rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

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Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired \|\| fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module Router_31( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [4:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_2_vc_sel_1_12; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_13; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_16; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_17; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_20; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_21; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_12; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_13; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_16; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_17; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_20; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_21; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_10; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_11; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_14; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_15; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_18; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_19; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_20; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_21; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_10; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_11; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_14; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_15; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_18; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_19; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_20; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_21; // @[Router.scala:136:32] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_12; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_13; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_16; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_17; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_21; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_12; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_13; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_16; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_17; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_21; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_10; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_11; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_14; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_15; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_18; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_19; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_21; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_10; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_11; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_14; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_15; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_18; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_19; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_21; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_10_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_11_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_14_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_15_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_18_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_19_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_21_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_12_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_13_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_16_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_17_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_21_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_12_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_13_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_16_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_17_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_21_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_10_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_11_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_14_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_15_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_18_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_19_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_12_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_13_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_16_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_17_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_12_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_13_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_16_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_17_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_2_to_37_io_credit_available_10; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_11; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_14; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_15; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_18; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_19; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_10_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_11_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_14_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_15_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_18_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_19_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_21_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_credit_available_12; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_credit_available_13; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_credit_available_16; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_credit_available_17; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_channel_status_12_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_channel_status_13_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_channel_status_16_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_channel_status_17_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_channel_status_21_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_credit_available_12; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_credit_available_13; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_credit_available_16; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_credit_available_17; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_channel_status_12_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_channel_status_13_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_channel_status_16_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_channel_status_17_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_channel_status_21_occupied; // @[Router.scala:122:13] wire [4:0] _input_unit_2_from_37_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_37_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_2_from_37_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_37_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_2_from_37_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_37_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_10; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_11; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_12; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_13; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_14; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_15; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_16; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_17; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_18; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_19; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_20; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_21; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_2_from_37_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_37_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_2_from_37_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_37_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_2_from_37_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_37_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_37_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_35_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_35_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_35_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_35_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_35_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_35_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_10; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_11; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_14; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_15; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_18; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_19; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_20; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_21; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_10; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_11; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_12; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_13; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_14; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_15; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_16; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_17; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_18; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_19; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_20; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_21; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_35_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_35_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_35_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_35_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_35_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_35_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_35_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_16_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_16_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_16_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_16_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_16_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_16_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_10; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_11; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_14; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_15; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_18; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_19; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_20; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_21; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_10; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_11; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_12; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_13; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_14; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_15; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_16; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_17; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_18; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_19; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_20; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_21; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_16_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_16_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_16_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_35_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_37_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels / // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /* Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) \| t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }	module NoCMonitor_16( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_\|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel \| (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens \| chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_\|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) \| 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_\|\|_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_\|\|_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }	module SwitchArbiter( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_3_ready, // @[SwitchAllocator.scala:18:14] input io_in_3_valid, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_4_ready, // @[SwitchAllocator.scala:18:14] input io_in_4_valid, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_5_ready, // @[SwitchAllocator.scala:18:14] input io_in_5_valid, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_6_ready, // @[SwitchAllocator.scala:18:14] input io_in_6_valid, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_7_ready, // @[SwitchAllocator.scala:18:14] input io_in_7_valid, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_tail, // @[SwitchAllocator.scala:18:14] input io_out_0_ready, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [7:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [7:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [7:0] unassigned = {io_in_7_valid, io_in_6_valid, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, 1'h0} & ~lock_0; // @[SwitchAllocator.scala:17:7, :24:38, :25:{23,52,54}] reg [7:0] mask; // @[SwitchAllocator.scala:27:21] wire [7:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [15:0] sel = _sel_T_1[0] ? 16'h1 : _sel_T_1[1] ? 16'h2 : _sel_T_1[2] ? 16'h4 : _sel_T_1[3] ? 16'h8 : _sel_T_1[4] ? 16'h10 : _sel_T_1[5] ? 16'h20 : _sel_T_1[6] ? 16'h40 : _sel_T_1[7] ? 16'h80 : unassigned[0] ? 16'h100 : unassigned[1] ? 16'h200 : unassigned[2] ? 16'h400 : unassigned[3] ? 16'h800 : unassigned[4] ? 16'h1000 : unassigned[5] ? 16'h2000 : unassigned[6] ? 16'h4000 : {unassigned[7], 15'h0}; // @[OneHot.scala:85:71] wire [6:0] _GEN = {io_in_7_valid, io_in_6_valid, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid}; // @[SwitchAllocator.scala:41:24] wire [7:0] chosen = (\|(_GEN & lock_0[7:1])) ? lock_0 : sel[7:0] \| sel[15:8]; // @[Mux.scala:50:70] wire [6:0] _io_out_0_valid_T = _GEN & chosen[7:1]; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire _GEN_0 = io_out_0_ready & (\|_io_out_0_valid_T); // @[Decoupled.scala:51:35] wire [6:0] _GEN_1 = chosen[6:0] \| chosen[7:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [5:0] _GEN_2 = _GEN_1[5:0] \| chosen[7:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [4:0] _GEN_3 = _GEN_2[4:0] \| chosen[7:3]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [3:0] _GEN_4 = _GEN_3[3:0] \| chosen[7:4]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [2:0] _GEN_5 = _GEN_4[2:0] \| chosen[7:5]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [1:0] _GEN_6 = _GEN_5[1:0] \| chosen[7:6]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 8'h0; // @[SwitchAllocator.scala:24:38] mask <= 8'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (_GEN_0) // @[Decoupled.scala:51:35] lock_0 <= chosen & {~io_in_7_bits_tail, ~io_in_6_bits_tail, ~io_in_5_bits_tail, ~io_in_4_bits_tail, ~io_in_3_bits_tail, ~io_in_2_bits_tail, ~io_in_1_bits_tail, 1'h1}; // @[SwitchAllocator.scala:17:7, :24:38, :39:21, :42:21, :53:{25,27}] mask <= _GEN_0 ? {chosen[7], _GEN_1[6], _GEN_2[5], _GEN_3[4], _GEN_4[3], _GEN_5[2], _GEN_6[1], _GEN_6[0] \| chosen[7]} : (&mask) ? 8'h0 : {mask[6:0], 1'h1}; // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_310( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_\|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel \| (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens \| chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_\|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) \| 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_\|\|_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_\|\|_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }	module SwitchAllocator_38( // @[SwitchAllocator.scala:64:7] input clock, // @[SwitchAllocator.scala:64:7] input reset, // @[SwitchAllocator.scala:64:7] output io_req_1_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_1_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_1_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_4_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_1_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_4_alloc, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_0_0 // @[SwitchAllocator.scala:74:14] ); wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_vc_sel_1_1; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_vc_sel_1_4; // @[SwitchAllocator.scala:83:45] wire [1:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:83:45] wire [1:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire arbs_0_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_0_1 \| io_req_0_0_bits_vc_sel_0_4); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_1_1 \| io_req_0_0_bits_vc_sel_1_4); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_0_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_0_1 \| io_req_1_0_bits_vc_sel_0_4); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_1_1 \| io_req_1_0_bits_vc_sel_1_4); // @[SwitchAllocator.scala:95:{37,65}] SwitchArbiter_223 arbs_0 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_0_io_in_0_ready), .io_in_0_valid (arbs_0_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_1_1 (io_req_0_0_bits_vc_sel_1_1), .io_in_0_bits_vc_sel_1_4 (io_req_0_0_bits_vc_sel_1_4), .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1), .io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_0_io_in_1_ready), .io_in_1_valid (arbs_0_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_1_1 (io_req_1_0_bits_vc_sel_1_1), .io_in_1_bits_vc_sel_1_4 (io_req_1_0_bits_vc_sel_1_4), .io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1), .io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_out_0_valid (_arbs_0_io_out_0_valid), .io_out_0_bits_vc_sel_1_1 (/* unused /), .io_out_0_bits_vc_sel_1_4 (/ unused /), .io_out_0_bits_vc_sel_0_1 (_arbs_0_io_out_0_bits_vc_sel_0_1), .io_out_0_bits_vc_sel_0_4 (_arbs_0_io_out_0_bits_vc_sel_0_4), .io_chosen_oh_0 (_arbs_0_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_223 arbs_1 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_1_1 (io_req_0_0_bits_vc_sel_1_1), .io_in_0_bits_vc_sel_1_4 (io_req_0_0_bits_vc_sel_1_4), .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1), .io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_1_io_in_1_ready), .io_in_1_valid (arbs_1_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_1_1 (io_req_1_0_bits_vc_sel_1_1), .io_in_1_bits_vc_sel_1_4 (io_req_1_0_bits_vc_sel_1_4), .io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1), .io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_out_0_valid (_arbs_1_io_out_0_valid), .io_out_0_bits_vc_sel_1_1 (_arbs_1_io_out_0_bits_vc_sel_1_1), .io_out_0_bits_vc_sel_1_4 (_arbs_1_io_out_0_bits_vc_sel_1_4), .io_out_0_bits_vc_sel_0_1 (/ unused /), .io_out_0_bits_vc_sel_0_4 (/ unused */), .io_chosen_oh_0 (_arbs_1_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] assign io_req_1_0_ready = _arbs_0_io_in_1_ready & arbs_0_io_in_1_valid \| _arbs_1_io_in_1_ready & arbs_1_io_in_1_valid; // @[Decoupled.scala:51:35] assign io_req_0_0_ready = _arbs_0_io_in_0_ready & arbs_0_io_in_0_valid \| _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid; // @[Decoupled.scala:51:35] assign io_credit_alloc_1_1_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_1_4_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_4; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_1_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_4_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_switch_sel_1_0_1_0 = arbs_1_io_in_1_valid & _arbs_1_io_chosen_oh_0[1] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_1_0 = arbs_0_io_in_1_valid & _arbs_0_io_chosen_oh_0[1] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_0_0 = arbs_0_io_in_0_valid & _arbs_0_io_chosen_oh_0[0] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_36( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34] wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34] wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34] wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_732; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [19:0] inflight; // @[Monitor.scala:614:27] reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [79:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [19:0] a_set; // @[Monitor.scala:626:34] wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [79:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_658 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [19:0] d_clr; // @[Monitor.scala:664:34] wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_673 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [19:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [79:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [79:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [19:0] inflight_1; // @[Monitor.scala:726:35] wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [19:0] d_clr_1; // @[Monitor.scala:774:34] wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_758 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_12( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [31:0] _GEN_0 = {27'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [31:0] _GEN_3 = {27'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [16:0] inflight_1; // @[Monitor.scala:726:35] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_47( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [8255:0] _inflight_opcodes_T_4 = 8256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [8255:0] _inflight_sizes_T_4 = 8256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [2063:0] _inflight_T_4 = 2064'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [8255:0] d_opcodes_clr_1 = 8256'h0; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1 = 8256'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2063:0] d_clr_1 = 2064'h0; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1 = 2064'h0; // @[Monitor.scala:775:34] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_659; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_592 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_4 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_605 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_297( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready \|\| !io.in.bits.head \|\| at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready \|\| !io.in.bits.head \|\| at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid \|\| !head) && (io.vcalloc_req.ready \|\| !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid \|\| !head) && (io.vcalloc_req.ready \|\| !head) && (vcalloc_q.io.enq.ready \|\| !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_\|\|_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }	module IngressUnit_2( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset // @[IngressUnit.scala:11:7] ); endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_245( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_262 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_223( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width2, width) >> 1) \| (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_\|\|_).init assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ \| _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_\|\|_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. / class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /* This tests that the lowest index is always selected across random single cycle transactions. / class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /* This tests that the highest index is always selected across random single cycle transactions. / class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module TLXbar_MasterXbar_SodorTile_i2_o1_a32d32s1k1z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_0_d_bits_sink; // @[Xbar.scala:216:19] wire in_1_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire requestBOI_0_0 = 1'h0; // @[Parameters.scala:46:9] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire in_0_a_bits_source = 1'h1; // @[Xbar.scala:159:18] wire _in_0_a_bits_source_T = 1'h1; // @[Xbar.scala:166:55] wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire requestBOI_0_1 = 1'h1; // @[Parameters.scala:46:9] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire portsAOI_filtered_0_bits_source = 1'h1; // @[Xbar.scala:352:24] wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _portsBIO_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsCOI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsCOI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_2_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_3_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _portsBIO_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_0_bits_mask = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_mask = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [9:0] beatsBO_decode = 10'h0; // @[Edges.scala:220:59] wire [9:0] beatsBO_0 = 10'h0; // @[Edges.scala:221:14] wire [9:0] beatsCI_decode = 10'h0; // @[Edges.scala:220:59] wire [9:0] beatsCI_0 = 10'h0; // @[Edges.scala:221:14] wire [9:0] beatsCI_decode_1 = 10'h0; // @[Edges.scala:220:59] wire [9:0] beatsCI_1 = 10'h0; // @[Edges.scala:221:14] wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [31:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18] wire _in_1_a_bits_source_T = anonIn_1_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire [3:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [31:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [31:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_ready = in_1_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [31:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_bits_source; // @[Xbar.scala:159:18] wire in_1_d_bits_source; // @[Xbar.scala:159:18] assign in_1_a_bits_source = _in_1_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire requestDOI_0_0 = out_0_d_bits_source; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_0_1 = ~out_0_d_bits_source; // @[Xbar.scala:216:19] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] beatsAI_decode = _beatsAI_decode_T_2[11:2]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [9:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:2]; // @[package.scala:243:46] wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [9:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] beatsDO_decode = _beatsDO_decode_T_2[11:2]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [9:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T \| _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] reg [9:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 10'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid \| portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_35( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_291 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_172( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_428 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RouteComputer.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.experimental.decode.{TruthTable, decoder} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import freechips.rocketchip.rocket.DecodeLogic import constellation.channel._ import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo} import constellation.noc.{HasNoCParams} class RouteComputerReq(implicit val p: Parameters) extends Bundle with HasNoCParams { val src_virt_id = UInt(virtualChannelBits.W) val flow = new FlowRoutingBundle } class RouteComputerResp( val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } class RouteComputer( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams with HasNoCParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new RouteComputerReq)) }) val resp = MixedVec(allInParams.map { u => Output(new RouteComputerResp(outParams, egressParams)) }) }) (io.req zip io.resp).zipWithIndex.map { case ((req, resp), i) => req.ready := true.B if (outParams.size == 0) { assert(!req.valid) resp.vc_sel := DontCare } else { def toUInt(t: (Int, FlowRoutingInfo)): UInt = { val l2 = (BigInt(t._1) << req.bits.flow.vnet_id .getWidth) \| t._2.vNetId val l3 = ( l2 << req.bits.flow.ingress_node .getWidth) \| t._2.ingressNode val l4 = ( l3 << req.bits.flow.ingress_node_id.getWidth) \| t._2.ingressNodeId val l5 = ( l4 << req.bits.flow.egress_node .getWidth) \| t._2.egressNode val l6 = ( l5 << req.bits.flow.egress_node_id .getWidth) \| t._2.egressNodeId l6.U(req.bits.getWidth.W) } val flow = req.bits.flow val table = allInParams(i).possibleFlows.toSeq.distinct.map { pI => allInParams(i).channelRoutingInfos.map { cI => var row: String = "b" (0 until nOutputs).foreach { o => (0 until outParams(o).nVirtualChannels).foreach { outVId => row = row + (if (routingRelation(cI, outParams(o).channelRoutingInfos(outVId), pI)) "1" else "0") } } ((cI.vc, pI), row) } }.flatten val addr = req.bits.asUInt val width = outParams.map(_.nVirtualChannels).reduce(_+_) val decoded = if (table.size > 0) { val truthTable = TruthTable( table.map { e => (BitPat(toUInt(e._1)), BitPat(e._2)) }, BitPat("b" + "?" * width) ) Reverse(decoder(addr, truthTable)) } else { 0.U(width.W) } var idx = 0 (0 until nAllOutputs).foreach { o => if (o < nOutputs) { (0 until outParams(o).nVirtualChannels).foreach { outVId => resp.vc_sel(o)(outVId) := decoded(idx) idx += 1 } } else { resp.vc_sel(o)(0) := false.B } } } } }	module RouteComputer_61( // @[RouteComputer.scala:29:7] input [3:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_3, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_8, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_9, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_8, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_9, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_9, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_9 // @[RouteComputer.scala:40:14] ); wire [12:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id[2:0], io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node[3]}; // @[pla.scala:78:21] wire [1:0] decoded_invInputs_1 = ~(io_req_1_bits_src_virt_id[2:1]); // @[pla.scala:78:21] wire [18:0] decoded_invInputs_2 = ~{io_req_2_bits_src_virt_id, io_req_2_bits_flow_vnet_id, io_req_2_bits_flow_ingress_node, io_req_2_bits_flow_ingress_node_id, io_req_2_bits_flow_egress_node, io_req_2_bits_flow_egress_node_id[2:1]}; // @[pla.scala:78:21] wire [15:0] _decoded_andMatrixOutputs_T_4 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[1], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_5 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[1], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_7 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_8 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_9 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_11 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_13 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[16], decoded_invInputs_2[17], io_req_2_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_14 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[16], decoded_invInputs_2[17], io_req_2_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_15 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[16], decoded_invInputs_2[17], io_req_2_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] assign io_resp_2_vc_sel_1_2 = \|{&{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[1], decoded_invInputs_2[18]}, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_13}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_3 = \|{&{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1], decoded_invInputs_2[18]}, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_13}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_4 = \|{&_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_13}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_5 = \|{&{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_13}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_6 = \|{&_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_13}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_7 = \|{&{decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}, &_decoded_andMatrixOutputs_T_13}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_8 = &_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] assign io_resp_2_vc_sel_1_9 = &{decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[0], decoded_invInputs_2[16], decoded_invInputs_2[17], io_req_2_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_2_vc_sel_0_2 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_3 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_4 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_5 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_6 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_7 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_8 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_9 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_9 = &{io_req_1_bits_src_virt_id[0], decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_0_vc_sel_2_9 = &{decoded_invInputs[0], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module MSHR_94( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire excluded_client = 1'h0; // @[MSHR.scala:279:28] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53] wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File RegField.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.regmapper import chisel3._ import chisel3.util.{DecoupledIO, ReadyValidIO} import org.json4s.JsonDSL._ import org.json4s.JsonAST.JValue import freechips.rocketchip.util.{SimpleRegIO} case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt)) object RegReadFn { // (ivalid: Bool, oready: Bool) => (iready: Bool, ovalid: Bool, data: UInt) // iready may combinationally depend on oready // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data is only inspected when ovalid && oready implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) = new RegReadFn(false, x) implicit def apply(x: RegisterReadIO[UInt]): RegReadFn = RegReadFn((ivalid, oready) => { x.request.valid := ivalid x.response.ready := oready (x.request.ready, x.response.valid, x.response.bits) }) // (ready: Bool) => (valid: Bool, data: UInt) // valid must not combinationally depend on ready // effects must become visible on the cycle after valid && ready implicit def apply(x: Bool => (Bool, UInt)) = new RegReadFn(true, { case (_, oready) => val (ovalid, data) = x(oready) (true.B, ovalid, data) }) // read from a ReadyValidIO (only safe if there is a consistent source of data) implicit def apply(x: ReadyValidIO[UInt]):RegReadFn = RegReadFn(ready => { x.ready := ready; (x.valid, x.bits) }) // read from a register implicit def apply(x: UInt):RegReadFn = RegReadFn(ready => (true.B, x)) // noop implicit def apply(x: Unit):RegReadFn = RegReadFn(0.U) } case class RegWriteFn private(combinational: Boolean, fn: (Bool, Bool, UInt) => (Bool, Bool)) object RegWriteFn { // (ivalid: Bool, oready: Bool, data: UInt) => (iready: Bool, ovalid: Bool) // iready may combinationally depend on both oready and data // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data should only be used for an effect when ivalid && iready implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) = new RegWriteFn(false, x) implicit def apply(x: RegisterWriteIO[UInt]): RegWriteFn = RegWriteFn((ivalid, oready, data) => { x.request.valid := ivalid x.request.bits := data x.response.ready := oready (x.request.ready, x.response.valid) }) // (valid: Bool, data: UInt) => (ready: Bool) // ready may combinationally depend on data (but not valid) // effects must become visible on the cycle after valid && ready implicit def apply(x: (Bool, UInt) => Bool) = // combinational => data valid on oready new RegWriteFn(true, { case (_, oready, data) => (true.B, x(oready, data)) }) // write to a DecoupledIO (only safe if there is a consistent sink draining data) // NOTE: this is not an IrrevocableIO (even on TL2) because other fields could cause a lowered valid implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready }) // updates a register (or adds a mux to a wire) implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; true.B }) // noop implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { true.B }) } case class RegField(width: Int, read: RegReadFn, write: RegWriteFn, desc: Option[RegFieldDesc]) { require (width >= 0, s"RegField width must be >= 0, not $width") def pipelined = !read.combinational \|\| !write.combinational def readOnly = this.copy(write = (), desc = this.desc.map(_.copy(access = RegFieldAccessType.R))) def toJson(byteOffset: Int, bitOffset: Int): JValue = { ( ("byteOffset" -> s"0x${byteOffset.toHexString}") ~ ("bitOffset" -> bitOffset) ~ ("bitWidth" -> width) ~ ("name" -> desc.map(_.name)) ~ ("description" -> desc.map{ d=> if (d.desc == "") None else Some(d.desc)}) ~ ("resetValue" -> desc.map{_.reset}) ~ ("group" -> desc.map{_.group}) ~ ("groupDesc" -> desc.map{_.groupDesc}) ~ ("accessType" -> desc.map {d => d.access.toString}) ~ ("writeType" -> desc.map {d => d.wrType.map(_.toString)}) ~ ("readAction" -> desc.map {d => d.rdAction.map(_.toString)}) ~ ("volatile" -> desc.map {d => if (d.volatile) Some(true) else None}) ~ ("enumerations" -> desc.map {d => Option(d.enumerations.map { case (key, (name, edesc)) => (("value" -> key) ~ ("name" -> name) ~ ("description" -> edesc)) }).filter(_.nonEmpty)}) ) } } object RegField { // Byte address => sequence of bitfields, lowest index => lowest address type Map = (Int, Seq[RegField]) def apply(n: Int) : RegField = apply(n, (), (), Some(RegFieldDesc.reserved)) def apply(n: Int, desc: RegFieldDesc) : RegField = apply(n, (), (), Some(desc)) def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None) def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc)) def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw, None) def apply(n: Int, rw: UInt, desc: RegFieldDesc) : RegField = apply(n, rw, rw, Some(desc)) def r(n: Int, r: RegReadFn) : RegField = apply(n, r, (), None) def r(n: Int, r: RegReadFn, desc: RegFieldDesc) : RegField = apply(n, r, (), Some(desc.copy(access = RegFieldAccessType.R))) def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w, None) def w(n: Int, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, (), w, Some(desc.copy(access = RegFieldAccessType.W))) // This RegField allows 'set' to set bits in 'reg'. // and to clear bits when the bus writes bits of value 1. // Setting takes priority over clearing. def w1ToClear(n: Int, reg: UInt, set: UInt, desc: Option[RegFieldDesc] = None): RegField = RegField(n, reg, RegWriteFn((valid, data) => { reg := (~((~reg) \| Mux(valid, data, 0.U))) \| set; true.B }), desc.map{_.copy(access = RegFieldAccessType.RW, wrType=Some(RegFieldWrType.ONE_TO_CLEAR), volatile = true)}) // This RegField wraps an explicit register // (e.g. Black-Boxed Register) to create a R/W register. def rwReg(n: Int, bb: SimpleRegIO, desc: Option[RegFieldDesc] = None) : RegField = RegField(n, bb.q, RegWriteFn((valid, data) => { bb.en := valid bb.d := data true.B }), desc) // Create byte-sized read-write RegFields out of a large UInt register. // It is updated when any of the (implemented) bytes are written, the non-written // bytes are just copied over from their current value. // Because the RegField are all byte-sized, this is also suitable when a register is larger // than the intended bus width of the device (atomic updates are impossible). def bytes(reg: UInt, numBytes: Int, desc: Option[RegFieldDesc]): Seq[RegField] = { require(reg.getWidth 8 >= numBytes, "Can't break a ${reg.getWidth}-bit-wide register into only ${numBytes} bytes.") val numFullBytes = reg.getWidth/8 val numPartialBytes = if ((reg.getWidth % 8) > 0) 1 else 0 val numPadBytes = numBytes - numFullBytes - numPartialBytes val pad = reg \| 0.U((8numBytes).W) val oldBytes = VecInit.tabulate(numBytes) { i => pad(8(i+1)-1, 8i) } val newBytes = WireDefault(oldBytes) val valids = WireDefault(VecInit.fill(numBytes) { false.B }) when (valids.reduce(_ \|\| _)) { reg := newBytes.asUInt } def wrFn(i: Int): RegWriteFn = RegWriteFn((valid, data) => { valids(i) := valid when (valid) {newBytes(i) := data} true.B }) val fullBytes = Seq.tabulate(numFullBytes) { i => val newDesc = desc.map {d => d.copy(name = d.name + s"_$i")} RegField(8, oldBytes(i), wrFn(i), newDesc)} val partialBytes = if (numPartialBytes > 0) { val newDesc = desc.map {d => d.copy(name = d.name + s"_$numFullBytes")} Seq(RegField(reg.getWidth % 8, oldBytes(numFullBytes), wrFn(numFullBytes), newDesc), RegField(8 - (reg.getWidth % 8))) } else Nil val padBytes = Seq.fill(numPadBytes){RegField(8)} fullBytes ++ partialBytes ++ padBytes } def bytes(reg: UInt, desc: Option[RegFieldDesc]): Seq[RegField] = { val width = reg.getWidth require (width % 8 == 0, s"RegField.bytes must be called on byte-sized reg, not ${width} bits") bytes(reg, width/8, desc) } def bytes(reg: UInt, numBytes: Int): Seq[RegField] = bytes(reg, numBytes, None) def bytes(reg: UInt): Seq[RegField] = bytes(reg, None) } trait HasRegMap { def regmap(mapping: RegField.Map): Unit val interrupts: Vec[Bool] } // See Example.scala for an example of how to use regmap File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File CLINT.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Resource, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.Annotated object CLINTConsts { def msipOffset(hart: Int) = hart * msipBytes def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes def timeOffset = 0xbff8 def msipBytes = 4 def timecmpBytes = 8 def size = 0x10000 def timeWidth = 64 def ipiWidth = 32 def ints = 2 } case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0) { def address = AddressSet(baseAddress, CLINTConsts.size-1) } case object CLINTKey extends Field[Option[CLINTParams]](None) case class CLINTAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object CLINTAttachKey extends Field(CLINTAttachParams()) class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { import CLINTConsts._ // clint0 => at most 4095 devices val device = new SimpleDevice("clint", Seq("riscv,clint0")) { override val alwaysExtended = true } val node: TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes) val intnode : IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them") val io = IO(new Bundle { val rtcTick = Input(Bool()) }) val time = RegInit(0.U(timeWidth.W)) when (io.rtcTick) { time := time + 1.U } val nTiles = intnode.out.size val timecmp = Seq.fill(nTiles) { Reg(UInt(timeWidth.W)) } val ipi = Seq.fill(nTiles) { RegInit(0.U(1.W)) } val (intnode_out, _) = intnode.out.unzip intnode_out.zipWithIndex.foreach { case (int, i) => int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip } /* 0000 msip hart 0 * 0004 msip hart 1 * 4000 mtimecmp hart 0 lo * 4004 mtimecmp hart 0 hi * 4008 mtimecmp hart 1 lo * 400c mtimecmp hart 1 hi * bff8 mtime lo * bffc mtime hi / node.regmap( 0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) => RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }), timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"), RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))}, timeOffset -> RegFieldGroup("mtime", Some("Timer Register"), RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true)))) ) } } /* Trait that will connect a CLINT to a subsystem */ trait CanHavePeripheryCLINT { this: BaseSubsystem => val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params => val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere) val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain") val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) } clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus, Some("CLINT")) := _ } } val clintTick = clintDomainWrapper { InModuleBody { val tick = IO(Input(Bool())) clint.module.io.rtcTick := tick tick }} (clint, clintDomainWrapper, clintTick) }.unzip3 }	module CLINT( // @[CLINT.scala:65:9] input clock, // @[CLINT.scala:65:9] input reset, // @[CLINT.scala:65:9] output auto_int_out_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_rtcTick // @[CLINT.scala:69:16] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [12:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CLINT.scala:65:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CLINT.scala:65:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CLINT.scala:65:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CLINT.scala:65:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CLINT.scala:65:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CLINT.scala:65:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CLINT.scala:65:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CLINT.scala:65:9] wire io_rtcTick_0 = io_rtcTick; // @[CLINT.scala:65:9] wire [12:0] out_maskMatch = 13'h7FF; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_denied = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_corrupt = 1'h0; // @[CLINT.scala:65:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_7 = 1'h0; // @[RegField.scala:153:53] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire intnodeOut_1; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CLINT.scala:65:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CLINT.scala:65:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CLINT.scala:65:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CLINT.scala:65:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CLINT.scala:65:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CLINT.scala:65:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CLINT.scala:65:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_0_0; // @[CLINT.scala:65:9] wire auto_int_out_1_0; // @[CLINT.scala:65:9] wire auto_in_a_ready_0; // @[CLINT.scala:65:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] wire [1:0] auto_in_d_bits_size_0; // @[CLINT.scala:65:9] wire [10:0] auto_in_d_bits_source_0; // @[CLINT.scala:65:9] wire [63:0] auto_in_d_bits_data_0; // @[CLINT.scala:65:9] wire auto_in_d_valid_0; // @[CLINT.scala:65:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CLINT.scala:65:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CLINT.scala:65:9] wire [10:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CLINT.scala:65:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CLINT.scala:65:9] wire _intnodeOut_0_T; // @[CLINT.scala:82:37] assign auto_int_out_0_0 = intnodeOut_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T; // @[CLINT.scala:83:43] assign auto_int_out_1_0 = intnodeOut_1; // @[CLINT.scala:65:9] reg [63:0] time_0; // @[CLINT.scala:73:23] wire [63:0] pad_1 = time_0; // @[RegField.scala:150:19] wire [64:0] _time_T = {1'h0, time_0} + 65'h1; // @[CLINT.scala:73:23, :74:38] wire [63:0] _time_T_1 = _time_T[63:0]; // @[CLINT.scala:74:38] reg [63:0] timecmp_0; // @[CLINT.scala:77:41] wire [63:0] pad = timecmp_0; // @[RegField.scala:150:19] reg ipi_0; // @[CLINT.scala:78:41] assign _intnodeOut_0_T = ipi_0; // @[CLINT.scala:78:41, :82:37] wire _out_T_15 = ipi_0; // @[RegisterRouter.scala:87:24] assign intnodeOut_0 = _intnodeOut_0_T; // @[CLINT.scala:82:37] assign _intnodeOut_1_T = time_0 >= timecmp_0; // @[CLINT.scala:73:23, :77:41, :83:43] assign intnodeOut_1 = _intnodeOut_1_T; // @[CLINT.scala:83:43] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_123 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] timecmp_0_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_lo = {timecmp_0_lo_hi, timecmp_0_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_0_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_hi = {timecmp_0_hi_hi, timecmp_0_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_0_T = {timecmp_0_hi, timecmp_0_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_8 = pad_1[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_0 = _oldBytes_T_8; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_9 = pad_1[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_1 = _oldBytes_T_9; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_10 = pad_1[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_2 = _oldBytes_T_10; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_11 = pad_1[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_3 = _oldBytes_T_11; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_12 = pad_1[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_4 = _oldBytes_T_12; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_13 = pad_1[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_5 = _oldBytes_T_13; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_14 = pad_1[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_6 = _oldBytes_T_14; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_15 = pad_1[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_7 = _oldBytes_T_15; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_35 = oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_1_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1_1; // @[RegField.scala:152:31] wire [7:0] newBytes_1_2; // @[RegField.scala:152:31] wire [7:0] newBytes_1_3; // @[RegField.scala:152:31] wire [7:0] newBytes_1_4; // @[RegField.scala:152:31] wire [7:0] newBytes_1_5; // @[RegField.scala:152:31] wire [7:0] newBytes_1_6; // @[RegField.scala:152:31] wire [7:0] newBytes_1_7; // @[RegField.scala:152:31] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire valids_1_0; // @[RegField.scala:153:29] wire valids_1_1; // @[RegField.scala:153:29] wire valids_1_2; // @[RegField.scala:153:29] wire valids_1_3; // @[RegField.scala:153:29] wire valids_1_4; // @[RegField.scala:153:29] wire valids_1_5; // @[RegField.scala:153:29] wire valids_1_6; // @[RegField.scala:153:29] wire valids_1_7; // @[RegField.scala:153:29] wire [15:0] time_lo_lo = {newBytes_1_1, newBytes_1_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_lo_hi = {newBytes_1_3, newBytes_1_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_lo = {time_lo_hi, time_lo_lo}; // @[RegField.scala:154:52] wire [15:0] time_hi_lo = {newBytes_1_5, newBytes_1_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_hi_hi = {newBytes_1_7, newBytes_1_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_hi = {time_hi_hi, time_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _time_T_2 = {time_hi, time_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = nodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[12:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [12:0] _GEN = out_front_bits_index & 13'h7FF; // @[RegisterRouter.scala:87:24] wire [12:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [12:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_T_2 = out_findex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_T_3 = out_bindex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_6 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = _out_T_15; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = _out_T_16; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_17 = out_front_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {1'h0, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_24 = {30'h0, out_prepend}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_25 = _out_T_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_1_0 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_26 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_114 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_1_0 = out_f_woready_2 ? _out_T_26 : oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_1_1 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_125 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1_1 = out_f_woready_3 ? _out_T_37 : oldBytes_1_1; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1 = {oldBytes_1_1, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_46 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_47 = _out_T_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_2 = _out_T_47; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_1_2 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_48 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_136 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_1_2 = out_f_woready_4 ? _out_T_48 : oldBytes_1_2; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_2 = {oldBytes_1_2, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_57 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_58 = _out_T_57; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_3 = _out_T_58; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_1_3 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_59 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_147 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_1_3 = out_f_woready_5 ? _out_T_59 : oldBytes_1_3; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_3 = {oldBytes_1_3, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_4 = _out_T_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = \|_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = \|_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_1_4 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_70 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_158 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_1_4 = out_f_woready_6 ? _out_T_70 : oldBytes_1_4; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_4 = {oldBytes_1_4, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_79 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_80 = _out_T_79; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_5 = _out_T_80; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = \|_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = \|_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_84 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_1_5 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_81 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_169 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_1_5 = out_f_woready_7 ? _out_T_81 : oldBytes_1_5; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_5 = {oldBytes_1_5, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_90 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_6 = _out_T_91; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign valids_1_6 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_92 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_180 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_1_6 = out_f_woready_8 ? _out_T_92 : oldBytes_1_6; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_6 = {oldBytes_1_6, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_101 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_7 = _out_T_102; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = \|_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = \|_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_106 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign valids_1_7 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_103 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_191 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_1_7 = out_f_woready_9 ? _out_T_103 : oldBytes_1_7; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_110 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_7 = {oldBytes_1_7, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_112 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_113 = _out_T_112; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_2 = _out_T_113; // @[MuxLiteral.scala:49:48] wire out_rimask_10 = \|_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = \|_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready_10 ? _out_T_114 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_121 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_124 = _out_T_123; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_8 = _out_T_124; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = \|_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = \|_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_11 ? _out_T_125 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_132 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_8 = {oldBytes_1, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_134 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_135 = _out_T_134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_9 = _out_T_135; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = \|_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = \|_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_12 ? _out_T_136 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_9 = {oldBytes_2, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_145 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_146 = _out_T_145; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_10 = _out_T_146; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = \|_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = \|_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_151 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_13 ? _out_T_147 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_155 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_10 = {oldBytes_3, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_156 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_157 = _out_T_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_11 = _out_T_157; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = \|_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = \|_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_162 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_14 ? _out_T_158 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_166 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_11 = {oldBytes_4, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_167 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_168 = _out_T_167; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_12 = _out_T_168; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = \|_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = \|_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_172 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_173 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_15 ? _out_T_169 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_176 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_177 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_12 = {oldBytes_5, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_178 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_179 = _out_T_178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_13 = _out_T_179; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = \|_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = \|_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_183 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_184 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_16 ? _out_T_180 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_187 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_188 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_13 = {oldBytes_6, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_189 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_190 = _out_T_189; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_14 = _out_T_190; // @[RegisterRouter.scala:87:24] wire out_rimask_17 = \|_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = \|_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_194 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_195 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_17 ? _out_T_191 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_198 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_199 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_14 = {oldBytes_7, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_200 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_201 = _out_T_200; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = _out_T_201; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{1'h1}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_0 = {32'h0, _out_T_25}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{64'h0}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[CLINT.scala:65:9] if (reset) begin // @[CLINT.scala:65:9] time_0 <= 64'h0; // @[CLINT.scala:73:23] ipi_0 <= 1'h0; // @[CLINT.scala:78:41] end else begin // @[CLINT.scala:65:9] if (valids_1_0 \| valids_1_1 \| valids_1_2 \| valids_1_3 \| valids_1_4 \| valids_1_5 \| valids_1_6 \| valids_1_7) // @[RegField.scala:153:29, :154:27] time_0 <= _time_T_2; // @[RegField.scala:154:52] else if (io_rtcTick_0) // @[CLINT.scala:65:9] time_0 <= _time_T_1; // @[CLINT.scala:73:23, :74:38] if (out_f_woready) // @[RegisterRouter.scala:87:24] ipi_0 <= _out_T_6; // @[RegisterRouter.scala:87:24] end if (valids_0 \| valids_1 \| valids_2 \| valids_3 \| valids_4 \| valids_5 \| valids_6 \| valids_7) // @[RegField.scala:153:29, :154:27] timecmp_0 <= _timecmp_0_T; // @[RegField.scala:154:52] always @(posedge) TLMonitor_46 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_int_out_0 = auto_int_out_0_0; // @[CLINT.scala:65:9] assign auto_int_out_1 = auto_int_out_1_0; // @[CLINT.scala:65:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[CLINT.scala:65:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[CLINT.scala:65:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_58( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_82 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid \|\| io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }	module PriorityQueueStage_123( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tilelink.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLMasterToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2)) a.io.protocol <> io.tilelink.a io.tilelink.b <> b.io.protocol c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol e.io.protocol <> io.tilelink.e io.flits.a <> a.io.flit b.io.flit <> io.flits.b io.flits.c <> c.io.flit d.io.flit <> io.flits.d io.flits.e <> e.io.flit } class TLMasterACDToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) a.io.protocol <> io.tilelink.a c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol io.flits.a <> a.io.flit io.flits.c <> c.io.flit d.io.flit <> io.flits.d } class TLMasterBEToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0)) io.tilelink.b <> b.io.protocol e.io.protocol <> io.tilelink.e b.io.flit <> io.flits.b io.flits.e <> e.io.flit } class TLSlaveToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val b = Decoupled(new IngressFlit(flitWidth)) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) io.tilelink.a <> a.io.protocol b.io.protocol <> io.tilelink.b io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d io.tilelink.e <> e.io.protocol a.io.flit <> io.flits.a io.flits.b <> b.io.flit c.io.flit <> io.flits.c io.flits.d <> d.io.flit e.io.flit <> io.flits.e } class TLSlaveACDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart)) io.tilelink.a <> a.io.protocol io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d a.io.flit <> io.flits.a c.io.flit <> io.flits.c io.flits.d <> d.io.flit } class TLSlaveBEToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val b = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) b.io.protocol <> io.tilelink.b io.tilelink.e <> e.io.protocol io.flits.b <> b.io.flit e.io.flit <> io.flits.e } class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle { val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) }) val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) }) } trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper { def edgesIn: Seq[TLEdge] def edgesOut: Seq[TLEdge] def edgeInNodes: Seq[Int] def edgeOutNodes: Seq[Int] require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size) def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle)) def genBundle = new TLBundle(wideBundle) def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut) } object TLConnect { def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = { l.valid := r.valid r.ready := l.ready l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll } } // BEGIN: TileLinkProtocolParams case class TileLinkABCDEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int] ) extends TileLinkProtocolParams { // END: TileLinkProtocolParams val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten val nVirtualNetworks = 5 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A (if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B (if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D (if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { edgesIn.zipWithIndex.map { case (e,i) => val nif_master = Module(new TLMasterToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 3 + edgesIn.size * 2 + egressOffset, minPayloadWidth )) nif_master.io.tilelink := DontCare nif_master.io.tilelink.a.valid := false.B nif_master.io.tilelink.c.valid := false.B nif_master.io.tilelink.e.valid := false.B TLConnect(nif_master.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master.io.tilelink.b) TLConnect(nif_master.io.tilelink.c, protocol.in(i).c) TLConnect(nif_master.io.tilelink.e, protocol.in(i).e) } ingresses(i * 3 + 0).flit <> nif_master.io.flits.a ingresses(i * 3 + 1).flit <> nif_master.io.flits.c ingresses(i * 3 + 2).flit <> nif_master.io.flits.e nif_master.io.flits.b <> egresses(i * 2 + 0).flit nif_master.io.flits.d <> egresses(i * 2 + 1).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave = Module(new TLSlaveToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 2 + egressOffset, minPayloadWidth )) nif_slave.io.tilelink := DontCare nif_slave.io.tilelink.b.valid := false.B nif_slave.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a) TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b) TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c) TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e) } ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit } } } } } case class TileLinkACDProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val nVirtualNetworks = 3 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A (if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_acd = Module(new TLMasterACDToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 2 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_acd.io.tilelink := DontCare nif_master_acd.io.tilelink.a.valid := false.B nif_master_acd.io.tilelink.c.valid := false.B nif_master_acd.io.tilelink.e.valid := false.B TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c) } ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_acd = Module(new TLSlaveACDToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_acd.io.tilelink := DontCare nif_slave_acd.io.tilelink.b.valid := false.B nif_slave_acd.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a) TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c) } ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit } }} } } case class TileLinkBEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val nVirtualNetworks = 2 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B (if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_be = Module(new TLMasterBEToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 1 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_be.io.tilelink := DontCare nif_master_be.io.tilelink.a.valid := false.B nif_master_be.io.tilelink.c.valid := false.B nif_master_be.io.tilelink.e.valid := false.B if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b) TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e) } ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_be = Module(new TLSlaveBEToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_be.io.tilelink := DontCare nif_slave_be.io.tilelink.b.valid := false.B nif_slave_be.io.tilelink.d.valid := false.B if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e) TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b) } ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit } }} } } abstract class TLNoCLike(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") // TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers port.managers map { manager => manager.v1copy(fifoId = None) } } ) } ) } abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) { val edgesIn: Seq[TLEdge] val edgesOut: Seq[TLEdge] val nodeMapping: DiplomaticNetworkNodeMapping val nocName: String lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name))) lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name))) lazy val edgeInNodes = nodeMapping.getNodesIn(inNames) lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames) def printNodeMappings() { println(s"Constellation: TLNoC $nocName inwards mapping:") for ((n, i) <- inNames zip edgeInNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } println(s"Constellation: TLNoC $nocName outwards mapping:") for ((n, i) <- outNames zip edgeOutNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } } } trait TLNoCParams // Instantiates a private TLNoC. Replaces the TLXbar // BEGIN: TLNoCParams case class SimpleTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, nocParams: NoCParams = NoCParams(), ) extends TLNoCParams class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { // END: TLNoCParams override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val noc = Module(new ProtocolNoC(ProtocolNoCParams( params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC), Seq(protocolParams), inlineNoC = inlineNoC ))) noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } } case class SplitACDxBETLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, acdNoCParams: NoCParams = NoCParams(), beNoCParams: NoCParams = NoCParams(), beDivision: Int = 2 ) extends TLNoCParams class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val acdProtocolParams = TileLinkACDProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val beProtocolParams = TileLinkBEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC), Seq(acdProtocolParams), inlineNoC = inlineNoC ))) val be_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC), Seq(beProtocolParams), widthDivision = params.beDivision, inlineNoC = inlineNoC ))) acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } }} be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.b <> r.b l.e <> r.e } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.b <> r.b l.e <> r.e } }} } } case class GlobalTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping ) extends TLNoCParams // Maps this interconnect onto a global NoC class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike { lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) printNodeMappings() val io_global = IO(Flipped(protocolParams.genIO())) io_global match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } }	module TLSlaveACDToNoC_4( // @[Tilelink.scala:161:7] input clock, // @[Tilelink.scala:161:7] input reset, // @[Tilelink.scala:161:7] input io_tilelink_a_ready, // @[Tilelink.scala:168:14] output io_tilelink_a_valid, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:168:14] output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:168:14] output [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:168:14] output [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:168:14] output [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:168:14] output [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:168:14] output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:168:14] input io_tilelink_c_ready, // @[Tilelink.scala:168:14] output io_tilelink_c_valid, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:168:14] output [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:168:14] output [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:168:14] output [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:168:14] output [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:168:14] output io_tilelink_c_bits_corrupt, // @[Tilelink.scala:168:14] output io_tilelink_d_ready, // @[Tilelink.scala:168:14] input io_tilelink_d_valid, // @[Tilelink.scala:168:14] input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:168:14] input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:168:14] input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:168:14] input [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:168:14] input [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:168:14] input io_tilelink_d_bits_denied, // @[Tilelink.scala:168:14] input [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:168:14] input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:168:14] output io_flits_a_ready, // @[Tilelink.scala:168:14] input io_flits_a_valid, // @[Tilelink.scala:168:14] input io_flits_a_bits_head, // @[Tilelink.scala:168:14] input io_flits_a_bits_tail, // @[Tilelink.scala:168:14] input [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:168:14] output io_flits_c_ready, // @[Tilelink.scala:168:14] input io_flits_c_valid, // @[Tilelink.scala:168:14] input io_flits_c_bits_head, // @[Tilelink.scala:168:14] input io_flits_c_bits_tail, // @[Tilelink.scala:168:14] input [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:168:14] input io_flits_d_ready, // @[Tilelink.scala:168:14] output io_flits_d_valid, // @[Tilelink.scala:168:14] output io_flits_d_bits_head, // @[Tilelink.scala:168:14] output io_flits_d_bits_tail, // @[Tilelink.scala:168:14] output [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:168:14] output [3:0] io_flits_d_bits_egress_id // @[Tilelink.scala:168:14] ); wire [64:0] _d_io_flit_bits_payload; // @[Tilelink.scala:179:17] TLAFromNoC a ( // @[Tilelink.scala:177:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload) ); // @[Tilelink.scala:177:17] TLCFromNoC_1 c ( // @[Tilelink.scala:178:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (io_flits_c_bits_payload[64:0]) // @[Tilelink.scala:185:14] ); // @[Tilelink.scala:178:17] TLDToNoC_4 d ( // @[Tilelink.scala:179:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (_d_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_d_bits_egress_id) ); // @[Tilelink.scala:179:17] assign io_flits_d_bits_payload = {8'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:161:7, :179:17, :186:14] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //**************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander / * Mixin for issue queue types / trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /* * Mixin for scalar operation constants / trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //********************************* // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //******************************** // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } / * Mixin for RISCV constants / trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /* * Mixin for exception cause constants / trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //*************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ / * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot / class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /* * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports / class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) \|\| (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid \|\| io.clear \|\| io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br \|\| slot_uop.is_jal \|\| slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 \|\| p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) \|\| (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned \|\| p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }	module IssueSlot_3( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [5:0] io_spec_ld_wakeup_0_bits = 6'h0; // @[issue-slot.scala:69:7] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN \| ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN \| ~_T_12 \| p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to the following Chisel files. File arbiter.scala: //************************************************************************** // Arbiter for Princeton Architectures //-------------------------------------------------------------------------- // // Arbitrates instruction and data accesses to a single port memory. package sodor.stage3 import chisel3._ import chisel3.util._ import sodor.common._ // arbitrates memory access class SodorMemArbiter(implicit val conf: SodorCoreParams) extends Module { val io = IO(new Bundle { // TODO I need to come up with better names... this is too confusing // from the point of view of the other modules val imem = Flipped(new MemPortIo(conf.xprlen)) // instruction fetch val dmem = Flipped(new MemPortIo(conf.xprlen)) // load/store val mem = new MemPortIo(conf.xprlen) // the single-ported memory }) val d_resp = RegInit(false.B) // hook up requests // d_resp ensures that data req gets access to bus only // for one cycle // alternate between data and instr to avoid starvation when (d_resp) { // Last request is a data request - do not allow data request this cycle io.dmem.req.ready := false.B io.imem.req.ready := io.mem.req.ready // We only clear the d_resp flag when the next request fired since it also indicates the allowed type of the next request when (io.mem.req.fire) { d_resp := false.B } } .otherwise { // Last request is not a data request - if this cycle has a new data request, dispatch it io.dmem.req.ready := io.mem.req.ready io.imem.req.ready := io.mem.req.ready && !io.dmem.req.valid when (io.dmem.req.fire) { d_resp := true.B } } // SWITCH BET DATA AND INST REQ FOR SINGLE PORT when (io.dmem.req.fire) { io.mem.req.valid := io.dmem.req.valid io.mem.req.bits.addr := io.dmem.req.bits.addr io.mem.req.bits.fcn := io.dmem.req.bits.fcn io.mem.req.bits.typ := io.dmem.req.bits.typ } .otherwise { io.mem.req.valid := io.imem.req.valid io.mem.req.bits.addr := io.imem.req.bits.addr io.mem.req.bits.fcn := io.imem.req.bits.fcn io.mem.req.bits.typ := io.imem.req.bits.typ } // Control valid signal when (d_resp) { io.imem.resp.valid := false.B io.dmem.resp.valid := io.mem.resp.valid } .otherwise { io.imem.resp.valid := io.mem.resp.valid io.dmem.resp.valid := false.B } // No need to switch data since instruction port doesn't write io.mem.req.bits.data := io.dmem.req.bits.data // Simply connect response data to both ports since we only have one inflight request // the validity of the data is controlled above io.imem.resp.bits.data := io.mem.resp.bits.data io.dmem.resp.bits.data := io.mem.resp.bits.data }	module SodorMemArbiter( // @[arbiter.scala:15:7] input clock, // @[arbiter.scala:15:7] input reset, // @[arbiter.scala:15:7] output io_imem_req_ready, // @[arbiter.scala:17:14] input io_imem_req_valid, // @[arbiter.scala:17:14] input [31:0] io_imem_req_bits_addr, // @[arbiter.scala:17:14] output io_imem_resp_valid, // @[arbiter.scala:17:14] output [31:0] io_imem_resp_bits_data, // @[arbiter.scala:17:14] output io_dmem_req_ready, // @[arbiter.scala:17:14] input io_dmem_req_valid, // @[arbiter.scala:17:14] input [31:0] io_dmem_req_bits_addr, // @[arbiter.scala:17:14] input [31:0] io_dmem_req_bits_data, // @[arbiter.scala:17:14] input io_dmem_req_bits_fcn, // @[arbiter.scala:17:14] input [2:0] io_dmem_req_bits_typ, // @[arbiter.scala:17:14] output io_dmem_resp_valid, // @[arbiter.scala:17:14] output [31:0] io_dmem_resp_bits_data, // @[arbiter.scala:17:14] output io_mem_req_valid, // @[arbiter.scala:17:14] output [31:0] io_mem_req_bits_addr, // @[arbiter.scala:17:14] output [31:0] io_mem_req_bits_data, // @[arbiter.scala:17:14] output io_mem_req_bits_fcn, // @[arbiter.scala:17:14] output [2:0] io_mem_req_bits_typ, // @[arbiter.scala:17:14] input io_mem_resp_valid, // @[arbiter.scala:17:14] input [31:0] io_mem_resp_bits_data // @[arbiter.scala:17:14] ); wire io_imem_req_valid_0 = io_imem_req_valid; // @[arbiter.scala:15:7] wire [31:0] io_imem_req_bits_addr_0 = io_imem_req_bits_addr; // @[arbiter.scala:15:7] wire io_dmem_req_valid_0 = io_dmem_req_valid; // @[arbiter.scala:15:7] wire [31:0] io_dmem_req_bits_addr_0 = io_dmem_req_bits_addr; // @[arbiter.scala:15:7] wire [31:0] io_dmem_req_bits_data_0 = io_dmem_req_bits_data; // @[arbiter.scala:15:7] wire io_dmem_req_bits_fcn_0 = io_dmem_req_bits_fcn; // @[arbiter.scala:15:7] wire [2:0] io_dmem_req_bits_typ_0 = io_dmem_req_bits_typ; // @[arbiter.scala:15:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[arbiter.scala:15:7] wire [31:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[arbiter.scala:15:7] wire io_mem_req_ready = 1'h1; // @[arbiter.scala:15:7] wire [2:0] io_imem_req_bits_typ = 3'h7; // @[arbiter.scala:15:7, :17:14] wire io_imem_req_bits_fcn = 1'h0; // @[arbiter.scala:15:7] wire [31:0] io_imem_req_bits_data = 32'h0; // @[arbiter.scala:15:7, :17:14] wire [31:0] io_mem_req_bits_data_0 = io_dmem_req_bits_data_0; // @[arbiter.scala:15:7] wire [31:0] io_imem_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[arbiter.scala:15:7] wire [31:0] io_dmem_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[arbiter.scala:15:7] wire io_imem_req_ready_0; // @[arbiter.scala:15:7] wire io_imem_resp_valid_0; // @[arbiter.scala:15:7] wire io_dmem_req_ready_0; // @[arbiter.scala:15:7] wire io_dmem_resp_valid_0; // @[arbiter.scala:15:7] wire [31:0] io_mem_req_bits_addr_0; // @[arbiter.scala:15:7] wire io_mem_req_bits_fcn_0; // @[arbiter.scala:15:7] wire [2:0] io_mem_req_bits_typ_0; // @[arbiter.scala:15:7] wire io_mem_req_valid_0; // @[arbiter.scala:15:7] reg d_resp; // @[arbiter.scala:26:23] assign io_dmem_req_ready_0 = ~d_resp; // @[arbiter.scala:15:7, :26:23, :33:3, :35:23, :47:23] wire _io_imem_req_ready_T = ~io_dmem_req_valid_0; // @[arbiter.scala:15:7, :48:46] wire _io_imem_req_ready_T_1 = _io_imem_req_ready_T; // @[arbiter.scala:48:{43,46}] assign io_imem_req_ready_0 = d_resp \| _io_imem_req_ready_T_1; // @[arbiter.scala:15:7, :26:23, :33:3, :36:23, :48:{23,43}] wire _T_2 = io_dmem_req_ready_0 & io_dmem_req_valid_0; // @[Decoupled.scala:51:35] assign io_mem_req_valid_0 = _T_2 ? io_dmem_req_valid_0 : io_imem_req_valid_0; // @[Decoupled.scala:51:35] assign io_mem_req_bits_addr_0 = _T_2 ? io_dmem_req_bits_addr_0 : io_imem_req_bits_addr_0; // @[Decoupled.scala:51:35] assign io_mem_req_bits_fcn_0 = _T_2 & io_dmem_req_bits_fcn_0; // @[Decoupled.scala:51:35] assign io_mem_req_bits_typ_0 = _T_2 ? io_dmem_req_bits_typ_0 : 3'h7; // @[Decoupled.scala:51:35] assign io_imem_resp_valid_0 = ~d_resp & io_mem_resp_valid_0; // @[arbiter.scala:15:7, :26:23, :72:3, :73:24, :77:24] assign io_dmem_resp_valid_0 = d_resp & io_mem_resp_valid_0; // @[arbiter.scala:15:7, :26:23, :72:3, :74:24, :78:24] always @(posedge clock) begin // @[arbiter.scala:15:7] if (reset) // @[arbiter.scala:15:7] d_resp <= 1'h0; // @[arbiter.scala:26:23] else if (d_resp) // @[arbiter.scala:26:23] d_resp <= ~io_mem_req_valid_0 & d_resp; // @[arbiter.scala:15:7, :26:23, :40:5, :41:14] else // @[arbiter.scala:26:23] d_resp <= io_dmem_req_ready_0 & io_dmem_req_valid_0 \| d_resp; // @[Decoupled.scala:51:35] always @(posedge) assign io_imem_req_ready = io_imem_req_ready_0; // @[arbiter.scala:15:7] assign io_imem_resp_valid = io_imem_resp_valid_0; // @[arbiter.scala:15:7] assign io_imem_resp_bits_data = io_imem_resp_bits_data_0; // @[arbiter.scala:15:7] assign io_dmem_req_ready = io_dmem_req_ready_0; // @[arbiter.scala:15:7] assign io_dmem_resp_valid = io_dmem_resp_valid_0; // @[arbiter.scala:15:7] assign io_dmem_resp_bits_data = io_dmem_resp_bits_data_0; // @[arbiter.scala:15:7] assign io_mem_req_valid = io_mem_req_valid_0; // @[arbiter.scala:15:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[arbiter.scala:15:7] assign io_mem_req_bits_data = io_mem_req_bits_data_0; // @[arbiter.scala:15:7] assign io_mem_req_bits_fcn = io_mem_req_bits_fcn_0; // @[arbiter.scala:15:7] assign io_mem_req_bits_typ = io_mem_req_bits_typ_0; // @[arbiter.scala:15:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module TLFragmenter_2( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [13:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [13:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} \| ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {\|dFirst_size_hi, \|(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] \| _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (\|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready \| drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [1:0] _maxLgHint_T = {2{~(_repeater_io_deq_bits_address[8])}}; // @[Mux.scala:30:73] wire [1:0] _maxLgHint_T_1 = {2{_repeater_io_deq_bits_address[8]}}; // @[Mux.scala:30:73] wire [7:0][1:0] _GEN_0 = {{2'h3}, {2'h3}, {_maxLgHint_T \| _maxLgHint_T_1}, {_maxLgHint_T \| _maxLgHint_T_1}, {_maxLgHint_T \| _maxLgHint_T_1}, {_maxLgHint_T \| _maxLgHint_T_1}, {_maxLgHint_T \| _maxLgHint_T_1}, {_maxLgHint_T \| _maxLgHint_T_1}}; // @[Mux.scala:30:73] wire [1:0] limit = _GEN_0[_repeater_io_deq_bits_opcode]; // @[Fragmenter.scala:274:30, :288:49] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_175( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) } File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File fpu.scala: //**************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ package boom.v3.exu import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile.FPConstants._ import freechips.rocketchip.tile.{FPUCtrlSigs, HasFPUParameters} import freechips.rocketchip.tile import freechips.rocketchip.rocket import freechips.rocketchip.util.uintToBitPat import boom.v3.common._ import boom.v3.util.{ImmGenRm, ImmGenTyp} / * FP Decoder for the FPU * * TODO get rid of this decoder and move into the Decode stage? Or the RRd stage? * most of these signals are already created, just need to be translated * to the Rocket FPU-speak / class UOPCodeFPUDecoder(implicit p: Parameters) extends BoomModule with HasFPUParameters { val io = IO(new Bundle { val uopc = Input(Bits(UOPC_SZ.W)) val sigs = Output(new FPUCtrlSigs()) }) // TODO change N,Y,X to BitPat("b1"), BitPat("b0"), and BitPat("b?") val N = false.B val Y = true.B val X = false.B val default: List[BitPat] = List(X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) val f_table: Array[(BitPat, List[BitPat])] = // Note: not all of these signals are used or necessary, but we're // constrained by the need to fit the rocket.FPU units' ctrl signals. // swap12 fma // \| swap32 \| div // \| \| typeTagIn \| \| sqrt // ldst \| \| \| typeTagOut \| \| wflags // \| wen \| \| \| \| from_int \| \| \| // \| \| ren1 \| \| \| \| \| to_int \| \| \| // \| \| \| ren2 \| \| \| \| \| \| fastpipe \| // \| \| \| \| ren3 \| \| \| \| \| \| \| \| \| \| // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| Array( BitPat(uopFCLASS_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,N), BitPat(uopFMV_W_X) -> List(X,X,N,N,N, X,X,S,D,Y,N,N, N,N,N,N), BitPat(uopFMV_X_W) -> List(X,X,Y,N,N, N,X,D,S,N,Y,N, N,N,N,N), BitPat(uopFCVT_S_X) -> List(X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), BitPat(uopFCVT_X_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), BitPat(uopCMPR_S) -> List(X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), BitPat(uopFSGNJ_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), BitPat(uopFMINMAX_S)-> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y), BitPat(uopFADD_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), BitPat(uopFSUB_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), BitPat(uopFMUL_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,N, Y,N,N,Y), BitPat(uopFMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), BitPat(uopFMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), BitPat(uopFNMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), BitPat(uopFNMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y) ) val d_table: Array[(BitPat, List[BitPat])] = Array( BitPat(uopFCLASS_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), BitPat(uopFMV_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,N), BitPat(uopFMV_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), BitPat(uopFCVT_S_D) -> List(X,X,Y,N,N, N,X,D,S,N,N,Y, N,N,N,Y), BitPat(uopFCVT_D_S) -> List(X,X,Y,N,N, N,X,S,D,N,N,Y, N,N,N,Y), BitPat(uopFCVT_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), BitPat(uopFCVT_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), BitPat(uopCMPR_D) -> List(X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), BitPat(uopFSGNJ_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), BitPat(uopFMINMAX_D)-> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y), BitPat(uopFADD_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), BitPat(uopFSUB_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), BitPat(uopFMUL_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,N, Y,N,N,Y), BitPat(uopFMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), BitPat(uopFMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), BitPat(uopFNMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), BitPat(uopFNMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y) ) // val insns = fLen match { // case 32 => f_table // case 64 => f_table ++ d_table // } val insns = f_table ++ d_table val decoder = rocket.DecodeLogic(io.uopc, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags) sigs zip decoder map {case(s,d) => s := d} s.vec := false.B } /* * FP fused multiple add decoder for the FPU / class FMADecoder extends Module { val io = IO(new Bundle { val uopc = Input(UInt(UOPC_SZ.W)) val cmd = Output(UInt(2.W)) }) val default: List[BitPat] = List(BitPat("b??")) val table: Array[(BitPat, List[BitPat])] = Array( BitPat(uopFADD_S) -> List(BitPat("b00")), BitPat(uopFSUB_S) -> List(BitPat("b01")), BitPat(uopFMUL_S) -> List(BitPat("b00")), BitPat(uopFMADD_S) -> List(BitPat("b00")), BitPat(uopFMSUB_S) -> List(BitPat("b01")), BitPat(uopFNMADD_S) -> List(BitPat("b11")), BitPat(uopFNMSUB_S) -> List(BitPat("b10")), BitPat(uopFADD_D) -> List(BitPat("b00")), BitPat(uopFSUB_D) -> List(BitPat("b01")), BitPat(uopFMUL_D) -> List(BitPat("b00")), BitPat(uopFMADD_D) -> List(BitPat("b00")), BitPat(uopFMSUB_D) -> List(BitPat("b01")), BitPat(uopFNMADD_D) -> List(BitPat("b11")), BitPat(uopFNMSUB_D) -> List(BitPat("b10")) ) val decoder = rocket.DecodeLogic(io.uopc, default, table) val (cmd: UInt) :: Nil = decoder io.cmd := cmd } /* * Bundle representing data to be sent to the FPU / class FpuReq()(implicit p: Parameters) extends BoomBundle { val uop = new MicroOp() val rs1_data = Bits(65.W) val rs2_data = Bits(65.W) val rs3_data = Bits(65.W) val fcsr_rm = Bits(tile.FPConstants.RM_SZ.W) } /* * FPU unit that wraps the RocketChip FPU units (which in turn wrap hardfloat) */ class FPU(implicit p: Parameters) extends BoomModule with tile.HasFPUParameters { val io = IO(new Bundle { val req = Flipped(new ValidIO(new FpuReq)) val resp = new ValidIO(new ExeUnitResp(65)) }) io.resp.bits := DontCare // all FP units are padded out to the same latency for easy scheduling of the write port val fpu_latency = dfmaLatency val io_req = io.req.bits val fp_decoder = Module(new UOPCodeFPUDecoder) fp_decoder.io.uopc := io_req.uop.uopc val fp_ctrl = fp_decoder.io.sigs val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io_req.fcsr_rm, ImmGenRm(io_req.uop.imm_packed)) def fuInput(minT: Option[tile.FType]): tile.FPInput = { val req = Wire(new tile.FPInput) val tag = fp_ctrl.typeTagIn req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl req.rm := fp_rm req.in1 := unbox(io_req.rs1_data, tag, minT) req.in2 := unbox(io_req.rs2_data, tag, minT) req.in3 := unbox(io_req.rs3_data, tag, minT) when (fp_ctrl.swap23) { req.in3 := req.in2 } req.typ := ImmGenTyp(io_req.uop.imm_packed) req.fmt := Mux(tag === S, 0.U, 1.U) // TODO support Zfh and avoid special-case below when (io_req.uop.uopc === uopFMV_X_W) { req.fmt := 0.U } val fma_decoder = Module(new FMADecoder) fma_decoder.io.uopc := io_req.uop.uopc req.fmaCmd := fma_decoder.io.cmd // ex_reg_inst(3,2) \| (!fp_ctrl.ren3 && ex_reg_inst(27)) req } val dfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.D)) dfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === D) dfma.io.in.bits := fuInput(Some(dfma.t)) val sfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.S)) sfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === S) sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new tile.FPToInt) fpiu.io.in.valid := io.req.valid && (fp_ctrl.toint \|\| (fp_ctrl.fastpipe && fp_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) val fpiu_out = Pipe(RegNext(fpiu.io.in.valid && !fp_ctrl.fastpipe), fpiu.io.out.bits, fpu_latency-1) val fpiu_result = Wire(new tile.FPResult) fpiu_result.data := fpiu_out.bits.toint fpiu_result.exc := fpiu_out.bits.exc val fpmu = Module(new tile.FPToFP(fpu_latency)) // latency 2 for rocket fpmu.io.in.valid := io.req.valid && fp_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val fpmu_double = Pipe(io.req.valid && fp_ctrl.fastpipe, fp_ctrl.typeTagOut === D, fpu_latency).bits // Response (all FP units have been padded out to the same latency) io.resp.valid := fpiu_out.valid \|\| fpmu.io.out.valid \|\| sfma.io.out.valid \|\| dfma.io.out.valid val fpu_out_data = Mux(dfma.io.out.valid, box(dfma.io.out.bits.data, true.B), Mux(sfma.io.out.valid, box(sfma.io.out.bits.data, false.B), Mux(fpiu_out.valid, fpiu_result.data, box(fpmu.io.out.bits.data, fpmu_double)))) val fpu_out_exc = Mux(dfma.io.out.valid, dfma.io.out.bits.exc, Mux(sfma.io.out.valid, sfma.io.out.bits.exc, Mux(fpiu_out.valid, fpiu_result.exc, fpmu.io.out.bits.exc))) io.resp.bits.data := fpu_out_data io.resp.bits.fflags.valid := io.resp.valid io.resp.bits.fflags.bits.flags := fpu_out_exc }	module FPU( // @[fpu.scala:170:7] input clock, // @[fpu.scala:170:7] input reset, // @[fpu.scala:170:7] input io_req_valid, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_uopc, // @[fpu.scala:172:14] input [31:0] io_req_bits_uop_inst, // @[fpu.scala:172:14] input [31:0] io_req_bits_uop_debug_inst, // @[fpu.scala:172:14] input io_req_bits_uop_is_rvc, // @[fpu.scala:172:14] input [39:0] io_req_bits_uop_debug_pc, // @[fpu.scala:172:14] input [2:0] io_req_bits_uop_iq_type, // @[fpu.scala:172:14] input [9:0] io_req_bits_uop_fu_code, // @[fpu.scala:172:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[fpu.scala:172:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[fpu.scala:172:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[fpu.scala:172:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[fpu.scala:172:14] input io_req_bits_uop_ctrl_fcn_dw, // @[fpu.scala:172:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[fpu.scala:172:14] input io_req_bits_uop_ctrl_is_load, // @[fpu.scala:172:14] input io_req_bits_uop_ctrl_is_sta, // @[fpu.scala:172:14] input io_req_bits_uop_ctrl_is_std, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_iw_state, // @[fpu.scala:172:14] input io_req_bits_uop_iw_p1_poisoned, // @[fpu.scala:172:14] input io_req_bits_uop_iw_p2_poisoned, // @[fpu.scala:172:14] input io_req_bits_uop_is_br, // @[fpu.scala:172:14] input io_req_bits_uop_is_jalr, // @[fpu.scala:172:14] input io_req_bits_uop_is_jal, // @[fpu.scala:172:14] input io_req_bits_uop_is_sfb, // @[fpu.scala:172:14] input [15:0] io_req_bits_uop_br_mask, // @[fpu.scala:172:14] input [3:0] io_req_bits_uop_br_tag, // @[fpu.scala:172:14] input [4:0] io_req_bits_uop_ftq_idx, // @[fpu.scala:172:14] input io_req_bits_uop_edge_inst, // @[fpu.scala:172:14] input [5:0] io_req_bits_uop_pc_lob, // @[fpu.scala:172:14] input io_req_bits_uop_taken, // @[fpu.scala:172:14] input [19:0] io_req_bits_uop_imm_packed, // @[fpu.scala:172:14] input [11:0] io_req_bits_uop_csr_addr, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_rob_idx, // @[fpu.scala:172:14] input [4:0] io_req_bits_uop_ldq_idx, // @[fpu.scala:172:14] input [4:0] io_req_bits_uop_stq_idx, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_rxq_idx, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_pdst, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_prs1, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_prs2, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_prs3, // @[fpu.scala:172:14] input [4:0] io_req_bits_uop_ppred, // @[fpu.scala:172:14] input io_req_bits_uop_prs1_busy, // @[fpu.scala:172:14] input io_req_bits_uop_prs2_busy, // @[fpu.scala:172:14] input io_req_bits_uop_prs3_busy, // @[fpu.scala:172:14] input io_req_bits_uop_ppred_busy, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_stale_pdst, // @[fpu.scala:172:14] input io_req_bits_uop_exception, // @[fpu.scala:172:14] input [63:0] io_req_bits_uop_exc_cause, // @[fpu.scala:172:14] input io_req_bits_uop_bypassable, // @[fpu.scala:172:14] input [4:0] io_req_bits_uop_mem_cmd, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_mem_size, // @[fpu.scala:172:14] input io_req_bits_uop_mem_signed, // @[fpu.scala:172:14] input io_req_bits_uop_is_fence, // @[fpu.scala:172:14] input io_req_bits_uop_is_fencei, // @[fpu.scala:172:14] input io_req_bits_uop_is_amo, // @[fpu.scala:172:14] input io_req_bits_uop_uses_ldq, // @[fpu.scala:172:14] input io_req_bits_uop_uses_stq, // @[fpu.scala:172:14] input io_req_bits_uop_is_sys_pc2epc, // @[fpu.scala:172:14] input io_req_bits_uop_is_unique, // @[fpu.scala:172:14] input io_req_bits_uop_flush_on_commit, // @[fpu.scala:172:14] input io_req_bits_uop_ldst_is_rs1, // @[fpu.scala:172:14] input [5:0] io_req_bits_uop_ldst, // @[fpu.scala:172:14] input [5:0] io_req_bits_uop_lrs1, // @[fpu.scala:172:14] input [5:0] io_req_bits_uop_lrs2, // @[fpu.scala:172:14] input [5:0] io_req_bits_uop_lrs3, // @[fpu.scala:172:14] input io_req_bits_uop_ldst_val, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_dst_rtype, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[fpu.scala:172:14] input io_req_bits_uop_frs3_en, // @[fpu.scala:172:14] input io_req_bits_uop_fp_val, // @[fpu.scala:172:14] input io_req_bits_uop_fp_single, // @[fpu.scala:172:14] input io_req_bits_uop_xcpt_pf_if, // @[fpu.scala:172:14] input io_req_bits_uop_xcpt_ae_if, // @[fpu.scala:172:14] input io_req_bits_uop_xcpt_ma_if, // @[fpu.scala:172:14] input io_req_bits_uop_bp_debug_if, // @[fpu.scala:172:14] input io_req_bits_uop_bp_xcpt_if, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[fpu.scala:172:14] input [64:0] io_req_bits_rs1_data, // @[fpu.scala:172:14] input [64:0] io_req_bits_rs2_data, // @[fpu.scala:172:14] input [64:0] io_req_bits_rs3_data, // @[fpu.scala:172:14] input [2:0] io_req_bits_fcsr_rm, // @[fpu.scala:172:14] output [64:0] io_resp_bits_data, // @[fpu.scala:172:14] output io_resp_bits_fflags_valid, // @[fpu.scala:172:14] output [4:0] io_resp_bits_fflags_bits_flags // @[fpu.scala:172:14] ); wire io_resp_valid; // @[fpu.scala:170:7] wire _fpmu_io_out_valid; // @[fpu.scala:225:20] wire [64:0] _fpmu_io_out_bits_data; // @[fpu.scala:225:20] wire [4:0] _fpmu_io_out_bits_exc; // @[fpu.scala:225:20] wire _fpiu_io_out_bits_in_ldst; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_wen; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_ren1; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_ren2; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_ren3; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_swap12; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_swap23; // @[fpu.scala:216:20] wire [1:0] _fpiu_io_out_bits_in_typeTagIn; // @[fpu.scala:216:20] wire [1:0] _fpiu_io_out_bits_in_typeTagOut; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_fromint; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_toint; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_fastpipe; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_fma; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_div; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_sqrt; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_wflags; // @[fpu.scala:216:20] wire [2:0] _fpiu_io_out_bits_in_rm; // @[fpu.scala:216:20] wire [1:0] _fpiu_io_out_bits_in_fmaCmd; // @[fpu.scala:216:20] wire [1:0] _fpiu_io_out_bits_in_typ; // @[fpu.scala:216:20] wire [1:0] _fpiu_io_out_bits_in_fmt; // @[fpu.scala:216:20] wire [64:0] _fpiu_io_out_bits_in_in1; // @[fpu.scala:216:20] wire [64:0] _fpiu_io_out_bits_in_in2; // @[fpu.scala:216:20] wire [64:0] _fpiu_io_out_bits_in_in3; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_lt; // @[fpu.scala:216:20] wire [63:0] _fpiu_io_out_bits_store; // @[fpu.scala:216:20] wire [63:0] _fpiu_io_out_bits_toint; // @[fpu.scala:216:20] wire [4:0] _fpiu_io_out_bits_exc; // @[fpu.scala:216:20] wire _sfma_io_out_valid; // @[fpu.scala:212:20] wire [64:0] _sfma_io_out_bits_data; // @[fpu.scala:212:20] wire [4:0] _sfma_io_out_bits_exc; // @[fpu.scala:212:20] wire _dfma_io_out_valid; // @[fpu.scala:208:20] wire [64:0] _dfma_io_out_bits_data; // @[fpu.scala:208:20] wire [4:0] _dfma_io_out_bits_exc; // @[fpu.scala:208:20] wire _fp_decoder_io_sigs_ldst; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_wen; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_ren1; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_ren2; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_ren3; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_swap12; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_swap23; // @[fpu.scala:182:26] wire [1:0] _fp_decoder_io_sigs_typeTagIn; // @[fpu.scala:182:26] wire [1:0] _fp_decoder_io_sigs_typeTagOut; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_fromint; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_toint; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_fma; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_div; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_sqrt; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26] wire io_req_valid_0 = io_req_valid; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[fpu.scala:170:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[fpu.scala:170:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[fpu.scala:170:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[fpu.scala:170:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[fpu.scala:170:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[fpu.scala:170:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[fpu.scala:170:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[fpu.scala:170:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[fpu.scala:170:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[fpu.scala:170:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[fpu.scala:170:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[fpu.scala:170:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[fpu.scala:170:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[fpu.scala:170:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[fpu.scala:170:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[fpu.scala:170:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[fpu.scala:170:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[fpu.scala:170:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[fpu.scala:170:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[fpu.scala:170:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[fpu.scala:170:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[fpu.scala:170:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[fpu.scala:170:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[fpu.scala:170:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[fpu.scala:170:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[fpu.scala:170:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[fpu.scala:170:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[fpu.scala:170:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[fpu.scala:170:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[fpu.scala:170:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[fpu.scala:170:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[fpu.scala:170:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[fpu.scala:170:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[fpu.scala:170:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[fpu.scala:170:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[fpu.scala:170:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[fpu.scala:170:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[fpu.scala:170:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[fpu.scala:170:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[fpu.scala:170:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[fpu.scala:170:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[fpu.scala:170:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[fpu.scala:170:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[fpu.scala:170:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[fpu.scala:170:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[fpu.scala:170:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[fpu.scala:170:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[fpu.scala:170:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[fpu.scala:170:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[fpu.scala:170:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[fpu.scala:170:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[fpu.scala:170:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[fpu.scala:170:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[fpu.scala:170:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[fpu.scala:170:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[fpu.scala:170:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[fpu.scala:170:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[fpu.scala:170:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[fpu.scala:170:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[fpu.scala:170:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[fpu.scala:170:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[fpu.scala:170:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[fpu.scala:170:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[fpu.scala:170:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[fpu.scala:170:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[fpu.scala:170:7] wire [64:0] io_req_bits_rs3_data_0 = io_req_bits_rs3_data; // @[fpu.scala:170:7] wire [2:0] io_req_bits_fcsr_rm_0 = io_req_bits_fcsr_rm; // @[fpu.scala:170:7] wire [64:0] _dfma_io_in_bits_req_in1_T = 65'h0; // @[FPU.scala:372:31] wire [64:0] _dfma_io_in_bits_req_in2_T = 65'h0; // @[FPU.scala:372:31] wire [64:0] _dfma_io_in_bits_req_in3_T = 65'h0; // @[FPU.scala:372:31] wire [4:0] fpu_out_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [4:0] fpu_out_data_opts_bigger_swizzledNaN_hi_hi_1 = 5'h1F; // @[FPU.scala:336:26] wire [4:0] fpu_out_data_opts_bigger_swizzledNaN_hi_hi_2 = 5'h1F; // @[FPU.scala:336:26] wire _fpu_out_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42] wire _fpu_out_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56] wire _fpu_out_data_T = 1'h1; // @[package.scala:39:86] wire _fpu_out_data_opts_bigger_swizzledNaN_T_4 = 1'h1; // @[FPU.scala:338:42] wire _fpu_out_data_opts_bigger_T_1 = 1'h1; // @[FPU.scala:249:56] wire _fpu_out_data_opts_bigger_swizzledNaN_T_8 = 1'h1; // @[FPU.scala:338:42] wire _fpu_out_data_opts_bigger_T_2 = 1'h1; // @[FPU.scala:249:56] wire [63:0] io_resp_bits_uop_exc_cause = 64'h0; // @[fpu.scala:170:7] wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[fpu.scala:170:7] wire [11:0] io_resp_bits_uop_csr_addr = 12'h0; // @[fpu.scala:170:7] wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[fpu.scala:170:7] wire [19:0] io_resp_bits_uop_imm_packed = 20'h0; // @[fpu.scala:170:7] wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_uop_pc_lob = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_uop_ldst = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_uop_lrs1 = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_uop_lrs2 = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_uop_lrs3 = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_fflags_bits_uop_ldst = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[fpu.scala:170:7] wire [15:0] io_resp_bits_uop_br_mask = 16'h0; // @[fpu.scala:170:7] wire [15:0] io_resp_bits_fflags_bits_uop_br_mask = 16'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_uop_ftq_idx = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_uop_ldq_idx = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_uop_stq_idx = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_uop_ppred = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_uop_mem_cmd = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_fflags_bits_uop_ppred = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_iw_state = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_rxq_idx = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_mem_size = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_dst_rtype = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_lrs1_rtype = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_lrs2_rtype = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_debug_fsrc = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_debug_tsrc = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_iw_state = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_mem_size = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[fpu.scala:170:7] wire [3:0] io_resp_bits_uop_ctrl_br_type = 4'h0; // @[fpu.scala:170:7] wire [3:0] io_resp_bits_uop_br_tag = 4'h0; // @[fpu.scala:170:7] wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[fpu.scala:170:7] wire [3:0] io_resp_bits_fflags_bits_uop_br_tag = 4'h0; // @[fpu.scala:170:7] wire [9:0] io_resp_bits_uop_fu_code = 10'h0; // @[fpu.scala:170:7] wire [9:0] io_resp_bits_fflags_bits_uop_fu_code = 10'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_uop_iq_type = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_fflags_bits_uop_iq_type = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[fpu.scala:170:7] wire [39:0] io_resp_bits_uop_debug_pc = 40'h0; // @[fpu.scala:170:7] wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[fpu.scala:170:7] wire [31:0] io_resp_bits_uop_inst = 32'h0; // @[fpu.scala:170:7] wire [31:0] io_resp_bits_uop_debug_inst = 32'h0; // @[fpu.scala:170:7] wire [31:0] io_resp_bits_fflags_bits_uop_inst = 32'h0; // @[fpu.scala:170:7] wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_uopc = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_rob_idx = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_pdst = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_prs1 = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_prs2 = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_prs3 = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_stale_pdst = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_uopc = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_pdst = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs1 = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs2 = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs3 = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_rvc = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ctrl_fcn_dw = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ctrl_is_load = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ctrl_is_sta = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ctrl_is_std = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_iw_p1_poisoned = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_iw_p2_poisoned = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_br = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_jalr = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_jal = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_sfb = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_edge_inst = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_taken = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_prs1_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_prs2_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_prs3_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ppred_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_exception = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_bypassable = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_mem_signed = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_fence = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_fencei = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_amo = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_uses_ldq = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_uses_stq = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_sys_pc2epc = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_unique = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_flush_on_commit = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ldst_is_rs1 = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ldst_val = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_frs3_en = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_fp_val = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_fp_single = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_xcpt_pf_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_xcpt_ae_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_xcpt_ma_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_bp_debug_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_bp_xcpt_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_predicated = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_br = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_jal = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_taken = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_exception = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_bypassable = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_fence = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_amo = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_unique = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_fp_val = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_fp_single = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[fpu.scala:170:7] wire dfma_io_in_bits_req_vec = 1'h0; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_vec = 1'h0; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_vec = 1'h0; // @[fpu.scala:188:19] wire _fpu_out_data_T_2 = 1'h0; // @[package.scala:39:86] wire [64:0] _dfma_io_in_bits_req_in1_T_1 = io_req_bits_rs1_data_0; // @[FPU.scala:372:26] wire [64:0] _dfma_io_in_bits_req_in2_T_1 = io_req_bits_rs2_data_0; // @[FPU.scala:372:26] wire [64:0] _dfma_io_in_bits_req_in3_T_1 = io_req_bits_rs3_data_0; // @[FPU.scala:372:26] wire _io_resp_valid_T_2; // @[fpu.scala:234:38] wire io_resp_bits_fflags_valid_0 = io_resp_valid; // @[fpu.scala:170:7] wire [64:0] fpu_out_data; // @[fpu.scala:237:8] wire [4:0] fpu_out_exc; // @[fpu.scala:243:8] wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[fpu.scala:170:7] wire [64:0] io_resp_bits_data_0; // @[fpu.scala:170:7] wire [2:0] _fp_rm_T = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire [2:0] _fp_rm_T_2 = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire _fp_rm_T_1 = &_fp_rm_T; // @[util.scala:289:58] wire [2:0] fp_rm = _fp_rm_T_1 ? io_req_bits_fcsr_rm_0 : _fp_rm_T_2; // @[util.scala:289:58] wire [2:0] dfma_io_in_bits_req_rm = fp_rm; // @[fpu.scala:185:18, :188:19] wire [2:0] sfma_io_in_bits_req_rm = fp_rm; // @[fpu.scala:185:18, :188:19] wire [2:0] fpiu_io_in_bits_req_rm = fp_rm; // @[fpu.scala:185:18, :188:19] wire _GEN = io_req_valid_0 & _fp_decoder_io_sigs_fma; // @[fpu.scala:170:7, :182:26, :209:36] wire _dfma_io_in_valid_T; // @[fpu.scala:209:36] assign _dfma_io_in_valid_T = _GEN; // @[fpu.scala:209:36] wire _sfma_io_in_valid_T; // @[fpu.scala:213:36] assign _sfma_io_in_valid_T = _GEN; // @[fpu.scala:209:36, :213:36] wire _GEN_0 = _fp_decoder_io_sigs_typeTagOut == 2'h1; // @[fpu.scala:182:26, :209:74] wire _dfma_io_in_valid_T_1; // @[fpu.scala:209:74] assign _dfma_io_in_valid_T_1 = _GEN_0; // @[fpu.scala:209:74] wire _fpmu_double_T_1; // @[fpu.scala:229:79] assign _fpmu_double_T_1 = _GEN_0; // @[fpu.scala:209:74, :229:79] wire _dfma_io_in_valid_T_2 = _dfma_io_in_valid_T & _dfma_io_in_valid_T_1; // @[fpu.scala:209:{36,51,74}] wire [1:0] _dfma_io_in_bits_req_typ_T; // @[util.scala:295:59] wire dfma_io_in_bits_req_ldst; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_wen; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_ren1; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_ren2; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_ren3; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_swap12; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_swap23; // @[fpu.scala:188:19] wire [1:0] dfma_io_in_bits_req_typeTagIn; // @[fpu.scala:188:19] wire [1:0] dfma_io_in_bits_req_typeTagOut; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_fromint; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_toint; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_fastpipe; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_fma; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_div; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_sqrt; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_wflags; // @[fpu.scala:188:19] wire [1:0] dfma_io_in_bits_req_fmaCmd; // @[fpu.scala:188:19] wire [1:0] dfma_io_in_bits_req_typ; // @[fpu.scala:188:19] wire [1:0] dfma_io_in_bits_req_fmt; // @[fpu.scala:188:19] wire [64:0] dfma_io_in_bits_req_in1; // @[fpu.scala:188:19] wire [64:0] dfma_io_in_bits_req_in2; // @[fpu.scala:188:19] wire [64:0] dfma_io_in_bits_req_in3; // @[fpu.scala:188:19] wire _dfma_io_in_bits_req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _sfma_io_in_bits_req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] dfma_io_in_bits_req_in1_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in1_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in1_prev_prev_sign = dfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in1_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in1_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in1_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_expOut_T \| _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in1_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in1_floats_0 = {dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _sfma_io_in_bits_req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _fpiu_io_in_bits_req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire dfma_io_in_bits_req_in1_prev_isbox = &_dfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in1_oks_0 = dfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in1 = _dfma_io_in_bits_req_in1_T_1; // @[FPU.scala:372:26] wire _dfma_io_in_bits_req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _sfma_io_in_bits_req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] dfma_io_in_bits_req_in2_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in2_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in2_prev_prev_sign = dfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in2_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in2_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in2_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_expOut_T \| _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in2_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in2_floats_0 = {dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _sfma_io_in_bits_req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _fpiu_io_in_bits_req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire dfma_io_in_bits_req_in2_prev_isbox = &_dfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in2_oks_0 = dfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in2 = _dfma_io_in_bits_req_in2_T_1; // @[FPU.scala:372:26] wire _dfma_io_in_bits_req_in3_prev_unswizzled_T = io_req_bits_rs3_data_0[31]; // @[FPU.scala:357:14] wire _sfma_io_in_bits_req_in3_prev_unswizzled_T = io_req_bits_rs3_data_0[31]; // @[FPU.scala:357:14] wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T = io_req_bits_rs3_data_0[31]; // @[FPU.scala:357:14] wire _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = io_req_bits_rs3_data_0[52]; // @[FPU.scala:358:14] wire _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = io_req_bits_rs3_data_0[52]; // @[FPU.scala:358:14] wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = io_req_bits_rs3_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = io_req_bits_rs3_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = io_req_bits_rs3_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = io_req_bits_rs3_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] dfma_io_in_bits_req_in3_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in3_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in3_prev_prev_sign = dfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in3_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in3_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in3_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_expOut_T \| _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in3_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in3_floats_0 = {dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in3_prev_isbox_T = io_req_bits_rs3_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _sfma_io_in_bits_req_in3_prev_isbox_T = io_req_bits_rs3_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _fpiu_io_in_bits_req_in3_prev_isbox_T = io_req_bits_rs3_data_0[64:60]; // @[FPU.scala:332:49] wire dfma_io_in_bits_req_in3_prev_isbox = &_dfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in3_oks_0 = dfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in3 = _fp_decoder_io_sigs_swap23 ? dfma_io_in_bits_req_in2 : _dfma_io_in_bits_req_in3_T_1; // @[FPU.scala:372:26] assign _dfma_io_in_bits_req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59] wire [1:0] _sfma_io_in_bits_req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59] wire [1:0] _fpiu_io_in_bits_req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59] assign dfma_io_in_bits_req_typ = _dfma_io_in_bits_req_typ_T; // @[util.scala:295:59] wire _GEN_1 = _fp_decoder_io_sigs_typeTagIn == 2'h0; // @[fpu.scala:182:26, :197:24] wire _dfma_io_in_bits_req_fmt_T; // @[fpu.scala:197:24] assign _dfma_io_in_bits_req_fmt_T = _GEN_1; // @[fpu.scala:197:24] wire _sfma_io_in_bits_req_fmt_T; // @[fpu.scala:197:24] assign _sfma_io_in_bits_req_fmt_T = _GEN_1; // @[fpu.scala:197:24] wire _fpiu_io_in_bits_req_fmt_T; // @[fpu.scala:197:24] assign _fpiu_io_in_bits_req_fmt_T = _GEN_1; // @[fpu.scala:197:24] wire _dfma_io_in_bits_req_fmt_T_1 = ~_dfma_io_in_bits_req_fmt_T; // @[fpu.scala:197:{19,24}] wire _GEN_2 = io_req_bits_uop_uopc_0 == 7'h46; // @[fpu.scala:170:7, :198:27] wire _dfma_io_in_bits_T; // @[fpu.scala:198:27] assign _dfma_io_in_bits_T = _GEN_2; // @[fpu.scala:198:27] wire _sfma_io_in_bits_T; // @[fpu.scala:198:27] assign _sfma_io_in_bits_T = _GEN_2; // @[fpu.scala:198:27] wire _fpiu_io_in_bits_T; // @[fpu.scala:198:27] assign _fpiu_io_in_bits_T = _GEN_2; // @[fpu.scala:198:27] assign dfma_io_in_bits_req_fmt = _dfma_io_in_bits_T ? 2'h0 : {1'h0, _dfma_io_in_bits_req_fmt_T_1}; // @[fpu.scala:188:19, :197:{13,19}, :198:{27,43}, :199:15] wire _sfma_io_in_valid_T_1 = _fp_decoder_io_sigs_typeTagOut == 2'h0; // @[fpu.scala:182:26, :213:74] wire _sfma_io_in_valid_T_2 = _sfma_io_in_valid_T & _sfma_io_in_valid_T_1; // @[fpu.scala:213:{36,51,74}] wire sfma_io_in_bits_req_ldst; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_wen; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_ren1; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_ren2; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_ren3; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_swap12; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_swap23; // @[fpu.scala:188:19] wire [1:0] sfma_io_in_bits_req_typeTagIn; // @[fpu.scala:188:19] wire [1:0] sfma_io_in_bits_req_typeTagOut; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_fromint; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_toint; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_fastpipe; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_fma; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_div; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_sqrt; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_wflags; // @[fpu.scala:188:19] wire [1:0] sfma_io_in_bits_req_fmaCmd; // @[fpu.scala:188:19] wire [1:0] sfma_io_in_bits_req_typ; // @[fpu.scala:188:19] wire [1:0] sfma_io_in_bits_req_fmt; // @[fpu.scala:188:19] wire [64:0] sfma_io_in_bits_req_in1; // @[fpu.scala:188:19] wire [64:0] sfma_io_in_bits_req_in2; // @[fpu.scala:188:19] wire [64:0] sfma_io_in_bits_req_in3; // @[fpu.scala:188:19] wire [1:0] sfma_io_in_bits_req_in1_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in1_floats_0 = {sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in1_prev_isbox = &_sfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in1_oks_0 = sfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in1_sign = io_req_bits_rs1_data_0[64]; // @[FPU.scala:274:17] wire [51:0] sfma_io_in_bits_req_in1_fractIn = io_req_bits_rs1_data_0[51:0]; // @[FPU.scala:275:20] wire [11:0] sfma_io_in_bits_req_in1_expIn = io_req_bits_rs1_data_0[63:52]; // @[FPU.scala:276:18] wire [75:0] _sfma_io_in_bits_req_in1_fractOut_T = {sfma_io_in_bits_req_in1_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in1_fractOut = _sfma_io_in_bits_req_in1_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in1_expOut_expCode = sfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in1_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in1_expOut_commonCase = _sfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in1_expOut_T = sfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in1_expOut_T_1 = sfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in1_expOut_T_2 = _sfma_io_in_bits_req_in1_expOut_T \| _sfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in1_expOut_T_3 = sfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_4 = {sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_5 = sfma_io_in_bits_req_in1_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in1_expOut = _sfma_io_in_bits_req_in1_expOut_T_2 ? _sfma_io_in_bits_req_in1_expOut_T_4 : _sfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in1_hi = {sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in1_floats_1 = {sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in1_T = sfma_io_in_bits_req_in1_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in1_T_1 = sfma_io_in_bits_req_in1_floats_0 \| _sfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in1 = {32'h0, _sfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:372:26] wire [1:0] sfma_io_in_bits_req_in2_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in2_floats_0 = {sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in2_prev_isbox = &_sfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in2_oks_0 = sfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in2_sign = io_req_bits_rs2_data_0[64]; // @[FPU.scala:274:17] wire [51:0] sfma_io_in_bits_req_in2_fractIn = io_req_bits_rs2_data_0[51:0]; // @[FPU.scala:275:20] wire [11:0] sfma_io_in_bits_req_in2_expIn = io_req_bits_rs2_data_0[63:52]; // @[FPU.scala:276:18] wire [75:0] _sfma_io_in_bits_req_in2_fractOut_T = {sfma_io_in_bits_req_in2_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in2_fractOut = _sfma_io_in_bits_req_in2_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in2_expOut_expCode = sfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in2_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in2_expOut_commonCase = _sfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in2_expOut_T = sfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in2_expOut_T_1 = sfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in2_expOut_T_2 = _sfma_io_in_bits_req_in2_expOut_T \| _sfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in2_expOut_T_3 = sfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_4 = {sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_5 = sfma_io_in_bits_req_in2_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in2_expOut = _sfma_io_in_bits_req_in2_expOut_T_2 ? _sfma_io_in_bits_req_in2_expOut_T_4 : _sfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in2_hi = {sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in2_floats_1 = {sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in2_T = sfma_io_in_bits_req_in2_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in2_T_1 = sfma_io_in_bits_req_in2_floats_0 \| _sfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in2 = {32'h0, _sfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:372:26] wire [1:0] sfma_io_in_bits_req_in3_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in3_floats_0 = {sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in3_prev_isbox = &_sfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in3_oks_0 = sfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in3_sign = io_req_bits_rs3_data_0[64]; // @[FPU.scala:274:17] wire [51:0] sfma_io_in_bits_req_in3_fractIn = io_req_bits_rs3_data_0[51:0]; // @[FPU.scala:275:20] wire [11:0] sfma_io_in_bits_req_in3_expIn = io_req_bits_rs3_data_0[63:52]; // @[FPU.scala:276:18] wire [75:0] _sfma_io_in_bits_req_in3_fractOut_T = {sfma_io_in_bits_req_in3_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in3_fractOut = _sfma_io_in_bits_req_in3_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in3_expOut_expCode = sfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in3_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in3_expOut_commonCase = _sfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in3_expOut_T = sfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in3_expOut_T_1 = sfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in3_expOut_T_2 = _sfma_io_in_bits_req_in3_expOut_T \| _sfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in3_expOut_T_3 = sfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_4 = {sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_5 = sfma_io_in_bits_req_in3_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in3_expOut = _sfma_io_in_bits_req_in3_expOut_T_2 ? _sfma_io_in_bits_req_in3_expOut_T_4 : _sfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in3_hi = {sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in3_floats_1 = {sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in3_T = sfma_io_in_bits_req_in3_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in3_T_1 = sfma_io_in_bits_req_in3_floats_0 \| _sfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in3 = _fp_decoder_io_sigs_swap23 ? sfma_io_in_bits_req_in2 : {32'h0, _sfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:372:26] assign sfma_io_in_bits_req_typ = _sfma_io_in_bits_req_typ_T; // @[util.scala:295:59] wire _sfma_io_in_bits_req_fmt_T_1 = ~_sfma_io_in_bits_req_fmt_T; // @[fpu.scala:197:{19,24}] assign sfma_io_in_bits_req_fmt = _sfma_io_in_bits_T ? 2'h0 : {1'h0, _sfma_io_in_bits_req_fmt_T_1}; // @[fpu.scala:188:19, :197:{13,19}, :198:{27,43}, :199:15] wire _fpiu_io_in_valid_T = _fp_decoder_io_sigs_fastpipe & _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26, :217:75] wire _fpiu_io_in_valid_T_1 = _fp_decoder_io_sigs_toint \| _fpiu_io_in_valid_T; // @[fpu.scala:182:26, :217:{54,75}] wire _fpiu_io_in_valid_T_2 = io_req_valid_0 & _fpiu_io_in_valid_T_1; // @[fpu.scala:170:7, :217:{36,54}] wire [64:0] _fpiu_io_in_bits_req_in1_T_4; // @[FPU.scala:369:10] wire [64:0] _fpiu_io_in_bits_req_in2_T_4; // @[FPU.scala:369:10] wire fpiu_io_in_bits_req_ldst; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_wen; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_ren1; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_ren2; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_ren3; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_swap12; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_swap23; // @[fpu.scala:188:19] wire [1:0] fpiu_io_in_bits_req_typeTagIn; // @[fpu.scala:188:19] wire [1:0] fpiu_io_in_bits_req_typeTagOut; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_fromint; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_toint; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_fastpipe; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_fma; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_div; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_sqrt; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_wflags; // @[fpu.scala:188:19] wire [1:0] fpiu_io_in_bits_req_fmaCmd; // @[fpu.scala:188:19] wire [1:0] fpiu_io_in_bits_req_typ; // @[fpu.scala:188:19] wire [1:0] fpiu_io_in_bits_req_fmt; // @[fpu.scala:188:19] wire [64:0] fpiu_io_in_bits_req_in1; // @[fpu.scala:188:19] wire [64:0] fpiu_io_in_bits_req_in2; // @[fpu.scala:188:19] wire [64:0] fpiu_io_in_bits_req_in3; // @[fpu.scala:188:19] wire [1:0] fpiu_io_in_bits_req_in1_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in1_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in1_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in1_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in1_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T \| _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in1_floats_0 = {fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in1_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in1_oks_0 = fpiu_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _fpiu_io_in_bits_req_in1_truncIdx_T; // @[package.scala:38:21] wire fpiu_io_in_bits_req_in1_truncIdx = _fpiu_io_in_bits_req_in1_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in1_T = fpiu_io_in_bits_req_in1_truncIdx; // @[package.scala:38:47, :39:86] wire _fpiu_io_in_bits_req_in1_T_1 = _fpiu_io_in_bits_req_in1_T \| fpiu_io_in_bits_req_in1_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _fpiu_io_in_bits_req_in1_truncIdx_T_1; // @[package.scala:38:21] wire fpiu_io_in_bits_req_in1_truncIdx_1 = _fpiu_io_in_bits_req_in1_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in1_T_2 = fpiu_io_in_bits_req_in1_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _fpiu_io_in_bits_req_in1_T_3 = _fpiu_io_in_bits_req_in1_T_2 ? io_req_bits_rs1_data_0 : fpiu_io_in_bits_req_in1_floats_0; // @[package.scala:39:{76,86}] assign _fpiu_io_in_bits_req_in1_T_4 = _fpiu_io_in_bits_req_in1_T_1 ? _fpiu_io_in_bits_req_in1_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in1 = _fpiu_io_in_bits_req_in1_T_4; // @[FPU.scala:369:10] wire [1:0] fpiu_io_in_bits_req_in2_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in2_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in2_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in2_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in2_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T \| _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in2_floats_0 = {fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in2_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in2_oks_0 = fpiu_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _fpiu_io_in_bits_req_in2_truncIdx_T; // @[package.scala:38:21] wire fpiu_io_in_bits_req_in2_truncIdx = _fpiu_io_in_bits_req_in2_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in2_T = fpiu_io_in_bits_req_in2_truncIdx; // @[package.scala:38:47, :39:86] wire _fpiu_io_in_bits_req_in2_T_1 = _fpiu_io_in_bits_req_in2_T \| fpiu_io_in_bits_req_in2_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _fpiu_io_in_bits_req_in2_truncIdx_T_1; // @[package.scala:38:21] wire fpiu_io_in_bits_req_in2_truncIdx_1 = _fpiu_io_in_bits_req_in2_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in2_T_2 = fpiu_io_in_bits_req_in2_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _fpiu_io_in_bits_req_in2_T_3 = _fpiu_io_in_bits_req_in2_T_2 ? io_req_bits_rs2_data_0 : fpiu_io_in_bits_req_in2_floats_0; // @[package.scala:39:{76,86}] assign _fpiu_io_in_bits_req_in2_T_4 = _fpiu_io_in_bits_req_in2_T_1 ? _fpiu_io_in_bits_req_in2_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in2 = _fpiu_io_in_bits_req_in2_T_4; // @[FPU.scala:369:10] wire [1:0] fpiu_io_in_bits_req_in3_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in3_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in3_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in3_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in3_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T \| _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in3_floats_0 = {fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in3_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in3_oks_0 = fpiu_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _fpiu_io_in_bits_req_in3_truncIdx_T; // @[package.scala:38:21] wire fpiu_io_in_bits_req_in3_truncIdx = _fpiu_io_in_bits_req_in3_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in3_T = fpiu_io_in_bits_req_in3_truncIdx; // @[package.scala:38:47, :39:86] wire _fpiu_io_in_bits_req_in3_T_1 = _fpiu_io_in_bits_req_in3_T \| fpiu_io_in_bits_req_in3_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _fpiu_io_in_bits_req_in3_truncIdx_T_1; // @[package.scala:38:21] wire fpiu_io_in_bits_req_in3_truncIdx_1 = _fpiu_io_in_bits_req_in3_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in3_T_2 = fpiu_io_in_bits_req_in3_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _fpiu_io_in_bits_req_in3_T_3 = _fpiu_io_in_bits_req_in3_T_2 ? io_req_bits_rs3_data_0 : fpiu_io_in_bits_req_in3_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in3_T_4 = _fpiu_io_in_bits_req_in3_T_1 ? _fpiu_io_in_bits_req_in3_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in3 = _fp_decoder_io_sigs_swap23 ? fpiu_io_in_bits_req_in2 : _fpiu_io_in_bits_req_in3_T_4; // @[FPU.scala:369:10] assign fpiu_io_in_bits_req_typ = _fpiu_io_in_bits_req_typ_T; // @[util.scala:295:59] wire _fpiu_io_in_bits_req_fmt_T_1 = ~_fpiu_io_in_bits_req_fmt_T; // @[fpu.scala:197:{19,24}] assign fpiu_io_in_bits_req_fmt = _fpiu_io_in_bits_T ? 2'h0 : {1'h0, _fpiu_io_in_bits_req_fmt_T_1}; // @[fpu.scala:188:19, :197:{13,19}, :198:{27,43}, :199:15] wire _fpiu_out_T = ~_fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26, :219:51] wire _fpiu_out_T_1 = _fpiu_io_in_valid_T_2 & _fpiu_out_T; // @[fpu.scala:217:36, :219:{48,51}] reg fpiu_out_REG; // @[fpu.scala:219:30] reg fpiu_out_pipe_v; // @[Valid.scala:141:24] reg fpiu_out_pipe_b_in_ldst; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_wen; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_ren1; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_ren2; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_ren3; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_swap12; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_swap23; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_fromint; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_toint; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_fastpipe; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_fma; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_div; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_sqrt; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_wflags; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_vec; // @[Valid.scala:142:26] reg [2:0] fpiu_out_pipe_b_in_rm; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_typ; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_fmt; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_b_in_in1; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_b_in_in2; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_b_in_in3; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_lt; // @[Valid.scala:142:26] reg [63:0] fpiu_out_pipe_b_store; // @[Valid.scala:142:26] reg [63:0] fpiu_out_pipe_b_toint; // @[Valid.scala:142:26] reg [4:0] fpiu_out_pipe_b_exc; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_v; // @[Valid.scala:141:24] reg fpiu_out_pipe_pipe_b_in_ldst; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_wen; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_ren1; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_ren2; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_ren3; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_swap12; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_swap23; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_fromint; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_toint; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_fastpipe; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_fma; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_div; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_sqrt; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_wflags; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_vec; // @[Valid.scala:142:26] reg [2:0] fpiu_out_pipe_pipe_b_in_rm; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_typ; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_fmt; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_pipe_b_in_in1; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_pipe_b_in_in2; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_pipe_b_in_in3; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_lt; // @[Valid.scala:142:26] reg [63:0] fpiu_out_pipe_pipe_b_store; // @[Valid.scala:142:26] reg [63:0] fpiu_out_pipe_pipe_b_toint; // @[Valid.scala:142:26] reg [4:0] fpiu_out_pipe_pipe_b_exc; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_pipe_v; // @[Valid.scala:141:24] wire fpiu_out_valid = fpiu_out_pipe_pipe_pipe_v; // @[Valid.scala:135:21, :141:24] reg fpiu_out_pipe_pipe_pipe_b_in_ldst; // @[Valid.scala:142:26] wire fpiu_out_bits_in_ldst = fpiu_out_pipe_pipe_pipe_b_in_ldst; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_wen; // @[Valid.scala:142:26] wire fpiu_out_bits_in_wen = fpiu_out_pipe_pipe_pipe_b_in_wen; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_ren1; // @[Valid.scala:142:26] wire fpiu_out_bits_in_ren1 = fpiu_out_pipe_pipe_pipe_b_in_ren1; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_ren2; // @[Valid.scala:142:26] wire fpiu_out_bits_in_ren2 = fpiu_out_pipe_pipe_pipe_b_in_ren2; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_ren3; // @[Valid.scala:142:26] wire fpiu_out_bits_in_ren3 = fpiu_out_pipe_pipe_pipe_b_in_ren3; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_swap12; // @[Valid.scala:142:26] wire fpiu_out_bits_in_swap12 = fpiu_out_pipe_pipe_pipe_b_in_swap12; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_swap23; // @[Valid.scala:142:26] wire fpiu_out_bits_in_swap23 = fpiu_out_pipe_pipe_pipe_b_in_swap23; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_typeTagIn = fpiu_out_pipe_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_typeTagOut = fpiu_out_pipe_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_fromint; // @[Valid.scala:142:26] wire fpiu_out_bits_in_fromint = fpiu_out_pipe_pipe_pipe_b_in_fromint; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_toint; // @[Valid.scala:142:26] wire fpiu_out_bits_in_toint = fpiu_out_pipe_pipe_pipe_b_in_toint; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_fastpipe; // @[Valid.scala:142:26] wire fpiu_out_bits_in_fastpipe = fpiu_out_pipe_pipe_pipe_b_in_fastpipe; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_fma; // @[Valid.scala:142:26] wire fpiu_out_bits_in_fma = fpiu_out_pipe_pipe_pipe_b_in_fma; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_div; // @[Valid.scala:142:26] wire fpiu_out_bits_in_div = fpiu_out_pipe_pipe_pipe_b_in_div; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_sqrt; // @[Valid.scala:142:26] wire fpiu_out_bits_in_sqrt = fpiu_out_pipe_pipe_pipe_b_in_sqrt; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_wflags; // @[Valid.scala:142:26] wire fpiu_out_bits_in_wflags = fpiu_out_pipe_pipe_pipe_b_in_wflags; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_vec; // @[Valid.scala:142:26] wire fpiu_out_bits_in_vec = fpiu_out_pipe_pipe_pipe_b_in_vec; // @[Valid.scala:135:21, :142:26] reg [2:0] fpiu_out_pipe_pipe_pipe_b_in_rm; // @[Valid.scala:142:26] wire [2:0] fpiu_out_bits_in_rm = fpiu_out_pipe_pipe_pipe_b_in_rm; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_fmaCmd = fpiu_out_pipe_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_typ; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_typ = fpiu_out_pipe_pipe_pipe_b_in_typ; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_fmt; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_fmt = fpiu_out_pipe_pipe_pipe_b_in_fmt; // @[Valid.scala:135:21, :142:26] reg [64:0] fpiu_out_pipe_pipe_pipe_b_in_in1; // @[Valid.scala:142:26] wire [64:0] fpiu_out_bits_in_in1 = fpiu_out_pipe_pipe_pipe_b_in_in1; // @[Valid.scala:135:21, :142:26] reg [64:0] fpiu_out_pipe_pipe_pipe_b_in_in2; // @[Valid.scala:142:26] wire [64:0] fpiu_out_bits_in_in2 = fpiu_out_pipe_pipe_pipe_b_in_in2; // @[Valid.scala:135:21, :142:26] reg [64:0] fpiu_out_pipe_pipe_pipe_b_in_in3; // @[Valid.scala:142:26] wire [64:0] fpiu_out_bits_in_in3 = fpiu_out_pipe_pipe_pipe_b_in_in3; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_lt; // @[Valid.scala:142:26] wire fpiu_out_bits_lt = fpiu_out_pipe_pipe_pipe_b_lt; // @[Valid.scala:135:21, :142:26] reg [63:0] fpiu_out_pipe_pipe_pipe_b_store; // @[Valid.scala:142:26] wire [63:0] fpiu_out_bits_store = fpiu_out_pipe_pipe_pipe_b_store; // @[Valid.scala:135:21, :142:26] reg [63:0] fpiu_out_pipe_pipe_pipe_b_toint; // @[Valid.scala:142:26] wire [63:0] fpiu_out_bits_toint = fpiu_out_pipe_pipe_pipe_b_toint; // @[Valid.scala:135:21, :142:26] reg [4:0] fpiu_out_pipe_pipe_pipe_b_exc; // @[Valid.scala:142:26] wire [4:0] fpiu_out_bits_exc = fpiu_out_pipe_pipe_pipe_b_exc; // @[Valid.scala:135:21, :142:26] wire [4:0] fpiu_result_exc = fpiu_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] fpiu_result_data; // @[fpu.scala:221:26] assign fpiu_result_data = {1'h0, fpiu_out_bits_toint}; // @[Valid.scala:135:21] wire _GEN_3 = io_req_valid_0 & _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:170:7, :182:26, :226:36] wire _fpmu_io_in_valid_T; // @[fpu.scala:226:36] assign _fpmu_io_in_valid_T = _GEN_3; // @[fpu.scala:226:36] wire _fpmu_double_T; // @[fpu.scala:229:39] assign _fpmu_double_T = _GEN_3; // @[fpu.scala:226:36, :229:39] reg fpmu_double_pipe_v; // @[Valid.scala:141:24] reg fpmu_double_pipe_b; // @[Valid.scala:142:26] reg fpmu_double_pipe_pipe_v; // @[Valid.scala:141:24] reg fpmu_double_pipe_pipe_b; // @[Valid.scala:142:26] reg fpmu_double_pipe_pipe_pipe_v; // @[Valid.scala:141:24] reg fpmu_double_pipe_pipe_pipe_b; // @[Valid.scala:142:26] reg fpmu_double_pipe_pipe_pipe_pipe_v; // @[Valid.scala:141:24] wire fpmu_double_pipe_pipe_pipe_pipe_out_valid = fpmu_double_pipe_pipe_pipe_pipe_v; // @[Valid.scala:135:21, :141:24] reg fpmu_double_pipe_pipe_pipe_pipe_b; // @[Valid.scala:142:26] wire fpmu_double_pipe_pipe_pipe_pipe_out_bits = fpmu_double_pipe_pipe_pipe_pipe_b; // @[Valid.scala:135:21, :142:26] wire _fpu_out_data_T_4 = fpmu_double_pipe_pipe_pipe_pipe_out_bits; // @[Valid.scala:135:21] wire _io_resp_valid_T = fpiu_out_valid \| _fpmu_io_out_valid; // @[Valid.scala:135:21] wire _io_resp_valid_T_1 = _io_resp_valid_T \| _sfma_io_out_valid; // @[fpu.scala:212:20, :232:35, :233:38] assign _io_resp_valid_T_2 = _io_resp_valid_T_1 \| _dfma_io_out_valid; // @[fpu.scala:208:20, :233:38, :234:38] assign io_resp_valid = _io_resp_valid_T_2; // @[fpu.scala:170:7, :234:38] wire _fpu_out_data_opts_bigger_swizzledNaN_T_1 = _dfma_io_out_bits_data[31]; // @[FPU.scala:340:8] wire _fpu_out_data_opts_bigger_swizzledNaN_T_2 = _dfma_io_out_bits_data[32]; // @[FPU.scala:342:8] wire [30:0] _fpu_out_data_opts_bigger_swizzledNaN_T_3 = _dfma_io_out_bits_data[30:0]; // @[FPU.scala:343:8] wire [20:0] fpu_out_data_opts_bigger_swizzledNaN_lo_hi = {20'hFFFFF, _fpu_out_data_opts_bigger_swizzledNaN_T_2}; // @[FPU.scala:336:26, :342:8] wire [51:0] fpu_out_data_opts_bigger_swizzledNaN_lo = {fpu_out_data_opts_bigger_swizzledNaN_lo_hi, _fpu_out_data_opts_bigger_swizzledNaN_T_3}; // @[FPU.scala:336:26, :343:8] wire [7:0] fpu_out_data_opts_bigger_swizzledNaN_hi_lo = {7'h7F, _fpu_out_data_opts_bigger_swizzledNaN_T_1}; // @[FPU.scala:336:26, :340:8] wire [12:0] fpu_out_data_opts_bigger_swizzledNaN_hi = {5'h1F, fpu_out_data_opts_bigger_swizzledNaN_hi_lo}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_swizzledNaN = {fpu_out_data_opts_bigger_swizzledNaN_hi, fpu_out_data_opts_bigger_swizzledNaN_lo}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger = fpu_out_data_opts_bigger_swizzledNaN; // @[FPU.scala:336:26, :344:8] wire [64:0] fpu_out_data_opts_0 = fpu_out_data_opts_bigger; // @[FPU.scala:344:8, :398:14] wire _fpu_out_data_opts_bigger_swizzledNaN_T_5 = _sfma_io_out_bits_data[31]; // @[FPU.scala:340:8] wire _fpu_out_data_opts_bigger_swizzledNaN_T_6 = _sfma_io_out_bits_data[32]; // @[FPU.scala:342:8] wire [30:0] _fpu_out_data_opts_bigger_swizzledNaN_T_7 = _sfma_io_out_bits_data[30:0]; // @[FPU.scala:343:8] wire [20:0] fpu_out_data_opts_bigger_swizzledNaN_lo_hi_1 = {20'hFFFFF, _fpu_out_data_opts_bigger_swizzledNaN_T_6}; // @[FPU.scala:336:26, :342:8] wire [51:0] fpu_out_data_opts_bigger_swizzledNaN_lo_1 = {fpu_out_data_opts_bigger_swizzledNaN_lo_hi_1, _fpu_out_data_opts_bigger_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8] wire [7:0] fpu_out_data_opts_bigger_swizzledNaN_hi_lo_1 = {7'h7F, _fpu_out_data_opts_bigger_swizzledNaN_T_5}; // @[FPU.scala:336:26, :340:8] wire [12:0] fpu_out_data_opts_bigger_swizzledNaN_hi_1 = {5'h1F, fpu_out_data_opts_bigger_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_swizzledNaN_1 = {fpu_out_data_opts_bigger_swizzledNaN_hi_1, fpu_out_data_opts_bigger_swizzledNaN_lo_1}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_1 = fpu_out_data_opts_bigger_swizzledNaN_1; // @[FPU.scala:336:26, :344:8] wire [64:0] fpu_out_data_opts_0_1 = fpu_out_data_opts_bigger_1; // @[FPU.scala:344:8, :398:14] wire [64:0] _fpu_out_data_T_3 = fpu_out_data_opts_0_1; // @[package.scala:39:76] wire _fpu_out_data_opts_bigger_swizzledNaN_T_9 = _fpmu_io_out_bits_data[31]; // @[FPU.scala:340:8] wire _fpu_out_data_opts_bigger_swizzledNaN_T_10 = _fpmu_io_out_bits_data[32]; // @[FPU.scala:342:8] wire [30:0] _fpu_out_data_opts_bigger_swizzledNaN_T_11 = _fpmu_io_out_bits_data[30:0]; // @[FPU.scala:343:8] wire [20:0] fpu_out_data_opts_bigger_swizzledNaN_lo_hi_2 = {20'hFFFFF, _fpu_out_data_opts_bigger_swizzledNaN_T_10}; // @[FPU.scala:336:26, :342:8] wire [51:0] fpu_out_data_opts_bigger_swizzledNaN_lo_2 = {fpu_out_data_opts_bigger_swizzledNaN_lo_hi_2, _fpu_out_data_opts_bigger_swizzledNaN_T_11}; // @[FPU.scala:336:26, :343:8] wire [7:0] fpu_out_data_opts_bigger_swizzledNaN_hi_lo_2 = {7'h7F, _fpu_out_data_opts_bigger_swizzledNaN_T_9}; // @[FPU.scala:336:26, :340:8] wire [12:0] fpu_out_data_opts_bigger_swizzledNaN_hi_2 = {5'h1F, fpu_out_data_opts_bigger_swizzledNaN_hi_lo_2}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_swizzledNaN_2 = {fpu_out_data_opts_bigger_swizzledNaN_hi_2, fpu_out_data_opts_bigger_swizzledNaN_lo_2}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_2 = fpu_out_data_opts_bigger_swizzledNaN_2; // @[FPU.scala:336:26, :344:8] wire [64:0] fpu_out_data_opts_0_2 = fpu_out_data_opts_bigger_2; // @[FPU.scala:344:8, :398:14] wire [64:0] _fpu_out_data_T_5 = _fpu_out_data_T_4 ? _fpmu_io_out_bits_data : fpu_out_data_opts_0_2; // @[package.scala:39:{76,86}] wire [64:0] _fpu_out_data_T_6 = fpiu_out_valid ? fpiu_result_data : _fpu_out_data_T_5; // @[Valid.scala:135:21] wire [64:0] _fpu_out_data_T_7 = _sfma_io_out_valid ? _fpu_out_data_T_3 : _fpu_out_data_T_6; // @[package.scala:39:76] wire [64:0] _fpu_out_data_T_1; // @[package.scala:39:76] assign fpu_out_data = _dfma_io_out_valid ? _fpu_out_data_T_1 : _fpu_out_data_T_7; // @[package.scala:39:76] assign io_resp_bits_data_0 = fpu_out_data; // @[fpu.scala:170:7, :237:8] wire [4:0] _fpu_out_exc_T = fpiu_out_valid ? fpiu_result_exc : _fpmu_io_out_bits_exc; // @[Valid.scala:135:21] wire [4:0] _fpu_out_exc_T_1 = _sfma_io_out_valid ? _sfma_io_out_bits_exc : _fpu_out_exc_T; // @[fpu.scala:212:20, :244:8, :245:8] assign fpu_out_exc = _dfma_io_out_valid ? _dfma_io_out_bits_exc : _fpu_out_exc_T_1; // @[fpu.scala:208:20, :243:8, :244:8] assign io_resp_bits_fflags_bits_flags_0 = fpu_out_exc; // @[fpu.scala:170:7, :243:8] always @(posedge clock) begin // @[fpu.scala:170:7] fpiu_out_REG <= _fpiu_out_T_1; // @[fpu.scala:219:{30,48}] if (fpiu_out_REG) begin // @[fpu.scala:219:30] fpiu_out_pipe_b_in_ldst <= _fpiu_io_out_bits_in_ldst; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_wen <= _fpiu_io_out_bits_in_wen; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_ren1 <= _fpiu_io_out_bits_in_ren1; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_ren2 <= _fpiu_io_out_bits_in_ren2; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_ren3 <= _fpiu_io_out_bits_in_ren3; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_swap12 <= _fpiu_io_out_bits_in_swap12; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_swap23 <= _fpiu_io_out_bits_in_swap23; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_typeTagIn <= _fpiu_io_out_bits_in_typeTagIn; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_typeTagOut <= _fpiu_io_out_bits_in_typeTagOut; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fromint <= _fpiu_io_out_bits_in_fromint; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_toint <= _fpiu_io_out_bits_in_toint; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fastpipe <= _fpiu_io_out_bits_in_fastpipe; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fma <= _fpiu_io_out_bits_in_fma; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_div <= _fpiu_io_out_bits_in_div; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_sqrt <= _fpiu_io_out_bits_in_sqrt; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_wflags <= _fpiu_io_out_bits_in_wflags; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_rm <= _fpiu_io_out_bits_in_rm; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fmaCmd <= _fpiu_io_out_bits_in_fmaCmd; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_typ <= _fpiu_io_out_bits_in_typ; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fmt <= _fpiu_io_out_bits_in_fmt; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_in1 <= _fpiu_io_out_bits_in_in1; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_in2 <= _fpiu_io_out_bits_in_in2; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_in3 <= _fpiu_io_out_bits_in_in3; // @[Valid.scala:142:26] fpiu_out_pipe_b_lt <= _fpiu_io_out_bits_lt; // @[Valid.scala:142:26] fpiu_out_pipe_b_store <= _fpiu_io_out_bits_store; // @[Valid.scala:142:26] fpiu_out_pipe_b_toint <= _fpiu_io_out_bits_toint; // @[Valid.scala:142:26] fpiu_out_pipe_b_exc <= _fpiu_io_out_bits_exc; // @[Valid.scala:142:26] end fpiu_out_pipe_b_in_vec <= ~fpiu_out_REG & fpiu_out_pipe_b_in_vec; // @[Valid.scala:142:26] if (fpiu_out_pipe_v) begin // @[Valid.scala:141:24] fpiu_out_pipe_pipe_b_in_ldst <= fpiu_out_pipe_b_in_ldst; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_wen <= fpiu_out_pipe_b_in_wen; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_ren1 <= fpiu_out_pipe_b_in_ren1; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_ren2 <= fpiu_out_pipe_b_in_ren2; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_ren3 <= fpiu_out_pipe_b_in_ren3; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_swap12 <= fpiu_out_pipe_b_in_swap12; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_swap23 <= fpiu_out_pipe_b_in_swap23; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_typeTagIn <= fpiu_out_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_typeTagOut <= fpiu_out_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fromint <= fpiu_out_pipe_b_in_fromint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_toint <= fpiu_out_pipe_b_in_toint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fastpipe <= fpiu_out_pipe_b_in_fastpipe; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fma <= fpiu_out_pipe_b_in_fma; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_div <= fpiu_out_pipe_b_in_div; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_sqrt <= fpiu_out_pipe_b_in_sqrt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_wflags <= fpiu_out_pipe_b_in_wflags; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_vec <= fpiu_out_pipe_b_in_vec; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_rm <= fpiu_out_pipe_b_in_rm; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fmaCmd <= fpiu_out_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_typ <= fpiu_out_pipe_b_in_typ; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fmt <= fpiu_out_pipe_b_in_fmt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_in1 <= fpiu_out_pipe_b_in_in1; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_in2 <= fpiu_out_pipe_b_in_in2; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_in3 <= fpiu_out_pipe_b_in_in3; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_lt <= fpiu_out_pipe_b_lt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_store <= fpiu_out_pipe_b_store; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_toint <= fpiu_out_pipe_b_toint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_exc <= fpiu_out_pipe_b_exc; // @[Valid.scala:142:26] end if (fpiu_out_pipe_pipe_v) begin // @[Valid.scala:141:24] fpiu_out_pipe_pipe_pipe_b_in_ldst <= fpiu_out_pipe_pipe_b_in_ldst; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_wen <= fpiu_out_pipe_pipe_b_in_wen; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_ren1 <= fpiu_out_pipe_pipe_b_in_ren1; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_ren2 <= fpiu_out_pipe_pipe_b_in_ren2; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_ren3 <= fpiu_out_pipe_pipe_b_in_ren3; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_swap12 <= fpiu_out_pipe_pipe_b_in_swap12; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_swap23 <= fpiu_out_pipe_pipe_b_in_swap23; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_typeTagIn <= fpiu_out_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_typeTagOut <= fpiu_out_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fromint <= fpiu_out_pipe_pipe_b_in_fromint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_toint <= fpiu_out_pipe_pipe_b_in_toint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fastpipe <= fpiu_out_pipe_pipe_b_in_fastpipe; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fma <= fpiu_out_pipe_pipe_b_in_fma; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_div <= fpiu_out_pipe_pipe_b_in_div; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_sqrt <= fpiu_out_pipe_pipe_b_in_sqrt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_wflags <= fpiu_out_pipe_pipe_b_in_wflags; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_vec <= fpiu_out_pipe_pipe_b_in_vec; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_rm <= fpiu_out_pipe_pipe_b_in_rm; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fmaCmd <= fpiu_out_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_typ <= fpiu_out_pipe_pipe_b_in_typ; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fmt <= fpiu_out_pipe_pipe_b_in_fmt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_in1 <= fpiu_out_pipe_pipe_b_in_in1; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_in2 <= fpiu_out_pipe_pipe_b_in_in2; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_in3 <= fpiu_out_pipe_pipe_b_in_in3; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_lt <= fpiu_out_pipe_pipe_b_lt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_store <= fpiu_out_pipe_pipe_b_store; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_toint <= fpiu_out_pipe_pipe_b_toint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_exc <= fpiu_out_pipe_pipe_b_exc; // @[Valid.scala:142:26] end if (_fpmu_double_T) // @[fpu.scala:229:39] fpmu_double_pipe_b <= _fpmu_double_T_1; // @[Valid.scala:142:26] if (fpmu_double_pipe_v) // @[Valid.scala:141:24] fpmu_double_pipe_pipe_b <= fpmu_double_pipe_b; // @[Valid.scala:142:26] if (fpmu_double_pipe_pipe_v) // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_b <= fpmu_double_pipe_pipe_b; // @[Valid.scala:142:26] if (fpmu_double_pipe_pipe_pipe_v) // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_pipe_b <= fpmu_double_pipe_pipe_pipe_b; // @[Valid.scala:142:26] if (reset) begin // @[fpu.scala:170:7] fpiu_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpiu_out_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpiu_out_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpmu_double_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[fpu.scala:170:7] fpiu_out_pipe_v <= fpiu_out_REG; // @[Valid.scala:141:24] fpiu_out_pipe_pipe_v <= fpiu_out_pipe_v; // @[Valid.scala:141:24] fpiu_out_pipe_pipe_pipe_v <= fpiu_out_pipe_pipe_v; // @[Valid.scala:141:24] fpmu_double_pipe_v <= _fpmu_double_T; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_v <= fpmu_double_pipe_v; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_v <= fpmu_double_pipe_pipe_v; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_pipe_v <= fpmu_double_pipe_pipe_pipe_v; // @[Valid.scala:141:24] end always @(posedge) UOPCodeFPUDecoder_1 fp_decoder ( // @[fpu.scala:182:26] .clock (clock), .reset (reset), .io_uopc (io_req_bits_uop_uopc_0), // @[fpu.scala:170:7] .io_sigs_ldst (_fp_decoder_io_sigs_ldst), .io_sigs_wen (_fp_decoder_io_sigs_wen), .io_sigs_ren1 (_fp_decoder_io_sigs_ren1), .io_sigs_ren2 (_fp_decoder_io_sigs_ren2), .io_sigs_ren3 (_fp_decoder_io_sigs_ren3), .io_sigs_swap12 (_fp_decoder_io_sigs_swap12), .io_sigs_swap23 (_fp_decoder_io_sigs_swap23), .io_sigs_typeTagIn (_fp_decoder_io_sigs_typeTagIn), .io_sigs_typeTagOut (_fp_decoder_io_sigs_typeTagOut), .io_sigs_fromint (_fp_decoder_io_sigs_fromint), .io_sigs_toint (_fp_decoder_io_sigs_toint), .io_sigs_fastpipe (_fp_decoder_io_sigs_fastpipe), .io_sigs_fma (_fp_decoder_io_sigs_fma), .io_sigs_div (_fp_decoder_io_sigs_div), .io_sigs_sqrt (_fp_decoder_io_sigs_sqrt), .io_sigs_wflags (_fp_decoder_io_sigs_wflags) ); // @[fpu.scala:182:26] assign dfma_io_in_bits_req_ldst = _fp_decoder_io_sigs_ldst; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_wen = _fp_decoder_io_sigs_wen; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_ren1 = _fp_decoder_io_sigs_ren1; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_ren2 = _fp_decoder_io_sigs_ren2; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_ren3 = _fp_decoder_io_sigs_ren3; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_swap12 = _fp_decoder_io_sigs_swap12; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_swap23 = _fp_decoder_io_sigs_swap23; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_typeTagIn = _fp_decoder_io_sigs_typeTagIn; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_typeTagOut = _fp_decoder_io_sigs_typeTagOut; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_fromint = _fp_decoder_io_sigs_fromint; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_toint = _fp_decoder_io_sigs_toint; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_fastpipe = _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_fma = _fp_decoder_io_sigs_fma; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_div = _fp_decoder_io_sigs_div; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_sqrt = _fp_decoder_io_sigs_sqrt; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_wflags = _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_ldst = _fp_decoder_io_sigs_ldst; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_wen = _fp_decoder_io_sigs_wen; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_ren1 = _fp_decoder_io_sigs_ren1; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_ren2 = _fp_decoder_io_sigs_ren2; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_ren3 = _fp_decoder_io_sigs_ren3; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_swap12 = _fp_decoder_io_sigs_swap12; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_swap23 = _fp_decoder_io_sigs_swap23; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_typeTagIn = _fp_decoder_io_sigs_typeTagIn; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_typeTagOut = _fp_decoder_io_sigs_typeTagOut; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_fromint = _fp_decoder_io_sigs_fromint; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_toint = _fp_decoder_io_sigs_toint; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_fastpipe = _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_fma = _fp_decoder_io_sigs_fma; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_div = _fp_decoder_io_sigs_div; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_sqrt = _fp_decoder_io_sigs_sqrt; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_wflags = _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_ldst = _fp_decoder_io_sigs_ldst; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_wen = _fp_decoder_io_sigs_wen; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_ren1 = _fp_decoder_io_sigs_ren1; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_ren2 = _fp_decoder_io_sigs_ren2; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_ren3 = _fp_decoder_io_sigs_ren3; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_swap12 = _fp_decoder_io_sigs_swap12; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_swap23 = _fp_decoder_io_sigs_swap23; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_typeTagIn = _fp_decoder_io_sigs_typeTagIn; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_typeTagOut = _fp_decoder_io_sigs_typeTagOut; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_fromint = _fp_decoder_io_sigs_fromint; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_toint = _fp_decoder_io_sigs_toint; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_fastpipe = _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_fma = _fp_decoder_io_sigs_fma; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_div = _fp_decoder_io_sigs_div; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_sqrt = _fp_decoder_io_sigs_sqrt; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_wflags = _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26, :188:19] assign _fpiu_io_in_bits_req_in1_truncIdx_T = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21] assign _fpiu_io_in_bits_req_in1_truncIdx_T_1 = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21] assign _fpiu_io_in_bits_req_in2_truncIdx_T = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21] assign _fpiu_io_in_bits_req_in2_truncIdx_T_1 = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21] assign _fpiu_io_in_bits_req_in3_truncIdx_T = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21] assign _fpiu_io_in_bits_req_in3_truncIdx_T_1 = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21] FPUFMAPipe_l4_f64 dfma ( // @[fpu.scala:208:20] .clock (clock), .reset (reset), .io_in_valid (_dfma_io_in_valid_T_2), // @[fpu.scala:209:51] .io_in_bits_ldst (dfma_io_in_bits_req_ldst), // @[fpu.scala:188:19] .io_in_bits_wen (dfma_io_in_bits_req_wen), // @[fpu.scala:188:19] .io_in_bits_ren1 (dfma_io_in_bits_req_ren1), // @[fpu.scala:188:19] .io_in_bits_ren2 (dfma_io_in_bits_req_ren2), // @[fpu.scala:188:19] .io_in_bits_ren3 (dfma_io_in_bits_req_ren3), // @[fpu.scala:188:19] .io_in_bits_swap12 (dfma_io_in_bits_req_swap12), // @[fpu.scala:188:19] .io_in_bits_swap23 (dfma_io_in_bits_req_swap23), // @[fpu.scala:188:19] .io_in_bits_typeTagIn (dfma_io_in_bits_req_typeTagIn), // @[fpu.scala:188:19] .io_in_bits_typeTagOut (dfma_io_in_bits_req_typeTagOut), // @[fpu.scala:188:19] .io_in_bits_fromint (dfma_io_in_bits_req_fromint), // @[fpu.scala:188:19] .io_in_bits_toint (dfma_io_in_bits_req_toint), // @[fpu.scala:188:19] .io_in_bits_fastpipe (dfma_io_in_bits_req_fastpipe), // @[fpu.scala:188:19] .io_in_bits_fma (dfma_io_in_bits_req_fma), // @[fpu.scala:188:19] .io_in_bits_div (dfma_io_in_bits_req_div), // @[fpu.scala:188:19] .io_in_bits_sqrt (dfma_io_in_bits_req_sqrt), // @[fpu.scala:188:19] .io_in_bits_wflags (dfma_io_in_bits_req_wflags), // @[fpu.scala:188:19] .io_in_bits_rm (dfma_io_in_bits_req_rm), // @[fpu.scala:188:19] .io_in_bits_fmaCmd (dfma_io_in_bits_req_fmaCmd), // @[fpu.scala:188:19] .io_in_bits_typ (dfma_io_in_bits_req_typ), // @[fpu.scala:188:19] .io_in_bits_fmt (dfma_io_in_bits_req_fmt), // @[fpu.scala:188:19] .io_in_bits_in1 (dfma_io_in_bits_req_in1), // @[fpu.scala:188:19] .io_in_bits_in2 (dfma_io_in_bits_req_in2), // @[fpu.scala:188:19] .io_in_bits_in3 (dfma_io_in_bits_req_in3), // @[fpu.scala:188:19] .io_out_valid (_dfma_io_out_valid), .io_out_bits_data (_dfma_io_out_bits_data), .io_out_bits_exc (_dfma_io_out_bits_exc) ); // @[fpu.scala:208:20] assign _fpu_out_data_T_1 = _dfma_io_out_bits_data; // @[package.scala:39:76] FMADecoder dfma_io_in_bits_fma_decoder ( // @[fpu.scala:202:29] .clock (clock), .reset (reset), .io_uopc (io_req_bits_uop_uopc_0), // @[fpu.scala:170:7] .io_cmd (dfma_io_in_bits_req_fmaCmd) ); // @[fpu.scala:202:29] FPUFMAPipe_l4_f32 sfma ( // @[fpu.scala:212:20] .clock (clock), .reset (reset), .io_in_valid (_sfma_io_in_valid_T_2), // @[fpu.scala:213:51] .io_in_bits_ldst (sfma_io_in_bits_req_ldst), // @[fpu.scala:188:19] .io_in_bits_wen (sfma_io_in_bits_req_wen), // @[fpu.scala:188:19] .io_in_bits_ren1 (sfma_io_in_bits_req_ren1), // @[fpu.scala:188:19] .io_in_bits_ren2 (sfma_io_in_bits_req_ren2), // @[fpu.scala:188:19] .io_in_bits_ren3 (sfma_io_in_bits_req_ren3), // @[fpu.scala:188:19] .io_in_bits_swap12 (sfma_io_in_bits_req_swap12), // @[fpu.scala:188:19] .io_in_bits_swap23 (sfma_io_in_bits_req_swap23), // @[fpu.scala:188:19] .io_in_bits_typeTagIn (sfma_io_in_bits_req_typeTagIn), // @[fpu.scala:188:19] .io_in_bits_typeTagOut (sfma_io_in_bits_req_typeTagOut), // @[fpu.scala:188:19] .io_in_bits_fromint (sfma_io_in_bits_req_fromint), // @[fpu.scala:188:19] .io_in_bits_toint (sfma_io_in_bits_req_toint), // @[fpu.scala:188:19] .io_in_bits_fastpipe (sfma_io_in_bits_req_fastpipe), // @[fpu.scala:188:19] .io_in_bits_fma (sfma_io_in_bits_req_fma), // @[fpu.scala:188:19] .io_in_bits_div (sfma_io_in_bits_req_div), // @[fpu.scala:188:19] .io_in_bits_sqrt (sfma_io_in_bits_req_sqrt), // @[fpu.scala:188:19] .io_in_bits_wflags (sfma_io_in_bits_req_wflags), // @[fpu.scala:188:19] .io_in_bits_rm (sfma_io_in_bits_req_rm), // @[fpu.scala:188:19] .io_in_bits_fmaCmd (sfma_io_in_bits_req_fmaCmd), // @[fpu.scala:188:19] .io_in_bits_typ (sfma_io_in_bits_req_typ), // @[fpu.scala:188:19] .io_in_bits_fmt (sfma_io_in_bits_req_fmt), // @[fpu.scala:188:19] .io_in_bits_in1 (sfma_io_in_bits_req_in1), // @[fpu.scala:188:19] .io_in_bits_in2 (sfma_io_in_bits_req_in2), // @[fpu.scala:188:19] .io_in_bits_in3 (sfma_io_in_bits_req_in3), // @[fpu.scala:188:19] .io_out_valid (_sfma_io_out_valid), .io_out_bits_data (_sfma_io_out_bits_data), .io_out_bits_exc (_sfma_io_out_bits_exc) ); // @[fpu.scala:212:20] FMADecoder_1 sfma_io_in_bits_fma_decoder ( // @[fpu.scala:202:29] .clock (clock), .reset (reset), .io_uopc (io_req_bits_uop_uopc_0), // @[fpu.scala:170:7] .io_cmd (sfma_io_in_bits_req_fmaCmd) ); // @[fpu.scala:202:29] FPToInt fpiu ( // @[fpu.scala:216:20] .clock (clock), .reset (reset), .io_in_valid (_fpiu_io_in_valid_T_2), // @[fpu.scala:217:36] .io_in_bits_ldst (fpiu_io_in_bits_req_ldst), // @[fpu.scala:188:19] .io_in_bits_wen (fpiu_io_in_bits_req_wen), // @[fpu.scala:188:19] .io_in_bits_ren1 (fpiu_io_in_bits_req_ren1), // @[fpu.scala:188:19] .io_in_bits_ren2 (fpiu_io_in_bits_req_ren2), // @[fpu.scala:188:19] .io_in_bits_ren3 (fpiu_io_in_bits_req_ren3), // @[fpu.scala:188:19] .io_in_bits_swap12 (fpiu_io_in_bits_req_swap12), // @[fpu.scala:188:19] .io_in_bits_swap23 (fpiu_io_in_bits_req_swap23), // @[fpu.scala:188:19] .io_in_bits_typeTagIn (fpiu_io_in_bits_req_typeTagIn), // @[fpu.scala:188:19] .io_in_bits_typeTagOut (fpiu_io_in_bits_req_typeTagOut), // @[fpu.scala:188:19] .io_in_bits_fromint (fpiu_io_in_bits_req_fromint), // @[fpu.scala:188:19] .io_in_bits_toint (fpiu_io_in_bits_req_toint), // @[fpu.scala:188:19] .io_in_bits_fastpipe (fpiu_io_in_bits_req_fastpipe), // @[fpu.scala:188:19] .io_in_bits_fma (fpiu_io_in_bits_req_fma), // @[fpu.scala:188:19] .io_in_bits_div (fpiu_io_in_bits_req_div), // @[fpu.scala:188:19] .io_in_bits_sqrt (fpiu_io_in_bits_req_sqrt), // @[fpu.scala:188:19] .io_in_bits_wflags (fpiu_io_in_bits_req_wflags), // @[fpu.scala:188:19] .io_in_bits_rm (fpiu_io_in_bits_req_rm), // @[fpu.scala:188:19] .io_in_bits_fmaCmd (fpiu_io_in_bits_req_fmaCmd), // @[fpu.scala:188:19] .io_in_bits_typ (fpiu_io_in_bits_req_typ), // @[fpu.scala:188:19] .io_in_bits_fmt (fpiu_io_in_bits_req_fmt), // @[fpu.scala:188:19] .io_in_bits_in1 (fpiu_io_in_bits_req_in1), // @[fpu.scala:188:19] .io_in_bits_in2 (fpiu_io_in_bits_req_in2), // @[fpu.scala:188:19] .io_in_bits_in3 (fpiu_io_in_bits_req_in3), // @[fpu.scala:188:19] .io_out_bits_in_ldst (_fpiu_io_out_bits_in_ldst), .io_out_bits_in_wen (_fpiu_io_out_bits_in_wen), .io_out_bits_in_ren1 (_fpiu_io_out_bits_in_ren1), .io_out_bits_in_ren2 (_fpiu_io_out_bits_in_ren2), .io_out_bits_in_ren3 (_fpiu_io_out_bits_in_ren3), .io_out_bits_in_swap12 (_fpiu_io_out_bits_in_swap12), .io_out_bits_in_swap23 (_fpiu_io_out_bits_in_swap23), .io_out_bits_in_typeTagIn (_fpiu_io_out_bits_in_typeTagIn), .io_out_bits_in_typeTagOut (_fpiu_io_out_bits_in_typeTagOut), .io_out_bits_in_fromint (_fpiu_io_out_bits_in_fromint), .io_out_bits_in_toint (_fpiu_io_out_bits_in_toint), .io_out_bits_in_fastpipe (_fpiu_io_out_bits_in_fastpipe), .io_out_bits_in_fma (_fpiu_io_out_bits_in_fma), .io_out_bits_in_div (_fpiu_io_out_bits_in_div), .io_out_bits_in_sqrt (_fpiu_io_out_bits_in_sqrt), .io_out_bits_in_wflags (_fpiu_io_out_bits_in_wflags), .io_out_bits_in_rm (_fpiu_io_out_bits_in_rm), .io_out_bits_in_fmaCmd (_fpiu_io_out_bits_in_fmaCmd), .io_out_bits_in_typ (_fpiu_io_out_bits_in_typ), .io_out_bits_in_fmt (_fpiu_io_out_bits_in_fmt), .io_out_bits_in_in1 (_fpiu_io_out_bits_in_in1), .io_out_bits_in_in2 (_fpiu_io_out_bits_in_in2), .io_out_bits_in_in3 (_fpiu_io_out_bits_in_in3), .io_out_bits_lt (_fpiu_io_out_bits_lt), .io_out_bits_store (_fpiu_io_out_bits_store), .io_out_bits_toint (_fpiu_io_out_bits_toint), .io_out_bits_exc (_fpiu_io_out_bits_exc) ); // @[fpu.scala:216:20] FMADecoder_2 fpiu_io_in_bits_fma_decoder ( // @[fpu.scala:202:29] .clock (clock), .reset (reset), .io_uopc (io_req_bits_uop_uopc_0), // @[fpu.scala:170:7] .io_cmd (fpiu_io_in_bits_req_fmaCmd) ); // @[fpu.scala:202:29] FPToFP fpmu ( // @[fpu.scala:225:20] .clock (clock), .reset (reset), .io_in_valid (_fpmu_io_in_valid_T), // @[fpu.scala:226:36] .io_in_bits_ldst (fpiu_io_in_bits_req_ldst), // @[fpu.scala:188:19] .io_in_bits_wen (fpiu_io_in_bits_req_wen), // @[fpu.scala:188:19] .io_in_bits_ren1 (fpiu_io_in_bits_req_ren1), // @[fpu.scala:188:19] .io_in_bits_ren2 (fpiu_io_in_bits_req_ren2), // @[fpu.scala:188:19] .io_in_bits_ren3 (fpiu_io_in_bits_req_ren3), // @[fpu.scala:188:19] .io_in_bits_swap12 (fpiu_io_in_bits_req_swap12), // @[fpu.scala:188:19] .io_in_bits_swap23 (fpiu_io_in_bits_req_swap23), // @[fpu.scala:188:19] .io_in_bits_typeTagIn (fpiu_io_in_bits_req_typeTagIn), // @[fpu.scala:188:19] .io_in_bits_typeTagOut (fpiu_io_in_bits_req_typeTagOut), // @[fpu.scala:188:19] .io_in_bits_fromint (fpiu_io_in_bits_req_fromint), // @[fpu.scala:188:19] .io_in_bits_toint (fpiu_io_in_bits_req_toint), // @[fpu.scala:188:19] .io_in_bits_fastpipe (fpiu_io_in_bits_req_fastpipe), // @[fpu.scala:188:19] .io_in_bits_fma (fpiu_io_in_bits_req_fma), // @[fpu.scala:188:19] .io_in_bits_div (fpiu_io_in_bits_req_div), // @[fpu.scala:188:19] .io_in_bits_sqrt (fpiu_io_in_bits_req_sqrt), // @[fpu.scala:188:19] .io_in_bits_wflags (fpiu_io_in_bits_req_wflags), // @[fpu.scala:188:19] .io_in_bits_rm (fpiu_io_in_bits_req_rm), // @[fpu.scala:188:19] .io_in_bits_fmaCmd (fpiu_io_in_bits_req_fmaCmd), // @[fpu.scala:188:19] .io_in_bits_typ (fpiu_io_in_bits_req_typ), // @[fpu.scala:188:19] .io_in_bits_fmt (fpiu_io_in_bits_req_fmt), // @[fpu.scala:188:19] .io_in_bits_in1 (fpiu_io_in_bits_req_in1), // @[fpu.scala:188:19] .io_in_bits_in2 (fpiu_io_in_bits_req_in2), // @[fpu.scala:188:19] .io_in_bits_in3 (fpiu_io_in_bits_req_in3), // @[fpu.scala:188:19] .io_out_valid (_fpmu_io_out_valid), .io_out_bits_data (_fpmu_io_out_bits_data), .io_out_bits_exc (_fpmu_io_out_bits_exc), .io_lt (_fpiu_io_out_bits_lt) // @[fpu.scala:216:20] ); // @[fpu.scala:225:20] assign io_resp_bits_data = io_resp_bits_data_0; // @[fpu.scala:170:7] assign io_resp_bits_fflags_valid = io_resp_bits_fflags_valid_0; // @[fpu.scala:170:7] assign io_resp_bits_fflags_bits_flags = io_resp_bits_fflags_bits_flags_0; // @[fpu.scala:170:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DspBlock.scala: // SPDX-License-Identifier: Apache-2.0 package dspblocks import chisel3._ import freechips.rocketchip.amba.ahb._ import freechips.rocketchip.amba.apb._ import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.amba.axi4stream._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.tilelink._ /** * Base trait for basic unit of computation * @tparam D Down parameter type * @tparam U Up parameter type * @tparam EO Edge-out parameter type * @tparam EI Edge-in parameter type * @tparam B Bundle parameter type / trait DspBlock[D, U, EO, EI, B <: Data] extends LazyModule { /* * Diplomatic node for AXI4-Stream interfaces / val streamNode: AXI4StreamNodeHandle /* * Diplmatic node for memory interface * Some blocks might not need memory mapping, so this is an Option[] / val mem: Option[MixedNode[D, U, EI, B, D, U, EO, B]] } /* * Mixin for DspBlock to make them standalone (i.e., you can build them as a top-level module). * This is especially important for testing. * * Adds BundleBridges to the input and output sides of the AXI4Stream node * @tparam D Down parameter type * @tparam U Up parameter type * @tparam EO Edge-out parameter type * @tparam EI Edge-in parameter type * @tparam B Bundle parameter type / trait StandaloneBlock[D, U, EO, EI, B <: Data] extends DspBlock[D, U, EO, EI, B] { val ioInNode = BundleBridgeSource(() => new AXI4StreamBundle(AXI4StreamBundleParameters(n = 8))) val ioOutNode = BundleBridgeSink[AXI4StreamBundle]() ioOutNode := AXI4StreamToBundleBridge(AXI4StreamSlaveParameters()) := streamNode := BundleBridgeToAXI4Stream(AXI4StreamMasterParameters()) := ioInNode val in = InModuleBody { ioInNode.makeIO() } val out = InModuleBody { ioOutNode.makeIO() } } /* * AXI4-flavor of standalone block. Adds BundleBridge AXI4 interface. / trait AXI4StandaloneBlock extends StandaloneBlock[ AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4EdgeParameters, AXI4Bundle ] { def standaloneParams = AXI4BundleParameters(addrBits = 64, dataBits = 64, idBits = 1) val ioMem = mem.map { m => { val ioMemNode = BundleBridgeSource(() => AXI4Bundle(standaloneParams)) m := BundleBridgeToAXI4(AXI4MasterPortParameters(Seq(AXI4MasterParameters("bundleBridgeToAXI4")))) := ioMemNode val ioMem = InModuleBody { ioMemNode.makeIO() } ioMem } } } /* * APB-flavor of standalone block. Adds BundleBridge APB interface. / trait APBStandaloneBlock extends StandaloneBlock[ APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBEdgeParameters, APBBundle ] { def standaloneParams = APBBundleParameters(addrBits = 64, dataBits = 64) val ioMem = mem.map { m => { val ioMemNode = BundleBridgeSource(() => APBBundle(standaloneParams)) m := BundleBridgeToAPB(APBMasterPortParameters(Seq(APBMasterParameters("bundleBridgeToAPB")))) := ioMemNode val ioMem = InModuleBody { ioMemNode.makeIO() } ioMem } } } /* * TL-flavor of standalone block. Adds BundleBridge TL interface. / trait TLStandaloneBlock extends StandaloneBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def standaloneParams = TLBundleParameters( addressBits = 64, dataBits = 64, sourceBits = 1, sinkBits = 1, sizeBits = 6, echoFields = Seq(), requestFields = Seq(), responseFields = Seq(), hasBCE = false ) val ioMem = mem.map { m => { val ioMemNode = BundleBridgeSource(() => TLBundle(standaloneParams)) m := BundleBridgeToTL(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1("bundleBridgeToTL")))) := ioMemNode val ioMem = InModuleBody { ioMemNode.makeIO() } ioMem } } } trait TLDspBlock extends DspBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle] trait TLDspBlockWithBus extends TLDspBlock { val bus = LazyModule(new TLXbar) val mem = Some(bus.node) } trait APBDspBlock extends DspBlock[APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBEdgeParameters, APBBundle] trait APBDspBlockWithBus extends APBDspBlock { val bus = LazyModule(new APBFanout) val mem = Some(bus.node) } object AXI4DspBlock { type AXI4Node = MixedNode[ AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4Bundle, AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4Bundle ] } trait AXI4DspBlock extends DspBlock[ AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4EdgeParameters, AXI4Bundle ] trait AXI4DspBlockWithBus extends AXI4DspBlock { val bus = LazyModule(new AXI4Xbar) val mem = Some(bus.node) } trait AHBSlaveDspBlock extends DspBlock[ AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBEdgeParameters, AHBSlaveBundle ] trait AHBSlaveDspBlockWithBus extends AHBSlaveDspBlock { val bus = LazyModule(new AHBFanout) val mem = Some(bus.node) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File StreamingPassthrough.scala: //// See LICENSE for license details. // package chipyard.example import chisel3._ import chisel3.{Bundle, Module} import chisel3.util._ import dspblocks._ import dsptools.numbers._ import freechips.rocketchip.amba.axi4stream._ import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ // Simple passthrough to use as testbed sanity check // StreamingPassthrough params case class StreamingPassthroughParams( writeAddress: BigInt = 0x2200, readAddress: BigInt = 0x2300, depth: Int ) // StreamingPassthrough key case object StreamingPassthroughKey extends Field[Option[StreamingPassthroughParams]](None) class StreamingPassthroughBundle[T<:Data:Ring](proto: T) extends Bundle { val data: T = proto.cloneType } object StreamingPassthroughBundle { def apply[T<:Data:Ring](proto: T): StreamingPassthroughBundle[T] = new StreamingPassthroughBundle(proto) } class StreamingPassthroughIO[T<:Data:Ring](proto: T) extends Bundle { val in = Flipped(Decoupled(StreamingPassthroughBundle(proto))) val out = Decoupled(StreamingPassthroughBundle(proto)) } object StreamingPassthroughIO { def apply[T<:Data:Ring](proto: T): StreamingPassthroughIO[T] = new StreamingPassthroughIO(proto) } class StreamingPassthrough[T<:Data:Ring](proto: T) extends Module { val io = IO(StreamingPassthroughIO(proto)) io.in.ready := io.out.ready io.out.bits.data := io.in.bits.data io.out.valid := io.in.valid } /* * Make DspBlock wrapper for StreamingPassthrough * @param cordicParams parameters for cordic * @param ev$1 * @param ev$2 * @param ev$3 * @param p * @tparam D * @tparam U * @tparam EO * @tparam EI * @tparam B * @tparam T Type parameter for passthrough, i.e. FixedPoint or DspReal / abstract class StreamingPassthroughBlock[D, U, EO, EI, B<:Data, T<:Data:Ring] ( proto: T )(implicit p: Parameters) extends DspBlock[D, U, EO, EI, B] { val streamNode = AXI4StreamIdentityNode() val mem = None lazy val module = new LazyModuleImp(this) { require(streamNode.in.length == 1) require(streamNode.out.length == 1) val in = streamNode.in.head._1 val out = streamNode.out.head._1 // instantiate passthrough val passthrough = Module(new StreamingPassthrough(proto)) // Pass ready and valid from read queue to write queue in.ready := passthrough.io.in.ready passthrough.io.in.valid := in.valid // cast UInt to T passthrough.io.in.bits := in.bits.data.asTypeOf(StreamingPassthroughBundle(proto)) passthrough.io.out.ready := out.ready out.valid := passthrough.io.out.valid // cast T to UInt out.bits.data := passthrough.io.out.bits.asUInt } } /* * TLDspBlock specialization of StreamingPassthrough * @param cordicParams parameters for passthrough * @param ev$1 * @param ev$2 * @param ev$3 * @param p * @tparam T Type parameter for passthrough data type / class TLStreamingPassthroughBlock[T<:Data:Ring] ( val proto: T )(implicit p: Parameters) extends StreamingPassthroughBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle, T](proto) with TLDspBlock /* * A chain of queues acting as our MMIOs with the passthrough module in between them. * @param depth depth of queues * @param ev$1 * @param ev$2 * @param ev$3 * @param p * @tparam T Type parameter for passthrough, i.e. FixedPoint or DspReal / class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughParams, proto: T)(implicit p: Parameters) extends TLChain(Seq( TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))(_), { implicit p: Parameters => { val streamingPassthrough = LazyModule(new TLStreamingPassthroughBlock(proto)) streamingPassthrough }}, TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))(_) )) trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem => val passthrough = p(StreamingPassthroughKey) match { case Some(params) => { val pbus = locateTLBusWrapper(PBUS) val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain") val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) } pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ } Some(streamingPassthroughChain) } case None => None } } /* * Mixin to add passthrough to rocket config / class WithStreamingPassthrough extends Config((site, here, up) => { case StreamingPassthroughKey => Some(StreamingPassthroughParams(depth = 8)) }) File DspBlocks.scala: package chipyard.example import chisel3._ import chisel3.util._ import dspblocks._ import dsptools.numbers._ import freechips.rocketchip.amba.axi4stream._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ /* * The memory interface writes entries into the queue. * They stream out the streaming interface * @param depth number of entries in the queue * @param streamParameters parameters for the stream node * @param p / abstract class WriteQueue[D, U, E, O, B <: Data] ( val depth: Int, val streamParameters: AXI4StreamMasterParameters = AXI4StreamMasterParameters() )(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR { // stream node, output only val streamNode = AXI4StreamMasterNode(streamParameters) lazy val module = new LazyModuleImp(this) { require(streamNode.out.length == 1) // get the output bundle associated with the AXI4Stream node val out = streamNode.out.head._1 // width (in bits) of the output interface val width = out.params.n 8 // instantiate a queue val queue = Module(new Queue(UInt(out.params.dataBits.W), depth)) // connect queue output to streaming output out.valid := queue.io.deq.valid out.bits.data := queue.io.deq.bits // don't use last out.bits.last := false.B queue.io.deq.ready := out.ready regmap( // each write adds an entry to the queue 0x0 -> Seq(RegField.w(width, queue.io.enq)), // read the number of entries in the queue (width+7)/8 -> Seq(RegField.r(width, queue.io.count)), ) } } /** * TLDspBlock specialization of WriteQueue * @param depth number of entries in the queue * @param csrAddress address range for peripheral * @param beatBytes beatBytes of TL interface * @param p / class TLWriteQueue (depth: Int, csrAddress: AddressSet, beatBytes: Int) (implicit p: Parameters) extends WriteQueue[ TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle ](depth) with TLHasCSR { val devname = "tlQueueIn" val devcompat = Seq("ucb-art", "dsptools") val device = new SimpleDevice(devname, devcompat) { override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) Description(name, mapping) } } // make diplomatic TL node for regmap override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) } object TLWriteQueue { def apply( depth: Int = 8, csrAddress: AddressSet = AddressSet(0x2000, 0xff), beatBytes: Int = 8, )(implicit p: Parameters) = { val writeQueue = LazyModule(new TLWriteQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes)) writeQueue } } /* * The streaming interface adds elements into the queue. * The memory interface can read elements out of the queue. * @param depth number of entries in the queue * @param streamParameters parameters for the stream node * @param p / abstract class ReadQueue[D, U, E, O, B <: Data] ( val depth: Int, val streamParameters: AXI4StreamSlaveParameters = AXI4StreamSlaveParameters() )(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR { val streamNode = AXI4StreamSlaveNode(streamParameters) lazy val module = new LazyModuleImp(this) { require(streamNode.in.length == 1) // get the input associated with the stream node val in = streamNode.in.head._1 // make a Decoupled[UInt] that RegReadFn can do something with val out = Wire(Decoupled(UInt())) // get width of streaming input interface val width = in.params.n 8 // instantiate a queue val queue = Module(new Queue(UInt(in.params.dataBits.W), depth)) // connect input to the streaming interface queue.io.enq.valid := in.valid queue.io.enq.bits := in.bits.data in.ready := queue.io.enq.ready // connect output to wire out.valid := queue.io.deq.valid out.bits := queue.io.deq.bits queue.io.deq.ready := out.ready regmap( // map the output of the queue 0x0 -> Seq(RegField.r(width, RegReadFn(out))), // read the number of elements in the queue (width+7)/8 -> Seq(RegField.r(width, queue.io.count)), ) } } /** * TLDspBlock specialization of ReadQueue * @param depth number of entries in the queue * @param csrAddress address range * @param beatBytes beatBytes of TL interface * @param p */ class TLReadQueue( depth: Int, csrAddress: AddressSet, beatBytes: Int) (implicit p: Parameters) extends ReadQueue[ TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle ](depth) with TLHasCSR { val devname = "tlQueueOut" val devcompat = Seq("ucb-art", "dsptools") val device = new SimpleDevice(devname, devcompat) { override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) Description(name, mapping) } } // make diplomatic TL node for regmap override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) } object TLReadQueue { def apply( depth: Int = 8, csrAddress: AddressSet = AddressSet(0x2100, 0xff), beatBytes: Int = 8)(implicit p: Parameters) = { val readQueue = LazyModule(new TLReadQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes)) readQueue } }	module TLStreamingPassthroughChain( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] output auto_bus_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_bus_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_bus_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_bus_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_bus_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_anon_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _bus_auto_anon_out_1_a_valid; // @[DspBlock.scala:146:23] wire [2:0] _bus_auto_anon_out_1_a_bits_opcode; // @[DspBlock.scala:146:23] wire [2:0] _bus_auto_anon_out_1_a_bits_param; // @[DspBlock.scala:146:23] wire [1:0] _bus_auto_anon_out_1_a_bits_size; // @[DspBlock.scala:146:23] wire [10:0] _bus_auto_anon_out_1_a_bits_source; // @[DspBlock.scala:146:23] wire [13:0] _bus_auto_anon_out_1_a_bits_address; // @[DspBlock.scala:146:23] wire [7:0] _bus_auto_anon_out_1_a_bits_mask; // @[DspBlock.scala:146:23] wire _bus_auto_anon_out_1_a_bits_corrupt; // @[DspBlock.scala:146:23] wire _bus_auto_anon_out_1_d_ready; // @[DspBlock.scala:146:23] wire _bus_auto_anon_out_0_a_valid; // @[DspBlock.scala:146:23] wire [2:0] _bus_auto_anon_out_0_a_bits_opcode; // @[DspBlock.scala:146:23] wire [2:0] _bus_auto_anon_out_0_a_bits_param; // @[DspBlock.scala:146:23] wire [1:0] _bus_auto_anon_out_0_a_bits_size; // @[DspBlock.scala:146:23] wire [10:0] _bus_auto_anon_out_0_a_bits_source; // @[DspBlock.scala:146:23] wire [13:0] _bus_auto_anon_out_0_a_bits_address; // @[DspBlock.scala:146:23] wire [7:0] _bus_auto_anon_out_0_a_bits_mask; // @[DspBlock.scala:146:23] wire [63:0] _bus_auto_anon_out_0_a_bits_data; // @[DspBlock.scala:146:23] wire _bus_auto_anon_out_0_a_bits_corrupt; // @[DspBlock.scala:146:23] wire _bus_auto_anon_out_0_d_ready; // @[DspBlock.scala:146:23] wire _readQueue_auto_mem_in_a_ready; // @[DspBlocks.scala:159:31] wire _readQueue_auto_mem_in_d_valid; // @[DspBlocks.scala:159:31] wire [2:0] _readQueue_auto_mem_in_d_bits_opcode; // @[DspBlocks.scala:159:31] wire [1:0] _readQueue_auto_mem_in_d_bits_size; // @[DspBlocks.scala:159:31] wire [10:0] _readQueue_auto_mem_in_d_bits_source; // @[DspBlocks.scala:159:31] wire [63:0] _readQueue_auto_mem_in_d_bits_data; // @[DspBlocks.scala:159:31] wire _readQueue_auto_stream_in_ready; // @[DspBlocks.scala:159:31] wire _streamingPassthrough_passthrough_io_in_ready; // @[StreamingPassthrough.scala:79:29] wire _streamingPassthrough_passthrough_io_out_valid; // @[StreamingPassthrough.scala:79:29] wire [31:0] _streamingPassthrough_passthrough_io_out_bits_data; // @[StreamingPassthrough.scala:79:29] wire _writeQueue_auto_mem_in_a_ready; // @[DspBlocks.scala:83:32] wire _writeQueue_auto_mem_in_d_valid; // @[DspBlocks.scala:83:32] wire [2:0] _writeQueue_auto_mem_in_d_bits_opcode; // @[DspBlocks.scala:83:32] wire [1:0] _writeQueue_auto_mem_in_d_bits_size; // @[DspBlocks.scala:83:32] wire [10:0] _writeQueue_auto_mem_in_d_bits_source; // @[DspBlocks.scala:83:32] wire [63:0] _writeQueue_auto_mem_in_d_bits_data; // @[DspBlocks.scala:83:32] wire _writeQueue_auto_stream_out_valid; // @[DspBlocks.scala:83:32] wire [63:0] _writeQueue_auto_stream_out_bits_data; // @[DspBlocks.scala:83:32] TLWriteQueue_1 writeQueue ( // @[DspBlocks.scala:83:32] .clock (clock), .reset (reset), .auto_mem_in_a_ready (_writeQueue_auto_mem_in_a_ready), .auto_mem_in_a_valid (_bus_auto_anon_out_0_a_valid), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_opcode (_bus_auto_anon_out_0_a_bits_opcode), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_param (_bus_auto_anon_out_0_a_bits_param), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_size (_bus_auto_anon_out_0_a_bits_size), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_source (_bus_auto_anon_out_0_a_bits_source), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_address (_bus_auto_anon_out_0_a_bits_address), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_mask (_bus_auto_anon_out_0_a_bits_mask), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_data (_bus_auto_anon_out_0_a_bits_data), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_corrupt (_bus_auto_anon_out_0_a_bits_corrupt), // @[DspBlock.scala:146:23] .auto_mem_in_d_ready (_bus_auto_anon_out_0_d_ready), // @[DspBlock.scala:146:23] .auto_mem_in_d_valid (_writeQueue_auto_mem_in_d_valid), .auto_mem_in_d_bits_opcode (_writeQueue_auto_mem_in_d_bits_opcode), .auto_mem_in_d_bits_size (_writeQueue_auto_mem_in_d_bits_size), .auto_mem_in_d_bits_source (_writeQueue_auto_mem_in_d_bits_source), .auto_mem_in_d_bits_data (_writeQueue_auto_mem_in_d_bits_data), .auto_stream_out_ready (_streamingPassthrough_passthrough_io_in_ready), // @[StreamingPassthrough.scala:79:29] .auto_stream_out_valid (_writeQueue_auto_stream_out_valid), .auto_stream_out_bits_data (_writeQueue_auto_stream_out_bits_data) ); // @[DspBlocks.scala:83:32] StreamingPassthrough streamingPassthrough_passthrough ( // @[StreamingPassthrough.scala:79:29] .io_in_ready (_streamingPassthrough_passthrough_io_in_ready), .io_in_valid (_writeQueue_auto_stream_out_valid), // @[DspBlocks.scala:83:32] .io_in_bits_data (_writeQueue_auto_stream_out_bits_data[31:0]), // @[StreamingPassthrough.scala:86:52] .io_out_ready (_readQueue_auto_stream_in_ready), // @[DspBlocks.scala:159:31] .io_out_valid (_streamingPassthrough_passthrough_io_out_valid), .io_out_bits_data (_streamingPassthrough_passthrough_io_out_bits_data) ); // @[StreamingPassthrough.scala:79:29] TLReadQueue_1 readQueue ( // @[DspBlocks.scala:159:31] .clock (clock), .reset (reset), .auto_mem_in_a_ready (_readQueue_auto_mem_in_a_ready), .auto_mem_in_a_valid (_bus_auto_anon_out_1_a_valid), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_opcode (_bus_auto_anon_out_1_a_bits_opcode), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_param (_bus_auto_anon_out_1_a_bits_param), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_size (_bus_auto_anon_out_1_a_bits_size), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_source (_bus_auto_anon_out_1_a_bits_source), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_address (_bus_auto_anon_out_1_a_bits_address), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_mask (_bus_auto_anon_out_1_a_bits_mask), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_corrupt (_bus_auto_anon_out_1_a_bits_corrupt), // @[DspBlock.scala:146:23] .auto_mem_in_d_ready (_bus_auto_anon_out_1_d_ready), // @[DspBlock.scala:146:23] .auto_mem_in_d_valid (_readQueue_auto_mem_in_d_valid), .auto_mem_in_d_bits_opcode (_readQueue_auto_mem_in_d_bits_opcode), .auto_mem_in_d_bits_size (_readQueue_auto_mem_in_d_bits_size), .auto_mem_in_d_bits_source (_readQueue_auto_mem_in_d_bits_source), .auto_mem_in_d_bits_data (_readQueue_auto_mem_in_d_bits_data), .auto_stream_in_ready (_readQueue_auto_stream_in_ready), .auto_stream_in_valid (_streamingPassthrough_passthrough_io_out_valid), // @[StreamingPassthrough.scala:79:29] .auto_stream_in_bits_data ({32'h0, _streamingPassthrough_passthrough_io_out_bits_data}) // @[StreamingPassthrough.scala:79:29, :92:19] ); // @[DspBlocks.scala:159:31] TLXbar_i1_o2_a14d64s11k1z2u_1 bus ( // @[DspBlock.scala:146:23] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_bus_anon_in_a_ready), .auto_anon_in_a_valid (auto_bus_anon_in_a_valid), .auto_anon_in_a_bits_opcode (auto_bus_anon_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_bus_anon_in_a_bits_param), .auto_anon_in_a_bits_size (auto_bus_anon_in_a_bits_size), .auto_anon_in_a_bits_source (auto_bus_anon_in_a_bits_source), .auto_anon_in_a_bits_address (auto_bus_anon_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_bus_anon_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_bus_anon_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_bus_anon_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_bus_anon_in_d_ready), .auto_anon_in_d_valid (auto_bus_anon_in_d_valid), .auto_anon_in_d_bits_opcode (auto_bus_anon_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_bus_anon_in_d_bits_size), .auto_anon_in_d_bits_source (auto_bus_anon_in_d_bits_source), .auto_anon_in_d_bits_data (auto_bus_anon_in_d_bits_data), .auto_anon_out_1_a_ready (_readQueue_auto_mem_in_a_ready), // @[DspBlocks.scala:159:31] .auto_anon_out_1_a_valid (_bus_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_bus_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_bus_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_bus_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_bus_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_bus_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_bus_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_corrupt (_bus_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_bus_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_readQueue_auto_mem_in_d_valid), // @[DspBlocks.scala:159:31] .auto_anon_out_1_d_bits_opcode (_readQueue_auto_mem_in_d_bits_opcode), // @[DspBlocks.scala:159:31] .auto_anon_out_1_d_bits_size (_readQueue_auto_mem_in_d_bits_size), // @[DspBlocks.scala:159:31] .auto_anon_out_1_d_bits_source (_readQueue_auto_mem_in_d_bits_source), // @[DspBlocks.scala:159:31] .auto_anon_out_1_d_bits_data (_readQueue_auto_mem_in_d_bits_data), // @[DspBlocks.scala:159:31] .auto_anon_out_0_a_ready (_writeQueue_auto_mem_in_a_ready), // @[DspBlocks.scala:83:32] .auto_anon_out_0_a_valid (_bus_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_bus_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_bus_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_bus_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_bus_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_bus_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_bus_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_bus_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_bus_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_bus_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_writeQueue_auto_mem_in_d_valid), // @[DspBlocks.scala:83:32] .auto_anon_out_0_d_bits_opcode (_writeQueue_auto_mem_in_d_bits_opcode), // @[DspBlocks.scala:83:32] .auto_anon_out_0_d_bits_size (_writeQueue_auto_mem_in_d_bits_size), // @[DspBlocks.scala:83:32] .auto_anon_out_0_d_bits_source (_writeQueue_auto_mem_in_d_bits_source), // @[DspBlocks.scala:83:32] .auto_anon_out_0_d_bits_data (_writeQueue_auto_mem_in_d_bits_data) // @[DspBlocks.scala:83:32] ); // @[DspBlock.scala:146:23] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_171( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_427 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File lsu.scala: //****************************************************************************** // Copyright (c) 2012 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Out-of-Order Load/Store Unit //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // Load/Store Unit is made up of the Load-Address Queue, the Store-Address // Queue, and the Store-Data queue (LAQ, SAQ, and SDQ). // // Stores are sent to memory at (well, after) commit, loads are executed // optimstically ASAP. If a misspeculation was discovered, the pipeline is // cleared. Loads put to sleep are retried. If a LoadAddr and StoreAddr match, // the Load can receive its data by forwarding data out of the Store-Data // Queue. // // Currently, loads are sent to memory immediately, and in parallel do an // associative search of the SAQ, on entering the LSU. If a hit on the SAQ // search, the memory request is killed on the next cycle, and if the SDQ entry // is valid, the store data is forwarded to the load (delayed to match the // load-use delay to delay with the write-port structural hazard). If the store // data is not present, or it's only a partial match (SB->LH), the load is put // to sleep in the LAQ. // // Memory ordering violations are detected by stores at their addr-gen time by // associatively searching the LAQ for newer loads that have been issued to // memory. // // The store queue contains both speculated and committed stores. // // Only one port to memory... loads and stores have to fight for it, West Side // Story style. // // TODO: // - Add predicting structure for ordering failures // - currently won't STD forward if DMEM is busy // - ability to turn off things if VM is disabled // - reconsider port count of the wakeup, retry stuff package boom.v4.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.Str import boom.v4.common._ import boom.v4.exu.{BrUpdateInfo, Exception, CommitSignals, MemGen, ExeUnitResp, Wakeup} import boom.v4.util._ class BoomDCacheReq(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = UInt(coreMaxAddrBits.W) val data = Bits(coreDataBits.W) val is_hella = Bool() // Is this the hellacache req? If so this is not tracked in LDQ or STQ } class BoomDCacheResp(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val data = Bits(coreDataBits.W) val is_hella = Bool() } class LSUDMemIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { // In LSU's dmem stage, send the request val req = new DecoupledIO(Vec(lsuWidth, Valid(new BoomDCacheReq))) // In LSU's LCAM search stage, kill if order fail (or forwarding possible) val s1_kill = Output(Vec(lsuWidth, Bool())) // The s1 inflight request will likely get nacked next cycle val s1_nack_advisory = Input(Vec(lsuWidth, Bool())) // Get a request any cycle val resp = Flipped(Vec(lsuWidth, new ValidIO(new BoomDCacheResp))) // The cache irrevocably accepted our store val store_ack = Flipped(Vec(lsuWidth, new ValidIO(new BoomDCacheReq))) // In our response stage, if we get a nack, we need to reexecute val nack = Flipped(Vec(lsuWidth, new ValidIO(new BoomDCacheReq))) val ll_resp = Flipped(new DecoupledIO(new BoomDCacheResp)) val brupdate = Output(new BrUpdateInfo) val exception = Output(Bool()) val rob_pnr_idx = Output(UInt(robAddrSz.W)) val rob_head_idx = Output(UInt(robAddrSz.W)) val release = Flipped(new DecoupledIO(new TLBundleC(edge.bundle))) // Clears prefetching MSHRs val force_order = Output(Bool()) val ordered = Input(Bool()) val perf = Input(new Bundle { val acquire = Bool() val release = Bool() }) } class LSUCoreIO(implicit p: Parameters) extends BoomBundle()(p) { val agen = Flipped(Vec(lsuWidth, Valid(new MemGen))) val dgen = Flipped(Vec(memWidth + 1, Valid(new MemGen))) val iwakeups = Vec(lsuWidth, Valid(new Wakeup)) val iresp = Vec(lsuWidth, Valid(new ExeUnitResp(xLen))) val fresp = Vec(lsuWidth, Valid(new ExeUnitResp(xLen))) val sfence = Flipped(Valid(new rocket.SFenceReq)) val dis_uops = Flipped(Vec(coreWidth, Valid(new MicroOp))) val dis_ldq_idx = Output(Vec(coreWidth, UInt(ldqAddrSz.W))) val dis_stq_idx = Output(Vec(coreWidth, UInt(stqAddrSz.W))) val ldq_full = Output(Vec(coreWidth, Bool())) val stq_full = Output(Vec(coreWidth, Bool())) val commit = Input(new CommitSignals) val commit_load_at_rob_head = Input(Bool()) // Stores clear busy bit when stdata is received // memWidth for incoming addr/datagen, +1 for fp dgen, +1 for clr_head pointer val clr_bsy = Output(Vec(coreWidth, Valid(UInt(robAddrSz.W)))) // Speculatively safe load (barring memory ordering failure) val clr_unsafe = Output(Vec(lsuWidth, Valid(UInt(robAddrSz.W)))) // Tell the DCache to clear prefetches/speculating misses val fence_dmem = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val exception = Input(Bool()) val fencei_rdy = Output(Bool()) val lxcpt = Output(Valid(new Exception)) val tsc_reg = Input(UInt()) val status = Input(new rocket.MStatus) val bp = Input(Vec(nBreakpoints, new rocket.BP)) val mcontext = Input(UInt()) val scontext = Input(UInt()) val perf = Output(new Bundle { val acquire = Bool() val release = Bool() val tlbMiss = Bool() }) } class LSUIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { val ptw = new rocket.TLBPTWIO val core = new LSUCoreIO val dmem = new LSUDMemIO val hellacache = Flipped(new freechips.rocketchip.rocket.HellaCacheIO) } class LDQEntry(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = Valid(UInt(coreMaxAddrBits.W)) val addr_is_virtual = Bool() // Virtual address, we got a TLB miss val addr_is_uncacheable = Bool() // Uncacheable, wait until head of ROB to execute val executed = Bool() // load sent to memory, reset by NACKs val succeeded = Bool() val order_fail = Bool() val observed = Bool() val st_dep_mask = UInt(numStqEntries.W) // list of stores older than us val ld_byte_mask = UInt(8.W) val forward_std_val = Bool() val forward_stq_idx = UInt(stqAddrSz.W) // Which store did we get the store-load forward from? val debug_wb_data = UInt(xLen.W) } class STQEntry(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = Valid(UInt(coreMaxAddrBits.W)) val addr_is_virtual = Bool() // Virtual address, we got a TLB miss val data = Valid(UInt(xLen.W)) val committed = Bool() // committed by ROB val succeeded = Bool() // D$ has ack'd this, we don't need to maintain this anymore val can_execute = Bool() val cleared = Bool() // we've cleared this entry in the ROB val debug_wb_data = UInt(xLen.W) } class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p) with rocket.HasL1HellaCacheParameters { val io = IO(new LSUIO) //val ldq = Reg(Vec(numLdqEntries, Valid(new LDQEntry))) val ldq_valid = Reg(Vec(numLdqEntries, Bool())) val ldq_uop = Reg(Vec(numLdqEntries, new MicroOp)) val ldq_addr = Reg(Vec(numLdqEntries, Valid(UInt(coreMaxAddrBits.W)))) val ldq_addr_is_virtual = Reg(Vec(numLdqEntries, Bool())) val ldq_addr_is_uncacheable = Reg(Vec(numLdqEntries, Bool())) val ldq_executed = Reg(Vec(numLdqEntries, Bool())) val ldq_succeeded = Reg(Vec(numLdqEntries, Bool())) val ldq_order_fail = Reg(Vec(numLdqEntries, Bool())) val ldq_observed = Reg(Vec(numLdqEntries, Bool())) val ldq_st_dep_mask = Reg(Vec(numLdqEntries, UInt(numStqEntries.W))) val ldq_ld_byte_mask = Reg(Vec(numLdqEntries, UInt(8.W))) val ldq_forward_std_val = Reg(Vec(numLdqEntries, Bool())) val ldq_forward_stq_idx = Reg(Vec(numLdqEntries, UInt(stqAddrSz.W))) val ldq_debug_wb_data = Reg(Vec(numLdqEntries, UInt(xLen.W))) def ldq_read(idx: UInt): Valid[LDQEntry] = { val e = Wire(Valid(new LDQEntry)) e.valid := ldq_valid (idx) e.bits.uop := ldq_uop (idx) e.bits.addr := ldq_addr (idx) e.bits.addr_is_virtual := ldq_addr_is_virtual (idx) e.bits.addr_is_uncacheable := ldq_addr_is_uncacheable(idx) e.bits.executed := ldq_executed (idx) e.bits.succeeded := ldq_succeeded (idx) e.bits.order_fail := ldq_order_fail (idx) e.bits.observed := ldq_observed (idx) e.bits.st_dep_mask := ldq_st_dep_mask (idx) e.bits.ld_byte_mask := ldq_ld_byte_mask (idx) e.bits.forward_std_val := ldq_forward_std_val (idx) e.bits.forward_stq_idx := ldq_forward_stq_idx (idx) e.bits.debug_wb_data := ldq_debug_wb_data (idx) e } //val stq = Reg(Vec(numStqEntries, Valid(new STQEntry))) val stq_valid = Reg(Vec(numStqEntries, Bool())) val stq_uop = Reg(Vec(numStqEntries, new MicroOp)) val stq_addr = Reg(Vec(numStqEntries, Valid(UInt(coreMaxAddrBits.W)))) val stq_addr_is_virtual = Reg(Vec(numStqEntries, Bool())) val stq_data = Reg(Vec(numStqEntries, Valid(UInt(xLen.W)))) val stq_committed = Reg(Vec(numStqEntries, Bool())) val stq_succeeded = Reg(Vec(numStqEntries, Bool())) val stq_can_execute = Reg(Vec(numStqEntries, Bool())) val stq_cleared = Reg(Vec(numStqEntries, Bool())) val stq_debug_wb_data = Reg(Vec(numStqEntries, UInt(xLen.W))) def stq_read(idx: UInt): Valid[STQEntry] = { val e = Wire(Valid(new STQEntry)) e.valid := stq_valid (idx) e.bits.uop := stq_uop (idx) e.bits.addr := stq_addr (idx) e.bits.addr_is_virtual := stq_addr_is_virtual (idx) e.bits.data := stq_data (idx) e.bits.committed := stq_committed (idx) e.bits.succeeded := stq_succeeded (idx) e.bits.can_execute := stq_can_execute (idx) e.bits.cleared := stq_cleared (idx) e.bits.debug_wb_data := stq_debug_wb_data (idx) e } val ldq_head = Reg(UInt(ldqAddrSz.W)) val ldq_tail = Reg(UInt(ldqAddrSz.W)) val stq_head = Reg(UInt(stqAddrSz.W)) // point to next store to clear from STQ (i.e., send to memory) val stq_tail = Reg(UInt(stqAddrSz.W)) val stq_commit_head = Reg(UInt(stqAddrSz.W)) // point to next store to commit val stq_execute_head = Reg(UInt(stqAddrSz.W)) // point to next store to execute val h_ready :: h_s1 :: h_s2 :: h_s2_nack :: h_wait :: h_replay :: h_dead :: Nil = Enum(7) // s1 : do TLB, if success and not killed, fire request go to h_s2 // store s1_data to register // if tlb miss, go to s2_nack // if don't get TLB, go to s2_nack // store tlb xcpt // s2 : If kill, go to dead // If tlb xcpt, send tlb xcpt, go to dead // s2_nack : send nack, go to dead // wait : wait for response, if nack, go to replay // replay : refire request, use already translated address // dead : wait for response, ignore it val hella_state = RegInit(h_ready) val hella_req = Reg(new rocket.HellaCacheReq) val hella_data = Reg(new rocket.HellaCacheWriteData) val hella_paddr = Reg(UInt(paddrBits.W)) val hella_xcpt = Reg(new rocket.HellaCacheExceptions) val dtlb = Module(new NBDTLB( instruction = false, lgMaxSize = log2Ceil(coreDataBytes), rocket.TLBConfig(dcacheParams.nTLBSets, dcacheParams.nTLBWays))) io.ptw <> dtlb.io.ptw io.core.perf.tlbMiss := io.ptw.req.fire io.core.perf.acquire := io.dmem.perf.acquire io.core.perf.release := io.dmem.perf.release val clear_store = WireInit(false.B) def widthMap[T <: Data](f: Int => T) = VecInit((0 until lsuWidth).map(f)) // default connection from flip flop to next state val ldq_will_succeed = WireDefault(ldq_succeeded) ldq_succeeded := ldq_will_succeed //------------------------------------------------------------- //------------------------------------------------------------- // Enqueue new entries //------------------------------------------------------------- //------------------------------------------------------------- // This is a newer store than existing loads, so clear the bit in all the store dependency masks for (i <- 0 until numLdqEntries) { when (clear_store) { ldq_st_dep_mask(i) := ldq_st_dep_mask(i) & ~(1.U << stq_head) } } // Decode stage var ld_enq_idx = ldq_tail var st_enq_idx = stq_tail val dis_ldq_oh = Reg(Vec(numLdqEntries, Bool())) val dis_stq_oh = Reg(Vec(numStqEntries, Bool())) dis_ldq_oh := 0.U(numLdqEntries.W).asBools dis_stq_oh := 0.U(numStqEntries.W).asBools val dis_uops = Reg(Vec(coreWidth, Valid(new MicroOp))) val live_store_mask = stq_valid.asUInt \| dis_stq_oh.asUInt var next_live_store_mask = Mux(clear_store, live_store_mask & ~(1.U << stq_head), live_store_mask) var ldq_tail_oh = UIntToOH(ldq_tail)(numLdqEntries-1,0) val ldq_valids = ldq_valid.asUInt \| dis_ldq_oh.asUInt var stq_tail_oh = UIntToOH(stq_tail)(numStqEntries-1,0) val stq_valids = stq_valid.asUInt \| dis_stq_oh.asUInt val stq_nonempty = stq_valid.reduce(_\|\|_) for (w <- 0 until coreWidth) { val ldq_full = (ldq_tail_oh & ldq_valids).orR io.core.ldq_full(w) := ldq_full io.core.dis_ldq_idx(w) := ld_enq_idx val stq_full = (stq_tail_oh & stq_valids).orR io.core.stq_full(w) := stq_full io.core.dis_stq_idx(w) := st_enq_idx val dis_ld_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_ldq && !io.core.dis_uops(w).bits.exception val dis_st_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_stq && !io.core.dis_uops(w).bits.exception dis_uops(w).valid := dis_ld_val \|\| dis_st_val dis_uops(w).bits := io.core.dis_uops(w).bits when (dis_ld_val) { dis_ldq_oh(ld_enq_idx) := true.B ldq_st_dep_mask(ld_enq_idx) := next_live_store_mask assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, "[lsu] mismatch enq load tag.") assert (!ldq_valid(ld_enq_idx), "[lsu] Enqueuing uop is overwriting ldq entries") } when (dis_st_val) { dis_stq_oh(st_enq_idx) := true.B assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, "[lsu] mismatch enq store tag.") assert (!stq_valid(st_enq_idx), "[lsu] Enqueuing uop is overwriting stq entries") } when (dis_uops(w).valid && dis_uops(w).bits.uses_ldq) { val ldq_idx = dis_uops(w).bits.ldq_idx ldq_valid (ldq_idx) := !IsKilledByBranch(io.core.brupdate, io.core.exception, dis_uops(w).bits) ldq_uop (ldq_idx) := UpdateBrMask(io.core.brupdate, dis_uops(w).bits) ldq_addr (ldq_idx).valid := false.B ldq_executed (ldq_idx) := false.B ldq_will_succeed (ldq_idx) := false.B ldq_order_fail (ldq_idx) := false.B ldq_observed (ldq_idx) := false.B ldq_forward_std_val(ldq_idx) := false.B } when (dis_uops(w).valid && dis_uops(w).bits.uses_stq) { val stq_idx = dis_uops(w).bits.stq_idx stq_valid (stq_idx) := !IsKilledByBranch(io.core.brupdate, io.core.exception, dis_uops(w).bits) stq_uop (stq_idx) := UpdateBrMask(io.core.brupdate, dis_uops(w).bits) stq_addr (stq_idx).valid := false.B stq_data (stq_idx).valid := false.B stq_committed (stq_idx) := false.B stq_can_execute (stq_idx) := false.B stq_succeeded (stq_idx) := false.B stq_cleared (stq_idx) := false.B } ld_enq_idx = Mux(dis_ld_val, WrapInc(ld_enq_idx, numLdqEntries), ld_enq_idx) next_live_store_mask = Mux(dis_st_val, next_live_store_mask \| (1.U << st_enq_idx), next_live_store_mask) st_enq_idx = Mux(dis_st_val, WrapInc(st_enq_idx, numStqEntries), st_enq_idx) assert(!(dis_ld_val && dis_st_val), "A UOP is trying to go into both the LDQ and the STQ") ldq_tail_oh = Mux((io.core.dis_uops(w).bits.uses_ldq && !io.core.dis_uops(w).bits.exception) \|\| !enableCompactingLSUDuringDispatch.B, RotateL1(ldq_tail_oh), ldq_tail_oh) stq_tail_oh = Mux((io.core.dis_uops(w).bits.uses_stq && !io.core.dis_uops(w).bits.exception) \|\| !enableCompactingLSUDuringDispatch.B, RotateL1(stq_tail_oh), stq_tail_oh) } ldq_tail := ld_enq_idx stq_tail := st_enq_idx // If we got a mispredict, the tail will be misaligned for 1 extra cycle assert (io.core.brupdate.b2.mispredict \|\| stq_valid(stq_execute_head) \|\| dis_stq_oh(stq_execute_head) \|\| stq_head === stq_execute_head \|\| stq_tail === stq_execute_head, "stq_execute_head got off track.") io.dmem.force_order := io.core.fence_dmem io.core.fencei_rdy := !stq_nonempty && io.dmem.ordered //------------------------------------------------------------- //------------------------------------------------------------- // Execute stage (access TLB, send requests to Memory) //------------------------------------------------------------- //------------------------------------------------------------- // We can only report 1 exception per cycle. // Just be sure to report the youngest one val mem_xcpt_valid = Wire(Bool()) val mem_xcpt_cause = Wire(UInt()) val mem_xcpt_uop = Wire(new MicroOp) val mem_xcpt_vaddr = Wire(UInt()) //--------------------------------------- // Can-fire logic and wakeup/retry select // // First we determine what operations are waiting to execute. // These are the "can_fire"/"will_fire" signals val will_fire_load_agen_exec = Wire(Vec(lsuWidth, Bool())) val will_fire_load_agen = Wire(Vec(lsuWidth, Bool())) val will_fire_store_agen = Wire(Vec(lsuWidth, Bool())) val will_fire_sfence = Wire(Vec(lsuWidth, Bool())) val will_fire_hella_incoming = Wire(Vec(lsuWidth, Bool())) val will_fire_hella_wakeup = Wire(Vec(lsuWidth, Bool())) val will_fire_release = Wire(Vec(lsuWidth, Bool())) val will_fire_load_retry = Wire(Vec(lsuWidth, Bool())) val will_fire_store_retry = Wire(Vec(lsuWidth, Bool())) val will_fire_store_commit_fast = Wire(Vec(lsuWidth, Bool())) val will_fire_store_commit_slow = Wire(Vec(lsuWidth, Bool())) val will_fire_load_wakeup = Wire(Vec(lsuWidth, Bool())) val agen = io.core.agen // ------------------------------- // Assorted signals for scheduling // Don't wakeup a load if we just sent it last cycle or two cycles ago // The block_load_mask may be wrong, but the executing_load mask must be accurate val block_load_mask = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) val p1_block_load_mask = RegNext(block_load_mask) val p2_block_load_mask = RegNext(p1_block_load_mask) // Prioritize emptying the store queue when it is almost full val stq_tail_plus = WrapAdd(stq_tail, (2coreWidth).U, numStqEntries) val stq_almost_full = RegNext(IsOlder(stq_head, stq_tail_plus, stq_tail)) // The store at the commit head needs the DCache to appear ordered // Delay firing load wakeups and retries now val store_needs_order = WireInit(false.B) val ldq_incoming_idx = widthMap(i => agen(i).bits.uop.ldq_idx) val ldq_incoming_e = widthMap(i => WireInit(ldq_read(ldq_incoming_idx(i)))) val stq_incoming_idx = widthMap(i => agen(i).bits.uop.stq_idx) val stq_incoming_e = widthMap(i => WireInit(stq_read(stq_incoming_idx(i)))) val ldq_wakeup_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i=> { val block = block_load_mask(i) \|\| p1_block_load_mask(i) ldq_addr(i).valid && !ldq_executed(i) && !ldq_succeeded(i) && !ldq_addr_is_virtual(i) && !block }), ldq_head)) val ldq_wakeup_e = WireInit(ldq_read(ldq_wakeup_idx)) // Enqueue into the retry queue val ldq_enq_retry_idx = Reg(UInt(ldqAddrSz.W)) ldq_enq_retry_idx := AgePriorityEncoder((0 until numLdqEntries).map(i => { ldq_addr(i).valid && ldq_addr_is_virtual(i) && (i.U =/= ldq_enq_retry_idx) }), ldq_head) val ldq_enq_retry_e = WireInit(ldq_read(ldq_enq_retry_idx)) val stq_enq_retry_idx = Reg(UInt(stqAddrSz.W)) stq_enq_retry_idx := AgePriorityEncoder((0 until numStqEntries).map(i => { stq_addr(i).valid && stq_addr_is_virtual(i) && (i.U =/= stq_enq_retry_idx) }), stq_commit_head) val stq_enq_retry_e = WireInit(stq_read(stq_enq_retry_idx)) val can_enq_load_retry = (ldq_enq_retry_e.valid && ldq_enq_retry_e.bits.addr.valid && ldq_enq_retry_e.bits.addr_is_virtual) val can_enq_store_retry = (stq_enq_retry_e.valid && stq_enq_retry_e.bits.addr.valid && stq_enq_retry_e.bits.addr_is_virtual) val retry_queue = Module(new BranchKillableQueue(new MemGen, 8)) retry_queue.io.brupdate := io.core.brupdate retry_queue.io.flush := io.core.exception retry_queue.io.enq.valid := can_enq_store_retry \|\| can_enq_load_retry retry_queue.io.enq.bits := DontCare retry_queue.io.enq.bits.data := Mux(can_enq_store_retry, stq_enq_retry_e.bits.addr.bits, ldq_enq_retry_e.bits.addr.bits) retry_queue.io.enq.bits.uop := Mux(can_enq_store_retry, stq_enq_retry_e.bits.uop , ldq_enq_retry_e.bits.uop) retry_queue.io.enq.bits.uop.uses_ldq := can_enq_load_retry && !can_enq_store_retry retry_queue.io.enq.bits.uop.ldq_idx := ldq_enq_retry_idx retry_queue.io.enq.bits.uop.uses_stq := can_enq_store_retry retry_queue.io.enq.bits.uop.stq_idx := stq_enq_retry_idx when (can_enq_store_retry && retry_queue.io.enq.fire) { stq_addr(stq_enq_retry_idx).valid := false.B } .elsewhen (can_enq_load_retry && retry_queue.io.enq.fire) { ldq_addr(ldq_enq_retry_idx).valid := false.B } val ldq_retry_idx = retry_queue.io.deq.bits.uop.ldq_idx val stq_retry_idx = retry_queue.io.deq.bits.uop.stq_idx retry_queue.io.deq.ready := will_fire_load_retry.reduce(_\|\|_) \|\| will_fire_store_retry.reduce(_\|\|_) val stq_execute_queue_flush = WireInit(false.B) val stq_execute_queue = withReset(reset.asBool \|\| stq_execute_queue_flush) { Module(new Queue(new STQEntry, 4)) } val stq_commit_e = stq_execute_queue.io.deq val stq_enq_e = WireInit(stq_read(stq_execute_head)) stq_execute_queue.io.enq.bits := stq_enq_e.bits stq_execute_queue.io.enq.bits.uop.stq_idx := stq_execute_head stq_execute_queue.io.deq.ready := will_fire_store_commit_fast.reduce(_\|\|_) \|\| will_fire_store_commit_slow.reduce(_\|\|_) val can_enq_store_execute = ( stq_enq_e.valid && stq_enq_e.bits.addr.valid && stq_enq_e.bits.data.valid && !stq_enq_e.bits.addr_is_virtual && !stq_enq_e.bits.uop.exception && !stq_enq_e.bits.uop.is_fence && (stq_enq_e.bits.committed \|\| stq_enq_e.bits.uop.is_amo) ) stq_execute_queue.io.enq.valid := can_enq_store_execute when (can_enq_store_execute && stq_execute_queue.io.enq.fire) { stq_execute_head := WrapInc(stq_execute_head, numStqEntries) } // ----------------------- // Determine what can fire // Can we fire a incoming load val can_fire_load_agen_exec = widthMap(w => agen(w).valid && agen(w).bits.uop.uses_ldq) val can_fire_load_agen = can_fire_load_agen_exec // Can we fire an incoming store addrgen + store datagen val can_fire_store_agen = widthMap(w => agen(w).valid && agen(w).bits.uop.uses_stq) // Can we fire an incoming sfence val can_fire_sfence = widthMap(w => io.core.sfence.valid) // Can we fire a request from dcache to release a line // This needs to go through LDQ search to mark loads as dangerous val can_fire_release = widthMap(w => (w == lsuWidth-1).B && io.dmem.release.valid) io.dmem.release.ready := will_fire_release.reduce(_\|\|_) // Can we retry a load that missed in the TLB val can_fire_load_retry = widthMap(w => ( retry_queue.io.deq.valid && retry_queue.io.deq.bits.uop.uses_ldq && !RegNext(store_needs_order) && (w == lsuWidth-1).B)) // Can we retry a store addrgen that missed in the TLB val can_fire_store_retry = widthMap(w => ( retry_queue.io.deq.valid && retry_queue.io.deq.bits.uop.uses_stq && (w == lsuWidth-1).B)) // Can we commit a store val can_fire_store_commit_slow = widthMap(w => ( stq_commit_e.valid && !mem_xcpt_valid && (w == 0).B)) val can_fire_store_commit_fast = widthMap(w => can_fire_store_commit_slow(w) && stq_almost_full) // Can we wakeup a load that was nack'd val block_load_wakeup = WireInit(false.B) val can_fire_load_wakeup = widthMap(w => ( ldq_wakeup_e.valid && ldq_wakeup_e.bits.addr.valid && !ldq_wakeup_e.bits.succeeded && !ldq_wakeup_e.bits.addr_is_virtual && !ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.order_fail && !p1_block_load_mask(ldq_wakeup_idx) && !p2_block_load_mask(ldq_wakeup_idx) && !RegNext(store_needs_order) && !block_load_wakeup && (w == lsuWidth-1).B && (!ldq_wakeup_e.bits.addr_is_uncacheable \|\| (io.core.commit_load_at_rob_head && ldq_head === ldq_wakeup_idx && ldq_wakeup_e.bits.st_dep_mask.asUInt === 0.U)))) // Can we fire an incoming hellacache request val can_fire_hella_incoming = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim ocntroller // Can we fire a hellacache request that the dcache nack'd val can_fire_hella_wakeup = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim controller //--------------------------------------------------------- // Controller logic. Arbitrate which request actually fires val exe_tlb_valid = Wire(Vec(lsuWidth, Bool())) for (w <- 0 until lsuWidth) { var tlb_avail = true.B var dc_avail = true.B var lcam_avail = true.B def lsu_sched(can_fire: Bool, uses_tlb:Boolean, uses_dc:Boolean, uses_lcam: Boolean): Bool = { val will_fire = can_fire && !(uses_tlb.B && !tlb_avail) && !(uses_lcam.B && !lcam_avail) && !(uses_dc.B && !dc_avail) tlb_avail = tlb_avail && !(will_fire && uses_tlb.B) lcam_avail = lcam_avail && !(will_fire && uses_lcam.B) dc_avail = dc_avail && !(will_fire && uses_dc.B) dontTouch(will_fire) // dontTouch these so we can inspect the will_fire signals will_fire } // The order of these statements is the priority // Some restrictions // - Incoming ops must get precedence, can't backpresure memaddrgen // - Incoming hellacache ops must get precedence over retrying ops (PTW must get precedence over retrying translation) // Notes on performance // - Prioritize releases, this speeds up cache line writebacks and refills // - Store commits are lowest priority, since they don't "block" younger instructions unless stq fills up will_fire_sfence (w) := lsu_sched(can_fire_sfence (w) , true , false, false) // TLB , , will_fire_store_commit_fast(w) := lsu_sched(can_fire_store_commit_fast(w) , false, true , false) // , DC If store queue is filling up, prioritize draining it will_fire_load_agen_exec (w) := lsu_sched(can_fire_load_agen_exec (w) , true , true , true ) // TLB , DC , LCAM Normally fire loads as soon as translation completes will_fire_load_agen (w) := lsu_sched(can_fire_load_agen (w) , true , false, true ) // TLB , , LCAM If we are draining stores, still translate the loads will_fire_store_agen (w) := lsu_sched(can_fire_store_agen (w) , true , false, true ) // TLB , , LCAM will_fire_release (w) := lsu_sched(can_fire_release (w) , false, false, true ) // LCAM will_fire_hella_incoming (w) := lsu_sched(can_fire_hella_incoming (w) , true , true , false) // TLB , DC will_fire_hella_wakeup (w) := lsu_sched(can_fire_hella_wakeup (w) , false, true , false) // , DC will_fire_store_retry (w) := lsu_sched(can_fire_store_retry (w) , true , false, true ) // TLB , , LCAM will_fire_load_retry (w) := lsu_sched(can_fire_load_retry (w) , true , true , true ) // TLB , DC , LCAM will_fire_load_wakeup (w) := lsu_sched(can_fire_load_wakeup (w) , false, true , true ) // , DC , LCAM will_fire_store_commit_slow(w) := lsu_sched(can_fire_store_commit_slow(w) , false, true , false) // , DC assert(!(agen(w).valid && !(will_fire_load_agen_exec(w) \|\| will_fire_load_agen(w) \|\| will_fire_store_agen(w)))) when (will_fire_load_wakeup(w)) { block_load_mask(ldq_wakeup_idx) := true.B } .elsewhen (will_fire_load_agen(w) \|\| will_fire_load_agen_exec(w)) { block_load_mask(agen(w).bits.uop.ldq_idx) := true.B } .elsewhen (will_fire_load_retry(w)) { block_load_mask(ldq_retry_idx) := true.B } exe_tlb_valid(w) := !tlb_avail } assert((lsuWidth == 1).B \|\| (!will_fire_hella_incoming.reduce(_&&_) && !will_fire_hella_wakeup.reduce(_&&_) && !will_fire_load_retry.reduce(_&&_) && !will_fire_store_retry.reduce(_&&_) && !will_fire_store_commit_fast.reduce(_&&_) && !will_fire_store_commit_slow.reduce(_&&_) && !will_fire_load_wakeup.reduce(_&&_)), "Some operations is proceeding down multiple pipes") require(lsuWidth <= 2) //-------------------------------------------- // TLB Access assert(!(hella_state =/= h_ready && hella_req.cmd === rocket.M_SFENCE), "SFENCE through hella interface not supported") val exe_tlb_uop = widthMap(w => Mux(will_fire_load_agen_exec(w) \|\| will_fire_load_agen (w) , ldq_incoming_e(w).bits.uop, Mux(will_fire_store_agen (w) , stq_incoming_e(w).bits.uop, Mux(will_fire_load_retry (w) \|\| will_fire_store_retry (w) , retry_queue.io.deq.bits.uop, Mux(will_fire_hella_incoming(w) , 0.U.asTypeOf(new MicroOp), 0.U.asTypeOf(new MicroOp)))))) val exe_tlb_vaddr = widthMap(w => Mux(will_fire_load_agen_exec(w) \|\| will_fire_load_agen (w) \|\| will_fire_store_agen (w) , agen(w).bits.data, Mux(will_fire_sfence (w) , io.core.sfence.bits.addr, Mux(will_fire_load_retry (w) \|\| will_fire_store_retry (w) , retry_queue.io.deq.bits.data, Mux(will_fire_hella_incoming(w) , hella_req.addr, 0.U))))) val exe_sfence = io.core.sfence val exe_size = widthMap(w => Mux(will_fire_load_agen_exec(w) \|\| will_fire_load_agen (w) \|\| will_fire_store_agen (w) \|\| will_fire_load_retry (w) \|\| will_fire_store_retry (w) , exe_tlb_uop(w).mem_size, Mux(will_fire_hella_incoming(w) , hella_req.size, 0.U))) val exe_cmd = widthMap(w => Mux(will_fire_load_agen_exec(w) \|\| will_fire_load_agen (w) \|\| will_fire_store_agen (w) \|\| will_fire_load_retry (w) \|\| will_fire_store_retry (w) , exe_tlb_uop(w).mem_cmd, Mux(will_fire_hella_incoming(w) , hella_req.cmd, Mux(will_fire_sfence (w) , rocket.M_SFENCE, 0.U)))) val exe_passthr= widthMap(w => Mux(will_fire_hella_incoming(w) , hella_req.phys, false.B)) val exe_kill = widthMap(w => Mux(will_fire_hella_incoming(w) , io.hellacache.s1_kill, false.B)) val bkptu = Seq.fill(lsuWidth) { Module(new rocket.BreakpointUnit(nBreakpoints)) } for (w <- 0 until lsuWidth) { dtlb.io.req(w).valid := exe_tlb_valid(w) dtlb.io.req(w).bits.vaddr := exe_tlb_vaddr(w) dtlb.io.req(w).bits.size := exe_size(w) dtlb.io.req(w).bits.cmd := exe_cmd(w) dtlb.io.req(w).bits.passthrough := exe_passthr(w) dtlb.io.req(w).bits.prv := io.ptw.status.prv dtlb.io.req(w).bits.v := io.ptw.status.v bkptu(w).io.status := io.core.status bkptu(w).io.bp := io.core.bp bkptu(w).io.pc := DontCare bkptu(w).io.ea := exe_tlb_vaddr(w) bkptu(w).io.mcontext := io.core.mcontext bkptu(w).io.scontext := io.core.scontext } dtlb.io.kill := exe_kill.reduce(_\|\|_) dtlb.io.sfence := exe_sfence // exceptions val ma_ld = widthMap(w => dtlb.io.resp(w).ma.ld && exe_tlb_uop(w).uses_ldq) val ma_st = widthMap(w => dtlb.io.resp(w).ma.st && exe_tlb_uop(w).uses_stq && !exe_tlb_uop(w).is_fence) val pf_ld = widthMap(w => dtlb.io.resp(w).pf.ld && exe_tlb_uop(w).uses_ldq) val pf_st = widthMap(w => dtlb.io.resp(w).pf.st && exe_tlb_uop(w).uses_stq) val ae_ld = widthMap(w => dtlb.io.resp(w).ae.ld && exe_tlb_uop(w).uses_ldq) val ae_st = widthMap(w => dtlb.io.resp(w).ae.st && exe_tlb_uop(w).uses_stq) val dbg_bp = widthMap(w => bkptu(w).io.debug_st && ((exe_tlb_uop(w).uses_ldq && bkptu(w).io.debug_ld) \|\| (exe_tlb_uop(w).uses_stq && bkptu(w).io.debug_st && !exe_tlb_uop(w).is_fence))) val bp = widthMap(w => bkptu(w).io.debug_st && ((exe_tlb_uop(w).uses_ldq && bkptu(w).io.xcpt_ld) \|\| (exe_tlb_uop(w).uses_stq && bkptu(w).io.xcpt_st && !exe_tlb_uop(w).is_fence))) // TODO check for xcpt_if and verify that never happens on non-speculative instructions. val mem_xcpt_valids = RegNext(widthMap(w => exe_tlb_valid(w) && (pf_ld(w) \|\| pf_st(w) \|\| ae_ld(w) \|\| ae_st(w) \|\| ma_ld(w) \|\| ma_st(w) \|\| dbg_bp(w) \|\| bp(w)) && !IsKilledByBranch(io.core.brupdate, io.core.exception, exe_tlb_uop(w)))) val mem_xcpt_uops = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_tlb_uop(w)))) val mem_xcpt_causes = RegNext(widthMap(w => Mux(dbg_bp(w), rocket.CSR.debugTriggerCause.U, Mux(bp (w), rocket.Causes.breakpoint.U, Mux(ma_st (w), rocket.Causes.misaligned_store.U, Mux(ma_ld (w), rocket.Causes.misaligned_load.U, Mux(pf_st (w), rocket.Causes.store_page_fault.U, Mux(pf_ld (w), rocket.Causes.load_page_fault.U, Mux(ae_st (w), rocket.Causes.store_access.U, Mux(ae_ld (w), rocket.Causes.load_access.U, 0.U)))))))))) val mem_xcpt_vaddrs = RegNext(exe_tlb_vaddr) for (w <- 0 until lsuWidth) { assert (!(dtlb.io.req(w).valid && exe_tlb_uop(w).is_fence), "Fence is pretending to talk to the TLB") } mem_xcpt_valid := mem_xcpt_valids.reduce(_\|\|_) mem_xcpt_cause := mem_xcpt_causes(0) mem_xcpt_uop := mem_xcpt_uops(0) mem_xcpt_vaddr := mem_xcpt_vaddrs(0) var xcpt_found = mem_xcpt_valids(0) var oldest_xcpt_rob_idx = mem_xcpt_uops(0).rob_idx for (w <- 1 until lsuWidth) { val is_older = WireInit(false.B) when (mem_xcpt_valids(w) && (IsOlder(mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx, io.core.rob_head_idx) \|\| !xcpt_found)) { is_older := true.B mem_xcpt_cause := mem_xcpt_causes(w) mem_xcpt_uop := mem_xcpt_uops(w) mem_xcpt_vaddr := mem_xcpt_vaddrs(w) } xcpt_found = xcpt_found \|\| mem_xcpt_valids(w) oldest_xcpt_rob_idx = Mux(is_older, mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx) } val exe_tlb_miss = widthMap(w => dtlb.io.req(w).valid && (dtlb.io.resp(w).miss \|\| !dtlb.io.req(w).ready)) val exe_tlb_paddr = widthMap(w => Cat(dtlb.io.resp(w).paddr(paddrBits-1,corePgIdxBits), exe_tlb_vaddr(w)(corePgIdxBits-1,0))) val exe_tlb_uncacheable = widthMap(w => !(dtlb.io.resp(w).cacheable)) for (w <- 0 until lsuWidth) { assert (exe_tlb_paddr(w) === dtlb.io.resp(w).paddr, "[lsu] paddrs should match.") when (mem_xcpt_valids(w)) { assert(RegNext(will_fire_load_agen_exec(w) \|\| will_fire_load_agen(w) \|\| will_fire_store_agen(w) \|\| will_fire_load_retry(w) \|\| will_fire_store_retry(w))) // Technically only faulting AMOs need this assert(mem_xcpt_uops(w).uses_ldq ^ mem_xcpt_uops(w).uses_stq) when (mem_xcpt_uops(w).uses_ldq) { ldq_uop(mem_xcpt_uops(w).ldq_idx).exception := true.B } .otherwise { stq_uop(mem_xcpt_uops(w).stq_idx).exception := true.B } } } val exe_agen_killed = widthMap(w => IsKilledByBranch(io.core.brupdate, io.core.exception, agen(w).bits.uop)) //------------------------------ // Issue Someting to Memory // // A memory op can come from many different places // The address either was freshly translated, or we are // reading a physical address from the LDQ,STQ, or the HellaCache adapter // defaults io.dmem.brupdate := io.core.brupdate io.dmem.exception := io.core.exception io.dmem.rob_head_idx := io.core.rob_head_idx io.dmem.rob_pnr_idx := io.core.rob_pnr_idx val dmem_req = Wire(Vec(lsuWidth, Valid(new BoomDCacheReq))) io.dmem.req.valid := dmem_req.map(_.valid).reduce(_\|\|_) io.dmem.req.bits := dmem_req val dmem_req_fire = widthMap(w => dmem_req(w).valid && io.dmem.req.fire) val s0_executing_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) val s0_kills = Wire(Vec(lsuWidth, Bool())) for (w <- 0 until lsuWidth) { dmem_req(w).valid := false.B dmem_req(w).bits.uop := NullMicroOp dmem_req(w).bits.addr := 0.U dmem_req(w).bits.data := 0.U dmem_req(w).bits.is_hella := false.B s0_kills(w) := false.B io.dmem.s1_kill(w) := RegNext(s0_kills(w) && dmem_req_fire(w)) when (will_fire_load_agen_exec(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.uop := exe_tlb_uop(w) s0_kills(w) := exe_tlb_miss(w) \|\| exe_tlb_uncacheable(w) \|\| ma_ld(w) \|\| ae_ld(w) \|\| pf_ld(w) s0_executing_loads(ldq_incoming_idx(w)) := dmem_req_fire(w) && !s0_kills(w) assert(!ldq_incoming_e(w).bits.executed) } .elsewhen (will_fire_load_retry(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.uop := exe_tlb_uop(w) s0_kills(w) := exe_tlb_miss(w) \|\| exe_tlb_uncacheable(w) \|\| ma_ld(w) \|\| ae_ld(w) \|\| pf_ld(w) s0_executing_loads(ldq_retry_idx) := dmem_req_fire(w) && !s0_kills(w) } .elsewhen (will_fire_store_commit_slow(w) \|\| will_fire_store_commit_fast(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := stq_commit_e.bits.addr.bits dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( stq_commit_e.bits.uop.mem_size, 0.U, stq_commit_e.bits.data.bits, coreDataBytes)).data dmem_req(w).bits.uop := stq_commit_e.bits.uop when (!dmem_req_fire(w)) { stq_execute_queue_flush := true.B stq_execute_head := stq_commit_e.bits.uop.stq_idx } stq_succeeded(stq_commit_e.bits.uop.stq_idx) := false.B } .elsewhen (will_fire_load_wakeup(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := ldq_wakeup_e.bits.addr.bits dmem_req(w).bits.uop := ldq_wakeup_e.bits.uop s0_executing_loads(ldq_wakeup_idx) := dmem_req_fire(w) assert(!ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.addr_is_virtual) } .elsewhen (will_fire_hella_incoming(w)) { assert(hella_state === h_s1) dmem_req(w).valid := !io.hellacache.s1_kill && (!exe_tlb_miss(w) \|\| hella_req.phys) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( hella_req.size, 0.U, io.hellacache.s1_data.data, coreDataBytes)).data dmem_req(w).bits.uop.mem_cmd := hella_req.cmd dmem_req(w).bits.uop.mem_size := hella_req.size dmem_req(w).bits.uop.mem_signed := hella_req.signed dmem_req(w).bits.is_hella := true.B hella_paddr := exe_tlb_paddr(w) } .elsewhen (will_fire_hella_wakeup(w)) { assert(hella_state === h_replay) dmem_req(w).valid := true.B dmem_req(w).bits.addr := hella_paddr dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( hella_req.size, 0.U, hella_data.data, coreDataBytes)).data dmem_req(w).bits.uop.mem_cmd := hella_req.cmd dmem_req(w).bits.uop.mem_size := hella_req.size dmem_req(w).bits.uop.mem_signed := hella_req.signed dmem_req(w).bits.is_hella := true.B } //------------------------------------------------------------- // Write Addr into the LAQ/SAQ when (will_fire_load_agen(w) \|\| will_fire_load_agen_exec(w) \|\| will_fire_load_retry(w)) { val ldq_idx = Mux(will_fire_load_agen(w) \|\| will_fire_load_agen_exec(w), ldq_incoming_idx(w), ldq_retry_idx) ldq_addr (ldq_idx).valid := !exe_agen_killed(w) \|\| will_fire_load_retry(w) ldq_addr (ldq_idx).bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w)) ldq_ld_byte_mask (ldq_idx) := GenByteMask(exe_tlb_vaddr(w), exe_tlb_uop(w).mem_size) ldq_uop (ldq_idx).pdst := exe_tlb_uop(w).pdst ldq_addr_is_virtual (ldq_idx) := exe_tlb_miss(w) ldq_addr_is_uncacheable(ldq_idx) := exe_tlb_uncacheable(w) && !exe_tlb_miss(w) assert(!ldq_addr(ldq_idx).valid, "[lsu] Translating load is overwriting a valid address") } when (will_fire_store_agen(w) \|\| will_fire_store_retry(w)) { val stq_idx = Mux(will_fire_store_agen(w), stq_incoming_idx(w), stq_retry_idx) stq_addr (stq_idx).valid := (!exe_agen_killed(w) \|\| will_fire_store_retry(w)) && !pf_st(w) // Prevent AMOs from executing! stq_addr (stq_idx).bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w)) stq_uop (stq_idx).pdst := exe_tlb_uop(w).pdst // Needed for AMOs stq_addr_is_virtual(stq_idx) := exe_tlb_miss(w) assert(!stq_addr(stq_idx).valid, "[lsu] Translating store is overwriting a valid address") } } //------------------------------------------------------------- // Write data into the STQ for (dgen <- io.core.dgen) { when (dgen.valid) { val sidx = dgen.bits.uop.stq_idx //val stq_e = WireInit(stq(sidx)) stq_data(sidx).valid := true.B stq_data(sidx).bits := dgen.bits.data assert(!stq_data(sidx).valid \|\| (stq_data(sidx).bits === dgen.bits.data)) } } require (xLen >= fLen) // for correct SDQ size //------------------------------------------------------------- // Speculative wakeup if loadUseDelay == 4 val wakeupArbs = Seq.fill(lsuWidth) { Module(new Arbiter(new Wakeup, 2)) } for (w <- 0 until lsuWidth) { wakeupArbs(w).io.out.ready := true.B wakeupArbs(w).io.in := DontCare io.core.iwakeups(w) := wakeupArbs(w).io.out if (enableFastLoadUse) { wakeupArbs(w).io.in(1).valid := (will_fire_load_agen_exec(w) && dmem_req_fire(w) && !agen(w).bits.uop.fp_val) wakeupArbs(w).io.in(1).bits.uop := agen(w).bits.uop wakeupArbs(w).io.in(1).bits.bypassable := true.B wakeupArbs(w).io.in(1).bits.speculative_mask := 0.U wakeupArbs(w).io.in(1).bits.rebusy := false.B } } //------------------------------------------------------------- //------------------------------------------------------------- // Cache Access Cycle (Mem) //------------------------------------------------------------- //------------------------------------------------------------- // Note the DCache may not have accepted our request val fired_load_agen_exec = widthMap(w => RegNext(will_fire_load_agen_exec(w) && !exe_agen_killed(w))) val fired_load_agen = widthMap(w => RegNext(will_fire_load_agen (w) && !exe_agen_killed(w))) val fired_store_agen = widthMap(w => RegNext(will_fire_store_agen (w) && !exe_agen_killed(w))) val fired_sfence = RegNext(will_fire_sfence) val fired_release = RegNext(will_fire_release) val fired_load_retry = widthMap(w => RegNext(will_fire_load_retry (w) && !IsKilledByBranch(io.core.brupdate, io.core.exception, retry_queue.io.deq.bits.uop))) val fired_store_retry = widthMap(w => RegNext(will_fire_store_retry (w) && !IsKilledByBranch(io.core.brupdate, io.core.exception, retry_queue.io.deq.bits.uop))) val fired_store_commit = widthMap(w => RegNext(will_fire_store_commit_slow(w) \|\| will_fire_store_commit_fast(w))) val fired_load_wakeup = widthMap(w => RegNext(will_fire_load_wakeup (w) && !IsKilledByBranch(io.core.brupdate, io.core.exception, ldq_wakeup_e.bits.uop))) val fired_hella_incoming = RegNext(will_fire_hella_incoming) val fired_hella_wakeup = RegNext(will_fire_hella_wakeup) val mem_incoming_uop = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, agen(w).bits.uop))) val mem_ldq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, io.core.exception, ldq_incoming_e(w)))) val mem_stq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, io.core.exception, stq_incoming_e(w)))) val mem_ldq_wakeup_e = RegNext(UpdateBrMask(io.core.brupdate, io.core.exception, ldq_wakeup_e)) val mem_ldq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, io.core.exception, ldq_read(ldq_retry_idx))) val mem_stq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, io.core.exception, stq_read(stq_retry_idx))) val mem_ldq_e = widthMap(w => Mux(fired_load_agen (w) \|\| fired_load_agen_exec(w), mem_ldq_incoming_e(w), Mux(fired_load_retry (w), mem_ldq_retry_e, Mux(fired_load_wakeup (w), mem_ldq_wakeup_e, (0.U).asTypeOf(Valid(new LDQEntry)))))) val mem_stq_e = widthMap(w => Mux(fired_store_agen (w), mem_stq_incoming_e(w), Mux(fired_store_retry(w), mem_stq_retry_e, (0.U).asTypeOf(Valid(new STQEntry))))) val mem_tlb_miss = RegNext(exe_tlb_miss) val mem_tlb_uncacheable = RegNext(exe_tlb_uncacheable) val mem_paddr = RegNext(widthMap(w => dmem_req(w).bits.addr)) // Task 1: Clr ROB busy bit val stq_clr_head_idx = RegNext(AgePriorityEncoder((0 until numStqEntries).map(i => { stq_valid(i) && !stq_cleared(i) }), stq_commit_head)) var clr_idx = stq_clr_head_idx for (i <- 0 until coreWidth) { // Delay store clearing 1 extra cycle, as the store clear can't occur // too quickly before an order fail caused by this store propagates to ROB val clr_valid = Reg(Bool()) clr_valid := false.B val clr_uop = Reg(new MicroOp) val clr_valid_1 = RegNext(clr_valid && !IsKilledByBranch(io.core.brupdate, io.core.exception, clr_uop)) val clr_uop_1 = RegNext(UpdateBrMask(io.core.brupdate, clr_uop)) //val stq_e = WireInit(stq(clr_idx)) val s_uop = WireInit(stq_uop(clr_idx)) when ( stq_valid (clr_idx) && stq_addr (clr_idx).valid && stq_data (clr_idx).valid && !stq_addr_is_virtual (clr_idx) && !s_uop.is_amo && !stq_cleared (clr_idx) && !IsKilledByBranch(io.core.brupdate, io.core.exception, s_uop)) { clr_valid := true.B clr_uop := UpdateBrMask(io.core.brupdate, s_uop) stq_cleared(clr_idx) := true.B } io.core.clr_bsy(i).valid := clr_valid_1 && !IsKilledByBranch(io.core.brupdate, io.core.exception, clr_uop_1) io.core.clr_bsy(i).bits := clr_uop_1.rob_idx clr_idx = WrapInc(clr_idx, numStqEntries) } // Task 2: Do LD-LD. ST-LD searches for ordering failures // Do LD-ST search for forwarding opportunities // We have the opportunity to kill a request we sent last cycle. Use it wisely! // We translated a store last cycle val do_st_search = widthMap(w => (fired_store_agen(w) \|\| fired_store_retry(w)) && !mem_tlb_miss(w)) // We translated a load last cycle val do_ld_search = widthMap(w => ((fired_load_agen(w) \|\| fired_load_agen_exec(w) \|\| fired_load_retry(w)) && !mem_tlb_miss(w)) \|\| fired_load_wakeup(w)) // We are making a local line visible to other harts val do_release_search = widthMap(w => fired_release(w)) // Store addrs don't go to memory yet, get it from the TLB response // Load wakeups don't go through TLB, get it through memory // Load incoming and load retries go through both val lcam_addr = widthMap(w => Mux(fired_store_agen(w) \|\| fired_store_retry(w) \|\| fired_load_agen(w) \|\| fired_load_agen_exec(w), RegNext(exe_tlb_paddr(w)), Mux(fired_release(w), RegNext(io.dmem.release.bits.address), mem_paddr(w)))) val lcam_uop = widthMap(w => Mux(do_st_search(w), mem_stq_e(w).bits.uop, Mux(do_ld_search(w), mem_ldq_e(w).bits.uop, NullMicroOp))) val lcam_mask = widthMap(w => GenByteMask(lcam_addr(w), lcam_uop(w).mem_size)) val lcam_st_dep_mask = widthMap(w => mem_ldq_e(w).bits.st_dep_mask) val lcam_is_release = widthMap(w => fired_release(w)) val lcam_ldq_idx = widthMap(w => Mux(fired_load_agen (w) \|\| fired_load_agen_exec(w) , mem_incoming_uop(w).ldq_idx, Mux(fired_load_wakeup (w), RegNext(ldq_wakeup_idx), Mux(fired_load_retry (w), RegNext(ldq_retry_idx), 0.U)))) val lcam_stq_idx = widthMap(w => Mux(fired_store_agen (w), mem_incoming_uop(w).stq_idx, Mux(fired_store_retry(w), RegNext(stq_retry_idx), 0.U))) val lcam_younger_load_mask = widthMap(w => IsYoungerMask(lcam_ldq_idx(w), ldq_head, numLdqEntries)) val can_forward = widthMap(w => Mux(fired_load_agen(w) \|\| fired_load_agen_exec(w) \|\| fired_load_retry(w), !mem_tlb_uncacheable(w), !mem_ldq_wakeup_e.bits.addr_is_uncacheable )) val kill_forward = WireInit(widthMap(w => false.B)) // Mask of stores which we conflict on address with val ldst_addr_matches = Wire(Vec(lsuWidth, UInt(numStqEntries.W))) // Mask of stores which we can forward from val ldst_forward_matches = Wire(Vec(lsuWidth, UInt(numStqEntries.W))) // Mask of stores we can forward to val stld_prs2_matches = Wire(Vec(lsuWidth, UInt(numStqEntries.W))) val s1_executing_loads = RegNext(s0_executing_loads) val s1_set_execute = WireInit(s1_executing_loads) val wb_ldst_forward_matches = RegNext(ldst_forward_matches) val wb_ldst_forward_valid = Wire(Vec(lsuWidth, Bool())) val wb_ldst_forward_e = widthMap(w => RegNext(UpdateBrMask(io.core.brupdate, ldq_read(lcam_ldq_idx(w)).bits))) val wb_ldst_forward_ldq_idx = RegNext(lcam_ldq_idx) val wb_ldst_forward_ld_addr = RegNext(lcam_addr) val wb_ldst_forward_stq_idx = Wire(Vec(lsuWidth, UInt(stqAddrSz.W))) val failed_load = WireInit(false.B) for (i <- 0 until numLdqEntries) { // val l_bits = ldq(i).bits val l_valid = ldq_valid(i) val l_addr = ldq_addr(i) val l_addr_is_virtual = ldq_addr_is_virtual(i) val l_executed = ldq_executed(i) val l_succeeded = ldq_succeeded(i) val l_will_succeed = ldq_will_succeed(i) val l_observed = ldq_observed(i) val l_mask = ldq_ld_byte_mask(i) val l_st_dep_mask = ldq_st_dep_mask(i) val l_uop = WireInit(ldq_uop(i)) val l_forward_std_val = ldq_forward_std_val(i) val l_forward_stq_idx = ldq_forward_stq_idx(i) val block_addr_matches = widthMap(w => lcam_addr(w) >> blockOffBits === l_addr.bits >> blockOffBits) val dword_addr_matches = widthMap(w => block_addr_matches(w) && lcam_addr(w)(blockOffBits-1,3) === l_addr.bits(blockOffBits-1,3)) val mask_match = widthMap(w => (l_mask & lcam_mask(w)) === l_mask) val mask_overlap = widthMap(w => (l_mask & lcam_mask(w)).orR) // Searcher is a store for (w <- 0 until lsuWidth) { when ( do_release_search(w) && l_valid && l_addr.valid && !l_addr_is_virtual && block_addr_matches(w)) { // This load has been observed, so if a younger load to the same address has not // executed yet, this load must be squashed ldq_observed(i) := true.B } when ( do_st_search(w) && l_valid && l_addr.valid && (l_executed \|\| l_succeeded) && !l_addr_is_virtual && l_st_dep_mask(lcam_stq_idx(w)) && dword_addr_matches(w) && mask_overlap(w)) { val forwarded_is_older = IsOlder(l_forward_stq_idx, lcam_stq_idx(w), l_uop.stq_idx) // We are older than this load, which overlapped us. when (!l_forward_std_val \|\| // If the load wasn't forwarded, it definitely failed ((l_forward_stq_idx =/= lcam_stq_idx(w)) && forwarded_is_older)) { // If the load forwarded from us, we might be ok ldq_order_fail(i) := true.B failed_load := true.B } } when ( do_ld_search(w) && l_valid && l_addr.valid && !l_addr_is_virtual && dword_addr_matches(w) && mask_overlap(w)) { val searcher_is_older = lcam_younger_load_mask(w)(i) assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older) when (searcher_is_older) { when ((l_executed \|\| l_succeeded) && !s1_executing_loads(i) && // If the load is proceeding in parallel we don't need to kill it l_observed) { // Its only a ordering failure if the cache line was observed between the younger load and us //ldq_order_fail(i) := true.B // failed_load := true.B // this case is no longer possible where an older search gets replayed and found that a younger search has already been released. Note that this is stronger than rvwmo. assert(false.B) } } .elsewhen (lcam_ldq_idx(w) =/= i.U) { // The load is older, and it wasn't executed // we need to kill ourselves, and prevent forwarding // can also forward from the next cycle when (!(l_executed && (l_succeeded \|\| l_will_succeed))) { s1_set_execute(lcam_ldq_idx(w)) := false.B when (RegNext(dmem_req_fire(w) && !s0_kills(w)) && !fired_load_agen(w)) { io.dmem.s1_kill(w) := true.B } kill_forward(w) := true.B } } } } } for (wi <- 0 until lsuWidth) { for (w <- 0 until lsuWidth) { // A younger load might find a older nacking load // this is not the full case, need also to account for the situation where the older load already went to sleep above val nack_dword_addr_matches = (lcam_addr(w) >> 3) === (io.dmem.nack(wi).bits.addr >> 3) val nack_mask = GenByteMask(io.dmem.nack(wi).bits.addr, io.dmem.nack(wi).bits.uop.mem_size) val nack_mask_overlap = (nack_mask & lcam_mask(w)) =/= 0.U when (do_ld_search(w) && io.dmem.nack(wi).valid && io.dmem.nack(wi).bits.uop.uses_ldq && nack_dword_addr_matches && nack_mask_overlap && IsOlder(io.dmem.nack(wi).bits.uop.ldq_idx, lcam_ldq_idx(w), ldq_head)) { s1_set_execute(lcam_ldq_idx(w)) := false.B when (RegNext(dmem_req_fire(w) && !s0_kills(w)) && !fired_load_agen(w)) { io.dmem.s1_kill(w) := true.B } kill_forward(w) := true.B } // A older load might find a younger forwarding load val forward_dword_addr_matches = (lcam_addr(w) >> 3 === wb_ldst_forward_ld_addr(wi) >> 3) val forward_mask = GenByteMask(wb_ldst_forward_ld_addr(wi), wb_ldst_forward_e(wi).uop.mem_size) val forward_mask_overlap = (forward_mask & lcam_mask(w)) =/= 0.U when (do_ld_search(w) && wb_ldst_forward_valid(wi) && forward_dword_addr_matches && forward_mask_overlap && wb_ldst_forward_e(wi).observed && IsOlder(lcam_ldq_idx(w), wb_ldst_forward_ldq_idx(wi), ldq_head)) { ldq_order_fail(wb_ldst_forward_ldq_idx(wi)) := true.B failed_load := true.B } // A older store might find a younger load which is forwarding from the wrong place val forwarded_is_older = IsOlder(wb_ldst_forward_stq_idx(wi), lcam_stq_idx(w), wb_ldst_forward_e(wi).uop.stq_idx) when (do_st_search(w) && wb_ldst_forward_valid(wi) && forward_dword_addr_matches && forward_mask_overlap && wb_ldst_forward_e(wi).st_dep_mask(lcam_stq_idx(w)) && forwarded_is_older) { ldq_order_fail(wb_ldst_forward_ldq_idx(wi)) := true.B failed_load := true.B } } } val addr_matches = Wire(Vec(lsuWidth, Vec(numStqEntries, Bool()))) val forward_matches = Wire(Vec(lsuWidth, Vec(numStqEntries, Bool()))) val prs2_matches = Wire(Vec(lsuWidth, Vec(numStqEntries, Bool()))) for (i <- 0 until numStqEntries) { //val s_e = WireInit(stq(i)) val s_addr = stq_addr(i) val s_data = stq_data(i) val s_addr_is_virtual = stq_addr_is_virtual(i) val s_uop = WireInit(stq_uop(i)) val write_mask = GenByteMask(s_addr.bits, s_uop.mem_size) for (w <- 0 until lsuWidth) { val dword_addr_matches = ( s_addr.valid && !s_uop.is_amo && !s_addr_is_virtual && (s_addr.bits(corePAddrBits-1,3) === lcam_addr(w)(corePAddrBits-1,3))) val mask_union = lcam_mask(w) & write_mask addr_matches(w)(i) := (mask_union =/= 0.U) && dword_addr_matches forward_matches(w)(i) := addr_matches(w)(i) && s_data.valid && (mask_union === lcam_mask(w)) prs2_matches(w)(i) := (s_uop.prs2 === lcam_uop(w).pdst && s_uop.lrs2_rtype === RT_FIX && enableLoadToStoreForwarding.B) } } val fast_stq_valids = stq_valid.asUInt for (w <- 0 until lsuWidth) { ldst_addr_matches(w) := (addr_matches(w).asUInt & lcam_st_dep_mask(w)) & fast_stq_valids ldst_forward_matches(w) := (forward_matches(w).asUInt & lcam_st_dep_mask(w)) & fast_stq_valids stld_prs2_matches(w) := (prs2_matches(w).asUInt & ~lcam_st_dep_mask(w)) & fast_stq_valids } val stq_amos = VecInit(stq_uop.map(u => u.is_fence \|\| u.is_amo)) for (w <- 0 until lsuWidth) { val has_older_amo = (stq_amos.asUInt & lcam_st_dep_mask(w)) =/= 0.U when (do_ld_search(w) && (has_older_amo \|\| (ldst_addr_matches(w) =/= 0.U))) { when (RegNext(dmem_req_fire(w) && !s0_kills(w)) && !fired_load_agen(w)) { io.dmem.s1_kill(w) := true.B } s1_set_execute(lcam_ldq_idx(w)) := false.B when (has_older_amo) { kill_forward(w) := true.B } } } // Set execute bit in LDQ for (i <- 0 until numLdqEntries) { when (s1_set_execute(i)) { ldq_executed(i) := true.B } } // Find the youngest store which the load is dependent on for (w <- 0 until lsuWidth) { val (youngest_matching, match_found) = ForwardingAgeLogic(numStqEntries, ldst_addr_matches(w), lcam_uop(w).stq_idx) val (youngest_forwarder, forwarder_found) = ForwardingAgeLogic(numStqEntries, ldst_forward_matches(w), lcam_uop(w).stq_idx) wb_ldst_forward_stq_idx(w) := youngest_forwarder // Forward if st-ld forwarding is possible from the writemask and loadmask wb_ldst_forward_valid(w) := (youngest_matching === youngest_forwarder && match_found && forwarder_found && RegNext(can_forward(w) && !kill_forward(w) && do_ld_search(w)) && !RegNext(IsKilledByBranch(io.core.brupdate, io.core.exception, lcam_uop(w)))) } // Avoid deadlock with a 1-w LSU prioritizing load wakeups > store commits // On a 2W machine, load wakeups and store commits occupy separate pipelines, // so only add this logic for 1-w LSU if (lsuWidth == 1) { // Wakeups may repeatedly find a st->ld addr conflict and fail to forward, // repeated wakeups may block the store from ever committing // Disallow load wakeups 1 cycle after this happens to allow the stores to drain when (RegNext(ldst_addr_matches(0) =/= 0.U) && !wb_ldst_forward_valid(0)) { block_load_wakeup := true.B } // If stores remain blocked for 15 cycles, block load wakeups to get a store through val store_blocked_counter = Reg(UInt(4.W)) when (will_fire_store_commit_fast(0) \|\| will_fire_store_commit_slow(0) \|\| !can_fire_store_commit_slow(0)) { store_blocked_counter := 0.U } .elsewhen (can_fire_store_commit_slow(0) && !(will_fire_store_commit_slow(0) \|\| will_fire_store_commit_fast(0))) { store_blocked_counter := Mux(store_blocked_counter === 15.U, 15.U, store_blocked_counter + 1.U) } when (store_blocked_counter === 15.U) { block_load_wakeup := true.B } } // Forward this load to the youngest matching store val mem_stld_forward_stq_idx = widthMap(w => AgePriorityEncoder(stld_prs2_matches(w).asBools, lcam_uop(w).stq_idx)) val mem_stld_forward_valid = widthMap(w => do_ld_search(w) && stld_prs2_matches(w)(mem_stld_forward_stq_idx(w))) // Task 3: Clr unsafe bit in ROB for succesful t_ranslations // Delay this a cycle to avoid going ahead of the exception broadcast // The unsafe bit is cleared on the first translation, so no need to fire for load wakeups for (w <- 0 until lsuWidth) { io.core.clr_unsafe(w).valid := ( RegNext(do_st_search(w)) \|\| (!io.dmem.nack(w).valid && RegNext(do_ld_search(w) && !fired_load_agen(w) && !io.dmem.s1_kill(w) && RegNext(dmem_req_fire(w)))) ) && !RegNext(failed_load) io.core.clr_unsafe(w).bits := RegNext(lcam_uop(w).rob_idx) } // detect which loads get marked as failures, but broadcast to the ROB the oldest failing load // TODO encapsulate this in an age-based priority-encoder val l_idx = AgePriorityEncoder((0 until numLdqEntries).map { i => ldq_valid(i) && ldq_order_fail(i) }, ldq_head) // one exception port, but multiple causes! // - 1) the incoming store-address finds a faulting load (it is by definition younger) // - 2) the incoming load or store address is excepting. It must be older and thus takes precedent. val r_xcpt_valid = RegInit(false.B) val r_xcpt = Reg(new Exception) val ld_xcpt_valid = (ldq_order_fail.asUInt & ldq_valid.asUInt) =/= 0.U val ld_xcpt_uop = WireInit(ldq_uop(Mux(l_idx >= numLdqEntries.U, l_idx - numLdqEntries.U, l_idx))) val use_mem_xcpt = (mem_xcpt_valid && IsOlder(mem_xcpt_uop.rob_idx, ld_xcpt_uop.rob_idx, io.core.rob_head_idx)) \|\| !ld_xcpt_valid val xcpt_uop = Mux(use_mem_xcpt, mem_xcpt_uop, ld_xcpt_uop) r_xcpt_valid := (ld_xcpt_valid \|\| mem_xcpt_valid) && !IsKilledByBranch(io.core.brupdate, io.core.exception, xcpt_uop) r_xcpt.uop := xcpt_uop r_xcpt.uop.br_mask := GetNewBrMask(io.core.brupdate, xcpt_uop) r_xcpt.cause := Mux(use_mem_xcpt, mem_xcpt_cause, MINI_EXCEPTION_MEM_ORDERING) r_xcpt.badvaddr := mem_xcpt_vaddr // TODO is there another register we can use instead? io.core.lxcpt.valid := r_xcpt_valid && !IsKilledByBranch(io.core.brupdate, io.core.exception, r_xcpt.uop) io.core.lxcpt.bits := r_xcpt // Task 4: Speculatively wakeup loads 1 cycle before they come back // if loadUseDelay == 5 for (w <- 0 until lsuWidth) { if (!enableFastLoadUse) { wakeupArbs(w).io.in(1).valid := (fired_load_agen_exec(w) && RegNext(dmem_req_fire(w)) && !io.dmem.s1_nack_advisory(w) && !mem_incoming_uop(w).fp_val) wakeupArbs(w).io.in(1).bits.uop := mem_incoming_uop(w) wakeupArbs(w).io.in(1).bits.bypassable := true.B wakeupArbs(w).io.in(1).bits.speculative_mask := 0.U wakeupArbs(w).io.in(1).bits.rebusy := false.B } } //------------------------------------------------------------- //------------------------------------------------------------- // Writeback Cycle (St->Ld Forwarding Path) //------------------------------------------------------------- //------------------------------------------------------------- // Handle Memory Responses and nacks //---------------------------------- val iresp = Wire(Vec(lsuWidth, Valid(new ExeUnitResp(xLen)))) val fresp = Wire(Vec(lsuWidth, Valid(new ExeUnitResp(xLen)))) for (w <- 0 until lsuWidth) { iresp(w).valid := false.B iresp(w).bits := DontCare fresp(w).valid := false.B fresp(w).bits := DontCare io.core.iresp(w) := (if (enableFastLoadUse) iresp(w) else RegNext( UpdateBrMask(io.core.brupdate, io.core.exception, iresp(w)))) io.core.fresp(w) := fresp(w) } // Initially assume the speculative load wakeup failed val wb_spec_wakeups = Wire(Vec(lsuWidth, Valid(new Wakeup))) val spec_wakeups = Wire(Vec(lsuWidth, Valid(new Wakeup))) val wb_slow_wakeups = Wire(Vec(lsuWidth, Valid(new Wakeup))) val slow_wakeups = Wire(Vec(lsuWidth, Valid(new Wakeup))) val dmem_resp_fired = WireInit(widthMap(w => false.B)) for (w <- 0 until lsuWidth) { val w1 = Reg(Valid(new Wakeup)) w1.valid := wakeupArbs(w).io.in(1).fire && !IsKilledByBranch(io.core.brupdate, io.core.exception, wakeupArbs(w).io.in(1).bits) w1.bits := UpdateBrMask(io.core.brupdate, wakeupArbs(w).io.in(1).bits) val w2 = Reg(Valid(new Wakeup)) w2.valid := w1.valid && !IsKilledByBranch(io.core.brupdate, io.core.exception, w1.bits) w2.bits := UpdateBrMask(io.core.brupdate, w1.bits) spec_wakeups(w).valid := w2.valid spec_wakeups(w).bits := w2.bits wb_spec_wakeups(w) := (if (enableFastLoadUse) w2 else w1) } for (w <- 0 until lsuWidth) { wb_slow_wakeups(w).valid := false.B wb_slow_wakeups(w).bits := DontCare // Handle nacks when (io.dmem.nack(w).valid) { when (io.dmem.nack(w).bits.is_hella) { assert(hella_state === h_wait \|\| hella_state === h_dead) } .elsewhen (io.dmem.nack(w).bits.uop.uses_ldq) { assert(ldq_executed(io.dmem.nack(w).bits.uop.ldq_idx)) ldq_executed(io.dmem.nack(w).bits.uop.ldq_idx) := false.B } .otherwise { assert(io.dmem.nack(w).bits.uop.uses_stq) when (IsOlder(io.dmem.nack(w).bits.uop.stq_idx, stq_execute_head, stq_head)) { stq_execute_queue_flush := true.B stq_execute_head := io.dmem.nack(w).bits.uop.stq_idx } } } // Handle the response val resp = Mux(!io.dmem.resp(w).valid && (w == lsuWidth-1).B, io.dmem.ll_resp.bits, io.dmem.resp(w).bits) if (w == lsuWidth-1) { io.dmem.ll_resp.ready := !io.dmem.resp(w).valid && !wb_spec_wakeups(w).valid } when (io.dmem.resp(w).valid \|\| ((w == lsuWidth-1).B && io.dmem.ll_resp.fire)) { when (resp.uop.uses_ldq) { assert(!resp.is_hella) val ldq_idx = resp.uop.ldq_idx val uop = WireInit(ldq_uop(ldq_idx)) val send_iresp = uop.dst_rtype === RT_FIX val send_fresp = uop.dst_rtype === RT_FLT iresp(w).bits.uop := uop fresp(w).bits.uop := uop iresp(w).valid := send_iresp iresp(w).bits.data := resp.data fresp(w).valid := send_fresp fresp(w).bits.data := resp.data assert(send_iresp ^ send_fresp) dmem_resp_fired(w) := true.B ldq_will_succeed (ldq_idx) := iresp(w).valid \|\| fresp(w).valid ldq_debug_wb_data(ldq_idx) := resp.data wb_slow_wakeups(w).valid := send_iresp wb_slow_wakeups(w).bits.uop := uop wb_slow_wakeups(w).bits.speculative_mask := 0.U wb_slow_wakeups(w).bits.rebusy := false.B wb_slow_wakeups(w).bits.bypassable := false.B } when (resp.uop.uses_stq) { val uop = stq_uop(resp.uop.stq_idx) assert(!resp.is_hella && resp.uop.is_amo) dmem_resp_fired(w) := true.B iresp(w).valid := true.B iresp(w).bits.uop := uop iresp(w).bits.data := resp.data wb_slow_wakeups(w).valid := true.B wb_slow_wakeups(w).bits.uop := uop wb_slow_wakeups(w).bits.speculative_mask := 0.U wb_slow_wakeups(w).bits.rebusy := false.B wb_slow_wakeups(w).bits.bypassable := false.B stq_debug_wb_data(resp.uop.stq_idx) := resp.data } } // Handle store acks when (io.dmem.store_ack(w).valid) { stq_succeeded(io.dmem.store_ack(w).bits.uop.stq_idx) := true.B } when (dmem_resp_fired(w) && wb_ldst_forward_valid(w)) { // Twiddle thumbs. Can't forward because dcache response takes precedence } .elsewhen (!dmem_resp_fired(w) && wb_ldst_forward_valid(w)) { val f_idx = wb_ldst_forward_ldq_idx(w) val forward_uop = wb_ldst_forward_e(w).uop //val stq_e = WireInit(stq(wb_ldst_forward_stq_idx(w))) val s_idx = wb_ldst_forward_stq_idx(w) val storegen = new freechips.rocketchip.rocket.StoreGen( stq_uop(s_idx).mem_size, stq_addr(s_idx).bits, stq_data(s_idx).bits, coreDataBytes) val loadgen = new freechips.rocketchip.rocket.LoadGen( forward_uop.mem_size, forward_uop.mem_signed, wb_ldst_forward_ld_addr(w), storegen.data, false.B, coreDataBytes) wb_slow_wakeups(w).valid := forward_uop.dst_rtype === RT_FIX wb_slow_wakeups(w).bits.uop := forward_uop wb_slow_wakeups(w).bits.speculative_mask := 0.U wb_slow_wakeups(w).bits.rebusy := false.B wb_slow_wakeups(w).bits.bypassable := false.B iresp(w).valid := (forward_uop.dst_rtype === RT_FIX) fresp(w).valid := (forward_uop.dst_rtype === RT_FLT) iresp(w).bits.uop := forward_uop fresp(w).bits.uop := forward_uop iresp(w).bits.data := loadgen.data fresp(w).bits.data := loadgen.data ldq_will_succeed (f_idx) := true.B ldq_forward_std_val(f_idx) := true.B ldq_forward_stq_idx(f_idx) := wb_ldst_forward_stq_idx(w) ldq_debug_wb_data (f_idx) := loadgen.data } // Forward loads to store-data if (enableStLdForwarding) { when (iresp(w).valid && iresp(w).bits.uop.uses_ldq && iresp(w).bits.uop.ldq_idx === RegNext(lcam_ldq_idx(w)) && RegNext(mem_stld_forward_valid(w))) { assert(!stq_data(RegNext(mem_stld_forward_stq_idx(w))).valid) stq_data(RegNext(mem_stld_forward_stq_idx(w))).valid := true.B stq_data(RegNext(mem_stld_forward_stq_idx(w))).bits := iresp(w).bits.data } } // Do wakeups wakeupArbs(w).io.in(0).valid := false.B wakeupArbs(w).io.in(0).bits := DontCare slow_wakeups(w) := (if (enableFastLoadUse) wb_slow_wakeups(w) else RegNext(UpdateBrMask( io.core.brupdate, io.core.exception, wb_slow_wakeups(w)))) when (slow_wakeups(w).valid) { when (spec_wakeups(w).valid) { // Do nothing, since the slow wakeup matches a earlier speculative wakeup assert(slow_wakeups(w).bits.uop.ldq_idx === spec_wakeups(w).bits.uop.ldq_idx) } .otherwise { // This wasn't speculatively woken up, so end the late slow wakeup wakeupArbs(w).io.in(0).valid := slow_wakeups(w).valid wakeupArbs(w).io.in(0).bits := slow_wakeups(w).bits } } .otherwise { when (spec_wakeups(w).valid) { // This sent a speculative wakeup, now we need to undo it wakeupArbs(w).io.in(0).valid := spec_wakeups(w).valid wakeupArbs(w).io.in(0).bits := spec_wakeups(w).bits wakeupArbs(w).io.in(0).bits.rebusy := true.B } } } //------------------------------------------------------------- // Kill speculated entries on branch mispredict //------------------------------------------------------------- //------------------------------------------------------------- // Kill stores for (i <- 0 until numStqEntries) { when (stq_valid(i)) { val uop = WireInit(stq_uop(i)) stq_uop(i).br_mask := GetNewBrMask(io.core.brupdate, uop.br_mask) when (IsKilledByBranch(io.core.brupdate, false.B, uop)) { stq_valid(i) := false.B stq_addr (i).valid := false.B stq_data (i).valid := false.B } } assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)), "Branch is trying to clear a committed store.") } // Kill loads for (i <- 0 until numLdqEntries) { when (ldq_valid(i)) { val uop = WireInit(ldq_uop(i)) ldq_uop(i).br_mask := GetNewBrMask(io.core.brupdate, uop.br_mask) when (IsKilledByBranch(io.core.brupdate, io.core.exception, uop)) { ldq_valid(i) := false.B ldq_addr (i).valid := false.B } } } //------------------------------------------------------------- when (io.core.brupdate.b2.mispredict && !io.core.exception) { stq_tail := io.core.brupdate.b2.uop.stq_idx ldq_tail := io.core.brupdate.b2.uop.ldq_idx } //------------------------------------------------------------- //------------------------------------------------------------- // dequeue old entries on commit //------------------------------------------------------------- //------------------------------------------------------------- var temp_stq_commit_head = stq_commit_head var temp_ldq_head = ldq_head for (w <- 0 until coreWidth) { val commit_store = io.core.commit.valids(w) && io.core.commit.uops(w).uses_stq val commit_load = io.core.commit.valids(w) && io.core.commit.uops(w).uses_ldq // val stq_e = WireInit(stq(temp_stq_commit_head)) // val ldq_e = WireInit(ldq(temp_ldq_head)) val l_uop = WireInit(ldq_uop(temp_ldq_head)) val s_uop = WireInit(stq_uop(temp_stq_commit_head)) when (commit_store) { stq_committed (temp_stq_commit_head) := true.B stq_can_execute(temp_stq_commit_head) := true.B } .elsewhen (commit_load) { assert (ldq_valid(temp_ldq_head), "[lsu] trying to commit an un-allocated load entry.") assert ((ldq_executed(temp_ldq_head) \|\| ldq_forward_std_val(temp_ldq_head)) && ldq_succeeded(temp_ldq_head), "[lsu] trying to commit an un-executed load entry.") ldq_valid(temp_ldq_head) := false.B } if (MEMTRACE_PRINTF) { when (commit_store \|\| commit_load) { val uop = Mux(commit_store, s_uop, l_uop) val addr = Mux(commit_store, stq_addr(temp_stq_commit_head).bits , ldq_addr(temp_ldq_head).bits) val stdata = Mux(commit_store, stq_data(temp_stq_commit_head).bits , 0.U) val wbdata = Mux(commit_store, stq_debug_wb_data(temp_stq_commit_head), ldq_debug_wb_data(temp_ldq_head)) printf("MT %x %x %x %x %x %x %x\n", io.core.tsc_reg, 0.U, uop.mem_cmd, uop.mem_size, addr, stdata, wbdata) } } temp_stq_commit_head = Mux(commit_store, WrapInc(temp_stq_commit_head, numStqEntries), temp_stq_commit_head) temp_ldq_head = Mux(commit_load, WrapInc(temp_ldq_head, numLdqEntries), temp_ldq_head) } stq_commit_head := temp_stq_commit_head ldq_head := temp_ldq_head // store has been committed AND successfully sent data to memory val stq_head_is_fence = stq_uop(stq_head).is_fence when (stq_valid(stq_head) && stq_committed(stq_head)) { when (stq_head_is_fence && !io.dmem.ordered) { io.dmem.force_order := true.B store_needs_order := true.B } clear_store := Mux(stq_head_is_fence, io.dmem.ordered, stq_succeeded(stq_head)) } when (clear_store) { stq_valid(stq_head) := false.B stq_head := WrapInc(stq_head, numStqEntries) when (stq_head_is_fence) { stq_execute_head := WrapInc(stq_execute_head, numStqEntries) } } // ----------------------- // Hellacache interface // We need to time things like a HellaCache would io.hellacache.req.ready := false.B io.hellacache.s2_nack := false.B io.hellacache.s2_nack_cause_raw := false.B io.hellacache.s2_uncached := DontCare io.hellacache.s2_paddr := DontCare io.hellacache.s2_xcpt := (0.U).asTypeOf(new rocket.HellaCacheExceptions) io.hellacache.replay_next := false.B io.hellacache.s2_gpa := DontCare io.hellacache.s2_gpa_is_pte := DontCare io.hellacache.ordered := DontCare io.hellacache.perf := DontCare io.hellacache.clock_enabled := true.B io.hellacache.store_pending := stq_valid.reduce(_\|\|_) io.hellacache.resp.valid := false.B io.hellacache.resp.bits.addr := hella_req.addr io.hellacache.resp.bits.tag := hella_req.tag io.hellacache.resp.bits.cmd := hella_req.cmd io.hellacache.resp.bits.signed := hella_req.signed io.hellacache.resp.bits.size := hella_req.size io.hellacache.resp.bits.mask := hella_req.mask io.hellacache.resp.bits.replay := false.B io.hellacache.resp.bits.has_data := true.B io.hellacache.resp.bits.data_word_bypass := io.dmem.ll_resp.bits.data io.hellacache.resp.bits.data_raw := io.dmem.ll_resp.bits.data io.hellacache.resp.bits.store_data := hella_req.data io.hellacache.resp.bits.dprv := io.ptw.status.prv io.hellacache.resp.bits.dv := io.ptw.status.v io.hellacache.resp.bits.data := io.dmem.ll_resp.bits.data when (hella_state === h_ready) { io.hellacache.req.ready := true.B when (io.hellacache.req.fire) { hella_req := io.hellacache.req.bits hella_state := h_s1 } } .elsewhen (hella_state === h_s1) { can_fire_hella_incoming(0) := true.B hella_data := io.hellacache.s1_data hella_xcpt := dtlb.io.resp(0) when (io.hellacache.s1_kill) { when (will_fire_hella_incoming(0) && dmem_req_fire(0)) { hella_state := h_dead } .otherwise { hella_state := h_ready } } .elsewhen (will_fire_hella_incoming(0) && dmem_req_fire(0)) { hella_state := h_s2 } .otherwise { hella_state := h_s2_nack } } .elsewhen (hella_state === h_s2_nack) { io.hellacache.s2_nack := true.B hella_state := h_ready } .elsewhen (hella_state === h_s2) { io.hellacache.s2_xcpt := hella_xcpt when (io.hellacache.s2_kill \|\| hella_xcpt.asUInt =/= 0.U) { hella_state := h_dead } .otherwise { hella_state := h_wait } } .elsewhen (hella_state === h_wait) { when (io.dmem.ll_resp.fire && io.dmem.ll_resp.bits.is_hella) { hella_state := h_ready io.hellacache.resp.valid := true.B io.hellacache.resp.bits.addr := hella_req.addr io.hellacache.resp.bits.tag := hella_req.tag io.hellacache.resp.bits.cmd := hella_req.cmd io.hellacache.resp.bits.signed := hella_req.signed io.hellacache.resp.bits.size := hella_req.size io.hellacache.resp.bits.data := io.dmem.ll_resp.bits.data } for (w <- 0 until lsuWidth) { when ((io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) \|\| (io.dmem.store_ack(w).valid && io.dmem.store_ack(w).bits.is_hella)) { hella_state := h_ready io.hellacache.resp.valid := true.B io.hellacache.resp.bits.addr := hella_req.addr io.hellacache.resp.bits.tag := hella_req.tag io.hellacache.resp.bits.cmd := hella_req.cmd io.hellacache.resp.bits.signed := hella_req.signed io.hellacache.resp.bits.size := hella_req.size io.hellacache.resp.bits.data := io.dmem.resp(w).bits.data } when (io.dmem.nack(w).valid && io.dmem.nack(w).bits.is_hella) { hella_state := h_replay } } } .elsewhen (hella_state === h_replay) { can_fire_hella_wakeup(0) := true.B when (will_fire_hella_wakeup(0) && dmem_req_fire(0)) { hella_state := h_wait } } .elsewhen (hella_state === h_dead) { when (io.dmem.ll_resp.fire && io.dmem.ll_resp.bits.is_hella) { hella_state := h_ready } for (w <- 0 until lsuWidth) { when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) { hella_state := h_ready } } } //------------------------------------------------------------- // Exception / Reset when (reset.asBool \|\| io.core.exception) { ldq_head := 0.U ldq_tail := 0.U when (reset.asBool) { stq_head := 0.U stq_tail := 0.U stq_commit_head := 0.U stq_execute_head := 0.U for (i <- 0 until numStqEntries) { stq_valid(i) := false.B } } .otherwise // exception { stq_tail := stq_commit_head for (i <- 0 until numStqEntries) { when (!stq_committed(i) && !stq_succeeded(i)) { stq_valid(i) := false.B } } } for (i <- 0 until numLdqEntries) { ldq_valid(i) := false.B } } } /* * Object to take an address and generate an 8-bit mask of which bytes within a * double-word. / object GenByteMask { def apply(addr: UInt, size: UInt): UInt = { val mask = Wire(UInt(8.W)) mask := MuxCase(255.U(8.W), Array( (size === 0.U) -> (1.U(8.W) << addr(2,0)), (size === 1.U) -> (3.U(8.W) << (addr(2,1) << 1.U)), (size === 2.U) -> Mux(addr(2), 240.U(8.W), 15.U(8.W)), (size === 3.U) -> 255.U(8.W))) mask } } object ForwardingAgeLogic { def apply(n: Int, matches: UInt, youngest: UInt): (UInt, Bool) = { val logic = Module(new ForwardingAgeLogic(n)) logic.io.matches := matches logic.io.youngest := youngest (logic.io.found_idx, logic.io.found) } } class ForwardingAgeLogic(n: Int) extends Module() { val io = IO(new Bundle { val matches = Input(UInt(n.W)) // bit vector of addresses that match // between the load and the SAQ val youngest = Input(UInt(log2Ceil(n).W)) // needed to get "age" val found = Output(Bool()) val found_idx = Output(UInt(log2Ceil(n).W)) }) // generating mask that zeroes out anything younger than tail val age_mask = Wire(Vec(n, Bool())) for (i <- 0 until n) { age_mask(i) := true.B when (i.U >= io.youngest) // currently the tail points PAST last store, so use >= { age_mask(i) := false.B } } // Priority encoder with moving tail: double length val matches = Wire(UInt((2n).W)) matches := Cat(io.matches & age_mask.asUInt, io.matches) val found_match = Reg(Bool()) val found_idx = Reg(UInt(log2Ceil(n).W)) found_match := false.B found_idx := 0.U io.found_idx := found_idx io.found := found_match // look for youngest, approach from the oldest side, let the last one found stick for (i <- 0 until (2n)) { when (matches(i)) { found_match := true.B found_idx := (i % n).U } } } File util.scala: //*************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File consts.scala: //**************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander / * Mixin for scalar operation constants / trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //********************************* // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 3 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_4 = 3.U(BSRC_SZ.W) // 4-cycle branch pred val BSRC_C = 4.U(BSRC_SZ.W) // core branch resolution //******************************** // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val B_N = 0.U(4.W) // Next val B_NE = 1.U(4.W) // Branch on NotEqual val B_EQ = 2.U(4.W) // Branch on Equal val B_GE = 3.U(4.W) // Branch on Greater/Equal val B_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val B_LT = 5.U(4.W) // Branch on Less Than val B_LTU = 6.U(4.W) // Branch on Less Than Unsigned val B_J = 7.U(4.W) // Jump val B_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_RS1SHL = 3.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_RS2OH = 5.U(3.W) val OP2_IMMOH = 6.U(3.W) val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_SH = 5.U(3.W) // short-type (sign extend from pimm to get imm) val IS_N = 6.U(3.W) // No immediate (zeros immediate) val IS_F3 = 7.U(3.W) // funct3 // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_X = 2.U(2.W) // not-a-register (prs1 = lrs1 special case) val RT_ZERO = 3.U(2.W) // IQT type val IQ_SZ = 4 val IQ_MEM = 0 val IQ_UNQ = 1 val IQ_ALU = 2 val IQ_FP = 3 // Functional unit select // bit mask, since a given execution pipeline may support multiple functional units val FC_SZ = 10 val FC_ALU = 0 val FC_AGEN = 1 val FC_DGEN = 2 val FC_MUL = 3 val FC_DIV = 4 val FC_CSR = 5 val FC_FPU = 6 val FC_FDV = 7 val FC_I2F = 8 val FC_F2I = 9 def NullMicroOp(implicit p: Parameters) = 0.U.asTypeOf(new boom.v4.common.MicroOp) } / * Mixin for RISCV constants / trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v4.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /* * Mixin for exception cause constants / trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out }	module LSU( // @[lsu.scala:211:7] input clock, // @[lsu.scala:211:7] input reset, // @[lsu.scala:211:7] input io_ptw_req_ready, // @[lsu.scala:214:14] output io_ptw_req_valid, // @[lsu.scala:214:14] output io_ptw_req_bits_valid, // @[lsu.scala:214:14] output [26:0] io_ptw_req_bits_bits_addr, // @[lsu.scala:214:14] input io_ptw_resp_valid, // @[lsu.scala:214:14] input io_ptw_resp_bits_ae_ptw, // @[lsu.scala:214:14] input io_ptw_resp_bits_ae_final, // @[lsu.scala:214:14] input io_ptw_resp_bits_pf, // @[lsu.scala:214:14] input io_ptw_resp_bits_gf, // @[lsu.scala:214:14] input io_ptw_resp_bits_hr, // @[lsu.scala:214:14] input io_ptw_resp_bits_hw, // @[lsu.scala:214:14] input io_ptw_resp_bits_hx, // @[lsu.scala:214:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[lsu.scala:214:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[lsu.scala:214:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_d, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_a, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_g, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_u, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_x, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_w, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_r, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_v, // @[lsu.scala:214:14] input [1:0] io_ptw_resp_bits_level, // @[lsu.scala:214:14] input io_ptw_resp_bits_homogeneous, // @[lsu.scala:214:14] input io_ptw_resp_bits_gpa_valid, // @[lsu.scala:214:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[lsu.scala:214:14] input io_ptw_resp_bits_gpa_is_pte, // @[lsu.scala:214:14] input [3:0] io_ptw_ptbr_mode, // @[lsu.scala:214:14] input [43:0] io_ptw_ptbr_ppn, // @[lsu.scala:214:14] input io_ptw_status_debug, // @[lsu.scala:214:14] input io_ptw_status_cease, // @[lsu.scala:214:14] input io_ptw_status_wfi, // @[lsu.scala:214:14] input [1:0] io_ptw_status_dprv, // @[lsu.scala:214:14] input io_ptw_status_dv, // @[lsu.scala:214:14] input [1:0] io_ptw_status_prv, // @[lsu.scala:214:14] input io_ptw_status_v, // @[lsu.scala:214:14] input io_ptw_status_sd, // @[lsu.scala:214:14] input io_ptw_status_mpv, // @[lsu.scala:214:14] input io_ptw_status_gva, // @[lsu.scala:214:14] input io_ptw_status_tsr, // @[lsu.scala:214:14] input io_ptw_status_tw, // @[lsu.scala:214:14] input io_ptw_status_tvm, // @[lsu.scala:214:14] input io_ptw_status_mxr, // @[lsu.scala:214:14] input io_ptw_status_sum, // @[lsu.scala:214:14] input io_ptw_status_mprv, // @[lsu.scala:214:14] input [1:0] io_ptw_status_fs, // @[lsu.scala:214:14] input [1:0] io_ptw_status_mpp, // @[lsu.scala:214:14] input io_ptw_status_spp, // @[lsu.scala:214:14] input io_ptw_status_mpie, // @[lsu.scala:214:14] input io_ptw_status_spie, // @[lsu.scala:214:14] input io_ptw_status_mie, // @[lsu.scala:214:14] input io_ptw_status_sie, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_0_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_0_mask, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_1_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_1_mask, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_2_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_2_mask, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_3_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_3_mask, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_4_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_4_mask, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_5_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_5_mask, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_6_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_6_mask, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_7_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_7_mask, // @[lsu.scala:214:14] input io_core_agen_0_valid, // @[lsu.scala:214:14] input [31:0] io_core_agen_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_agen_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_agen_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_agen_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_agen_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_agen_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_taken, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_agen_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_agen_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_agen_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_agen_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_agen_0_bits_data, // @[lsu.scala:214:14] input io_core_dgen_0_valid, // @[lsu.scala:214:14] input [31:0] io_core_dgen_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_dgen_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dgen_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_dgen_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dgen_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dgen_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_taken, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dgen_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_dgen_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_dgen_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_dgen_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_dgen_0_bits_data, // @[lsu.scala:214:14] input io_core_dgen_1_valid, // @[lsu.scala:214:14] input [31:0] io_core_dgen_1_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_dgen_1_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dgen_1_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_dgen_1_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dgen_1_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dgen_1_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_taken, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dgen_1_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_dgen_1_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_dgen_1_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_dgen_1_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_dgen_1_bits_data, // @[lsu.scala:214:14] input io_core_dgen_2_valid, // @[lsu.scala:214:14] input [31:0] io_core_dgen_2_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_dgen_2_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dgen_2_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_dgen_2_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dgen_2_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dgen_2_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_taken, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dgen_2_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_dgen_2_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_dgen_2_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_dgen_2_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_dgen_2_bits_data, // @[lsu.scala:214:14] output io_core_iwakeups_0_valid, // @[lsu.scala:214:14] output [31:0] io_core_iwakeups_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_iwakeups_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_iwakeups_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [11:0] io_core_iwakeups_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_iwakeups_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_iwakeups_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_taken, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_iwakeups_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [3:0] io_core_iwakeups_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [3:0] io_core_iwakeups_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_iwakeups_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_bypassable, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_speculative_mask, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_rebusy, // @[lsu.scala:214:14] output io_core_iresp_0_valid, // @[lsu.scala:214:14] output [31:0] io_core_iresp_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_iresp_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_iresp_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [11:0] io_core_iresp_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_iresp_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_iresp_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_taken, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_iresp_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [3:0] io_core_iresp_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [3:0] io_core_iresp_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_iresp_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [63:0] io_core_iresp_0_bits_data, // @[lsu.scala:214:14] output io_core_fresp_0_valid, // @[lsu.scala:214:14] output [31:0] io_core_fresp_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_fresp_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_fresp_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [11:0] io_core_fresp_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_fresp_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_fresp_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_taken, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_fresp_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [3:0] io_core_fresp_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [3:0] io_core_fresp_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_fresp_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [63:0] io_core_fresp_0_bits_data, // @[lsu.scala:214:14] input io_core_sfence_valid, // @[lsu.scala:214:14] input io_core_sfence_bits_rs1, // @[lsu.scala:214:14] input io_core_sfence_bits_rs2, // @[lsu.scala:214:14] input [38:0] io_core_sfence_bits_addr, // @[lsu.scala:214:14] input io_core_sfence_bits_asid, // @[lsu.scala:214:14] input io_core_sfence_bits_hv, // @[lsu.scala:214:14] input io_core_sfence_bits_hg, // @[lsu.scala:214:14] input io_core_dis_uops_0_valid, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_0_bits_inst, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_0_bits_debug_inst, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dis_uops_0_bits_debug_pc, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_0, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_1, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_2, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_3, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_0, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_1, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_2, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_3, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_4, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_5, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_6, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_7, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_8, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_9, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_issued, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_dis_uops_0_bits_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_0_bits_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_0_bits_br_type, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_sfb, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_fence, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_fencei, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_sfence, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_amo, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_eret, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_rocc, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_ftq_idx, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_pc_lob, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_taken, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dis_uops_0_bits_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_op2_sel, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_0_bits_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_0_bits_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_ppred, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_prs1_busy, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_prs2_busy, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_prs3_busy, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_stale_pdst, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_exception, // @[lsu.scala:214:14] input [63:0] io_core_dis_uops_0_bits_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_mem_size, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_mem_signed, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_uses_ldq, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_uses_stq, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_unique, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_csr_cmd, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_frs3_en, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_fcn_op, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_fp_typ, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_bp_debug_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_debug_tsrc, // @[lsu.scala:214:14] input io_core_dis_uops_1_valid, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_1_bits_inst, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_1_bits_debug_inst, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dis_uops_1_bits_debug_pc, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_0, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_1, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_2, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_3, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_0, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_1, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_2, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_3, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_4, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_5, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_6, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_7, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_8, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_9, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_issued, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_dis_uops_1_bits_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_1_bits_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_1_bits_br_type, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_sfb, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_fence, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_fencei, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_sfence, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_amo, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_eret, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_rocc, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_ftq_idx, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_pc_lob, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_taken, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dis_uops_1_bits_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_op2_sel, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_1_bits_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_1_bits_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_ppred, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_prs1_busy, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_prs2_busy, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_prs3_busy, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_stale_pdst, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_exception, // @[lsu.scala:214:14] input [63:0] io_core_dis_uops_1_bits_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_mem_size, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_mem_signed, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_uses_ldq, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_uses_stq, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_unique, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_csr_cmd, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_frs3_en, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_fcn_op, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_fp_typ, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_bp_debug_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_debug_tsrc, // @[lsu.scala:214:14] output [3:0] io_core_dis_ldq_idx_0, // @[lsu.scala:214:14] output [3:0] io_core_dis_ldq_idx_1, // @[lsu.scala:214:14] output [3:0] io_core_dis_stq_idx_0, // @[lsu.scala:214:14] output [3:0] io_core_dis_stq_idx_1, // @[lsu.scala:214:14] output io_core_ldq_full_0, // @[lsu.scala:214:14] output io_core_ldq_full_1, // @[lsu.scala:214:14] output io_core_stq_full_0, // @[lsu.scala:214:14] output io_core_stq_full_1, // @[lsu.scala:214:14] input io_core_commit_valids_0, // @[lsu.scala:214:14] input io_core_commit_valids_1, // @[lsu.scala:214:14] input io_core_commit_arch_valids_0, // @[lsu.scala:214:14] input io_core_commit_arch_valids_1, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_0_inst, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_0_debug_inst, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_commit_uops_0_debug_pc, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_0, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_1, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_2, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_3, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_0, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_1, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_2, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_3, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_4, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_5, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_6, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_7, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_8, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_9, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_issued, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_commit_uops_0_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_0_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_0_br_type, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_sfb, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_fence, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_fencei, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_sfence, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_amo, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_eret, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_rocc, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_ftq_idx, // @[lsu.scala:214:14] input io_core_commit_uops_0_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_pc_lob, // @[lsu.scala:214:14] input io_core_commit_uops_0_taken, // @[lsu.scala:214:14] input io_core_commit_uops_0_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_pimm, // @[lsu.scala:214:14] input [19:0] io_core_commit_uops_0_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_op2_sel, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_0_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_0_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_pdst, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_prs1, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_prs2, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_prs3, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_ppred, // @[lsu.scala:214:14] input io_core_commit_uops_0_prs1_busy, // @[lsu.scala:214:14] input io_core_commit_uops_0_prs2_busy, // @[lsu.scala:214:14] input io_core_commit_uops_0_prs3_busy, // @[lsu.scala:214:14] input io_core_commit_uops_0_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_stale_pdst, // @[lsu.scala:214:14] input io_core_commit_uops_0_exception, // @[lsu.scala:214:14] input [63:0] io_core_commit_uops_0_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_mem_size, // @[lsu.scala:214:14] input io_core_commit_uops_0_mem_signed, // @[lsu.scala:214:14] input io_core_commit_uops_0_uses_ldq, // @[lsu.scala:214:14] input io_core_commit_uops_0_uses_stq, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_unique, // @[lsu.scala:214:14] input io_core_commit_uops_0_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_csr_cmd, // @[lsu.scala:214:14] input io_core_commit_uops_0_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_ldst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_lrs2_rtype, // @[lsu.scala:214:14] input io_core_commit_uops_0_frs3_en, // @[lsu.scala:214:14] input io_core_commit_uops_0_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_fcn_op, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_fp_typ, // @[lsu.scala:214:14] input io_core_commit_uops_0_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_bp_debug_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_debug_tsrc, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_1_inst, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_1_debug_inst, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_commit_uops_1_debug_pc, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_0, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_1, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_2, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_3, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_0, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_1, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_2, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_3, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_4, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_5, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_6, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_7, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_8, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_9, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_issued, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_commit_uops_1_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_1_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_1_br_type, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_sfb, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_fence, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_fencei, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_sfence, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_amo, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_eret, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_rocc, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_ftq_idx, // @[lsu.scala:214:14] input io_core_commit_uops_1_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_pc_lob, // @[lsu.scala:214:14] input io_core_commit_uops_1_taken, // @[lsu.scala:214:14] input io_core_commit_uops_1_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_pimm, // @[lsu.scala:214:14] input [19:0] io_core_commit_uops_1_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_op2_sel, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_1_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_1_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_pdst, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_prs1, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_prs2, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_prs3, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_ppred, // @[lsu.scala:214:14] input io_core_commit_uops_1_prs1_busy, // @[lsu.scala:214:14] input io_core_commit_uops_1_prs2_busy, // @[lsu.scala:214:14] input io_core_commit_uops_1_prs3_busy, // @[lsu.scala:214:14] input io_core_commit_uops_1_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_stale_pdst, // @[lsu.scala:214:14] input io_core_commit_uops_1_exception, // @[lsu.scala:214:14] input [63:0] io_core_commit_uops_1_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_mem_size, // @[lsu.scala:214:14] input io_core_commit_uops_1_mem_signed, // @[lsu.scala:214:14] input io_core_commit_uops_1_uses_ldq, // @[lsu.scala:214:14] input io_core_commit_uops_1_uses_stq, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_unique, // @[lsu.scala:214:14] input io_core_commit_uops_1_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_csr_cmd, // @[lsu.scala:214:14] input io_core_commit_uops_1_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_ldst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_lrs2_rtype, // @[lsu.scala:214:14] input io_core_commit_uops_1_frs3_en, // @[lsu.scala:214:14] input io_core_commit_uops_1_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_fcn_op, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_fp_typ, // @[lsu.scala:214:14] input io_core_commit_uops_1_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_bp_debug_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_debug_tsrc, // @[lsu.scala:214:14] input io_core_commit_fflags_valid, // @[lsu.scala:214:14] input [4:0] io_core_commit_fflags_bits, // @[lsu.scala:214:14] input [63:0] io_core_commit_debug_wdata_0, // @[lsu.scala:214:14] input [63:0] io_core_commit_debug_wdata_1, // @[lsu.scala:214:14] input io_core_commit_load_at_rob_head, // @[lsu.scala:214:14] output io_core_clr_bsy_0_valid, // @[lsu.scala:214:14] output [5:0] io_core_clr_bsy_0_bits, // @[lsu.scala:214:14] output io_core_clr_bsy_1_valid, // @[lsu.scala:214:14] output [5:0] io_core_clr_bsy_1_bits, // @[lsu.scala:214:14] output io_core_clr_unsafe_0_valid, // @[lsu.scala:214:14] output [5:0] io_core_clr_unsafe_0_bits, // @[lsu.scala:214:14] input io_core_fence_dmem, // @[lsu.scala:214:14] input [11:0] io_core_brupdate_b1_resolve_mask, // @[lsu.scala:214:14] input [11:0] io_core_brupdate_b1_mispredict_mask, // @[lsu.scala:214:14] input [31:0] io_core_brupdate_b2_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_brupdate_b2_uop_debug_inst, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_brupdate_b2_uop_debug_pc, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_issued, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_brupdate_b2_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_brupdate_b2_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_brupdate_b2_uop_br_type, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_sfb, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_fence, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_fencei, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_sfence, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_amo, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_eret, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_rocc, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_pc_lob, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_taken, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_brupdate_b2_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_op2_sel, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_brupdate_b2_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_brupdate_b2_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_ppred, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_brupdate_b2_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_mem_size, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_mem_signed, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_uses_stq, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_unique, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_frs3_en, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_fcn_op, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_fp_typ, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:214:14] input io_core_brupdate_b2_mispredict, // @[lsu.scala:214:14] input io_core_brupdate_b2_taken, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_cfi_type, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_pc_sel, // @[lsu.scala:214:14] input [39:0] io_core_brupdate_b2_jalr_target, // @[lsu.scala:214:14] input [20:0] io_core_brupdate_b2_target_offset, // @[lsu.scala:214:14] input [5:0] io_core_rob_pnr_idx, // @[lsu.scala:214:14] input [5:0] io_core_rob_head_idx, // @[lsu.scala:214:14] input io_core_exception, // @[lsu.scala:214:14] output io_core_fencei_rdy, // @[lsu.scala:214:14] output io_core_lxcpt_valid, // @[lsu.scala:214:14] output [31:0] io_core_lxcpt_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_lxcpt_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_lxcpt_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [11:0] io_core_lxcpt_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_lxcpt_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_lxcpt_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_taken, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_lxcpt_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_rob_idx, // @[lsu.scala:214:14] output [3:0] io_core_lxcpt_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [3:0] io_core_lxcpt_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_lxcpt_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_cause, // @[lsu.scala:214:14] output [39:0] io_core_lxcpt_bits_badvaddr, // @[lsu.scala:214:14] input [63:0] io_core_tsc_reg, // @[lsu.scala:214:14] input io_core_status_debug, // @[lsu.scala:214:14] input io_core_status_cease, // @[lsu.scala:214:14] input io_core_status_wfi, // @[lsu.scala:214:14] input [1:0] io_core_status_dprv, // @[lsu.scala:214:14] input io_core_status_dv, // @[lsu.scala:214:14] input [1:0] io_core_status_prv, // @[lsu.scala:214:14] input io_core_status_v, // @[lsu.scala:214:14] input io_core_status_sd, // @[lsu.scala:214:14] input io_core_status_mpv, // @[lsu.scala:214:14] input io_core_status_gva, // @[lsu.scala:214:14] input io_core_status_tsr, // @[lsu.scala:214:14] input io_core_status_tw, // @[lsu.scala:214:14] input io_core_status_tvm, // @[lsu.scala:214:14] input io_core_status_mxr, // @[lsu.scala:214:14] input io_core_status_sum, // @[lsu.scala:214:14] input io_core_status_mprv, // @[lsu.scala:214:14] input [1:0] io_core_status_fs, // @[lsu.scala:214:14] input [1:0] io_core_status_mpp, // @[lsu.scala:214:14] input io_core_status_spp, // @[lsu.scala:214:14] input io_core_status_mpie, // @[lsu.scala:214:14] input io_core_status_spie, // @[lsu.scala:214:14] input io_core_status_mie, // @[lsu.scala:214:14] input io_core_status_sie, // @[lsu.scala:214:14] output io_core_perf_acquire, // @[lsu.scala:214:14] output io_core_perf_release, // @[lsu.scala:214:14] output io_core_perf_tlbMiss, // @[lsu.scala:214:14] input io_dmem_req_ready, // @[lsu.scala:214:14] output io_dmem_req_valid, // @[lsu.scala:214:14] output io_dmem_req_bits_0_valid, // @[lsu.scala:214:14] output [31:0] io_dmem_req_bits_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_dmem_req_bits_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_dmem_req_bits_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [11:0] io_dmem_req_bits_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_dmem_req_bits_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_dmem_req_bits_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_taken, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_dmem_req_bits_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [3:0] io_dmem_req_bits_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [3:0] io_dmem_req_bits_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_dmem_req_bits_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [39:0] io_dmem_req_bits_0_bits_addr, // @[lsu.scala:214:14] output [63:0] io_dmem_req_bits_0_bits_data, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_is_hella, // @[lsu.scala:214:14] output io_dmem_s1_kill_0, // @[lsu.scala:214:14] input io_dmem_resp_0_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_resp_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_resp_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_resp_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_dmem_resp_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_resp_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_resp_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_resp_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_resp_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_resp_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_resp_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_dmem_resp_0_bits_data, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_is_hella, // @[lsu.scala:214:14] input io_dmem_store_ack_0_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_store_ack_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_store_ack_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_store_ack_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_dmem_store_ack_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_store_ack_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_store_ack_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_store_ack_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_store_ack_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_store_ack_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_store_ack_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [39:0] io_dmem_store_ack_0_bits_addr, // @[lsu.scala:214:14] input [63:0] io_dmem_store_ack_0_bits_data, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_is_hella, // @[lsu.scala:214:14] input io_dmem_nack_0_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_nack_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_nack_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_nack_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_dmem_nack_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_nack_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_nack_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_nack_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_nack_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_nack_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_nack_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [39:0] io_dmem_nack_0_bits_addr, // @[lsu.scala:214:14] input [63:0] io_dmem_nack_0_bits_data, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_is_hella, // @[lsu.scala:214:14] output io_dmem_ll_resp_ready, // @[lsu.scala:214:14] input io_dmem_ll_resp_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_ll_resp_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_ll_resp_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_ll_resp_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_dmem_ll_resp_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_ll_resp_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_ll_resp_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_ll_resp_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_ll_resp_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_ll_resp_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_ll_resp_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_dmem_ll_resp_bits_data, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_is_hella, // @[lsu.scala:214:14] output [11:0] io_dmem_brupdate_b1_resolve_mask, // @[lsu.scala:214:14] output [11:0] io_dmem_brupdate_b1_mispredict_mask, // @[lsu.scala:214:14] output [31:0] io_dmem_brupdate_b2_uop_inst, // @[lsu.scala:214:14] output [31:0] io_dmem_brupdate_b2_uop_debug_inst, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_dmem_brupdate_b2_uop_debug_pc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_0, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_1, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_2, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_3, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_0, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_1, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_2, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_3, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_4, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_5, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_6, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_7, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_8, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_9, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_issued, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_dis_col_sel, // @[lsu.scala:214:14] output [11:0] io_dmem_brupdate_b2_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_dmem_brupdate_b2_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_dmem_brupdate_b2_uop_br_type, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_sfb, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_fence, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_fencei, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_sfence, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_amo, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_eret, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_rocc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_ftq_idx, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_pc_lob, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_taken, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_dmem_brupdate_b2_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_op2_sel, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_rob_idx, // @[lsu.scala:214:14] output [3:0] io_dmem_brupdate_b2_uop_ldq_idx, // @[lsu.scala:214:14] output [3:0] io_dmem_brupdate_b2_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_ppred, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_prs1_busy, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_prs2_busy, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_prs3_busy, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_stale_pdst, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_exception, // @[lsu.scala:214:14] output [63:0] io_dmem_brupdate_b2_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_mem_size, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_mem_signed, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_uses_ldq, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_uses_stq, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_unique, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_csr_cmd, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_frs3_en, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_fcn_op, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_fp_typ, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_mispredict, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_taken, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_cfi_type, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_pc_sel, // @[lsu.scala:214:14] output [39:0] io_dmem_brupdate_b2_jalr_target, // @[lsu.scala:214:14] output [20:0] io_dmem_brupdate_b2_target_offset, // @[lsu.scala:214:14] output io_dmem_exception, // @[lsu.scala:214:14] output [5:0] io_dmem_rob_pnr_idx, // @[lsu.scala:214:14] output [5:0] io_dmem_rob_head_idx, // @[lsu.scala:214:14] output io_dmem_release_ready, // @[lsu.scala:214:14] input io_dmem_release_valid, // @[lsu.scala:214:14] input [2:0] io_dmem_release_bits_opcode, // @[lsu.scala:214:14] input [2:0] io_dmem_release_bits_param, // @[lsu.scala:214:14] input [3:0] io_dmem_release_bits_size, // @[lsu.scala:214:14] input [1:0] io_dmem_release_bits_source, // @[lsu.scala:214:14] input [31:0] io_dmem_release_bits_address, // @[lsu.scala:214:14] input [63:0] io_dmem_release_bits_data, // @[lsu.scala:214:14] output io_dmem_force_order, // @[lsu.scala:214:14] input io_dmem_ordered, // @[lsu.scala:214:14] input io_dmem_perf_acquire, // @[lsu.scala:214:14] input io_dmem_perf_release, // @[lsu.scala:214:14] output io_hellacache_req_ready, // @[lsu.scala:214:14] input io_hellacache_req_valid, // @[lsu.scala:214:14] input [39:0] io_hellacache_req_bits_addr, // @[lsu.scala:214:14] input io_hellacache_req_bits_dv, // @[lsu.scala:214:14] input io_hellacache_s1_kill, // @[lsu.scala:214:14] output io_hellacache_s2_nack, // @[lsu.scala:214:14] output io_hellacache_resp_valid, // @[lsu.scala:214:14] output [39:0] io_hellacache_resp_bits_addr, // @[lsu.scala:214:14] output [1:0] io_hellacache_resp_bits_dprv, // @[lsu.scala:214:14] output io_hellacache_resp_bits_dv, // @[lsu.scala:214:14] output [63:0] io_hellacache_resp_bits_data, // @[lsu.scala:214:14] output [63:0] io_hellacache_resp_bits_data_word_bypass, // @[lsu.scala:214:14] output [63:0] io_hellacache_resp_bits_data_raw, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ma_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ma_st, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_pf_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_pf_st, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_gf_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_gf_st, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ae_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ae_st, // @[lsu.scala:214:14] output io_hellacache_store_pending // @[lsu.scala:214:14] ); wire [2:0] wb_slow_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_ldst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1494:29] wire [63:0] wb_slow_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_exception; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_ppred; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_prs3; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_prs2; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_prs1; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_pdst; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1494:29] wire [3:0] wb_slow_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1494:29] wire [3:0] wb_slow_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1494:29] wire [19:0] wb_slow_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_pimm; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_taken; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1494:29] wire [3:0] wb_slow_wakeups_0_bits_uop_br_type; // @[lsu.scala:1494:29] wire [3:0] wb_slow_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1494:29] wire [39:0] wb_slow_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1494:29] wire [31:0] wb_slow_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1494:29] wire [31:0] wb_slow_wakeups_0_bits_uop_inst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1494:29] wire [63:0] iresp_0_bits_data; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_debug_tsrc; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_debug_fsrc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_bp_debug_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_fp_typ; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_fp_rm; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_val; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_fcn_op; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fcn_dw; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_frs3_en; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_lrs2_rtype; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_lrs1_rtype; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_dst_rtype; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_lrs3; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_lrs2; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_lrs1; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_ldst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_csr_cmd; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_flush_on_commit; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_unique; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_uses_stq; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_uses_ldq; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_mem_signed; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_mem_size; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_mem_cmd; // @[lsu.scala:1477:19] wire [63:0] iresp_0_bits_uop_exc_cause; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_exception; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_stale_pdst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_ppred_busy; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_prs3_busy; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_prs2_busy; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_prs1_busy; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_ppred; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_prs3; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_prs2; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_prs1; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_pdst; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_rxq_idx; // @[lsu.scala:1477:19] wire [3:0] iresp_0_bits_uop_stq_idx; // @[lsu.scala:1477:19] wire [3:0] iresp_0_bits_uop_ldq_idx; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_rob_idx; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_op2_sel; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_op1_sel; // @[lsu.scala:1477:19] wire [19:0] iresp_0_bits_uop_imm_packed; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_pimm; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_imm_sel; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_imm_rename; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_taken; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_pc_lob; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_edge_inst; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_ftq_idx; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_mov; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_rocc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_eret; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_amo; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_sfence; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_fencei; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_fence; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_sfb; // @[lsu.scala:1477:19] wire [3:0] iresp_0_bits_uop_br_type; // @[lsu.scala:1477:19] wire [3:0] iresp_0_bits_uop_br_tag; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_dis_col_sel; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_issued; // @[lsu.scala:1477:19] wire [39:0] iresp_0_bits_uop_debug_pc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_rvc; // @[lsu.scala:1477:19] wire [31:0] iresp_0_bits_uop_debug_inst; // @[lsu.scala:1477:19] wire [31:0] iresp_0_bits_uop_inst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_9; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_8; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_7; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_6; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_5; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_4; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_3; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_2; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_1; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_0; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_3; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_2; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_1; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_0; // @[lsu.scala:1477:19] wire [63:0] wb_ldst_forward_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] wb_ldst_forward_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [15:0] wb_ldst_forward_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_observed; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_order_fail; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_succeeded; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_executed; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] wb_ldst_forward_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] wb_ldst_forward_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] wb_ldst_forward_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] wb_ldst_forward_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] wb_ldst_forward_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] wb_ldst_forward_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire [2:0] s_uop_1_debug_tsrc; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_debug_fsrc; // @[lsu.scala:1093:25] wire s_uop_1_bp_xcpt_if; // @[lsu.scala:1093:25] wire s_uop_1_bp_debug_if; // @[lsu.scala:1093:25] wire s_uop_1_xcpt_ma_if; // @[lsu.scala:1093:25] wire s_uop_1_xcpt_ae_if; // @[lsu.scala:1093:25] wire s_uop_1_xcpt_pf_if; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_fp_typ; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_fp_rm; // @[lsu.scala:1093:25] wire s_uop_1_fp_val; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_fcn_op; // @[lsu.scala:1093:25] wire s_uop_1_fcn_dw; // @[lsu.scala:1093:25] wire s_uop_1_frs3_en; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_lrs2_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_lrs1_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_dst_rtype; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_lrs3; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_lrs2; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_lrs1; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_ldst; // @[lsu.scala:1093:25] wire s_uop_1_ldst_is_rs1; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_csr_cmd; // @[lsu.scala:1093:25] wire s_uop_1_flush_on_commit; // @[lsu.scala:1093:25] wire s_uop_1_is_unique; // @[lsu.scala:1093:25] wire s_uop_1_uses_stq; // @[lsu.scala:1093:25] wire s_uop_1_uses_ldq; // @[lsu.scala:1093:25] wire s_uop_1_mem_signed; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_mem_size; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_mem_cmd; // @[lsu.scala:1093:25] wire [63:0] s_uop_1_exc_cause; // @[lsu.scala:1093:25] wire s_uop_1_exception; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_stale_pdst; // @[lsu.scala:1093:25] wire s_uop_1_ppred_busy; // @[lsu.scala:1093:25] wire s_uop_1_prs3_busy; // @[lsu.scala:1093:25] wire s_uop_1_prs2_busy; // @[lsu.scala:1093:25] wire s_uop_1_prs1_busy; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_ppred; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_prs3; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_prs2; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_prs1; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_pdst; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_rxq_idx; // @[lsu.scala:1093:25] wire [3:0] s_uop_1_stq_idx; // @[lsu.scala:1093:25] wire [3:0] s_uop_1_ldq_idx; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_rob_idx; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_op2_sel; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_op1_sel; // @[lsu.scala:1093:25] wire [19:0] s_uop_1_imm_packed; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_pimm; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_imm_sel; // @[lsu.scala:1093:25] wire s_uop_1_imm_rename; // @[lsu.scala:1093:25] wire s_uop_1_taken; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_pc_lob; // @[lsu.scala:1093:25] wire s_uop_1_edge_inst; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_ftq_idx; // @[lsu.scala:1093:25] wire s_uop_1_is_mov; // @[lsu.scala:1093:25] wire s_uop_1_is_rocc; // @[lsu.scala:1093:25] wire s_uop_1_is_sys_pc2epc; // @[lsu.scala:1093:25] wire s_uop_1_is_eret; // @[lsu.scala:1093:25] wire s_uop_1_is_amo; // @[lsu.scala:1093:25] wire s_uop_1_is_sfence; // @[lsu.scala:1093:25] wire s_uop_1_is_fencei; // @[lsu.scala:1093:25] wire s_uop_1_is_fence; // @[lsu.scala:1093:25] wire s_uop_1_is_sfb; // @[lsu.scala:1093:25] wire [3:0] s_uop_1_br_type; // @[lsu.scala:1093:25] wire [3:0] s_uop_1_br_tag; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_dis_col_sel; // @[lsu.scala:1093:25] wire s_uop_1_iw_p3_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_1_iw_p2_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_1_iw_p1_bypass_hint; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_iw_p2_speculative_child; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_iw_p1_speculative_child; // @[lsu.scala:1093:25] wire s_uop_1_iw_issued_partial_dgen; // @[lsu.scala:1093:25] wire s_uop_1_iw_issued_partial_agen; // @[lsu.scala:1093:25] wire s_uop_1_iw_issued; // @[lsu.scala:1093:25] wire [39:0] s_uop_1_debug_pc; // @[lsu.scala:1093:25] wire s_uop_1_is_rvc; // @[lsu.scala:1093:25] wire [31:0] s_uop_1_debug_inst; // @[lsu.scala:1093:25] wire [31:0] s_uop_1_inst; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_vec; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_wflags; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_sqrt; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_div; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_fma; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_toint; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_fromint; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_swap23; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_swap12; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ren3; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ren2; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ren1; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_wen; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ldst; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_9; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_8; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_7; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_6; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_5; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_4; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_3; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_2; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_1; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_0; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_3; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_2; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_1; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_0; // @[lsu.scala:1093:25] wire [2:0] s_uop_debug_tsrc; // @[lsu.scala:1093:25] wire [2:0] s_uop_debug_fsrc; // @[lsu.scala:1093:25] wire s_uop_bp_xcpt_if; // @[lsu.scala:1093:25] wire s_uop_bp_debug_if; // @[lsu.scala:1093:25] wire s_uop_xcpt_ma_if; // @[lsu.scala:1093:25] wire s_uop_xcpt_ae_if; // @[lsu.scala:1093:25] wire s_uop_xcpt_pf_if; // @[lsu.scala:1093:25] wire [1:0] s_uop_fp_typ; // @[lsu.scala:1093:25] wire [2:0] s_uop_fp_rm; // @[lsu.scala:1093:25] wire s_uop_fp_val; // @[lsu.scala:1093:25] wire [4:0] s_uop_fcn_op; // @[lsu.scala:1093:25] wire s_uop_fcn_dw; // @[lsu.scala:1093:25] wire s_uop_frs3_en; // @[lsu.scala:1093:25] wire [1:0] s_uop_lrs2_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_lrs1_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_dst_rtype; // @[lsu.scala:1093:25] wire [5:0] s_uop_lrs3; // @[lsu.scala:1093:25] wire [5:0] s_uop_lrs2; // @[lsu.scala:1093:25] wire [5:0] s_uop_lrs1; // @[lsu.scala:1093:25] wire [5:0] s_uop_ldst; // @[lsu.scala:1093:25] wire s_uop_ldst_is_rs1; // @[lsu.scala:1093:25] wire [2:0] s_uop_csr_cmd; // @[lsu.scala:1093:25] wire s_uop_flush_on_commit; // @[lsu.scala:1093:25] wire s_uop_is_unique; // @[lsu.scala:1093:25] wire s_uop_uses_stq; // @[lsu.scala:1093:25] wire s_uop_uses_ldq; // @[lsu.scala:1093:25] wire s_uop_mem_signed; // @[lsu.scala:1093:25] wire [1:0] s_uop_mem_size; // @[lsu.scala:1093:25] wire [4:0] s_uop_mem_cmd; // @[lsu.scala:1093:25] wire [63:0] s_uop_exc_cause; // @[lsu.scala:1093:25] wire s_uop_exception; // @[lsu.scala:1093:25] wire [6:0] s_uop_stale_pdst; // @[lsu.scala:1093:25] wire s_uop_ppred_busy; // @[lsu.scala:1093:25] wire s_uop_prs3_busy; // @[lsu.scala:1093:25] wire s_uop_prs2_busy; // @[lsu.scala:1093:25] wire s_uop_prs1_busy; // @[lsu.scala:1093:25] wire [4:0] s_uop_ppred; // @[lsu.scala:1093:25] wire [6:0] s_uop_prs3; // @[lsu.scala:1093:25] wire [6:0] s_uop_prs2; // @[lsu.scala:1093:25] wire [6:0] s_uop_prs1; // @[lsu.scala:1093:25] wire [6:0] s_uop_pdst; // @[lsu.scala:1093:25] wire [1:0] s_uop_rxq_idx; // @[lsu.scala:1093:25] wire [3:0] s_uop_stq_idx; // @[lsu.scala:1093:25] wire [3:0] s_uop_ldq_idx; // @[lsu.scala:1093:25] wire [5:0] s_uop_rob_idx; // @[lsu.scala:1093:25] wire [2:0] s_uop_op2_sel; // @[lsu.scala:1093:25] wire [1:0] s_uop_op1_sel; // @[lsu.scala:1093:25] wire [19:0] s_uop_imm_packed; // @[lsu.scala:1093:25] wire [4:0] s_uop_pimm; // @[lsu.scala:1093:25] wire [2:0] s_uop_imm_sel; // @[lsu.scala:1093:25] wire s_uop_imm_rename; // @[lsu.scala:1093:25] wire s_uop_taken; // @[lsu.scala:1093:25] wire [5:0] s_uop_pc_lob; // @[lsu.scala:1093:25] wire s_uop_edge_inst; // @[lsu.scala:1093:25] wire [4:0] s_uop_ftq_idx; // @[lsu.scala:1093:25] wire s_uop_is_mov; // @[lsu.scala:1093:25] wire s_uop_is_rocc; // @[lsu.scala:1093:25] wire s_uop_is_sys_pc2epc; // @[lsu.scala:1093:25] wire s_uop_is_eret; // @[lsu.scala:1093:25] wire s_uop_is_amo; // @[lsu.scala:1093:25] wire s_uop_is_sfence; // @[lsu.scala:1093:25] wire s_uop_is_fencei; // @[lsu.scala:1093:25] wire s_uop_is_fence; // @[lsu.scala:1093:25] wire s_uop_is_sfb; // @[lsu.scala:1093:25] wire [3:0] s_uop_br_type; // @[lsu.scala:1093:25] wire [3:0] s_uop_br_tag; // @[lsu.scala:1093:25] wire [1:0] s_uop_dis_col_sel; // @[lsu.scala:1093:25] wire s_uop_iw_p3_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_iw_p2_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_iw_p1_bypass_hint; // @[lsu.scala:1093:25] wire [1:0] s_uop_iw_p2_speculative_child; // @[lsu.scala:1093:25] wire [1:0] s_uop_iw_p1_speculative_child; // @[lsu.scala:1093:25] wire s_uop_iw_issued_partial_dgen; // @[lsu.scala:1093:25] wire s_uop_iw_issued_partial_agen; // @[lsu.scala:1093:25] wire s_uop_iw_issued; // @[lsu.scala:1093:25] wire [39:0] s_uop_debug_pc; // @[lsu.scala:1093:25] wire s_uop_is_rvc; // @[lsu.scala:1093:25] wire [31:0] s_uop_debug_inst; // @[lsu.scala:1093:25] wire [31:0] s_uop_inst; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_vec; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_wflags; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_sqrt; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_div; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_fma; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_fastpipe; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_toint; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_fromint; // @[lsu.scala:1093:25] wire [1:0] s_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1093:25] wire [1:0] s_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_swap23; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_swap12; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ren3; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ren2; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ren1; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_wen; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ldst; // @[lsu.scala:1093:25] wire s_uop_fu_code_9; // @[lsu.scala:1093:25] wire s_uop_fu_code_8; // @[lsu.scala:1093:25] wire s_uop_fu_code_7; // @[lsu.scala:1093:25] wire s_uop_fu_code_6; // @[lsu.scala:1093:25] wire s_uop_fu_code_5; // @[lsu.scala:1093:25] wire s_uop_fu_code_4; // @[lsu.scala:1093:25] wire s_uop_fu_code_3; // @[lsu.scala:1093:25] wire s_uop_fu_code_2; // @[lsu.scala:1093:25] wire s_uop_fu_code_1; // @[lsu.scala:1093:25] wire s_uop_fu_code_0; // @[lsu.scala:1093:25] wire s_uop_iq_type_3; // @[lsu.scala:1093:25] wire s_uop_iq_type_2; // @[lsu.scala:1093:25] wire s_uop_iq_type_1; // @[lsu.scala:1093:25] wire s_uop_iq_type_0; // @[lsu.scala:1093:25] wire [63:0] mem_stq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_cleared; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_can_execute; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_succeeded; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_committed; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] mem_stq_retry_e_e_bits_data_bits; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] mem_stq_retry_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] mem_stq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [3:0] mem_stq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [3:0] mem_stq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] mem_stq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] mem_stq_retry_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] mem_stq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] mem_stq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] mem_stq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] mem_stq_retry_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire [63:0] mem_ldq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] mem_ldq_retry_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [15:0] mem_ldq_retry_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_observed; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_order_fail; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_succeeded; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_executed; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] mem_ldq_retry_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] mem_ldq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] mem_ldq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] mem_ldq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] mem_ldq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] mem_ldq_retry_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire mem_stq_incoming_e_out_valid; // @[util.scala:114:23] wire [11:0] mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_valid; // @[util.scala:114:23] wire [11:0] mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire [11:0] mem_incoming_uop_out_br_mask; // @[util.scala:104:23] wire [11:0] mem_xcpt_uops_out_br_mask; // @[util.scala:104:23] wire [63:0] stq_enq_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_cleared; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_can_execute; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_succeeded; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_committed; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] stq_enq_e_e_bits_data_bits; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] stq_enq_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] stq_enq_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [3:0] stq_enq_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [3:0] stq_enq_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] stq_enq_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] stq_enq_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] stq_enq_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [11:0] stq_enq_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] stq_enq_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] stq_enq_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] stq_enq_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_valid; // @[lsu.scala:262:17] wire [63:0] stq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_cleared; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_can_execute; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_committed; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] stq_enq_retry_e_e_bits_data_bits; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] stq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] stq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [3:0] stq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [3:0] stq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] stq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] stq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] stq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [11:0] stq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] stq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] stq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] stq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire ldq_enq_retry_e_e_valid; // @[lsu.scala:233:17] wire [63:0] ldq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] ldq_enq_retry_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [15:0] ldq_enq_retry_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_observed; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_order_fail; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_executed; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] ldq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] ldq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] ldq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [11:0] ldq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] ldq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] ldq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] ldq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_valid; // @[lsu.scala:233:17] wire [63:0] ldq_wakeup_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] ldq_wakeup_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [15:0] ldq_wakeup_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_observed; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_order_fail; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_succeeded; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_executed; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] ldq_wakeup_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] ldq_wakeup_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] ldq_wakeup_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [11:0] ldq_wakeup_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] ldq_wakeup_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] ldq_wakeup_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] ldq_wakeup_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire stq_incoming_e_e_valid; // @[lsu.scala:262:17] wire [63:0] stq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_cleared; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_can_execute; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_succeeded; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_committed; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] stq_incoming_e_e_bits_data_bits; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] stq_incoming_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] stq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [3:0] stq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [3:0] stq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] stq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] stq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] stq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [11:0] stq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] stq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] stq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] stq_incoming_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire ldq_incoming_e_e_valid; // @[lsu.scala:233:17] wire [63:0] ldq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] ldq_incoming_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [15:0] ldq_incoming_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_observed; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_order_fail; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_succeeded; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_executed; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] ldq_incoming_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] ldq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] ldq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [11:0] ldq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] ldq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] ldq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] ldq_incoming_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire _logic_1_io_found; // @[lsu.scala:1965:23] wire [3:0] _logic_1_io_found_idx; // @[lsu.scala:1965:23] wire _logic_io_found; // @[lsu.scala:1965:23] wire [3:0] _logic_io_found_idx; // @[lsu.scala:1965:23] wire _wakeupArbs_0_io_in_1_ready; // @[lsu.scala:1016:47] wire _stq_execute_queue_io_enq_ready; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_valid; // @[lsu.scala:558:11] wire [31:0] _stq_execute_queue_io_deq_bits_uop_inst; // @[lsu.scala:558:11] wire [31:0] _stq_execute_queue_io_deq_bits_uop_debug_inst; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_rvc; // @[lsu.scala:558:11] wire [39:0] _stq_execute_queue_io_deq_bits_uop_debug_pc; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_0; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_1; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_2; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_3; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_0; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_1; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_2; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_3; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_4; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_5; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_6; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_7; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_8; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_9; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_issued; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_agen; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_iw_p1_speculative_child; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_iw_p2_speculative_child; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_dis_col_sel; // @[lsu.scala:558:11] wire [11:0] _stq_execute_queue_io_deq_bits_uop_br_mask; // @[lsu.scala:558:11] wire [3:0] _stq_execute_queue_io_deq_bits_uop_br_tag; // @[lsu.scala:558:11] wire [3:0] _stq_execute_queue_io_deq_bits_uop_br_type; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_sfb; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_fence; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_fencei; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_sfence; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_amo; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_eret; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_sys_pc2epc; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_rocc; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_mov; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_ftq_idx; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_edge_inst; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_pc_lob; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_taken; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_imm_rename; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_imm_sel; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_pimm; // @[lsu.scala:558:11] wire [19:0] _stq_execute_queue_io_deq_bits_uop_imm_packed; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_op1_sel; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_op2_sel; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ldst; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wen; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren1; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren2; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren3; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap12; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap23; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fromint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_toint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fma; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_div; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wflags; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_vec; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_rob_idx; // @[lsu.scala:558:11] wire [3:0] _stq_execute_queue_io_deq_bits_uop_ldq_idx; // @[lsu.scala:558:11] wire [3:0] _stq_execute_queue_io_deq_bits_uop_stq_idx; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_rxq_idx; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_pdst; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_prs1; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_prs2; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_prs3; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_ppred; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_prs1_busy; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_prs2_busy; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_prs3_busy; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_ppred_busy; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_stale_pdst; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_exception; // @[lsu.scala:558:11] wire [63:0] _stq_execute_queue_io_deq_bits_uop_exc_cause; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_mem_cmd; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_mem_size; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_mem_signed; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_unique; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_flush_on_commit; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_csr_cmd; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_ldst_is_rs1; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_ldst; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_lrs1; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_lrs2; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_lrs3; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_dst_rtype; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_lrs1_rtype; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_lrs2_rtype; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_frs3_en; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fcn_dw; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_fcn_op; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_val; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_fp_rm; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_fp_typ; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_xcpt_pf_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_xcpt_ae_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_xcpt_ma_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_bp_debug_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_bp_xcpt_if; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_debug_fsrc; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_debug_tsrc; // @[lsu.scala:558:11] wire [39:0] _stq_execute_queue_io_deq_bits_addr_bits; // @[lsu.scala:558:11] wire [63:0] _stq_execute_queue_io_deq_bits_data_bits; // @[lsu.scala:558:11] wire _retry_queue_io_enq_ready; // @[lsu.scala:533:27] wire _retry_queue_io_deq_valid; // @[lsu.scala:533:27] wire [31:0] _retry_queue_io_deq_bits_uop_inst; // @[lsu.scala:533:27] wire [31:0] _retry_queue_io_deq_bits_uop_debug_inst; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_rvc; // @[lsu.scala:533:27] wire [39:0] _retry_queue_io_deq_bits_uop_debug_pc; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_0; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_1; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_2; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_3; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_0; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_1; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_2; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_3; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_4; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_5; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_6; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_7; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_8; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_9; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_issued; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_issued_partial_agen; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_iw_p1_speculative_child; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_iw_p2_speculative_child; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_dis_col_sel; // @[lsu.scala:533:27] wire [11:0] _retry_queue_io_deq_bits_uop_br_mask; // @[lsu.scala:533:27] wire [3:0] _retry_queue_io_deq_bits_uop_br_tag; // @[lsu.scala:533:27] wire [3:0] _retry_queue_io_deq_bits_uop_br_type; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_sfb; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_fence; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_fencei; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_sfence; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_amo; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_eret; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_sys_pc2epc; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_rocc; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_mov; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_ftq_idx; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_edge_inst; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_pc_lob; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_taken; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_imm_rename; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_imm_sel; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_pimm; // @[lsu.scala:533:27] wire [19:0] _retry_queue_io_deq_bits_uop_imm_packed; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_op1_sel; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_op2_sel; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ldst; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_wen; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ren1; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ren2; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ren3; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_swap12; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_swap23; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_fromint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_toint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_fma; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_div; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_wflags; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_vec; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_rob_idx; // @[lsu.scala:533:27] wire [3:0] _retry_queue_io_deq_bits_uop_ldq_idx; // @[lsu.scala:533:27] wire [3:0] _retry_queue_io_deq_bits_uop_stq_idx; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_rxq_idx; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_pdst; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_prs1; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_prs2; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_prs3; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_ppred; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_prs1_busy; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_prs2_busy; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_prs3_busy; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_ppred_busy; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_stale_pdst; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_exception; // @[lsu.scala:533:27] wire [63:0] _retry_queue_io_deq_bits_uop_exc_cause; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_mem_cmd; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_mem_size; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_mem_signed; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_unique; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_flush_on_commit; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_csr_cmd; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_ldst_is_rs1; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_ldst; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_lrs1; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_lrs2; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_lrs3; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_dst_rtype; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_lrs1_rtype; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_lrs2_rtype; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_frs3_en; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fcn_dw; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_fcn_op; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_val; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_fp_rm; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_fp_typ; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_xcpt_pf_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_xcpt_ae_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_xcpt_ma_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_bp_debug_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_bp_xcpt_if; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_debug_fsrc; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_debug_tsrc; // @[lsu.scala:533:27] wire [63:0] _retry_queue_io_deq_bits_data; // @[lsu.scala:533:27] wire [31:0] _dtlb_io_resp_0_paddr; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_pf_ld; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_pf_st; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ae_ld; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ae_st; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ma_ld; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ma_st; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_cacheable; // @[lsu.scala:308:20] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[lsu.scala:211:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[lsu.scala:211:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[lsu.scala:211:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[lsu.scala:211:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[lsu.scala:211:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[lsu.scala:211:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[lsu.scala:211:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[lsu.scala:211:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[lsu.scala:211:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[lsu.scala:211:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[lsu.scala:211:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[lsu.scala:211:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[lsu.scala:211:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[lsu.scala:211:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[lsu.scala:211:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[lsu.scala:211:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[lsu.scala:211:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[lsu.scala:211:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[lsu.scala:211:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[lsu.scala:211:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[lsu.scala:211:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[lsu.scala:211:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[lsu.scala:211:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[lsu.scala:211:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[lsu.scala:211:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[lsu.scala:211:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[lsu.scala:211:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[lsu.scala:211:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[lsu.scala:211:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[lsu.scala:211:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[lsu.scala:211:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[lsu.scala:211:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[lsu.scala:211:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[lsu.scala:211:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[lsu.scala:211:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[lsu.scala:211:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[lsu.scala:211:7] wire io_core_agen_0_valid_0 = io_core_agen_0_valid; // @[lsu.scala:211:7] wire [31:0] io_core_agen_0_bits_uop_inst_0 = io_core_agen_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_agen_0_bits_uop_debug_inst_0 = io_core_agen_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_rvc_0 = io_core_agen_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_agen_0_bits_uop_debug_pc_0 = io_core_agen_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_0_0 = io_core_agen_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_1_0 = io_core_agen_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_2_0 = io_core_agen_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_3_0 = io_core_agen_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_0_0 = io_core_agen_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_1_0 = io_core_agen_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_2_0 = io_core_agen_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_3_0 = io_core_agen_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_4_0 = io_core_agen_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_5_0 = io_core_agen_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_6_0 = io_core_agen_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_7_0 = io_core_agen_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_8_0 = io_core_agen_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_9_0 = io_core_agen_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_issued_0 = io_core_agen_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_issued_partial_agen_0 = io_core_agen_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_issued_partial_dgen_0 = io_core_agen_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_iw_p1_speculative_child_0 = io_core_agen_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_iw_p2_speculative_child_0 = io_core_agen_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_p1_bypass_hint_0 = io_core_agen_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_p2_bypass_hint_0 = io_core_agen_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_p3_bypass_hint_0 = io_core_agen_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_dis_col_sel_0 = io_core_agen_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_agen_0_bits_uop_br_mask_0 = io_core_agen_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_agen_0_bits_uop_br_tag_0 = io_core_agen_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_agen_0_bits_uop_br_type_0 = io_core_agen_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_sfb_0 = io_core_agen_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_fence_0 = io_core_agen_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_fencei_0 = io_core_agen_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_sfence_0 = io_core_agen_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_amo_0 = io_core_agen_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_eret_0 = io_core_agen_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_sys_pc2epc_0 = io_core_agen_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_rocc_0 = io_core_agen_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_mov_0 = io_core_agen_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_ftq_idx_0 = io_core_agen_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_edge_inst_0 = io_core_agen_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_pc_lob_0 = io_core_agen_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_taken_0 = io_core_agen_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_imm_rename_0 = io_core_agen_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_imm_sel_0 = io_core_agen_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_pimm_0 = io_core_agen_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_agen_0_bits_uop_imm_packed_0 = io_core_agen_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_op1_sel_0 = io_core_agen_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_op2_sel_0 = io_core_agen_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ldst_0 = io_core_agen_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_wen_0 = io_core_agen_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ren1_0 = io_core_agen_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ren2_0 = io_core_agen_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ren3_0 = io_core_agen_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_swap12_0 = io_core_agen_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_swap23_0 = io_core_agen_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagIn_0 = io_core_agen_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagOut_0 = io_core_agen_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_fromint_0 = io_core_agen_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_toint_0 = io_core_agen_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_fastpipe_0 = io_core_agen_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_fma_0 = io_core_agen_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_div_0 = io_core_agen_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_sqrt_0 = io_core_agen_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_wflags_0 = io_core_agen_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_vec_0 = io_core_agen_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_rob_idx_0 = io_core_agen_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_agen_0_bits_uop_ldq_idx_0 = io_core_agen_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_agen_0_bits_uop_stq_idx_0 = io_core_agen_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_rxq_idx_0 = io_core_agen_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_pdst_0 = io_core_agen_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_prs1_0 = io_core_agen_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_prs2_0 = io_core_agen_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_prs3_0 = io_core_agen_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_ppred_0 = io_core_agen_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_prs1_busy_0 = io_core_agen_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_prs2_busy_0 = io_core_agen_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_prs3_busy_0 = io_core_agen_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_ppred_busy_0 = io_core_agen_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_stale_pdst_0 = io_core_agen_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_exception_0 = io_core_agen_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_agen_0_bits_uop_exc_cause_0 = io_core_agen_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_mem_cmd_0 = io_core_agen_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_mem_size_0 = io_core_agen_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_mem_signed_0 = io_core_agen_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_uses_ldq_0 = io_core_agen_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_uses_stq_0 = io_core_agen_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_unique_0 = io_core_agen_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_flush_on_commit_0 = io_core_agen_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_csr_cmd_0 = io_core_agen_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_ldst_is_rs1_0 = io_core_agen_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_ldst_0 = io_core_agen_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_lrs1_0 = io_core_agen_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_lrs2_0 = io_core_agen_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_lrs3_0 = io_core_agen_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_dst_rtype_0 = io_core_agen_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_lrs1_rtype_0 = io_core_agen_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_lrs2_rtype_0 = io_core_agen_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_frs3_en_0 = io_core_agen_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fcn_dw_0 = io_core_agen_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_fcn_op_0 = io_core_agen_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_val_0 = io_core_agen_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_fp_rm_0 = io_core_agen_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_fp_typ_0 = io_core_agen_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_xcpt_pf_if_0 = io_core_agen_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_xcpt_ae_if_0 = io_core_agen_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_xcpt_ma_if_0 = io_core_agen_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_bp_debug_if_0 = io_core_agen_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_bp_xcpt_if_0 = io_core_agen_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_debug_fsrc_0 = io_core_agen_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_debug_tsrc_0 = io_core_agen_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_agen_0_bits_data_0 = io_core_agen_0_bits_data; // @[lsu.scala:211:7] wire io_core_dgen_0_valid_0 = io_core_dgen_0_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_0_bits_uop_inst_0 = io_core_dgen_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_0_bits_uop_debug_inst_0 = io_core_dgen_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_rvc_0 = io_core_dgen_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dgen_0_bits_uop_debug_pc_0 = io_core_dgen_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_0_0 = io_core_dgen_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_1_0 = io_core_dgen_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_2_0 = io_core_dgen_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_3_0 = io_core_dgen_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_0_0 = io_core_dgen_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_1_0 = io_core_dgen_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_2_0 = io_core_dgen_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_3_0 = io_core_dgen_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_4_0 = io_core_dgen_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_5_0 = io_core_dgen_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_6_0 = io_core_dgen_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_7_0 = io_core_dgen_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_8_0 = io_core_dgen_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_9_0 = io_core_dgen_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_issued_0 = io_core_dgen_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_issued_partial_agen_0 = io_core_dgen_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_issued_partial_dgen_0 = io_core_dgen_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_iw_p1_speculative_child_0 = io_core_dgen_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_iw_p2_speculative_child_0 = io_core_dgen_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_p1_bypass_hint_0 = io_core_dgen_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_p2_bypass_hint_0 = io_core_dgen_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_p3_bypass_hint_0 = io_core_dgen_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_dis_col_sel_0 = io_core_dgen_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_dgen_0_bits_uop_br_mask_0 = io_core_dgen_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_0_bits_uop_br_tag_0 = io_core_dgen_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_0_bits_uop_br_type_0 = io_core_dgen_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_sfb_0 = io_core_dgen_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_fence_0 = io_core_dgen_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_fencei_0 = io_core_dgen_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_sfence_0 = io_core_dgen_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_amo_0 = io_core_dgen_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_eret_0 = io_core_dgen_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_sys_pc2epc_0 = io_core_dgen_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_rocc_0 = io_core_dgen_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_mov_0 = io_core_dgen_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_ftq_idx_0 = io_core_dgen_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_edge_inst_0 = io_core_dgen_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_pc_lob_0 = io_core_dgen_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_taken_0 = io_core_dgen_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_imm_rename_0 = io_core_dgen_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_imm_sel_0 = io_core_dgen_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_pimm_0 = io_core_dgen_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dgen_0_bits_uop_imm_packed_0 = io_core_dgen_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_op1_sel_0 = io_core_dgen_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_op2_sel_0 = io_core_dgen_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ldst_0 = io_core_dgen_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_wen_0 = io_core_dgen_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ren1_0 = io_core_dgen_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ren2_0 = io_core_dgen_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ren3_0 = io_core_dgen_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_swap12_0 = io_core_dgen_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_swap23_0 = io_core_dgen_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn_0 = io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut_0 = io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_fromint_0 = io_core_dgen_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_toint_0 = io_core_dgen_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_fastpipe_0 = io_core_dgen_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_fma_0 = io_core_dgen_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_div_0 = io_core_dgen_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_sqrt_0 = io_core_dgen_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_wflags_0 = io_core_dgen_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_vec_0 = io_core_dgen_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_rob_idx_0 = io_core_dgen_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_0_bits_uop_ldq_idx_0 = io_core_dgen_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_0_bits_uop_stq_idx_0 = io_core_dgen_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_rxq_idx_0 = io_core_dgen_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_pdst_0 = io_core_dgen_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_prs1_0 = io_core_dgen_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_prs2_0 = io_core_dgen_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_prs3_0 = io_core_dgen_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_ppred_0 = io_core_dgen_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_prs1_busy_0 = io_core_dgen_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_prs2_busy_0 = io_core_dgen_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_prs3_busy_0 = io_core_dgen_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_ppred_busy_0 = io_core_dgen_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_stale_pdst_0 = io_core_dgen_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_exception_0 = io_core_dgen_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_0_bits_uop_exc_cause_0 = io_core_dgen_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_mem_cmd_0 = io_core_dgen_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_mem_size_0 = io_core_dgen_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_mem_signed_0 = io_core_dgen_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_uses_ldq_0 = io_core_dgen_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_uses_stq_0 = io_core_dgen_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_unique_0 = io_core_dgen_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_flush_on_commit_0 = io_core_dgen_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_csr_cmd_0 = io_core_dgen_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_ldst_is_rs1_0 = io_core_dgen_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_ldst_0 = io_core_dgen_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_lrs1_0 = io_core_dgen_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_lrs2_0 = io_core_dgen_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_lrs3_0 = io_core_dgen_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_dst_rtype_0 = io_core_dgen_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_lrs1_rtype_0 = io_core_dgen_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_lrs2_rtype_0 = io_core_dgen_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_frs3_en_0 = io_core_dgen_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fcn_dw_0 = io_core_dgen_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_fcn_op_0 = io_core_dgen_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_val_0 = io_core_dgen_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_fp_rm_0 = io_core_dgen_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_fp_typ_0 = io_core_dgen_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_xcpt_pf_if_0 = io_core_dgen_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_xcpt_ae_if_0 = io_core_dgen_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_xcpt_ma_if_0 = io_core_dgen_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_bp_debug_if_0 = io_core_dgen_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_bp_xcpt_if_0 = io_core_dgen_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_debug_fsrc_0 = io_core_dgen_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_debug_tsrc_0 = io_core_dgen_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_0_bits_data_0 = io_core_dgen_0_bits_data; // @[lsu.scala:211:7] wire io_core_dgen_1_valid_0 = io_core_dgen_1_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_1_bits_uop_inst_0 = io_core_dgen_1_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_1_bits_uop_debug_inst_0 = io_core_dgen_1_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_rvc_0 = io_core_dgen_1_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dgen_1_bits_uop_debug_pc_0 = io_core_dgen_1_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_0_0 = io_core_dgen_1_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_1_0 = io_core_dgen_1_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_2_0 = io_core_dgen_1_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_3_0 = io_core_dgen_1_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_0_0 = io_core_dgen_1_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_1_0 = io_core_dgen_1_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_2_0 = io_core_dgen_1_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_3_0 = io_core_dgen_1_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_4_0 = io_core_dgen_1_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_5_0 = io_core_dgen_1_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_6_0 = io_core_dgen_1_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_7_0 = io_core_dgen_1_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_8_0 = io_core_dgen_1_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_9_0 = io_core_dgen_1_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_issued_0 = io_core_dgen_1_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_issued_partial_agen_0 = io_core_dgen_1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_issued_partial_dgen_0 = io_core_dgen_1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_iw_p1_speculative_child_0 = io_core_dgen_1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_iw_p2_speculative_child_0 = io_core_dgen_1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_p1_bypass_hint_0 = io_core_dgen_1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_p2_bypass_hint_0 = io_core_dgen_1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_p3_bypass_hint_0 = io_core_dgen_1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_dis_col_sel_0 = io_core_dgen_1_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_dgen_1_bits_uop_br_mask_0 = io_core_dgen_1_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_1_bits_uop_br_tag_0 = io_core_dgen_1_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_1_bits_uop_br_type_0 = io_core_dgen_1_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_sfb_0 = io_core_dgen_1_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_fence_0 = io_core_dgen_1_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_fencei_0 = io_core_dgen_1_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_sfence_0 = io_core_dgen_1_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_amo_0 = io_core_dgen_1_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_eret_0 = io_core_dgen_1_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_sys_pc2epc_0 = io_core_dgen_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_rocc_0 = io_core_dgen_1_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_mov_0 = io_core_dgen_1_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_ftq_idx_0 = io_core_dgen_1_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_edge_inst_0 = io_core_dgen_1_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_pc_lob_0 = io_core_dgen_1_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_taken_0 = io_core_dgen_1_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_imm_rename_0 = io_core_dgen_1_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_imm_sel_0 = io_core_dgen_1_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_pimm_0 = io_core_dgen_1_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dgen_1_bits_uop_imm_packed_0 = io_core_dgen_1_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_op1_sel_0 = io_core_dgen_1_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_op2_sel_0 = io_core_dgen_1_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ldst_0 = io_core_dgen_1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_wen_0 = io_core_dgen_1_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ren1_0 = io_core_dgen_1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ren2_0 = io_core_dgen_1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ren3_0 = io_core_dgen_1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_swap12_0 = io_core_dgen_1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_swap23_0 = io_core_dgen_1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn_0 = io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut_0 = io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_fromint_0 = io_core_dgen_1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_toint_0 = io_core_dgen_1_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_fastpipe_0 = io_core_dgen_1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_fma_0 = io_core_dgen_1_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_div_0 = io_core_dgen_1_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_sqrt_0 = io_core_dgen_1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_wflags_0 = io_core_dgen_1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_vec_0 = io_core_dgen_1_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_rob_idx_0 = io_core_dgen_1_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_1_bits_uop_ldq_idx_0 = io_core_dgen_1_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_1_bits_uop_stq_idx_0 = io_core_dgen_1_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_rxq_idx_0 = io_core_dgen_1_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_pdst_0 = io_core_dgen_1_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_prs1_0 = io_core_dgen_1_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_prs2_0 = io_core_dgen_1_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_prs3_0 = io_core_dgen_1_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_ppred_0 = io_core_dgen_1_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_prs1_busy_0 = io_core_dgen_1_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_prs2_busy_0 = io_core_dgen_1_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_prs3_busy_0 = io_core_dgen_1_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_ppred_busy_0 = io_core_dgen_1_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_stale_pdst_0 = io_core_dgen_1_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_exception_0 = io_core_dgen_1_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_1_bits_uop_exc_cause_0 = io_core_dgen_1_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_mem_cmd_0 = io_core_dgen_1_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_mem_size_0 = io_core_dgen_1_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_mem_signed_0 = io_core_dgen_1_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_uses_ldq_0 = io_core_dgen_1_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_uses_stq_0 = io_core_dgen_1_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_unique_0 = io_core_dgen_1_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_flush_on_commit_0 = io_core_dgen_1_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_csr_cmd_0 = io_core_dgen_1_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_ldst_is_rs1_0 = io_core_dgen_1_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_ldst_0 = io_core_dgen_1_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_lrs1_0 = io_core_dgen_1_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_lrs2_0 = io_core_dgen_1_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_lrs3_0 = io_core_dgen_1_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_dst_rtype_0 = io_core_dgen_1_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_lrs1_rtype_0 = io_core_dgen_1_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_lrs2_rtype_0 = io_core_dgen_1_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_frs3_en_0 = io_core_dgen_1_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fcn_dw_0 = io_core_dgen_1_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_fcn_op_0 = io_core_dgen_1_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_val_0 = io_core_dgen_1_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_fp_rm_0 = io_core_dgen_1_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_fp_typ_0 = io_core_dgen_1_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_xcpt_pf_if_0 = io_core_dgen_1_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_xcpt_ae_if_0 = io_core_dgen_1_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_xcpt_ma_if_0 = io_core_dgen_1_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_bp_debug_if_0 = io_core_dgen_1_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_bp_xcpt_if_0 = io_core_dgen_1_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_debug_fsrc_0 = io_core_dgen_1_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_debug_tsrc_0 = io_core_dgen_1_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_1_bits_data_0 = io_core_dgen_1_bits_data; // @[lsu.scala:211:7] wire io_core_dgen_2_valid_0 = io_core_dgen_2_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_2_bits_uop_inst_0 = io_core_dgen_2_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_2_bits_uop_debug_inst_0 = io_core_dgen_2_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_rvc_0 = io_core_dgen_2_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dgen_2_bits_uop_debug_pc_0 = io_core_dgen_2_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_0_0 = io_core_dgen_2_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_1_0 = io_core_dgen_2_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_2_0 = io_core_dgen_2_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_3_0 = io_core_dgen_2_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_0_0 = io_core_dgen_2_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_1_0 = io_core_dgen_2_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_2_0 = io_core_dgen_2_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_3_0 = io_core_dgen_2_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_4_0 = io_core_dgen_2_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_5_0 = io_core_dgen_2_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_6_0 = io_core_dgen_2_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_7_0 = io_core_dgen_2_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_8_0 = io_core_dgen_2_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_9_0 = io_core_dgen_2_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_issued_0 = io_core_dgen_2_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_issued_partial_agen_0 = io_core_dgen_2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_issued_partial_dgen_0 = io_core_dgen_2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_iw_p1_speculative_child_0 = io_core_dgen_2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_iw_p2_speculative_child_0 = io_core_dgen_2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_p1_bypass_hint_0 = io_core_dgen_2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_p2_bypass_hint_0 = io_core_dgen_2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_p3_bypass_hint_0 = io_core_dgen_2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_dis_col_sel_0 = io_core_dgen_2_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_dgen_2_bits_uop_br_mask_0 = io_core_dgen_2_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_2_bits_uop_br_tag_0 = io_core_dgen_2_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_2_bits_uop_br_type_0 = io_core_dgen_2_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_sfb_0 = io_core_dgen_2_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_fence_0 = io_core_dgen_2_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_fencei_0 = io_core_dgen_2_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_sfence_0 = io_core_dgen_2_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_amo_0 = io_core_dgen_2_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_eret_0 = io_core_dgen_2_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_sys_pc2epc_0 = io_core_dgen_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_rocc_0 = io_core_dgen_2_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_mov_0 = io_core_dgen_2_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_ftq_idx_0 = io_core_dgen_2_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_edge_inst_0 = io_core_dgen_2_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_pc_lob_0 = io_core_dgen_2_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_taken_0 = io_core_dgen_2_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_imm_rename_0 = io_core_dgen_2_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_imm_sel_0 = io_core_dgen_2_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_pimm_0 = io_core_dgen_2_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dgen_2_bits_uop_imm_packed_0 = io_core_dgen_2_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_op1_sel_0 = io_core_dgen_2_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_op2_sel_0 = io_core_dgen_2_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ldst_0 = io_core_dgen_2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_wen_0 = io_core_dgen_2_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ren1_0 = io_core_dgen_2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ren2_0 = io_core_dgen_2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ren3_0 = io_core_dgen_2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_swap12_0 = io_core_dgen_2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_swap23_0 = io_core_dgen_2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn_0 = io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut_0 = io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_fromint_0 = io_core_dgen_2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_toint_0 = io_core_dgen_2_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_fastpipe_0 = io_core_dgen_2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_fma_0 = io_core_dgen_2_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_div_0 = io_core_dgen_2_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_sqrt_0 = io_core_dgen_2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_wflags_0 = io_core_dgen_2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_vec_0 = io_core_dgen_2_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_rob_idx_0 = io_core_dgen_2_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_2_bits_uop_ldq_idx_0 = io_core_dgen_2_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_2_bits_uop_stq_idx_0 = io_core_dgen_2_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_rxq_idx_0 = io_core_dgen_2_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_pdst_0 = io_core_dgen_2_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_prs1_0 = io_core_dgen_2_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_prs2_0 = io_core_dgen_2_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_prs3_0 = io_core_dgen_2_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_ppred_0 = io_core_dgen_2_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_prs1_busy_0 = io_core_dgen_2_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_prs2_busy_0 = io_core_dgen_2_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_prs3_busy_0 = io_core_dgen_2_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_ppred_busy_0 = io_core_dgen_2_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_stale_pdst_0 = io_core_dgen_2_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_exception_0 = io_core_dgen_2_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_2_bits_uop_exc_cause_0 = io_core_dgen_2_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_mem_cmd_0 = io_core_dgen_2_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_mem_size_0 = io_core_dgen_2_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_mem_signed_0 = io_core_dgen_2_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_uses_ldq_0 = io_core_dgen_2_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_uses_stq_0 = io_core_dgen_2_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_unique_0 = io_core_dgen_2_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_flush_on_commit_0 = io_core_dgen_2_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_csr_cmd_0 = io_core_dgen_2_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_ldst_is_rs1_0 = io_core_dgen_2_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_ldst_0 = io_core_dgen_2_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_lrs1_0 = io_core_dgen_2_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_lrs2_0 = io_core_dgen_2_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_lrs3_0 = io_core_dgen_2_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_dst_rtype_0 = io_core_dgen_2_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_lrs1_rtype_0 = io_core_dgen_2_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_lrs2_rtype_0 = io_core_dgen_2_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_frs3_en_0 = io_core_dgen_2_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fcn_dw_0 = io_core_dgen_2_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_fcn_op_0 = io_core_dgen_2_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_val_0 = io_core_dgen_2_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_fp_rm_0 = io_core_dgen_2_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_fp_typ_0 = io_core_dgen_2_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_xcpt_pf_if_0 = io_core_dgen_2_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_xcpt_ae_if_0 = io_core_dgen_2_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_xcpt_ma_if_0 = io_core_dgen_2_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_bp_debug_if_0 = io_core_dgen_2_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_bp_xcpt_if_0 = io_core_dgen_2_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_debug_fsrc_0 = io_core_dgen_2_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_debug_tsrc_0 = io_core_dgen_2_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_2_bits_data_0 = io_core_dgen_2_bits_data; // @[lsu.scala:211:7] wire io_core_sfence_valid_0 = io_core_sfence_valid; // @[lsu.scala:211:7] wire io_core_sfence_bits_rs1_0 = io_core_sfence_bits_rs1; // @[lsu.scala:211:7] wire io_core_sfence_bits_rs2_0 = io_core_sfence_bits_rs2; // @[lsu.scala:211:7] wire [38:0] io_core_sfence_bits_addr_0 = io_core_sfence_bits_addr; // @[lsu.scala:211:7] wire io_core_sfence_bits_asid_0 = io_core_sfence_bits_asid; // @[lsu.scala:211:7] wire io_core_sfence_bits_hv_0 = io_core_sfence_bits_hv; // @[lsu.scala:211:7] wire io_core_sfence_bits_hg_0 = io_core_sfence_bits_hg; // @[lsu.scala:211:7] wire io_core_dis_uops_0_valid_0 = io_core_dis_uops_0_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_0_bits_inst_0 = io_core_dis_uops_0_bits_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_0_bits_debug_inst_0 = io_core_dis_uops_0_bits_debug_inst; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_rvc_0 = io_core_dis_uops_0_bits_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dis_uops_0_bits_debug_pc_0 = io_core_dis_uops_0_bits_debug_pc; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_0_0 = io_core_dis_uops_0_bits_iq_type_0; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_1_0 = io_core_dis_uops_0_bits_iq_type_1; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_2_0 = io_core_dis_uops_0_bits_iq_type_2; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_3_0 = io_core_dis_uops_0_bits_iq_type_3; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_0_0 = io_core_dis_uops_0_bits_fu_code_0; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_1_0 = io_core_dis_uops_0_bits_fu_code_1; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_2_0 = io_core_dis_uops_0_bits_fu_code_2; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_3_0 = io_core_dis_uops_0_bits_fu_code_3; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_4_0 = io_core_dis_uops_0_bits_fu_code_4; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_5_0 = io_core_dis_uops_0_bits_fu_code_5; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_6_0 = io_core_dis_uops_0_bits_fu_code_6; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_7_0 = io_core_dis_uops_0_bits_fu_code_7; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_8_0 = io_core_dis_uops_0_bits_fu_code_8; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_9_0 = io_core_dis_uops_0_bits_fu_code_9; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_issued_0 = io_core_dis_uops_0_bits_iw_issued; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_issued_partial_agen_0 = io_core_dis_uops_0_bits_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_core_dis_uops_0_bits_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_iw_p1_speculative_child_0 = io_core_dis_uops_0_bits_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_iw_p2_speculative_child_0 = io_core_dis_uops_0_bits_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_core_dis_uops_0_bits_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_core_dis_uops_0_bits_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_core_dis_uops_0_bits_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_dis_col_sel_0 = io_core_dis_uops_0_bits_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_dis_uops_0_bits_br_mask_0 = io_core_dis_uops_0_bits_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_0_bits_br_tag_0 = io_core_dis_uops_0_bits_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_0_bits_br_type_0 = io_core_dis_uops_0_bits_br_type; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_sfb_0 = io_core_dis_uops_0_bits_is_sfb; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_fence_0 = io_core_dis_uops_0_bits_is_fence; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_fencei_0 = io_core_dis_uops_0_bits_is_fencei; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_sfence_0 = io_core_dis_uops_0_bits_is_sfence; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_amo_0 = io_core_dis_uops_0_bits_is_amo; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_eret_0 = io_core_dis_uops_0_bits_is_eret; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_sys_pc2epc_0 = io_core_dis_uops_0_bits_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_rocc_0 = io_core_dis_uops_0_bits_is_rocc; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_mov_0 = io_core_dis_uops_0_bits_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_ftq_idx_0 = io_core_dis_uops_0_bits_ftq_idx; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_edge_inst_0 = io_core_dis_uops_0_bits_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_pc_lob_0 = io_core_dis_uops_0_bits_pc_lob; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_taken_0 = io_core_dis_uops_0_bits_taken; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_imm_rename_0 = io_core_dis_uops_0_bits_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_imm_sel_0 = io_core_dis_uops_0_bits_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_pimm_0 = io_core_dis_uops_0_bits_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dis_uops_0_bits_imm_packed_0 = io_core_dis_uops_0_bits_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_op1_sel_0 = io_core_dis_uops_0_bits_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_op2_sel_0 = io_core_dis_uops_0_bits_op2_sel; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ldst_0 = io_core_dis_uops_0_bits_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_wen_0 = io_core_dis_uops_0_bits_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ren1_0 = io_core_dis_uops_0_bits_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ren2_0 = io_core_dis_uops_0_bits_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ren3_0 = io_core_dis_uops_0_bits_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_swap12_0 = io_core_dis_uops_0_bits_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_swap23_0 = io_core_dis_uops_0_bits_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_core_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_core_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_fromint_0 = io_core_dis_uops_0_bits_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_toint_0 = io_core_dis_uops_0_bits_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_core_dis_uops_0_bits_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_fma_0 = io_core_dis_uops_0_bits_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_div_0 = io_core_dis_uops_0_bits_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_core_dis_uops_0_bits_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_wflags_0 = io_core_dis_uops_0_bits_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_vec_0 = io_core_dis_uops_0_bits_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_rob_idx_0 = io_core_dis_uops_0_bits_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_0_bits_ldq_idx_0 = io_core_dis_uops_0_bits_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_0_bits_stq_idx_0 = io_core_dis_uops_0_bits_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_rxq_idx_0 = io_core_dis_uops_0_bits_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_pdst_0 = io_core_dis_uops_0_bits_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_prs1_0 = io_core_dis_uops_0_bits_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_prs2_0 = io_core_dis_uops_0_bits_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_prs3_0 = io_core_dis_uops_0_bits_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_ppred_0 = io_core_dis_uops_0_bits_ppred; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_prs1_busy_0 = io_core_dis_uops_0_bits_prs1_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_prs2_busy_0 = io_core_dis_uops_0_bits_prs2_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_prs3_busy_0 = io_core_dis_uops_0_bits_prs3_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_ppred_busy_0 = io_core_dis_uops_0_bits_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_stale_pdst_0 = io_core_dis_uops_0_bits_stale_pdst; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_exception_0 = io_core_dis_uops_0_bits_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dis_uops_0_bits_exc_cause_0 = io_core_dis_uops_0_bits_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_mem_cmd_0 = io_core_dis_uops_0_bits_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_mem_size_0 = io_core_dis_uops_0_bits_mem_size; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_mem_signed_0 = io_core_dis_uops_0_bits_mem_signed; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_uses_ldq_0 = io_core_dis_uops_0_bits_uses_ldq; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_uses_stq_0 = io_core_dis_uops_0_bits_uses_stq; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_unique_0 = io_core_dis_uops_0_bits_is_unique; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_flush_on_commit_0 = io_core_dis_uops_0_bits_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_csr_cmd_0 = io_core_dis_uops_0_bits_csr_cmd; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_ldst_is_rs1_0 = io_core_dis_uops_0_bits_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_ldst_0 = io_core_dis_uops_0_bits_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_lrs1_0 = io_core_dis_uops_0_bits_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_lrs2_0 = io_core_dis_uops_0_bits_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_lrs3_0 = io_core_dis_uops_0_bits_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_dst_rtype_0 = io_core_dis_uops_0_bits_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_lrs1_rtype_0 = io_core_dis_uops_0_bits_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_lrs2_rtype_0 = io_core_dis_uops_0_bits_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_frs3_en_0 = io_core_dis_uops_0_bits_frs3_en; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fcn_dw_0 = io_core_dis_uops_0_bits_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_fcn_op_0 = io_core_dis_uops_0_bits_fcn_op; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_val_0 = io_core_dis_uops_0_bits_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_fp_rm_0 = io_core_dis_uops_0_bits_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_fp_typ_0 = io_core_dis_uops_0_bits_fp_typ; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_xcpt_pf_if_0 = io_core_dis_uops_0_bits_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_xcpt_ae_if_0 = io_core_dis_uops_0_bits_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_xcpt_ma_if_0 = io_core_dis_uops_0_bits_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_bp_debug_if_0 = io_core_dis_uops_0_bits_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_bp_xcpt_if_0 = io_core_dis_uops_0_bits_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_debug_fsrc_0 = io_core_dis_uops_0_bits_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_debug_tsrc_0 = io_core_dis_uops_0_bits_debug_tsrc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_valid_0 = io_core_dis_uops_1_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_1_bits_inst_0 = io_core_dis_uops_1_bits_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_1_bits_debug_inst_0 = io_core_dis_uops_1_bits_debug_inst; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_rvc_0 = io_core_dis_uops_1_bits_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dis_uops_1_bits_debug_pc_0 = io_core_dis_uops_1_bits_debug_pc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_0_0 = io_core_dis_uops_1_bits_iq_type_0; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_1_0 = io_core_dis_uops_1_bits_iq_type_1; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_2_0 = io_core_dis_uops_1_bits_iq_type_2; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_3_0 = io_core_dis_uops_1_bits_iq_type_3; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_0_0 = io_core_dis_uops_1_bits_fu_code_0; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_1_0 = io_core_dis_uops_1_bits_fu_code_1; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_2_0 = io_core_dis_uops_1_bits_fu_code_2; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_3_0 = io_core_dis_uops_1_bits_fu_code_3; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_4_0 = io_core_dis_uops_1_bits_fu_code_4; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_5_0 = io_core_dis_uops_1_bits_fu_code_5; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_6_0 = io_core_dis_uops_1_bits_fu_code_6; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_7_0 = io_core_dis_uops_1_bits_fu_code_7; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_8_0 = io_core_dis_uops_1_bits_fu_code_8; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_9_0 = io_core_dis_uops_1_bits_fu_code_9; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_issued_0 = io_core_dis_uops_1_bits_iw_issued; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_issued_partial_agen_0 = io_core_dis_uops_1_bits_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_core_dis_uops_1_bits_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_iw_p1_speculative_child_0 = io_core_dis_uops_1_bits_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_iw_p2_speculative_child_0 = io_core_dis_uops_1_bits_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_core_dis_uops_1_bits_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_core_dis_uops_1_bits_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_core_dis_uops_1_bits_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_dis_col_sel_0 = io_core_dis_uops_1_bits_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_dis_uops_1_bits_br_mask_0 = io_core_dis_uops_1_bits_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_1_bits_br_tag_0 = io_core_dis_uops_1_bits_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_1_bits_br_type_0 = io_core_dis_uops_1_bits_br_type; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_sfb_0 = io_core_dis_uops_1_bits_is_sfb; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_fence_0 = io_core_dis_uops_1_bits_is_fence; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_fencei_0 = io_core_dis_uops_1_bits_is_fencei; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_sfence_0 = io_core_dis_uops_1_bits_is_sfence; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_amo_0 = io_core_dis_uops_1_bits_is_amo; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_eret_0 = io_core_dis_uops_1_bits_is_eret; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_sys_pc2epc_0 = io_core_dis_uops_1_bits_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_rocc_0 = io_core_dis_uops_1_bits_is_rocc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_mov_0 = io_core_dis_uops_1_bits_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_ftq_idx_0 = io_core_dis_uops_1_bits_ftq_idx; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_edge_inst_0 = io_core_dis_uops_1_bits_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_pc_lob_0 = io_core_dis_uops_1_bits_pc_lob; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_taken_0 = io_core_dis_uops_1_bits_taken; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_imm_rename_0 = io_core_dis_uops_1_bits_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_imm_sel_0 = io_core_dis_uops_1_bits_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_pimm_0 = io_core_dis_uops_1_bits_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dis_uops_1_bits_imm_packed_0 = io_core_dis_uops_1_bits_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_op1_sel_0 = io_core_dis_uops_1_bits_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_op2_sel_0 = io_core_dis_uops_1_bits_op2_sel; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ldst_0 = io_core_dis_uops_1_bits_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_wen_0 = io_core_dis_uops_1_bits_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ren1_0 = io_core_dis_uops_1_bits_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ren2_0 = io_core_dis_uops_1_bits_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ren3_0 = io_core_dis_uops_1_bits_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_swap12_0 = io_core_dis_uops_1_bits_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_swap23_0 = io_core_dis_uops_1_bits_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_core_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_core_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_fromint_0 = io_core_dis_uops_1_bits_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_toint_0 = io_core_dis_uops_1_bits_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_core_dis_uops_1_bits_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_fma_0 = io_core_dis_uops_1_bits_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_div_0 = io_core_dis_uops_1_bits_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_core_dis_uops_1_bits_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_wflags_0 = io_core_dis_uops_1_bits_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_vec_0 = io_core_dis_uops_1_bits_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_rob_idx_0 = io_core_dis_uops_1_bits_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_1_bits_ldq_idx_0 = io_core_dis_uops_1_bits_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_1_bits_stq_idx_0 = io_core_dis_uops_1_bits_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_rxq_idx_0 = io_core_dis_uops_1_bits_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_pdst_0 = io_core_dis_uops_1_bits_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_prs1_0 = io_core_dis_uops_1_bits_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_prs2_0 = io_core_dis_uops_1_bits_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_prs3_0 = io_core_dis_uops_1_bits_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_ppred_0 = io_core_dis_uops_1_bits_ppred; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_prs1_busy_0 = io_core_dis_uops_1_bits_prs1_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_prs2_busy_0 = io_core_dis_uops_1_bits_prs2_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_prs3_busy_0 = io_core_dis_uops_1_bits_prs3_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_ppred_busy_0 = io_core_dis_uops_1_bits_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_stale_pdst_0 = io_core_dis_uops_1_bits_stale_pdst; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_exception_0 = io_core_dis_uops_1_bits_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dis_uops_1_bits_exc_cause_0 = io_core_dis_uops_1_bits_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_mem_cmd_0 = io_core_dis_uops_1_bits_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_mem_size_0 = io_core_dis_uops_1_bits_mem_size; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_mem_signed_0 = io_core_dis_uops_1_bits_mem_signed; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_uses_ldq_0 = io_core_dis_uops_1_bits_uses_ldq; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_uses_stq_0 = io_core_dis_uops_1_bits_uses_stq; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_unique_0 = io_core_dis_uops_1_bits_is_unique; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_flush_on_commit_0 = io_core_dis_uops_1_bits_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_csr_cmd_0 = io_core_dis_uops_1_bits_csr_cmd; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_ldst_is_rs1_0 = io_core_dis_uops_1_bits_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_ldst_0 = io_core_dis_uops_1_bits_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_lrs1_0 = io_core_dis_uops_1_bits_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_lrs2_0 = io_core_dis_uops_1_bits_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_lrs3_0 = io_core_dis_uops_1_bits_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_dst_rtype_0 = io_core_dis_uops_1_bits_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_lrs1_rtype_0 = io_core_dis_uops_1_bits_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_lrs2_rtype_0 = io_core_dis_uops_1_bits_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_frs3_en_0 = io_core_dis_uops_1_bits_frs3_en; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fcn_dw_0 = io_core_dis_uops_1_bits_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_fcn_op_0 = io_core_dis_uops_1_bits_fcn_op; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_val_0 = io_core_dis_uops_1_bits_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_fp_rm_0 = io_core_dis_uops_1_bits_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_fp_typ_0 = io_core_dis_uops_1_bits_fp_typ; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_xcpt_pf_if_0 = io_core_dis_uops_1_bits_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_xcpt_ae_if_0 = io_core_dis_uops_1_bits_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_xcpt_ma_if_0 = io_core_dis_uops_1_bits_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_bp_debug_if_0 = io_core_dis_uops_1_bits_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_bp_xcpt_if_0 = io_core_dis_uops_1_bits_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_debug_fsrc_0 = io_core_dis_uops_1_bits_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_debug_tsrc_0 = io_core_dis_uops_1_bits_debug_tsrc; // @[lsu.scala:211:7] wire io_core_commit_valids_0_0 = io_core_commit_valids_0; // @[lsu.scala:211:7] wire io_core_commit_valids_1_0 = io_core_commit_valids_1; // @[lsu.scala:211:7] wire io_core_commit_arch_valids_0_0 = io_core_commit_arch_valids_0; // @[lsu.scala:211:7] wire io_core_commit_arch_valids_1_0 = io_core_commit_arch_valids_1; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_0_inst_0 = io_core_commit_uops_0_inst; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_0_debug_inst_0 = io_core_commit_uops_0_debug_inst; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_rvc_0 = io_core_commit_uops_0_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_commit_uops_0_debug_pc_0 = io_core_commit_uops_0_debug_pc; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_0_0 = io_core_commit_uops_0_iq_type_0; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_1_0 = io_core_commit_uops_0_iq_type_1; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_2_0 = io_core_commit_uops_0_iq_type_2; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_3_0 = io_core_commit_uops_0_iq_type_3; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_0_0 = io_core_commit_uops_0_fu_code_0; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_1_0 = io_core_commit_uops_0_fu_code_1; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_2_0 = io_core_commit_uops_0_fu_code_2; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_3_0 = io_core_commit_uops_0_fu_code_3; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_4_0 = io_core_commit_uops_0_fu_code_4; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_5_0 = io_core_commit_uops_0_fu_code_5; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_6_0 = io_core_commit_uops_0_fu_code_6; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_7_0 = io_core_commit_uops_0_fu_code_7; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_8_0 = io_core_commit_uops_0_fu_code_8; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_9_0 = io_core_commit_uops_0_fu_code_9; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_issued_0 = io_core_commit_uops_0_iw_issued; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_issued_partial_agen_0 = io_core_commit_uops_0_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_issued_partial_dgen_0 = io_core_commit_uops_0_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_iw_p1_speculative_child_0 = io_core_commit_uops_0_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_iw_p2_speculative_child_0 = io_core_commit_uops_0_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_p1_bypass_hint_0 = io_core_commit_uops_0_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_p2_bypass_hint_0 = io_core_commit_uops_0_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_p3_bypass_hint_0 = io_core_commit_uops_0_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_dis_col_sel_0 = io_core_commit_uops_0_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_commit_uops_0_br_mask_0 = io_core_commit_uops_0_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_0_br_tag_0 = io_core_commit_uops_0_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_0_br_type_0 = io_core_commit_uops_0_br_type; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_sfb_0 = io_core_commit_uops_0_is_sfb; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_fence_0 = io_core_commit_uops_0_is_fence; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_fencei_0 = io_core_commit_uops_0_is_fencei; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_sfence_0 = io_core_commit_uops_0_is_sfence; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_amo_0 = io_core_commit_uops_0_is_amo; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_eret_0 = io_core_commit_uops_0_is_eret; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_sys_pc2epc_0 = io_core_commit_uops_0_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_rocc_0 = io_core_commit_uops_0_is_rocc; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_mov_0 = io_core_commit_uops_0_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_ftq_idx_0 = io_core_commit_uops_0_ftq_idx; // @[lsu.scala:211:7] wire io_core_commit_uops_0_edge_inst_0 = io_core_commit_uops_0_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_pc_lob_0 = io_core_commit_uops_0_pc_lob; // @[lsu.scala:211:7] wire io_core_commit_uops_0_taken_0 = io_core_commit_uops_0_taken; // @[lsu.scala:211:7] wire io_core_commit_uops_0_imm_rename_0 = io_core_commit_uops_0_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_imm_sel_0 = io_core_commit_uops_0_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_pimm_0 = io_core_commit_uops_0_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_commit_uops_0_imm_packed_0 = io_core_commit_uops_0_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_op1_sel_0 = io_core_commit_uops_0_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_op2_sel_0 = io_core_commit_uops_0_op2_sel; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ldst_0 = io_core_commit_uops_0_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_wen_0 = io_core_commit_uops_0_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ren1_0 = io_core_commit_uops_0_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ren2_0 = io_core_commit_uops_0_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ren3_0 = io_core_commit_uops_0_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_swap12_0 = io_core_commit_uops_0_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_swap23_0 = io_core_commit_uops_0_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_fp_ctrl_typeTagIn_0 = io_core_commit_uops_0_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_fp_ctrl_typeTagOut_0 = io_core_commit_uops_0_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_fromint_0 = io_core_commit_uops_0_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_toint_0 = io_core_commit_uops_0_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_fastpipe_0 = io_core_commit_uops_0_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_fma_0 = io_core_commit_uops_0_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_div_0 = io_core_commit_uops_0_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_sqrt_0 = io_core_commit_uops_0_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_wflags_0 = io_core_commit_uops_0_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_vec_0 = io_core_commit_uops_0_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_rob_idx_0 = io_core_commit_uops_0_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_0_ldq_idx_0 = io_core_commit_uops_0_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_0_stq_idx_0 = io_core_commit_uops_0_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_rxq_idx_0 = io_core_commit_uops_0_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_pdst_0 = io_core_commit_uops_0_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_prs1_0 = io_core_commit_uops_0_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_prs2_0 = io_core_commit_uops_0_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_prs3_0 = io_core_commit_uops_0_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_ppred_0 = io_core_commit_uops_0_ppred; // @[lsu.scala:211:7] wire io_core_commit_uops_0_prs1_busy_0 = io_core_commit_uops_0_prs1_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_0_prs2_busy_0 = io_core_commit_uops_0_prs2_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_0_prs3_busy_0 = io_core_commit_uops_0_prs3_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_0_ppred_busy_0 = io_core_commit_uops_0_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_stale_pdst_0 = io_core_commit_uops_0_stale_pdst; // @[lsu.scala:211:7] wire io_core_commit_uops_0_exception_0 = io_core_commit_uops_0_exception; // @[lsu.scala:211:7] wire [63:0] io_core_commit_uops_0_exc_cause_0 = io_core_commit_uops_0_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_mem_cmd_0 = io_core_commit_uops_0_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_mem_size_0 = io_core_commit_uops_0_mem_size; // @[lsu.scala:211:7] wire io_core_commit_uops_0_mem_signed_0 = io_core_commit_uops_0_mem_signed; // @[lsu.scala:211:7] wire io_core_commit_uops_0_uses_ldq_0 = io_core_commit_uops_0_uses_ldq; // @[lsu.scala:211:7] wire io_core_commit_uops_0_uses_stq_0 = io_core_commit_uops_0_uses_stq; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_unique_0 = io_core_commit_uops_0_is_unique; // @[lsu.scala:211:7] wire io_core_commit_uops_0_flush_on_commit_0 = io_core_commit_uops_0_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_csr_cmd_0 = io_core_commit_uops_0_csr_cmd; // @[lsu.scala:211:7] wire io_core_commit_uops_0_ldst_is_rs1_0 = io_core_commit_uops_0_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_ldst_0 = io_core_commit_uops_0_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_lrs1_0 = io_core_commit_uops_0_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_lrs2_0 = io_core_commit_uops_0_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_lrs3_0 = io_core_commit_uops_0_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_dst_rtype_0 = io_core_commit_uops_0_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_lrs1_rtype_0 = io_core_commit_uops_0_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_lrs2_rtype_0 = io_core_commit_uops_0_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_commit_uops_0_frs3_en_0 = io_core_commit_uops_0_frs3_en; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fcn_dw_0 = io_core_commit_uops_0_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_fcn_op_0 = io_core_commit_uops_0_fcn_op; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_val_0 = io_core_commit_uops_0_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_fp_rm_0 = io_core_commit_uops_0_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_fp_typ_0 = io_core_commit_uops_0_fp_typ; // @[lsu.scala:211:7] wire io_core_commit_uops_0_xcpt_pf_if_0 = io_core_commit_uops_0_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_xcpt_ae_if_0 = io_core_commit_uops_0_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_xcpt_ma_if_0 = io_core_commit_uops_0_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_bp_debug_if_0 = io_core_commit_uops_0_bp_debug_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_bp_xcpt_if_0 = io_core_commit_uops_0_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_debug_fsrc_0 = io_core_commit_uops_0_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_debug_tsrc_0 = io_core_commit_uops_0_debug_tsrc; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_1_inst_0 = io_core_commit_uops_1_inst; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_1_debug_inst_0 = io_core_commit_uops_1_debug_inst; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_rvc_0 = io_core_commit_uops_1_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_commit_uops_1_debug_pc_0 = io_core_commit_uops_1_debug_pc; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_0_0 = io_core_commit_uops_1_iq_type_0; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_1_0 = io_core_commit_uops_1_iq_type_1; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_2_0 = io_core_commit_uops_1_iq_type_2; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_3_0 = io_core_commit_uops_1_iq_type_3; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_0_0 = io_core_commit_uops_1_fu_code_0; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_1_0 = io_core_commit_uops_1_fu_code_1; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_2_0 = io_core_commit_uops_1_fu_code_2; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_3_0 = io_core_commit_uops_1_fu_code_3; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_4_0 = io_core_commit_uops_1_fu_code_4; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_5_0 = io_core_commit_uops_1_fu_code_5; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_6_0 = io_core_commit_uops_1_fu_code_6; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_7_0 = io_core_commit_uops_1_fu_code_7; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_8_0 = io_core_commit_uops_1_fu_code_8; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_9_0 = io_core_commit_uops_1_fu_code_9; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_issued_0 = io_core_commit_uops_1_iw_issued; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_issued_partial_agen_0 = io_core_commit_uops_1_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_issued_partial_dgen_0 = io_core_commit_uops_1_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_iw_p1_speculative_child_0 = io_core_commit_uops_1_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_iw_p2_speculative_child_0 = io_core_commit_uops_1_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_p1_bypass_hint_0 = io_core_commit_uops_1_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_p2_bypass_hint_0 = io_core_commit_uops_1_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_p3_bypass_hint_0 = io_core_commit_uops_1_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_dis_col_sel_0 = io_core_commit_uops_1_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_commit_uops_1_br_mask_0 = io_core_commit_uops_1_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_1_br_tag_0 = io_core_commit_uops_1_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_1_br_type_0 = io_core_commit_uops_1_br_type; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_sfb_0 = io_core_commit_uops_1_is_sfb; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_fence_0 = io_core_commit_uops_1_is_fence; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_fencei_0 = io_core_commit_uops_1_is_fencei; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_sfence_0 = io_core_commit_uops_1_is_sfence; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_amo_0 = io_core_commit_uops_1_is_amo; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_eret_0 = io_core_commit_uops_1_is_eret; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_sys_pc2epc_0 = io_core_commit_uops_1_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_rocc_0 = io_core_commit_uops_1_is_rocc; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_mov_0 = io_core_commit_uops_1_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_ftq_idx_0 = io_core_commit_uops_1_ftq_idx; // @[lsu.scala:211:7] wire io_core_commit_uops_1_edge_inst_0 = io_core_commit_uops_1_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_pc_lob_0 = io_core_commit_uops_1_pc_lob; // @[lsu.scala:211:7] wire io_core_commit_uops_1_taken_0 = io_core_commit_uops_1_taken; // @[lsu.scala:211:7] wire io_core_commit_uops_1_imm_rename_0 = io_core_commit_uops_1_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_imm_sel_0 = io_core_commit_uops_1_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_pimm_0 = io_core_commit_uops_1_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_commit_uops_1_imm_packed_0 = io_core_commit_uops_1_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_op1_sel_0 = io_core_commit_uops_1_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_op2_sel_0 = io_core_commit_uops_1_op2_sel; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ldst_0 = io_core_commit_uops_1_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_wen_0 = io_core_commit_uops_1_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ren1_0 = io_core_commit_uops_1_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ren2_0 = io_core_commit_uops_1_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ren3_0 = io_core_commit_uops_1_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_swap12_0 = io_core_commit_uops_1_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_swap23_0 = io_core_commit_uops_1_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_fp_ctrl_typeTagIn_0 = io_core_commit_uops_1_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_fp_ctrl_typeTagOut_0 = io_core_commit_uops_1_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_fromint_0 = io_core_commit_uops_1_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_toint_0 = io_core_commit_uops_1_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_fastpipe_0 = io_core_commit_uops_1_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_fma_0 = io_core_commit_uops_1_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_div_0 = io_core_commit_uops_1_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_sqrt_0 = io_core_commit_uops_1_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_wflags_0 = io_core_commit_uops_1_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_vec_0 = io_core_commit_uops_1_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_rob_idx_0 = io_core_commit_uops_1_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_1_ldq_idx_0 = io_core_commit_uops_1_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_1_stq_idx_0 = io_core_commit_uops_1_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_rxq_idx_0 = io_core_commit_uops_1_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_pdst_0 = io_core_commit_uops_1_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_prs1_0 = io_core_commit_uops_1_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_prs2_0 = io_core_commit_uops_1_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_prs3_0 = io_core_commit_uops_1_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_ppred_0 = io_core_commit_uops_1_ppred; // @[lsu.scala:211:7] wire io_core_commit_uops_1_prs1_busy_0 = io_core_commit_uops_1_prs1_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_1_prs2_busy_0 = io_core_commit_uops_1_prs2_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_1_prs3_busy_0 = io_core_commit_uops_1_prs3_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_1_ppred_busy_0 = io_core_commit_uops_1_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_stale_pdst_0 = io_core_commit_uops_1_stale_pdst; // @[lsu.scala:211:7] wire io_core_commit_uops_1_exception_0 = io_core_commit_uops_1_exception; // @[lsu.scala:211:7] wire [63:0] io_core_commit_uops_1_exc_cause_0 = io_core_commit_uops_1_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_mem_cmd_0 = io_core_commit_uops_1_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_mem_size_0 = io_core_commit_uops_1_mem_size; // @[lsu.scala:211:7] wire io_core_commit_uops_1_mem_signed_0 = io_core_commit_uops_1_mem_signed; // @[lsu.scala:211:7] wire io_core_commit_uops_1_uses_ldq_0 = io_core_commit_uops_1_uses_ldq; // @[lsu.scala:211:7] wire io_core_commit_uops_1_uses_stq_0 = io_core_commit_uops_1_uses_stq; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_unique_0 = io_core_commit_uops_1_is_unique; // @[lsu.scala:211:7] wire io_core_commit_uops_1_flush_on_commit_0 = io_core_commit_uops_1_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_csr_cmd_0 = io_core_commit_uops_1_csr_cmd; // @[lsu.scala:211:7] wire io_core_commit_uops_1_ldst_is_rs1_0 = io_core_commit_uops_1_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_ldst_0 = io_core_commit_uops_1_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_lrs1_0 = io_core_commit_uops_1_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_lrs2_0 = io_core_commit_uops_1_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_lrs3_0 = io_core_commit_uops_1_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_dst_rtype_0 = io_core_commit_uops_1_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_lrs1_rtype_0 = io_core_commit_uops_1_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_lrs2_rtype_0 = io_core_commit_uops_1_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_commit_uops_1_frs3_en_0 = io_core_commit_uops_1_frs3_en; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fcn_dw_0 = io_core_commit_uops_1_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_fcn_op_0 = io_core_commit_uops_1_fcn_op; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_val_0 = io_core_commit_uops_1_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_fp_rm_0 = io_core_commit_uops_1_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_fp_typ_0 = io_core_commit_uops_1_fp_typ; // @[lsu.scala:211:7] wire io_core_commit_uops_1_xcpt_pf_if_0 = io_core_commit_uops_1_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_xcpt_ae_if_0 = io_core_commit_uops_1_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_xcpt_ma_if_0 = io_core_commit_uops_1_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_bp_debug_if_0 = io_core_commit_uops_1_bp_debug_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_bp_xcpt_if_0 = io_core_commit_uops_1_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_debug_fsrc_0 = io_core_commit_uops_1_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_debug_tsrc_0 = io_core_commit_uops_1_debug_tsrc; // @[lsu.scala:211:7] wire io_core_commit_fflags_valid_0 = io_core_commit_fflags_valid; // @[lsu.scala:211:7] wire [4:0] io_core_commit_fflags_bits_0 = io_core_commit_fflags_bits; // @[lsu.scala:211:7] wire [63:0] io_core_commit_debug_wdata_0_0 = io_core_commit_debug_wdata_0; // @[lsu.scala:211:7] wire [63:0] io_core_commit_debug_wdata_1_0 = io_core_commit_debug_wdata_1; // @[lsu.scala:211:7] wire io_core_commit_load_at_rob_head_0 = io_core_commit_load_at_rob_head; // @[lsu.scala:211:7] wire io_core_fence_dmem_0 = io_core_fence_dmem; // @[lsu.scala:211:7] wire [11:0] io_core_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask; // @[lsu.scala:211:7] wire [11:0] io_core_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask; // @[lsu.scala:211:7] wire [31:0] io_core_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_0_0 = io_core_brupdate_b2_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_1_0 = io_core_brupdate_b2_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_2_0 = io_core_brupdate_b2_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_3_0 = io_core_brupdate_b2_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_0_0 = io_core_brupdate_b2_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_1_0 = io_core_brupdate_b2_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_2_0 = io_core_brupdate_b2_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_3_0 = io_core_brupdate_b2_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_4_0 = io_core_brupdate_b2_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_5_0 = io_core_brupdate_b2_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_6_0 = io_core_brupdate_b2_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_7_0 = io_core_brupdate_b2_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_8_0 = io_core_brupdate_b2_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_9_0 = io_core_brupdate_b2_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_issued_0 = io_core_brupdate_b2_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_issued_partial_agen_0 = io_core_brupdate_b2_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_core_brupdate_b2_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_iw_p1_speculative_child_0 = io_core_brupdate_b2_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_iw_p2_speculative_child_0 = io_core_brupdate_b2_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_dis_col_sel_0 = io_core_brupdate_b2_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_brupdate_b2_uop_br_type_0 = io_core_brupdate_b2_uop_br_type; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_sfence_0 = io_core_brupdate_b2_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_eret_0 = io_core_brupdate_b2_uop_is_eret; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_rocc_0 = io_core_brupdate_b2_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_mov_0 = io_core_brupdate_b2_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_imm_rename_0 = io_core_brupdate_b2_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_imm_sel_0 = io_core_brupdate_b2_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_pimm_0 = io_core_brupdate_b2_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_op1_sel_0 = io_core_brupdate_b2_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_op2_sel_0 = io_core_brupdate_b2_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ldst_0 = io_core_brupdate_b2_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_wen_0 = io_core_brupdate_b2_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ren1_0 = io_core_brupdate_b2_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ren2_0 = io_core_brupdate_b2_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ren3_0 = io_core_brupdate_b2_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_swap12_0 = io_core_brupdate_b2_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_swap23_0 = io_core_brupdate_b2_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_fromint_0 = io_core_brupdate_b2_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_toint_0 = io_core_brupdate_b2_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_core_brupdate_b2_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_fma_0 = io_core_brupdate_b2_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_div_0 = io_core_brupdate_b2_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_core_brupdate_b2_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_wflags_0 = io_core_brupdate_b2_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_vec_0 = io_core_brupdate_b2_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_csr_cmd_0 = io_core_brupdate_b2_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fcn_dw_0 = io_core_brupdate_b2_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_fcn_op_0 = io_core_brupdate_b2_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_fp_rm_0 = io_core_brupdate_b2_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_fp_typ_0 = io_core_brupdate_b2_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict; // @[lsu.scala:211:7] wire io_core_brupdate_b2_taken_0 = io_core_brupdate_b2_taken; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel; // @[lsu.scala:211:7] wire [39:0] io_core_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target; // @[lsu.scala:211:7] wire [20:0] io_core_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset; // @[lsu.scala:211:7] wire [5:0] io_core_rob_pnr_idx_0 = io_core_rob_pnr_idx; // @[lsu.scala:211:7] wire [5:0] io_core_rob_head_idx_0 = io_core_rob_head_idx; // @[lsu.scala:211:7] wire io_core_exception_0 = io_core_exception; // @[lsu.scala:211:7] wire [63:0] io_core_tsc_reg_0 = io_core_tsc_reg; // @[lsu.scala:211:7] wire io_core_status_debug_0 = io_core_status_debug; // @[lsu.scala:211:7] wire io_core_status_cease_0 = io_core_status_cease; // @[lsu.scala:211:7] wire io_core_status_wfi_0 = io_core_status_wfi; // @[lsu.scala:211:7] wire [1:0] io_core_status_dprv_0 = io_core_status_dprv; // @[lsu.scala:211:7] wire io_core_status_dv_0 = io_core_status_dv; // @[lsu.scala:211:7] wire [1:0] io_core_status_prv_0 = io_core_status_prv; // @[lsu.scala:211:7] wire io_core_status_v_0 = io_core_status_v; // @[lsu.scala:211:7] wire io_core_status_sd_0 = io_core_status_sd; // @[lsu.scala:211:7] wire io_core_status_mpv_0 = io_core_status_mpv; // @[lsu.scala:211:7] wire io_core_status_gva_0 = io_core_status_gva; // @[lsu.scala:211:7] wire io_core_status_tsr_0 = io_core_status_tsr; // @[lsu.scala:211:7] wire io_core_status_tw_0 = io_core_status_tw; // @[lsu.scala:211:7] wire io_core_status_tvm_0 = io_core_status_tvm; // @[lsu.scala:211:7] wire io_core_status_mxr_0 = io_core_status_mxr; // @[lsu.scala:211:7] wire io_core_status_sum_0 = io_core_status_sum; // @[lsu.scala:211:7] wire io_core_status_mprv_0 = io_core_status_mprv; // @[lsu.scala:211:7] wire [1:0] io_core_status_fs_0 = io_core_status_fs; // @[lsu.scala:211:7] wire [1:0] io_core_status_mpp_0 = io_core_status_mpp; // @[lsu.scala:211:7] wire io_core_status_spp_0 = io_core_status_spp; // @[lsu.scala:211:7] wire io_core_status_mpie_0 = io_core_status_mpie; // @[lsu.scala:211:7] wire io_core_status_spie_0 = io_core_status_spie; // @[lsu.scala:211:7] wire io_core_status_mie_0 = io_core_status_mie; // @[lsu.scala:211:7] wire io_core_status_sie_0 = io_core_status_sie; // @[lsu.scala:211:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[lsu.scala:211:7] wire io_dmem_resp_0_valid_0 = io_dmem_resp_0_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_resp_0_bits_uop_inst_0 = io_dmem_resp_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_resp_0_bits_uop_debug_inst_0 = io_dmem_resp_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_rvc_0 = io_dmem_resp_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_resp_0_bits_uop_debug_pc_0 = io_dmem_resp_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_0_0 = io_dmem_resp_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_1_0 = io_dmem_resp_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_2_0 = io_dmem_resp_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_3_0 = io_dmem_resp_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_0_0 = io_dmem_resp_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_1_0 = io_dmem_resp_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_2_0 = io_dmem_resp_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_3_0 = io_dmem_resp_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_4_0 = io_dmem_resp_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_5_0 = io_dmem_resp_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_6_0 = io_dmem_resp_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_7_0 = io_dmem_resp_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_8_0 = io_dmem_resp_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_9_0 = io_dmem_resp_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_issued_0 = io_dmem_resp_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_issued_partial_agen_0 = io_dmem_resp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_issued_partial_dgen_0 = io_dmem_resp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_iw_p1_speculative_child_0 = io_dmem_resp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_iw_p2_speculative_child_0 = io_dmem_resp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_p1_bypass_hint_0 = io_dmem_resp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_p2_bypass_hint_0 = io_dmem_resp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_p3_bypass_hint_0 = io_dmem_resp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_dis_col_sel_0 = io_dmem_resp_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_dmem_resp_0_bits_uop_br_mask_0 = io_dmem_resp_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_resp_0_bits_uop_br_tag_0 = io_dmem_resp_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_resp_0_bits_uop_br_type_0 = io_dmem_resp_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_sfb_0 = io_dmem_resp_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_fence_0 = io_dmem_resp_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_fencei_0 = io_dmem_resp_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_sfence_0 = io_dmem_resp_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_amo_0 = io_dmem_resp_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_eret_0 = io_dmem_resp_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_sys_pc2epc_0 = io_dmem_resp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_rocc_0 = io_dmem_resp_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_mov_0 = io_dmem_resp_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_ftq_idx_0 = io_dmem_resp_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_edge_inst_0 = io_dmem_resp_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_pc_lob_0 = io_dmem_resp_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_taken_0 = io_dmem_resp_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_imm_rename_0 = io_dmem_resp_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_imm_sel_0 = io_dmem_resp_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_pimm_0 = io_dmem_resp_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_resp_0_bits_uop_imm_packed_0 = io_dmem_resp_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_op1_sel_0 = io_dmem_resp_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_op2_sel_0 = io_dmem_resp_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ldst_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_wen_0 = io_dmem_resp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ren1_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ren2_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ren3_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_swap12_0 = io_dmem_resp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_swap23_0 = io_dmem_resp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_fromint_0 = io_dmem_resp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_toint_0 = io_dmem_resp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_fma_0 = io_dmem_resp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_div_0 = io_dmem_resp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_sqrt_0 = io_dmem_resp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_wflags_0 = io_dmem_resp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_vec_0 = io_dmem_resp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_rob_idx_0 = io_dmem_resp_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_resp_0_bits_uop_ldq_idx_0 = io_dmem_resp_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_resp_0_bits_uop_stq_idx_0 = io_dmem_resp_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_rxq_idx_0 = io_dmem_resp_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_pdst_0 = io_dmem_resp_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_prs1_0 = io_dmem_resp_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_prs2_0 = io_dmem_resp_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_prs3_0 = io_dmem_resp_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_ppred_0 = io_dmem_resp_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_prs1_busy_0 = io_dmem_resp_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_prs2_busy_0 = io_dmem_resp_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_prs3_busy_0 = io_dmem_resp_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_ppred_busy_0 = io_dmem_resp_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_stale_pdst_0 = io_dmem_resp_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_exception_0 = io_dmem_resp_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_resp_0_bits_uop_exc_cause_0 = io_dmem_resp_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_mem_cmd_0 = io_dmem_resp_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_mem_size_0 = io_dmem_resp_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_mem_signed_0 = io_dmem_resp_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_uses_ldq_0 = io_dmem_resp_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_uses_stq_0 = io_dmem_resp_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_unique_0 = io_dmem_resp_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_flush_on_commit_0 = io_dmem_resp_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_csr_cmd_0 = io_dmem_resp_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_ldst_is_rs1_0 = io_dmem_resp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_ldst_0 = io_dmem_resp_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs1_0 = io_dmem_resp_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs2_0 = io_dmem_resp_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs3_0 = io_dmem_resp_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_dst_rtype_0 = io_dmem_resp_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype_0 = io_dmem_resp_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype_0 = io_dmem_resp_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_frs3_en_0 = io_dmem_resp_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fcn_dw_0 = io_dmem_resp_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_fcn_op_0 = io_dmem_resp_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_val_0 = io_dmem_resp_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_fp_rm_0 = io_dmem_resp_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_fp_typ_0 = io_dmem_resp_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_xcpt_pf_if_0 = io_dmem_resp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_xcpt_ae_if_0 = io_dmem_resp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_xcpt_ma_if_0 = io_dmem_resp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_bp_debug_if_0 = io_dmem_resp_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_bp_xcpt_if_0 = io_dmem_resp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_debug_fsrc_0 = io_dmem_resp_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_debug_tsrc_0 = io_dmem_resp_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_dmem_resp_0_bits_data_0 = io_dmem_resp_0_bits_data; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_is_hella_0 = io_dmem_resp_0_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_valid_0 = io_dmem_store_ack_0_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_store_ack_0_bits_uop_inst_0 = io_dmem_store_ack_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_store_ack_0_bits_uop_debug_inst_0 = io_dmem_store_ack_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_rvc_0 = io_dmem_store_ack_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_store_ack_0_bits_uop_debug_pc_0 = io_dmem_store_ack_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_0_0 = io_dmem_store_ack_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_1_0 = io_dmem_store_ack_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_2_0 = io_dmem_store_ack_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_3_0 = io_dmem_store_ack_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_0_0 = io_dmem_store_ack_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_1_0 = io_dmem_store_ack_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_2_0 = io_dmem_store_ack_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_3_0 = io_dmem_store_ack_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_4_0 = io_dmem_store_ack_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_5_0 = io_dmem_store_ack_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_6_0 = io_dmem_store_ack_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_7_0 = io_dmem_store_ack_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_8_0 = io_dmem_store_ack_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_9_0 = io_dmem_store_ack_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_issued_0 = io_dmem_store_ack_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen_0 = io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen_0 = io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child_0 = io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child_0 = io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint_0 = io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint_0 = io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint_0 = io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_dis_col_sel_0 = io_dmem_store_ack_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_dmem_store_ack_0_bits_uop_br_mask_0 = io_dmem_store_ack_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_store_ack_0_bits_uop_br_tag_0 = io_dmem_store_ack_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_store_ack_0_bits_uop_br_type_0 = io_dmem_store_ack_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_sfb_0 = io_dmem_store_ack_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_fence_0 = io_dmem_store_ack_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_fencei_0 = io_dmem_store_ack_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_sfence_0 = io_dmem_store_ack_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_amo_0 = io_dmem_store_ack_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_eret_0 = io_dmem_store_ack_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_sys_pc2epc_0 = io_dmem_store_ack_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_rocc_0 = io_dmem_store_ack_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_mov_0 = io_dmem_store_ack_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_ftq_idx_0 = io_dmem_store_ack_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_edge_inst_0 = io_dmem_store_ack_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_pc_lob_0 = io_dmem_store_ack_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_taken_0 = io_dmem_store_ack_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_imm_rename_0 = io_dmem_store_ack_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_imm_sel_0 = io_dmem_store_ack_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_pimm_0 = io_dmem_store_ack_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_store_ack_0_bits_uop_imm_packed_0 = io_dmem_store_ack_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_op1_sel_0 = io_dmem_store_ack_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_op2_sel_0 = io_dmem_store_ack_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_wen_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_toint_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_fma_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_div_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_vec_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_rob_idx_0 = io_dmem_store_ack_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_store_ack_0_bits_uop_ldq_idx_0 = io_dmem_store_ack_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_store_ack_0_bits_uop_stq_idx_0 = io_dmem_store_ack_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_rxq_idx_0 = io_dmem_store_ack_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_pdst_0 = io_dmem_store_ack_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_prs1_0 = io_dmem_store_ack_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_prs2_0 = io_dmem_store_ack_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_prs3_0 = io_dmem_store_ack_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_ppred_0 = io_dmem_store_ack_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_prs1_busy_0 = io_dmem_store_ack_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_prs2_busy_0 = io_dmem_store_ack_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_prs3_busy_0 = io_dmem_store_ack_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_ppred_busy_0 = io_dmem_store_ack_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_stale_pdst_0 = io_dmem_store_ack_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_exception_0 = io_dmem_store_ack_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_store_ack_0_bits_uop_exc_cause_0 = io_dmem_store_ack_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_mem_cmd_0 = io_dmem_store_ack_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_mem_size_0 = io_dmem_store_ack_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_mem_signed_0 = io_dmem_store_ack_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_uses_ldq_0 = io_dmem_store_ack_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_uses_stq_0 = io_dmem_store_ack_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_unique_0 = io_dmem_store_ack_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_flush_on_commit_0 = io_dmem_store_ack_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_csr_cmd_0 = io_dmem_store_ack_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_ldst_is_rs1_0 = io_dmem_store_ack_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_ldst_0 = io_dmem_store_ack_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_lrs1_0 = io_dmem_store_ack_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_lrs2_0 = io_dmem_store_ack_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_lrs3_0 = io_dmem_store_ack_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_dst_rtype_0 = io_dmem_store_ack_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_lrs1_rtype_0 = io_dmem_store_ack_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_lrs2_rtype_0 = io_dmem_store_ack_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_frs3_en_0 = io_dmem_store_ack_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fcn_dw_0 = io_dmem_store_ack_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_fcn_op_0 = io_dmem_store_ack_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_val_0 = io_dmem_store_ack_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_fp_rm_0 = io_dmem_store_ack_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_fp_typ_0 = io_dmem_store_ack_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_xcpt_pf_if_0 = io_dmem_store_ack_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_xcpt_ae_if_0 = io_dmem_store_ack_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_xcpt_ma_if_0 = io_dmem_store_ack_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_bp_debug_if_0 = io_dmem_store_ack_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_bp_xcpt_if_0 = io_dmem_store_ack_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_debug_fsrc_0 = io_dmem_store_ack_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_debug_tsrc_0 = io_dmem_store_ack_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [39:0] io_dmem_store_ack_0_bits_addr_0 = io_dmem_store_ack_0_bits_addr; // @[lsu.scala:211:7] wire [63:0] io_dmem_store_ack_0_bits_data_0 = io_dmem_store_ack_0_bits_data; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_is_hella_0 = io_dmem_store_ack_0_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_nack_0_valid_0 = io_dmem_nack_0_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_nack_0_bits_uop_inst_0 = io_dmem_nack_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_nack_0_bits_uop_debug_inst_0 = io_dmem_nack_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_rvc_0 = io_dmem_nack_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_nack_0_bits_uop_debug_pc_0 = io_dmem_nack_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_0_0 = io_dmem_nack_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_1_0 = io_dmem_nack_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_2_0 = io_dmem_nack_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_3_0 = io_dmem_nack_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_0_0 = io_dmem_nack_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_1_0 = io_dmem_nack_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_2_0 = io_dmem_nack_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_3_0 = io_dmem_nack_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_4_0 = io_dmem_nack_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_5_0 = io_dmem_nack_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_6_0 = io_dmem_nack_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_7_0 = io_dmem_nack_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_8_0 = io_dmem_nack_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_9_0 = io_dmem_nack_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_issued_0 = io_dmem_nack_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_issued_partial_agen_0 = io_dmem_nack_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_issued_partial_dgen_0 = io_dmem_nack_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_iw_p1_speculative_child_0 = io_dmem_nack_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_iw_p2_speculative_child_0 = io_dmem_nack_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_p1_bypass_hint_0 = io_dmem_nack_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_p2_bypass_hint_0 = io_dmem_nack_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_p3_bypass_hint_0 = io_dmem_nack_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_dis_col_sel_0 = io_dmem_nack_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_dmem_nack_0_bits_uop_br_mask_0 = io_dmem_nack_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_nack_0_bits_uop_br_tag_0 = io_dmem_nack_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_nack_0_bits_uop_br_type_0 = io_dmem_nack_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_sfb_0 = io_dmem_nack_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_fence_0 = io_dmem_nack_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_fencei_0 = io_dmem_nack_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_sfence_0 = io_dmem_nack_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_amo_0 = io_dmem_nack_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_eret_0 = io_dmem_nack_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_sys_pc2epc_0 = io_dmem_nack_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_rocc_0 = io_dmem_nack_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_mov_0 = io_dmem_nack_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_ftq_idx_0 = io_dmem_nack_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_edge_inst_0 = io_dmem_nack_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_pc_lob_0 = io_dmem_nack_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_taken_0 = io_dmem_nack_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_imm_rename_0 = io_dmem_nack_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_imm_sel_0 = io_dmem_nack_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_pimm_0 = io_dmem_nack_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_nack_0_bits_uop_imm_packed_0 = io_dmem_nack_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_op1_sel_0 = io_dmem_nack_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_op2_sel_0 = io_dmem_nack_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ldst_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_wen_0 = io_dmem_nack_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ren1_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ren2_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ren3_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_swap12_0 = io_dmem_nack_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_swap23_0 = io_dmem_nack_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_fromint_0 = io_dmem_nack_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_toint_0 = io_dmem_nack_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_fma_0 = io_dmem_nack_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_div_0 = io_dmem_nack_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_sqrt_0 = io_dmem_nack_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_wflags_0 = io_dmem_nack_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_vec_0 = io_dmem_nack_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_rob_idx_0 = io_dmem_nack_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_nack_0_bits_uop_ldq_idx_0 = io_dmem_nack_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_nack_0_bits_uop_stq_idx_0 = io_dmem_nack_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_rxq_idx_0 = io_dmem_nack_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_pdst_0 = io_dmem_nack_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_prs1_0 = io_dmem_nack_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_prs2_0 = io_dmem_nack_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_prs3_0 = io_dmem_nack_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_ppred_0 = io_dmem_nack_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_prs1_busy_0 = io_dmem_nack_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_prs2_busy_0 = io_dmem_nack_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_prs3_busy_0 = io_dmem_nack_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_ppred_busy_0 = io_dmem_nack_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_stale_pdst_0 = io_dmem_nack_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_exception_0 = io_dmem_nack_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_nack_0_bits_uop_exc_cause_0 = io_dmem_nack_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_mem_cmd_0 = io_dmem_nack_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_mem_size_0 = io_dmem_nack_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_mem_signed_0 = io_dmem_nack_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_uses_ldq_0 = io_dmem_nack_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_uses_stq_0 = io_dmem_nack_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_unique_0 = io_dmem_nack_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_flush_on_commit_0 = io_dmem_nack_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_csr_cmd_0 = io_dmem_nack_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_ldst_is_rs1_0 = io_dmem_nack_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_ldst_0 = io_dmem_nack_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs1_0 = io_dmem_nack_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs2_0 = io_dmem_nack_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs3_0 = io_dmem_nack_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_dst_rtype_0 = io_dmem_nack_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype_0 = io_dmem_nack_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype_0 = io_dmem_nack_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_frs3_en_0 = io_dmem_nack_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fcn_dw_0 = io_dmem_nack_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_fcn_op_0 = io_dmem_nack_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_val_0 = io_dmem_nack_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_fp_rm_0 = io_dmem_nack_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_fp_typ_0 = io_dmem_nack_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_xcpt_pf_if_0 = io_dmem_nack_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_xcpt_ae_if_0 = io_dmem_nack_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_xcpt_ma_if_0 = io_dmem_nack_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_bp_debug_if_0 = io_dmem_nack_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_bp_xcpt_if_0 = io_dmem_nack_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_debug_fsrc_0 = io_dmem_nack_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_debug_tsrc_0 = io_dmem_nack_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [39:0] io_dmem_nack_0_bits_addr_0 = io_dmem_nack_0_bits_addr; // @[lsu.scala:211:7] wire [63:0] io_dmem_nack_0_bits_data_0 = io_dmem_nack_0_bits_data; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_is_hella_0 = io_dmem_nack_0_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_ll_resp_valid_0 = io_dmem_ll_resp_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_ll_resp_bits_uop_inst_0 = io_dmem_ll_resp_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_ll_resp_bits_uop_debug_inst_0 = io_dmem_ll_resp_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_rvc_0 = io_dmem_ll_resp_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_ll_resp_bits_uop_debug_pc_0 = io_dmem_ll_resp_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_0_0 = io_dmem_ll_resp_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_1_0 = io_dmem_ll_resp_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_2_0 = io_dmem_ll_resp_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_3_0 = io_dmem_ll_resp_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_0_0 = io_dmem_ll_resp_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_1_0 = io_dmem_ll_resp_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_2_0 = io_dmem_ll_resp_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_3_0 = io_dmem_ll_resp_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_4_0 = io_dmem_ll_resp_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_5_0 = io_dmem_ll_resp_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_6_0 = io_dmem_ll_resp_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_7_0 = io_dmem_ll_resp_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_8_0 = io_dmem_ll_resp_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_9_0 = io_dmem_ll_resp_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_issued_0 = io_dmem_ll_resp_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_issued_partial_agen_0 = io_dmem_ll_resp_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen_0 = io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_iw_p1_speculative_child_0 = io_dmem_ll_resp_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_iw_p2_speculative_child_0 = io_dmem_ll_resp_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint_0 = io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint_0 = io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint_0 = io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_dis_col_sel_0 = io_dmem_ll_resp_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_dmem_ll_resp_bits_uop_br_mask_0 = io_dmem_ll_resp_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_ll_resp_bits_uop_br_tag_0 = io_dmem_ll_resp_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_ll_resp_bits_uop_br_type_0 = io_dmem_ll_resp_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_sfb_0 = io_dmem_ll_resp_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_fence_0 = io_dmem_ll_resp_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_fencei_0 = io_dmem_ll_resp_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_sfence_0 = io_dmem_ll_resp_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_amo_0 = io_dmem_ll_resp_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_eret_0 = io_dmem_ll_resp_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_sys_pc2epc_0 = io_dmem_ll_resp_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_rocc_0 = io_dmem_ll_resp_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_mov_0 = io_dmem_ll_resp_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_ftq_idx_0 = io_dmem_ll_resp_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_edge_inst_0 = io_dmem_ll_resp_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_pc_lob_0 = io_dmem_ll_resp_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_taken_0 = io_dmem_ll_resp_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_imm_rename_0 = io_dmem_ll_resp_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_imm_sel_0 = io_dmem_ll_resp_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_pimm_0 = io_dmem_ll_resp_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_ll_resp_bits_uop_imm_packed_0 = io_dmem_ll_resp_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_op1_sel_0 = io_dmem_ll_resp_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_op2_sel_0 = io_dmem_ll_resp_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ldst_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_wen_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ren1_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ren2_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ren3_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_swap12_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_swap23_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_fromint_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_toint_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_fma_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_div_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_wflags_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_vec_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_rob_idx_0 = io_dmem_ll_resp_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_ll_resp_bits_uop_ldq_idx_0 = io_dmem_ll_resp_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_ll_resp_bits_uop_stq_idx_0 = io_dmem_ll_resp_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_rxq_idx_0 = io_dmem_ll_resp_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_pdst_0 = io_dmem_ll_resp_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_prs1_0 = io_dmem_ll_resp_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_prs2_0 = io_dmem_ll_resp_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_prs3_0 = io_dmem_ll_resp_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_ppred_0 = io_dmem_ll_resp_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_prs1_busy_0 = io_dmem_ll_resp_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_prs2_busy_0 = io_dmem_ll_resp_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_prs3_busy_0 = io_dmem_ll_resp_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_ppred_busy_0 = io_dmem_ll_resp_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_stale_pdst_0 = io_dmem_ll_resp_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_exception_0 = io_dmem_ll_resp_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_ll_resp_bits_uop_exc_cause_0 = io_dmem_ll_resp_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_mem_cmd_0 = io_dmem_ll_resp_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_mem_size_0 = io_dmem_ll_resp_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_mem_signed_0 = io_dmem_ll_resp_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_uses_ldq_0 = io_dmem_ll_resp_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_uses_stq_0 = io_dmem_ll_resp_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_unique_0 = io_dmem_ll_resp_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_flush_on_commit_0 = io_dmem_ll_resp_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_csr_cmd_0 = io_dmem_ll_resp_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_ldst_is_rs1_0 = io_dmem_ll_resp_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_ldst_0 = io_dmem_ll_resp_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_lrs1_0 = io_dmem_ll_resp_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_lrs2_0 = io_dmem_ll_resp_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_lrs3_0 = io_dmem_ll_resp_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_dst_rtype_0 = io_dmem_ll_resp_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_lrs1_rtype_0 = io_dmem_ll_resp_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_lrs2_rtype_0 = io_dmem_ll_resp_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_frs3_en_0 = io_dmem_ll_resp_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fcn_dw_0 = io_dmem_ll_resp_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_fcn_op_0 = io_dmem_ll_resp_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_val_0 = io_dmem_ll_resp_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_fp_rm_0 = io_dmem_ll_resp_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_fp_typ_0 = io_dmem_ll_resp_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_xcpt_pf_if_0 = io_dmem_ll_resp_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_xcpt_ae_if_0 = io_dmem_ll_resp_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_xcpt_ma_if_0 = io_dmem_ll_resp_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_bp_debug_if_0 = io_dmem_ll_resp_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_bp_xcpt_if_0 = io_dmem_ll_resp_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_debug_fsrc_0 = io_dmem_ll_resp_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_debug_tsrc_0 = io_dmem_ll_resp_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_dmem_ll_resp_bits_data_0 = io_dmem_ll_resp_bits_data; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_is_hella_0 = io_dmem_ll_resp_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_release_valid_0 = io_dmem_release_valid; // @[lsu.scala:211:7] wire [2:0] io_dmem_release_bits_opcode_0 = io_dmem_release_bits_opcode; // @[lsu.scala:211:7] wire [2:0] io_dmem_release_bits_param_0 = io_dmem_release_bits_param; // @[lsu.scala:211:7] wire [3:0] io_dmem_release_bits_size_0 = io_dmem_release_bits_size; // @[lsu.scala:211:7] wire [1:0] io_dmem_release_bits_source_0 = io_dmem_release_bits_source; // @[lsu.scala:211:7] wire [31:0] io_dmem_release_bits_address_0 = io_dmem_release_bits_address; // @[lsu.scala:211:7] wire [63:0] io_dmem_release_bits_data_0 = io_dmem_release_bits_data; // @[lsu.scala:211:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[lsu.scala:211:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[lsu.scala:211:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[lsu.scala:211:7] wire io_hellacache_req_valid_0 = io_hellacache_req_valid; // @[lsu.scala:211:7] wire [39:0] io_hellacache_req_bits_addr_0 = io_hellacache_req_bits_addr; // @[lsu.scala:211:7] wire io_hellacache_req_bits_dv_0 = io_hellacache_req_bits_dv; // @[lsu.scala:211:7] wire io_hellacache_s1_kill_0 = io_hellacache_s1_kill; // @[lsu.scala:211:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[lsu.scala:211:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[lsu.scala:211:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[lsu.scala:211:7] wire [15:0] _dmem_req_0_bits_data_T_17 = 16'h0; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_21 = 16'h0; // @[AMOALU.scala:29:69] wire [15:0] _mem_ldq_e_WIRE_bits_st_dep_mask = 16'h0; // @[lsu.scala:1064:73] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[lsu.scala:211:7] wire [31:0] io_core_status_isa = 32'h14112D; // @[lsu.scala:211:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[lsu.scala:211:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[lsu.scala:211:7] wire [22:0] io_core_status_zero2 = 23'h0; // @[lsu.scala:211:7] wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[lsu.scala:211:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_mbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_sbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_ube = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_upie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_hie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_uie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vtw = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_hu = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_spvp = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_spv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_gva = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_debug = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_cease = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_wfi = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_dv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_v = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sd = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mpv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_gva = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_tsr = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_tw = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_tvm = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mxr = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sum = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mprv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_spp = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mpie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_ube = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_spie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_upie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_hie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_uie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_predicated = 1'h0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_predicated = 1'h0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:211:7] wire io_core_status_mbe = 1'h0; // @[lsu.scala:211:7] wire io_core_status_sbe = 1'h0; // @[lsu.scala:211:7] wire io_core_status_sd_rv32 = 1'h0; // @[lsu.scala:211:7] wire io_core_status_ube = 1'h0; // @[lsu.scala:211:7] wire io_core_status_upie = 1'h0; // @[lsu.scala:211:7] wire io_core_status_hie = 1'h0; // @[lsu.scala:211:7] wire io_core_status_uie = 1'h0; // @[lsu.scala:211:7] wire io_dmem_s1_nack_advisory_0 = 1'h0; // @[lsu.scala:211:7] wire io_dmem_release_bits_corrupt = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_signed = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_no_resp = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_no_alloc = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_no_xcpt = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_nack_cause_raw = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_kill = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_uncached = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_signed = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_replay = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_replay_next = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_gpa_is_pte = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_ordered = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_acquire = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_release = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_grant = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_tlbMiss = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_blocked = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_canAcceptStoreThenLoad = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_canAcceptStoreThenRMW = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_canAcceptLoadThenLoad = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_storeBufferEmptyAfterLoad = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_storeBufferEmptyAfterStore = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_keep_clock_enabled = 1'h0; // @[lsu.scala:211:7] wire _block_load_mask_WIRE_0 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_1 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_2 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_3 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_4 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_5 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_6 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_7 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_8 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_9 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_10 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_11 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_12 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_13 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_14 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_15 = 1'h0; // @[lsu.scala:488:44] wire _can_fire_hella_incoming_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire _can_fire_hella_wakeup_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire _will_fire_sfence_0_will_fire_T = 1'h0; // @[lsu.scala:656:51] wire _will_fire_sfence_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_sfence_0_will_fire_T_4 = 1'h0; // @[lsu.scala:657:52] wire _will_fire_sfence_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_sfence_0_will_fire_T_8 = 1'h0; // @[lsu.scala:658:50] wire _will_fire_sfence_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_sfence_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_sfence_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_store_commit_fast_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_store_commit_fast_0_will_fire_T_4 = 1'h0; // @[lsu.scala:657:52] wire _will_fire_store_commit_fast_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_store_commit_fast_0_will_fire_T_8 = 1'h0; // @[lsu.scala:658:50] wire _will_fire_store_commit_fast_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_store_commit_fast_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_store_commit_fast_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_load_agen_exec_0_will_fire_T_4 = 1'h0; // @[lsu.scala:657:52] wire _will_fire_load_agen_exec_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_load_agen_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_load_agen_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_store_agen_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_store_agen_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_release_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_release_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_release_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_release_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_hella_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_hella_incoming_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_hella_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_hella_wakeup_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_hella_wakeup_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_hella_wakeup_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_store_retry_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_store_retry_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_load_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_load_wakeup_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_store_commit_slow_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_store_commit_slow_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_store_commit_slow_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_store_commit_slow_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _exe_tlb_uop_WIRE_is_rvc = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_0 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_2 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_3 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_0 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_2 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_3 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_4 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_5 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_6 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_7 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_8 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_9 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_issued = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_sfb = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_fence = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_fencei = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_sfence = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_amo = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_eret = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_sys_pc2epc = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_rocc = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_mov = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_edge_inst = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_taken = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_imm_rename = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_wen = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_toint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_fma = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_div = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_vec = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_prs1_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_prs2_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_prs3_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_ppred_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_exception = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_mem_signed = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_uses_ldq = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_uses_stq = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_unique = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_flush_on_commit = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_ldst_is_rs1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_frs3_en = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fcn_dw = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_val = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_xcpt_pf_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_xcpt_ae_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_xcpt_ma_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_bp_debug_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_bp_xcpt_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_1_is_rvc = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_0 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_2 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_3 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_0 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_2 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_3 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_4 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_5 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_6 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_7 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_8 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_9 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_issued = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_issued_partial_agen = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_sfb = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_fence = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_fencei = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_sfence = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_amo = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_eret = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_sys_pc2epc = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_rocc = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_mov = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_edge_inst = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_taken = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_imm_rename = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ldst = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_wen = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_fromint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_toint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_fma = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_div = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_wflags = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_vec = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_prs1_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_prs2_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_prs3_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_ppred_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_exception = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_mem_signed = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_uses_ldq = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_uses_stq = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_unique = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_flush_on_commit = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_ldst_is_rs1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_frs3_en = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fcn_dw = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_val = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_xcpt_pf_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_xcpt_ae_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_xcpt_ma_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_bp_debug_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_bp_xcpt_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_T_2_is_rvc = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_0 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_2 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_3 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_0 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_2 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_3 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_4 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_5 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_6 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_7 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_8 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_9 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_issued = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_issued_partial_agen = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_sfb = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_fence = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_fencei = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_sfence = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_amo = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_eret = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_sys_pc2epc = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_rocc = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_mov = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_edge_inst = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_taken = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_imm_rename = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ldst = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_wen = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_fromint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_toint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_fma = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_div = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_wflags = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_vec = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_prs1_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_prs2_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_prs3_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_ppred_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_exception = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_mem_signed = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_uses_ldq = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_uses_stq = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_unique = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_flush_on_commit = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_ldst_is_rs1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_frs3_en = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fcn_dw = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_val = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_xcpt_pf_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_xcpt_ae_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_xcpt_ma_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_bp_debug_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_bp_xcpt_if = 1'h0; // @[lsu.scala:722:24] wire _dbg_bp_T = 1'h0; // @[lsu.scala:788:80] wire _dbg_bp_T_1 = 1'h0; // @[lsu.scala:789:80] wire _dbg_bp_T_3 = 1'h0; // @[lsu.scala:789:104] wire _dbg_bp_T_4 = 1'h0; // @[lsu.scala:788:105] wire _dbg_bp_T_5 = 1'h0; // @[lsu.scala:788:51] wire dbg_bp_0 = 1'h0; // @[lsu.scala:321:49] wire _bp_T = 1'h0; // @[lsu.scala:790:80] wire _bp_T_1 = 1'h0; // @[lsu.scala:791:80] wire _bp_T_3 = 1'h0; // @[lsu.scala:791:103] wire _bp_T_4 = 1'h0; // @[lsu.scala:790:104] wire _bp_T_5 = 1'h0; // @[lsu.scala:790:51] wire bp_0 = 1'h0; // @[lsu.scala:321:49] wire _exe_tlb_miss_T = 1'h0; // @[lsu.scala:835:86] wire _s0_executing_loads_WIRE_0 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_1 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_2 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_3 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_4 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_5 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_6 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_7 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_8 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_9 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_10 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_11 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_12 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_13 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_14 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_15 = 1'h0; // @[lsu.scala:882:44] wire _dmem_req_0_bits_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_data_T_15 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_20 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_24 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_30 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_35 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_39 = 1'h0; // @[AMOALU.scala:29:19] wire _mem_ldq_e_WIRE_valid = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_0 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_2 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_3 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_0 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_2 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_3 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_4 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_5 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_6 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_7 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_8 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_9 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_issued = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_issued_partial_agen = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_sfence = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_eret = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_rocc = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_mov = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_imm_rename = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ldst = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_wen = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_fromint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_toint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_fma = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_div = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_wflags = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_vec = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fcn_dw = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_addr_is_uncacheable = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_executed = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_order_fail = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_observed = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_forward_std_val = 1'h0; // @[lsu.scala:1064:73] wire _mem_stq_e_WIRE_valid = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_0 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_2 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_3 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_0 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_2 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_3 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_4 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_5 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_6 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_7 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_8 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_9 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_issued = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_issued_partial_agen = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_sfence = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_eret = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_rocc = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_mov = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_imm_rename = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ldst = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_wen = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_fromint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_toint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_fma = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_div = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_wflags = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_vec = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fcn_dw = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_data_valid = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_committed = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_can_execute = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_cleared = 1'h0; // @[lsu.scala:1067:87] wire _lcam_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57] wire _kill_forward_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire _ld_xcpt_uop_T = 1'h0; // @[lsu.scala:1438:50] wire iresp_0_bits_predicated = 1'h0; // @[lsu.scala:1477:19] wire iresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:1477:19] wire fresp_0_bits_predicated = 1'h0; // @[lsu.scala:1478:19] wire fresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:1478:19] wire io_core_iresp_0_out_bits_predicated = 1'h0; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_fflags_valid = 1'h0; // @[util.scala:114:23] wire wb_spec_wakeups_0_bits_rebusy = 1'h0; // @[lsu.scala:1491:29] wire wb_slow_wakeups_0_bits_bypassable = 1'h0; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_rebusy = 1'h0; // @[lsu.scala:1494:29] wire slow_wakeups_0_bits_bypassable = 1'h0; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_rebusy = 1'h0; // @[lsu.scala:1495:26] wire _dmem_resp_fired_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire w1_bits_out_rebusy = 1'h0; // @[util.scala:109:23] wire w2_bits_out_rebusy = 1'h0; // @[util.scala:109:23] wire iresp_0_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire iresp_0_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire iresp_0_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire fresp_0_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire fresp_0_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire fresp_0_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_debug_wb_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire ldq_debug_wb_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_debug_wb_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire slow_wakeups_0_out_bits_bypassable = 1'h0; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_rebusy = 1'h0; // @[util.scala:114:23] wire _io_hellacache_s2_xcpt_WIRE_ma_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_ma_st = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_pf_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_pf_st = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_gf_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_gf_st = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_ae_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_ae_st = 1'h0; // @[lsu.scala:1797:44] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_core_status_zero1 = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_hellacache_req_bits_mask = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_hellacache_s1_data_mask = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_hellacache_resp_bits_mask = 8'h0; // @[lsu.scala:211:7] wire [7:0] _dmem_req_0_bits_data_T_16 = 8'h0; // @[AMOALU.scala:29:69] wire [7:0] _mem_ldq_e_WIRE_bits_ld_byte_mask = 8'h0; // @[lsu.scala:1064:73] wire [1:0] io_ptw_status_xs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_core_status_xs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_core_status_vs = 2'h0; // @[lsu.scala:211:7] wire [1:0] _exe_tlb_uop_WIRE_iw_p1_speculative_child = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_iw_p2_speculative_child = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_dis_col_sel = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_op1_sel = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_rxq_idx = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_mem_size = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_dst_rtype = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_lrs1_rtype = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_lrs2_rtype = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_fp_typ = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_1_iw_p1_speculative_child = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_iw_p2_speculative_child = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_dis_col_sel = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_op1_sel = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_rxq_idx = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_mem_size = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_dst_rtype = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_lrs1_rtype = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_lrs2_rtype = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_fp_typ = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_T_2_iw_p1_speculative_child = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_iw_p2_speculative_child = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_dis_col_sel = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_op1_sel = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_rxq_idx = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_mem_size = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_dst_rtype = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_lrs1_rtype = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_lrs2_rtype = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_fp_typ = 2'h0; // @[lsu.scala:722:24] wire [1:0] _dmem_req_0_bits_uop_WIRE_iw_p1_speculative_child = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_iw_p2_speculative_child = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_dis_col_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57] wire [1:0] _mem_ldq_e_WIRE_bits_uop_iw_p1_speculative_child = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_iw_p2_speculative_child = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_dis_col_sel = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_op1_sel = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_fp_typ = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_stq_e_WIRE_bits_uop_iw_p1_speculative_child = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_iw_p2_speculative_child = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_dis_col_sel = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_op1_sel = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_fp_typ = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _lcam_uop_WIRE_iw_p1_speculative_child = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_iw_p2_speculative_child = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_dis_col_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57] wire [1:0] wb_spec_wakeups_0_bits_speculative_mask = 2'h0; // @[lsu.scala:1491:29] wire [1:0] wb_slow_wakeups_0_bits_speculative_mask = 2'h0; // @[lsu.scala:1494:29] wire [1:0] slow_wakeups_0_bits_speculative_mask = 2'h0; // @[lsu.scala:1495:26] wire [1:0] w1_bits_out_speculative_mask = 2'h0; // @[util.scala:109:23] wire [1:0] w2_bits_out_speculative_mask = 2'h0; // @[util.scala:109:23] wire [1:0] slow_wakeups_0_out_bits_speculative_mask = 2'h0; // @[util.scala:114:23] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_hellacache_req_bits_cmd = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_hellacache_resp_bits_cmd = 5'h0; // @[lsu.scala:211:7] wire [4:0] _exe_tlb_uop_WIRE_ftq_idx = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_pimm = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_ppred = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_mem_cmd = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_fcn_op = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_1_ftq_idx = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_pimm = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_ppred = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_mem_cmd = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_fcn_op = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_T_2_ftq_idx = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_pimm = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_ppred = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_mem_cmd = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_fcn_op = 5'h0; // @[lsu.scala:722:24] wire [4:0] _dmem_req_0_bits_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_pimm = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ppred = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_fcn_op = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_stq_e_WIRE_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_pimm = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_ppred = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_fcn_op = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _lcam_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57] wire [4:0] iresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:1477:19] wire [4:0] fresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:1478:19] wire [4:0] io_core_iresp_0_out_bits_fflags_bits = 5'h0; // @[util.scala:114:23] wire [6:0] io_hellacache_req_bits_tag = 7'h0; // @[lsu.scala:211:7] wire [6:0] io_hellacache_resp_bits_tag = 7'h0; // @[lsu.scala:211:7] wire [6:0] _exe_tlb_uop_WIRE_pdst = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_prs1 = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_prs2 = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_prs3 = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_stale_pdst = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_1_pdst = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_prs1 = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_prs2 = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_prs3 = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_stale_pdst = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_T_2_pdst = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_prs1 = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_prs2 = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_prs3 = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_stale_pdst = 7'h0; // @[lsu.scala:722:24] wire [6:0] _dmem_req_0_bits_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _mem_ldq_e_WIRE_bits_uop_pdst = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs1 = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs2 = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs3 = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_stq_e_WIRE_bits_uop_pdst = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs1 = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs2 = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs3 = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _lcam_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57] wire [1:0] io_hellacache_req_bits_size = 2'h3; // @[lsu.scala:211:7] wire [1:0] io_hellacache_resp_bits_size = 2'h3; // @[lsu.scala:211:7] wire [1:0] dmem_req_0_bits_data_size_1 = 2'h3; // @[AMOALU.scala:11:18] wire [1:0] dmem_req_0_bits_data_size_2 = 2'h3; // @[AMOALU.scala:11:18] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_2_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_3_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_req_bits_data = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_s1_data_data = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_resp_bits_store_data = 64'h0; // @[lsu.scala:211:7] wire [63:0] _exe_tlb_uop_WIRE_exc_cause = 64'h0; // @[lsu.scala:722:68] wire [63:0] _exe_tlb_uop_WIRE_1_exc_cause = 64'h0; // @[lsu.scala:723:68] wire [63:0] _exe_tlb_uop_T_2_exc_cause = 64'h0; // @[lsu.scala:722:24] wire [63:0] _dmem_req_0_bits_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57] wire [63:0] _dmem_req_0_bits_data_T_19 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_23 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_26 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_27 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_28 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_29 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _mem_ldq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:1064:73] wire [63:0] _mem_ldq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:1064:73] wire [63:0] _mem_stq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:1067:87] wire [63:0] _mem_stq_e_WIRE_bits_data_bits = 64'h0; // @[lsu.scala:1067:87] wire [63:0] _mem_stq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:1067:87] wire [63:0] _lcam_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57] wire io_hellacache_req_bits_phys = 1'h1; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_has_data = 1'h1; // @[lsu.scala:211:7] wire io_hellacache_clock_enabled = 1'h1; // @[lsu.scala:211:7] wire _ldq_wakeup_idx_temp_vec_T_15 = 1'h1; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_15 = 1'h1; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_15 = 1'h1; // @[util.scala:352:72] wire _will_fire_sfence_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_sfence_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_sfence_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_sfence_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_sfence_0_T_5 = 1'h1; // @[lsu.scala:660:31] wire _will_fire_sfence_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_sfence_0_T_8 = 1'h1; // @[lsu.scala:661:31] wire _will_fire_store_commit_fast_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_store_commit_fast_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_store_commit_fast_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_store_commit_fast_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_store_commit_fast_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_store_commit_fast_0_T_5 = 1'h1; // @[lsu.scala:660:31] wire _will_fire_load_agen_exec_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_load_agen_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_load_agen_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_store_agen_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_store_agen_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_release_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_release_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_release_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_release_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_hella_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_hella_incoming_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_hella_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_hella_wakeup_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_hella_wakeup_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_hella_wakeup_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_store_retry_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_store_retry_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_load_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_load_wakeup_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_store_commit_slow_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_store_commit_slow_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_store_commit_slow_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_store_commit_slow_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _dmem_req_0_valid_T_2 = 1'h1; // @[lsu.scala:937:86] wire _stq_clr_head_idx_temp_vec_T_15 = 1'h1; // @[util.scala:352:72] wire _mem_stld_forward_stq_idx_temp_vec_T_15 = 1'h1; // @[util.scala:352:72] wire _l_idx_temp_vec_T_15 = 1'h1; // @[util.scala:352:72] wire _wakeupArbs_0_io_in_1_valid_T_1 = 1'h1; // @[lsu.scala:1459:40] wire wb_spec_wakeups_0_bits_bypassable = 1'h1; // @[lsu.scala:1491:29] wire w1_bits_out_bypassable = 1'h1; // @[util.scala:109:23] wire w2_bits_out_bypassable = 1'h1; // @[util.scala:109:23] wire [1:0] io_hellacache_req_bits_dprv = 2'h1; // @[lsu.scala:211:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[lsu.scala:211:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[lsu.scala:211:7] wire [3:0] _exe_tlb_uop_WIRE_br_tag = 4'h0; // @[lsu.scala:722:68] wire [3:0] _exe_tlb_uop_WIRE_br_type = 4'h0; // @[lsu.scala:722:68] wire [3:0] _exe_tlb_uop_WIRE_ldq_idx = 4'h0; // @[lsu.scala:722:68] wire [3:0] _exe_tlb_uop_WIRE_stq_idx = 4'h0; // @[lsu.scala:722:68] wire [3:0] _exe_tlb_uop_WIRE_1_br_tag = 4'h0; // @[lsu.scala:723:68] wire [3:0] _exe_tlb_uop_WIRE_1_br_type = 4'h0; // @[lsu.scala:723:68] wire [3:0] _exe_tlb_uop_WIRE_1_ldq_idx = 4'h0; // @[lsu.scala:723:68] wire [3:0] _exe_tlb_uop_WIRE_1_stq_idx = 4'h0; // @[lsu.scala:723:68] wire [3:0] _exe_tlb_uop_T_2_br_tag = 4'h0; // @[lsu.scala:722:24] wire [3:0] _exe_tlb_uop_T_2_br_type = 4'h0; // @[lsu.scala:722:24] wire [3:0] _exe_tlb_uop_T_2_ldq_idx = 4'h0; // @[lsu.scala:722:24] wire [3:0] _exe_tlb_uop_T_2_stq_idx = 4'h0; // @[lsu.scala:722:24] wire [3:0] _dmem_req_0_bits_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57] wire [3:0] _dmem_req_0_bits_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57] wire [3:0] _dmem_req_0_bits_uop_WIRE_ldq_idx = 4'h0; // @[consts.scala:141:57] wire [3:0] _dmem_req_0_bits_uop_WIRE_stq_idx = 4'h0; // @[consts.scala:141:57] wire [3:0] _mem_ldq_e_WIRE_bits_uop_br_tag = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_ldq_e_WIRE_bits_uop_br_type = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_ldq_e_WIRE_bits_uop_ldq_idx = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_ldq_e_WIRE_bits_uop_stq_idx = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_ldq_e_WIRE_bits_forward_stq_idx = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_stq_e_WIRE_bits_uop_br_tag = 4'h0; // @[lsu.scala:1067:87] wire [3:0] _mem_stq_e_WIRE_bits_uop_br_type = 4'h0; // @[lsu.scala:1067:87] wire [3:0] _mem_stq_e_WIRE_bits_uop_ldq_idx = 4'h0; // @[lsu.scala:1067:87] wire [3:0] _mem_stq_e_WIRE_bits_uop_stq_idx = 4'h0; // @[lsu.scala:1067:87] wire [3:0] _lcam_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57] wire [3:0] _lcam_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57] wire [3:0] _lcam_uop_WIRE_ldq_idx = 4'h0; // @[consts.scala:141:57] wire [3:0] _lcam_uop_WIRE_stq_idx = 4'h0; // @[consts.scala:141:57] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[lsu.scala:211:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[lsu.scala:211:7] wire [1:0] io_core_status_sxl = 2'h2; // @[lsu.scala:211:7] wire [1:0] io_core_status_uxl = 2'h2; // @[lsu.scala:211:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[lsu.scala:211:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[lsu.scala:211:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[lsu.scala:211:7] wire [5:0] _exe_tlb_uop_WIRE_pc_lob = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_rob_idx = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_ldst = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_lrs1 = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_lrs2 = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_lrs3 = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_1_pc_lob = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_rob_idx = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_ldst = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_lrs1 = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_lrs2 = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_lrs3 = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_T_2_pc_lob = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_rob_idx = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_ldst = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_lrs1 = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_lrs2 = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_lrs3 = 6'h0; // @[lsu.scala:722:24] wire [5:0] _dmem_req_0_bits_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_rob_idx = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57] wire [5:0] _mem_ldq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_rob_idx = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_stq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_rob_idx = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _lcam_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_rob_idx = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_core_commit_debug_insts_0 = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_core_commit_debug_insts_1 = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_hellacache_s2_paddr = 32'h0; // @[lsu.scala:211:7] wire [31:0] _exe_tlb_uop_WIRE_inst = 32'h0; // @[lsu.scala:722:68] wire [31:0] _exe_tlb_uop_WIRE_debug_inst = 32'h0; // @[lsu.scala:722:68] wire [31:0] _exe_tlb_uop_WIRE_1_inst = 32'h0; // @[lsu.scala:723:68] wire [31:0] _exe_tlb_uop_WIRE_1_debug_inst = 32'h0; // @[lsu.scala:723:68] wire [31:0] _exe_tlb_uop_T_2_inst = 32'h0; // @[lsu.scala:722:24] wire [31:0] _exe_tlb_uop_T_2_debug_inst = 32'h0; // @[lsu.scala:722:24] wire [31:0] _dmem_req_0_bits_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _dmem_req_0_bits_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _dmem_req_0_bits_data_T_18 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_22 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_25 = 32'h0; // @[AMOALU.scala:29:69] wire [31:0] _mem_ldq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:1064:73] wire [31:0] _mem_ldq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:1064:73] wire [31:0] _mem_stq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:1067:87] wire [31:0] _mem_stq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:1067:87] wire [31:0] _lcam_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _lcam_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57] wire [39:0] io_hellacache_s2_gpa = 40'h0; // @[lsu.scala:211:7] wire [39:0] _exe_tlb_uop_WIRE_debug_pc = 40'h0; // @[lsu.scala:722:68] wire [39:0] _exe_tlb_uop_WIRE_1_debug_pc = 40'h0; // @[lsu.scala:723:68] wire [39:0] _exe_tlb_uop_T_2_debug_pc = 40'h0; // @[lsu.scala:722:24] wire [39:0] _dmem_req_0_bits_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57] wire [39:0] _mem_ldq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:1064:73] wire [39:0] _mem_ldq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:1064:73] wire [39:0] _mem_stq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:1067:87] wire [39:0] _mem_stq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:1067:87] wire [39:0] _lcam_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57] wire [7:0] _ldq_ld_byte_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _lcam_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _nack_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _forward_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_26 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_41 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_56 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_71 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_86 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_101 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_116 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_131 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_146 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_161 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_176 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_191 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_206 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_221 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_236 = 8'hFF; // @[Mux.scala:126:16] wire [2:0] _exe_tlb_uop_WIRE_imm_sel = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_op2_sel = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_csr_cmd = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_fp_rm = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_debug_fsrc = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_debug_tsrc = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_1_imm_sel = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_op2_sel = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_csr_cmd = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_fp_rm = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_debug_fsrc = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_debug_tsrc = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_T_2_imm_sel = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_op2_sel = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_csr_cmd = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_fp_rm = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_debug_fsrc = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_debug_tsrc = 3'h0; // @[lsu.scala:722:24] wire [2:0] _dmem_req_0_bits_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _mem_ldq_e_WIRE_bits_uop_imm_sel = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_op2_sel = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_csr_cmd = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_fp_rm = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_debug_fsrc = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_debug_tsrc = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_stq_e_WIRE_bits_uop_imm_sel = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_op2_sel = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_csr_cmd = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_fp_rm = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_debug_fsrc = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_debug_tsrc = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _lcam_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57] wire [19:0] _exe_tlb_uop_WIRE_imm_packed = 20'h0; // @[lsu.scala:722:68] wire [19:0] _exe_tlb_uop_WIRE_1_imm_packed = 20'h0; // @[lsu.scala:723:68] wire [19:0] _exe_tlb_uop_T_2_imm_packed = 20'h0; // @[lsu.scala:722:24] wire [19:0] _dmem_req_0_bits_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57] wire [19:0] _mem_ldq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:1064:73] wire [19:0] _mem_stq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:1067:87] wire [19:0] _lcam_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57] wire [11:0] _exe_tlb_uop_WIRE_br_mask = 12'h0; // @[lsu.scala:722:68] wire [11:0] _exe_tlb_uop_WIRE_1_br_mask = 12'h0; // @[lsu.scala:723:68] wire [11:0] _exe_tlb_uop_T_2_br_mask = 12'h0; // @[lsu.scala:722:24] wire [11:0] _dmem_req_0_bits_uop_WIRE_br_mask = 12'h0; // @[consts.scala:141:57] wire [11:0] _mem_ldq_e_WIRE_bits_uop_br_mask = 12'h0; // @[lsu.scala:1064:73] wire [11:0] _mem_stq_e_WIRE_bits_uop_br_mask = 12'h0; // @[lsu.scala:1067:87] wire [11:0] _lcam_uop_WIRE_br_mask = 12'h0; // @[consts.scala:141:57] wire [1:0] io_hellacache_resp_bits_dprv_0 = io_ptw_status_prv_0; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_dv_0 = io_ptw_status_v_0; // @[lsu.scala:211:7] wire [31:0] mem_incoming_uop_out_inst = io_core_agen_0_bits_uop_inst_0; // @[util.scala:104:23] wire [31:0] mem_incoming_uop_out_debug_inst = io_core_agen_0_bits_uop_debug_inst_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_rvc = io_core_agen_0_bits_uop_is_rvc_0; // @[util.scala:104:23] wire [39:0] mem_incoming_uop_out_debug_pc = io_core_agen_0_bits_uop_debug_pc_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_0 = io_core_agen_0_bits_uop_iq_type_0_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_1 = io_core_agen_0_bits_uop_iq_type_1_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_2 = io_core_agen_0_bits_uop_iq_type_2_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_3 = io_core_agen_0_bits_uop_iq_type_3_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_0 = io_core_agen_0_bits_uop_fu_code_0_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_1 = io_core_agen_0_bits_uop_fu_code_1_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_2 = io_core_agen_0_bits_uop_fu_code_2_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_3 = io_core_agen_0_bits_uop_fu_code_3_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_4 = io_core_agen_0_bits_uop_fu_code_4_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_5 = io_core_agen_0_bits_uop_fu_code_5_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_6 = io_core_agen_0_bits_uop_fu_code_6_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_7 = io_core_agen_0_bits_uop_fu_code_7_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_8 = io_core_agen_0_bits_uop_fu_code_8_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_9 = io_core_agen_0_bits_uop_fu_code_9_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_issued = io_core_agen_0_bits_uop_iw_issued_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_issued_partial_agen = io_core_agen_0_bits_uop_iw_issued_partial_agen_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_issued_partial_dgen = io_core_agen_0_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_iw_p1_speculative_child = io_core_agen_0_bits_uop_iw_p1_speculative_child_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_iw_p2_speculative_child = io_core_agen_0_bits_uop_iw_p2_speculative_child_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_p1_bypass_hint = io_core_agen_0_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_p2_bypass_hint = io_core_agen_0_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_p3_bypass_hint = io_core_agen_0_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_dis_col_sel = io_core_agen_0_bits_uop_dis_col_sel_0; // @[util.scala:104:23] wire [3:0] mem_incoming_uop_out_br_tag = io_core_agen_0_bits_uop_br_tag_0; // @[util.scala:104:23] wire [3:0] mem_incoming_uop_out_br_type = io_core_agen_0_bits_uop_br_type_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_sfb = io_core_agen_0_bits_uop_is_sfb_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_fence = io_core_agen_0_bits_uop_is_fence_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_fencei = io_core_agen_0_bits_uop_is_fencei_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_sfence = io_core_agen_0_bits_uop_is_sfence_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_amo = io_core_agen_0_bits_uop_is_amo_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_eret = io_core_agen_0_bits_uop_is_eret_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_sys_pc2epc = io_core_agen_0_bits_uop_is_sys_pc2epc_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_rocc = io_core_agen_0_bits_uop_is_rocc_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_mov = io_core_agen_0_bits_uop_is_mov_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_ftq_idx = io_core_agen_0_bits_uop_ftq_idx_0; // @[util.scala:104:23] wire mem_incoming_uop_out_edge_inst = io_core_agen_0_bits_uop_edge_inst_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_pc_lob = io_core_agen_0_bits_uop_pc_lob_0; // @[util.scala:104:23] wire mem_incoming_uop_out_taken = io_core_agen_0_bits_uop_taken_0; // @[util.scala:104:23] wire mem_incoming_uop_out_imm_rename = io_core_agen_0_bits_uop_imm_rename_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_imm_sel = io_core_agen_0_bits_uop_imm_sel_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_pimm = io_core_agen_0_bits_uop_pimm_0; // @[util.scala:104:23] wire [19:0] mem_incoming_uop_out_imm_packed = io_core_agen_0_bits_uop_imm_packed_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_op1_sel = io_core_agen_0_bits_uop_op1_sel_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_op2_sel = io_core_agen_0_bits_uop_op2_sel_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ldst = io_core_agen_0_bits_uop_fp_ctrl_ldst_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_wen = io_core_agen_0_bits_uop_fp_ctrl_wen_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ren1 = io_core_agen_0_bits_uop_fp_ctrl_ren1_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ren2 = io_core_agen_0_bits_uop_fp_ctrl_ren2_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ren3 = io_core_agen_0_bits_uop_fp_ctrl_ren3_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_swap12 = io_core_agen_0_bits_uop_fp_ctrl_swap12_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_swap23 = io_core_agen_0_bits_uop_fp_ctrl_swap23_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_fp_ctrl_typeTagIn = io_core_agen_0_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_fp_ctrl_typeTagOut = io_core_agen_0_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_fromint = io_core_agen_0_bits_uop_fp_ctrl_fromint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_toint = io_core_agen_0_bits_uop_fp_ctrl_toint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_fastpipe = io_core_agen_0_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_fma = io_core_agen_0_bits_uop_fp_ctrl_fma_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_div = io_core_agen_0_bits_uop_fp_ctrl_div_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_sqrt = io_core_agen_0_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_wflags = io_core_agen_0_bits_uop_fp_ctrl_wflags_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_vec = io_core_agen_0_bits_uop_fp_ctrl_vec_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_rob_idx = io_core_agen_0_bits_uop_rob_idx_0; // @[util.scala:104:23] wire [3:0] ldq_incoming_idx_0 = io_core_agen_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7, :321:49] wire [3:0] mem_incoming_uop_out_ldq_idx = io_core_agen_0_bits_uop_ldq_idx_0; // @[util.scala:104:23] wire [3:0] stq_incoming_idx_0 = io_core_agen_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7, :321:49] wire [3:0] mem_incoming_uop_out_stq_idx = io_core_agen_0_bits_uop_stq_idx_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_rxq_idx = io_core_agen_0_bits_uop_rxq_idx_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_pdst = io_core_agen_0_bits_uop_pdst_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_prs1 = io_core_agen_0_bits_uop_prs1_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_prs2 = io_core_agen_0_bits_uop_prs2_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_prs3 = io_core_agen_0_bits_uop_prs3_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_ppred = io_core_agen_0_bits_uop_ppred_0; // @[util.scala:104:23] wire mem_incoming_uop_out_prs1_busy = io_core_agen_0_bits_uop_prs1_busy_0; // @[util.scala:104:23] wire mem_incoming_uop_out_prs2_busy = io_core_agen_0_bits_uop_prs2_busy_0; // @[util.scala:104:23] wire mem_incoming_uop_out_prs3_busy = io_core_agen_0_bits_uop_prs3_busy_0; // @[util.scala:104:23] wire mem_incoming_uop_out_ppred_busy = io_core_agen_0_bits_uop_ppred_busy_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_stale_pdst = io_core_agen_0_bits_uop_stale_pdst_0; // @[util.scala:104:23] wire mem_incoming_uop_out_exception = io_core_agen_0_bits_uop_exception_0; // @[util.scala:104:23] wire [63:0] mem_incoming_uop_out_exc_cause = io_core_agen_0_bits_uop_exc_cause_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_mem_cmd = io_core_agen_0_bits_uop_mem_cmd_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_mem_size = io_core_agen_0_bits_uop_mem_size_0; // @[util.scala:104:23] wire mem_incoming_uop_out_mem_signed = io_core_agen_0_bits_uop_mem_signed_0; // @[util.scala:104:23] wire mem_incoming_uop_out_uses_ldq = io_core_agen_0_bits_uop_uses_ldq_0; // @[util.scala:104:23] wire mem_incoming_uop_out_uses_stq = io_core_agen_0_bits_uop_uses_stq_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_unique = io_core_agen_0_bits_uop_is_unique_0; // @[util.scala:104:23] wire mem_incoming_uop_out_flush_on_commit = io_core_agen_0_bits_uop_flush_on_commit_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_csr_cmd = io_core_agen_0_bits_uop_csr_cmd_0; // @[util.scala:104:23] wire mem_incoming_uop_out_ldst_is_rs1 = io_core_agen_0_bits_uop_ldst_is_rs1_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_ldst = io_core_agen_0_bits_uop_ldst_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_lrs1 = io_core_agen_0_bits_uop_lrs1_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_lrs2 = io_core_agen_0_bits_uop_lrs2_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_lrs3 = io_core_agen_0_bits_uop_lrs3_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_dst_rtype = io_core_agen_0_bits_uop_dst_rtype_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_lrs1_rtype = io_core_agen_0_bits_uop_lrs1_rtype_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_lrs2_rtype = io_core_agen_0_bits_uop_lrs2_rtype_0; // @[util.scala:104:23] wire mem_incoming_uop_out_frs3_en = io_core_agen_0_bits_uop_frs3_en_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fcn_dw = io_core_agen_0_bits_uop_fcn_dw_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_fcn_op = io_core_agen_0_bits_uop_fcn_op_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_val = io_core_agen_0_bits_uop_fp_val_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_fp_rm = io_core_agen_0_bits_uop_fp_rm_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_fp_typ = io_core_agen_0_bits_uop_fp_typ_0; // @[util.scala:104:23] wire mem_incoming_uop_out_xcpt_pf_if = io_core_agen_0_bits_uop_xcpt_pf_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_xcpt_ae_if = io_core_agen_0_bits_uop_xcpt_ae_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_xcpt_ma_if = io_core_agen_0_bits_uop_xcpt_ma_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_bp_debug_if = io_core_agen_0_bits_uop_bp_debug_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_bp_xcpt_if = io_core_agen_0_bits_uop_bp_xcpt_if_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_debug_fsrc = io_core_agen_0_bits_uop_debug_fsrc_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_debug_tsrc = io_core_agen_0_bits_uop_debug_tsrc_0; // @[util.scala:104:23] wire fresp_0_valid; // @[lsu.scala:1478:19] wire [31:0] fresp_0_bits_uop_inst; // @[lsu.scala:1478:19] wire [31:0] fresp_0_bits_uop_debug_inst; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_rvc; // @[lsu.scala:1478:19] wire [39:0] fresp_0_bits_uop_debug_pc; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_0; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_1; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_2; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_3; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_0; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_1; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_2; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_3; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_4; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_5; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_6; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_7; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_8; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_9; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_issued; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_dis_col_sel; // @[lsu.scala:1478:19] wire [11:0] fresp_0_bits_uop_br_mask; // @[lsu.scala:1478:19] wire [3:0] fresp_0_bits_uop_br_tag; // @[lsu.scala:1478:19] wire [3:0] fresp_0_bits_uop_br_type; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_sfb; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_fence; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_fencei; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_sfence; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_amo; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_eret; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_rocc; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_mov; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_ftq_idx; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_edge_inst; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_pc_lob; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_taken; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_imm_rename; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_imm_sel; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_pimm; // @[lsu.scala:1478:19] wire [19:0] fresp_0_bits_uop_imm_packed; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_op1_sel; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_op2_sel; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_rob_idx; // @[lsu.scala:1478:19] wire [3:0] fresp_0_bits_uop_ldq_idx; // @[lsu.scala:1478:19] wire [3:0] fresp_0_bits_uop_stq_idx; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_rxq_idx; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_pdst; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_prs1; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_prs2; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_prs3; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_ppred; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_prs1_busy; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_prs2_busy; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_prs3_busy; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_ppred_busy; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_stale_pdst; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_exception; // @[lsu.scala:1478:19] wire [63:0] fresp_0_bits_uop_exc_cause; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_mem_cmd; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_mem_size; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_mem_signed; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_uses_ldq; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_uses_stq; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_unique; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_flush_on_commit; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_csr_cmd; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_ldst; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_lrs1; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_lrs2; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_lrs3; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_dst_rtype; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_lrs1_rtype; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_lrs2_rtype; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_frs3_en; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fcn_dw; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_fcn_op; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_val; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_fp_rm; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_fp_typ; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_bp_debug_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_debug_fsrc; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_debug_tsrc; // @[lsu.scala:1478:19] wire [63:0] fresp_0_bits_data; // @[lsu.scala:1478:19] wire can_fire_sfence_0 = io_core_sfence_valid_0; // @[lsu.scala:211:7, :321:49] wire ldq_full; // @[lsu.scala:369:47] wire ldq_full_1; // @[lsu.scala:369:47] wire stq_full; // @[lsu.scala:373:47] wire stq_full_1; // @[lsu.scala:373:47] wire _io_core_clr_bsy_0_valid_T_4; // @[lsu.scala:1107:45] wire _io_core_clr_bsy_1_valid_T_4; // @[lsu.scala:1107:45] wire _io_core_clr_unsafe_0_valid_T_9; // @[lsu.scala:1423:7] wire [11:0] io_dmem_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask_0; // @[lsu.scala:211:7] wire [11:0] io_dmem_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_0_0 = io_core_brupdate_b2_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_1_0 = io_core_brupdate_b2_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_2_0 = io_core_brupdate_b2_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_3_0 = io_core_brupdate_b2_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_0_0 = io_core_brupdate_b2_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_1_0 = io_core_brupdate_b2_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_2_0 = io_core_brupdate_b2_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_3_0 = io_core_brupdate_b2_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_4_0 = io_core_brupdate_b2_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_5_0 = io_core_brupdate_b2_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_6_0 = io_core_brupdate_b2_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_7_0 = io_core_brupdate_b2_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_8_0 = io_core_brupdate_b2_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_9_0 = io_core_brupdate_b2_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_issued_0 = io_core_brupdate_b2_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_issued_partial_agen_0 = io_core_brupdate_b2_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_core_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_iw_p1_speculative_child_0 = io_core_brupdate_b2_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_iw_p2_speculative_child_0 = io_core_brupdate_b2_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_dis_col_sel_0 = io_core_brupdate_b2_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [11:0] io_dmem_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_brupdate_b2_uop_br_type_0 = io_core_brupdate_b2_uop_br_type_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_sfence_0 = io_core_brupdate_b2_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_eret_0 = io_core_brupdate_b2_uop_is_eret_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_rocc_0 = io_core_brupdate_b2_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_mov_0 = io_core_brupdate_b2_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_imm_rename_0 = io_core_brupdate_b2_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_imm_sel_0 = io_core_brupdate_b2_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_pimm_0 = io_core_brupdate_b2_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_dmem_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_op1_sel_0 = io_core_brupdate_b2_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_op2_sel_0 = io_core_brupdate_b2_uop_op2_sel_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ldst_0 = io_core_brupdate_b2_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_wen_0 = io_core_brupdate_b2_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ren1_0 = io_core_brupdate_b2_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ren2_0 = io_core_brupdate_b2_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ren3_0 = io_core_brupdate_b2_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_swap12_0 = io_core_brupdate_b2_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_swap23_0 = io_core_brupdate_b2_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_fromint_0 = io_core_brupdate_b2_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_toint_0 = io_core_brupdate_b2_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_core_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_fma_0 = io_core_brupdate_b2_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_div_0 = io_core_brupdate_b2_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_core_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_wflags_0 = io_core_brupdate_b2_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_vec_0 = io_core_brupdate_b2_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_dmem_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_csr_cmd_0 = io_core_brupdate_b2_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fcn_dw_0 = io_core_brupdate_b2_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_fcn_op_0 = io_core_brupdate_b2_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_fp_rm_0 = io_core_brupdate_b2_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_fp_typ_0 = io_core_brupdate_b2_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_taken_0 = io_core_brupdate_b2_taken_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target_0; // @[lsu.scala:211:7] wire [20:0] io_dmem_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_rob_pnr_idx_0 = io_core_rob_pnr_idx_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_rob_head_idx_0 = io_core_rob_head_idx_0; // @[lsu.scala:211:7] wire io_dmem_exception_0 = io_core_exception_0; // @[lsu.scala:211:7] wire _io_core_fencei_rdy_T_1; // @[lsu.scala:446:42] wire _io_core_lxcpt_valid_T_4; // @[lsu.scala:1450:39] wire _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire dmem_req_0_valid; // @[lsu.scala:877:22] wire [31:0] dmem_req_0_bits_uop_inst; // @[lsu.scala:877:22] wire [31:0] dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:877:22] wire [39:0] dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_0; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_1; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_2; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_3; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_0; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_1; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_2; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_3; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_4; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_5; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_6; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_7; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_8; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_9; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_issued; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_dis_col_sel; // @[lsu.scala:877:22] wire [11:0] dmem_req_0_bits_uop_br_mask; // @[lsu.scala:877:22] wire [3:0] dmem_req_0_bits_uop_br_tag; // @[lsu.scala:877:22] wire [3:0] dmem_req_0_bits_uop_br_type; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_fence; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_sfence; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_amo; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_eret; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_rocc; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_mov; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_taken; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_imm_rename; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_imm_sel; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_pimm; // @[lsu.scala:877:22] wire [19:0] dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_op1_sel; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_op2_sel; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_div; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:877:22] wire [3:0] dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:877:22] wire [3:0] dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_pdst; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_prs1; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_prs2; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_prs3; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_ppred; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_exception; // @[lsu.scala:877:22] wire [63:0] dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_mem_size; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_unique; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_csr_cmd; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_ldst; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_lrs1; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_lrs2; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_lrs3; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fcn_dw; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_fcn_op; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_val; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_fp_rm; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_fp_typ; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:877:22] wire [39:0] dmem_req_0_bits_addr; // @[lsu.scala:877:22] wire [63:0] dmem_req_0_bits_data; // @[lsu.scala:877:22] wire dmem_req_0_bits_is_hella; // @[lsu.scala:877:22] wire _io_dmem_ll_resp_ready_T_2; // @[lsu.scala:1537:55] wire [63:0] io_hellacache_resp_bits_data_word_bypass_0 = io_dmem_ll_resp_bits_data_0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_resp_bits_data_raw_0 = io_dmem_ll_resp_bits_data_0; // @[lsu.scala:211:7] wire will_fire_release_0; // @[lsu.scala:475:41] wire _can_fire_release_T = io_dmem_release_valid_0; // @[lsu.scala:211:7, :598:66] wire io_core_perf_acquire_0 = io_dmem_perf_acquire_0; // @[lsu.scala:211:7] wire io_core_perf_release_0 = io_dmem_perf_release_0; // @[lsu.scala:211:7] wire _io_hellacache_store_pending_T_14; // @[lsu.scala:1804:52] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[lsu.scala:211:7] wire io_ptw_req_bits_valid_0; // @[lsu.scala:211:7] wire io_ptw_req_valid_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_iwakeups_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_iwakeups_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_iwakeups_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [11:0] io_core_iwakeups_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_iwakeups_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_iwakeups_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_iwakeups_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_iwakeups_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_iwakeups_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_iwakeups_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_bypassable_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_speculative_mask_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_rebusy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_valid_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_iresp_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_iresp_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_iresp_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [11:0] io_core_iresp_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_iresp_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_iresp_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_iresp_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_iresp_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_iresp_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_iresp_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [63:0] io_core_iresp_0_bits_data_0; // @[lsu.scala:211:7] wire io_core_iresp_0_valid_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_fresp_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_fresp_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_fresp_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [11:0] io_core_fresp_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_fresp_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_fresp_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_fresp_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_fresp_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_fresp_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_fresp_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [63:0] io_core_fresp_0_bits_data_0; // @[lsu.scala:211:7] wire io_core_fresp_0_valid_0; // @[lsu.scala:211:7] wire [3:0] io_core_dis_ldq_idx_0_0; // @[lsu.scala:211:7] wire [3:0] io_core_dis_ldq_idx_1_0; // @[lsu.scala:211:7] wire [3:0] io_core_dis_stq_idx_0_0; // @[lsu.scala:211:7] wire [3:0] io_core_dis_stq_idx_1_0; // @[lsu.scala:211:7] wire io_core_ldq_full_0_0; // @[lsu.scala:211:7] wire io_core_ldq_full_1_0; // @[lsu.scala:211:7] wire io_core_stq_full_0_0; // @[lsu.scala:211:7] wire io_core_stq_full_1_0; // @[lsu.scala:211:7] wire io_core_clr_bsy_0_valid_0; // @[lsu.scala:211:7] wire [5:0] io_core_clr_bsy_0_bits_0; // @[lsu.scala:211:7] wire io_core_clr_bsy_1_valid_0; // @[lsu.scala:211:7] wire [5:0] io_core_clr_bsy_1_bits_0; // @[lsu.scala:211:7] wire io_core_clr_unsafe_0_valid_0; // @[lsu.scala:211:7] wire [5:0] io_core_clr_unsafe_0_bits_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_lxcpt_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_lxcpt_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_lxcpt_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [11:0] io_core_lxcpt_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_lxcpt_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_lxcpt_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_lxcpt_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_lxcpt_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_lxcpt_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_lxcpt_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_cause_0; // @[lsu.scala:211:7] wire [39:0] io_core_lxcpt_bits_badvaddr_0; // @[lsu.scala:211:7] wire io_core_lxcpt_valid_0; // @[lsu.scala:211:7] wire io_core_perf_tlbMiss_0; // @[lsu.scala:211:7] wire io_core_fencei_rdy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_req_bits_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_req_bits_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_req_bits_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [11:0] io_dmem_req_bits_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_req_bits_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_req_bits_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_dmem_req_bits_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_req_bits_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_req_bits_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_dmem_req_bits_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_req_bits_0_bits_addr_0; // @[lsu.scala:211:7] wire [63:0] io_dmem_req_bits_0_bits_data_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_is_hella_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_valid_0; // @[lsu.scala:211:7] wire io_dmem_req_valid_0; // @[lsu.scala:211:7] wire io_dmem_s1_kill_0_0; // @[lsu.scala:211:7] wire io_dmem_ll_resp_ready_0; // @[lsu.scala:211:7] wire io_dmem_release_ready_0; // @[lsu.scala:211:7] wire io_dmem_force_order_0; // @[lsu.scala:211:7] wire io_hellacache_req_ready_0; // @[lsu.scala:211:7] wire [39:0] io_hellacache_resp_bits_addr_0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_resp_bits_data_0; // @[lsu.scala:211:7] wire io_hellacache_resp_valid_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ma_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ma_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_pf_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_pf_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_gf_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_gf_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ae_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ae_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_nack_0; // @[lsu.scala:211:7] wire io_hellacache_store_pending_0; // @[lsu.scala:211:7] reg ldq_valid_0; // @[lsu.scala:218:36] reg ldq_valid_1; // @[lsu.scala:218:36] reg ldq_valid_2; // @[lsu.scala:218:36] reg ldq_valid_3; // @[lsu.scala:218:36] reg ldq_valid_4; // @[lsu.scala:218:36] reg ldq_valid_5; // @[lsu.scala:218:36] reg ldq_valid_6; // @[lsu.scala:218:36] reg ldq_valid_7; // @[lsu.scala:218:36] reg ldq_valid_8; // @[lsu.scala:218:36] reg ldq_valid_9; // @[lsu.scala:218:36] reg ldq_valid_10; // @[lsu.scala:218:36] reg ldq_valid_11; // @[lsu.scala:218:36] reg ldq_valid_12; // @[lsu.scala:218:36] reg ldq_valid_13; // @[lsu.scala:218:36] reg ldq_valid_14; // @[lsu.scala:218:36] reg ldq_valid_15; // @[lsu.scala:218:36] reg [31:0] ldq_uop_0_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_inst = ldq_uop_0_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_17_inst = ldq_uop_0_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_0_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_debug_inst = ldq_uop_0_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_17_debug_inst = ldq_uop_0_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_rvc; // @[lsu.scala:219:36] wire l_uop_is_rvc = ldq_uop_0_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_rvc = ldq_uop_0_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_0_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_debug_pc = ldq_uop_0_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_17_debug_pc = ldq_uop_0_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_0; // @[lsu.scala:219:36] wire l_uop_iq_type_0 = ldq_uop_0_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_17_iq_type_0 = ldq_uop_0_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_1; // @[lsu.scala:219:36] wire l_uop_iq_type_1 = ldq_uop_0_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_17_iq_type_1 = ldq_uop_0_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_2; // @[lsu.scala:219:36] wire l_uop_iq_type_2 = ldq_uop_0_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_17_iq_type_2 = ldq_uop_0_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_3; // @[lsu.scala:219:36] wire l_uop_iq_type_3 = ldq_uop_0_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_17_iq_type_3 = ldq_uop_0_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_0; // @[lsu.scala:219:36] wire l_uop_fu_code_0 = ldq_uop_0_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_0 = ldq_uop_0_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_1; // @[lsu.scala:219:36] wire l_uop_fu_code_1 = ldq_uop_0_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_1 = ldq_uop_0_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_2; // @[lsu.scala:219:36] wire l_uop_fu_code_2 = ldq_uop_0_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_2 = ldq_uop_0_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_3; // @[lsu.scala:219:36] wire l_uop_fu_code_3 = ldq_uop_0_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_3 = ldq_uop_0_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_4; // @[lsu.scala:219:36] wire l_uop_fu_code_4 = ldq_uop_0_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_4 = ldq_uop_0_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_5; // @[lsu.scala:219:36] wire l_uop_fu_code_5 = ldq_uop_0_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_5 = ldq_uop_0_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_6; // @[lsu.scala:219:36] wire l_uop_fu_code_6 = ldq_uop_0_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_6 = ldq_uop_0_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_7; // @[lsu.scala:219:36] wire l_uop_fu_code_7 = ldq_uop_0_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_7 = ldq_uop_0_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_8; // @[lsu.scala:219:36] wire l_uop_fu_code_8 = ldq_uop_0_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_8 = ldq_uop_0_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_9; // @[lsu.scala:219:36] wire l_uop_fu_code_9 = ldq_uop_0_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_9 = ldq_uop_0_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_issued; // @[lsu.scala:219:36] wire l_uop_iw_issued = ldq_uop_0_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_17_iw_issued = ldq_uop_0_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_iw_issued_partial_agen = ldq_uop_0_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_17_iw_issued_partial_agen = ldq_uop_0_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_iw_issued_partial_dgen = ldq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_17_iw_issued_partial_dgen = ldq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_iw_p1_speculative_child = ldq_uop_0_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_iw_p1_speculative_child = ldq_uop_0_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_iw_p2_speculative_child = ldq_uop_0_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_iw_p2_speculative_child = ldq_uop_0_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_iw_p1_bypass_hint = ldq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_17_iw_p1_bypass_hint = ldq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_iw_p2_bypass_hint = ldq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_17_iw_p2_bypass_hint = ldq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_iw_p3_bypass_hint = ldq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_17_iw_p3_bypass_hint = ldq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_dis_col_sel = ldq_uop_0_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_dis_col_sel = ldq_uop_0_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_0_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_br_mask = ldq_uop_0_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_17_br_mask = ldq_uop_0_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_0_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_br_tag = ldq_uop_0_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_17_br_tag = ldq_uop_0_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_0_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_br_type = ldq_uop_0_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_17_br_type = ldq_uop_0_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_sfb; // @[lsu.scala:219:36] wire l_uop_is_sfb = ldq_uop_0_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_sfb = ldq_uop_0_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_fence; // @[lsu.scala:219:36] wire l_uop_is_fence = ldq_uop_0_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_fence = ldq_uop_0_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_fencei; // @[lsu.scala:219:36] wire l_uop_is_fencei = ldq_uop_0_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_fencei = ldq_uop_0_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_sfence; // @[lsu.scala:219:36] wire l_uop_is_sfence = ldq_uop_0_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_sfence = ldq_uop_0_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_amo; // @[lsu.scala:219:36] wire l_uop_is_amo = ldq_uop_0_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_amo = ldq_uop_0_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_eret; // @[lsu.scala:219:36] wire l_uop_is_eret = ldq_uop_0_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_eret = ldq_uop_0_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_is_sys_pc2epc = ldq_uop_0_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_sys_pc2epc = ldq_uop_0_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_rocc; // @[lsu.scala:219:36] wire l_uop_is_rocc = ldq_uop_0_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_rocc = ldq_uop_0_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_mov; // @[lsu.scala:219:36] wire l_uop_is_mov = ldq_uop_0_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_mov = ldq_uop_0_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_ftq_idx = ldq_uop_0_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_17_ftq_idx = ldq_uop_0_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_edge_inst; // @[lsu.scala:219:36] wire l_uop_edge_inst = ldq_uop_0_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_17_edge_inst = ldq_uop_0_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_pc_lob = ldq_uop_0_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_17_pc_lob = ldq_uop_0_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_taken; // @[lsu.scala:219:36] wire l_uop_taken = ldq_uop_0_taken; // @[lsu.scala:219:36, :1191:37] wire uop_17_taken = ldq_uop_0_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_imm_rename; // @[lsu.scala:219:36] wire l_uop_imm_rename = ldq_uop_0_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_17_imm_rename = ldq_uop_0_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_imm_sel = ldq_uop_0_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_17_imm_sel = ldq_uop_0_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_pimm = ldq_uop_0_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_17_pimm = ldq_uop_0_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_0_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_imm_packed = ldq_uop_0_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_17_imm_packed = ldq_uop_0_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_op1_sel = ldq_uop_0_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_op1_sel = ldq_uop_0_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_op2_sel = ldq_uop_0_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_17_op2_sel = ldq_uop_0_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ldst = ldq_uop_0_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_ldst = ldq_uop_0_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_wen = ldq_uop_0_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_wen = ldq_uop_0_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ren1 = ldq_uop_0_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_ren1 = ldq_uop_0_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ren2 = ldq_uop_0_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_ren2 = ldq_uop_0_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ren3 = ldq_uop_0_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_ren3 = ldq_uop_0_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_swap12 = ldq_uop_0_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_swap12 = ldq_uop_0_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_swap23 = ldq_uop_0_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_swap23 = ldq_uop_0_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_fp_ctrl_typeTagIn = ldq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_fp_ctrl_typeTagIn = ldq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_fp_ctrl_typeTagOut = ldq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_fp_ctrl_typeTagOut = ldq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_fromint = ldq_uop_0_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_fromint = ldq_uop_0_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_toint = ldq_uop_0_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_toint = ldq_uop_0_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_fastpipe = ldq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_fastpipe = ldq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_fma = ldq_uop_0_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_fma = ldq_uop_0_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_div = ldq_uop_0_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_div = ldq_uop_0_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_sqrt = ldq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_sqrt = ldq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_wflags = ldq_uop_0_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_wflags = ldq_uop_0_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_vec = ldq_uop_0_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_vec = ldq_uop_0_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_rob_idx = ldq_uop_0_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_17_rob_idx = ldq_uop_0_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_0_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_ldq_idx = ldq_uop_0_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_17_ldq_idx = ldq_uop_0_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_0_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_stq_idx = ldq_uop_0_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_17_stq_idx = ldq_uop_0_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_rxq_idx = ldq_uop_0_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_rxq_idx = ldq_uop_0_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_pdst = ldq_uop_0_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_17_pdst = ldq_uop_0_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_prs1 = ldq_uop_0_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_17_prs1 = ldq_uop_0_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_prs2 = ldq_uop_0_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_17_prs2 = ldq_uop_0_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_prs3 = ldq_uop_0_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_17_prs3 = ldq_uop_0_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_ppred = ldq_uop_0_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_17_ppred = ldq_uop_0_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_prs1_busy; // @[lsu.scala:219:36] wire l_uop_prs1_busy = ldq_uop_0_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_17_prs1_busy = ldq_uop_0_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_prs2_busy; // @[lsu.scala:219:36] wire l_uop_prs2_busy = ldq_uop_0_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_17_prs2_busy = ldq_uop_0_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_prs3_busy; // @[lsu.scala:219:36] wire l_uop_prs3_busy = ldq_uop_0_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_17_prs3_busy = ldq_uop_0_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_ppred_busy; // @[lsu.scala:219:36] wire l_uop_ppred_busy = ldq_uop_0_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_17_ppred_busy = ldq_uop_0_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_stale_pdst = ldq_uop_0_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_17_stale_pdst = ldq_uop_0_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_exception; // @[lsu.scala:219:36] wire l_uop_exception = ldq_uop_0_exception; // @[lsu.scala:219:36, :1191:37] wire uop_17_exception = ldq_uop_0_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_0_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_exc_cause = ldq_uop_0_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_17_exc_cause = ldq_uop_0_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_mem_cmd = ldq_uop_0_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_17_mem_cmd = ldq_uop_0_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_mem_size = ldq_uop_0_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_mem_size = ldq_uop_0_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_mem_signed; // @[lsu.scala:219:36] wire l_uop_mem_signed = ldq_uop_0_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_17_mem_signed = ldq_uop_0_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_uses_ldq; // @[lsu.scala:219:36] wire l_uop_uses_ldq = ldq_uop_0_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_17_uses_ldq = ldq_uop_0_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_uses_stq; // @[lsu.scala:219:36] wire l_uop_uses_stq = ldq_uop_0_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_17_uses_stq = ldq_uop_0_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_unique; // @[lsu.scala:219:36] wire l_uop_is_unique = ldq_uop_0_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_unique = ldq_uop_0_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_flush_on_commit = ldq_uop_0_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_17_flush_on_commit = ldq_uop_0_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_csr_cmd = ldq_uop_0_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_17_csr_cmd = ldq_uop_0_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_ldst_is_rs1 = ldq_uop_0_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_17_ldst_is_rs1 = ldq_uop_0_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_ldst = ldq_uop_0_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_17_ldst = ldq_uop_0_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_lrs1 = ldq_uop_0_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_17_lrs1 = ldq_uop_0_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_lrs2 = ldq_uop_0_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_17_lrs2 = ldq_uop_0_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_lrs3 = ldq_uop_0_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_17_lrs3 = ldq_uop_0_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_dst_rtype = ldq_uop_0_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_dst_rtype = ldq_uop_0_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_lrs1_rtype = ldq_uop_0_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_lrs1_rtype = ldq_uop_0_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_lrs2_rtype = ldq_uop_0_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_lrs2_rtype = ldq_uop_0_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_frs3_en; // @[lsu.scala:219:36] wire l_uop_frs3_en = ldq_uop_0_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_17_frs3_en = ldq_uop_0_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fcn_dw; // @[lsu.scala:219:36] wire l_uop_fcn_dw = ldq_uop_0_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_17_fcn_dw = ldq_uop_0_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_fcn_op = ldq_uop_0_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_17_fcn_op = ldq_uop_0_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_val; // @[lsu.scala:219:36] wire l_uop_fp_val = ldq_uop_0_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_val = ldq_uop_0_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_fp_rm = ldq_uop_0_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_17_fp_rm = ldq_uop_0_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_fp_typ = ldq_uop_0_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_fp_typ = ldq_uop_0_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_xcpt_pf_if = ldq_uop_0_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_17_xcpt_pf_if = ldq_uop_0_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_xcpt_ae_if = ldq_uop_0_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_17_xcpt_ae_if = ldq_uop_0_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_xcpt_ma_if = ldq_uop_0_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_17_xcpt_ma_if = ldq_uop_0_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_bp_debug_if = ldq_uop_0_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_17_bp_debug_if = ldq_uop_0_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_bp_xcpt_if = ldq_uop_0_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_17_bp_xcpt_if = ldq_uop_0_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_debug_fsrc = ldq_uop_0_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_17_debug_fsrc = ldq_uop_0_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_debug_tsrc = ldq_uop_0_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_17_debug_tsrc = ldq_uop_0_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_1_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_1_inst = ldq_uop_1_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_18_inst = ldq_uop_1_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_1_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_1_debug_inst = ldq_uop_1_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_18_debug_inst = ldq_uop_1_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_rvc; // @[lsu.scala:219:36] wire l_uop_1_is_rvc = ldq_uop_1_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_rvc = ldq_uop_1_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_1_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_1_debug_pc = ldq_uop_1_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_18_debug_pc = ldq_uop_1_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_0; // @[lsu.scala:219:36] wire l_uop_1_iq_type_0 = ldq_uop_1_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_18_iq_type_0 = ldq_uop_1_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_1; // @[lsu.scala:219:36] wire l_uop_1_iq_type_1 = ldq_uop_1_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_18_iq_type_1 = ldq_uop_1_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_2; // @[lsu.scala:219:36] wire l_uop_1_iq_type_2 = ldq_uop_1_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_18_iq_type_2 = ldq_uop_1_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_3; // @[lsu.scala:219:36] wire l_uop_1_iq_type_3 = ldq_uop_1_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_18_iq_type_3 = ldq_uop_1_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_0; // @[lsu.scala:219:36] wire l_uop_1_fu_code_0 = ldq_uop_1_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_0 = ldq_uop_1_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_1; // @[lsu.scala:219:36] wire l_uop_1_fu_code_1 = ldq_uop_1_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_1 = ldq_uop_1_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_2; // @[lsu.scala:219:36] wire l_uop_1_fu_code_2 = ldq_uop_1_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_2 = ldq_uop_1_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_3; // @[lsu.scala:219:36] wire l_uop_1_fu_code_3 = ldq_uop_1_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_3 = ldq_uop_1_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_4; // @[lsu.scala:219:36] wire l_uop_1_fu_code_4 = ldq_uop_1_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_4 = ldq_uop_1_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_5; // @[lsu.scala:219:36] wire l_uop_1_fu_code_5 = ldq_uop_1_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_5 = ldq_uop_1_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_6; // @[lsu.scala:219:36] wire l_uop_1_fu_code_6 = ldq_uop_1_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_6 = ldq_uop_1_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_7; // @[lsu.scala:219:36] wire l_uop_1_fu_code_7 = ldq_uop_1_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_7 = ldq_uop_1_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_8; // @[lsu.scala:219:36] wire l_uop_1_fu_code_8 = ldq_uop_1_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_8 = ldq_uop_1_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_9; // @[lsu.scala:219:36] wire l_uop_1_fu_code_9 = ldq_uop_1_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_9 = ldq_uop_1_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_issued; // @[lsu.scala:219:36] wire l_uop_1_iw_issued = ldq_uop_1_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_18_iw_issued = ldq_uop_1_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_1_iw_issued_partial_agen = ldq_uop_1_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_18_iw_issued_partial_agen = ldq_uop_1_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_1_iw_issued_partial_dgen = ldq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_18_iw_issued_partial_dgen = ldq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_1_iw_p1_speculative_child = ldq_uop_1_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_iw_p1_speculative_child = ldq_uop_1_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_1_iw_p2_speculative_child = ldq_uop_1_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_iw_p2_speculative_child = ldq_uop_1_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_1_iw_p1_bypass_hint = ldq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_18_iw_p1_bypass_hint = ldq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_1_iw_p2_bypass_hint = ldq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_18_iw_p2_bypass_hint = ldq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_1_iw_p3_bypass_hint = ldq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_18_iw_p3_bypass_hint = ldq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_1_dis_col_sel = ldq_uop_1_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_dis_col_sel = ldq_uop_1_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_1_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_1_br_mask = ldq_uop_1_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_18_br_mask = ldq_uop_1_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_1_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_1_br_tag = ldq_uop_1_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_18_br_tag = ldq_uop_1_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_1_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_1_br_type = ldq_uop_1_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_18_br_type = ldq_uop_1_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_sfb; // @[lsu.scala:219:36] wire l_uop_1_is_sfb = ldq_uop_1_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_sfb = ldq_uop_1_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_fence; // @[lsu.scala:219:36] wire l_uop_1_is_fence = ldq_uop_1_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_fence = ldq_uop_1_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_fencei; // @[lsu.scala:219:36] wire l_uop_1_is_fencei = ldq_uop_1_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_fencei = ldq_uop_1_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_sfence; // @[lsu.scala:219:36] wire l_uop_1_is_sfence = ldq_uop_1_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_sfence = ldq_uop_1_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_amo; // @[lsu.scala:219:36] wire l_uop_1_is_amo = ldq_uop_1_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_amo = ldq_uop_1_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_eret; // @[lsu.scala:219:36] wire l_uop_1_is_eret = ldq_uop_1_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_eret = ldq_uop_1_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_1_is_sys_pc2epc = ldq_uop_1_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_sys_pc2epc = ldq_uop_1_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_rocc; // @[lsu.scala:219:36] wire l_uop_1_is_rocc = ldq_uop_1_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_rocc = ldq_uop_1_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_mov; // @[lsu.scala:219:36] wire l_uop_1_is_mov = ldq_uop_1_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_mov = ldq_uop_1_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_1_ftq_idx = ldq_uop_1_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_18_ftq_idx = ldq_uop_1_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_edge_inst; // @[lsu.scala:219:36] wire l_uop_1_edge_inst = ldq_uop_1_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_18_edge_inst = ldq_uop_1_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_1_pc_lob = ldq_uop_1_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_18_pc_lob = ldq_uop_1_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_taken; // @[lsu.scala:219:36] wire l_uop_1_taken = ldq_uop_1_taken; // @[lsu.scala:219:36, :1191:37] wire uop_18_taken = ldq_uop_1_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_imm_rename; // @[lsu.scala:219:36] wire l_uop_1_imm_rename = ldq_uop_1_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_18_imm_rename = ldq_uop_1_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_1_imm_sel = ldq_uop_1_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_18_imm_sel = ldq_uop_1_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_1_pimm = ldq_uop_1_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_18_pimm = ldq_uop_1_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_1_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_1_imm_packed = ldq_uop_1_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_18_imm_packed = ldq_uop_1_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_1_op1_sel = ldq_uop_1_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_op1_sel = ldq_uop_1_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_1_op2_sel = ldq_uop_1_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_18_op2_sel = ldq_uop_1_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ldst = ldq_uop_1_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_ldst = ldq_uop_1_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_wen = ldq_uop_1_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_wen = ldq_uop_1_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ren1 = ldq_uop_1_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_ren1 = ldq_uop_1_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ren2 = ldq_uop_1_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_ren2 = ldq_uop_1_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ren3 = ldq_uop_1_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_ren3 = ldq_uop_1_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_swap12 = ldq_uop_1_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_swap12 = ldq_uop_1_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_swap23 = ldq_uop_1_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_swap23 = ldq_uop_1_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_1_fp_ctrl_typeTagIn = ldq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_fp_ctrl_typeTagIn = ldq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_1_fp_ctrl_typeTagOut = ldq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_fp_ctrl_typeTagOut = ldq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_fromint = ldq_uop_1_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_fromint = ldq_uop_1_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_toint = ldq_uop_1_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_toint = ldq_uop_1_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_fastpipe = ldq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_fastpipe = ldq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_fma = ldq_uop_1_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_fma = ldq_uop_1_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_div = ldq_uop_1_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_div = ldq_uop_1_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_sqrt = ldq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_sqrt = ldq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_wflags = ldq_uop_1_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_wflags = ldq_uop_1_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_vec = ldq_uop_1_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_vec = ldq_uop_1_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_1_rob_idx = ldq_uop_1_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_18_rob_idx = ldq_uop_1_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_1_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_1_ldq_idx = ldq_uop_1_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_18_ldq_idx = ldq_uop_1_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_1_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_1_stq_idx = ldq_uop_1_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_18_stq_idx = ldq_uop_1_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_1_rxq_idx = ldq_uop_1_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_rxq_idx = ldq_uop_1_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_1_pdst = ldq_uop_1_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_18_pdst = ldq_uop_1_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_1_prs1 = ldq_uop_1_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_18_prs1 = ldq_uop_1_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_1_prs2 = ldq_uop_1_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_18_prs2 = ldq_uop_1_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_1_prs3 = ldq_uop_1_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_18_prs3 = ldq_uop_1_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_1_ppred = ldq_uop_1_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_18_ppred = ldq_uop_1_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_prs1_busy; // @[lsu.scala:219:36] wire l_uop_1_prs1_busy = ldq_uop_1_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_18_prs1_busy = ldq_uop_1_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_prs2_busy; // @[lsu.scala:219:36] wire l_uop_1_prs2_busy = ldq_uop_1_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_18_prs2_busy = ldq_uop_1_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_prs3_busy; // @[lsu.scala:219:36] wire l_uop_1_prs3_busy = ldq_uop_1_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_18_prs3_busy = ldq_uop_1_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_ppred_busy; // @[lsu.scala:219:36] wire l_uop_1_ppred_busy = ldq_uop_1_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_18_ppred_busy = ldq_uop_1_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_1_stale_pdst = ldq_uop_1_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_18_stale_pdst = ldq_uop_1_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_exception; // @[lsu.scala:219:36] wire l_uop_1_exception = ldq_uop_1_exception; // @[lsu.scala:219:36, :1191:37] wire uop_18_exception = ldq_uop_1_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_1_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_1_exc_cause = ldq_uop_1_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_18_exc_cause = ldq_uop_1_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_1_mem_cmd = ldq_uop_1_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_18_mem_cmd = ldq_uop_1_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_1_mem_size = ldq_uop_1_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_mem_size = ldq_uop_1_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_mem_signed; // @[lsu.scala:219:36] wire l_uop_1_mem_signed = ldq_uop_1_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_18_mem_signed = ldq_uop_1_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_uses_ldq; // @[lsu.scala:219:36] wire l_uop_1_uses_ldq = ldq_uop_1_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_18_uses_ldq = ldq_uop_1_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_uses_stq; // @[lsu.scala:219:36] wire l_uop_1_uses_stq = ldq_uop_1_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_18_uses_stq = ldq_uop_1_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_unique; // @[lsu.scala:219:36] wire l_uop_1_is_unique = ldq_uop_1_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_unique = ldq_uop_1_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_1_flush_on_commit = ldq_uop_1_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_18_flush_on_commit = ldq_uop_1_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_1_csr_cmd = ldq_uop_1_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_18_csr_cmd = ldq_uop_1_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_1_ldst_is_rs1 = ldq_uop_1_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_18_ldst_is_rs1 = ldq_uop_1_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_1_ldst = ldq_uop_1_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_18_ldst = ldq_uop_1_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_1_lrs1 = ldq_uop_1_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_18_lrs1 = ldq_uop_1_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_1_lrs2 = ldq_uop_1_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_18_lrs2 = ldq_uop_1_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_1_lrs3 = ldq_uop_1_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_18_lrs3 = ldq_uop_1_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_1_dst_rtype = ldq_uop_1_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_dst_rtype = ldq_uop_1_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_1_lrs1_rtype = ldq_uop_1_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_lrs1_rtype = ldq_uop_1_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_1_lrs2_rtype = ldq_uop_1_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_lrs2_rtype = ldq_uop_1_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_frs3_en; // @[lsu.scala:219:36] wire l_uop_1_frs3_en = ldq_uop_1_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_18_frs3_en = ldq_uop_1_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fcn_dw; // @[lsu.scala:219:36] wire l_uop_1_fcn_dw = ldq_uop_1_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_18_fcn_dw = ldq_uop_1_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_1_fcn_op = ldq_uop_1_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_18_fcn_op = ldq_uop_1_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_val; // @[lsu.scala:219:36] wire l_uop_1_fp_val = ldq_uop_1_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_val = ldq_uop_1_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_1_fp_rm = ldq_uop_1_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_18_fp_rm = ldq_uop_1_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_1_fp_typ = ldq_uop_1_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_fp_typ = ldq_uop_1_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_1_xcpt_pf_if = ldq_uop_1_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_18_xcpt_pf_if = ldq_uop_1_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_1_xcpt_ae_if = ldq_uop_1_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_18_xcpt_ae_if = ldq_uop_1_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_1_xcpt_ma_if = ldq_uop_1_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_18_xcpt_ma_if = ldq_uop_1_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_1_bp_debug_if = ldq_uop_1_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_18_bp_debug_if = ldq_uop_1_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_1_bp_xcpt_if = ldq_uop_1_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_18_bp_xcpt_if = ldq_uop_1_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_1_debug_fsrc = ldq_uop_1_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_18_debug_fsrc = ldq_uop_1_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_1_debug_tsrc = ldq_uop_1_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_18_debug_tsrc = ldq_uop_1_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_2_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_2_inst = ldq_uop_2_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_19_inst = ldq_uop_2_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_2_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_2_debug_inst = ldq_uop_2_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_19_debug_inst = ldq_uop_2_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_rvc; // @[lsu.scala:219:36] wire l_uop_2_is_rvc = ldq_uop_2_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_rvc = ldq_uop_2_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_2_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_2_debug_pc = ldq_uop_2_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_19_debug_pc = ldq_uop_2_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_0; // @[lsu.scala:219:36] wire l_uop_2_iq_type_0 = ldq_uop_2_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_19_iq_type_0 = ldq_uop_2_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_1; // @[lsu.scala:219:36] wire l_uop_2_iq_type_1 = ldq_uop_2_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_19_iq_type_1 = ldq_uop_2_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_2; // @[lsu.scala:219:36] wire l_uop_2_iq_type_2 = ldq_uop_2_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_19_iq_type_2 = ldq_uop_2_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_3; // @[lsu.scala:219:36] wire l_uop_2_iq_type_3 = ldq_uop_2_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_19_iq_type_3 = ldq_uop_2_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_0; // @[lsu.scala:219:36] wire l_uop_2_fu_code_0 = ldq_uop_2_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_0 = ldq_uop_2_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_1; // @[lsu.scala:219:36] wire l_uop_2_fu_code_1 = ldq_uop_2_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_1 = ldq_uop_2_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_2; // @[lsu.scala:219:36] wire l_uop_2_fu_code_2 = ldq_uop_2_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_2 = ldq_uop_2_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_3; // @[lsu.scala:219:36] wire l_uop_2_fu_code_3 = ldq_uop_2_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_3 = ldq_uop_2_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_4; // @[lsu.scala:219:36] wire l_uop_2_fu_code_4 = ldq_uop_2_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_4 = ldq_uop_2_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_5; // @[lsu.scala:219:36] wire l_uop_2_fu_code_5 = ldq_uop_2_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_5 = ldq_uop_2_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_6; // @[lsu.scala:219:36] wire l_uop_2_fu_code_6 = ldq_uop_2_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_6 = ldq_uop_2_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_7; // @[lsu.scala:219:36] wire l_uop_2_fu_code_7 = ldq_uop_2_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_7 = ldq_uop_2_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_8; // @[lsu.scala:219:36] wire l_uop_2_fu_code_8 = ldq_uop_2_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_8 = ldq_uop_2_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_9; // @[lsu.scala:219:36] wire l_uop_2_fu_code_9 = ldq_uop_2_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_9 = ldq_uop_2_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_issued; // @[lsu.scala:219:36] wire l_uop_2_iw_issued = ldq_uop_2_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_19_iw_issued = ldq_uop_2_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_2_iw_issued_partial_agen = ldq_uop_2_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_19_iw_issued_partial_agen = ldq_uop_2_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_2_iw_issued_partial_dgen = ldq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_19_iw_issued_partial_dgen = ldq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_2_iw_p1_speculative_child = ldq_uop_2_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_iw_p1_speculative_child = ldq_uop_2_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_2_iw_p2_speculative_child = ldq_uop_2_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_iw_p2_speculative_child = ldq_uop_2_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_2_iw_p1_bypass_hint = ldq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_19_iw_p1_bypass_hint = ldq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_2_iw_p2_bypass_hint = ldq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_19_iw_p2_bypass_hint = ldq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_2_iw_p3_bypass_hint = ldq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_19_iw_p3_bypass_hint = ldq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_2_dis_col_sel = ldq_uop_2_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_dis_col_sel = ldq_uop_2_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_2_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_2_br_mask = ldq_uop_2_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_19_br_mask = ldq_uop_2_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_2_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_2_br_tag = ldq_uop_2_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_19_br_tag = ldq_uop_2_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_2_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_2_br_type = ldq_uop_2_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_19_br_type = ldq_uop_2_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_sfb; // @[lsu.scala:219:36] wire l_uop_2_is_sfb = ldq_uop_2_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_sfb = ldq_uop_2_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_fence; // @[lsu.scala:219:36] wire l_uop_2_is_fence = ldq_uop_2_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_fence = ldq_uop_2_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_fencei; // @[lsu.scala:219:36] wire l_uop_2_is_fencei = ldq_uop_2_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_fencei = ldq_uop_2_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_sfence; // @[lsu.scala:219:36] wire l_uop_2_is_sfence = ldq_uop_2_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_sfence = ldq_uop_2_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_amo; // @[lsu.scala:219:36] wire l_uop_2_is_amo = ldq_uop_2_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_amo = ldq_uop_2_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_eret; // @[lsu.scala:219:36] wire l_uop_2_is_eret = ldq_uop_2_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_eret = ldq_uop_2_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_2_is_sys_pc2epc = ldq_uop_2_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_sys_pc2epc = ldq_uop_2_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_rocc; // @[lsu.scala:219:36] wire l_uop_2_is_rocc = ldq_uop_2_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_rocc = ldq_uop_2_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_mov; // @[lsu.scala:219:36] wire l_uop_2_is_mov = ldq_uop_2_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_mov = ldq_uop_2_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_2_ftq_idx = ldq_uop_2_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_19_ftq_idx = ldq_uop_2_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_edge_inst; // @[lsu.scala:219:36] wire l_uop_2_edge_inst = ldq_uop_2_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_19_edge_inst = ldq_uop_2_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_2_pc_lob = ldq_uop_2_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_19_pc_lob = ldq_uop_2_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_taken; // @[lsu.scala:219:36] wire l_uop_2_taken = ldq_uop_2_taken; // @[lsu.scala:219:36, :1191:37] wire uop_19_taken = ldq_uop_2_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_imm_rename; // @[lsu.scala:219:36] wire l_uop_2_imm_rename = ldq_uop_2_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_19_imm_rename = ldq_uop_2_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_2_imm_sel = ldq_uop_2_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_19_imm_sel = ldq_uop_2_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_2_pimm = ldq_uop_2_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_19_pimm = ldq_uop_2_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_2_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_2_imm_packed = ldq_uop_2_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_19_imm_packed = ldq_uop_2_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_2_op1_sel = ldq_uop_2_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_op1_sel = ldq_uop_2_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_2_op2_sel = ldq_uop_2_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_19_op2_sel = ldq_uop_2_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ldst = ldq_uop_2_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_ldst = ldq_uop_2_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_wen = ldq_uop_2_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_wen = ldq_uop_2_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ren1 = ldq_uop_2_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_ren1 = ldq_uop_2_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ren2 = ldq_uop_2_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_ren2 = ldq_uop_2_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ren3 = ldq_uop_2_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_ren3 = ldq_uop_2_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_swap12 = ldq_uop_2_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_swap12 = ldq_uop_2_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_swap23 = ldq_uop_2_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_swap23 = ldq_uop_2_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_2_fp_ctrl_typeTagIn = ldq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_fp_ctrl_typeTagIn = ldq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_2_fp_ctrl_typeTagOut = ldq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_fp_ctrl_typeTagOut = ldq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_fromint = ldq_uop_2_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_fromint = ldq_uop_2_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_toint = ldq_uop_2_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_toint = ldq_uop_2_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_fastpipe = ldq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_fastpipe = ldq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_fma = ldq_uop_2_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_fma = ldq_uop_2_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_div = ldq_uop_2_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_div = ldq_uop_2_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_sqrt = ldq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_sqrt = ldq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_wflags = ldq_uop_2_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_wflags = ldq_uop_2_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_vec = ldq_uop_2_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_vec = ldq_uop_2_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_2_rob_idx = ldq_uop_2_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_19_rob_idx = ldq_uop_2_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_2_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_2_ldq_idx = ldq_uop_2_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_19_ldq_idx = ldq_uop_2_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_2_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_2_stq_idx = ldq_uop_2_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_19_stq_idx = ldq_uop_2_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_2_rxq_idx = ldq_uop_2_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_rxq_idx = ldq_uop_2_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_2_pdst = ldq_uop_2_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_19_pdst = ldq_uop_2_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_2_prs1 = ldq_uop_2_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_19_prs1 = ldq_uop_2_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_2_prs2 = ldq_uop_2_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_19_prs2 = ldq_uop_2_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_2_prs3 = ldq_uop_2_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_19_prs3 = ldq_uop_2_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_2_ppred = ldq_uop_2_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_19_ppred = ldq_uop_2_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_prs1_busy; // @[lsu.scala:219:36] wire l_uop_2_prs1_busy = ldq_uop_2_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_19_prs1_busy = ldq_uop_2_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_prs2_busy; // @[lsu.scala:219:36] wire l_uop_2_prs2_busy = ldq_uop_2_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_19_prs2_busy = ldq_uop_2_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_prs3_busy; // @[lsu.scala:219:36] wire l_uop_2_prs3_busy = ldq_uop_2_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_19_prs3_busy = ldq_uop_2_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_ppred_busy; // @[lsu.scala:219:36] wire l_uop_2_ppred_busy = ldq_uop_2_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_19_ppred_busy = ldq_uop_2_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_2_stale_pdst = ldq_uop_2_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_19_stale_pdst = ldq_uop_2_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_exception; // @[lsu.scala:219:36] wire l_uop_2_exception = ldq_uop_2_exception; // @[lsu.scala:219:36, :1191:37] wire uop_19_exception = ldq_uop_2_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_2_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_2_exc_cause = ldq_uop_2_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_19_exc_cause = ldq_uop_2_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_2_mem_cmd = ldq_uop_2_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_19_mem_cmd = ldq_uop_2_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_2_mem_size = ldq_uop_2_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_mem_size = ldq_uop_2_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_mem_signed; // @[lsu.scala:219:36] wire l_uop_2_mem_signed = ldq_uop_2_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_19_mem_signed = ldq_uop_2_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_uses_ldq; // @[lsu.scala:219:36] wire l_uop_2_uses_ldq = ldq_uop_2_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_19_uses_ldq = ldq_uop_2_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_uses_stq; // @[lsu.scala:219:36] wire l_uop_2_uses_stq = ldq_uop_2_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_19_uses_stq = ldq_uop_2_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_unique; // @[lsu.scala:219:36] wire l_uop_2_is_unique = ldq_uop_2_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_unique = ldq_uop_2_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_2_flush_on_commit = ldq_uop_2_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_19_flush_on_commit = ldq_uop_2_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_2_csr_cmd = ldq_uop_2_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_19_csr_cmd = ldq_uop_2_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_2_ldst_is_rs1 = ldq_uop_2_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_19_ldst_is_rs1 = ldq_uop_2_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_2_ldst = ldq_uop_2_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_19_ldst = ldq_uop_2_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_2_lrs1 = ldq_uop_2_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_19_lrs1 = ldq_uop_2_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_2_lrs2 = ldq_uop_2_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_19_lrs2 = ldq_uop_2_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_2_lrs3 = ldq_uop_2_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_19_lrs3 = ldq_uop_2_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_2_dst_rtype = ldq_uop_2_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_dst_rtype = ldq_uop_2_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_2_lrs1_rtype = ldq_uop_2_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_lrs1_rtype = ldq_uop_2_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_2_lrs2_rtype = ldq_uop_2_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_lrs2_rtype = ldq_uop_2_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_frs3_en; // @[lsu.scala:219:36] wire l_uop_2_frs3_en = ldq_uop_2_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_19_frs3_en = ldq_uop_2_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fcn_dw; // @[lsu.scala:219:36] wire l_uop_2_fcn_dw = ldq_uop_2_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_19_fcn_dw = ldq_uop_2_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_2_fcn_op = ldq_uop_2_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_19_fcn_op = ldq_uop_2_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_val; // @[lsu.scala:219:36] wire l_uop_2_fp_val = ldq_uop_2_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_val = ldq_uop_2_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_2_fp_rm = ldq_uop_2_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_19_fp_rm = ldq_uop_2_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_2_fp_typ = ldq_uop_2_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_fp_typ = ldq_uop_2_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_2_xcpt_pf_if = ldq_uop_2_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_19_xcpt_pf_if = ldq_uop_2_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_2_xcpt_ae_if = ldq_uop_2_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_19_xcpt_ae_if = ldq_uop_2_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_2_xcpt_ma_if = ldq_uop_2_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_19_xcpt_ma_if = ldq_uop_2_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_2_bp_debug_if = ldq_uop_2_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_19_bp_debug_if = ldq_uop_2_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_2_bp_xcpt_if = ldq_uop_2_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_19_bp_xcpt_if = ldq_uop_2_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_2_debug_fsrc = ldq_uop_2_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_19_debug_fsrc = ldq_uop_2_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_2_debug_tsrc = ldq_uop_2_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_19_debug_tsrc = ldq_uop_2_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_3_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_3_inst = ldq_uop_3_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_20_inst = ldq_uop_3_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_3_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_3_debug_inst = ldq_uop_3_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_20_debug_inst = ldq_uop_3_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_rvc; // @[lsu.scala:219:36] wire l_uop_3_is_rvc = ldq_uop_3_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_rvc = ldq_uop_3_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_3_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_3_debug_pc = ldq_uop_3_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_20_debug_pc = ldq_uop_3_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_0; // @[lsu.scala:219:36] wire l_uop_3_iq_type_0 = ldq_uop_3_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_20_iq_type_0 = ldq_uop_3_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_1; // @[lsu.scala:219:36] wire l_uop_3_iq_type_1 = ldq_uop_3_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_20_iq_type_1 = ldq_uop_3_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_2; // @[lsu.scala:219:36] wire l_uop_3_iq_type_2 = ldq_uop_3_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_20_iq_type_2 = ldq_uop_3_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_3; // @[lsu.scala:219:36] wire l_uop_3_iq_type_3 = ldq_uop_3_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_20_iq_type_3 = ldq_uop_3_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_0; // @[lsu.scala:219:36] wire l_uop_3_fu_code_0 = ldq_uop_3_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_0 = ldq_uop_3_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_1; // @[lsu.scala:219:36] wire l_uop_3_fu_code_1 = ldq_uop_3_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_1 = ldq_uop_3_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_2; // @[lsu.scala:219:36] wire l_uop_3_fu_code_2 = ldq_uop_3_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_2 = ldq_uop_3_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_3; // @[lsu.scala:219:36] wire l_uop_3_fu_code_3 = ldq_uop_3_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_3 = ldq_uop_3_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_4; // @[lsu.scala:219:36] wire l_uop_3_fu_code_4 = ldq_uop_3_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_4 = ldq_uop_3_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_5; // @[lsu.scala:219:36] wire l_uop_3_fu_code_5 = ldq_uop_3_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_5 = ldq_uop_3_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_6; // @[lsu.scala:219:36] wire l_uop_3_fu_code_6 = ldq_uop_3_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_6 = ldq_uop_3_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_7; // @[lsu.scala:219:36] wire l_uop_3_fu_code_7 = ldq_uop_3_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_7 = ldq_uop_3_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_8; // @[lsu.scala:219:36] wire l_uop_3_fu_code_8 = ldq_uop_3_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_8 = ldq_uop_3_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_9; // @[lsu.scala:219:36] wire l_uop_3_fu_code_9 = ldq_uop_3_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_9 = ldq_uop_3_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_issued; // @[lsu.scala:219:36] wire l_uop_3_iw_issued = ldq_uop_3_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_20_iw_issued = ldq_uop_3_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_3_iw_issued_partial_agen = ldq_uop_3_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_20_iw_issued_partial_agen = ldq_uop_3_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_3_iw_issued_partial_dgen = ldq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_20_iw_issued_partial_dgen = ldq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_3_iw_p1_speculative_child = ldq_uop_3_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_iw_p1_speculative_child = ldq_uop_3_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_3_iw_p2_speculative_child = ldq_uop_3_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_iw_p2_speculative_child = ldq_uop_3_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_3_iw_p1_bypass_hint = ldq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_20_iw_p1_bypass_hint = ldq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_3_iw_p2_bypass_hint = ldq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_20_iw_p2_bypass_hint = ldq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_3_iw_p3_bypass_hint = ldq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_20_iw_p3_bypass_hint = ldq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_3_dis_col_sel = ldq_uop_3_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_dis_col_sel = ldq_uop_3_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_3_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_3_br_mask = ldq_uop_3_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_20_br_mask = ldq_uop_3_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_3_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_3_br_tag = ldq_uop_3_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_20_br_tag = ldq_uop_3_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_3_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_3_br_type = ldq_uop_3_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_20_br_type = ldq_uop_3_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_sfb; // @[lsu.scala:219:36] wire l_uop_3_is_sfb = ldq_uop_3_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_sfb = ldq_uop_3_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_fence; // @[lsu.scala:219:36] wire l_uop_3_is_fence = ldq_uop_3_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_fence = ldq_uop_3_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_fencei; // @[lsu.scala:219:36] wire l_uop_3_is_fencei = ldq_uop_3_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_fencei = ldq_uop_3_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_sfence; // @[lsu.scala:219:36] wire l_uop_3_is_sfence = ldq_uop_3_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_sfence = ldq_uop_3_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_amo; // @[lsu.scala:219:36] wire l_uop_3_is_amo = ldq_uop_3_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_amo = ldq_uop_3_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_eret; // @[lsu.scala:219:36] wire l_uop_3_is_eret = ldq_uop_3_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_eret = ldq_uop_3_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_3_is_sys_pc2epc = ldq_uop_3_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_sys_pc2epc = ldq_uop_3_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_rocc; // @[lsu.scala:219:36] wire l_uop_3_is_rocc = ldq_uop_3_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_rocc = ldq_uop_3_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_mov; // @[lsu.scala:219:36] wire l_uop_3_is_mov = ldq_uop_3_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_mov = ldq_uop_3_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_3_ftq_idx = ldq_uop_3_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_20_ftq_idx = ldq_uop_3_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_edge_inst; // @[lsu.scala:219:36] wire l_uop_3_edge_inst = ldq_uop_3_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_20_edge_inst = ldq_uop_3_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_3_pc_lob = ldq_uop_3_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_20_pc_lob = ldq_uop_3_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_taken; // @[lsu.scala:219:36] wire l_uop_3_taken = ldq_uop_3_taken; // @[lsu.scala:219:36, :1191:37] wire uop_20_taken = ldq_uop_3_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_imm_rename; // @[lsu.scala:219:36] wire l_uop_3_imm_rename = ldq_uop_3_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_20_imm_rename = ldq_uop_3_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_3_imm_sel = ldq_uop_3_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_20_imm_sel = ldq_uop_3_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_3_pimm = ldq_uop_3_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_20_pimm = ldq_uop_3_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_3_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_3_imm_packed = ldq_uop_3_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_20_imm_packed = ldq_uop_3_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_3_op1_sel = ldq_uop_3_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_op1_sel = ldq_uop_3_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_3_op2_sel = ldq_uop_3_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_20_op2_sel = ldq_uop_3_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ldst = ldq_uop_3_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_ldst = ldq_uop_3_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_wen = ldq_uop_3_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_wen = ldq_uop_3_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ren1 = ldq_uop_3_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_ren1 = ldq_uop_3_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ren2 = ldq_uop_3_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_ren2 = ldq_uop_3_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ren3 = ldq_uop_3_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_ren3 = ldq_uop_3_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_swap12 = ldq_uop_3_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_swap12 = ldq_uop_3_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_swap23 = ldq_uop_3_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_swap23 = ldq_uop_3_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_3_fp_ctrl_typeTagIn = ldq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_fp_ctrl_typeTagIn = ldq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_3_fp_ctrl_typeTagOut = ldq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_fp_ctrl_typeTagOut = ldq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_fromint = ldq_uop_3_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_fromint = ldq_uop_3_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_toint = ldq_uop_3_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_toint = ldq_uop_3_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_fastpipe = ldq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_fastpipe = ldq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_fma = ldq_uop_3_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_fma = ldq_uop_3_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_div = ldq_uop_3_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_div = ldq_uop_3_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_sqrt = ldq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_sqrt = ldq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_wflags = ldq_uop_3_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_wflags = ldq_uop_3_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_vec = ldq_uop_3_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_vec = ldq_uop_3_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_3_rob_idx = ldq_uop_3_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_20_rob_idx = ldq_uop_3_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_3_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_3_ldq_idx = ldq_uop_3_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_20_ldq_idx = ldq_uop_3_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_3_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_3_stq_idx = ldq_uop_3_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_20_stq_idx = ldq_uop_3_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_3_rxq_idx = ldq_uop_3_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_rxq_idx = ldq_uop_3_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_3_pdst = ldq_uop_3_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_20_pdst = ldq_uop_3_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_3_prs1 = ldq_uop_3_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_20_prs1 = ldq_uop_3_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_3_prs2 = ldq_uop_3_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_20_prs2 = ldq_uop_3_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_3_prs3 = ldq_uop_3_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_20_prs3 = ldq_uop_3_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_3_ppred = ldq_uop_3_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_20_ppred = ldq_uop_3_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_prs1_busy; // @[lsu.scala:219:36] wire l_uop_3_prs1_busy = ldq_uop_3_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_20_prs1_busy = ldq_uop_3_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_prs2_busy; // @[lsu.scala:219:36] wire l_uop_3_prs2_busy = ldq_uop_3_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_20_prs2_busy = ldq_uop_3_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_prs3_busy; // @[lsu.scala:219:36] wire l_uop_3_prs3_busy = ldq_uop_3_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_20_prs3_busy = ldq_uop_3_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_ppred_busy; // @[lsu.scala:219:36] wire l_uop_3_ppred_busy = ldq_uop_3_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_20_ppred_busy = ldq_uop_3_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_3_stale_pdst = ldq_uop_3_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_20_stale_pdst = ldq_uop_3_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_exception; // @[lsu.scala:219:36] wire l_uop_3_exception = ldq_uop_3_exception; // @[lsu.scala:219:36, :1191:37] wire uop_20_exception = ldq_uop_3_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_3_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_3_exc_cause = ldq_uop_3_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_20_exc_cause = ldq_uop_3_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_3_mem_cmd = ldq_uop_3_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_20_mem_cmd = ldq_uop_3_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_3_mem_size = ldq_uop_3_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_mem_size = ldq_uop_3_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_mem_signed; // @[lsu.scala:219:36] wire l_uop_3_mem_signed = ldq_uop_3_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_20_mem_signed = ldq_uop_3_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_uses_ldq; // @[lsu.scala:219:36] wire l_uop_3_uses_ldq = ldq_uop_3_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_20_uses_ldq = ldq_uop_3_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_uses_stq; // @[lsu.scala:219:36] wire l_uop_3_uses_stq = ldq_uop_3_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_20_uses_stq = ldq_uop_3_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_unique; // @[lsu.scala:219:36] wire l_uop_3_is_unique = ldq_uop_3_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_unique = ldq_uop_3_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_3_flush_on_commit = ldq_uop_3_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_20_flush_on_commit = ldq_uop_3_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_3_csr_cmd = ldq_uop_3_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_20_csr_cmd = ldq_uop_3_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_3_ldst_is_rs1 = ldq_uop_3_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_20_ldst_is_rs1 = ldq_uop_3_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_3_ldst = ldq_uop_3_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_20_ldst = ldq_uop_3_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_3_lrs1 = ldq_uop_3_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_20_lrs1 = ldq_uop_3_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_3_lrs2 = ldq_uop_3_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_20_lrs2 = ldq_uop_3_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_3_lrs3 = ldq_uop_3_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_20_lrs3 = ldq_uop_3_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_3_dst_rtype = ldq_uop_3_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_dst_rtype = ldq_uop_3_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_3_lrs1_rtype = ldq_uop_3_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_lrs1_rtype = ldq_uop_3_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_3_lrs2_rtype = ldq_uop_3_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_lrs2_rtype = ldq_uop_3_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_frs3_en; // @[lsu.scala:219:36] wire l_uop_3_frs3_en = ldq_uop_3_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_20_frs3_en = ldq_uop_3_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fcn_dw; // @[lsu.scala:219:36] wire l_uop_3_fcn_dw = ldq_uop_3_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_20_fcn_dw = ldq_uop_3_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_3_fcn_op = ldq_uop_3_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_20_fcn_op = ldq_uop_3_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_val; // @[lsu.scala:219:36] wire l_uop_3_fp_val = ldq_uop_3_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_val = ldq_uop_3_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_3_fp_rm = ldq_uop_3_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_20_fp_rm = ldq_uop_3_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_3_fp_typ = ldq_uop_3_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_fp_typ = ldq_uop_3_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_3_xcpt_pf_if = ldq_uop_3_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_20_xcpt_pf_if = ldq_uop_3_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_3_xcpt_ae_if = ldq_uop_3_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_20_xcpt_ae_if = ldq_uop_3_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_3_xcpt_ma_if = ldq_uop_3_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_20_xcpt_ma_if = ldq_uop_3_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_3_bp_debug_if = ldq_uop_3_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_20_bp_debug_if = ldq_uop_3_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_3_bp_xcpt_if = ldq_uop_3_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_20_bp_xcpt_if = ldq_uop_3_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_3_debug_fsrc = ldq_uop_3_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_20_debug_fsrc = ldq_uop_3_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_3_debug_tsrc = ldq_uop_3_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_20_debug_tsrc = ldq_uop_3_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_4_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_4_inst = ldq_uop_4_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_21_inst = ldq_uop_4_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_4_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_4_debug_inst = ldq_uop_4_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_21_debug_inst = ldq_uop_4_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_rvc; // @[lsu.scala:219:36] wire l_uop_4_is_rvc = ldq_uop_4_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_rvc = ldq_uop_4_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_4_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_4_debug_pc = ldq_uop_4_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_21_debug_pc = ldq_uop_4_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_0; // @[lsu.scala:219:36] wire l_uop_4_iq_type_0 = ldq_uop_4_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_21_iq_type_0 = ldq_uop_4_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_1; // @[lsu.scala:219:36] wire l_uop_4_iq_type_1 = ldq_uop_4_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_21_iq_type_1 = ldq_uop_4_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_2; // @[lsu.scala:219:36] wire l_uop_4_iq_type_2 = ldq_uop_4_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_21_iq_type_2 = ldq_uop_4_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_3; // @[lsu.scala:219:36] wire l_uop_4_iq_type_3 = ldq_uop_4_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_21_iq_type_3 = ldq_uop_4_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_0; // @[lsu.scala:219:36] wire l_uop_4_fu_code_0 = ldq_uop_4_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_0 = ldq_uop_4_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_1; // @[lsu.scala:219:36] wire l_uop_4_fu_code_1 = ldq_uop_4_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_1 = ldq_uop_4_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_2; // @[lsu.scala:219:36] wire l_uop_4_fu_code_2 = ldq_uop_4_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_2 = ldq_uop_4_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_3; // @[lsu.scala:219:36] wire l_uop_4_fu_code_3 = ldq_uop_4_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_3 = ldq_uop_4_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_4; // @[lsu.scala:219:36] wire l_uop_4_fu_code_4 = ldq_uop_4_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_4 = ldq_uop_4_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_5; // @[lsu.scala:219:36] wire l_uop_4_fu_code_5 = ldq_uop_4_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_5 = ldq_uop_4_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_6; // @[lsu.scala:219:36] wire l_uop_4_fu_code_6 = ldq_uop_4_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_6 = ldq_uop_4_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_7; // @[lsu.scala:219:36] wire l_uop_4_fu_code_7 = ldq_uop_4_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_7 = ldq_uop_4_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_8; // @[lsu.scala:219:36] wire l_uop_4_fu_code_8 = ldq_uop_4_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_8 = ldq_uop_4_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_9; // @[lsu.scala:219:36] wire l_uop_4_fu_code_9 = ldq_uop_4_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_9 = ldq_uop_4_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_issued; // @[lsu.scala:219:36] wire l_uop_4_iw_issued = ldq_uop_4_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_21_iw_issued = ldq_uop_4_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_4_iw_issued_partial_agen = ldq_uop_4_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_21_iw_issued_partial_agen = ldq_uop_4_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_4_iw_issued_partial_dgen = ldq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_21_iw_issued_partial_dgen = ldq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_4_iw_p1_speculative_child = ldq_uop_4_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_iw_p1_speculative_child = ldq_uop_4_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_4_iw_p2_speculative_child = ldq_uop_4_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_iw_p2_speculative_child = ldq_uop_4_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_4_iw_p1_bypass_hint = ldq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_21_iw_p1_bypass_hint = ldq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_4_iw_p2_bypass_hint = ldq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_21_iw_p2_bypass_hint = ldq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_4_iw_p3_bypass_hint = ldq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_21_iw_p3_bypass_hint = ldq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_4_dis_col_sel = ldq_uop_4_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_dis_col_sel = ldq_uop_4_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_4_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_4_br_mask = ldq_uop_4_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_21_br_mask = ldq_uop_4_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_4_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_4_br_tag = ldq_uop_4_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_21_br_tag = ldq_uop_4_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_4_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_4_br_type = ldq_uop_4_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_21_br_type = ldq_uop_4_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_sfb; // @[lsu.scala:219:36] wire l_uop_4_is_sfb = ldq_uop_4_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_sfb = ldq_uop_4_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_fence; // @[lsu.scala:219:36] wire l_uop_4_is_fence = ldq_uop_4_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_fence = ldq_uop_4_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_fencei; // @[lsu.scala:219:36] wire l_uop_4_is_fencei = ldq_uop_4_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_fencei = ldq_uop_4_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_sfence; // @[lsu.scala:219:36] wire l_uop_4_is_sfence = ldq_uop_4_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_sfence = ldq_uop_4_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_amo; // @[lsu.scala:219:36] wire l_uop_4_is_amo = ldq_uop_4_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_amo = ldq_uop_4_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_eret; // @[lsu.scala:219:36] wire l_uop_4_is_eret = ldq_uop_4_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_eret = ldq_uop_4_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_4_is_sys_pc2epc = ldq_uop_4_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_sys_pc2epc = ldq_uop_4_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_rocc; // @[lsu.scala:219:36] wire l_uop_4_is_rocc = ldq_uop_4_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_rocc = ldq_uop_4_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_mov; // @[lsu.scala:219:36] wire l_uop_4_is_mov = ldq_uop_4_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_mov = ldq_uop_4_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_4_ftq_idx = ldq_uop_4_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_21_ftq_idx = ldq_uop_4_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_edge_inst; // @[lsu.scala:219:36] wire l_uop_4_edge_inst = ldq_uop_4_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_21_edge_inst = ldq_uop_4_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_4_pc_lob = ldq_uop_4_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_21_pc_lob = ldq_uop_4_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_taken; // @[lsu.scala:219:36] wire l_uop_4_taken = ldq_uop_4_taken; // @[lsu.scala:219:36, :1191:37] wire uop_21_taken = ldq_uop_4_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_imm_rename; // @[lsu.scala:219:36] wire l_uop_4_imm_rename = ldq_uop_4_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_21_imm_rename = ldq_uop_4_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_4_imm_sel = ldq_uop_4_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_21_imm_sel = ldq_uop_4_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_4_pimm = ldq_uop_4_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_21_pimm = ldq_uop_4_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_4_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_4_imm_packed = ldq_uop_4_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_21_imm_packed = ldq_uop_4_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_4_op1_sel = ldq_uop_4_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_op1_sel = ldq_uop_4_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_4_op2_sel = ldq_uop_4_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_21_op2_sel = ldq_uop_4_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ldst = ldq_uop_4_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_ldst = ldq_uop_4_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_wen = ldq_uop_4_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_wen = ldq_uop_4_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ren1 = ldq_uop_4_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_ren1 = ldq_uop_4_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ren2 = ldq_uop_4_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_ren2 = ldq_uop_4_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ren3 = ldq_uop_4_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_ren3 = ldq_uop_4_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_swap12 = ldq_uop_4_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_swap12 = ldq_uop_4_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_swap23 = ldq_uop_4_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_swap23 = ldq_uop_4_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_4_fp_ctrl_typeTagIn = ldq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_fp_ctrl_typeTagIn = ldq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_4_fp_ctrl_typeTagOut = ldq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_fp_ctrl_typeTagOut = ldq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_fromint = ldq_uop_4_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_fromint = ldq_uop_4_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_toint = ldq_uop_4_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_toint = ldq_uop_4_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_fastpipe = ldq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_fastpipe = ldq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_fma = ldq_uop_4_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_fma = ldq_uop_4_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_div = ldq_uop_4_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_div = ldq_uop_4_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_sqrt = ldq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_sqrt = ldq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_wflags = ldq_uop_4_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_wflags = ldq_uop_4_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_vec = ldq_uop_4_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_vec = ldq_uop_4_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_4_rob_idx = ldq_uop_4_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_21_rob_idx = ldq_uop_4_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_4_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_4_ldq_idx = ldq_uop_4_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_21_ldq_idx = ldq_uop_4_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_4_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_4_stq_idx = ldq_uop_4_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_21_stq_idx = ldq_uop_4_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_4_rxq_idx = ldq_uop_4_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_rxq_idx = ldq_uop_4_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_4_pdst = ldq_uop_4_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_21_pdst = ldq_uop_4_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_4_prs1 = ldq_uop_4_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_21_prs1 = ldq_uop_4_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_4_prs2 = ldq_uop_4_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_21_prs2 = ldq_uop_4_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_4_prs3 = ldq_uop_4_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_21_prs3 = ldq_uop_4_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_4_ppred = ldq_uop_4_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_21_ppred = ldq_uop_4_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_prs1_busy; // @[lsu.scala:219:36] wire l_uop_4_prs1_busy = ldq_uop_4_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_21_prs1_busy = ldq_uop_4_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_prs2_busy; // @[lsu.scala:219:36] wire l_uop_4_prs2_busy = ldq_uop_4_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_21_prs2_busy = ldq_uop_4_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_prs3_busy; // @[lsu.scala:219:36] wire l_uop_4_prs3_busy = ldq_uop_4_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_21_prs3_busy = ldq_uop_4_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_ppred_busy; // @[lsu.scala:219:36] wire l_uop_4_ppred_busy = ldq_uop_4_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_21_ppred_busy = ldq_uop_4_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_4_stale_pdst = ldq_uop_4_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_21_stale_pdst = ldq_uop_4_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_exception; // @[lsu.scala:219:36] wire l_uop_4_exception = ldq_uop_4_exception; // @[lsu.scala:219:36, :1191:37] wire uop_21_exception = ldq_uop_4_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_4_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_4_exc_cause = ldq_uop_4_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_21_exc_cause = ldq_uop_4_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_4_mem_cmd = ldq_uop_4_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_21_mem_cmd = ldq_uop_4_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_4_mem_size = ldq_uop_4_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_mem_size = ldq_uop_4_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_mem_signed; // @[lsu.scala:219:36] wire l_uop_4_mem_signed = ldq_uop_4_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_21_mem_signed = ldq_uop_4_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_uses_ldq; // @[lsu.scala:219:36] wire l_uop_4_uses_ldq = ldq_uop_4_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_21_uses_ldq = ldq_uop_4_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_uses_stq; // @[lsu.scala:219:36] wire l_uop_4_uses_stq = ldq_uop_4_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_21_uses_stq = ldq_uop_4_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_unique; // @[lsu.scala:219:36] wire l_uop_4_is_unique = ldq_uop_4_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_unique = ldq_uop_4_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_4_flush_on_commit = ldq_uop_4_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_21_flush_on_commit = ldq_uop_4_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_4_csr_cmd = ldq_uop_4_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_21_csr_cmd = ldq_uop_4_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_4_ldst_is_rs1 = ldq_uop_4_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_21_ldst_is_rs1 = ldq_uop_4_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_4_ldst = ldq_uop_4_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_21_ldst = ldq_uop_4_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_4_lrs1 = ldq_uop_4_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_21_lrs1 = ldq_uop_4_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_4_lrs2 = ldq_uop_4_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_21_lrs2 = ldq_uop_4_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_4_lrs3 = ldq_uop_4_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_21_lrs3 = ldq_uop_4_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_4_dst_rtype = ldq_uop_4_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_dst_rtype = ldq_uop_4_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_4_lrs1_rtype = ldq_uop_4_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_lrs1_rtype = ldq_uop_4_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_4_lrs2_rtype = ldq_uop_4_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_lrs2_rtype = ldq_uop_4_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_frs3_en; // @[lsu.scala:219:36] wire l_uop_4_frs3_en = ldq_uop_4_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_21_frs3_en = ldq_uop_4_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fcn_dw; // @[lsu.scala:219:36] wire l_uop_4_fcn_dw = ldq_uop_4_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_21_fcn_dw = ldq_uop_4_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_4_fcn_op = ldq_uop_4_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_21_fcn_op = ldq_uop_4_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_val; // @[lsu.scala:219:36] wire l_uop_4_fp_val = ldq_uop_4_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_val = ldq_uop_4_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_4_fp_rm = ldq_uop_4_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_21_fp_rm = ldq_uop_4_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_4_fp_typ = ldq_uop_4_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_fp_typ = ldq_uop_4_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_4_xcpt_pf_if = ldq_uop_4_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_21_xcpt_pf_if = ldq_uop_4_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_4_xcpt_ae_if = ldq_uop_4_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_21_xcpt_ae_if = ldq_uop_4_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_4_xcpt_ma_if = ldq_uop_4_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_21_xcpt_ma_if = ldq_uop_4_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_4_bp_debug_if = ldq_uop_4_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_21_bp_debug_if = ldq_uop_4_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_4_bp_xcpt_if = ldq_uop_4_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_21_bp_xcpt_if = ldq_uop_4_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_4_debug_fsrc = ldq_uop_4_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_21_debug_fsrc = ldq_uop_4_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_4_debug_tsrc = ldq_uop_4_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_21_debug_tsrc = ldq_uop_4_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_5_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_5_inst = ldq_uop_5_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_22_inst = ldq_uop_5_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_5_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_5_debug_inst = ldq_uop_5_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_22_debug_inst = ldq_uop_5_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_rvc; // @[lsu.scala:219:36] wire l_uop_5_is_rvc = ldq_uop_5_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_rvc = ldq_uop_5_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_5_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_5_debug_pc = ldq_uop_5_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_22_debug_pc = ldq_uop_5_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_0; // @[lsu.scala:219:36] wire l_uop_5_iq_type_0 = ldq_uop_5_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_22_iq_type_0 = ldq_uop_5_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_1; // @[lsu.scala:219:36] wire l_uop_5_iq_type_1 = ldq_uop_5_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_22_iq_type_1 = ldq_uop_5_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_2; // @[lsu.scala:219:36] wire l_uop_5_iq_type_2 = ldq_uop_5_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_22_iq_type_2 = ldq_uop_5_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_3; // @[lsu.scala:219:36] wire l_uop_5_iq_type_3 = ldq_uop_5_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_22_iq_type_3 = ldq_uop_5_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_0; // @[lsu.scala:219:36] wire l_uop_5_fu_code_0 = ldq_uop_5_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_0 = ldq_uop_5_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_1; // @[lsu.scala:219:36] wire l_uop_5_fu_code_1 = ldq_uop_5_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_1 = ldq_uop_5_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_2; // @[lsu.scala:219:36] wire l_uop_5_fu_code_2 = ldq_uop_5_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_2 = ldq_uop_5_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_3; // @[lsu.scala:219:36] wire l_uop_5_fu_code_3 = ldq_uop_5_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_3 = ldq_uop_5_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_4; // @[lsu.scala:219:36] wire l_uop_5_fu_code_4 = ldq_uop_5_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_4 = ldq_uop_5_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_5; // @[lsu.scala:219:36] wire l_uop_5_fu_code_5 = ldq_uop_5_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_5 = ldq_uop_5_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_6; // @[lsu.scala:219:36] wire l_uop_5_fu_code_6 = ldq_uop_5_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_6 = ldq_uop_5_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_7; // @[lsu.scala:219:36] wire l_uop_5_fu_code_7 = ldq_uop_5_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_7 = ldq_uop_5_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_8; // @[lsu.scala:219:36] wire l_uop_5_fu_code_8 = ldq_uop_5_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_8 = ldq_uop_5_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_9; // @[lsu.scala:219:36] wire l_uop_5_fu_code_9 = ldq_uop_5_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_9 = ldq_uop_5_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_issued; // @[lsu.scala:219:36] wire l_uop_5_iw_issued = ldq_uop_5_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_22_iw_issued = ldq_uop_5_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_5_iw_issued_partial_agen = ldq_uop_5_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_22_iw_issued_partial_agen = ldq_uop_5_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_5_iw_issued_partial_dgen = ldq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_22_iw_issued_partial_dgen = ldq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_5_iw_p1_speculative_child = ldq_uop_5_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_iw_p1_speculative_child = ldq_uop_5_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_5_iw_p2_speculative_child = ldq_uop_5_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_iw_p2_speculative_child = ldq_uop_5_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_5_iw_p1_bypass_hint = ldq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_22_iw_p1_bypass_hint = ldq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_5_iw_p2_bypass_hint = ldq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_22_iw_p2_bypass_hint = ldq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_5_iw_p3_bypass_hint = ldq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_22_iw_p3_bypass_hint = ldq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_5_dis_col_sel = ldq_uop_5_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_dis_col_sel = ldq_uop_5_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_5_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_5_br_mask = ldq_uop_5_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_22_br_mask = ldq_uop_5_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_5_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_5_br_tag = ldq_uop_5_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_22_br_tag = ldq_uop_5_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_5_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_5_br_type = ldq_uop_5_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_22_br_type = ldq_uop_5_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_sfb; // @[lsu.scala:219:36] wire l_uop_5_is_sfb = ldq_uop_5_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_sfb = ldq_uop_5_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_fence; // @[lsu.scala:219:36] wire l_uop_5_is_fence = ldq_uop_5_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_fence = ldq_uop_5_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_fencei; // @[lsu.scala:219:36] wire l_uop_5_is_fencei = ldq_uop_5_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_fencei = ldq_uop_5_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_sfence; // @[lsu.scala:219:36] wire l_uop_5_is_sfence = ldq_uop_5_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_sfence = ldq_uop_5_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_amo; // @[lsu.scala:219:36] wire l_uop_5_is_amo = ldq_uop_5_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_amo = ldq_uop_5_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_eret; // @[lsu.scala:219:36] wire l_uop_5_is_eret = ldq_uop_5_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_eret = ldq_uop_5_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_5_is_sys_pc2epc = ldq_uop_5_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_sys_pc2epc = ldq_uop_5_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_rocc; // @[lsu.scala:219:36] wire l_uop_5_is_rocc = ldq_uop_5_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_rocc = ldq_uop_5_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_mov; // @[lsu.scala:219:36] wire l_uop_5_is_mov = ldq_uop_5_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_mov = ldq_uop_5_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_5_ftq_idx = ldq_uop_5_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_22_ftq_idx = ldq_uop_5_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_edge_inst; // @[lsu.scala:219:36] wire l_uop_5_edge_inst = ldq_uop_5_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_22_edge_inst = ldq_uop_5_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_5_pc_lob = ldq_uop_5_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_22_pc_lob = ldq_uop_5_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_taken; // @[lsu.scala:219:36] wire l_uop_5_taken = ldq_uop_5_taken; // @[lsu.scala:219:36, :1191:37] wire uop_22_taken = ldq_uop_5_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_imm_rename; // @[lsu.scala:219:36] wire l_uop_5_imm_rename = ldq_uop_5_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_22_imm_rename = ldq_uop_5_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_5_imm_sel = ldq_uop_5_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_22_imm_sel = ldq_uop_5_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_5_pimm = ldq_uop_5_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_22_pimm = ldq_uop_5_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_5_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_5_imm_packed = ldq_uop_5_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_22_imm_packed = ldq_uop_5_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_5_op1_sel = ldq_uop_5_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_op1_sel = ldq_uop_5_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_5_op2_sel = ldq_uop_5_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_22_op2_sel = ldq_uop_5_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ldst = ldq_uop_5_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_ldst = ldq_uop_5_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_wen = ldq_uop_5_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_wen = ldq_uop_5_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ren1 = ldq_uop_5_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_ren1 = ldq_uop_5_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ren2 = ldq_uop_5_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_ren2 = ldq_uop_5_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ren3 = ldq_uop_5_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_ren3 = ldq_uop_5_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_swap12 = ldq_uop_5_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_swap12 = ldq_uop_5_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_swap23 = ldq_uop_5_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_swap23 = ldq_uop_5_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_5_fp_ctrl_typeTagIn = ldq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_fp_ctrl_typeTagIn = ldq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_5_fp_ctrl_typeTagOut = ldq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_fp_ctrl_typeTagOut = ldq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_fromint = ldq_uop_5_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_fromint = ldq_uop_5_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_toint = ldq_uop_5_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_toint = ldq_uop_5_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_fastpipe = ldq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_fastpipe = ldq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_fma = ldq_uop_5_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_fma = ldq_uop_5_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_div = ldq_uop_5_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_div = ldq_uop_5_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_sqrt = ldq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_sqrt = ldq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_wflags = ldq_uop_5_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_wflags = ldq_uop_5_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_vec = ldq_uop_5_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_vec = ldq_uop_5_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_5_rob_idx = ldq_uop_5_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_22_rob_idx = ldq_uop_5_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_5_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_5_ldq_idx = ldq_uop_5_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_22_ldq_idx = ldq_uop_5_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_5_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_5_stq_idx = ldq_uop_5_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_22_stq_idx = ldq_uop_5_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_5_rxq_idx = ldq_uop_5_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_rxq_idx = ldq_uop_5_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_5_pdst = ldq_uop_5_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_22_pdst = ldq_uop_5_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_5_prs1 = ldq_uop_5_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_22_prs1 = ldq_uop_5_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_5_prs2 = ldq_uop_5_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_22_prs2 = ldq_uop_5_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_5_prs3 = ldq_uop_5_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_22_prs3 = ldq_uop_5_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_5_ppred = ldq_uop_5_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_22_ppred = ldq_uop_5_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_prs1_busy; // @[lsu.scala:219:36] wire l_uop_5_prs1_busy = ldq_uop_5_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_22_prs1_busy = ldq_uop_5_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_prs2_busy; // @[lsu.scala:219:36] wire l_uop_5_prs2_busy = ldq_uop_5_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_22_prs2_busy = ldq_uop_5_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_prs3_busy; // @[lsu.scala:219:36] wire l_uop_5_prs3_busy = ldq_uop_5_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_22_prs3_busy = ldq_uop_5_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_ppred_busy; // @[lsu.scala:219:36] wire l_uop_5_ppred_busy = ldq_uop_5_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_22_ppred_busy = ldq_uop_5_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_5_stale_pdst = ldq_uop_5_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_22_stale_pdst = ldq_uop_5_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_exception; // @[lsu.scala:219:36] wire l_uop_5_exception = ldq_uop_5_exception; // @[lsu.scala:219:36, :1191:37] wire uop_22_exception = ldq_uop_5_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_5_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_5_exc_cause = ldq_uop_5_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_22_exc_cause = ldq_uop_5_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_5_mem_cmd = ldq_uop_5_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_22_mem_cmd = ldq_uop_5_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_5_mem_size = ldq_uop_5_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_mem_size = ldq_uop_5_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_mem_signed; // @[lsu.scala:219:36] wire l_uop_5_mem_signed = ldq_uop_5_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_22_mem_signed = ldq_uop_5_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_uses_ldq; // @[lsu.scala:219:36] wire l_uop_5_uses_ldq = ldq_uop_5_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_22_uses_ldq = ldq_uop_5_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_uses_stq; // @[lsu.scala:219:36] wire l_uop_5_uses_stq = ldq_uop_5_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_22_uses_stq = ldq_uop_5_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_unique; // @[lsu.scala:219:36] wire l_uop_5_is_unique = ldq_uop_5_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_unique = ldq_uop_5_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_5_flush_on_commit = ldq_uop_5_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_22_flush_on_commit = ldq_uop_5_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_5_csr_cmd = ldq_uop_5_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_22_csr_cmd = ldq_uop_5_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_5_ldst_is_rs1 = ldq_uop_5_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_22_ldst_is_rs1 = ldq_uop_5_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_5_ldst = ldq_uop_5_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_22_ldst = ldq_uop_5_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_5_lrs1 = ldq_uop_5_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_22_lrs1 = ldq_uop_5_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_5_lrs2 = ldq_uop_5_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_22_lrs2 = ldq_uop_5_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_5_lrs3 = ldq_uop_5_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_22_lrs3 = ldq_uop_5_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_5_dst_rtype = ldq_uop_5_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_dst_rtype = ldq_uop_5_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_5_lrs1_rtype = ldq_uop_5_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_lrs1_rtype = ldq_uop_5_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_5_lrs2_rtype = ldq_uop_5_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_lrs2_rtype = ldq_uop_5_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_frs3_en; // @[lsu.scala:219:36] wire l_uop_5_frs3_en = ldq_uop_5_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_22_frs3_en = ldq_uop_5_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fcn_dw; // @[lsu.scala:219:36] wire l_uop_5_fcn_dw = ldq_uop_5_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_22_fcn_dw = ldq_uop_5_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_5_fcn_op = ldq_uop_5_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_22_fcn_op = ldq_uop_5_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_val; // @[lsu.scala:219:36] wire l_uop_5_fp_val = ldq_uop_5_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_val = ldq_uop_5_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_5_fp_rm = ldq_uop_5_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_22_fp_rm = ldq_uop_5_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_5_fp_typ = ldq_uop_5_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_fp_typ = ldq_uop_5_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_5_xcpt_pf_if = ldq_uop_5_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_22_xcpt_pf_if = ldq_uop_5_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_5_xcpt_ae_if = ldq_uop_5_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_22_xcpt_ae_if = ldq_uop_5_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_5_xcpt_ma_if = ldq_uop_5_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_22_xcpt_ma_if = ldq_uop_5_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_5_bp_debug_if = ldq_uop_5_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_22_bp_debug_if = ldq_uop_5_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_5_bp_xcpt_if = ldq_uop_5_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_22_bp_xcpt_if = ldq_uop_5_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_5_debug_fsrc = ldq_uop_5_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_22_debug_fsrc = ldq_uop_5_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_5_debug_tsrc = ldq_uop_5_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_22_debug_tsrc = ldq_uop_5_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_6_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_6_inst = ldq_uop_6_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_23_inst = ldq_uop_6_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_6_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_6_debug_inst = ldq_uop_6_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_23_debug_inst = ldq_uop_6_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_rvc; // @[lsu.scala:219:36] wire l_uop_6_is_rvc = ldq_uop_6_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_rvc = ldq_uop_6_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_6_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_6_debug_pc = ldq_uop_6_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_23_debug_pc = ldq_uop_6_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_0; // @[lsu.scala:219:36] wire l_uop_6_iq_type_0 = ldq_uop_6_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_23_iq_type_0 = ldq_uop_6_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_1; // @[lsu.scala:219:36] wire l_uop_6_iq_type_1 = ldq_uop_6_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_23_iq_type_1 = ldq_uop_6_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_2; // @[lsu.scala:219:36] wire l_uop_6_iq_type_2 = ldq_uop_6_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_23_iq_type_2 = ldq_uop_6_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_3; // @[lsu.scala:219:36] wire l_uop_6_iq_type_3 = ldq_uop_6_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_23_iq_type_3 = ldq_uop_6_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_0; // @[lsu.scala:219:36] wire l_uop_6_fu_code_0 = ldq_uop_6_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_0 = ldq_uop_6_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_1; // @[lsu.scala:219:36] wire l_uop_6_fu_code_1 = ldq_uop_6_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_1 = ldq_uop_6_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_2; // @[lsu.scala:219:36] wire l_uop_6_fu_code_2 = ldq_uop_6_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_2 = ldq_uop_6_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_3; // @[lsu.scala:219:36] wire l_uop_6_fu_code_3 = ldq_uop_6_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_3 = ldq_uop_6_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_4; // @[lsu.scala:219:36] wire l_uop_6_fu_code_4 = ldq_uop_6_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_4 = ldq_uop_6_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_5; // @[lsu.scala:219:36] wire l_uop_6_fu_code_5 = ldq_uop_6_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_5 = ldq_uop_6_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_6; // @[lsu.scala:219:36] wire l_uop_6_fu_code_6 = ldq_uop_6_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_6 = ldq_uop_6_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_7; // @[lsu.scala:219:36] wire l_uop_6_fu_code_7 = ldq_uop_6_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_7 = ldq_uop_6_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_8; // @[lsu.scala:219:36] wire l_uop_6_fu_code_8 = ldq_uop_6_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_8 = ldq_uop_6_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_9; // @[lsu.scala:219:36] wire l_uop_6_fu_code_9 = ldq_uop_6_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_9 = ldq_uop_6_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_issued; // @[lsu.scala:219:36] wire l_uop_6_iw_issued = ldq_uop_6_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_23_iw_issued = ldq_uop_6_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_6_iw_issued_partial_agen = ldq_uop_6_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_23_iw_issued_partial_agen = ldq_uop_6_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_6_iw_issued_partial_dgen = ldq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_23_iw_issued_partial_dgen = ldq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_6_iw_p1_speculative_child = ldq_uop_6_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_iw_p1_speculative_child = ldq_uop_6_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_6_iw_p2_speculative_child = ldq_uop_6_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_iw_p2_speculative_child = ldq_uop_6_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_6_iw_p1_bypass_hint = ldq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_23_iw_p1_bypass_hint = ldq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_6_iw_p2_bypass_hint = ldq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_23_iw_p2_bypass_hint = ldq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_6_iw_p3_bypass_hint = ldq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_23_iw_p3_bypass_hint = ldq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_6_dis_col_sel = ldq_uop_6_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_dis_col_sel = ldq_uop_6_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_6_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_6_br_mask = ldq_uop_6_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_23_br_mask = ldq_uop_6_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_6_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_6_br_tag = ldq_uop_6_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_23_br_tag = ldq_uop_6_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_6_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_6_br_type = ldq_uop_6_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_23_br_type = ldq_uop_6_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_sfb; // @[lsu.scala:219:36] wire l_uop_6_is_sfb = ldq_uop_6_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_sfb = ldq_uop_6_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_fence; // @[lsu.scala:219:36] wire l_uop_6_is_fence = ldq_uop_6_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_fence = ldq_uop_6_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_fencei; // @[lsu.scala:219:36] wire l_uop_6_is_fencei = ldq_uop_6_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_fencei = ldq_uop_6_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_sfence; // @[lsu.scala:219:36] wire l_uop_6_is_sfence = ldq_uop_6_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_sfence = ldq_uop_6_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_amo; // @[lsu.scala:219:36] wire l_uop_6_is_amo = ldq_uop_6_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_amo = ldq_uop_6_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_eret; // @[lsu.scala:219:36] wire l_uop_6_is_eret = ldq_uop_6_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_eret = ldq_uop_6_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_6_is_sys_pc2epc = ldq_uop_6_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_sys_pc2epc = ldq_uop_6_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_rocc; // @[lsu.scala:219:36] wire l_uop_6_is_rocc = ldq_uop_6_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_rocc = ldq_uop_6_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_mov; // @[lsu.scala:219:36] wire l_uop_6_is_mov = ldq_uop_6_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_mov = ldq_uop_6_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_6_ftq_idx = ldq_uop_6_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_23_ftq_idx = ldq_uop_6_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_edge_inst; // @[lsu.scala:219:36] wire l_uop_6_edge_inst = ldq_uop_6_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_23_edge_inst = ldq_uop_6_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_6_pc_lob = ldq_uop_6_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_23_pc_lob = ldq_uop_6_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_taken; // @[lsu.scala:219:36] wire l_uop_6_taken = ldq_uop_6_taken; // @[lsu.scala:219:36, :1191:37] wire uop_23_taken = ldq_uop_6_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_imm_rename; // @[lsu.scala:219:36] wire l_uop_6_imm_rename = ldq_uop_6_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_23_imm_rename = ldq_uop_6_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_6_imm_sel = ldq_uop_6_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_23_imm_sel = ldq_uop_6_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_6_pimm = ldq_uop_6_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_23_pimm = ldq_uop_6_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_6_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_6_imm_packed = ldq_uop_6_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_23_imm_packed = ldq_uop_6_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_6_op1_sel = ldq_uop_6_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_op1_sel = ldq_uop_6_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_6_op2_sel = ldq_uop_6_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_23_op2_sel = ldq_uop_6_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ldst = ldq_uop_6_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_ldst = ldq_uop_6_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_wen = ldq_uop_6_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_wen = ldq_uop_6_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ren1 = ldq_uop_6_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_ren1 = ldq_uop_6_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ren2 = ldq_uop_6_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_ren2 = ldq_uop_6_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ren3 = ldq_uop_6_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_ren3 = ldq_uop_6_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_swap12 = ldq_uop_6_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_swap12 = ldq_uop_6_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_swap23 = ldq_uop_6_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_swap23 = ldq_uop_6_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_6_fp_ctrl_typeTagIn = ldq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_fp_ctrl_typeTagIn = ldq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_6_fp_ctrl_typeTagOut = ldq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_fp_ctrl_typeTagOut = ldq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_fromint = ldq_uop_6_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_fromint = ldq_uop_6_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_toint = ldq_uop_6_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_toint = ldq_uop_6_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_fastpipe = ldq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_fastpipe = ldq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_fma = ldq_uop_6_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_fma = ldq_uop_6_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_div = ldq_uop_6_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_div = ldq_uop_6_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_sqrt = ldq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_sqrt = ldq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_wflags = ldq_uop_6_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_wflags = ldq_uop_6_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_vec = ldq_uop_6_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_vec = ldq_uop_6_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_6_rob_idx = ldq_uop_6_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_23_rob_idx = ldq_uop_6_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_6_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_6_ldq_idx = ldq_uop_6_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_23_ldq_idx = ldq_uop_6_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_6_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_6_stq_idx = ldq_uop_6_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_23_stq_idx = ldq_uop_6_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_6_rxq_idx = ldq_uop_6_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_rxq_idx = ldq_uop_6_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_6_pdst = ldq_uop_6_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_23_pdst = ldq_uop_6_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_6_prs1 = ldq_uop_6_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_23_prs1 = ldq_uop_6_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_6_prs2 = ldq_uop_6_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_23_prs2 = ldq_uop_6_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_6_prs3 = ldq_uop_6_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_23_prs3 = ldq_uop_6_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_6_ppred = ldq_uop_6_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_23_ppred = ldq_uop_6_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_prs1_busy; // @[lsu.scala:219:36] wire l_uop_6_prs1_busy = ldq_uop_6_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_23_prs1_busy = ldq_uop_6_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_prs2_busy; // @[lsu.scala:219:36] wire l_uop_6_prs2_busy = ldq_uop_6_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_23_prs2_busy = ldq_uop_6_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_prs3_busy; // @[lsu.scala:219:36] wire l_uop_6_prs3_busy = ldq_uop_6_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_23_prs3_busy = ldq_uop_6_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_ppred_busy; // @[lsu.scala:219:36] wire l_uop_6_ppred_busy = ldq_uop_6_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_23_ppred_busy = ldq_uop_6_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_6_stale_pdst = ldq_uop_6_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_23_stale_pdst = ldq_uop_6_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_exception; // @[lsu.scala:219:36] wire l_uop_6_exception = ldq_uop_6_exception; // @[lsu.scala:219:36, :1191:37] wire uop_23_exception = ldq_uop_6_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_6_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_6_exc_cause = ldq_uop_6_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_23_exc_cause = ldq_uop_6_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_6_mem_cmd = ldq_uop_6_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_23_mem_cmd = ldq_uop_6_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_6_mem_size = ldq_uop_6_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_mem_size = ldq_uop_6_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_mem_signed; // @[lsu.scala:219:36] wire l_uop_6_mem_signed = ldq_uop_6_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_23_mem_signed = ldq_uop_6_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_uses_ldq; // @[lsu.scala:219:36] wire l_uop_6_uses_ldq = ldq_uop_6_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_23_uses_ldq = ldq_uop_6_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_uses_stq; // @[lsu.scala:219:36] wire l_uop_6_uses_stq = ldq_uop_6_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_23_uses_stq = ldq_uop_6_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_unique; // @[lsu.scala:219:36] wire l_uop_6_is_unique = ldq_uop_6_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_unique = ldq_uop_6_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_6_flush_on_commit = ldq_uop_6_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_23_flush_on_commit = ldq_uop_6_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_6_csr_cmd = ldq_uop_6_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_23_csr_cmd = ldq_uop_6_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_6_ldst_is_rs1 = ldq_uop_6_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_23_ldst_is_rs1 = ldq_uop_6_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_6_ldst = ldq_uop_6_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_23_ldst = ldq_uop_6_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_6_lrs1 = ldq_uop_6_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_23_lrs1 = ldq_uop_6_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_6_lrs2 = ldq_uop_6_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_23_lrs2 = ldq_uop_6_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_6_lrs3 = ldq_uop_6_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_23_lrs3 = ldq_uop_6_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_6_dst_rtype = ldq_uop_6_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_dst_rtype = ldq_uop_6_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_6_lrs1_rtype = ldq_uop_6_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_lrs1_rtype = ldq_uop_6_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_6_lrs2_rtype = ldq_uop_6_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_lrs2_rtype = ldq_uop_6_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_frs3_en; // @[lsu.scala:219:36] wire l_uop_6_frs3_en = ldq_uop_6_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_23_frs3_en = ldq_uop_6_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fcn_dw; // @[lsu.scala:219:36] wire l_uop_6_fcn_dw = ldq_uop_6_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_23_fcn_dw = ldq_uop_6_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_6_fcn_op = ldq_uop_6_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_23_fcn_op = ldq_uop_6_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_val; // @[lsu.scala:219:36] wire l_uop_6_fp_val = ldq_uop_6_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_val = ldq_uop_6_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_6_fp_rm = ldq_uop_6_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_23_fp_rm = ldq_uop_6_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_6_fp_typ = ldq_uop_6_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_fp_typ = ldq_uop_6_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_6_xcpt_pf_if = ldq_uop_6_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_23_xcpt_pf_if = ldq_uop_6_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_6_xcpt_ae_if = ldq_uop_6_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_23_xcpt_ae_if = ldq_uop_6_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_6_xcpt_ma_if = ldq_uop_6_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_23_xcpt_ma_if = ldq_uop_6_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_6_bp_debug_if = ldq_uop_6_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_23_bp_debug_if = ldq_uop_6_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_6_bp_xcpt_if = ldq_uop_6_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_23_bp_xcpt_if = ldq_uop_6_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_6_debug_fsrc = ldq_uop_6_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_23_debug_fsrc = ldq_uop_6_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_6_debug_tsrc = ldq_uop_6_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_23_debug_tsrc = ldq_uop_6_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_7_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_7_inst = ldq_uop_7_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_24_inst = ldq_uop_7_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_7_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_7_debug_inst = ldq_uop_7_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_24_debug_inst = ldq_uop_7_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_rvc; // @[lsu.scala:219:36] wire l_uop_7_is_rvc = ldq_uop_7_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_rvc = ldq_uop_7_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_7_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_7_debug_pc = ldq_uop_7_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_24_debug_pc = ldq_uop_7_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_0; // @[lsu.scala:219:36] wire l_uop_7_iq_type_0 = ldq_uop_7_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_24_iq_type_0 = ldq_uop_7_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_1; // @[lsu.scala:219:36] wire l_uop_7_iq_type_1 = ldq_uop_7_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_24_iq_type_1 = ldq_uop_7_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_2; // @[lsu.scala:219:36] wire l_uop_7_iq_type_2 = ldq_uop_7_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_24_iq_type_2 = ldq_uop_7_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_3; // @[lsu.scala:219:36] wire l_uop_7_iq_type_3 = ldq_uop_7_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_24_iq_type_3 = ldq_uop_7_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_0; // @[lsu.scala:219:36] wire l_uop_7_fu_code_0 = ldq_uop_7_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_0 = ldq_uop_7_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_1; // @[lsu.scala:219:36] wire l_uop_7_fu_code_1 = ldq_uop_7_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_1 = ldq_uop_7_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_2; // @[lsu.scala:219:36] wire l_uop_7_fu_code_2 = ldq_uop_7_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_2 = ldq_uop_7_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_3; // @[lsu.scala:219:36] wire l_uop_7_fu_code_3 = ldq_uop_7_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_3 = ldq_uop_7_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_4; // @[lsu.scala:219:36] wire l_uop_7_fu_code_4 = ldq_uop_7_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_4 = ldq_uop_7_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_5; // @[lsu.scala:219:36] wire l_uop_7_fu_code_5 = ldq_uop_7_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_5 = ldq_uop_7_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_6; // @[lsu.scala:219:36] wire l_uop_7_fu_code_6 = ldq_uop_7_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_6 = ldq_uop_7_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_7; // @[lsu.scala:219:36] wire l_uop_7_fu_code_7 = ldq_uop_7_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_7 = ldq_uop_7_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_8; // @[lsu.scala:219:36] wire l_uop_7_fu_code_8 = ldq_uop_7_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_8 = ldq_uop_7_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_9; // @[lsu.scala:219:36] wire l_uop_7_fu_code_9 = ldq_uop_7_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_9 = ldq_uop_7_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_issued; // @[lsu.scala:219:36] wire l_uop_7_iw_issued = ldq_uop_7_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_24_iw_issued = ldq_uop_7_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_7_iw_issued_partial_agen = ldq_uop_7_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_24_iw_issued_partial_agen = ldq_uop_7_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_7_iw_issued_partial_dgen = ldq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_24_iw_issued_partial_dgen = ldq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_7_iw_p1_speculative_child = ldq_uop_7_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_iw_p1_speculative_child = ldq_uop_7_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_7_iw_p2_speculative_child = ldq_uop_7_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_iw_p2_speculative_child = ldq_uop_7_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_7_iw_p1_bypass_hint = ldq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_24_iw_p1_bypass_hint = ldq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_7_iw_p2_bypass_hint = ldq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_24_iw_p2_bypass_hint = ldq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_7_iw_p3_bypass_hint = ldq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_24_iw_p3_bypass_hint = ldq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_7_dis_col_sel = ldq_uop_7_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_dis_col_sel = ldq_uop_7_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_7_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_7_br_mask = ldq_uop_7_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_24_br_mask = ldq_uop_7_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_7_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_7_br_tag = ldq_uop_7_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_24_br_tag = ldq_uop_7_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_7_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_7_br_type = ldq_uop_7_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_24_br_type = ldq_uop_7_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_sfb; // @[lsu.scala:219:36] wire l_uop_7_is_sfb = ldq_uop_7_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_sfb = ldq_uop_7_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_fence; // @[lsu.scala:219:36] wire l_uop_7_is_fence = ldq_uop_7_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_fence = ldq_uop_7_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_fencei; // @[lsu.scala:219:36] wire l_uop_7_is_fencei = ldq_uop_7_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_fencei = ldq_uop_7_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_sfence; // @[lsu.scala:219:36] wire l_uop_7_is_sfence = ldq_uop_7_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_sfence = ldq_uop_7_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_amo; // @[lsu.scala:219:36] wire l_uop_7_is_amo = ldq_uop_7_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_amo = ldq_uop_7_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_eret; // @[lsu.scala:219:36] wire l_uop_7_is_eret = ldq_uop_7_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_eret = ldq_uop_7_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_7_is_sys_pc2epc = ldq_uop_7_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_sys_pc2epc = ldq_uop_7_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_rocc; // @[lsu.scala:219:36] wire l_uop_7_is_rocc = ldq_uop_7_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_rocc = ldq_uop_7_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_mov; // @[lsu.scala:219:36] wire l_uop_7_is_mov = ldq_uop_7_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_mov = ldq_uop_7_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_7_ftq_idx = ldq_uop_7_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_24_ftq_idx = ldq_uop_7_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_edge_inst; // @[lsu.scala:219:36] wire l_uop_7_edge_inst = ldq_uop_7_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_24_edge_inst = ldq_uop_7_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_7_pc_lob = ldq_uop_7_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_24_pc_lob = ldq_uop_7_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_taken; // @[lsu.scala:219:36] wire l_uop_7_taken = ldq_uop_7_taken; // @[lsu.scala:219:36, :1191:37] wire uop_24_taken = ldq_uop_7_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_imm_rename; // @[lsu.scala:219:36] wire l_uop_7_imm_rename = ldq_uop_7_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_24_imm_rename = ldq_uop_7_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_7_imm_sel = ldq_uop_7_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_24_imm_sel = ldq_uop_7_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_7_pimm = ldq_uop_7_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_24_pimm = ldq_uop_7_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_7_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_7_imm_packed = ldq_uop_7_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_24_imm_packed = ldq_uop_7_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_7_op1_sel = ldq_uop_7_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_op1_sel = ldq_uop_7_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_7_op2_sel = ldq_uop_7_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_24_op2_sel = ldq_uop_7_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ldst = ldq_uop_7_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_ldst = ldq_uop_7_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_wen = ldq_uop_7_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_wen = ldq_uop_7_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ren1 = ldq_uop_7_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_ren1 = ldq_uop_7_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ren2 = ldq_uop_7_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_ren2 = ldq_uop_7_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ren3 = ldq_uop_7_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_ren3 = ldq_uop_7_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_swap12 = ldq_uop_7_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_swap12 = ldq_uop_7_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_swap23 = ldq_uop_7_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_swap23 = ldq_uop_7_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_7_fp_ctrl_typeTagIn = ldq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_fp_ctrl_typeTagIn = ldq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_7_fp_ctrl_typeTagOut = ldq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_fp_ctrl_typeTagOut = ldq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_fromint = ldq_uop_7_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_fromint = ldq_uop_7_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_toint = ldq_uop_7_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_toint = ldq_uop_7_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_fastpipe = ldq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_fastpipe = ldq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_fma = ldq_uop_7_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_fma = ldq_uop_7_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_div = ldq_uop_7_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_div = ldq_uop_7_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_sqrt = ldq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_sqrt = ldq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_wflags = ldq_uop_7_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_wflags = ldq_uop_7_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_vec = ldq_uop_7_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_vec = ldq_uop_7_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_7_rob_idx = ldq_uop_7_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_24_rob_idx = ldq_uop_7_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_7_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_7_ldq_idx = ldq_uop_7_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_24_ldq_idx = ldq_uop_7_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_7_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_7_stq_idx = ldq_uop_7_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_24_stq_idx = ldq_uop_7_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_7_rxq_idx = ldq_uop_7_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_rxq_idx = ldq_uop_7_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_7_pdst = ldq_uop_7_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_24_pdst = ldq_uop_7_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_7_prs1 = ldq_uop_7_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_24_prs1 = ldq_uop_7_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_7_prs2 = ldq_uop_7_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_24_prs2 = ldq_uop_7_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_7_prs3 = ldq_uop_7_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_24_prs3 = ldq_uop_7_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_7_ppred = ldq_uop_7_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_24_ppred = ldq_uop_7_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_prs1_busy; // @[lsu.scala:219:36] wire l_uop_7_prs1_busy = ldq_uop_7_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_24_prs1_busy = ldq_uop_7_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_prs2_busy; // @[lsu.scala:219:36] wire l_uop_7_prs2_busy = ldq_uop_7_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_24_prs2_busy = ldq_uop_7_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_prs3_busy; // @[lsu.scala:219:36] wire l_uop_7_prs3_busy = ldq_uop_7_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_24_prs3_busy = ldq_uop_7_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_ppred_busy; // @[lsu.scala:219:36] wire l_uop_7_ppred_busy = ldq_uop_7_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_24_ppred_busy = ldq_uop_7_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_7_stale_pdst = ldq_uop_7_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_24_stale_pdst = ldq_uop_7_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_exception; // @[lsu.scala:219:36] wire l_uop_7_exception = ldq_uop_7_exception; // @[lsu.scala:219:36, :1191:37] wire uop_24_exception = ldq_uop_7_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_7_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_7_exc_cause = ldq_uop_7_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_24_exc_cause = ldq_uop_7_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_7_mem_cmd = ldq_uop_7_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_24_mem_cmd = ldq_uop_7_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_7_mem_size = ldq_uop_7_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_mem_size = ldq_uop_7_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_mem_signed; // @[lsu.scala:219:36] wire l_uop_7_mem_signed = ldq_uop_7_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_24_mem_signed = ldq_uop_7_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_uses_ldq; // @[lsu.scala:219:36] wire l_uop_7_uses_ldq = ldq_uop_7_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_24_uses_ldq = ldq_uop_7_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_uses_stq; // @[lsu.scala:219:36] wire l_uop_7_uses_stq = ldq_uop_7_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_24_uses_stq = ldq_uop_7_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_unique; // @[lsu.scala:219:36] wire l_uop_7_is_unique = ldq_uop_7_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_unique = ldq_uop_7_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_7_flush_on_commit = ldq_uop_7_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_24_flush_on_commit = ldq_uop_7_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_7_csr_cmd = ldq_uop_7_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_24_csr_cmd = ldq_uop_7_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_7_ldst_is_rs1 = ldq_uop_7_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_24_ldst_is_rs1 = ldq_uop_7_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_7_ldst = ldq_uop_7_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_24_ldst = ldq_uop_7_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_7_lrs1 = ldq_uop_7_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_24_lrs1 = ldq_uop_7_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_7_lrs2 = ldq_uop_7_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_24_lrs2 = ldq_uop_7_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_7_lrs3 = ldq_uop_7_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_24_lrs3 = ldq_uop_7_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_7_dst_rtype = ldq_uop_7_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_dst_rtype = ldq_uop_7_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_7_lrs1_rtype = ldq_uop_7_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_lrs1_rtype = ldq_uop_7_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_7_lrs2_rtype = ldq_uop_7_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_lrs2_rtype = ldq_uop_7_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_frs3_en; // @[lsu.scala:219:36] wire l_uop_7_frs3_en = ldq_uop_7_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_24_frs3_en = ldq_uop_7_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fcn_dw; // @[lsu.scala:219:36] wire l_uop_7_fcn_dw = ldq_uop_7_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_24_fcn_dw = ldq_uop_7_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_7_fcn_op = ldq_uop_7_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_24_fcn_op = ldq_uop_7_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_val; // @[lsu.scala:219:36] wire l_uop_7_fp_val = ldq_uop_7_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_val = ldq_uop_7_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_7_fp_rm = ldq_uop_7_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_24_fp_rm = ldq_uop_7_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_7_fp_typ = ldq_uop_7_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_fp_typ = ldq_uop_7_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_7_xcpt_pf_if = ldq_uop_7_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_24_xcpt_pf_if = ldq_uop_7_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_7_xcpt_ae_if = ldq_uop_7_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_24_xcpt_ae_if = ldq_uop_7_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_7_xcpt_ma_if = ldq_uop_7_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_24_xcpt_ma_if = ldq_uop_7_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_7_bp_debug_if = ldq_uop_7_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_24_bp_debug_if = ldq_uop_7_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_7_bp_xcpt_if = ldq_uop_7_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_24_bp_xcpt_if = ldq_uop_7_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_7_debug_fsrc = ldq_uop_7_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_24_debug_fsrc = ldq_uop_7_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_7_debug_tsrc = ldq_uop_7_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_24_debug_tsrc = ldq_uop_7_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_8_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_8_inst = ldq_uop_8_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_25_inst = ldq_uop_8_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_8_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_8_debug_inst = ldq_uop_8_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_25_debug_inst = ldq_uop_8_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_rvc; // @[lsu.scala:219:36] wire l_uop_8_is_rvc = ldq_uop_8_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_rvc = ldq_uop_8_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_8_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_8_debug_pc = ldq_uop_8_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_25_debug_pc = ldq_uop_8_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_0; // @[lsu.scala:219:36] wire l_uop_8_iq_type_0 = ldq_uop_8_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_0 = ldq_uop_8_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_1; // @[lsu.scala:219:36] wire l_uop_8_iq_type_1 = ldq_uop_8_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_1 = ldq_uop_8_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_2; // @[lsu.scala:219:36] wire l_uop_8_iq_type_2 = ldq_uop_8_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_2 = ldq_uop_8_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_3; // @[lsu.scala:219:36] wire l_uop_8_iq_type_3 = ldq_uop_8_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_3 = ldq_uop_8_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_0; // @[lsu.scala:219:36] wire l_uop_8_fu_code_0 = ldq_uop_8_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_0 = ldq_uop_8_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_1; // @[lsu.scala:219:36] wire l_uop_8_fu_code_1 = ldq_uop_8_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_1 = ldq_uop_8_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_2; // @[lsu.scala:219:36] wire l_uop_8_fu_code_2 = ldq_uop_8_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_2 = ldq_uop_8_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_3; // @[lsu.scala:219:36] wire l_uop_8_fu_code_3 = ldq_uop_8_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_3 = ldq_uop_8_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_4; // @[lsu.scala:219:36] wire l_uop_8_fu_code_4 = ldq_uop_8_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_4 = ldq_uop_8_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_5; // @[lsu.scala:219:36] wire l_uop_8_fu_code_5 = ldq_uop_8_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_5 = ldq_uop_8_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_6; // @[lsu.scala:219:36] wire l_uop_8_fu_code_6 = ldq_uop_8_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_6 = ldq_uop_8_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_7; // @[lsu.scala:219:36] wire l_uop_8_fu_code_7 = ldq_uop_8_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_7 = ldq_uop_8_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_8; // @[lsu.scala:219:36] wire l_uop_8_fu_code_8 = ldq_uop_8_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_8 = ldq_uop_8_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_9; // @[lsu.scala:219:36] wire l_uop_8_fu_code_9 = ldq_uop_8_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_9 = ldq_uop_8_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_issued; // @[lsu.scala:219:36] wire l_uop_8_iw_issued = ldq_uop_8_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_issued = ldq_uop_8_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_8_iw_issued_partial_agen = ldq_uop_8_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_issued_partial_agen = ldq_uop_8_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_8_iw_issued_partial_dgen = ldq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_issued_partial_dgen = ldq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_8_iw_p1_speculative_child = ldq_uop_8_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_iw_p1_speculative_child = ldq_uop_8_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_8_iw_p2_speculative_child = ldq_uop_8_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_iw_p2_speculative_child = ldq_uop_8_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_8_iw_p1_bypass_hint = ldq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_p1_bypass_hint = ldq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_8_iw_p2_bypass_hint = ldq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_p2_bypass_hint = ldq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_8_iw_p3_bypass_hint = ldq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_p3_bypass_hint = ldq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_8_dis_col_sel = ldq_uop_8_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_dis_col_sel = ldq_uop_8_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_8_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_8_br_mask = ldq_uop_8_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_25_br_mask = ldq_uop_8_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_8_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_8_br_tag = ldq_uop_8_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_25_br_tag = ldq_uop_8_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_8_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_8_br_type = ldq_uop_8_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_25_br_type = ldq_uop_8_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_sfb; // @[lsu.scala:219:36] wire l_uop_8_is_sfb = ldq_uop_8_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_sfb = ldq_uop_8_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_fence; // @[lsu.scala:219:36] wire l_uop_8_is_fence = ldq_uop_8_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_fence = ldq_uop_8_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_fencei; // @[lsu.scala:219:36] wire l_uop_8_is_fencei = ldq_uop_8_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_fencei = ldq_uop_8_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_sfence; // @[lsu.scala:219:36] wire l_uop_8_is_sfence = ldq_uop_8_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_sfence = ldq_uop_8_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_amo; // @[lsu.scala:219:36] wire l_uop_8_is_amo = ldq_uop_8_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_amo = ldq_uop_8_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_eret; // @[lsu.scala:219:36] wire l_uop_8_is_eret = ldq_uop_8_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_eret = ldq_uop_8_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_8_is_sys_pc2epc = ldq_uop_8_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_sys_pc2epc = ldq_uop_8_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_rocc; // @[lsu.scala:219:36] wire l_uop_8_is_rocc = ldq_uop_8_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_rocc = ldq_uop_8_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_mov; // @[lsu.scala:219:36] wire l_uop_8_is_mov = ldq_uop_8_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_mov = ldq_uop_8_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_8_ftq_idx = ldq_uop_8_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_ftq_idx = ldq_uop_8_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_edge_inst; // @[lsu.scala:219:36] wire l_uop_8_edge_inst = ldq_uop_8_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_25_edge_inst = ldq_uop_8_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_8_pc_lob = ldq_uop_8_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_pc_lob = ldq_uop_8_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_taken; // @[lsu.scala:219:36] wire l_uop_8_taken = ldq_uop_8_taken; // @[lsu.scala:219:36, :1191:37] wire uop_25_taken = ldq_uop_8_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_imm_rename; // @[lsu.scala:219:36] wire l_uop_8_imm_rename = ldq_uop_8_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_25_imm_rename = ldq_uop_8_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_8_imm_sel = ldq_uop_8_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_imm_sel = ldq_uop_8_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_8_pimm = ldq_uop_8_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_pimm = ldq_uop_8_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_8_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_8_imm_packed = ldq_uop_8_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_25_imm_packed = ldq_uop_8_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_8_op1_sel = ldq_uop_8_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_op1_sel = ldq_uop_8_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_8_op2_sel = ldq_uop_8_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_op2_sel = ldq_uop_8_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ldst = ldq_uop_8_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ldst = ldq_uop_8_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_wen = ldq_uop_8_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_wen = ldq_uop_8_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ren1 = ldq_uop_8_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ren1 = ldq_uop_8_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ren2 = ldq_uop_8_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ren2 = ldq_uop_8_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ren3 = ldq_uop_8_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ren3 = ldq_uop_8_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_swap12 = ldq_uop_8_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_swap12 = ldq_uop_8_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_swap23 = ldq_uop_8_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_swap23 = ldq_uop_8_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_8_fp_ctrl_typeTagIn = ldq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_fp_ctrl_typeTagIn = ldq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_8_fp_ctrl_typeTagOut = ldq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_fp_ctrl_typeTagOut = ldq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_fromint = ldq_uop_8_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_fromint = ldq_uop_8_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_toint = ldq_uop_8_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_toint = ldq_uop_8_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_fastpipe = ldq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_fastpipe = ldq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_fma = ldq_uop_8_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_fma = ldq_uop_8_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_div = ldq_uop_8_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_div = ldq_uop_8_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_sqrt = ldq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_sqrt = ldq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_wflags = ldq_uop_8_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_wflags = ldq_uop_8_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_vec = ldq_uop_8_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_vec = ldq_uop_8_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_8_rob_idx = ldq_uop_8_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_rob_idx = ldq_uop_8_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_8_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_8_ldq_idx = ldq_uop_8_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_25_ldq_idx = ldq_uop_8_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_8_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_8_stq_idx = ldq_uop_8_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_25_stq_idx = ldq_uop_8_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_8_rxq_idx = ldq_uop_8_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_rxq_idx = ldq_uop_8_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_8_pdst = ldq_uop_8_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_pdst = ldq_uop_8_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_8_prs1 = ldq_uop_8_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_prs1 = ldq_uop_8_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_8_prs2 = ldq_uop_8_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_prs2 = ldq_uop_8_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_8_prs3 = ldq_uop_8_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_prs3 = ldq_uop_8_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_8_ppred = ldq_uop_8_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_ppred = ldq_uop_8_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_prs1_busy; // @[lsu.scala:219:36] wire l_uop_8_prs1_busy = ldq_uop_8_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_prs1_busy = ldq_uop_8_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_prs2_busy; // @[lsu.scala:219:36] wire l_uop_8_prs2_busy = ldq_uop_8_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_prs2_busy = ldq_uop_8_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_prs3_busy; // @[lsu.scala:219:36] wire l_uop_8_prs3_busy = ldq_uop_8_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_prs3_busy = ldq_uop_8_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_ppred_busy; // @[lsu.scala:219:36] wire l_uop_8_ppred_busy = ldq_uop_8_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_ppred_busy = ldq_uop_8_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_8_stale_pdst = ldq_uop_8_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_stale_pdst = ldq_uop_8_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_exception; // @[lsu.scala:219:36] wire l_uop_8_exception = ldq_uop_8_exception; // @[lsu.scala:219:36, :1191:37] wire uop_25_exception = ldq_uop_8_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_8_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_8_exc_cause = ldq_uop_8_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_25_exc_cause = ldq_uop_8_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_8_mem_cmd = ldq_uop_8_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_mem_cmd = ldq_uop_8_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_8_mem_size = ldq_uop_8_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_mem_size = ldq_uop_8_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_mem_signed; // @[lsu.scala:219:36] wire l_uop_8_mem_signed = ldq_uop_8_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_25_mem_signed = ldq_uop_8_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_uses_ldq; // @[lsu.scala:219:36] wire l_uop_8_uses_ldq = ldq_uop_8_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_25_uses_ldq = ldq_uop_8_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_uses_stq; // @[lsu.scala:219:36] wire l_uop_8_uses_stq = ldq_uop_8_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_25_uses_stq = ldq_uop_8_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_unique; // @[lsu.scala:219:36] wire l_uop_8_is_unique = ldq_uop_8_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_unique = ldq_uop_8_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_8_flush_on_commit = ldq_uop_8_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_25_flush_on_commit = ldq_uop_8_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_8_csr_cmd = ldq_uop_8_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_csr_cmd = ldq_uop_8_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_8_ldst_is_rs1 = ldq_uop_8_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_25_ldst_is_rs1 = ldq_uop_8_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_8_ldst = ldq_uop_8_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_ldst = ldq_uop_8_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_8_lrs1 = ldq_uop_8_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_lrs1 = ldq_uop_8_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_8_lrs2 = ldq_uop_8_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_lrs2 = ldq_uop_8_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_8_lrs3 = ldq_uop_8_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_lrs3 = ldq_uop_8_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_8_dst_rtype = ldq_uop_8_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_dst_rtype = ldq_uop_8_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_8_lrs1_rtype = ldq_uop_8_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_lrs1_rtype = ldq_uop_8_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_8_lrs2_rtype = ldq_uop_8_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_lrs2_rtype = ldq_uop_8_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_frs3_en; // @[lsu.scala:219:36] wire l_uop_8_frs3_en = ldq_uop_8_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_25_frs3_en = ldq_uop_8_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fcn_dw; // @[lsu.scala:219:36] wire l_uop_8_fcn_dw = ldq_uop_8_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_25_fcn_dw = ldq_uop_8_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_8_fcn_op = ldq_uop_8_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_fcn_op = ldq_uop_8_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_val; // @[lsu.scala:219:36] wire l_uop_8_fp_val = ldq_uop_8_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_val = ldq_uop_8_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_8_fp_rm = ldq_uop_8_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_fp_rm = ldq_uop_8_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_8_fp_typ = ldq_uop_8_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_fp_typ = ldq_uop_8_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_8_xcpt_pf_if = ldq_uop_8_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_xcpt_pf_if = ldq_uop_8_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_8_xcpt_ae_if = ldq_uop_8_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_xcpt_ae_if = ldq_uop_8_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_8_xcpt_ma_if = ldq_uop_8_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_xcpt_ma_if = ldq_uop_8_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_8_bp_debug_if = ldq_uop_8_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_bp_debug_if = ldq_uop_8_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_8_bp_xcpt_if = ldq_uop_8_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_bp_xcpt_if = ldq_uop_8_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_8_debug_fsrc = ldq_uop_8_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_debug_fsrc = ldq_uop_8_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_8_debug_tsrc = ldq_uop_8_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_debug_tsrc = ldq_uop_8_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_9_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_9_inst = ldq_uop_9_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_26_inst = ldq_uop_9_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_9_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_9_debug_inst = ldq_uop_9_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_26_debug_inst = ldq_uop_9_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_rvc; // @[lsu.scala:219:36] wire l_uop_9_is_rvc = ldq_uop_9_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_rvc = ldq_uop_9_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_9_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_9_debug_pc = ldq_uop_9_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_26_debug_pc = ldq_uop_9_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_0; // @[lsu.scala:219:36] wire l_uop_9_iq_type_0 = ldq_uop_9_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_0 = ldq_uop_9_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_1; // @[lsu.scala:219:36] wire l_uop_9_iq_type_1 = ldq_uop_9_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_1 = ldq_uop_9_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_2; // @[lsu.scala:219:36] wire l_uop_9_iq_type_2 = ldq_uop_9_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_2 = ldq_uop_9_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_3; // @[lsu.scala:219:36] wire l_uop_9_iq_type_3 = ldq_uop_9_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_3 = ldq_uop_9_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_0; // @[lsu.scala:219:36] wire l_uop_9_fu_code_0 = ldq_uop_9_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_0 = ldq_uop_9_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_1; // @[lsu.scala:219:36] wire l_uop_9_fu_code_1 = ldq_uop_9_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_1 = ldq_uop_9_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_2; // @[lsu.scala:219:36] wire l_uop_9_fu_code_2 = ldq_uop_9_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_2 = ldq_uop_9_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_3; // @[lsu.scala:219:36] wire l_uop_9_fu_code_3 = ldq_uop_9_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_3 = ldq_uop_9_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_4; // @[lsu.scala:219:36] wire l_uop_9_fu_code_4 = ldq_uop_9_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_4 = ldq_uop_9_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_5; // @[lsu.scala:219:36] wire l_uop_9_fu_code_5 = ldq_uop_9_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_5 = ldq_uop_9_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_6; // @[lsu.scala:219:36] wire l_uop_9_fu_code_6 = ldq_uop_9_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_6 = ldq_uop_9_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_7; // @[lsu.scala:219:36] wire l_uop_9_fu_code_7 = ldq_uop_9_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_7 = ldq_uop_9_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_8; // @[lsu.scala:219:36] wire l_uop_9_fu_code_8 = ldq_uop_9_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_8 = ldq_uop_9_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_9; // @[lsu.scala:219:36] wire l_uop_9_fu_code_9 = ldq_uop_9_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_9 = ldq_uop_9_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_issued; // @[lsu.scala:219:36] wire l_uop_9_iw_issued = ldq_uop_9_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_issued = ldq_uop_9_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_9_iw_issued_partial_agen = ldq_uop_9_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_issued_partial_agen = ldq_uop_9_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_9_iw_issued_partial_dgen = ldq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_issued_partial_dgen = ldq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_9_iw_p1_speculative_child = ldq_uop_9_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_iw_p1_speculative_child = ldq_uop_9_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_9_iw_p2_speculative_child = ldq_uop_9_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_iw_p2_speculative_child = ldq_uop_9_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_9_iw_p1_bypass_hint = ldq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_p1_bypass_hint = ldq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_9_iw_p2_bypass_hint = ldq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_p2_bypass_hint = ldq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_9_iw_p3_bypass_hint = ldq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_p3_bypass_hint = ldq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_9_dis_col_sel = ldq_uop_9_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_dis_col_sel = ldq_uop_9_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_9_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_9_br_mask = ldq_uop_9_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_26_br_mask = ldq_uop_9_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_9_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_9_br_tag = ldq_uop_9_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_26_br_tag = ldq_uop_9_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_9_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_9_br_type = ldq_uop_9_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_26_br_type = ldq_uop_9_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_sfb; // @[lsu.scala:219:36] wire l_uop_9_is_sfb = ldq_uop_9_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_sfb = ldq_uop_9_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_fence; // @[lsu.scala:219:36] wire l_uop_9_is_fence = ldq_uop_9_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_fence = ldq_uop_9_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_fencei; // @[lsu.scala:219:36] wire l_uop_9_is_fencei = ldq_uop_9_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_fencei = ldq_uop_9_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_sfence; // @[lsu.scala:219:36] wire l_uop_9_is_sfence = ldq_uop_9_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_sfence = ldq_uop_9_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_amo; // @[lsu.scala:219:36] wire l_uop_9_is_amo = ldq_uop_9_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_amo = ldq_uop_9_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_eret; // @[lsu.scala:219:36] wire l_uop_9_is_eret = ldq_uop_9_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_eret = ldq_uop_9_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_9_is_sys_pc2epc = ldq_uop_9_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_sys_pc2epc = ldq_uop_9_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_rocc; // @[lsu.scala:219:36] wire l_uop_9_is_rocc = ldq_uop_9_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_rocc = ldq_uop_9_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_mov; // @[lsu.scala:219:36] wire l_uop_9_is_mov = ldq_uop_9_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_mov = ldq_uop_9_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_9_ftq_idx = ldq_uop_9_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_ftq_idx = ldq_uop_9_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_edge_inst; // @[lsu.scala:219:36] wire l_uop_9_edge_inst = ldq_uop_9_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_26_edge_inst = ldq_uop_9_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_9_pc_lob = ldq_uop_9_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_pc_lob = ldq_uop_9_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_taken; // @[lsu.scala:219:36] wire l_uop_9_taken = ldq_uop_9_taken; // @[lsu.scala:219:36, :1191:37] wire uop_26_taken = ldq_uop_9_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_imm_rename; // @[lsu.scala:219:36] wire l_uop_9_imm_rename = ldq_uop_9_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_26_imm_rename = ldq_uop_9_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_9_imm_sel = ldq_uop_9_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_imm_sel = ldq_uop_9_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_9_pimm = ldq_uop_9_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_pimm = ldq_uop_9_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_9_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_9_imm_packed = ldq_uop_9_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_26_imm_packed = ldq_uop_9_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_9_op1_sel = ldq_uop_9_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_op1_sel = ldq_uop_9_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_9_op2_sel = ldq_uop_9_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_op2_sel = ldq_uop_9_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ldst = ldq_uop_9_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ldst = ldq_uop_9_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_wen = ldq_uop_9_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_wen = ldq_uop_9_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ren1 = ldq_uop_9_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ren1 = ldq_uop_9_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ren2 = ldq_uop_9_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ren2 = ldq_uop_9_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ren3 = ldq_uop_9_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ren3 = ldq_uop_9_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_swap12 = ldq_uop_9_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_swap12 = ldq_uop_9_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_swap23 = ldq_uop_9_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_swap23 = ldq_uop_9_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_9_fp_ctrl_typeTagIn = ldq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_fp_ctrl_typeTagIn = ldq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_9_fp_ctrl_typeTagOut = ldq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_fp_ctrl_typeTagOut = ldq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_fromint = ldq_uop_9_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_fromint = ldq_uop_9_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_toint = ldq_uop_9_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_toint = ldq_uop_9_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_fastpipe = ldq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_fastpipe = ldq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_fma = ldq_uop_9_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_fma = ldq_uop_9_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_div = ldq_uop_9_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_div = ldq_uop_9_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_sqrt = ldq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_sqrt = ldq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_wflags = ldq_uop_9_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_wflags = ldq_uop_9_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_vec = ldq_uop_9_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_vec = ldq_uop_9_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_9_rob_idx = ldq_uop_9_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_rob_idx = ldq_uop_9_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_9_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_9_ldq_idx = ldq_uop_9_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_26_ldq_idx = ldq_uop_9_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_9_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_9_stq_idx = ldq_uop_9_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_26_stq_idx = ldq_uop_9_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_9_rxq_idx = ldq_uop_9_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_rxq_idx = ldq_uop_9_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_9_pdst = ldq_uop_9_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_pdst = ldq_uop_9_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_9_prs1 = ldq_uop_9_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_prs1 = ldq_uop_9_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_9_prs2 = ldq_uop_9_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_prs2 = ldq_uop_9_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_9_prs3 = ldq_uop_9_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_prs3 = ldq_uop_9_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_9_ppred = ldq_uop_9_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_ppred = ldq_uop_9_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_prs1_busy; // @[lsu.scala:219:36] wire l_uop_9_prs1_busy = ldq_uop_9_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_prs1_busy = ldq_uop_9_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_prs2_busy; // @[lsu.scala:219:36] wire l_uop_9_prs2_busy = ldq_uop_9_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_prs2_busy = ldq_uop_9_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_prs3_busy; // @[lsu.scala:219:36] wire l_uop_9_prs3_busy = ldq_uop_9_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_prs3_busy = ldq_uop_9_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_ppred_busy; // @[lsu.scala:219:36] wire l_uop_9_ppred_busy = ldq_uop_9_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_ppred_busy = ldq_uop_9_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_9_stale_pdst = ldq_uop_9_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_stale_pdst = ldq_uop_9_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_exception; // @[lsu.scala:219:36] wire l_uop_9_exception = ldq_uop_9_exception; // @[lsu.scala:219:36, :1191:37] wire uop_26_exception = ldq_uop_9_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_9_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_9_exc_cause = ldq_uop_9_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_26_exc_cause = ldq_uop_9_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_9_mem_cmd = ldq_uop_9_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_mem_cmd = ldq_uop_9_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_9_mem_size = ldq_uop_9_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_mem_size = ldq_uop_9_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_mem_signed; // @[lsu.scala:219:36] wire l_uop_9_mem_signed = ldq_uop_9_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_26_mem_signed = ldq_uop_9_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_uses_ldq; // @[lsu.scala:219:36] wire l_uop_9_uses_ldq = ldq_uop_9_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_26_uses_ldq = ldq_uop_9_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_uses_stq; // @[lsu.scala:219:36] wire l_uop_9_uses_stq = ldq_uop_9_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_26_uses_stq = ldq_uop_9_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_unique; // @[lsu.scala:219:36] wire l_uop_9_is_unique = ldq_uop_9_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_unique = ldq_uop_9_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_9_flush_on_commit = ldq_uop_9_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_26_flush_on_commit = ldq_uop_9_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_9_csr_cmd = ldq_uop_9_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_csr_cmd = ldq_uop_9_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_9_ldst_is_rs1 = ldq_uop_9_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_26_ldst_is_rs1 = ldq_uop_9_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_9_ldst = ldq_uop_9_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_ldst = ldq_uop_9_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_9_lrs1 = ldq_uop_9_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_lrs1 = ldq_uop_9_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_9_lrs2 = ldq_uop_9_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_lrs2 = ldq_uop_9_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_9_lrs3 = ldq_uop_9_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_lrs3 = ldq_uop_9_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_9_dst_rtype = ldq_uop_9_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_dst_rtype = ldq_uop_9_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_9_lrs1_rtype = ldq_uop_9_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_lrs1_rtype = ldq_uop_9_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_9_lrs2_rtype = ldq_uop_9_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_lrs2_rtype = ldq_uop_9_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_frs3_en; // @[lsu.scala:219:36] wire l_uop_9_frs3_en = ldq_uop_9_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_26_frs3_en = ldq_uop_9_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fcn_dw; // @[lsu.scala:219:36] wire l_uop_9_fcn_dw = ldq_uop_9_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_26_fcn_dw = ldq_uop_9_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_9_fcn_op = ldq_uop_9_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_fcn_op = ldq_uop_9_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_val; // @[lsu.scala:219:36] wire l_uop_9_fp_val = ldq_uop_9_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_val = ldq_uop_9_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_9_fp_rm = ldq_uop_9_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_fp_rm = ldq_uop_9_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_9_fp_typ = ldq_uop_9_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_fp_typ = ldq_uop_9_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_9_xcpt_pf_if = ldq_uop_9_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_xcpt_pf_if = ldq_uop_9_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_9_xcpt_ae_if = ldq_uop_9_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_xcpt_ae_if = ldq_uop_9_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_9_xcpt_ma_if = ldq_uop_9_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_xcpt_ma_if = ldq_uop_9_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_9_bp_debug_if = ldq_uop_9_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_bp_debug_if = ldq_uop_9_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_9_bp_xcpt_if = ldq_uop_9_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_bp_xcpt_if = ldq_uop_9_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_9_debug_fsrc = ldq_uop_9_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_debug_fsrc = ldq_uop_9_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_9_debug_tsrc = ldq_uop_9_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_debug_tsrc = ldq_uop_9_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_10_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_10_inst = ldq_uop_10_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_27_inst = ldq_uop_10_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_10_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_10_debug_inst = ldq_uop_10_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_27_debug_inst = ldq_uop_10_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_rvc; // @[lsu.scala:219:36] wire l_uop_10_is_rvc = ldq_uop_10_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_rvc = ldq_uop_10_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_10_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_10_debug_pc = ldq_uop_10_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_27_debug_pc = ldq_uop_10_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_0; // @[lsu.scala:219:36] wire l_uop_10_iq_type_0 = ldq_uop_10_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_0 = ldq_uop_10_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_1; // @[lsu.scala:219:36] wire l_uop_10_iq_type_1 = ldq_uop_10_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_1 = ldq_uop_10_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_2; // @[lsu.scala:219:36] wire l_uop_10_iq_type_2 = ldq_uop_10_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_2 = ldq_uop_10_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_3; // @[lsu.scala:219:36] wire l_uop_10_iq_type_3 = ldq_uop_10_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_3 = ldq_uop_10_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_0; // @[lsu.scala:219:36] wire l_uop_10_fu_code_0 = ldq_uop_10_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_0 = ldq_uop_10_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_1; // @[lsu.scala:219:36] wire l_uop_10_fu_code_1 = ldq_uop_10_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_1 = ldq_uop_10_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_2; // @[lsu.scala:219:36] wire l_uop_10_fu_code_2 = ldq_uop_10_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_2 = ldq_uop_10_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_3; // @[lsu.scala:219:36] wire l_uop_10_fu_code_3 = ldq_uop_10_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_3 = ldq_uop_10_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_4; // @[lsu.scala:219:36] wire l_uop_10_fu_code_4 = ldq_uop_10_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_4 = ldq_uop_10_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_5; // @[lsu.scala:219:36] wire l_uop_10_fu_code_5 = ldq_uop_10_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_5 = ldq_uop_10_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_6; // @[lsu.scala:219:36] wire l_uop_10_fu_code_6 = ldq_uop_10_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_6 = ldq_uop_10_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_7; // @[lsu.scala:219:36] wire l_uop_10_fu_code_7 = ldq_uop_10_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_7 = ldq_uop_10_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_8; // @[lsu.scala:219:36] wire l_uop_10_fu_code_8 = ldq_uop_10_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_8 = ldq_uop_10_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_9; // @[lsu.scala:219:36] wire l_uop_10_fu_code_9 = ldq_uop_10_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_9 = ldq_uop_10_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_issued; // @[lsu.scala:219:36] wire l_uop_10_iw_issued = ldq_uop_10_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_issued = ldq_uop_10_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_10_iw_issued_partial_agen = ldq_uop_10_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_issued_partial_agen = ldq_uop_10_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_10_iw_issued_partial_dgen = ldq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_issued_partial_dgen = ldq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_10_iw_p1_speculative_child = ldq_uop_10_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_iw_p1_speculative_child = ldq_uop_10_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_10_iw_p2_speculative_child = ldq_uop_10_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_iw_p2_speculative_child = ldq_uop_10_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_10_iw_p1_bypass_hint = ldq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_p1_bypass_hint = ldq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_10_iw_p2_bypass_hint = ldq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_p2_bypass_hint = ldq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_10_iw_p3_bypass_hint = ldq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_p3_bypass_hint = ldq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_10_dis_col_sel = ldq_uop_10_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_dis_col_sel = ldq_uop_10_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_10_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_10_br_mask = ldq_uop_10_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_27_br_mask = ldq_uop_10_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_10_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_10_br_tag = ldq_uop_10_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_27_br_tag = ldq_uop_10_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_10_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_10_br_type = ldq_uop_10_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_27_br_type = ldq_uop_10_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_sfb; // @[lsu.scala:219:36] wire l_uop_10_is_sfb = ldq_uop_10_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_sfb = ldq_uop_10_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_fence; // @[lsu.scala:219:36] wire l_uop_10_is_fence = ldq_uop_10_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_fence = ldq_uop_10_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_fencei; // @[lsu.scala:219:36] wire l_uop_10_is_fencei = ldq_uop_10_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_fencei = ldq_uop_10_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_sfence; // @[lsu.scala:219:36] wire l_uop_10_is_sfence = ldq_uop_10_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_sfence = ldq_uop_10_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_amo; // @[lsu.scala:219:36] wire l_uop_10_is_amo = ldq_uop_10_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_amo = ldq_uop_10_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_eret; // @[lsu.scala:219:36] wire l_uop_10_is_eret = ldq_uop_10_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_eret = ldq_uop_10_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_10_is_sys_pc2epc = ldq_uop_10_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_sys_pc2epc = ldq_uop_10_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_rocc; // @[lsu.scala:219:36] wire l_uop_10_is_rocc = ldq_uop_10_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_rocc = ldq_uop_10_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_mov; // @[lsu.scala:219:36] wire l_uop_10_is_mov = ldq_uop_10_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_mov = ldq_uop_10_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_10_ftq_idx = ldq_uop_10_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_ftq_idx = ldq_uop_10_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_edge_inst; // @[lsu.scala:219:36] wire l_uop_10_edge_inst = ldq_uop_10_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_27_edge_inst = ldq_uop_10_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_10_pc_lob = ldq_uop_10_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_pc_lob = ldq_uop_10_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_taken; // @[lsu.scala:219:36] wire l_uop_10_taken = ldq_uop_10_taken; // @[lsu.scala:219:36, :1191:37] wire uop_27_taken = ldq_uop_10_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_imm_rename; // @[lsu.scala:219:36] wire l_uop_10_imm_rename = ldq_uop_10_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_27_imm_rename = ldq_uop_10_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_10_imm_sel = ldq_uop_10_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_imm_sel = ldq_uop_10_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_10_pimm = ldq_uop_10_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_pimm = ldq_uop_10_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_10_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_10_imm_packed = ldq_uop_10_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_27_imm_packed = ldq_uop_10_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_10_op1_sel = ldq_uop_10_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_op1_sel = ldq_uop_10_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_10_op2_sel = ldq_uop_10_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_op2_sel = ldq_uop_10_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ldst = ldq_uop_10_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ldst = ldq_uop_10_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_wen = ldq_uop_10_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_wen = ldq_uop_10_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ren1 = ldq_uop_10_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ren1 = ldq_uop_10_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ren2 = ldq_uop_10_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ren2 = ldq_uop_10_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ren3 = ldq_uop_10_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ren3 = ldq_uop_10_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_swap12 = ldq_uop_10_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_swap12 = ldq_uop_10_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_swap23 = ldq_uop_10_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_swap23 = ldq_uop_10_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_10_fp_ctrl_typeTagIn = ldq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_fp_ctrl_typeTagIn = ldq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_10_fp_ctrl_typeTagOut = ldq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_fp_ctrl_typeTagOut = ldq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_fromint = ldq_uop_10_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_fromint = ldq_uop_10_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_toint = ldq_uop_10_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_toint = ldq_uop_10_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_fastpipe = ldq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_fastpipe = ldq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_fma = ldq_uop_10_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_fma = ldq_uop_10_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_div = ldq_uop_10_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_div = ldq_uop_10_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_sqrt = ldq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_sqrt = ldq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_wflags = ldq_uop_10_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_wflags = ldq_uop_10_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_vec = ldq_uop_10_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_vec = ldq_uop_10_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_10_rob_idx = ldq_uop_10_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_rob_idx = ldq_uop_10_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_10_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_10_ldq_idx = ldq_uop_10_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_27_ldq_idx = ldq_uop_10_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_10_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_10_stq_idx = ldq_uop_10_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_27_stq_idx = ldq_uop_10_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_10_rxq_idx = ldq_uop_10_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_rxq_idx = ldq_uop_10_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_10_pdst = ldq_uop_10_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_pdst = ldq_uop_10_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_10_prs1 = ldq_uop_10_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_prs1 = ldq_uop_10_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_10_prs2 = ldq_uop_10_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_prs2 = ldq_uop_10_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_10_prs3 = ldq_uop_10_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_prs3 = ldq_uop_10_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_10_ppred = ldq_uop_10_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_ppred = ldq_uop_10_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_prs1_busy; // @[lsu.scala:219:36] wire l_uop_10_prs1_busy = ldq_uop_10_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_prs1_busy = ldq_uop_10_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_prs2_busy; // @[lsu.scala:219:36] wire l_uop_10_prs2_busy = ldq_uop_10_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_prs2_busy = ldq_uop_10_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_prs3_busy; // @[lsu.scala:219:36] wire l_uop_10_prs3_busy = ldq_uop_10_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_prs3_busy = ldq_uop_10_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_ppred_busy; // @[lsu.scala:219:36] wire l_uop_10_ppred_busy = ldq_uop_10_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_ppred_busy = ldq_uop_10_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_10_stale_pdst = ldq_uop_10_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_stale_pdst = ldq_uop_10_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_exception; // @[lsu.scala:219:36] wire l_uop_10_exception = ldq_uop_10_exception; // @[lsu.scala:219:36, :1191:37] wire uop_27_exception = ldq_uop_10_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_10_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_10_exc_cause = ldq_uop_10_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_27_exc_cause = ldq_uop_10_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_10_mem_cmd = ldq_uop_10_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_mem_cmd = ldq_uop_10_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_10_mem_size = ldq_uop_10_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_mem_size = ldq_uop_10_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_mem_signed; // @[lsu.scala:219:36] wire l_uop_10_mem_signed = ldq_uop_10_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_27_mem_signed = ldq_uop_10_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_uses_ldq; // @[lsu.scala:219:36] wire l_uop_10_uses_ldq = ldq_uop_10_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_27_uses_ldq = ldq_uop_10_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_uses_stq; // @[lsu.scala:219:36] wire l_uop_10_uses_stq = ldq_uop_10_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_27_uses_stq = ldq_uop_10_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_unique; // @[lsu.scala:219:36] wire l_uop_10_is_unique = ldq_uop_10_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_unique = ldq_uop_10_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_10_flush_on_commit = ldq_uop_10_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_27_flush_on_commit = ldq_uop_10_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_10_csr_cmd = ldq_uop_10_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_csr_cmd = ldq_uop_10_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_10_ldst_is_rs1 = ldq_uop_10_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_27_ldst_is_rs1 = ldq_uop_10_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_10_ldst = ldq_uop_10_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_ldst = ldq_uop_10_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_10_lrs1 = ldq_uop_10_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_lrs1 = ldq_uop_10_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_10_lrs2 = ldq_uop_10_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_lrs2 = ldq_uop_10_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_10_lrs3 = ldq_uop_10_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_lrs3 = ldq_uop_10_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_10_dst_rtype = ldq_uop_10_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_dst_rtype = ldq_uop_10_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_10_lrs1_rtype = ldq_uop_10_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_lrs1_rtype = ldq_uop_10_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_10_lrs2_rtype = ldq_uop_10_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_lrs2_rtype = ldq_uop_10_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_frs3_en; // @[lsu.scala:219:36] wire l_uop_10_frs3_en = ldq_uop_10_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_27_frs3_en = ldq_uop_10_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fcn_dw; // @[lsu.scala:219:36] wire l_uop_10_fcn_dw = ldq_uop_10_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_27_fcn_dw = ldq_uop_10_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_10_fcn_op = ldq_uop_10_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_fcn_op = ldq_uop_10_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_val; // @[lsu.scala:219:36] wire l_uop_10_fp_val = ldq_uop_10_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_val = ldq_uop_10_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_10_fp_rm = ldq_uop_10_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_fp_rm = ldq_uop_10_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_10_fp_typ = ldq_uop_10_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_fp_typ = ldq_uop_10_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_10_xcpt_pf_if = ldq_uop_10_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_xcpt_pf_if = ldq_uop_10_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_10_xcpt_ae_if = ldq_uop_10_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_xcpt_ae_if = ldq_uop_10_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_10_xcpt_ma_if = ldq_uop_10_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_xcpt_ma_if = ldq_uop_10_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_10_bp_debug_if = ldq_uop_10_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_bp_debug_if = ldq_uop_10_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_10_bp_xcpt_if = ldq_uop_10_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_bp_xcpt_if = ldq_uop_10_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_10_debug_fsrc = ldq_uop_10_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_debug_fsrc = ldq_uop_10_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_10_debug_tsrc = ldq_uop_10_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_debug_tsrc = ldq_uop_10_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_11_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_11_inst = ldq_uop_11_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_28_inst = ldq_uop_11_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_11_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_11_debug_inst = ldq_uop_11_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_28_debug_inst = ldq_uop_11_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_rvc; // @[lsu.scala:219:36] wire l_uop_11_is_rvc = ldq_uop_11_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_rvc = ldq_uop_11_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_11_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_11_debug_pc = ldq_uop_11_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_28_debug_pc = ldq_uop_11_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_0; // @[lsu.scala:219:36] wire l_uop_11_iq_type_0 = ldq_uop_11_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_0 = ldq_uop_11_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_1; // @[lsu.scala:219:36] wire l_uop_11_iq_type_1 = ldq_uop_11_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_1 = ldq_uop_11_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_2; // @[lsu.scala:219:36] wire l_uop_11_iq_type_2 = ldq_uop_11_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_2 = ldq_uop_11_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_3; // @[lsu.scala:219:36] wire l_uop_11_iq_type_3 = ldq_uop_11_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_3 = ldq_uop_11_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_0; // @[lsu.scala:219:36] wire l_uop_11_fu_code_0 = ldq_uop_11_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_0 = ldq_uop_11_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_1; // @[lsu.scala:219:36] wire l_uop_11_fu_code_1 = ldq_uop_11_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_1 = ldq_uop_11_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_2; // @[lsu.scala:219:36] wire l_uop_11_fu_code_2 = ldq_uop_11_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_2 = ldq_uop_11_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_3; // @[lsu.scala:219:36] wire l_uop_11_fu_code_3 = ldq_uop_11_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_3 = ldq_uop_11_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_4; // @[lsu.scala:219:36] wire l_uop_11_fu_code_4 = ldq_uop_11_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_4 = ldq_uop_11_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_5; // @[lsu.scala:219:36] wire l_uop_11_fu_code_5 = ldq_uop_11_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_5 = ldq_uop_11_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_6; // @[lsu.scala:219:36] wire l_uop_11_fu_code_6 = ldq_uop_11_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_6 = ldq_uop_11_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_7; // @[lsu.scala:219:36] wire l_uop_11_fu_code_7 = ldq_uop_11_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_7 = ldq_uop_11_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_8; // @[lsu.scala:219:36] wire l_uop_11_fu_code_8 = ldq_uop_11_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_8 = ldq_uop_11_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_9; // @[lsu.scala:219:36] wire l_uop_11_fu_code_9 = ldq_uop_11_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_9 = ldq_uop_11_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_issued; // @[lsu.scala:219:36] wire l_uop_11_iw_issued = ldq_uop_11_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_issued = ldq_uop_11_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_11_iw_issued_partial_agen = ldq_uop_11_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_issued_partial_agen = ldq_uop_11_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_11_iw_issued_partial_dgen = ldq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_issued_partial_dgen = ldq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_11_iw_p1_speculative_child = ldq_uop_11_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_iw_p1_speculative_child = ldq_uop_11_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_11_iw_p2_speculative_child = ldq_uop_11_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_iw_p2_speculative_child = ldq_uop_11_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_11_iw_p1_bypass_hint = ldq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_p1_bypass_hint = ldq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_11_iw_p2_bypass_hint = ldq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_p2_bypass_hint = ldq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_11_iw_p3_bypass_hint = ldq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_p3_bypass_hint = ldq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_11_dis_col_sel = ldq_uop_11_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_dis_col_sel = ldq_uop_11_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_11_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_11_br_mask = ldq_uop_11_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_28_br_mask = ldq_uop_11_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_11_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_11_br_tag = ldq_uop_11_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_28_br_tag = ldq_uop_11_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_11_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_11_br_type = ldq_uop_11_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_28_br_type = ldq_uop_11_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_sfb; // @[lsu.scala:219:36] wire l_uop_11_is_sfb = ldq_uop_11_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_sfb = ldq_uop_11_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_fence; // @[lsu.scala:219:36] wire l_uop_11_is_fence = ldq_uop_11_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_fence = ldq_uop_11_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_fencei; // @[lsu.scala:219:36] wire l_uop_11_is_fencei = ldq_uop_11_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_fencei = ldq_uop_11_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_sfence; // @[lsu.scala:219:36] wire l_uop_11_is_sfence = ldq_uop_11_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_sfence = ldq_uop_11_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_amo; // @[lsu.scala:219:36] wire l_uop_11_is_amo = ldq_uop_11_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_amo = ldq_uop_11_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_eret; // @[lsu.scala:219:36] wire l_uop_11_is_eret = ldq_uop_11_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_eret = ldq_uop_11_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_11_is_sys_pc2epc = ldq_uop_11_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_sys_pc2epc = ldq_uop_11_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_rocc; // @[lsu.scala:219:36] wire l_uop_11_is_rocc = ldq_uop_11_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_rocc = ldq_uop_11_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_mov; // @[lsu.scala:219:36] wire l_uop_11_is_mov = ldq_uop_11_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_mov = ldq_uop_11_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_11_ftq_idx = ldq_uop_11_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_ftq_idx = ldq_uop_11_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_edge_inst; // @[lsu.scala:219:36] wire l_uop_11_edge_inst = ldq_uop_11_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_28_edge_inst = ldq_uop_11_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_11_pc_lob = ldq_uop_11_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_pc_lob = ldq_uop_11_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_taken; // @[lsu.scala:219:36] wire l_uop_11_taken = ldq_uop_11_taken; // @[lsu.scala:219:36, :1191:37] wire uop_28_taken = ldq_uop_11_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_imm_rename; // @[lsu.scala:219:36] wire l_uop_11_imm_rename = ldq_uop_11_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_28_imm_rename = ldq_uop_11_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_11_imm_sel = ldq_uop_11_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_imm_sel = ldq_uop_11_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_11_pimm = ldq_uop_11_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_pimm = ldq_uop_11_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_11_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_11_imm_packed = ldq_uop_11_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_28_imm_packed = ldq_uop_11_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_11_op1_sel = ldq_uop_11_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_op1_sel = ldq_uop_11_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_11_op2_sel = ldq_uop_11_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_op2_sel = ldq_uop_11_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ldst = ldq_uop_11_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ldst = ldq_uop_11_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_wen = ldq_uop_11_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_wen = ldq_uop_11_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ren1 = ldq_uop_11_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ren1 = ldq_uop_11_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ren2 = ldq_uop_11_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ren2 = ldq_uop_11_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ren3 = ldq_uop_11_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ren3 = ldq_uop_11_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_swap12 = ldq_uop_11_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_swap12 = ldq_uop_11_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_swap23 = ldq_uop_11_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_swap23 = ldq_uop_11_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_11_fp_ctrl_typeTagIn = ldq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_fp_ctrl_typeTagIn = ldq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_11_fp_ctrl_typeTagOut = ldq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_fp_ctrl_typeTagOut = ldq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_fromint = ldq_uop_11_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_fromint = ldq_uop_11_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_toint = ldq_uop_11_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_toint = ldq_uop_11_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_fastpipe = ldq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_fastpipe = ldq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_fma = ldq_uop_11_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_fma = ldq_uop_11_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_div = ldq_uop_11_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_div = ldq_uop_11_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_sqrt = ldq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_sqrt = ldq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_wflags = ldq_uop_11_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_wflags = ldq_uop_11_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_vec = ldq_uop_11_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_vec = ldq_uop_11_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_11_rob_idx = ldq_uop_11_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_rob_idx = ldq_uop_11_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_11_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_11_ldq_idx = ldq_uop_11_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_28_ldq_idx = ldq_uop_11_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_11_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_11_stq_idx = ldq_uop_11_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_28_stq_idx = ldq_uop_11_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_11_rxq_idx = ldq_uop_11_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_rxq_idx = ldq_uop_11_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_11_pdst = ldq_uop_11_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_pdst = ldq_uop_11_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_11_prs1 = ldq_uop_11_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_prs1 = ldq_uop_11_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_11_prs2 = ldq_uop_11_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_prs2 = ldq_uop_11_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_11_prs3 = ldq_uop_11_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_prs3 = ldq_uop_11_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_11_ppred = ldq_uop_11_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_ppred = ldq_uop_11_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_prs1_busy; // @[lsu.scala:219:36] wire l_uop_11_prs1_busy = ldq_uop_11_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_prs1_busy = ldq_uop_11_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_prs2_busy; // @[lsu.scala:219:36] wire l_uop_11_prs2_busy = ldq_uop_11_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_prs2_busy = ldq_uop_11_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_prs3_busy; // @[lsu.scala:219:36] wire l_uop_11_prs3_busy = ldq_uop_11_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_prs3_busy = ldq_uop_11_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_ppred_busy; // @[lsu.scala:219:36] wire l_uop_11_ppred_busy = ldq_uop_11_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_ppred_busy = ldq_uop_11_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_11_stale_pdst = ldq_uop_11_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_stale_pdst = ldq_uop_11_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_exception; // @[lsu.scala:219:36] wire l_uop_11_exception = ldq_uop_11_exception; // @[lsu.scala:219:36, :1191:37] wire uop_28_exception = ldq_uop_11_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_11_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_11_exc_cause = ldq_uop_11_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_28_exc_cause = ldq_uop_11_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_11_mem_cmd = ldq_uop_11_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_mem_cmd = ldq_uop_11_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_11_mem_size = ldq_uop_11_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_mem_size = ldq_uop_11_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_mem_signed; // @[lsu.scala:219:36] wire l_uop_11_mem_signed = ldq_uop_11_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_28_mem_signed = ldq_uop_11_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_uses_ldq; // @[lsu.scala:219:36] wire l_uop_11_uses_ldq = ldq_uop_11_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_28_uses_ldq = ldq_uop_11_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_uses_stq; // @[lsu.scala:219:36] wire l_uop_11_uses_stq = ldq_uop_11_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_28_uses_stq = ldq_uop_11_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_unique; // @[lsu.scala:219:36] wire l_uop_11_is_unique = ldq_uop_11_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_unique = ldq_uop_11_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_11_flush_on_commit = ldq_uop_11_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_28_flush_on_commit = ldq_uop_11_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_11_csr_cmd = ldq_uop_11_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_csr_cmd = ldq_uop_11_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_11_ldst_is_rs1 = ldq_uop_11_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_28_ldst_is_rs1 = ldq_uop_11_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_11_ldst = ldq_uop_11_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_ldst = ldq_uop_11_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_11_lrs1 = ldq_uop_11_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_lrs1 = ldq_uop_11_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_11_lrs2 = ldq_uop_11_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_lrs2 = ldq_uop_11_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_11_lrs3 = ldq_uop_11_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_lrs3 = ldq_uop_11_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_11_dst_rtype = ldq_uop_11_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_dst_rtype = ldq_uop_11_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_11_lrs1_rtype = ldq_uop_11_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_lrs1_rtype = ldq_uop_11_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_11_lrs2_rtype = ldq_uop_11_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_lrs2_rtype = ldq_uop_11_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_frs3_en; // @[lsu.scala:219:36] wire l_uop_11_frs3_en = ldq_uop_11_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_28_frs3_en = ldq_uop_11_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fcn_dw; // @[lsu.scala:219:36] wire l_uop_11_fcn_dw = ldq_uop_11_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_28_fcn_dw = ldq_uop_11_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_11_fcn_op = ldq_uop_11_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_fcn_op = ldq_uop_11_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_val; // @[lsu.scala:219:36] wire l_uop_11_fp_val = ldq_uop_11_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_val = ldq_uop_11_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_11_fp_rm = ldq_uop_11_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_fp_rm = ldq_uop_11_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_11_fp_typ = ldq_uop_11_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_fp_typ = ldq_uop_11_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_11_xcpt_pf_if = ldq_uop_11_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_xcpt_pf_if = ldq_uop_11_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_11_xcpt_ae_if = ldq_uop_11_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_xcpt_ae_if = ldq_uop_11_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_11_xcpt_ma_if = ldq_uop_11_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_xcpt_ma_if = ldq_uop_11_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_11_bp_debug_if = ldq_uop_11_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_bp_debug_if = ldq_uop_11_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_11_bp_xcpt_if = ldq_uop_11_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_bp_xcpt_if = ldq_uop_11_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_11_debug_fsrc = ldq_uop_11_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_debug_fsrc = ldq_uop_11_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_11_debug_tsrc = ldq_uop_11_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_debug_tsrc = ldq_uop_11_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_12_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_12_inst = ldq_uop_12_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_29_inst = ldq_uop_12_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_12_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_12_debug_inst = ldq_uop_12_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_29_debug_inst = ldq_uop_12_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_rvc; // @[lsu.scala:219:36] wire l_uop_12_is_rvc = ldq_uop_12_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_rvc = ldq_uop_12_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_12_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_12_debug_pc = ldq_uop_12_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_29_debug_pc = ldq_uop_12_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_0; // @[lsu.scala:219:36] wire l_uop_12_iq_type_0 = ldq_uop_12_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_0 = ldq_uop_12_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_1; // @[lsu.scala:219:36] wire l_uop_12_iq_type_1 = ldq_uop_12_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_1 = ldq_uop_12_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_2; // @[lsu.scala:219:36] wire l_uop_12_iq_type_2 = ldq_uop_12_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_2 = ldq_uop_12_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_3; // @[lsu.scala:219:36] wire l_uop_12_iq_type_3 = ldq_uop_12_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_3 = ldq_uop_12_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_0; // @[lsu.scala:219:36] wire l_uop_12_fu_code_0 = ldq_uop_12_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_0 = ldq_uop_12_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_1; // @[lsu.scala:219:36] wire l_uop_12_fu_code_1 = ldq_uop_12_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_1 = ldq_uop_12_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_2; // @[lsu.scala:219:36] wire l_uop_12_fu_code_2 = ldq_uop_12_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_2 = ldq_uop_12_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_3; // @[lsu.scala:219:36] wire l_uop_12_fu_code_3 = ldq_uop_12_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_3 = ldq_uop_12_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_4; // @[lsu.scala:219:36] wire l_uop_12_fu_code_4 = ldq_uop_12_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_4 = ldq_uop_12_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_5; // @[lsu.scala:219:36] wire l_uop_12_fu_code_5 = ldq_uop_12_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_5 = ldq_uop_12_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_6; // @[lsu.scala:219:36] wire l_uop_12_fu_code_6 = ldq_uop_12_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_6 = ldq_uop_12_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_7; // @[lsu.scala:219:36] wire l_uop_12_fu_code_7 = ldq_uop_12_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_7 = ldq_uop_12_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_8; // @[lsu.scala:219:36] wire l_uop_12_fu_code_8 = ldq_uop_12_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_8 = ldq_uop_12_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_9; // @[lsu.scala:219:36] wire l_uop_12_fu_code_9 = ldq_uop_12_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_9 = ldq_uop_12_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_issued; // @[lsu.scala:219:36] wire l_uop_12_iw_issued = ldq_uop_12_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_issued = ldq_uop_12_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_12_iw_issued_partial_agen = ldq_uop_12_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_issued_partial_agen = ldq_uop_12_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_12_iw_issued_partial_dgen = ldq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_issued_partial_dgen = ldq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_12_iw_p1_speculative_child = ldq_uop_12_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_iw_p1_speculative_child = ldq_uop_12_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_12_iw_p2_speculative_child = ldq_uop_12_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_iw_p2_speculative_child = ldq_uop_12_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_12_iw_p1_bypass_hint = ldq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_p1_bypass_hint = ldq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_12_iw_p2_bypass_hint = ldq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_p2_bypass_hint = ldq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_12_iw_p3_bypass_hint = ldq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_p3_bypass_hint = ldq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_12_dis_col_sel = ldq_uop_12_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_dis_col_sel = ldq_uop_12_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_12_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_12_br_mask = ldq_uop_12_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_29_br_mask = ldq_uop_12_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_12_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_12_br_tag = ldq_uop_12_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_29_br_tag = ldq_uop_12_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_12_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_12_br_type = ldq_uop_12_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_29_br_type = ldq_uop_12_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_sfb; // @[lsu.scala:219:36] wire l_uop_12_is_sfb = ldq_uop_12_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_sfb = ldq_uop_12_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_fence; // @[lsu.scala:219:36] wire l_uop_12_is_fence = ldq_uop_12_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_fence = ldq_uop_12_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_fencei; // @[lsu.scala:219:36] wire l_uop_12_is_fencei = ldq_uop_12_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_fencei = ldq_uop_12_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_sfence; // @[lsu.scala:219:36] wire l_uop_12_is_sfence = ldq_uop_12_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_sfence = ldq_uop_12_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_amo; // @[lsu.scala:219:36] wire l_uop_12_is_amo = ldq_uop_12_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_amo = ldq_uop_12_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_eret; // @[lsu.scala:219:36] wire l_uop_12_is_eret = ldq_uop_12_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_eret = ldq_uop_12_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_12_is_sys_pc2epc = ldq_uop_12_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_sys_pc2epc = ldq_uop_12_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_rocc; // @[lsu.scala:219:36] wire l_uop_12_is_rocc = ldq_uop_12_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_rocc = ldq_uop_12_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_mov; // @[lsu.scala:219:36] wire l_uop_12_is_mov = ldq_uop_12_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_mov = ldq_uop_12_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_12_ftq_idx = ldq_uop_12_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_ftq_idx = ldq_uop_12_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_edge_inst; // @[lsu.scala:219:36] wire l_uop_12_edge_inst = ldq_uop_12_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_29_edge_inst = ldq_uop_12_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_12_pc_lob = ldq_uop_12_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_pc_lob = ldq_uop_12_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_taken; // @[lsu.scala:219:36] wire l_uop_12_taken = ldq_uop_12_taken; // @[lsu.scala:219:36, :1191:37] wire uop_29_taken = ldq_uop_12_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_imm_rename; // @[lsu.scala:219:36] wire l_uop_12_imm_rename = ldq_uop_12_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_29_imm_rename = ldq_uop_12_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_12_imm_sel = ldq_uop_12_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_imm_sel = ldq_uop_12_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_12_pimm = ldq_uop_12_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_pimm = ldq_uop_12_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_12_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_12_imm_packed = ldq_uop_12_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_29_imm_packed = ldq_uop_12_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_12_op1_sel = ldq_uop_12_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_op1_sel = ldq_uop_12_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_12_op2_sel = ldq_uop_12_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_op2_sel = ldq_uop_12_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ldst = ldq_uop_12_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ldst = ldq_uop_12_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_wen = ldq_uop_12_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_wen = ldq_uop_12_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ren1 = ldq_uop_12_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ren1 = ldq_uop_12_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ren2 = ldq_uop_12_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ren2 = ldq_uop_12_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ren3 = ldq_uop_12_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ren3 = ldq_uop_12_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_swap12 = ldq_uop_12_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_swap12 = ldq_uop_12_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_swap23 = ldq_uop_12_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_swap23 = ldq_uop_12_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_12_fp_ctrl_typeTagIn = ldq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_fp_ctrl_typeTagIn = ldq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_12_fp_ctrl_typeTagOut = ldq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_fp_ctrl_typeTagOut = ldq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_fromint = ldq_uop_12_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_fromint = ldq_uop_12_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_toint = ldq_uop_12_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_toint = ldq_uop_12_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_fastpipe = ldq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_fastpipe = ldq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_fma = ldq_uop_12_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_fma = ldq_uop_12_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_div = ldq_uop_12_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_div = ldq_uop_12_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_sqrt = ldq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_sqrt = ldq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_wflags = ldq_uop_12_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_wflags = ldq_uop_12_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_vec = ldq_uop_12_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_vec = ldq_uop_12_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_12_rob_idx = ldq_uop_12_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_rob_idx = ldq_uop_12_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_12_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_12_ldq_idx = ldq_uop_12_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_29_ldq_idx = ldq_uop_12_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_12_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_12_stq_idx = ldq_uop_12_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_29_stq_idx = ldq_uop_12_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_12_rxq_idx = ldq_uop_12_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_rxq_idx = ldq_uop_12_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_12_pdst = ldq_uop_12_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_pdst = ldq_uop_12_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_12_prs1 = ldq_uop_12_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_prs1 = ldq_uop_12_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_12_prs2 = ldq_uop_12_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_prs2 = ldq_uop_12_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_12_prs3 = ldq_uop_12_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_prs3 = ldq_uop_12_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_12_ppred = ldq_uop_12_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_ppred = ldq_uop_12_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_prs1_busy; // @[lsu.scala:219:36] wire l_uop_12_prs1_busy = ldq_uop_12_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_prs1_busy = ldq_uop_12_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_prs2_busy; // @[lsu.scala:219:36] wire l_uop_12_prs2_busy = ldq_uop_12_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_prs2_busy = ldq_uop_12_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_prs3_busy; // @[lsu.scala:219:36] wire l_uop_12_prs3_busy = ldq_uop_12_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_prs3_busy = ldq_uop_12_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_ppred_busy; // @[lsu.scala:219:36] wire l_uop_12_ppred_busy = ldq_uop_12_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_ppred_busy = ldq_uop_12_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_12_stale_pdst = ldq_uop_12_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_stale_pdst = ldq_uop_12_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_exception; // @[lsu.scala:219:36] wire l_uop_12_exception = ldq_uop_12_exception; // @[lsu.scala:219:36, :1191:37] wire uop_29_exception = ldq_uop_12_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_12_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_12_exc_cause = ldq_uop_12_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_29_exc_cause = ldq_uop_12_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_12_mem_cmd = ldq_uop_12_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_mem_cmd = ldq_uop_12_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_12_mem_size = ldq_uop_12_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_mem_size = ldq_uop_12_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_mem_signed; // @[lsu.scala:219:36] wire l_uop_12_mem_signed = ldq_uop_12_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_29_mem_signed = ldq_uop_12_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_uses_ldq; // @[lsu.scala:219:36] wire l_uop_12_uses_ldq = ldq_uop_12_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_29_uses_ldq = ldq_uop_12_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_uses_stq; // @[lsu.scala:219:36] wire l_uop_12_uses_stq = ldq_uop_12_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_29_uses_stq = ldq_uop_12_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_unique; // @[lsu.scala:219:36] wire l_uop_12_is_unique = ldq_uop_12_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_unique = ldq_uop_12_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_12_flush_on_commit = ldq_uop_12_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_29_flush_on_commit = ldq_uop_12_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_12_csr_cmd = ldq_uop_12_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_csr_cmd = ldq_uop_12_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_12_ldst_is_rs1 = ldq_uop_12_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_29_ldst_is_rs1 = ldq_uop_12_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_12_ldst = ldq_uop_12_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_ldst = ldq_uop_12_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_12_lrs1 = ldq_uop_12_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_lrs1 = ldq_uop_12_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_12_lrs2 = ldq_uop_12_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_lrs2 = ldq_uop_12_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_12_lrs3 = ldq_uop_12_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_lrs3 = ldq_uop_12_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_12_dst_rtype = ldq_uop_12_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_dst_rtype = ldq_uop_12_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_12_lrs1_rtype = ldq_uop_12_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_lrs1_rtype = ldq_uop_12_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_12_lrs2_rtype = ldq_uop_12_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_lrs2_rtype = ldq_uop_12_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_frs3_en; // @[lsu.scala:219:36] wire l_uop_12_frs3_en = ldq_uop_12_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_29_frs3_en = ldq_uop_12_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fcn_dw; // @[lsu.scala:219:36] wire l_uop_12_fcn_dw = ldq_uop_12_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_29_fcn_dw = ldq_uop_12_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_12_fcn_op = ldq_uop_12_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_fcn_op = ldq_uop_12_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_val; // @[lsu.scala:219:36] wire l_uop_12_fp_val = ldq_uop_12_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_val = ldq_uop_12_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_12_fp_rm = ldq_uop_12_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_fp_rm = ldq_uop_12_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_12_fp_typ = ldq_uop_12_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_fp_typ = ldq_uop_12_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_12_xcpt_pf_if = ldq_uop_12_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_xcpt_pf_if = ldq_uop_12_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_12_xcpt_ae_if = ldq_uop_12_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_xcpt_ae_if = ldq_uop_12_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_12_xcpt_ma_if = ldq_uop_12_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_xcpt_ma_if = ldq_uop_12_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_12_bp_debug_if = ldq_uop_12_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_bp_debug_if = ldq_uop_12_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_12_bp_xcpt_if = ldq_uop_12_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_bp_xcpt_if = ldq_uop_12_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_12_debug_fsrc = ldq_uop_12_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_debug_fsrc = ldq_uop_12_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_12_debug_tsrc = ldq_uop_12_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_debug_tsrc = ldq_uop_12_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_13_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_13_inst = ldq_uop_13_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_30_inst = ldq_uop_13_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_13_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_13_debug_inst = ldq_uop_13_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_30_debug_inst = ldq_uop_13_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_rvc; // @[lsu.scala:219:36] wire l_uop_13_is_rvc = ldq_uop_13_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_rvc = ldq_uop_13_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_13_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_13_debug_pc = ldq_uop_13_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_30_debug_pc = ldq_uop_13_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_0; // @[lsu.scala:219:36] wire l_uop_13_iq_type_0 = ldq_uop_13_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_0 = ldq_uop_13_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_1; // @[lsu.scala:219:36] wire l_uop_13_iq_type_1 = ldq_uop_13_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_1 = ldq_uop_13_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_2; // @[lsu.scala:219:36] wire l_uop_13_iq_type_2 = ldq_uop_13_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_2 = ldq_uop_13_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_3; // @[lsu.scala:219:36] wire l_uop_13_iq_type_3 = ldq_uop_13_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_3 = ldq_uop_13_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_0; // @[lsu.scala:219:36] wire l_uop_13_fu_code_0 = ldq_uop_13_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_0 = ldq_uop_13_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_1; // @[lsu.scala:219:36] wire l_uop_13_fu_code_1 = ldq_uop_13_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_1 = ldq_uop_13_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_2; // @[lsu.scala:219:36] wire l_uop_13_fu_code_2 = ldq_uop_13_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_2 = ldq_uop_13_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_3; // @[lsu.scala:219:36] wire l_uop_13_fu_code_3 = ldq_uop_13_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_3 = ldq_uop_13_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_4; // @[lsu.scala:219:36] wire l_uop_13_fu_code_4 = ldq_uop_13_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_4 = ldq_uop_13_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_5; // @[lsu.scala:219:36] wire l_uop_13_fu_code_5 = ldq_uop_13_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_5 = ldq_uop_13_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_6; // @[lsu.scala:219:36] wire l_uop_13_fu_code_6 = ldq_uop_13_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_6 = ldq_uop_13_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_7; // @[lsu.scala:219:36] wire l_uop_13_fu_code_7 = ldq_uop_13_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_7 = ldq_uop_13_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_8; // @[lsu.scala:219:36] wire l_uop_13_fu_code_8 = ldq_uop_13_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_8 = ldq_uop_13_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_9; // @[lsu.scala:219:36] wire l_uop_13_fu_code_9 = ldq_uop_13_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_9 = ldq_uop_13_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_issued; // @[lsu.scala:219:36] wire l_uop_13_iw_issued = ldq_uop_13_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_issued = ldq_uop_13_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_13_iw_issued_partial_agen = ldq_uop_13_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_issued_partial_agen = ldq_uop_13_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_13_iw_issued_partial_dgen = ldq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_issued_partial_dgen = ldq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_13_iw_p1_speculative_child = ldq_uop_13_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_iw_p1_speculative_child = ldq_uop_13_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_13_iw_p2_speculative_child = ldq_uop_13_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_iw_p2_speculative_child = ldq_uop_13_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_13_iw_p1_bypass_hint = ldq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_p1_bypass_hint = ldq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_13_iw_p2_bypass_hint = ldq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_p2_bypass_hint = ldq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_13_iw_p3_bypass_hint = ldq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_p3_bypass_hint = ldq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_13_dis_col_sel = ldq_uop_13_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_dis_col_sel = ldq_uop_13_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_13_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_13_br_mask = ldq_uop_13_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_30_br_mask = ldq_uop_13_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_13_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_13_br_tag = ldq_uop_13_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_30_br_tag = ldq_uop_13_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_13_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_13_br_type = ldq_uop_13_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_30_br_type = ldq_uop_13_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_sfb; // @[lsu.scala:219:36] wire l_uop_13_is_sfb = ldq_uop_13_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_sfb = ldq_uop_13_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_fence; // @[lsu.scala:219:36] wire l_uop_13_is_fence = ldq_uop_13_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_fence = ldq_uop_13_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_fencei; // @[lsu.scala:219:36] wire l_uop_13_is_fencei = ldq_uop_13_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_fencei = ldq_uop_13_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_sfence; // @[lsu.scala:219:36] wire l_uop_13_is_sfence = ldq_uop_13_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_sfence = ldq_uop_13_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_amo; // @[lsu.scala:219:36] wire l_uop_13_is_amo = ldq_uop_13_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_amo = ldq_uop_13_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_eret; // @[lsu.scala:219:36] wire l_uop_13_is_eret = ldq_uop_13_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_eret = ldq_uop_13_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_13_is_sys_pc2epc = ldq_uop_13_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_sys_pc2epc = ldq_uop_13_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_rocc; // @[lsu.scala:219:36] wire l_uop_13_is_rocc = ldq_uop_13_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_rocc = ldq_uop_13_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_mov; // @[lsu.scala:219:36] wire l_uop_13_is_mov = ldq_uop_13_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_mov = ldq_uop_13_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_13_ftq_idx = ldq_uop_13_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_ftq_idx = ldq_uop_13_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_edge_inst; // @[lsu.scala:219:36] wire l_uop_13_edge_inst = ldq_uop_13_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_30_edge_inst = ldq_uop_13_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_13_pc_lob = ldq_uop_13_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_pc_lob = ldq_uop_13_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_taken; // @[lsu.scala:219:36] wire l_uop_13_taken = ldq_uop_13_taken; // @[lsu.scala:219:36, :1191:37] wire uop_30_taken = ldq_uop_13_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_imm_rename; // @[lsu.scala:219:36] wire l_uop_13_imm_rename = ldq_uop_13_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_30_imm_rename = ldq_uop_13_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_13_imm_sel = ldq_uop_13_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_imm_sel = ldq_uop_13_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_13_pimm = ldq_uop_13_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_pimm = ldq_uop_13_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_13_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_13_imm_packed = ldq_uop_13_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_30_imm_packed = ldq_uop_13_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_13_op1_sel = ldq_uop_13_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_op1_sel = ldq_uop_13_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_13_op2_sel = ldq_uop_13_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_op2_sel = ldq_uop_13_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ldst = ldq_uop_13_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ldst = ldq_uop_13_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_wen = ldq_uop_13_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_wen = ldq_uop_13_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ren1 = ldq_uop_13_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ren1 = ldq_uop_13_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ren2 = ldq_uop_13_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ren2 = ldq_uop_13_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ren3 = ldq_uop_13_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ren3 = ldq_uop_13_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_swap12 = ldq_uop_13_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_swap12 = ldq_uop_13_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_swap23 = ldq_uop_13_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_swap23 = ldq_uop_13_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_13_fp_ctrl_typeTagIn = ldq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_fp_ctrl_typeTagIn = ldq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_13_fp_ctrl_typeTagOut = ldq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_fp_ctrl_typeTagOut = ldq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_fromint = ldq_uop_13_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_fromint = ldq_uop_13_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_toint = ldq_uop_13_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_toint = ldq_uop_13_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_fastpipe = ldq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_fastpipe = ldq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_fma = ldq_uop_13_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_fma = ldq_uop_13_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_div = ldq_uop_13_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_div = ldq_uop_13_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_sqrt = ldq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_sqrt = ldq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_wflags = ldq_uop_13_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_wflags = ldq_uop_13_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_vec = ldq_uop_13_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_vec = ldq_uop_13_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_13_rob_idx = ldq_uop_13_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_rob_idx = ldq_uop_13_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_13_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_13_ldq_idx = ldq_uop_13_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_30_ldq_idx = ldq_uop_13_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_13_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_13_stq_idx = ldq_uop_13_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_30_stq_idx = ldq_uop_13_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_13_rxq_idx = ldq_uop_13_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_rxq_idx = ldq_uop_13_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_13_pdst = ldq_uop_13_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_pdst = ldq_uop_13_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_13_prs1 = ldq_uop_13_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_prs1 = ldq_uop_13_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_13_prs2 = ldq_uop_13_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_prs2 = ldq_uop_13_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_13_prs3 = ldq_uop_13_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_prs3 = ldq_uop_13_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_13_ppred = ldq_uop_13_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_ppred = ldq_uop_13_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_prs1_busy; // @[lsu.scala:219:36] wire l_uop_13_prs1_busy = ldq_uop_13_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_prs1_busy = ldq_uop_13_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_prs2_busy; // @[lsu.scala:219:36] wire l_uop_13_prs2_busy = ldq_uop_13_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_prs2_busy = ldq_uop_13_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_prs3_busy; // @[lsu.scala:219:36] wire l_uop_13_prs3_busy = ldq_uop_13_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_prs3_busy = ldq_uop_13_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_ppred_busy; // @[lsu.scala:219:36] wire l_uop_13_ppred_busy = ldq_uop_13_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_ppred_busy = ldq_uop_13_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_13_stale_pdst = ldq_uop_13_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_stale_pdst = ldq_uop_13_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_exception; // @[lsu.scala:219:36] wire l_uop_13_exception = ldq_uop_13_exception; // @[lsu.scala:219:36, :1191:37] wire uop_30_exception = ldq_uop_13_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_13_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_13_exc_cause = ldq_uop_13_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_30_exc_cause = ldq_uop_13_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_13_mem_cmd = ldq_uop_13_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_mem_cmd = ldq_uop_13_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_13_mem_size = ldq_uop_13_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_mem_size = ldq_uop_13_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_mem_signed; // @[lsu.scala:219:36] wire l_uop_13_mem_signed = ldq_uop_13_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_30_mem_signed = ldq_uop_13_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_uses_ldq; // @[lsu.scala:219:36] wire l_uop_13_uses_ldq = ldq_uop_13_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_30_uses_ldq = ldq_uop_13_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_uses_stq; // @[lsu.scala:219:36] wire l_uop_13_uses_stq = ldq_uop_13_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_30_uses_stq = ldq_uop_13_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_unique; // @[lsu.scala:219:36] wire l_uop_13_is_unique = ldq_uop_13_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_unique = ldq_uop_13_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_13_flush_on_commit = ldq_uop_13_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_30_flush_on_commit = ldq_uop_13_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_13_csr_cmd = ldq_uop_13_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_csr_cmd = ldq_uop_13_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_13_ldst_is_rs1 = ldq_uop_13_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_30_ldst_is_rs1 = ldq_uop_13_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_13_ldst = ldq_uop_13_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_ldst = ldq_uop_13_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_13_lrs1 = ldq_uop_13_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_lrs1 = ldq_uop_13_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_13_lrs2 = ldq_uop_13_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_lrs2 = ldq_uop_13_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_13_lrs3 = ldq_uop_13_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_lrs3 = ldq_uop_13_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_13_dst_rtype = ldq_uop_13_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_dst_rtype = ldq_uop_13_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_13_lrs1_rtype = ldq_uop_13_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_lrs1_rtype = ldq_uop_13_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_13_lrs2_rtype = ldq_uop_13_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_lrs2_rtype = ldq_uop_13_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_frs3_en; // @[lsu.scala:219:36] wire l_uop_13_frs3_en = ldq_uop_13_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_30_frs3_en = ldq_uop_13_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fcn_dw; // @[lsu.scala:219:36] wire l_uop_13_fcn_dw = ldq_uop_13_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_30_fcn_dw = ldq_uop_13_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_13_fcn_op = ldq_uop_13_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_fcn_op = ldq_uop_13_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_val; // @[lsu.scala:219:36] wire l_uop_13_fp_val = ldq_uop_13_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_val = ldq_uop_13_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_13_fp_rm = ldq_uop_13_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_fp_rm = ldq_uop_13_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_13_fp_typ = ldq_uop_13_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_fp_typ = ldq_uop_13_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_13_xcpt_pf_if = ldq_uop_13_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_xcpt_pf_if = ldq_uop_13_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_13_xcpt_ae_if = ldq_uop_13_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_xcpt_ae_if = ldq_uop_13_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_13_xcpt_ma_if = ldq_uop_13_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_xcpt_ma_if = ldq_uop_13_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_13_bp_debug_if = ldq_uop_13_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_bp_debug_if = ldq_uop_13_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_13_bp_xcpt_if = ldq_uop_13_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_bp_xcpt_if = ldq_uop_13_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_13_debug_fsrc = ldq_uop_13_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_debug_fsrc = ldq_uop_13_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_13_debug_tsrc = ldq_uop_13_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_debug_tsrc = ldq_uop_13_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_14_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_14_inst = ldq_uop_14_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_31_inst = ldq_uop_14_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_14_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_14_debug_inst = ldq_uop_14_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_31_debug_inst = ldq_uop_14_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_rvc; // @[lsu.scala:219:36] wire l_uop_14_is_rvc = ldq_uop_14_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_rvc = ldq_uop_14_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_14_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_14_debug_pc = ldq_uop_14_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_31_debug_pc = ldq_uop_14_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_0; // @[lsu.scala:219:36] wire l_uop_14_iq_type_0 = ldq_uop_14_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_0 = ldq_uop_14_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_1; // @[lsu.scala:219:36] wire l_uop_14_iq_type_1 = ldq_uop_14_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_1 = ldq_uop_14_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_2; // @[lsu.scala:219:36] wire l_uop_14_iq_type_2 = ldq_uop_14_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_2 = ldq_uop_14_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_3; // @[lsu.scala:219:36] wire l_uop_14_iq_type_3 = ldq_uop_14_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_3 = ldq_uop_14_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_0; // @[lsu.scala:219:36] wire l_uop_14_fu_code_0 = ldq_uop_14_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_0 = ldq_uop_14_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_1; // @[lsu.scala:219:36] wire l_uop_14_fu_code_1 = ldq_uop_14_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_1 = ldq_uop_14_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_2; // @[lsu.scala:219:36] wire l_uop_14_fu_code_2 = ldq_uop_14_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_2 = ldq_uop_14_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_3; // @[lsu.scala:219:36] wire l_uop_14_fu_code_3 = ldq_uop_14_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_3 = ldq_uop_14_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_4; // @[lsu.scala:219:36] wire l_uop_14_fu_code_4 = ldq_uop_14_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_4 = ldq_uop_14_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_5; // @[lsu.scala:219:36] wire l_uop_14_fu_code_5 = ldq_uop_14_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_5 = ldq_uop_14_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_6; // @[lsu.scala:219:36] wire l_uop_14_fu_code_6 = ldq_uop_14_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_6 = ldq_uop_14_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_7; // @[lsu.scala:219:36] wire l_uop_14_fu_code_7 = ldq_uop_14_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_7 = ldq_uop_14_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_8; // @[lsu.scala:219:36] wire l_uop_14_fu_code_8 = ldq_uop_14_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_8 = ldq_uop_14_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_9; // @[lsu.scala:219:36] wire l_uop_14_fu_code_9 = ldq_uop_14_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_9 = ldq_uop_14_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_issued; // @[lsu.scala:219:36] wire l_uop_14_iw_issued = ldq_uop_14_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_issued = ldq_uop_14_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_14_iw_issued_partial_agen = ldq_uop_14_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_issued_partial_agen = ldq_uop_14_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_14_iw_issued_partial_dgen = ldq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_issued_partial_dgen = ldq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_14_iw_p1_speculative_child = ldq_uop_14_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_iw_p1_speculative_child = ldq_uop_14_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_14_iw_p2_speculative_child = ldq_uop_14_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_iw_p2_speculative_child = ldq_uop_14_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_14_iw_p1_bypass_hint = ldq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_p1_bypass_hint = ldq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_14_iw_p2_bypass_hint = ldq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_p2_bypass_hint = ldq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_14_iw_p3_bypass_hint = ldq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_p3_bypass_hint = ldq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_14_dis_col_sel = ldq_uop_14_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_dis_col_sel = ldq_uop_14_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_14_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_14_br_mask = ldq_uop_14_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_31_br_mask = ldq_uop_14_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_14_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_14_br_tag = ldq_uop_14_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_31_br_tag = ldq_uop_14_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_14_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_14_br_type = ldq_uop_14_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_31_br_type = ldq_uop_14_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_sfb; // @[lsu.scala:219:36] wire l_uop_14_is_sfb = ldq_uop_14_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_sfb = ldq_uop_14_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_fence; // @[lsu.scala:219:36] wire l_uop_14_is_fence = ldq_uop_14_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_fence = ldq_uop_14_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_fencei; // @[lsu.scala:219:36] wire l_uop_14_is_fencei = ldq_uop_14_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_fencei = ldq_uop_14_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_sfence; // @[lsu.scala:219:36] wire l_uop_14_is_sfence = ldq_uop_14_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_sfence = ldq_uop_14_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_amo; // @[lsu.scala:219:36] wire l_uop_14_is_amo = ldq_uop_14_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_amo = ldq_uop_14_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_eret; // @[lsu.scala:219:36] wire l_uop_14_is_eret = ldq_uop_14_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_eret = ldq_uop_14_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_14_is_sys_pc2epc = ldq_uop_14_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_sys_pc2epc = ldq_uop_14_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_rocc; // @[lsu.scala:219:36] wire l_uop_14_is_rocc = ldq_uop_14_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_rocc = ldq_uop_14_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_mov; // @[lsu.scala:219:36] wire l_uop_14_is_mov = ldq_uop_14_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_mov = ldq_uop_14_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_14_ftq_idx = ldq_uop_14_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_ftq_idx = ldq_uop_14_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_edge_inst; // @[lsu.scala:219:36] wire l_uop_14_edge_inst = ldq_uop_14_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_31_edge_inst = ldq_uop_14_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_14_pc_lob = ldq_uop_14_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_pc_lob = ldq_uop_14_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_taken; // @[lsu.scala:219:36] wire l_uop_14_taken = ldq_uop_14_taken; // @[lsu.scala:219:36, :1191:37] wire uop_31_taken = ldq_uop_14_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_imm_rename; // @[lsu.scala:219:36] wire l_uop_14_imm_rename = ldq_uop_14_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_31_imm_rename = ldq_uop_14_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_14_imm_sel = ldq_uop_14_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_imm_sel = ldq_uop_14_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_14_pimm = ldq_uop_14_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_pimm = ldq_uop_14_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_14_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_14_imm_packed = ldq_uop_14_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_31_imm_packed = ldq_uop_14_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_14_op1_sel = ldq_uop_14_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_op1_sel = ldq_uop_14_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_14_op2_sel = ldq_uop_14_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_op2_sel = ldq_uop_14_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ldst = ldq_uop_14_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ldst = ldq_uop_14_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_wen = ldq_uop_14_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_wen = ldq_uop_14_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ren1 = ldq_uop_14_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ren1 = ldq_uop_14_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ren2 = ldq_uop_14_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ren2 = ldq_uop_14_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ren3 = ldq_uop_14_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ren3 = ldq_uop_14_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_swap12 = ldq_uop_14_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_swap12 = ldq_uop_14_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_swap23 = ldq_uop_14_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_swap23 = ldq_uop_14_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_14_fp_ctrl_typeTagIn = ldq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_fp_ctrl_typeTagIn = ldq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_14_fp_ctrl_typeTagOut = ldq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_fp_ctrl_typeTagOut = ldq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_fromint = ldq_uop_14_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_fromint = ldq_uop_14_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_toint = ldq_uop_14_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_toint = ldq_uop_14_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_fastpipe = ldq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_fastpipe = ldq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_fma = ldq_uop_14_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_fma = ldq_uop_14_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_div = ldq_uop_14_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_div = ldq_uop_14_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_sqrt = ldq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_sqrt = ldq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_wflags = ldq_uop_14_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_wflags = ldq_uop_14_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_vec = ldq_uop_14_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_vec = ldq_uop_14_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_14_rob_idx = ldq_uop_14_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_rob_idx = ldq_uop_14_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_14_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_14_ldq_idx = ldq_uop_14_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_31_ldq_idx = ldq_uop_14_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_14_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_14_stq_idx = ldq_uop_14_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_31_stq_idx = ldq_uop_14_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_14_rxq_idx = ldq_uop_14_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_rxq_idx = ldq_uop_14_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_14_pdst = ldq_uop_14_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_pdst = ldq_uop_14_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_14_prs1 = ldq_uop_14_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_prs1 = ldq_uop_14_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_14_prs2 = ldq_uop_14_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_prs2 = ldq_uop_14_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_14_prs3 = ldq_uop_14_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_prs3 = ldq_uop_14_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_14_ppred = ldq_uop_14_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_ppred = ldq_uop_14_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_prs1_busy; // @[lsu.scala:219:36] wire l_uop_14_prs1_busy = ldq_uop_14_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_prs1_busy = ldq_uop_14_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_prs2_busy; // @[lsu.scala:219:36] wire l_uop_14_prs2_busy = ldq_uop_14_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_prs2_busy = ldq_uop_14_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_prs3_busy; // @[lsu.scala:219:36] wire l_uop_14_prs3_busy = ldq_uop_14_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_prs3_busy = ldq_uop_14_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_ppred_busy; // @[lsu.scala:219:36] wire l_uop_14_ppred_busy = ldq_uop_14_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_ppred_busy = ldq_uop_14_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_14_stale_pdst = ldq_uop_14_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_stale_pdst = ldq_uop_14_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_exception; // @[lsu.scala:219:36] wire l_uop_14_exception = ldq_uop_14_exception; // @[lsu.scala:219:36, :1191:37] wire uop_31_exception = ldq_uop_14_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_14_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_14_exc_cause = ldq_uop_14_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_31_exc_cause = ldq_uop_14_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_14_mem_cmd = ldq_uop_14_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_mem_cmd = ldq_uop_14_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_14_mem_size = ldq_uop_14_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_mem_size = ldq_uop_14_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_mem_signed; // @[lsu.scala:219:36] wire l_uop_14_mem_signed = ldq_uop_14_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_31_mem_signed = ldq_uop_14_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_uses_ldq; // @[lsu.scala:219:36] wire l_uop_14_uses_ldq = ldq_uop_14_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_31_uses_ldq = ldq_uop_14_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_uses_stq; // @[lsu.scala:219:36] wire l_uop_14_uses_stq = ldq_uop_14_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_31_uses_stq = ldq_uop_14_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_unique; // @[lsu.scala:219:36] wire l_uop_14_is_unique = ldq_uop_14_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_unique = ldq_uop_14_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_14_flush_on_commit = ldq_uop_14_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_31_flush_on_commit = ldq_uop_14_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_14_csr_cmd = ldq_uop_14_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_csr_cmd = ldq_uop_14_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_14_ldst_is_rs1 = ldq_uop_14_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_31_ldst_is_rs1 = ldq_uop_14_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_14_ldst = ldq_uop_14_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_ldst = ldq_uop_14_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_14_lrs1 = ldq_uop_14_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_lrs1 = ldq_uop_14_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_14_lrs2 = ldq_uop_14_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_lrs2 = ldq_uop_14_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_14_lrs3 = ldq_uop_14_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_lrs3 = ldq_uop_14_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_14_dst_rtype = ldq_uop_14_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_dst_rtype = ldq_uop_14_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_14_lrs1_rtype = ldq_uop_14_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_lrs1_rtype = ldq_uop_14_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_14_lrs2_rtype = ldq_uop_14_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_lrs2_rtype = ldq_uop_14_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_frs3_en; // @[lsu.scala:219:36] wire l_uop_14_frs3_en = ldq_uop_14_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_31_frs3_en = ldq_uop_14_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fcn_dw; // @[lsu.scala:219:36] wire l_uop_14_fcn_dw = ldq_uop_14_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_31_fcn_dw = ldq_uop_14_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_14_fcn_op = ldq_uop_14_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_fcn_op = ldq_uop_14_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_val; // @[lsu.scala:219:36] wire l_uop_14_fp_val = ldq_uop_14_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_val = ldq_uop_14_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_14_fp_rm = ldq_uop_14_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_fp_rm = ldq_uop_14_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_14_fp_typ = ldq_uop_14_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_fp_typ = ldq_uop_14_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_14_xcpt_pf_if = ldq_uop_14_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_xcpt_pf_if = ldq_uop_14_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_14_xcpt_ae_if = ldq_uop_14_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_xcpt_ae_if = ldq_uop_14_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_14_xcpt_ma_if = ldq_uop_14_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_xcpt_ma_if = ldq_uop_14_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_14_bp_debug_if = ldq_uop_14_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_bp_debug_if = ldq_uop_14_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_14_bp_xcpt_if = ldq_uop_14_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_bp_xcpt_if = ldq_uop_14_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_14_debug_fsrc = ldq_uop_14_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_debug_fsrc = ldq_uop_14_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_14_debug_tsrc = ldq_uop_14_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_debug_tsrc = ldq_uop_14_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_15_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_15_inst = ldq_uop_15_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_32_inst = ldq_uop_15_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_15_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_15_debug_inst = ldq_uop_15_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_32_debug_inst = ldq_uop_15_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_rvc; // @[lsu.scala:219:36] wire l_uop_15_is_rvc = ldq_uop_15_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_rvc = ldq_uop_15_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_15_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_15_debug_pc = ldq_uop_15_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_32_debug_pc = ldq_uop_15_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_0; // @[lsu.scala:219:36] wire l_uop_15_iq_type_0 = ldq_uop_15_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_0 = ldq_uop_15_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_1; // @[lsu.scala:219:36] wire l_uop_15_iq_type_1 = ldq_uop_15_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_1 = ldq_uop_15_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_2; // @[lsu.scala:219:36] wire l_uop_15_iq_type_2 = ldq_uop_15_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_2 = ldq_uop_15_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_3; // @[lsu.scala:219:36] wire l_uop_15_iq_type_3 = ldq_uop_15_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_3 = ldq_uop_15_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_0; // @[lsu.scala:219:36] wire l_uop_15_fu_code_0 = ldq_uop_15_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_0 = ldq_uop_15_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_1; // @[lsu.scala:219:36] wire l_uop_15_fu_code_1 = ldq_uop_15_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_1 = ldq_uop_15_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_2; // @[lsu.scala:219:36] wire l_uop_15_fu_code_2 = ldq_uop_15_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_2 = ldq_uop_15_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_3; // @[lsu.scala:219:36] wire l_uop_15_fu_code_3 = ldq_uop_15_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_3 = ldq_uop_15_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_4; // @[lsu.scala:219:36] wire l_uop_15_fu_code_4 = ldq_uop_15_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_4 = ldq_uop_15_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_5; // @[lsu.scala:219:36] wire l_uop_15_fu_code_5 = ldq_uop_15_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_5 = ldq_uop_15_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_6; // @[lsu.scala:219:36] wire l_uop_15_fu_code_6 = ldq_uop_15_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_6 = ldq_uop_15_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_7; // @[lsu.scala:219:36] wire l_uop_15_fu_code_7 = ldq_uop_15_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_7 = ldq_uop_15_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_8; // @[lsu.scala:219:36] wire l_uop_15_fu_code_8 = ldq_uop_15_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_8 = ldq_uop_15_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_9; // @[lsu.scala:219:36] wire l_uop_15_fu_code_9 = ldq_uop_15_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_9 = ldq_uop_15_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_issued; // @[lsu.scala:219:36] wire l_uop_15_iw_issued = ldq_uop_15_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_issued = ldq_uop_15_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_15_iw_issued_partial_agen = ldq_uop_15_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_issued_partial_agen = ldq_uop_15_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_15_iw_issued_partial_dgen = ldq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_issued_partial_dgen = ldq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_15_iw_p1_speculative_child = ldq_uop_15_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_iw_p1_speculative_child = ldq_uop_15_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_15_iw_p2_speculative_child = ldq_uop_15_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_iw_p2_speculative_child = ldq_uop_15_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_15_iw_p1_bypass_hint = ldq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_p1_bypass_hint = ldq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_15_iw_p2_bypass_hint = ldq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_p2_bypass_hint = ldq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_15_iw_p3_bypass_hint = ldq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_p3_bypass_hint = ldq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_15_dis_col_sel = ldq_uop_15_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_dis_col_sel = ldq_uop_15_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_15_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_15_br_mask = ldq_uop_15_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_32_br_mask = ldq_uop_15_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_15_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_15_br_tag = ldq_uop_15_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_32_br_tag = ldq_uop_15_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_15_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_15_br_type = ldq_uop_15_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_32_br_type = ldq_uop_15_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_sfb; // @[lsu.scala:219:36] wire l_uop_15_is_sfb = ldq_uop_15_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_sfb = ldq_uop_15_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_fence; // @[lsu.scala:219:36] wire l_uop_15_is_fence = ldq_uop_15_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_fence = ldq_uop_15_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_fencei; // @[lsu.scala:219:36] wire l_uop_15_is_fencei = ldq_uop_15_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_fencei = ldq_uop_15_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_sfence; // @[lsu.scala:219:36] wire l_uop_15_is_sfence = ldq_uop_15_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_sfence = ldq_uop_15_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_amo; // @[lsu.scala:219:36] wire l_uop_15_is_amo = ldq_uop_15_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_amo = ldq_uop_15_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_eret; // @[lsu.scala:219:36] wire l_uop_15_is_eret = ldq_uop_15_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_eret = ldq_uop_15_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_15_is_sys_pc2epc = ldq_uop_15_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_sys_pc2epc = ldq_uop_15_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_rocc; // @[lsu.scala:219:36] wire l_uop_15_is_rocc = ldq_uop_15_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_rocc = ldq_uop_15_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_mov; // @[lsu.scala:219:36] wire l_uop_15_is_mov = ldq_uop_15_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_mov = ldq_uop_15_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_15_ftq_idx = ldq_uop_15_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_ftq_idx = ldq_uop_15_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_edge_inst; // @[lsu.scala:219:36] wire l_uop_15_edge_inst = ldq_uop_15_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_32_edge_inst = ldq_uop_15_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_15_pc_lob = ldq_uop_15_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_pc_lob = ldq_uop_15_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_taken; // @[lsu.scala:219:36] wire l_uop_15_taken = ldq_uop_15_taken; // @[lsu.scala:219:36, :1191:37] wire uop_32_taken = ldq_uop_15_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_imm_rename; // @[lsu.scala:219:36] wire l_uop_15_imm_rename = ldq_uop_15_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_32_imm_rename = ldq_uop_15_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_15_imm_sel = ldq_uop_15_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_imm_sel = ldq_uop_15_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_15_pimm = ldq_uop_15_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_pimm = ldq_uop_15_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_15_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_15_imm_packed = ldq_uop_15_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_32_imm_packed = ldq_uop_15_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_15_op1_sel = ldq_uop_15_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_op1_sel = ldq_uop_15_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_15_op2_sel = ldq_uop_15_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_op2_sel = ldq_uop_15_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ldst = ldq_uop_15_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ldst = ldq_uop_15_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_wen = ldq_uop_15_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_wen = ldq_uop_15_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ren1 = ldq_uop_15_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ren1 = ldq_uop_15_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ren2 = ldq_uop_15_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ren2 = ldq_uop_15_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ren3 = ldq_uop_15_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ren3 = ldq_uop_15_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_swap12 = ldq_uop_15_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_swap12 = ldq_uop_15_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_swap23 = ldq_uop_15_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_swap23 = ldq_uop_15_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_15_fp_ctrl_typeTagIn = ldq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_fp_ctrl_typeTagIn = ldq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_15_fp_ctrl_typeTagOut = ldq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_fp_ctrl_typeTagOut = ldq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_fromint = ldq_uop_15_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_fromint = ldq_uop_15_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_toint = ldq_uop_15_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_toint = ldq_uop_15_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_fastpipe = ldq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_fastpipe = ldq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_fma = ldq_uop_15_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_fma = ldq_uop_15_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_div = ldq_uop_15_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_div = ldq_uop_15_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_sqrt = ldq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_sqrt = ldq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_wflags = ldq_uop_15_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_wflags = ldq_uop_15_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_vec = ldq_uop_15_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_vec = ldq_uop_15_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_15_rob_idx = ldq_uop_15_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_rob_idx = ldq_uop_15_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_15_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_15_ldq_idx = ldq_uop_15_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_32_ldq_idx = ldq_uop_15_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_15_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_15_stq_idx = ldq_uop_15_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_32_stq_idx = ldq_uop_15_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_15_rxq_idx = ldq_uop_15_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_rxq_idx = ldq_uop_15_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_15_pdst = ldq_uop_15_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_pdst = ldq_uop_15_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_15_prs1 = ldq_uop_15_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_prs1 = ldq_uop_15_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_15_prs2 = ldq_uop_15_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_prs2 = ldq_uop_15_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_15_prs3 = ldq_uop_15_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_prs3 = ldq_uop_15_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_15_ppred = ldq_uop_15_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_ppred = ldq_uop_15_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_prs1_busy; // @[lsu.scala:219:36] wire l_uop_15_prs1_busy = ldq_uop_15_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_prs1_busy = ldq_uop_15_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_prs2_busy; // @[lsu.scala:219:36] wire l_uop_15_prs2_busy = ldq_uop_15_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_prs2_busy = ldq_uop_15_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_prs3_busy; // @[lsu.scala:219:36] wire l_uop_15_prs3_busy = ldq_uop_15_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_prs3_busy = ldq_uop_15_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_ppred_busy; // @[lsu.scala:219:36] wire l_uop_15_ppred_busy = ldq_uop_15_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_ppred_busy = ldq_uop_15_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_15_stale_pdst = ldq_uop_15_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_stale_pdst = ldq_uop_15_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_exception; // @[lsu.scala:219:36] wire l_uop_15_exception = ldq_uop_15_exception; // @[lsu.scala:219:36, :1191:37] wire uop_32_exception = ldq_uop_15_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_15_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_15_exc_cause = ldq_uop_15_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_32_exc_cause = ldq_uop_15_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_15_mem_cmd = ldq_uop_15_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_mem_cmd = ldq_uop_15_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_15_mem_size = ldq_uop_15_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_mem_size = ldq_uop_15_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_mem_signed; // @[lsu.scala:219:36] wire l_uop_15_mem_signed = ldq_uop_15_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_32_mem_signed = ldq_uop_15_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_uses_ldq; // @[lsu.scala:219:36] wire l_uop_15_uses_ldq = ldq_uop_15_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_32_uses_ldq = ldq_uop_15_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_uses_stq; // @[lsu.scala:219:36] wire l_uop_15_uses_stq = ldq_uop_15_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_32_uses_stq = ldq_uop_15_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_unique; // @[lsu.scala:219:36] wire l_uop_15_is_unique = ldq_uop_15_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_unique = ldq_uop_15_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_15_flush_on_commit = ldq_uop_15_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_32_flush_on_commit = ldq_uop_15_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_15_csr_cmd = ldq_uop_15_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_csr_cmd = ldq_uop_15_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_15_ldst_is_rs1 = ldq_uop_15_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_32_ldst_is_rs1 = ldq_uop_15_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_15_ldst = ldq_uop_15_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_ldst = ldq_uop_15_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_15_lrs1 = ldq_uop_15_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_lrs1 = ldq_uop_15_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_15_lrs2 = ldq_uop_15_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_lrs2 = ldq_uop_15_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_15_lrs3 = ldq_uop_15_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_lrs3 = ldq_uop_15_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_15_dst_rtype = ldq_uop_15_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_dst_rtype = ldq_uop_15_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_15_lrs1_rtype = ldq_uop_15_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_lrs1_rtype = ldq_uop_15_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_15_lrs2_rtype = ldq_uop_15_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_lrs2_rtype = ldq_uop_15_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_frs3_en; // @[lsu.scala:219:36] wire l_uop_15_frs3_en = ldq_uop_15_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_32_frs3_en = ldq_uop_15_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fcn_dw; // @[lsu.scala:219:36] wire l_uop_15_fcn_dw = ldq_uop_15_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_32_fcn_dw = ldq_uop_15_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_15_fcn_op = ldq_uop_15_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_fcn_op = ldq_uop_15_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_val; // @[lsu.scala:219:36] wire l_uop_15_fp_val = ldq_uop_15_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_val = ldq_uop_15_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_15_fp_rm = ldq_uop_15_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_fp_rm = ldq_uop_15_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_15_fp_typ = ldq_uop_15_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_fp_typ = ldq_uop_15_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_15_xcpt_pf_if = ldq_uop_15_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_xcpt_pf_if = ldq_uop_15_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_15_xcpt_ae_if = ldq_uop_15_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_xcpt_ae_if = ldq_uop_15_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_15_xcpt_ma_if = ldq_uop_15_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_xcpt_ma_if = ldq_uop_15_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_15_bp_debug_if = ldq_uop_15_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_bp_debug_if = ldq_uop_15_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_15_bp_xcpt_if = ldq_uop_15_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_bp_xcpt_if = ldq_uop_15_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_15_debug_fsrc = ldq_uop_15_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_debug_fsrc = ldq_uop_15_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_15_debug_tsrc = ldq_uop_15_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_debug_tsrc = ldq_uop_15_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg ldq_addr_0_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_0_bits; // @[lsu.scala:220:36] reg ldq_addr_1_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_1_bits; // @[lsu.scala:220:36] reg ldq_addr_2_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_2_bits; // @[lsu.scala:220:36] reg ldq_addr_3_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_3_bits; // @[lsu.scala:220:36] reg ldq_addr_4_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_4_bits; // @[lsu.scala:220:36] reg ldq_addr_5_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_5_bits; // @[lsu.scala:220:36] reg ldq_addr_6_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_6_bits; // @[lsu.scala:220:36] reg ldq_addr_7_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_7_bits; // @[lsu.scala:220:36] reg ldq_addr_8_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_8_bits; // @[lsu.scala:220:36] reg ldq_addr_9_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_9_bits; // @[lsu.scala:220:36] reg ldq_addr_10_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_10_bits; // @[lsu.scala:220:36] reg ldq_addr_11_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_11_bits; // @[lsu.scala:220:36] reg ldq_addr_12_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_12_bits; // @[lsu.scala:220:36] reg ldq_addr_13_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_13_bits; // @[lsu.scala:220:36] reg ldq_addr_14_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_14_bits; // @[lsu.scala:220:36] reg ldq_addr_15_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_15_bits; // @[lsu.scala:220:36] reg ldq_addr_is_virtual_0; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_1; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_2; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_3; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_4; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_5; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_6; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_7; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_8; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_9; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_10; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_11; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_12; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_13; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_14; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_15; // @[lsu.scala:221:36] reg ldq_addr_is_uncacheable_0; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_1; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_2; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_3; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_4; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_5; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_6; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_7; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_8; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_9; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_10; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_11; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_12; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_13; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_14; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_15; // @[lsu.scala:222:36] reg ldq_executed_0; // @[lsu.scala:223:36] reg ldq_executed_1; // @[lsu.scala:223:36] reg ldq_executed_2; // @[lsu.scala:223:36] reg ldq_executed_3; // @[lsu.scala:223:36] reg ldq_executed_4; // @[lsu.scala:223:36] reg ldq_executed_5; // @[lsu.scala:223:36] reg ldq_executed_6; // @[lsu.scala:223:36] reg ldq_executed_7; // @[lsu.scala:223:36] reg ldq_executed_8; // @[lsu.scala:223:36] reg ldq_executed_9; // @[lsu.scala:223:36] reg ldq_executed_10; // @[lsu.scala:223:36] reg ldq_executed_11; // @[lsu.scala:223:36] reg ldq_executed_12; // @[lsu.scala:223:36] reg ldq_executed_13; // @[lsu.scala:223:36] reg ldq_executed_14; // @[lsu.scala:223:36] reg ldq_executed_15; // @[lsu.scala:223:36] reg ldq_succeeded_0; // @[lsu.scala:224:36] reg ldq_succeeded_1; // @[lsu.scala:224:36] reg ldq_succeeded_2; // @[lsu.scala:224:36] reg ldq_succeeded_3; // @[lsu.scala:224:36] reg ldq_succeeded_4; // @[lsu.scala:224:36] reg ldq_succeeded_5; // @[lsu.scala:224:36] reg ldq_succeeded_6; // @[lsu.scala:224:36] reg ldq_succeeded_7; // @[lsu.scala:224:36] reg ldq_succeeded_8; // @[lsu.scala:224:36] reg ldq_succeeded_9; // @[lsu.scala:224:36] reg ldq_succeeded_10; // @[lsu.scala:224:36] reg ldq_succeeded_11; // @[lsu.scala:224:36] reg ldq_succeeded_12; // @[lsu.scala:224:36] reg ldq_succeeded_13; // @[lsu.scala:224:36] reg ldq_succeeded_14; // @[lsu.scala:224:36] reg ldq_succeeded_15; // @[lsu.scala:224:36] reg ldq_order_fail_0; // @[lsu.scala:225:36] reg ldq_order_fail_1; // @[lsu.scala:225:36] reg ldq_order_fail_2; // @[lsu.scala:225:36] reg ldq_order_fail_3; // @[lsu.scala:225:36] reg ldq_order_fail_4; // @[lsu.scala:225:36] reg ldq_order_fail_5; // @[lsu.scala:225:36] reg ldq_order_fail_6; // @[lsu.scala:225:36] reg ldq_order_fail_7; // @[lsu.scala:225:36] reg ldq_order_fail_8; // @[lsu.scala:225:36] reg ldq_order_fail_9; // @[lsu.scala:225:36] reg ldq_order_fail_10; // @[lsu.scala:225:36] reg ldq_order_fail_11; // @[lsu.scala:225:36] reg ldq_order_fail_12; // @[lsu.scala:225:36] reg ldq_order_fail_13; // @[lsu.scala:225:36] reg ldq_order_fail_14; // @[lsu.scala:225:36] reg ldq_order_fail_15; // @[lsu.scala:225:36] reg ldq_observed_0; // @[lsu.scala:226:36] reg ldq_observed_1; // @[lsu.scala:226:36] reg ldq_observed_2; // @[lsu.scala:226:36] reg ldq_observed_3; // @[lsu.scala:226:36] reg ldq_observed_4; // @[lsu.scala:226:36] reg ldq_observed_5; // @[lsu.scala:226:36] reg ldq_observed_6; // @[lsu.scala:226:36] reg ldq_observed_7; // @[lsu.scala:226:36] reg ldq_observed_8; // @[lsu.scala:226:36] reg ldq_observed_9; // @[lsu.scala:226:36] reg ldq_observed_10; // @[lsu.scala:226:36] reg ldq_observed_11; // @[lsu.scala:226:36] reg ldq_observed_12; // @[lsu.scala:226:36] reg ldq_observed_13; // @[lsu.scala:226:36] reg ldq_observed_14; // @[lsu.scala:226:36] reg ldq_observed_15; // @[lsu.scala:226:36] reg [15:0] ldq_st_dep_mask_0; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_1; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_2; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_3; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_4; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_5; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_6; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_7; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_8; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_9; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_10; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_11; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_12; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_13; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_14; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_15; // @[lsu.scala:227:36] reg [7:0] ldq_ld_byte_mask_0; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_1; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_2; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_3; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_4; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_5; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_6; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_7; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_8; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_9; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_10; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_11; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_12; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_13; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_14; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_15; // @[lsu.scala:228:36] reg ldq_forward_std_val_0; // @[lsu.scala:229:36] reg ldq_forward_std_val_1; // @[lsu.scala:229:36] reg ldq_forward_std_val_2; // @[lsu.scala:229:36] reg ldq_forward_std_val_3; // @[lsu.scala:229:36] reg ldq_forward_std_val_4; // @[lsu.scala:229:36] reg ldq_forward_std_val_5; // @[lsu.scala:229:36] reg ldq_forward_std_val_6; // @[lsu.scala:229:36] reg ldq_forward_std_val_7; // @[lsu.scala:229:36] reg ldq_forward_std_val_8; // @[lsu.scala:229:36] reg ldq_forward_std_val_9; // @[lsu.scala:229:36] reg ldq_forward_std_val_10; // @[lsu.scala:229:36] reg ldq_forward_std_val_11; // @[lsu.scala:229:36] reg ldq_forward_std_val_12; // @[lsu.scala:229:36] reg ldq_forward_std_val_13; // @[lsu.scala:229:36] reg ldq_forward_std_val_14; // @[lsu.scala:229:36] reg ldq_forward_std_val_15; // @[lsu.scala:229:36] reg [3:0] ldq_forward_stq_idx_0; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_1; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_2; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_3; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_4; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_5; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_6; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_7; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_8; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_9; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_10; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_11; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_12; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_13; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_14; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_15; // @[lsu.scala:230:36] reg [63:0] ldq_debug_wb_data_0; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_1; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_2; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_3; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_4; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_5; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_6; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_7; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_8; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_9; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_10; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_11; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_12; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_13; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_14; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_15; // @[lsu.scala:231:36] reg stq_valid_0; // @[lsu.scala:251:32] reg stq_valid_1; // @[lsu.scala:251:32] reg stq_valid_2; // @[lsu.scala:251:32] reg stq_valid_3; // @[lsu.scala:251:32] reg stq_valid_4; // @[lsu.scala:251:32] reg stq_valid_5; // @[lsu.scala:251:32] reg stq_valid_6; // @[lsu.scala:251:32] reg stq_valid_7; // @[lsu.scala:251:32] reg stq_valid_8; // @[lsu.scala:251:32] reg stq_valid_9; // @[lsu.scala:251:32] reg stq_valid_10; // @[lsu.scala:251:32] reg stq_valid_11; // @[lsu.scala:251:32] reg stq_valid_12; // @[lsu.scala:251:32] reg stq_valid_13; // @[lsu.scala:251:32] reg stq_valid_14; // @[lsu.scala:251:32] reg stq_valid_15; // @[lsu.scala:251:32] reg [31:0] stq_uop_0_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_2_inst = stq_uop_0_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_1_inst = stq_uop_0_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_0_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_2_debug_inst = stq_uop_0_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_1_debug_inst = stq_uop_0_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_rvc; // @[lsu.scala:252:32] wire s_uop_2_is_rvc = stq_uop_0_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_rvc = stq_uop_0_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_0_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_2_debug_pc = stq_uop_0_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_1_debug_pc = stq_uop_0_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_0; // @[lsu.scala:252:32] wire s_uop_2_iq_type_0 = stq_uop_0_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_0 = stq_uop_0_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_1; // @[lsu.scala:252:32] wire s_uop_2_iq_type_1 = stq_uop_0_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_1 = stq_uop_0_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_2; // @[lsu.scala:252:32] wire s_uop_2_iq_type_2 = stq_uop_0_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_2 = stq_uop_0_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_3; // @[lsu.scala:252:32] wire s_uop_2_iq_type_3 = stq_uop_0_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_3 = stq_uop_0_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_0; // @[lsu.scala:252:32] wire s_uop_2_fu_code_0 = stq_uop_0_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_0 = stq_uop_0_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_1; // @[lsu.scala:252:32] wire s_uop_2_fu_code_1 = stq_uop_0_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_1 = stq_uop_0_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_2; // @[lsu.scala:252:32] wire s_uop_2_fu_code_2 = stq_uop_0_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_2 = stq_uop_0_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_3; // @[lsu.scala:252:32] wire s_uop_2_fu_code_3 = stq_uop_0_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_3 = stq_uop_0_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_4; // @[lsu.scala:252:32] wire s_uop_2_fu_code_4 = stq_uop_0_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_4 = stq_uop_0_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_5; // @[lsu.scala:252:32] wire s_uop_2_fu_code_5 = stq_uop_0_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_5 = stq_uop_0_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_6; // @[lsu.scala:252:32] wire s_uop_2_fu_code_6 = stq_uop_0_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_6 = stq_uop_0_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_7; // @[lsu.scala:252:32] wire s_uop_2_fu_code_7 = stq_uop_0_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_7 = stq_uop_0_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_8; // @[lsu.scala:252:32] wire s_uop_2_fu_code_8 = stq_uop_0_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_8 = stq_uop_0_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_9; // @[lsu.scala:252:32] wire s_uop_2_fu_code_9 = stq_uop_0_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_9 = stq_uop_0_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_issued; // @[lsu.scala:252:32] wire s_uop_2_iw_issued = stq_uop_0_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_issued = stq_uop_0_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_2_iw_issued_partial_agen = stq_uop_0_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_issued_partial_agen = stq_uop_0_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_2_iw_issued_partial_dgen = stq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_issued_partial_dgen = stq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_2_iw_p1_speculative_child = stq_uop_0_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_iw_p1_speculative_child = stq_uop_0_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_2_iw_p2_speculative_child = stq_uop_0_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_iw_p2_speculative_child = stq_uop_0_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_2_iw_p1_bypass_hint = stq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_p1_bypass_hint = stq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_2_iw_p2_bypass_hint = stq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_p2_bypass_hint = stq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_2_iw_p3_bypass_hint = stq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_p3_bypass_hint = stq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_2_dis_col_sel = stq_uop_0_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_dis_col_sel = stq_uop_0_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_0_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_2_br_mask = stq_uop_0_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_1_br_mask = stq_uop_0_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_0_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_2_br_tag = stq_uop_0_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_1_br_tag = stq_uop_0_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_0_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_2_br_type = stq_uop_0_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_1_br_type = stq_uop_0_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_sfb; // @[lsu.scala:252:32] wire s_uop_2_is_sfb = stq_uop_0_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_sfb = stq_uop_0_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_fence; // @[lsu.scala:252:32] wire s_uop_2_is_fence = stq_uop_0_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_fence = stq_uop_0_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_fencei; // @[lsu.scala:252:32] wire s_uop_2_is_fencei = stq_uop_0_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_fencei = stq_uop_0_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_sfence; // @[lsu.scala:252:32] wire s_uop_2_is_sfence = stq_uop_0_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_sfence = stq_uop_0_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_amo; // @[lsu.scala:252:32] wire s_uop_2_is_amo = stq_uop_0_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_amo = stq_uop_0_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_eret; // @[lsu.scala:252:32] wire s_uop_2_is_eret = stq_uop_0_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_eret = stq_uop_0_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_2_is_sys_pc2epc = stq_uop_0_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_sys_pc2epc = stq_uop_0_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_rocc; // @[lsu.scala:252:32] wire s_uop_2_is_rocc = stq_uop_0_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_rocc = stq_uop_0_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_mov; // @[lsu.scala:252:32] wire s_uop_2_is_mov = stq_uop_0_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_mov = stq_uop_0_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_2_ftq_idx = stq_uop_0_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_ftq_idx = stq_uop_0_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_edge_inst; // @[lsu.scala:252:32] wire s_uop_2_edge_inst = stq_uop_0_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_1_edge_inst = stq_uop_0_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_2_pc_lob = stq_uop_0_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_pc_lob = stq_uop_0_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_taken; // @[lsu.scala:252:32] wire s_uop_2_taken = stq_uop_0_taken; // @[lsu.scala:252:32, :1324:37] wire uop_1_taken = stq_uop_0_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_imm_rename; // @[lsu.scala:252:32] wire s_uop_2_imm_rename = stq_uop_0_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_1_imm_rename = stq_uop_0_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_2_imm_sel = stq_uop_0_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_imm_sel = stq_uop_0_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_2_pimm = stq_uop_0_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_pimm = stq_uop_0_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_0_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_2_imm_packed = stq_uop_0_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_1_imm_packed = stq_uop_0_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_2_op1_sel = stq_uop_0_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_op1_sel = stq_uop_0_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_2_op2_sel = stq_uop_0_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_op2_sel = stq_uop_0_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_ldst = stq_uop_0_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ldst = stq_uop_0_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_wen = stq_uop_0_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_wen = stq_uop_0_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_ren1 = stq_uop_0_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ren1 = stq_uop_0_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_ren2 = stq_uop_0_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ren2 = stq_uop_0_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_ren3 = stq_uop_0_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ren3 = stq_uop_0_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_swap12 = stq_uop_0_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_swap12 = stq_uop_0_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_swap23 = stq_uop_0_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_swap23 = stq_uop_0_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_2_fp_ctrl_typeTagIn = stq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_fp_ctrl_typeTagIn = stq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_2_fp_ctrl_typeTagOut = stq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_fp_ctrl_typeTagOut = stq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_fromint = stq_uop_0_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_fromint = stq_uop_0_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_toint = stq_uop_0_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_toint = stq_uop_0_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_fastpipe = stq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_fastpipe = stq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_fma = stq_uop_0_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_fma = stq_uop_0_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_div = stq_uop_0_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_div = stq_uop_0_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_sqrt = stq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_sqrt = stq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_wflags = stq_uop_0_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_wflags = stq_uop_0_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_vec = stq_uop_0_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_vec = stq_uop_0_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_2_rob_idx = stq_uop_0_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_rob_idx = stq_uop_0_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_0_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_2_ldq_idx = stq_uop_0_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_1_ldq_idx = stq_uop_0_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_0_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_2_stq_idx = stq_uop_0_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_1_stq_idx = stq_uop_0_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_2_rxq_idx = stq_uop_0_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_rxq_idx = stq_uop_0_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_2_pdst = stq_uop_0_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_pdst = stq_uop_0_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_2_prs1 = stq_uop_0_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_prs1 = stq_uop_0_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_2_prs2 = stq_uop_0_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_prs2 = stq_uop_0_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_2_prs3 = stq_uop_0_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_prs3 = stq_uop_0_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_2_ppred = stq_uop_0_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_ppred = stq_uop_0_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_prs1_busy; // @[lsu.scala:252:32] wire s_uop_2_prs1_busy = stq_uop_0_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_prs1_busy = stq_uop_0_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_prs2_busy; // @[lsu.scala:252:32] wire s_uop_2_prs2_busy = stq_uop_0_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_prs2_busy = stq_uop_0_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_prs3_busy; // @[lsu.scala:252:32] wire s_uop_2_prs3_busy = stq_uop_0_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_prs3_busy = stq_uop_0_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_ppred_busy; // @[lsu.scala:252:32] wire s_uop_2_ppred_busy = stq_uop_0_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_ppred_busy = stq_uop_0_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_2_stale_pdst = stq_uop_0_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_stale_pdst = stq_uop_0_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_exception; // @[lsu.scala:252:32] wire s_uop_2_exception = stq_uop_0_exception; // @[lsu.scala:252:32, :1324:37] wire uop_1_exception = stq_uop_0_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_0_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_2_exc_cause = stq_uop_0_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_1_exc_cause = stq_uop_0_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_2_mem_cmd = stq_uop_0_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_mem_cmd = stq_uop_0_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_2_mem_size = stq_uop_0_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_mem_size = stq_uop_0_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_mem_signed; // @[lsu.scala:252:32] wire s_uop_2_mem_signed = stq_uop_0_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_1_mem_signed = stq_uop_0_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_uses_ldq; // @[lsu.scala:252:32] wire s_uop_2_uses_ldq = stq_uop_0_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_1_uses_ldq = stq_uop_0_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_uses_stq; // @[lsu.scala:252:32] wire s_uop_2_uses_stq = stq_uop_0_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_1_uses_stq = stq_uop_0_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_unique; // @[lsu.scala:252:32] wire s_uop_2_is_unique = stq_uop_0_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_unique = stq_uop_0_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_2_flush_on_commit = stq_uop_0_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_1_flush_on_commit = stq_uop_0_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_2_csr_cmd = stq_uop_0_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_csr_cmd = stq_uop_0_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_2_ldst_is_rs1 = stq_uop_0_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_1_ldst_is_rs1 = stq_uop_0_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_2_ldst = stq_uop_0_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_ldst = stq_uop_0_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_2_lrs1 = stq_uop_0_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_lrs1 = stq_uop_0_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_2_lrs2 = stq_uop_0_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_lrs2 = stq_uop_0_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_2_lrs3 = stq_uop_0_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_lrs3 = stq_uop_0_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_2_dst_rtype = stq_uop_0_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_dst_rtype = stq_uop_0_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_2_lrs1_rtype = stq_uop_0_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_lrs1_rtype = stq_uop_0_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_2_lrs2_rtype = stq_uop_0_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_lrs2_rtype = stq_uop_0_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_frs3_en; // @[lsu.scala:252:32] wire s_uop_2_frs3_en = stq_uop_0_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_1_frs3_en = stq_uop_0_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fcn_dw; // @[lsu.scala:252:32] wire s_uop_2_fcn_dw = stq_uop_0_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_1_fcn_dw = stq_uop_0_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_2_fcn_op = stq_uop_0_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_fcn_op = stq_uop_0_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_val; // @[lsu.scala:252:32] wire s_uop_2_fp_val = stq_uop_0_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_val = stq_uop_0_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_2_fp_rm = stq_uop_0_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_fp_rm = stq_uop_0_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_2_fp_typ = stq_uop_0_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_fp_typ = stq_uop_0_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_2_xcpt_pf_if = stq_uop_0_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_xcpt_pf_if = stq_uop_0_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_2_xcpt_ae_if = stq_uop_0_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_xcpt_ae_if = stq_uop_0_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_2_xcpt_ma_if = stq_uop_0_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_xcpt_ma_if = stq_uop_0_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_2_bp_debug_if = stq_uop_0_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_bp_debug_if = stq_uop_0_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_2_bp_xcpt_if = stq_uop_0_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_bp_xcpt_if = stq_uop_0_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_2_debug_fsrc = stq_uop_0_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_debug_fsrc = stq_uop_0_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_2_debug_tsrc = stq_uop_0_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_debug_tsrc = stq_uop_0_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_1_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_3_inst = stq_uop_1_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_2_inst = stq_uop_1_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_1_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_3_debug_inst = stq_uop_1_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_2_debug_inst = stq_uop_1_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_rvc; // @[lsu.scala:252:32] wire s_uop_3_is_rvc = stq_uop_1_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_rvc = stq_uop_1_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_1_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_3_debug_pc = stq_uop_1_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_2_debug_pc = stq_uop_1_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_0; // @[lsu.scala:252:32] wire s_uop_3_iq_type_0 = stq_uop_1_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_0 = stq_uop_1_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_1; // @[lsu.scala:252:32] wire s_uop_3_iq_type_1 = stq_uop_1_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_1 = stq_uop_1_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_2; // @[lsu.scala:252:32] wire s_uop_3_iq_type_2 = stq_uop_1_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_2 = stq_uop_1_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_3; // @[lsu.scala:252:32] wire s_uop_3_iq_type_3 = stq_uop_1_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_3 = stq_uop_1_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_0; // @[lsu.scala:252:32] wire s_uop_3_fu_code_0 = stq_uop_1_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_0 = stq_uop_1_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_1; // @[lsu.scala:252:32] wire s_uop_3_fu_code_1 = stq_uop_1_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_1 = stq_uop_1_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_2; // @[lsu.scala:252:32] wire s_uop_3_fu_code_2 = stq_uop_1_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_2 = stq_uop_1_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_3; // @[lsu.scala:252:32] wire s_uop_3_fu_code_3 = stq_uop_1_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_3 = stq_uop_1_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_4; // @[lsu.scala:252:32] wire s_uop_3_fu_code_4 = stq_uop_1_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_4 = stq_uop_1_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_5; // @[lsu.scala:252:32] wire s_uop_3_fu_code_5 = stq_uop_1_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_5 = stq_uop_1_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_6; // @[lsu.scala:252:32] wire s_uop_3_fu_code_6 = stq_uop_1_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_6 = stq_uop_1_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_7; // @[lsu.scala:252:32] wire s_uop_3_fu_code_7 = stq_uop_1_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_7 = stq_uop_1_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_8; // @[lsu.scala:252:32] wire s_uop_3_fu_code_8 = stq_uop_1_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_8 = stq_uop_1_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_9; // @[lsu.scala:252:32] wire s_uop_3_fu_code_9 = stq_uop_1_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_9 = stq_uop_1_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_issued; // @[lsu.scala:252:32] wire s_uop_3_iw_issued = stq_uop_1_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_issued = stq_uop_1_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_3_iw_issued_partial_agen = stq_uop_1_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_issued_partial_agen = stq_uop_1_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_3_iw_issued_partial_dgen = stq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_issued_partial_dgen = stq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_3_iw_p1_speculative_child = stq_uop_1_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_iw_p1_speculative_child = stq_uop_1_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_3_iw_p2_speculative_child = stq_uop_1_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_iw_p2_speculative_child = stq_uop_1_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_3_iw_p1_bypass_hint = stq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_p1_bypass_hint = stq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_3_iw_p2_bypass_hint = stq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_p2_bypass_hint = stq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_3_iw_p3_bypass_hint = stq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_p3_bypass_hint = stq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_3_dis_col_sel = stq_uop_1_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_dis_col_sel = stq_uop_1_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_1_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_3_br_mask = stq_uop_1_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_2_br_mask = stq_uop_1_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_1_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_3_br_tag = stq_uop_1_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_2_br_tag = stq_uop_1_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_1_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_3_br_type = stq_uop_1_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_2_br_type = stq_uop_1_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_sfb; // @[lsu.scala:252:32] wire s_uop_3_is_sfb = stq_uop_1_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_sfb = stq_uop_1_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_fence; // @[lsu.scala:252:32] wire s_uop_3_is_fence = stq_uop_1_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_fence = stq_uop_1_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_fencei; // @[lsu.scala:252:32] wire s_uop_3_is_fencei = stq_uop_1_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_fencei = stq_uop_1_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_sfence; // @[lsu.scala:252:32] wire s_uop_3_is_sfence = stq_uop_1_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_sfence = stq_uop_1_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_amo; // @[lsu.scala:252:32] wire s_uop_3_is_amo = stq_uop_1_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_amo = stq_uop_1_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_eret; // @[lsu.scala:252:32] wire s_uop_3_is_eret = stq_uop_1_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_eret = stq_uop_1_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_3_is_sys_pc2epc = stq_uop_1_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_sys_pc2epc = stq_uop_1_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_rocc; // @[lsu.scala:252:32] wire s_uop_3_is_rocc = stq_uop_1_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_rocc = stq_uop_1_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_mov; // @[lsu.scala:252:32] wire s_uop_3_is_mov = stq_uop_1_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_mov = stq_uop_1_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_3_ftq_idx = stq_uop_1_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_ftq_idx = stq_uop_1_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_edge_inst; // @[lsu.scala:252:32] wire s_uop_3_edge_inst = stq_uop_1_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_2_edge_inst = stq_uop_1_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_3_pc_lob = stq_uop_1_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_pc_lob = stq_uop_1_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_taken; // @[lsu.scala:252:32] wire s_uop_3_taken = stq_uop_1_taken; // @[lsu.scala:252:32, :1324:37] wire uop_2_taken = stq_uop_1_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_imm_rename; // @[lsu.scala:252:32] wire s_uop_3_imm_rename = stq_uop_1_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_2_imm_rename = stq_uop_1_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_3_imm_sel = stq_uop_1_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_imm_sel = stq_uop_1_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_3_pimm = stq_uop_1_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_pimm = stq_uop_1_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_1_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_3_imm_packed = stq_uop_1_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_2_imm_packed = stq_uop_1_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_3_op1_sel = stq_uop_1_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_op1_sel = stq_uop_1_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_3_op2_sel = stq_uop_1_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_op2_sel = stq_uop_1_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ldst = stq_uop_1_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ldst = stq_uop_1_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_wen = stq_uop_1_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_wen = stq_uop_1_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ren1 = stq_uop_1_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ren1 = stq_uop_1_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ren2 = stq_uop_1_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ren2 = stq_uop_1_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ren3 = stq_uop_1_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ren3 = stq_uop_1_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_swap12 = stq_uop_1_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_swap12 = stq_uop_1_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_swap23 = stq_uop_1_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_swap23 = stq_uop_1_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_3_fp_ctrl_typeTagIn = stq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_fp_ctrl_typeTagIn = stq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_3_fp_ctrl_typeTagOut = stq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_fp_ctrl_typeTagOut = stq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_fromint = stq_uop_1_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_fromint = stq_uop_1_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_toint = stq_uop_1_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_toint = stq_uop_1_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_fastpipe = stq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_fastpipe = stq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_fma = stq_uop_1_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_fma = stq_uop_1_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_div = stq_uop_1_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_div = stq_uop_1_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_sqrt = stq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_sqrt = stq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_wflags = stq_uop_1_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_wflags = stq_uop_1_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_vec = stq_uop_1_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_vec = stq_uop_1_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_3_rob_idx = stq_uop_1_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_rob_idx = stq_uop_1_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_1_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_3_ldq_idx = stq_uop_1_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_2_ldq_idx = stq_uop_1_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_1_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_3_stq_idx = stq_uop_1_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_2_stq_idx = stq_uop_1_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_3_rxq_idx = stq_uop_1_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_rxq_idx = stq_uop_1_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_3_pdst = stq_uop_1_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_pdst = stq_uop_1_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_3_prs1 = stq_uop_1_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_prs1 = stq_uop_1_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_3_prs2 = stq_uop_1_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_prs2 = stq_uop_1_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_3_prs3 = stq_uop_1_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_prs3 = stq_uop_1_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_3_ppred = stq_uop_1_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_ppred = stq_uop_1_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_prs1_busy; // @[lsu.scala:252:32] wire s_uop_3_prs1_busy = stq_uop_1_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_prs1_busy = stq_uop_1_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_prs2_busy; // @[lsu.scala:252:32] wire s_uop_3_prs2_busy = stq_uop_1_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_prs2_busy = stq_uop_1_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_prs3_busy; // @[lsu.scala:252:32] wire s_uop_3_prs3_busy = stq_uop_1_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_prs3_busy = stq_uop_1_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_ppred_busy; // @[lsu.scala:252:32] wire s_uop_3_ppred_busy = stq_uop_1_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_ppred_busy = stq_uop_1_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_3_stale_pdst = stq_uop_1_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_stale_pdst = stq_uop_1_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_exception; // @[lsu.scala:252:32] wire s_uop_3_exception = stq_uop_1_exception; // @[lsu.scala:252:32, :1324:37] wire uop_2_exception = stq_uop_1_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_1_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_3_exc_cause = stq_uop_1_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_2_exc_cause = stq_uop_1_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_3_mem_cmd = stq_uop_1_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_mem_cmd = stq_uop_1_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_3_mem_size = stq_uop_1_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_mem_size = stq_uop_1_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_mem_signed; // @[lsu.scala:252:32] wire s_uop_3_mem_signed = stq_uop_1_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_2_mem_signed = stq_uop_1_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_uses_ldq; // @[lsu.scala:252:32] wire s_uop_3_uses_ldq = stq_uop_1_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_2_uses_ldq = stq_uop_1_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_uses_stq; // @[lsu.scala:252:32] wire s_uop_3_uses_stq = stq_uop_1_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_2_uses_stq = stq_uop_1_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_unique; // @[lsu.scala:252:32] wire s_uop_3_is_unique = stq_uop_1_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_unique = stq_uop_1_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_3_flush_on_commit = stq_uop_1_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_2_flush_on_commit = stq_uop_1_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_3_csr_cmd = stq_uop_1_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_csr_cmd = stq_uop_1_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_3_ldst_is_rs1 = stq_uop_1_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_2_ldst_is_rs1 = stq_uop_1_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_3_ldst = stq_uop_1_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_ldst = stq_uop_1_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_3_lrs1 = stq_uop_1_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_lrs1 = stq_uop_1_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_3_lrs2 = stq_uop_1_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_lrs2 = stq_uop_1_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_3_lrs3 = stq_uop_1_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_lrs3 = stq_uop_1_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_3_dst_rtype = stq_uop_1_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_dst_rtype = stq_uop_1_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_3_lrs1_rtype = stq_uop_1_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_lrs1_rtype = stq_uop_1_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_3_lrs2_rtype = stq_uop_1_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_lrs2_rtype = stq_uop_1_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_frs3_en; // @[lsu.scala:252:32] wire s_uop_3_frs3_en = stq_uop_1_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_2_frs3_en = stq_uop_1_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fcn_dw; // @[lsu.scala:252:32] wire s_uop_3_fcn_dw = stq_uop_1_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_2_fcn_dw = stq_uop_1_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_3_fcn_op = stq_uop_1_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_fcn_op = stq_uop_1_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_val; // @[lsu.scala:252:32] wire s_uop_3_fp_val = stq_uop_1_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_val = stq_uop_1_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_3_fp_rm = stq_uop_1_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_fp_rm = stq_uop_1_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_3_fp_typ = stq_uop_1_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_fp_typ = stq_uop_1_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_3_xcpt_pf_if = stq_uop_1_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_xcpt_pf_if = stq_uop_1_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_3_xcpt_ae_if = stq_uop_1_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_xcpt_ae_if = stq_uop_1_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_3_xcpt_ma_if = stq_uop_1_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_xcpt_ma_if = stq_uop_1_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_3_bp_debug_if = stq_uop_1_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_bp_debug_if = stq_uop_1_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_3_bp_xcpt_if = stq_uop_1_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_bp_xcpt_if = stq_uop_1_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_3_debug_fsrc = stq_uop_1_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_debug_fsrc = stq_uop_1_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_3_debug_tsrc = stq_uop_1_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_debug_tsrc = stq_uop_1_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_2_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_4_inst = stq_uop_2_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_3_inst = stq_uop_2_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_2_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_4_debug_inst = stq_uop_2_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_3_debug_inst = stq_uop_2_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_rvc; // @[lsu.scala:252:32] wire s_uop_4_is_rvc = stq_uop_2_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_rvc = stq_uop_2_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_2_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_4_debug_pc = stq_uop_2_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_3_debug_pc = stq_uop_2_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_0; // @[lsu.scala:252:32] wire s_uop_4_iq_type_0 = stq_uop_2_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_0 = stq_uop_2_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_1; // @[lsu.scala:252:32] wire s_uop_4_iq_type_1 = stq_uop_2_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_1 = stq_uop_2_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_2; // @[lsu.scala:252:32] wire s_uop_4_iq_type_2 = stq_uop_2_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_2 = stq_uop_2_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_3; // @[lsu.scala:252:32] wire s_uop_4_iq_type_3 = stq_uop_2_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_3 = stq_uop_2_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_0; // @[lsu.scala:252:32] wire s_uop_4_fu_code_0 = stq_uop_2_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_0 = stq_uop_2_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_1; // @[lsu.scala:252:32] wire s_uop_4_fu_code_1 = stq_uop_2_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_1 = stq_uop_2_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_2; // @[lsu.scala:252:32] wire s_uop_4_fu_code_2 = stq_uop_2_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_2 = stq_uop_2_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_3; // @[lsu.scala:252:32] wire s_uop_4_fu_code_3 = stq_uop_2_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_3 = stq_uop_2_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_4; // @[lsu.scala:252:32] wire s_uop_4_fu_code_4 = stq_uop_2_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_4 = stq_uop_2_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_5; // @[lsu.scala:252:32] wire s_uop_4_fu_code_5 = stq_uop_2_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_5 = stq_uop_2_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_6; // @[lsu.scala:252:32] wire s_uop_4_fu_code_6 = stq_uop_2_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_6 = stq_uop_2_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_7; // @[lsu.scala:252:32] wire s_uop_4_fu_code_7 = stq_uop_2_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_7 = stq_uop_2_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_8; // @[lsu.scala:252:32] wire s_uop_4_fu_code_8 = stq_uop_2_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_8 = stq_uop_2_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_9; // @[lsu.scala:252:32] wire s_uop_4_fu_code_9 = stq_uop_2_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_9 = stq_uop_2_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_issued; // @[lsu.scala:252:32] wire s_uop_4_iw_issued = stq_uop_2_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_issued = stq_uop_2_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_4_iw_issued_partial_agen = stq_uop_2_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_issued_partial_agen = stq_uop_2_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_4_iw_issued_partial_dgen = stq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_issued_partial_dgen = stq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_4_iw_p1_speculative_child = stq_uop_2_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_iw_p1_speculative_child = stq_uop_2_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_4_iw_p2_speculative_child = stq_uop_2_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_iw_p2_speculative_child = stq_uop_2_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_4_iw_p1_bypass_hint = stq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_p1_bypass_hint = stq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_4_iw_p2_bypass_hint = stq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_p2_bypass_hint = stq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_4_iw_p3_bypass_hint = stq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_p3_bypass_hint = stq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_4_dis_col_sel = stq_uop_2_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_dis_col_sel = stq_uop_2_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_2_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_4_br_mask = stq_uop_2_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_3_br_mask = stq_uop_2_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_2_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_4_br_tag = stq_uop_2_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_3_br_tag = stq_uop_2_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_2_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_4_br_type = stq_uop_2_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_3_br_type = stq_uop_2_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_sfb; // @[lsu.scala:252:32] wire s_uop_4_is_sfb = stq_uop_2_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_sfb = stq_uop_2_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_fence; // @[lsu.scala:252:32] wire s_uop_4_is_fence = stq_uop_2_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_fence = stq_uop_2_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_fencei; // @[lsu.scala:252:32] wire s_uop_4_is_fencei = stq_uop_2_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_fencei = stq_uop_2_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_sfence; // @[lsu.scala:252:32] wire s_uop_4_is_sfence = stq_uop_2_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_sfence = stq_uop_2_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_amo; // @[lsu.scala:252:32] wire s_uop_4_is_amo = stq_uop_2_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_amo = stq_uop_2_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_eret; // @[lsu.scala:252:32] wire s_uop_4_is_eret = stq_uop_2_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_eret = stq_uop_2_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_4_is_sys_pc2epc = stq_uop_2_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_sys_pc2epc = stq_uop_2_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_rocc; // @[lsu.scala:252:32] wire s_uop_4_is_rocc = stq_uop_2_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_rocc = stq_uop_2_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_mov; // @[lsu.scala:252:32] wire s_uop_4_is_mov = stq_uop_2_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_mov = stq_uop_2_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_4_ftq_idx = stq_uop_2_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_ftq_idx = stq_uop_2_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_edge_inst; // @[lsu.scala:252:32] wire s_uop_4_edge_inst = stq_uop_2_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_3_edge_inst = stq_uop_2_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_4_pc_lob = stq_uop_2_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_pc_lob = stq_uop_2_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_taken; // @[lsu.scala:252:32] wire s_uop_4_taken = stq_uop_2_taken; // @[lsu.scala:252:32, :1324:37] wire uop_3_taken = stq_uop_2_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_imm_rename; // @[lsu.scala:252:32] wire s_uop_4_imm_rename = stq_uop_2_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_3_imm_rename = stq_uop_2_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_4_imm_sel = stq_uop_2_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_imm_sel = stq_uop_2_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_4_pimm = stq_uop_2_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_pimm = stq_uop_2_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_2_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_4_imm_packed = stq_uop_2_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_3_imm_packed = stq_uop_2_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_4_op1_sel = stq_uop_2_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_op1_sel = stq_uop_2_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_4_op2_sel = stq_uop_2_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_op2_sel = stq_uop_2_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ldst = stq_uop_2_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ldst = stq_uop_2_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_wen = stq_uop_2_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_wen = stq_uop_2_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ren1 = stq_uop_2_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ren1 = stq_uop_2_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ren2 = stq_uop_2_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ren2 = stq_uop_2_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ren3 = stq_uop_2_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ren3 = stq_uop_2_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_swap12 = stq_uop_2_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_swap12 = stq_uop_2_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_swap23 = stq_uop_2_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_swap23 = stq_uop_2_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_4_fp_ctrl_typeTagIn = stq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_fp_ctrl_typeTagIn = stq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_4_fp_ctrl_typeTagOut = stq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_fp_ctrl_typeTagOut = stq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_fromint = stq_uop_2_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_fromint = stq_uop_2_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_toint = stq_uop_2_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_toint = stq_uop_2_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_fastpipe = stq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_fastpipe = stq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_fma = stq_uop_2_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_fma = stq_uop_2_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_div = stq_uop_2_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_div = stq_uop_2_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_sqrt = stq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_sqrt = stq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_wflags = stq_uop_2_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_wflags = stq_uop_2_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_vec = stq_uop_2_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_vec = stq_uop_2_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_4_rob_idx = stq_uop_2_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_rob_idx = stq_uop_2_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_2_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_4_ldq_idx = stq_uop_2_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_3_ldq_idx = stq_uop_2_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_2_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_4_stq_idx = stq_uop_2_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_3_stq_idx = stq_uop_2_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_4_rxq_idx = stq_uop_2_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_rxq_idx = stq_uop_2_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_4_pdst = stq_uop_2_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_pdst = stq_uop_2_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_4_prs1 = stq_uop_2_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_prs1 = stq_uop_2_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_4_prs2 = stq_uop_2_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_prs2 = stq_uop_2_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_4_prs3 = stq_uop_2_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_prs3 = stq_uop_2_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_4_ppred = stq_uop_2_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_ppred = stq_uop_2_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_prs1_busy; // @[lsu.scala:252:32] wire s_uop_4_prs1_busy = stq_uop_2_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_prs1_busy = stq_uop_2_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_prs2_busy; // @[lsu.scala:252:32] wire s_uop_4_prs2_busy = stq_uop_2_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_prs2_busy = stq_uop_2_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_prs3_busy; // @[lsu.scala:252:32] wire s_uop_4_prs3_busy = stq_uop_2_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_prs3_busy = stq_uop_2_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_ppred_busy; // @[lsu.scala:252:32] wire s_uop_4_ppred_busy = stq_uop_2_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_ppred_busy = stq_uop_2_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_4_stale_pdst = stq_uop_2_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_stale_pdst = stq_uop_2_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_exception; // @[lsu.scala:252:32] wire s_uop_4_exception = stq_uop_2_exception; // @[lsu.scala:252:32, :1324:37] wire uop_3_exception = stq_uop_2_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_2_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_4_exc_cause = stq_uop_2_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_3_exc_cause = stq_uop_2_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_4_mem_cmd = stq_uop_2_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_mem_cmd = stq_uop_2_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_4_mem_size = stq_uop_2_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_mem_size = stq_uop_2_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_mem_signed; // @[lsu.scala:252:32] wire s_uop_4_mem_signed = stq_uop_2_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_3_mem_signed = stq_uop_2_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_uses_ldq; // @[lsu.scala:252:32] wire s_uop_4_uses_ldq = stq_uop_2_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_3_uses_ldq = stq_uop_2_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_uses_stq; // @[lsu.scala:252:32] wire s_uop_4_uses_stq = stq_uop_2_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_3_uses_stq = stq_uop_2_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_unique; // @[lsu.scala:252:32] wire s_uop_4_is_unique = stq_uop_2_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_unique = stq_uop_2_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_4_flush_on_commit = stq_uop_2_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_3_flush_on_commit = stq_uop_2_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_4_csr_cmd = stq_uop_2_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_csr_cmd = stq_uop_2_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_4_ldst_is_rs1 = stq_uop_2_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_3_ldst_is_rs1 = stq_uop_2_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_4_ldst = stq_uop_2_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_ldst = stq_uop_2_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_4_lrs1 = stq_uop_2_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_lrs1 = stq_uop_2_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_4_lrs2 = stq_uop_2_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_lrs2 = stq_uop_2_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_4_lrs3 = stq_uop_2_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_lrs3 = stq_uop_2_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_4_dst_rtype = stq_uop_2_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_dst_rtype = stq_uop_2_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_4_lrs1_rtype = stq_uop_2_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_lrs1_rtype = stq_uop_2_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_4_lrs2_rtype = stq_uop_2_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_lrs2_rtype = stq_uop_2_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_frs3_en; // @[lsu.scala:252:32] wire s_uop_4_frs3_en = stq_uop_2_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_3_frs3_en = stq_uop_2_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fcn_dw; // @[lsu.scala:252:32] wire s_uop_4_fcn_dw = stq_uop_2_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_3_fcn_dw = stq_uop_2_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_4_fcn_op = stq_uop_2_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_fcn_op = stq_uop_2_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_val; // @[lsu.scala:252:32] wire s_uop_4_fp_val = stq_uop_2_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_val = stq_uop_2_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_4_fp_rm = stq_uop_2_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_fp_rm = stq_uop_2_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_4_fp_typ = stq_uop_2_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_fp_typ = stq_uop_2_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_4_xcpt_pf_if = stq_uop_2_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_xcpt_pf_if = stq_uop_2_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_4_xcpt_ae_if = stq_uop_2_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_xcpt_ae_if = stq_uop_2_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_4_xcpt_ma_if = stq_uop_2_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_xcpt_ma_if = stq_uop_2_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_4_bp_debug_if = stq_uop_2_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_bp_debug_if = stq_uop_2_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_4_bp_xcpt_if = stq_uop_2_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_bp_xcpt_if = stq_uop_2_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_4_debug_fsrc = stq_uop_2_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_debug_fsrc = stq_uop_2_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_4_debug_tsrc = stq_uop_2_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_debug_tsrc = stq_uop_2_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_3_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_5_inst = stq_uop_3_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_4_inst = stq_uop_3_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_3_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_5_debug_inst = stq_uop_3_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_4_debug_inst = stq_uop_3_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_rvc; // @[lsu.scala:252:32] wire s_uop_5_is_rvc = stq_uop_3_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_rvc = stq_uop_3_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_3_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_5_debug_pc = stq_uop_3_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_4_debug_pc = stq_uop_3_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_0; // @[lsu.scala:252:32] wire s_uop_5_iq_type_0 = stq_uop_3_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_0 = stq_uop_3_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_1; // @[lsu.scala:252:32] wire s_uop_5_iq_type_1 = stq_uop_3_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_1 = stq_uop_3_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_2; // @[lsu.scala:252:32] wire s_uop_5_iq_type_2 = stq_uop_3_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_2 = stq_uop_3_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_3; // @[lsu.scala:252:32] wire s_uop_5_iq_type_3 = stq_uop_3_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_3 = stq_uop_3_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_0; // @[lsu.scala:252:32] wire s_uop_5_fu_code_0 = stq_uop_3_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_0 = stq_uop_3_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_1; // @[lsu.scala:252:32] wire s_uop_5_fu_code_1 = stq_uop_3_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_1 = stq_uop_3_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_2; // @[lsu.scala:252:32] wire s_uop_5_fu_code_2 = stq_uop_3_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_2 = stq_uop_3_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_3; // @[lsu.scala:252:32] wire s_uop_5_fu_code_3 = stq_uop_3_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_3 = stq_uop_3_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_4; // @[lsu.scala:252:32] wire s_uop_5_fu_code_4 = stq_uop_3_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_4 = stq_uop_3_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_5; // @[lsu.scala:252:32] wire s_uop_5_fu_code_5 = stq_uop_3_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_5 = stq_uop_3_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_6; // @[lsu.scala:252:32] wire s_uop_5_fu_code_6 = stq_uop_3_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_6 = stq_uop_3_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_7; // @[lsu.scala:252:32] wire s_uop_5_fu_code_7 = stq_uop_3_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_7 = stq_uop_3_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_8; // @[lsu.scala:252:32] wire s_uop_5_fu_code_8 = stq_uop_3_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_8 = stq_uop_3_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_9; // @[lsu.scala:252:32] wire s_uop_5_fu_code_9 = stq_uop_3_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_9 = stq_uop_3_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_issued; // @[lsu.scala:252:32] wire s_uop_5_iw_issued = stq_uop_3_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_issued = stq_uop_3_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_5_iw_issued_partial_agen = stq_uop_3_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_issued_partial_agen = stq_uop_3_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_5_iw_issued_partial_dgen = stq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_issued_partial_dgen = stq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_5_iw_p1_speculative_child = stq_uop_3_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_iw_p1_speculative_child = stq_uop_3_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_5_iw_p2_speculative_child = stq_uop_3_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_iw_p2_speculative_child = stq_uop_3_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_5_iw_p1_bypass_hint = stq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_p1_bypass_hint = stq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_5_iw_p2_bypass_hint = stq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_p2_bypass_hint = stq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_5_iw_p3_bypass_hint = stq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_p3_bypass_hint = stq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_5_dis_col_sel = stq_uop_3_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_dis_col_sel = stq_uop_3_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_3_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_5_br_mask = stq_uop_3_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_4_br_mask = stq_uop_3_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_3_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_5_br_tag = stq_uop_3_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_4_br_tag = stq_uop_3_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_3_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_5_br_type = stq_uop_3_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_4_br_type = stq_uop_3_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_sfb; // @[lsu.scala:252:32] wire s_uop_5_is_sfb = stq_uop_3_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_sfb = stq_uop_3_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_fence; // @[lsu.scala:252:32] wire s_uop_5_is_fence = stq_uop_3_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_fence = stq_uop_3_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_fencei; // @[lsu.scala:252:32] wire s_uop_5_is_fencei = stq_uop_3_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_fencei = stq_uop_3_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_sfence; // @[lsu.scala:252:32] wire s_uop_5_is_sfence = stq_uop_3_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_sfence = stq_uop_3_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_amo; // @[lsu.scala:252:32] wire s_uop_5_is_amo = stq_uop_3_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_amo = stq_uop_3_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_eret; // @[lsu.scala:252:32] wire s_uop_5_is_eret = stq_uop_3_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_eret = stq_uop_3_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_5_is_sys_pc2epc = stq_uop_3_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_sys_pc2epc = stq_uop_3_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_rocc; // @[lsu.scala:252:32] wire s_uop_5_is_rocc = stq_uop_3_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_rocc = stq_uop_3_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_mov; // @[lsu.scala:252:32] wire s_uop_5_is_mov = stq_uop_3_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_mov = stq_uop_3_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_5_ftq_idx = stq_uop_3_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_ftq_idx = stq_uop_3_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_edge_inst; // @[lsu.scala:252:32] wire s_uop_5_edge_inst = stq_uop_3_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_4_edge_inst = stq_uop_3_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_5_pc_lob = stq_uop_3_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_pc_lob = stq_uop_3_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_taken; // @[lsu.scala:252:32] wire s_uop_5_taken = stq_uop_3_taken; // @[lsu.scala:252:32, :1324:37] wire uop_4_taken = stq_uop_3_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_imm_rename; // @[lsu.scala:252:32] wire s_uop_5_imm_rename = stq_uop_3_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_4_imm_rename = stq_uop_3_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_5_imm_sel = stq_uop_3_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_imm_sel = stq_uop_3_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_5_pimm = stq_uop_3_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_pimm = stq_uop_3_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_3_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_5_imm_packed = stq_uop_3_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_4_imm_packed = stq_uop_3_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_5_op1_sel = stq_uop_3_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_op1_sel = stq_uop_3_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_5_op2_sel = stq_uop_3_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_op2_sel = stq_uop_3_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ldst = stq_uop_3_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ldst = stq_uop_3_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_wen = stq_uop_3_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_wen = stq_uop_3_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ren1 = stq_uop_3_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ren1 = stq_uop_3_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ren2 = stq_uop_3_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ren2 = stq_uop_3_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ren3 = stq_uop_3_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ren3 = stq_uop_3_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_swap12 = stq_uop_3_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_swap12 = stq_uop_3_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_swap23 = stq_uop_3_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_swap23 = stq_uop_3_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_5_fp_ctrl_typeTagIn = stq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_fp_ctrl_typeTagIn = stq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_5_fp_ctrl_typeTagOut = stq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_fp_ctrl_typeTagOut = stq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_fromint = stq_uop_3_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_fromint = stq_uop_3_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_toint = stq_uop_3_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_toint = stq_uop_3_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_fastpipe = stq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_fastpipe = stq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_fma = stq_uop_3_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_fma = stq_uop_3_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_div = stq_uop_3_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_div = stq_uop_3_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_sqrt = stq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_sqrt = stq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_wflags = stq_uop_3_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_wflags = stq_uop_3_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_vec = stq_uop_3_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_vec = stq_uop_3_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_5_rob_idx = stq_uop_3_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_rob_idx = stq_uop_3_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_3_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_5_ldq_idx = stq_uop_3_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_4_ldq_idx = stq_uop_3_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_3_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_5_stq_idx = stq_uop_3_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_4_stq_idx = stq_uop_3_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_5_rxq_idx = stq_uop_3_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_rxq_idx = stq_uop_3_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_5_pdst = stq_uop_3_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_pdst = stq_uop_3_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_5_prs1 = stq_uop_3_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_prs1 = stq_uop_3_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_5_prs2 = stq_uop_3_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_prs2 = stq_uop_3_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_5_prs3 = stq_uop_3_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_prs3 = stq_uop_3_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_5_ppred = stq_uop_3_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_ppred = stq_uop_3_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_prs1_busy; // @[lsu.scala:252:32] wire s_uop_5_prs1_busy = stq_uop_3_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_prs1_busy = stq_uop_3_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_prs2_busy; // @[lsu.scala:252:32] wire s_uop_5_prs2_busy = stq_uop_3_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_prs2_busy = stq_uop_3_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_prs3_busy; // @[lsu.scala:252:32] wire s_uop_5_prs3_busy = stq_uop_3_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_prs3_busy = stq_uop_3_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_ppred_busy; // @[lsu.scala:252:32] wire s_uop_5_ppred_busy = stq_uop_3_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_ppred_busy = stq_uop_3_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_5_stale_pdst = stq_uop_3_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_stale_pdst = stq_uop_3_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_exception; // @[lsu.scala:252:32] wire s_uop_5_exception = stq_uop_3_exception; // @[lsu.scala:252:32, :1324:37] wire uop_4_exception = stq_uop_3_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_3_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_5_exc_cause = stq_uop_3_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_4_exc_cause = stq_uop_3_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_5_mem_cmd = stq_uop_3_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_mem_cmd = stq_uop_3_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_5_mem_size = stq_uop_3_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_mem_size = stq_uop_3_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_mem_signed; // @[lsu.scala:252:32] wire s_uop_5_mem_signed = stq_uop_3_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_4_mem_signed = stq_uop_3_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_uses_ldq; // @[lsu.scala:252:32] wire s_uop_5_uses_ldq = stq_uop_3_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_4_uses_ldq = stq_uop_3_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_uses_stq; // @[lsu.scala:252:32] wire s_uop_5_uses_stq = stq_uop_3_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_4_uses_stq = stq_uop_3_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_unique; // @[lsu.scala:252:32] wire s_uop_5_is_unique = stq_uop_3_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_unique = stq_uop_3_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_5_flush_on_commit = stq_uop_3_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_4_flush_on_commit = stq_uop_3_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_5_csr_cmd = stq_uop_3_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_csr_cmd = stq_uop_3_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_5_ldst_is_rs1 = stq_uop_3_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_4_ldst_is_rs1 = stq_uop_3_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_5_ldst = stq_uop_3_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_ldst = stq_uop_3_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_5_lrs1 = stq_uop_3_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_lrs1 = stq_uop_3_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_5_lrs2 = stq_uop_3_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_lrs2 = stq_uop_3_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_5_lrs3 = stq_uop_3_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_lrs3 = stq_uop_3_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_5_dst_rtype = stq_uop_3_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_dst_rtype = stq_uop_3_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_5_lrs1_rtype = stq_uop_3_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_lrs1_rtype = stq_uop_3_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_5_lrs2_rtype = stq_uop_3_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_lrs2_rtype = stq_uop_3_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_frs3_en; // @[lsu.scala:252:32] wire s_uop_5_frs3_en = stq_uop_3_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_4_frs3_en = stq_uop_3_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fcn_dw; // @[lsu.scala:252:32] wire s_uop_5_fcn_dw = stq_uop_3_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_4_fcn_dw = stq_uop_3_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_5_fcn_op = stq_uop_3_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_fcn_op = stq_uop_3_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_val; // @[lsu.scala:252:32] wire s_uop_5_fp_val = stq_uop_3_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_val = stq_uop_3_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_5_fp_rm = stq_uop_3_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_fp_rm = stq_uop_3_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_5_fp_typ = stq_uop_3_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_fp_typ = stq_uop_3_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_5_xcpt_pf_if = stq_uop_3_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_xcpt_pf_if = stq_uop_3_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_5_xcpt_ae_if = stq_uop_3_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_xcpt_ae_if = stq_uop_3_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_5_xcpt_ma_if = stq_uop_3_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_xcpt_ma_if = stq_uop_3_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_5_bp_debug_if = stq_uop_3_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_bp_debug_if = stq_uop_3_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_5_bp_xcpt_if = stq_uop_3_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_bp_xcpt_if = stq_uop_3_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_5_debug_fsrc = stq_uop_3_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_debug_fsrc = stq_uop_3_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_5_debug_tsrc = stq_uop_3_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_debug_tsrc = stq_uop_3_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_4_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_6_inst = stq_uop_4_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_5_inst = stq_uop_4_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_4_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_6_debug_inst = stq_uop_4_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_5_debug_inst = stq_uop_4_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_rvc; // @[lsu.scala:252:32] wire s_uop_6_is_rvc = stq_uop_4_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_rvc = stq_uop_4_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_4_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_6_debug_pc = stq_uop_4_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_5_debug_pc = stq_uop_4_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_0; // @[lsu.scala:252:32] wire s_uop_6_iq_type_0 = stq_uop_4_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_0 = stq_uop_4_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_1; // @[lsu.scala:252:32] wire s_uop_6_iq_type_1 = stq_uop_4_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_1 = stq_uop_4_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_2; // @[lsu.scala:252:32] wire s_uop_6_iq_type_2 = stq_uop_4_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_2 = stq_uop_4_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_3; // @[lsu.scala:252:32] wire s_uop_6_iq_type_3 = stq_uop_4_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_3 = stq_uop_4_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_0; // @[lsu.scala:252:32] wire s_uop_6_fu_code_0 = stq_uop_4_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_0 = stq_uop_4_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_1; // @[lsu.scala:252:32] wire s_uop_6_fu_code_1 = stq_uop_4_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_1 = stq_uop_4_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_2; // @[lsu.scala:252:32] wire s_uop_6_fu_code_2 = stq_uop_4_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_2 = stq_uop_4_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_3; // @[lsu.scala:252:32] wire s_uop_6_fu_code_3 = stq_uop_4_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_3 = stq_uop_4_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_4; // @[lsu.scala:252:32] wire s_uop_6_fu_code_4 = stq_uop_4_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_4 = stq_uop_4_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_5; // @[lsu.scala:252:32] wire s_uop_6_fu_code_5 = stq_uop_4_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_5 = stq_uop_4_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_6; // @[lsu.scala:252:32] wire s_uop_6_fu_code_6 = stq_uop_4_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_6 = stq_uop_4_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_7; // @[lsu.scala:252:32] wire s_uop_6_fu_code_7 = stq_uop_4_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_7 = stq_uop_4_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_8; // @[lsu.scala:252:32] wire s_uop_6_fu_code_8 = stq_uop_4_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_8 = stq_uop_4_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_9; // @[lsu.scala:252:32] wire s_uop_6_fu_code_9 = stq_uop_4_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_9 = stq_uop_4_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_issued; // @[lsu.scala:252:32] wire s_uop_6_iw_issued = stq_uop_4_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_issued = stq_uop_4_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_6_iw_issued_partial_agen = stq_uop_4_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_issued_partial_agen = stq_uop_4_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_6_iw_issued_partial_dgen = stq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_issued_partial_dgen = stq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_6_iw_p1_speculative_child = stq_uop_4_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_iw_p1_speculative_child = stq_uop_4_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_6_iw_p2_speculative_child = stq_uop_4_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_iw_p2_speculative_child = stq_uop_4_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_6_iw_p1_bypass_hint = stq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_p1_bypass_hint = stq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_6_iw_p2_bypass_hint = stq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_p2_bypass_hint = stq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_6_iw_p3_bypass_hint = stq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_p3_bypass_hint = stq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_6_dis_col_sel = stq_uop_4_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_dis_col_sel = stq_uop_4_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_4_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_6_br_mask = stq_uop_4_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_5_br_mask = stq_uop_4_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_4_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_6_br_tag = stq_uop_4_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_5_br_tag = stq_uop_4_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_4_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_6_br_type = stq_uop_4_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_5_br_type = stq_uop_4_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_sfb; // @[lsu.scala:252:32] wire s_uop_6_is_sfb = stq_uop_4_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_sfb = stq_uop_4_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_fence; // @[lsu.scala:252:32] wire s_uop_6_is_fence = stq_uop_4_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_fence = stq_uop_4_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_fencei; // @[lsu.scala:252:32] wire s_uop_6_is_fencei = stq_uop_4_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_fencei = stq_uop_4_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_sfence; // @[lsu.scala:252:32] wire s_uop_6_is_sfence = stq_uop_4_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_sfence = stq_uop_4_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_amo; // @[lsu.scala:252:32] wire s_uop_6_is_amo = stq_uop_4_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_amo = stq_uop_4_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_eret; // @[lsu.scala:252:32] wire s_uop_6_is_eret = stq_uop_4_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_eret = stq_uop_4_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_6_is_sys_pc2epc = stq_uop_4_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_sys_pc2epc = stq_uop_4_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_rocc; // @[lsu.scala:252:32] wire s_uop_6_is_rocc = stq_uop_4_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_rocc = stq_uop_4_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_mov; // @[lsu.scala:252:32] wire s_uop_6_is_mov = stq_uop_4_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_mov = stq_uop_4_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_6_ftq_idx = stq_uop_4_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_ftq_idx = stq_uop_4_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_edge_inst; // @[lsu.scala:252:32] wire s_uop_6_edge_inst = stq_uop_4_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_5_edge_inst = stq_uop_4_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_6_pc_lob = stq_uop_4_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_pc_lob = stq_uop_4_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_taken; // @[lsu.scala:252:32] wire s_uop_6_taken = stq_uop_4_taken; // @[lsu.scala:252:32, :1324:37] wire uop_5_taken = stq_uop_4_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_imm_rename; // @[lsu.scala:252:32] wire s_uop_6_imm_rename = stq_uop_4_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_5_imm_rename = stq_uop_4_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_6_imm_sel = stq_uop_4_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_imm_sel = stq_uop_4_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_6_pimm = stq_uop_4_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_pimm = stq_uop_4_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_4_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_6_imm_packed = stq_uop_4_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_5_imm_packed = stq_uop_4_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_6_op1_sel = stq_uop_4_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_op1_sel = stq_uop_4_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_6_op2_sel = stq_uop_4_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_op2_sel = stq_uop_4_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ldst = stq_uop_4_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ldst = stq_uop_4_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_wen = stq_uop_4_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_wen = stq_uop_4_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ren1 = stq_uop_4_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ren1 = stq_uop_4_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ren2 = stq_uop_4_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ren2 = stq_uop_4_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ren3 = stq_uop_4_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ren3 = stq_uop_4_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_swap12 = stq_uop_4_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_swap12 = stq_uop_4_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_swap23 = stq_uop_4_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_swap23 = stq_uop_4_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_6_fp_ctrl_typeTagIn = stq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_fp_ctrl_typeTagIn = stq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_6_fp_ctrl_typeTagOut = stq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_fp_ctrl_typeTagOut = stq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_fromint = stq_uop_4_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_fromint = stq_uop_4_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_toint = stq_uop_4_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_toint = stq_uop_4_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_fastpipe = stq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_fastpipe = stq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_fma = stq_uop_4_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_fma = stq_uop_4_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_div = stq_uop_4_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_div = stq_uop_4_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_sqrt = stq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_sqrt = stq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_wflags = stq_uop_4_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_wflags = stq_uop_4_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_vec = stq_uop_4_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_vec = stq_uop_4_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_6_rob_idx = stq_uop_4_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_rob_idx = stq_uop_4_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_4_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_6_ldq_idx = stq_uop_4_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_5_ldq_idx = stq_uop_4_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_4_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_6_stq_idx = stq_uop_4_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_5_stq_idx = stq_uop_4_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_6_rxq_idx = stq_uop_4_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_rxq_idx = stq_uop_4_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_6_pdst = stq_uop_4_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_pdst = stq_uop_4_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_6_prs1 = stq_uop_4_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_prs1 = stq_uop_4_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_6_prs2 = stq_uop_4_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_prs2 = stq_uop_4_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_6_prs3 = stq_uop_4_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_prs3 = stq_uop_4_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_6_ppred = stq_uop_4_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_ppred = stq_uop_4_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_prs1_busy; // @[lsu.scala:252:32] wire s_uop_6_prs1_busy = stq_uop_4_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_prs1_busy = stq_uop_4_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_prs2_busy; // @[lsu.scala:252:32] wire s_uop_6_prs2_busy = stq_uop_4_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_prs2_busy = stq_uop_4_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_prs3_busy; // @[lsu.scala:252:32] wire s_uop_6_prs3_busy = stq_uop_4_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_prs3_busy = stq_uop_4_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_ppred_busy; // @[lsu.scala:252:32] wire s_uop_6_ppred_busy = stq_uop_4_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_ppred_busy = stq_uop_4_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_6_stale_pdst = stq_uop_4_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_stale_pdst = stq_uop_4_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_exception; // @[lsu.scala:252:32] wire s_uop_6_exception = stq_uop_4_exception; // @[lsu.scala:252:32, :1324:37] wire uop_5_exception = stq_uop_4_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_4_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_6_exc_cause = stq_uop_4_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_5_exc_cause = stq_uop_4_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_6_mem_cmd = stq_uop_4_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_mem_cmd = stq_uop_4_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_6_mem_size = stq_uop_4_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_mem_size = stq_uop_4_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_mem_signed; // @[lsu.scala:252:32] wire s_uop_6_mem_signed = stq_uop_4_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_5_mem_signed = stq_uop_4_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_uses_ldq; // @[lsu.scala:252:32] wire s_uop_6_uses_ldq = stq_uop_4_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_5_uses_ldq = stq_uop_4_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_uses_stq; // @[lsu.scala:252:32] wire s_uop_6_uses_stq = stq_uop_4_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_5_uses_stq = stq_uop_4_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_unique; // @[lsu.scala:252:32] wire s_uop_6_is_unique = stq_uop_4_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_unique = stq_uop_4_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_6_flush_on_commit = stq_uop_4_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_5_flush_on_commit = stq_uop_4_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_6_csr_cmd = stq_uop_4_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_csr_cmd = stq_uop_4_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_6_ldst_is_rs1 = stq_uop_4_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_5_ldst_is_rs1 = stq_uop_4_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_6_ldst = stq_uop_4_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_ldst = stq_uop_4_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_6_lrs1 = stq_uop_4_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_lrs1 = stq_uop_4_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_6_lrs2 = stq_uop_4_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_lrs2 = stq_uop_4_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_6_lrs3 = stq_uop_4_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_lrs3 = stq_uop_4_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_6_dst_rtype = stq_uop_4_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_dst_rtype = stq_uop_4_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_6_lrs1_rtype = stq_uop_4_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_lrs1_rtype = stq_uop_4_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_6_lrs2_rtype = stq_uop_4_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_lrs2_rtype = stq_uop_4_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_frs3_en; // @[lsu.scala:252:32] wire s_uop_6_frs3_en = stq_uop_4_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_5_frs3_en = stq_uop_4_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fcn_dw; // @[lsu.scala:252:32] wire s_uop_6_fcn_dw = stq_uop_4_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_5_fcn_dw = stq_uop_4_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_6_fcn_op = stq_uop_4_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_fcn_op = stq_uop_4_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_val; // @[lsu.scala:252:32] wire s_uop_6_fp_val = stq_uop_4_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_val = stq_uop_4_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_6_fp_rm = stq_uop_4_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_fp_rm = stq_uop_4_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_6_fp_typ = stq_uop_4_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_fp_typ = stq_uop_4_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_6_xcpt_pf_if = stq_uop_4_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_xcpt_pf_if = stq_uop_4_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_6_xcpt_ae_if = stq_uop_4_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_xcpt_ae_if = stq_uop_4_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_6_xcpt_ma_if = stq_uop_4_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_xcpt_ma_if = stq_uop_4_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_6_bp_debug_if = stq_uop_4_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_bp_debug_if = stq_uop_4_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_6_bp_xcpt_if = stq_uop_4_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_bp_xcpt_if = stq_uop_4_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_6_debug_fsrc = stq_uop_4_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_debug_fsrc = stq_uop_4_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_6_debug_tsrc = stq_uop_4_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_debug_tsrc = stq_uop_4_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_5_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_7_inst = stq_uop_5_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_6_inst = stq_uop_5_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_5_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_7_debug_inst = stq_uop_5_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_6_debug_inst = stq_uop_5_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_rvc; // @[lsu.scala:252:32] wire s_uop_7_is_rvc = stq_uop_5_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_rvc = stq_uop_5_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_5_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_7_debug_pc = stq_uop_5_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_6_debug_pc = stq_uop_5_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_0; // @[lsu.scala:252:32] wire s_uop_7_iq_type_0 = stq_uop_5_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_0 = stq_uop_5_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_1; // @[lsu.scala:252:32] wire s_uop_7_iq_type_1 = stq_uop_5_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_1 = stq_uop_5_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_2; // @[lsu.scala:252:32] wire s_uop_7_iq_type_2 = stq_uop_5_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_2 = stq_uop_5_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_3; // @[lsu.scala:252:32] wire s_uop_7_iq_type_3 = stq_uop_5_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_3 = stq_uop_5_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_0; // @[lsu.scala:252:32] wire s_uop_7_fu_code_0 = stq_uop_5_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_0 = stq_uop_5_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_1; // @[lsu.scala:252:32] wire s_uop_7_fu_code_1 = stq_uop_5_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_1 = stq_uop_5_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_2; // @[lsu.scala:252:32] wire s_uop_7_fu_code_2 = stq_uop_5_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_2 = stq_uop_5_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_3; // @[lsu.scala:252:32] wire s_uop_7_fu_code_3 = stq_uop_5_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_3 = stq_uop_5_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_4; // @[lsu.scala:252:32] wire s_uop_7_fu_code_4 = stq_uop_5_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_4 = stq_uop_5_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_5; // @[lsu.scala:252:32] wire s_uop_7_fu_code_5 = stq_uop_5_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_5 = stq_uop_5_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_6; // @[lsu.scala:252:32] wire s_uop_7_fu_code_6 = stq_uop_5_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_6 = stq_uop_5_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_7; // @[lsu.scala:252:32] wire s_uop_7_fu_code_7 = stq_uop_5_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_7 = stq_uop_5_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_8; // @[lsu.scala:252:32] wire s_uop_7_fu_code_8 = stq_uop_5_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_8 = stq_uop_5_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_9; // @[lsu.scala:252:32] wire s_uop_7_fu_code_9 = stq_uop_5_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_9 = stq_uop_5_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_issued; // @[lsu.scala:252:32] wire s_uop_7_iw_issued = stq_uop_5_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_issued = stq_uop_5_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_7_iw_issued_partial_agen = stq_uop_5_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_issued_partial_agen = stq_uop_5_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_7_iw_issued_partial_dgen = stq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_issued_partial_dgen = stq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_7_iw_p1_speculative_child = stq_uop_5_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_iw_p1_speculative_child = stq_uop_5_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_7_iw_p2_speculative_child = stq_uop_5_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_iw_p2_speculative_child = stq_uop_5_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_7_iw_p1_bypass_hint = stq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_p1_bypass_hint = stq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_7_iw_p2_bypass_hint = stq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_p2_bypass_hint = stq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_7_iw_p3_bypass_hint = stq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_p3_bypass_hint = stq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_7_dis_col_sel = stq_uop_5_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_dis_col_sel = stq_uop_5_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_5_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_7_br_mask = stq_uop_5_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_6_br_mask = stq_uop_5_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_5_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_7_br_tag = stq_uop_5_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_6_br_tag = stq_uop_5_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_5_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_7_br_type = stq_uop_5_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_6_br_type = stq_uop_5_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_sfb; // @[lsu.scala:252:32] wire s_uop_7_is_sfb = stq_uop_5_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_sfb = stq_uop_5_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_fence; // @[lsu.scala:252:32] wire s_uop_7_is_fence = stq_uop_5_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_fence = stq_uop_5_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_fencei; // @[lsu.scala:252:32] wire s_uop_7_is_fencei = stq_uop_5_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_fencei = stq_uop_5_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_sfence; // @[lsu.scala:252:32] wire s_uop_7_is_sfence = stq_uop_5_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_sfence = stq_uop_5_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_amo; // @[lsu.scala:252:32] wire s_uop_7_is_amo = stq_uop_5_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_amo = stq_uop_5_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_eret; // @[lsu.scala:252:32] wire s_uop_7_is_eret = stq_uop_5_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_eret = stq_uop_5_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_7_is_sys_pc2epc = stq_uop_5_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_sys_pc2epc = stq_uop_5_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_rocc; // @[lsu.scala:252:32] wire s_uop_7_is_rocc = stq_uop_5_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_rocc = stq_uop_5_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_mov; // @[lsu.scala:252:32] wire s_uop_7_is_mov = stq_uop_5_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_mov = stq_uop_5_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_7_ftq_idx = stq_uop_5_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_ftq_idx = stq_uop_5_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_edge_inst; // @[lsu.scala:252:32] wire s_uop_7_edge_inst = stq_uop_5_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_6_edge_inst = stq_uop_5_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_7_pc_lob = stq_uop_5_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_pc_lob = stq_uop_5_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_taken; // @[lsu.scala:252:32] wire s_uop_7_taken = stq_uop_5_taken; // @[lsu.scala:252:32, :1324:37] wire uop_6_taken = stq_uop_5_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_imm_rename; // @[lsu.scala:252:32] wire s_uop_7_imm_rename = stq_uop_5_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_6_imm_rename = stq_uop_5_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_7_imm_sel = stq_uop_5_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_imm_sel = stq_uop_5_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_7_pimm = stq_uop_5_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_pimm = stq_uop_5_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_5_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_7_imm_packed = stq_uop_5_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_6_imm_packed = stq_uop_5_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_7_op1_sel = stq_uop_5_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_op1_sel = stq_uop_5_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_7_op2_sel = stq_uop_5_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_op2_sel = stq_uop_5_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ldst = stq_uop_5_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ldst = stq_uop_5_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_wen = stq_uop_5_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_wen = stq_uop_5_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ren1 = stq_uop_5_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ren1 = stq_uop_5_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ren2 = stq_uop_5_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ren2 = stq_uop_5_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ren3 = stq_uop_5_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ren3 = stq_uop_5_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_swap12 = stq_uop_5_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_swap12 = stq_uop_5_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_swap23 = stq_uop_5_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_swap23 = stq_uop_5_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_7_fp_ctrl_typeTagIn = stq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_fp_ctrl_typeTagIn = stq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_7_fp_ctrl_typeTagOut = stq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_fp_ctrl_typeTagOut = stq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_fromint = stq_uop_5_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_fromint = stq_uop_5_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_toint = stq_uop_5_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_toint = stq_uop_5_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_fastpipe = stq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_fastpipe = stq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_fma = stq_uop_5_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_fma = stq_uop_5_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_div = stq_uop_5_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_div = stq_uop_5_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_sqrt = stq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_sqrt = stq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_wflags = stq_uop_5_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_wflags = stq_uop_5_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_vec = stq_uop_5_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_vec = stq_uop_5_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_7_rob_idx = stq_uop_5_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_rob_idx = stq_uop_5_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_5_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_7_ldq_idx = stq_uop_5_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_6_ldq_idx = stq_uop_5_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_5_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_7_stq_idx = stq_uop_5_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_6_stq_idx = stq_uop_5_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_7_rxq_idx = stq_uop_5_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_rxq_idx = stq_uop_5_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_7_pdst = stq_uop_5_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_pdst = stq_uop_5_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_7_prs1 = stq_uop_5_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_prs1 = stq_uop_5_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_7_prs2 = stq_uop_5_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_prs2 = stq_uop_5_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_7_prs3 = stq_uop_5_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_prs3 = stq_uop_5_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_7_ppred = stq_uop_5_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_ppred = stq_uop_5_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_prs1_busy; // @[lsu.scala:252:32] wire s_uop_7_prs1_busy = stq_uop_5_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_prs1_busy = stq_uop_5_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_prs2_busy; // @[lsu.scala:252:32] wire s_uop_7_prs2_busy = stq_uop_5_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_prs2_busy = stq_uop_5_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_prs3_busy; // @[lsu.scala:252:32] wire s_uop_7_prs3_busy = stq_uop_5_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_prs3_busy = stq_uop_5_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_ppred_busy; // @[lsu.scala:252:32] wire s_uop_7_ppred_busy = stq_uop_5_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_ppred_busy = stq_uop_5_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_7_stale_pdst = stq_uop_5_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_stale_pdst = stq_uop_5_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_exception; // @[lsu.scala:252:32] wire s_uop_7_exception = stq_uop_5_exception; // @[lsu.scala:252:32, :1324:37] wire uop_6_exception = stq_uop_5_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_5_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_7_exc_cause = stq_uop_5_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_6_exc_cause = stq_uop_5_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_7_mem_cmd = stq_uop_5_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_mem_cmd = stq_uop_5_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_7_mem_size = stq_uop_5_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_mem_size = stq_uop_5_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_mem_signed; // @[lsu.scala:252:32] wire s_uop_7_mem_signed = stq_uop_5_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_6_mem_signed = stq_uop_5_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_uses_ldq; // @[lsu.scala:252:32] wire s_uop_7_uses_ldq = stq_uop_5_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_6_uses_ldq = stq_uop_5_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_uses_stq; // @[lsu.scala:252:32] wire s_uop_7_uses_stq = stq_uop_5_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_6_uses_stq = stq_uop_5_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_unique; // @[lsu.scala:252:32] wire s_uop_7_is_unique = stq_uop_5_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_unique = stq_uop_5_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_7_flush_on_commit = stq_uop_5_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_6_flush_on_commit = stq_uop_5_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_7_csr_cmd = stq_uop_5_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_csr_cmd = stq_uop_5_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_7_ldst_is_rs1 = stq_uop_5_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_6_ldst_is_rs1 = stq_uop_5_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_7_ldst = stq_uop_5_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_ldst = stq_uop_5_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_7_lrs1 = stq_uop_5_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_lrs1 = stq_uop_5_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_7_lrs2 = stq_uop_5_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_lrs2 = stq_uop_5_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_7_lrs3 = stq_uop_5_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_lrs3 = stq_uop_5_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_7_dst_rtype = stq_uop_5_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_dst_rtype = stq_uop_5_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_7_lrs1_rtype = stq_uop_5_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_lrs1_rtype = stq_uop_5_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_7_lrs2_rtype = stq_uop_5_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_lrs2_rtype = stq_uop_5_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_frs3_en; // @[lsu.scala:252:32] wire s_uop_7_frs3_en = stq_uop_5_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_6_frs3_en = stq_uop_5_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fcn_dw; // @[lsu.scala:252:32] wire s_uop_7_fcn_dw = stq_uop_5_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_6_fcn_dw = stq_uop_5_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_7_fcn_op = stq_uop_5_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_fcn_op = stq_uop_5_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_val; // @[lsu.scala:252:32] wire s_uop_7_fp_val = stq_uop_5_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_val = stq_uop_5_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_7_fp_rm = stq_uop_5_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_fp_rm = stq_uop_5_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_7_fp_typ = stq_uop_5_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_fp_typ = stq_uop_5_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_7_xcpt_pf_if = stq_uop_5_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_xcpt_pf_if = stq_uop_5_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_7_xcpt_ae_if = stq_uop_5_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_xcpt_ae_if = stq_uop_5_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_7_xcpt_ma_if = stq_uop_5_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_xcpt_ma_if = stq_uop_5_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_7_bp_debug_if = stq_uop_5_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_bp_debug_if = stq_uop_5_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_7_bp_xcpt_if = stq_uop_5_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_bp_xcpt_if = stq_uop_5_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_7_debug_fsrc = stq_uop_5_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_debug_fsrc = stq_uop_5_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_7_debug_tsrc = stq_uop_5_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_debug_tsrc = stq_uop_5_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_6_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_8_inst = stq_uop_6_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_7_inst = stq_uop_6_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_6_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_8_debug_inst = stq_uop_6_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_7_debug_inst = stq_uop_6_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_rvc; // @[lsu.scala:252:32] wire s_uop_8_is_rvc = stq_uop_6_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_rvc = stq_uop_6_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_6_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_8_debug_pc = stq_uop_6_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_7_debug_pc = stq_uop_6_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_0; // @[lsu.scala:252:32] wire s_uop_8_iq_type_0 = stq_uop_6_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_0 = stq_uop_6_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_1; // @[lsu.scala:252:32] wire s_uop_8_iq_type_1 = stq_uop_6_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_1 = stq_uop_6_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_2; // @[lsu.scala:252:32] wire s_uop_8_iq_type_2 = stq_uop_6_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_2 = stq_uop_6_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_3; // @[lsu.scala:252:32] wire s_uop_8_iq_type_3 = stq_uop_6_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_3 = stq_uop_6_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_0; // @[lsu.scala:252:32] wire s_uop_8_fu_code_0 = stq_uop_6_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_0 = stq_uop_6_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_1; // @[lsu.scala:252:32] wire s_uop_8_fu_code_1 = stq_uop_6_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_1 = stq_uop_6_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_2; // @[lsu.scala:252:32] wire s_uop_8_fu_code_2 = stq_uop_6_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_2 = stq_uop_6_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_3; // @[lsu.scala:252:32] wire s_uop_8_fu_code_3 = stq_uop_6_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_3 = stq_uop_6_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_4; // @[lsu.scala:252:32] wire s_uop_8_fu_code_4 = stq_uop_6_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_4 = stq_uop_6_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_5; // @[lsu.scala:252:32] wire s_uop_8_fu_code_5 = stq_uop_6_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_5 = stq_uop_6_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_6; // @[lsu.scala:252:32] wire s_uop_8_fu_code_6 = stq_uop_6_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_6 = stq_uop_6_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_7; // @[lsu.scala:252:32] wire s_uop_8_fu_code_7 = stq_uop_6_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_7 = stq_uop_6_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_8; // @[lsu.scala:252:32] wire s_uop_8_fu_code_8 = stq_uop_6_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_8 = stq_uop_6_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_9; // @[lsu.scala:252:32] wire s_uop_8_fu_code_9 = stq_uop_6_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_9 = stq_uop_6_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_issued; // @[lsu.scala:252:32] wire s_uop_8_iw_issued = stq_uop_6_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_issued = stq_uop_6_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_8_iw_issued_partial_agen = stq_uop_6_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_issued_partial_agen = stq_uop_6_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_8_iw_issued_partial_dgen = stq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_issued_partial_dgen = stq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_8_iw_p1_speculative_child = stq_uop_6_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_iw_p1_speculative_child = stq_uop_6_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_8_iw_p2_speculative_child = stq_uop_6_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_iw_p2_speculative_child = stq_uop_6_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_8_iw_p1_bypass_hint = stq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_p1_bypass_hint = stq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_8_iw_p2_bypass_hint = stq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_p2_bypass_hint = stq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_8_iw_p3_bypass_hint = stq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_p3_bypass_hint = stq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_8_dis_col_sel = stq_uop_6_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_dis_col_sel = stq_uop_6_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_6_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_8_br_mask = stq_uop_6_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_7_br_mask = stq_uop_6_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_6_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_8_br_tag = stq_uop_6_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_7_br_tag = stq_uop_6_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_6_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_8_br_type = stq_uop_6_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_7_br_type = stq_uop_6_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_sfb; // @[lsu.scala:252:32] wire s_uop_8_is_sfb = stq_uop_6_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_sfb = stq_uop_6_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_fence; // @[lsu.scala:252:32] wire s_uop_8_is_fence = stq_uop_6_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_fence = stq_uop_6_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_fencei; // @[lsu.scala:252:32] wire s_uop_8_is_fencei = stq_uop_6_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_fencei = stq_uop_6_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_sfence; // @[lsu.scala:252:32] wire s_uop_8_is_sfence = stq_uop_6_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_sfence = stq_uop_6_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_amo; // @[lsu.scala:252:32] wire s_uop_8_is_amo = stq_uop_6_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_amo = stq_uop_6_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_eret; // @[lsu.scala:252:32] wire s_uop_8_is_eret = stq_uop_6_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_eret = stq_uop_6_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_8_is_sys_pc2epc = stq_uop_6_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_sys_pc2epc = stq_uop_6_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_rocc; // @[lsu.scala:252:32] wire s_uop_8_is_rocc = stq_uop_6_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_rocc = stq_uop_6_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_mov; // @[lsu.scala:252:32] wire s_uop_8_is_mov = stq_uop_6_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_mov = stq_uop_6_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_8_ftq_idx = stq_uop_6_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_ftq_idx = stq_uop_6_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_edge_inst; // @[lsu.scala:252:32] wire s_uop_8_edge_inst = stq_uop_6_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_7_edge_inst = stq_uop_6_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_8_pc_lob = stq_uop_6_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_pc_lob = stq_uop_6_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_taken; // @[lsu.scala:252:32] wire s_uop_8_taken = stq_uop_6_taken; // @[lsu.scala:252:32, :1324:37] wire uop_7_taken = stq_uop_6_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_imm_rename; // @[lsu.scala:252:32] wire s_uop_8_imm_rename = stq_uop_6_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_7_imm_rename = stq_uop_6_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_8_imm_sel = stq_uop_6_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_imm_sel = stq_uop_6_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_8_pimm = stq_uop_6_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_pimm = stq_uop_6_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_6_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_8_imm_packed = stq_uop_6_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_7_imm_packed = stq_uop_6_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_8_op1_sel = stq_uop_6_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_op1_sel = stq_uop_6_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_8_op2_sel = stq_uop_6_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_op2_sel = stq_uop_6_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ldst = stq_uop_6_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ldst = stq_uop_6_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_wen = stq_uop_6_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_wen = stq_uop_6_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ren1 = stq_uop_6_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ren1 = stq_uop_6_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ren2 = stq_uop_6_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ren2 = stq_uop_6_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ren3 = stq_uop_6_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ren3 = stq_uop_6_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_swap12 = stq_uop_6_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_swap12 = stq_uop_6_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_swap23 = stq_uop_6_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_swap23 = stq_uop_6_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_8_fp_ctrl_typeTagIn = stq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_fp_ctrl_typeTagIn = stq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_8_fp_ctrl_typeTagOut = stq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_fp_ctrl_typeTagOut = stq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_fromint = stq_uop_6_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_fromint = stq_uop_6_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_toint = stq_uop_6_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_toint = stq_uop_6_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_fastpipe = stq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_fastpipe = stq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_fma = stq_uop_6_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_fma = stq_uop_6_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_div = stq_uop_6_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_div = stq_uop_6_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_sqrt = stq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_sqrt = stq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_wflags = stq_uop_6_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_wflags = stq_uop_6_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_vec = stq_uop_6_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_vec = stq_uop_6_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_8_rob_idx = stq_uop_6_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_rob_idx = stq_uop_6_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_6_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_8_ldq_idx = stq_uop_6_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_7_ldq_idx = stq_uop_6_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_6_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_8_stq_idx = stq_uop_6_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_7_stq_idx = stq_uop_6_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_8_rxq_idx = stq_uop_6_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_rxq_idx = stq_uop_6_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_8_pdst = stq_uop_6_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_pdst = stq_uop_6_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_8_prs1 = stq_uop_6_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_prs1 = stq_uop_6_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_8_prs2 = stq_uop_6_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_prs2 = stq_uop_6_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_8_prs3 = stq_uop_6_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_prs3 = stq_uop_6_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_8_ppred = stq_uop_6_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_ppred = stq_uop_6_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_prs1_busy; // @[lsu.scala:252:32] wire s_uop_8_prs1_busy = stq_uop_6_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_prs1_busy = stq_uop_6_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_prs2_busy; // @[lsu.scala:252:32] wire s_uop_8_prs2_busy = stq_uop_6_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_prs2_busy = stq_uop_6_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_prs3_busy; // @[lsu.scala:252:32] wire s_uop_8_prs3_busy = stq_uop_6_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_prs3_busy = stq_uop_6_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_ppred_busy; // @[lsu.scala:252:32] wire s_uop_8_ppred_busy = stq_uop_6_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_ppred_busy = stq_uop_6_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_8_stale_pdst = stq_uop_6_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_stale_pdst = stq_uop_6_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_exception; // @[lsu.scala:252:32] wire s_uop_8_exception = stq_uop_6_exception; // @[lsu.scala:252:32, :1324:37] wire uop_7_exception = stq_uop_6_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_6_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_8_exc_cause = stq_uop_6_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_7_exc_cause = stq_uop_6_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_8_mem_cmd = stq_uop_6_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_mem_cmd = stq_uop_6_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_8_mem_size = stq_uop_6_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_mem_size = stq_uop_6_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_mem_signed; // @[lsu.scala:252:32] wire s_uop_8_mem_signed = stq_uop_6_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_7_mem_signed = stq_uop_6_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_uses_ldq; // @[lsu.scala:252:32] wire s_uop_8_uses_ldq = stq_uop_6_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_7_uses_ldq = stq_uop_6_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_uses_stq; // @[lsu.scala:252:32] wire s_uop_8_uses_stq = stq_uop_6_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_7_uses_stq = stq_uop_6_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_unique; // @[lsu.scala:252:32] wire s_uop_8_is_unique = stq_uop_6_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_unique = stq_uop_6_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_8_flush_on_commit = stq_uop_6_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_7_flush_on_commit = stq_uop_6_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_8_csr_cmd = stq_uop_6_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_csr_cmd = stq_uop_6_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_8_ldst_is_rs1 = stq_uop_6_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_7_ldst_is_rs1 = stq_uop_6_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_8_ldst = stq_uop_6_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_ldst = stq_uop_6_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_8_lrs1 = stq_uop_6_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_lrs1 = stq_uop_6_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_8_lrs2 = stq_uop_6_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_lrs2 = stq_uop_6_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_8_lrs3 = stq_uop_6_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_lrs3 = stq_uop_6_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_8_dst_rtype = stq_uop_6_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_dst_rtype = stq_uop_6_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_8_lrs1_rtype = stq_uop_6_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_lrs1_rtype = stq_uop_6_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_8_lrs2_rtype = stq_uop_6_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_lrs2_rtype = stq_uop_6_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_frs3_en; // @[lsu.scala:252:32] wire s_uop_8_frs3_en = stq_uop_6_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_7_frs3_en = stq_uop_6_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fcn_dw; // @[lsu.scala:252:32] wire s_uop_8_fcn_dw = stq_uop_6_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_7_fcn_dw = stq_uop_6_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_8_fcn_op = stq_uop_6_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_fcn_op = stq_uop_6_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_val; // @[lsu.scala:252:32] wire s_uop_8_fp_val = stq_uop_6_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_val = stq_uop_6_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_8_fp_rm = stq_uop_6_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_fp_rm = stq_uop_6_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_8_fp_typ = stq_uop_6_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_fp_typ = stq_uop_6_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_8_xcpt_pf_if = stq_uop_6_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_xcpt_pf_if = stq_uop_6_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_8_xcpt_ae_if = stq_uop_6_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_xcpt_ae_if = stq_uop_6_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_8_xcpt_ma_if = stq_uop_6_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_xcpt_ma_if = stq_uop_6_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_8_bp_debug_if = stq_uop_6_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_bp_debug_if = stq_uop_6_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_8_bp_xcpt_if = stq_uop_6_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_bp_xcpt_if = stq_uop_6_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_8_debug_fsrc = stq_uop_6_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_debug_fsrc = stq_uop_6_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_8_debug_tsrc = stq_uop_6_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_debug_tsrc = stq_uop_6_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_7_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_9_inst = stq_uop_7_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_8_inst = stq_uop_7_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_7_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_9_debug_inst = stq_uop_7_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_8_debug_inst = stq_uop_7_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_rvc; // @[lsu.scala:252:32] wire s_uop_9_is_rvc = stq_uop_7_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_rvc = stq_uop_7_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_7_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_9_debug_pc = stq_uop_7_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_8_debug_pc = stq_uop_7_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_0; // @[lsu.scala:252:32] wire s_uop_9_iq_type_0 = stq_uop_7_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_0 = stq_uop_7_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_1; // @[lsu.scala:252:32] wire s_uop_9_iq_type_1 = stq_uop_7_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_1 = stq_uop_7_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_2; // @[lsu.scala:252:32] wire s_uop_9_iq_type_2 = stq_uop_7_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_2 = stq_uop_7_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_3; // @[lsu.scala:252:32] wire s_uop_9_iq_type_3 = stq_uop_7_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_3 = stq_uop_7_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_0; // @[lsu.scala:252:32] wire s_uop_9_fu_code_0 = stq_uop_7_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_0 = stq_uop_7_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_1; // @[lsu.scala:252:32] wire s_uop_9_fu_code_1 = stq_uop_7_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_1 = stq_uop_7_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_2; // @[lsu.scala:252:32] wire s_uop_9_fu_code_2 = stq_uop_7_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_2 = stq_uop_7_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_3; // @[lsu.scala:252:32] wire s_uop_9_fu_code_3 = stq_uop_7_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_3 = stq_uop_7_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_4; // @[lsu.scala:252:32] wire s_uop_9_fu_code_4 = stq_uop_7_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_4 = stq_uop_7_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_5; // @[lsu.scala:252:32] wire s_uop_9_fu_code_5 = stq_uop_7_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_5 = stq_uop_7_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_6; // @[lsu.scala:252:32] wire s_uop_9_fu_code_6 = stq_uop_7_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_6 = stq_uop_7_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_7; // @[lsu.scala:252:32] wire s_uop_9_fu_code_7 = stq_uop_7_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_7 = stq_uop_7_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_8; // @[lsu.scala:252:32] wire s_uop_9_fu_code_8 = stq_uop_7_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_8 = stq_uop_7_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_9; // @[lsu.scala:252:32] wire s_uop_9_fu_code_9 = stq_uop_7_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_9 = stq_uop_7_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_issued; // @[lsu.scala:252:32] wire s_uop_9_iw_issued = stq_uop_7_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_issued = stq_uop_7_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_9_iw_issued_partial_agen = stq_uop_7_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_issued_partial_agen = stq_uop_7_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_9_iw_issued_partial_dgen = stq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_issued_partial_dgen = stq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_9_iw_p1_speculative_child = stq_uop_7_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_iw_p1_speculative_child = stq_uop_7_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_9_iw_p2_speculative_child = stq_uop_7_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_iw_p2_speculative_child = stq_uop_7_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_9_iw_p1_bypass_hint = stq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_p1_bypass_hint = stq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_9_iw_p2_bypass_hint = stq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_p2_bypass_hint = stq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_9_iw_p3_bypass_hint = stq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_p3_bypass_hint = stq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_9_dis_col_sel = stq_uop_7_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_dis_col_sel = stq_uop_7_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_7_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_9_br_mask = stq_uop_7_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_8_br_mask = stq_uop_7_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_7_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_9_br_tag = stq_uop_7_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_8_br_tag = stq_uop_7_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_7_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_9_br_type = stq_uop_7_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_8_br_type = stq_uop_7_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_sfb; // @[lsu.scala:252:32] wire s_uop_9_is_sfb = stq_uop_7_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_sfb = stq_uop_7_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_fence; // @[lsu.scala:252:32] wire s_uop_9_is_fence = stq_uop_7_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_fence = stq_uop_7_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_fencei; // @[lsu.scala:252:32] wire s_uop_9_is_fencei = stq_uop_7_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_fencei = stq_uop_7_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_sfence; // @[lsu.scala:252:32] wire s_uop_9_is_sfence = stq_uop_7_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_sfence = stq_uop_7_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_amo; // @[lsu.scala:252:32] wire s_uop_9_is_amo = stq_uop_7_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_amo = stq_uop_7_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_eret; // @[lsu.scala:252:32] wire s_uop_9_is_eret = stq_uop_7_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_eret = stq_uop_7_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_9_is_sys_pc2epc = stq_uop_7_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_sys_pc2epc = stq_uop_7_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_rocc; // @[lsu.scala:252:32] wire s_uop_9_is_rocc = stq_uop_7_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_rocc = stq_uop_7_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_mov; // @[lsu.scala:252:32] wire s_uop_9_is_mov = stq_uop_7_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_mov = stq_uop_7_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_9_ftq_idx = stq_uop_7_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_ftq_idx = stq_uop_7_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_edge_inst; // @[lsu.scala:252:32] wire s_uop_9_edge_inst = stq_uop_7_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_8_edge_inst = stq_uop_7_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_9_pc_lob = stq_uop_7_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_pc_lob = stq_uop_7_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_taken; // @[lsu.scala:252:32] wire s_uop_9_taken = stq_uop_7_taken; // @[lsu.scala:252:32, :1324:37] wire uop_8_taken = stq_uop_7_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_imm_rename; // @[lsu.scala:252:32] wire s_uop_9_imm_rename = stq_uop_7_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_8_imm_rename = stq_uop_7_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_9_imm_sel = stq_uop_7_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_imm_sel = stq_uop_7_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_9_pimm = stq_uop_7_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_pimm = stq_uop_7_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_7_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_9_imm_packed = stq_uop_7_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_8_imm_packed = stq_uop_7_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_9_op1_sel = stq_uop_7_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_op1_sel = stq_uop_7_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_9_op2_sel = stq_uop_7_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_op2_sel = stq_uop_7_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ldst = stq_uop_7_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ldst = stq_uop_7_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_wen = stq_uop_7_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_wen = stq_uop_7_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ren1 = stq_uop_7_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ren1 = stq_uop_7_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ren2 = stq_uop_7_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ren2 = stq_uop_7_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ren3 = stq_uop_7_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ren3 = stq_uop_7_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_swap12 = stq_uop_7_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_swap12 = stq_uop_7_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_swap23 = stq_uop_7_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_swap23 = stq_uop_7_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_9_fp_ctrl_typeTagIn = stq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_fp_ctrl_typeTagIn = stq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_9_fp_ctrl_typeTagOut = stq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_fp_ctrl_typeTagOut = stq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_fromint = stq_uop_7_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_fromint = stq_uop_7_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_toint = stq_uop_7_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_toint = stq_uop_7_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_fastpipe = stq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_fastpipe = stq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_fma = stq_uop_7_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_fma = stq_uop_7_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_div = stq_uop_7_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_div = stq_uop_7_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_sqrt = stq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_sqrt = stq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_wflags = stq_uop_7_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_wflags = stq_uop_7_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_vec = stq_uop_7_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_vec = stq_uop_7_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_9_rob_idx = stq_uop_7_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_rob_idx = stq_uop_7_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_7_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_9_ldq_idx = stq_uop_7_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_8_ldq_idx = stq_uop_7_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_7_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_9_stq_idx = stq_uop_7_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_8_stq_idx = stq_uop_7_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_9_rxq_idx = stq_uop_7_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_rxq_idx = stq_uop_7_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_9_pdst = stq_uop_7_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_pdst = stq_uop_7_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_9_prs1 = stq_uop_7_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_prs1 = stq_uop_7_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_9_prs2 = stq_uop_7_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_prs2 = stq_uop_7_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_9_prs3 = stq_uop_7_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_prs3 = stq_uop_7_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_9_ppred = stq_uop_7_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_ppred = stq_uop_7_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_prs1_busy; // @[lsu.scala:252:32] wire s_uop_9_prs1_busy = stq_uop_7_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_prs1_busy = stq_uop_7_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_prs2_busy; // @[lsu.scala:252:32] wire s_uop_9_prs2_busy = stq_uop_7_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_prs2_busy = stq_uop_7_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_prs3_busy; // @[lsu.scala:252:32] wire s_uop_9_prs3_busy = stq_uop_7_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_prs3_busy = stq_uop_7_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_ppred_busy; // @[lsu.scala:252:32] wire s_uop_9_ppred_busy = stq_uop_7_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_ppred_busy = stq_uop_7_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_9_stale_pdst = stq_uop_7_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_stale_pdst = stq_uop_7_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_exception; // @[lsu.scala:252:32] wire s_uop_9_exception = stq_uop_7_exception; // @[lsu.scala:252:32, :1324:37] wire uop_8_exception = stq_uop_7_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_7_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_9_exc_cause = stq_uop_7_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_8_exc_cause = stq_uop_7_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_9_mem_cmd = stq_uop_7_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_mem_cmd = stq_uop_7_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_9_mem_size = stq_uop_7_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_mem_size = stq_uop_7_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_mem_signed; // @[lsu.scala:252:32] wire s_uop_9_mem_signed = stq_uop_7_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_8_mem_signed = stq_uop_7_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_uses_ldq; // @[lsu.scala:252:32] wire s_uop_9_uses_ldq = stq_uop_7_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_8_uses_ldq = stq_uop_7_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_uses_stq; // @[lsu.scala:252:32] wire s_uop_9_uses_stq = stq_uop_7_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_8_uses_stq = stq_uop_7_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_unique; // @[lsu.scala:252:32] wire s_uop_9_is_unique = stq_uop_7_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_unique = stq_uop_7_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_9_flush_on_commit = stq_uop_7_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_8_flush_on_commit = stq_uop_7_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_9_csr_cmd = stq_uop_7_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_csr_cmd = stq_uop_7_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_9_ldst_is_rs1 = stq_uop_7_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_8_ldst_is_rs1 = stq_uop_7_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_9_ldst = stq_uop_7_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_ldst = stq_uop_7_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_9_lrs1 = stq_uop_7_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_lrs1 = stq_uop_7_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_9_lrs2 = stq_uop_7_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_lrs2 = stq_uop_7_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_9_lrs3 = stq_uop_7_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_lrs3 = stq_uop_7_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_9_dst_rtype = stq_uop_7_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_dst_rtype = stq_uop_7_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_9_lrs1_rtype = stq_uop_7_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_lrs1_rtype = stq_uop_7_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_9_lrs2_rtype = stq_uop_7_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_lrs2_rtype = stq_uop_7_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_frs3_en; // @[lsu.scala:252:32] wire s_uop_9_frs3_en = stq_uop_7_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_8_frs3_en = stq_uop_7_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fcn_dw; // @[lsu.scala:252:32] wire s_uop_9_fcn_dw = stq_uop_7_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_8_fcn_dw = stq_uop_7_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_9_fcn_op = stq_uop_7_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_fcn_op = stq_uop_7_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_val; // @[lsu.scala:252:32] wire s_uop_9_fp_val = stq_uop_7_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_val = stq_uop_7_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_9_fp_rm = stq_uop_7_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_fp_rm = stq_uop_7_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_9_fp_typ = stq_uop_7_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_fp_typ = stq_uop_7_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_9_xcpt_pf_if = stq_uop_7_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_xcpt_pf_if = stq_uop_7_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_9_xcpt_ae_if = stq_uop_7_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_xcpt_ae_if = stq_uop_7_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_9_xcpt_ma_if = stq_uop_7_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_xcpt_ma_if = stq_uop_7_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_9_bp_debug_if = stq_uop_7_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_bp_debug_if = stq_uop_7_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_9_bp_xcpt_if = stq_uop_7_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_bp_xcpt_if = stq_uop_7_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_9_debug_fsrc = stq_uop_7_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_debug_fsrc = stq_uop_7_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_9_debug_tsrc = stq_uop_7_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_debug_tsrc = stq_uop_7_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_8_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_10_inst = stq_uop_8_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_9_inst = stq_uop_8_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_8_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_10_debug_inst = stq_uop_8_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_9_debug_inst = stq_uop_8_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_rvc; // @[lsu.scala:252:32] wire s_uop_10_is_rvc = stq_uop_8_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_rvc = stq_uop_8_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_8_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_10_debug_pc = stq_uop_8_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_9_debug_pc = stq_uop_8_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_0; // @[lsu.scala:252:32] wire s_uop_10_iq_type_0 = stq_uop_8_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_0 = stq_uop_8_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_1; // @[lsu.scala:252:32] wire s_uop_10_iq_type_1 = stq_uop_8_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_1 = stq_uop_8_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_2; // @[lsu.scala:252:32] wire s_uop_10_iq_type_2 = stq_uop_8_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_2 = stq_uop_8_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_3; // @[lsu.scala:252:32] wire s_uop_10_iq_type_3 = stq_uop_8_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_3 = stq_uop_8_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_0; // @[lsu.scala:252:32] wire s_uop_10_fu_code_0 = stq_uop_8_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_0 = stq_uop_8_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_1; // @[lsu.scala:252:32] wire s_uop_10_fu_code_1 = stq_uop_8_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_1 = stq_uop_8_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_2; // @[lsu.scala:252:32] wire s_uop_10_fu_code_2 = stq_uop_8_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_2 = stq_uop_8_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_3; // @[lsu.scala:252:32] wire s_uop_10_fu_code_3 = stq_uop_8_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_3 = stq_uop_8_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_4; // @[lsu.scala:252:32] wire s_uop_10_fu_code_4 = stq_uop_8_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_4 = stq_uop_8_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_5; // @[lsu.scala:252:32] wire s_uop_10_fu_code_5 = stq_uop_8_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_5 = stq_uop_8_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_6; // @[lsu.scala:252:32] wire s_uop_10_fu_code_6 = stq_uop_8_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_6 = stq_uop_8_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_7; // @[lsu.scala:252:32] wire s_uop_10_fu_code_7 = stq_uop_8_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_7 = stq_uop_8_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_8; // @[lsu.scala:252:32] wire s_uop_10_fu_code_8 = stq_uop_8_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_8 = stq_uop_8_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_9; // @[lsu.scala:252:32] wire s_uop_10_fu_code_9 = stq_uop_8_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_9 = stq_uop_8_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_issued; // @[lsu.scala:252:32] wire s_uop_10_iw_issued = stq_uop_8_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_issued = stq_uop_8_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_10_iw_issued_partial_agen = stq_uop_8_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_issued_partial_agen = stq_uop_8_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_10_iw_issued_partial_dgen = stq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_issued_partial_dgen = stq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_10_iw_p1_speculative_child = stq_uop_8_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_iw_p1_speculative_child = stq_uop_8_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_10_iw_p2_speculative_child = stq_uop_8_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_iw_p2_speculative_child = stq_uop_8_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_10_iw_p1_bypass_hint = stq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_p1_bypass_hint = stq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_10_iw_p2_bypass_hint = stq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_p2_bypass_hint = stq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_10_iw_p3_bypass_hint = stq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_p3_bypass_hint = stq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_10_dis_col_sel = stq_uop_8_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_dis_col_sel = stq_uop_8_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_8_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_10_br_mask = stq_uop_8_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_9_br_mask = stq_uop_8_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_8_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_10_br_tag = stq_uop_8_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_9_br_tag = stq_uop_8_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_8_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_10_br_type = stq_uop_8_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_9_br_type = stq_uop_8_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_sfb; // @[lsu.scala:252:32] wire s_uop_10_is_sfb = stq_uop_8_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_sfb = stq_uop_8_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_fence; // @[lsu.scala:252:32] wire s_uop_10_is_fence = stq_uop_8_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_fence = stq_uop_8_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_fencei; // @[lsu.scala:252:32] wire s_uop_10_is_fencei = stq_uop_8_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_fencei = stq_uop_8_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_sfence; // @[lsu.scala:252:32] wire s_uop_10_is_sfence = stq_uop_8_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_sfence = stq_uop_8_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_amo; // @[lsu.scala:252:32] wire s_uop_10_is_amo = stq_uop_8_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_amo = stq_uop_8_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_eret; // @[lsu.scala:252:32] wire s_uop_10_is_eret = stq_uop_8_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_eret = stq_uop_8_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_10_is_sys_pc2epc = stq_uop_8_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_sys_pc2epc = stq_uop_8_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_rocc; // @[lsu.scala:252:32] wire s_uop_10_is_rocc = stq_uop_8_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_rocc = stq_uop_8_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_mov; // @[lsu.scala:252:32] wire s_uop_10_is_mov = stq_uop_8_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_mov = stq_uop_8_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_10_ftq_idx = stq_uop_8_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_ftq_idx = stq_uop_8_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_edge_inst; // @[lsu.scala:252:32] wire s_uop_10_edge_inst = stq_uop_8_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_9_edge_inst = stq_uop_8_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_10_pc_lob = stq_uop_8_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_pc_lob = stq_uop_8_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_taken; // @[lsu.scala:252:32] wire s_uop_10_taken = stq_uop_8_taken; // @[lsu.scala:252:32, :1324:37] wire uop_9_taken = stq_uop_8_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_imm_rename; // @[lsu.scala:252:32] wire s_uop_10_imm_rename = stq_uop_8_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_9_imm_rename = stq_uop_8_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_10_imm_sel = stq_uop_8_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_imm_sel = stq_uop_8_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_10_pimm = stq_uop_8_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_pimm = stq_uop_8_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_8_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_10_imm_packed = stq_uop_8_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_9_imm_packed = stq_uop_8_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_10_op1_sel = stq_uop_8_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_op1_sel = stq_uop_8_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_10_op2_sel = stq_uop_8_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_op2_sel = stq_uop_8_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ldst = stq_uop_8_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ldst = stq_uop_8_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_wen = stq_uop_8_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_wen = stq_uop_8_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ren1 = stq_uop_8_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ren1 = stq_uop_8_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ren2 = stq_uop_8_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ren2 = stq_uop_8_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ren3 = stq_uop_8_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ren3 = stq_uop_8_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_swap12 = stq_uop_8_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_swap12 = stq_uop_8_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_swap23 = stq_uop_8_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_swap23 = stq_uop_8_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_10_fp_ctrl_typeTagIn = stq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_fp_ctrl_typeTagIn = stq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_10_fp_ctrl_typeTagOut = stq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_fp_ctrl_typeTagOut = stq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_fromint = stq_uop_8_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_fromint = stq_uop_8_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_toint = stq_uop_8_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_toint = stq_uop_8_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_fastpipe = stq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_fastpipe = stq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_fma = stq_uop_8_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_fma = stq_uop_8_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_div = stq_uop_8_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_div = stq_uop_8_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_sqrt = stq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_sqrt = stq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_wflags = stq_uop_8_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_wflags = stq_uop_8_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_vec = stq_uop_8_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_vec = stq_uop_8_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_10_rob_idx = stq_uop_8_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_rob_idx = stq_uop_8_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_8_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_10_ldq_idx = stq_uop_8_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_9_ldq_idx = stq_uop_8_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_8_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_10_stq_idx = stq_uop_8_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_9_stq_idx = stq_uop_8_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_10_rxq_idx = stq_uop_8_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_rxq_idx = stq_uop_8_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_10_pdst = stq_uop_8_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_pdst = stq_uop_8_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_10_prs1 = stq_uop_8_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_prs1 = stq_uop_8_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_10_prs2 = stq_uop_8_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_prs2 = stq_uop_8_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_10_prs3 = stq_uop_8_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_prs3 = stq_uop_8_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_10_ppred = stq_uop_8_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_ppred = stq_uop_8_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_prs1_busy; // @[lsu.scala:252:32] wire s_uop_10_prs1_busy = stq_uop_8_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_prs1_busy = stq_uop_8_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_prs2_busy; // @[lsu.scala:252:32] wire s_uop_10_prs2_busy = stq_uop_8_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_prs2_busy = stq_uop_8_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_prs3_busy; // @[lsu.scala:252:32] wire s_uop_10_prs3_busy = stq_uop_8_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_prs3_busy = stq_uop_8_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_ppred_busy; // @[lsu.scala:252:32] wire s_uop_10_ppred_busy = stq_uop_8_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_ppred_busy = stq_uop_8_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_10_stale_pdst = stq_uop_8_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_stale_pdst = stq_uop_8_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_exception; // @[lsu.scala:252:32] wire s_uop_10_exception = stq_uop_8_exception; // @[lsu.scala:252:32, :1324:37] wire uop_9_exception = stq_uop_8_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_8_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_10_exc_cause = stq_uop_8_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_9_exc_cause = stq_uop_8_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_10_mem_cmd = stq_uop_8_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_mem_cmd = stq_uop_8_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_10_mem_size = stq_uop_8_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_mem_size = stq_uop_8_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_mem_signed; // @[lsu.scala:252:32] wire s_uop_10_mem_signed = stq_uop_8_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_9_mem_signed = stq_uop_8_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_uses_ldq; // @[lsu.scala:252:32] wire s_uop_10_uses_ldq = stq_uop_8_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_9_uses_ldq = stq_uop_8_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_uses_stq; // @[lsu.scala:252:32] wire s_uop_10_uses_stq = stq_uop_8_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_9_uses_stq = stq_uop_8_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_unique; // @[lsu.scala:252:32] wire s_uop_10_is_unique = stq_uop_8_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_unique = stq_uop_8_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_10_flush_on_commit = stq_uop_8_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_9_flush_on_commit = stq_uop_8_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_10_csr_cmd = stq_uop_8_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_csr_cmd = stq_uop_8_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_10_ldst_is_rs1 = stq_uop_8_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_9_ldst_is_rs1 = stq_uop_8_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_10_ldst = stq_uop_8_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_ldst = stq_uop_8_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_10_lrs1 = stq_uop_8_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_lrs1 = stq_uop_8_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_10_lrs2 = stq_uop_8_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_lrs2 = stq_uop_8_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_10_lrs3 = stq_uop_8_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_lrs3 = stq_uop_8_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_10_dst_rtype = stq_uop_8_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_dst_rtype = stq_uop_8_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_10_lrs1_rtype = stq_uop_8_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_lrs1_rtype = stq_uop_8_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_10_lrs2_rtype = stq_uop_8_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_lrs2_rtype = stq_uop_8_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_frs3_en; // @[lsu.scala:252:32] wire s_uop_10_frs3_en = stq_uop_8_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_9_frs3_en = stq_uop_8_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fcn_dw; // @[lsu.scala:252:32] wire s_uop_10_fcn_dw = stq_uop_8_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_9_fcn_dw = stq_uop_8_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_10_fcn_op = stq_uop_8_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_fcn_op = stq_uop_8_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_val; // @[lsu.scala:252:32] wire s_uop_10_fp_val = stq_uop_8_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_val = stq_uop_8_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_10_fp_rm = stq_uop_8_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_fp_rm = stq_uop_8_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_10_fp_typ = stq_uop_8_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_fp_typ = stq_uop_8_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_10_xcpt_pf_if = stq_uop_8_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_xcpt_pf_if = stq_uop_8_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_10_xcpt_ae_if = stq_uop_8_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_xcpt_ae_if = stq_uop_8_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_10_xcpt_ma_if = stq_uop_8_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_xcpt_ma_if = stq_uop_8_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_10_bp_debug_if = stq_uop_8_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_bp_debug_if = stq_uop_8_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_10_bp_xcpt_if = stq_uop_8_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_bp_xcpt_if = stq_uop_8_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_10_debug_fsrc = stq_uop_8_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_debug_fsrc = stq_uop_8_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_10_debug_tsrc = stq_uop_8_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_debug_tsrc = stq_uop_8_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_9_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_11_inst = stq_uop_9_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_10_inst = stq_uop_9_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_9_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_11_debug_inst = stq_uop_9_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_10_debug_inst = stq_uop_9_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_rvc; // @[lsu.scala:252:32] wire s_uop_11_is_rvc = stq_uop_9_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_rvc = stq_uop_9_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_9_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_11_debug_pc = stq_uop_9_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_10_debug_pc = stq_uop_9_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_0; // @[lsu.scala:252:32] wire s_uop_11_iq_type_0 = stq_uop_9_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_0 = stq_uop_9_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_1; // @[lsu.scala:252:32] wire s_uop_11_iq_type_1 = stq_uop_9_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_1 = stq_uop_9_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_2; // @[lsu.scala:252:32] wire s_uop_11_iq_type_2 = stq_uop_9_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_2 = stq_uop_9_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_3; // @[lsu.scala:252:32] wire s_uop_11_iq_type_3 = stq_uop_9_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_3 = stq_uop_9_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_0; // @[lsu.scala:252:32] wire s_uop_11_fu_code_0 = stq_uop_9_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_0 = stq_uop_9_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_1; // @[lsu.scala:252:32] wire s_uop_11_fu_code_1 = stq_uop_9_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_1 = stq_uop_9_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_2; // @[lsu.scala:252:32] wire s_uop_11_fu_code_2 = stq_uop_9_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_2 = stq_uop_9_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_3; // @[lsu.scala:252:32] wire s_uop_11_fu_code_3 = stq_uop_9_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_3 = stq_uop_9_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_4; // @[lsu.scala:252:32] wire s_uop_11_fu_code_4 = stq_uop_9_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_4 = stq_uop_9_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_5; // @[lsu.scala:252:32] wire s_uop_11_fu_code_5 = stq_uop_9_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_5 = stq_uop_9_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_6; // @[lsu.scala:252:32] wire s_uop_11_fu_code_6 = stq_uop_9_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_6 = stq_uop_9_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_7; // @[lsu.scala:252:32] wire s_uop_11_fu_code_7 = stq_uop_9_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_7 = stq_uop_9_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_8; // @[lsu.scala:252:32] wire s_uop_11_fu_code_8 = stq_uop_9_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_8 = stq_uop_9_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_9; // @[lsu.scala:252:32] wire s_uop_11_fu_code_9 = stq_uop_9_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_9 = stq_uop_9_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_issued; // @[lsu.scala:252:32] wire s_uop_11_iw_issued = stq_uop_9_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_issued = stq_uop_9_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_11_iw_issued_partial_agen = stq_uop_9_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_issued_partial_agen = stq_uop_9_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_11_iw_issued_partial_dgen = stq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_issued_partial_dgen = stq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_11_iw_p1_speculative_child = stq_uop_9_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_iw_p1_speculative_child = stq_uop_9_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_11_iw_p2_speculative_child = stq_uop_9_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_iw_p2_speculative_child = stq_uop_9_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_11_iw_p1_bypass_hint = stq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_p1_bypass_hint = stq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_11_iw_p2_bypass_hint = stq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_p2_bypass_hint = stq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_11_iw_p3_bypass_hint = stq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_p3_bypass_hint = stq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_11_dis_col_sel = stq_uop_9_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_dis_col_sel = stq_uop_9_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_9_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_11_br_mask = stq_uop_9_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_10_br_mask = stq_uop_9_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_9_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_11_br_tag = stq_uop_9_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_10_br_tag = stq_uop_9_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_9_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_11_br_type = stq_uop_9_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_10_br_type = stq_uop_9_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_sfb; // @[lsu.scala:252:32] wire s_uop_11_is_sfb = stq_uop_9_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_sfb = stq_uop_9_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_fence; // @[lsu.scala:252:32] wire s_uop_11_is_fence = stq_uop_9_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_fence = stq_uop_9_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_fencei; // @[lsu.scala:252:32] wire s_uop_11_is_fencei = stq_uop_9_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_fencei = stq_uop_9_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_sfence; // @[lsu.scala:252:32] wire s_uop_11_is_sfence = stq_uop_9_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_sfence = stq_uop_9_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_amo; // @[lsu.scala:252:32] wire s_uop_11_is_amo = stq_uop_9_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_amo = stq_uop_9_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_eret; // @[lsu.scala:252:32] wire s_uop_11_is_eret = stq_uop_9_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_eret = stq_uop_9_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_11_is_sys_pc2epc = stq_uop_9_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_sys_pc2epc = stq_uop_9_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_rocc; // @[lsu.scala:252:32] wire s_uop_11_is_rocc = stq_uop_9_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_rocc = stq_uop_9_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_mov; // @[lsu.scala:252:32] wire s_uop_11_is_mov = stq_uop_9_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_mov = stq_uop_9_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_11_ftq_idx = stq_uop_9_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_ftq_idx = stq_uop_9_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_edge_inst; // @[lsu.scala:252:32] wire s_uop_11_edge_inst = stq_uop_9_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_10_edge_inst = stq_uop_9_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_11_pc_lob = stq_uop_9_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_pc_lob = stq_uop_9_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_taken; // @[lsu.scala:252:32] wire s_uop_11_taken = stq_uop_9_taken; // @[lsu.scala:252:32, :1324:37] wire uop_10_taken = stq_uop_9_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_imm_rename; // @[lsu.scala:252:32] wire s_uop_11_imm_rename = stq_uop_9_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_10_imm_rename = stq_uop_9_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_11_imm_sel = stq_uop_9_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_imm_sel = stq_uop_9_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_11_pimm = stq_uop_9_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_pimm = stq_uop_9_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_9_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_11_imm_packed = stq_uop_9_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_10_imm_packed = stq_uop_9_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_11_op1_sel = stq_uop_9_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_op1_sel = stq_uop_9_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_11_op2_sel = stq_uop_9_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_op2_sel = stq_uop_9_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ldst = stq_uop_9_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ldst = stq_uop_9_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_wen = stq_uop_9_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_wen = stq_uop_9_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ren1 = stq_uop_9_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ren1 = stq_uop_9_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ren2 = stq_uop_9_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ren2 = stq_uop_9_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ren3 = stq_uop_9_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ren3 = stq_uop_9_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_swap12 = stq_uop_9_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_swap12 = stq_uop_9_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_swap23 = stq_uop_9_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_swap23 = stq_uop_9_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_11_fp_ctrl_typeTagIn = stq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_fp_ctrl_typeTagIn = stq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_11_fp_ctrl_typeTagOut = stq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_fp_ctrl_typeTagOut = stq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_fromint = stq_uop_9_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_fromint = stq_uop_9_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_toint = stq_uop_9_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_toint = stq_uop_9_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_fastpipe = stq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_fastpipe = stq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_fma = stq_uop_9_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_fma = stq_uop_9_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_div = stq_uop_9_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_div = stq_uop_9_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_sqrt = stq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_sqrt = stq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_wflags = stq_uop_9_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_wflags = stq_uop_9_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_vec = stq_uop_9_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_vec = stq_uop_9_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_11_rob_idx = stq_uop_9_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_rob_idx = stq_uop_9_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_9_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_11_ldq_idx = stq_uop_9_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_10_ldq_idx = stq_uop_9_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_9_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_11_stq_idx = stq_uop_9_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_10_stq_idx = stq_uop_9_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_11_rxq_idx = stq_uop_9_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_rxq_idx = stq_uop_9_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_11_pdst = stq_uop_9_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_pdst = stq_uop_9_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_11_prs1 = stq_uop_9_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_prs1 = stq_uop_9_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_11_prs2 = stq_uop_9_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_prs2 = stq_uop_9_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_11_prs3 = stq_uop_9_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_prs3 = stq_uop_9_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_11_ppred = stq_uop_9_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_ppred = stq_uop_9_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_prs1_busy; // @[lsu.scala:252:32] wire s_uop_11_prs1_busy = stq_uop_9_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_prs1_busy = stq_uop_9_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_prs2_busy; // @[lsu.scala:252:32] wire s_uop_11_prs2_busy = stq_uop_9_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_prs2_busy = stq_uop_9_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_prs3_busy; // @[lsu.scala:252:32] wire s_uop_11_prs3_busy = stq_uop_9_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_prs3_busy = stq_uop_9_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_ppred_busy; // @[lsu.scala:252:32] wire s_uop_11_ppred_busy = stq_uop_9_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_ppred_busy = stq_uop_9_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_11_stale_pdst = stq_uop_9_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_stale_pdst = stq_uop_9_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_exception; // @[lsu.scala:252:32] wire s_uop_11_exception = stq_uop_9_exception; // @[lsu.scala:252:32, :1324:37] wire uop_10_exception = stq_uop_9_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_9_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_11_exc_cause = stq_uop_9_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_10_exc_cause = stq_uop_9_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_11_mem_cmd = stq_uop_9_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_mem_cmd = stq_uop_9_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_11_mem_size = stq_uop_9_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_mem_size = stq_uop_9_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_mem_signed; // @[lsu.scala:252:32] wire s_uop_11_mem_signed = stq_uop_9_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_10_mem_signed = stq_uop_9_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_uses_ldq; // @[lsu.scala:252:32] wire s_uop_11_uses_ldq = stq_uop_9_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_10_uses_ldq = stq_uop_9_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_uses_stq; // @[lsu.scala:252:32] wire s_uop_11_uses_stq = stq_uop_9_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_10_uses_stq = stq_uop_9_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_unique; // @[lsu.scala:252:32] wire s_uop_11_is_unique = stq_uop_9_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_unique = stq_uop_9_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_11_flush_on_commit = stq_uop_9_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_10_flush_on_commit = stq_uop_9_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_11_csr_cmd = stq_uop_9_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_csr_cmd = stq_uop_9_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_11_ldst_is_rs1 = stq_uop_9_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_10_ldst_is_rs1 = stq_uop_9_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_11_ldst = stq_uop_9_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_ldst = stq_uop_9_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_11_lrs1 = stq_uop_9_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_lrs1 = stq_uop_9_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_11_lrs2 = stq_uop_9_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_lrs2 = stq_uop_9_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_11_lrs3 = stq_uop_9_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_lrs3 = stq_uop_9_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_11_dst_rtype = stq_uop_9_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_dst_rtype = stq_uop_9_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_11_lrs1_rtype = stq_uop_9_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_lrs1_rtype = stq_uop_9_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_11_lrs2_rtype = stq_uop_9_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_lrs2_rtype = stq_uop_9_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_frs3_en; // @[lsu.scala:252:32] wire s_uop_11_frs3_en = stq_uop_9_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_10_frs3_en = stq_uop_9_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fcn_dw; // @[lsu.scala:252:32] wire s_uop_11_fcn_dw = stq_uop_9_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_10_fcn_dw = stq_uop_9_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_11_fcn_op = stq_uop_9_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_fcn_op = stq_uop_9_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_val; // @[lsu.scala:252:32] wire s_uop_11_fp_val = stq_uop_9_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_val = stq_uop_9_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_11_fp_rm = stq_uop_9_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_fp_rm = stq_uop_9_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_11_fp_typ = stq_uop_9_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_fp_typ = stq_uop_9_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_11_xcpt_pf_if = stq_uop_9_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_xcpt_pf_if = stq_uop_9_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_11_xcpt_ae_if = stq_uop_9_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_xcpt_ae_if = stq_uop_9_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_11_xcpt_ma_if = stq_uop_9_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_xcpt_ma_if = stq_uop_9_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_11_bp_debug_if = stq_uop_9_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_bp_debug_if = stq_uop_9_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_11_bp_xcpt_if = stq_uop_9_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_bp_xcpt_if = stq_uop_9_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_11_debug_fsrc = stq_uop_9_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_debug_fsrc = stq_uop_9_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_11_debug_tsrc = stq_uop_9_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_debug_tsrc = stq_uop_9_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_10_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_12_inst = stq_uop_10_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_11_inst = stq_uop_10_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_10_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_12_debug_inst = stq_uop_10_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_11_debug_inst = stq_uop_10_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_rvc; // @[lsu.scala:252:32] wire s_uop_12_is_rvc = stq_uop_10_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_rvc = stq_uop_10_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_10_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_12_debug_pc = stq_uop_10_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_11_debug_pc = stq_uop_10_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_0; // @[lsu.scala:252:32] wire s_uop_12_iq_type_0 = stq_uop_10_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_0 = stq_uop_10_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_1; // @[lsu.scala:252:32] wire s_uop_12_iq_type_1 = stq_uop_10_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_1 = stq_uop_10_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_2; // @[lsu.scala:252:32] wire s_uop_12_iq_type_2 = stq_uop_10_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_2 = stq_uop_10_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_3; // @[lsu.scala:252:32] wire s_uop_12_iq_type_3 = stq_uop_10_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_3 = stq_uop_10_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_0; // @[lsu.scala:252:32] wire s_uop_12_fu_code_0 = stq_uop_10_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_0 = stq_uop_10_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_1; // @[lsu.scala:252:32] wire s_uop_12_fu_code_1 = stq_uop_10_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_1 = stq_uop_10_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_2; // @[lsu.scala:252:32] wire s_uop_12_fu_code_2 = stq_uop_10_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_2 = stq_uop_10_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_3; // @[lsu.scala:252:32] wire s_uop_12_fu_code_3 = stq_uop_10_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_3 = stq_uop_10_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_4; // @[lsu.scala:252:32] wire s_uop_12_fu_code_4 = stq_uop_10_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_4 = stq_uop_10_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_5; // @[lsu.scala:252:32] wire s_uop_12_fu_code_5 = stq_uop_10_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_5 = stq_uop_10_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_6; // @[lsu.scala:252:32] wire s_uop_12_fu_code_6 = stq_uop_10_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_6 = stq_uop_10_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_7; // @[lsu.scala:252:32] wire s_uop_12_fu_code_7 = stq_uop_10_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_7 = stq_uop_10_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_8; // @[lsu.scala:252:32] wire s_uop_12_fu_code_8 = stq_uop_10_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_8 = stq_uop_10_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_9; // @[lsu.scala:252:32] wire s_uop_12_fu_code_9 = stq_uop_10_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_9 = stq_uop_10_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_issued; // @[lsu.scala:252:32] wire s_uop_12_iw_issued = stq_uop_10_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_issued = stq_uop_10_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_12_iw_issued_partial_agen = stq_uop_10_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_issued_partial_agen = stq_uop_10_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_12_iw_issued_partial_dgen = stq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_issued_partial_dgen = stq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_12_iw_p1_speculative_child = stq_uop_10_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_iw_p1_speculative_child = stq_uop_10_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_12_iw_p2_speculative_child = stq_uop_10_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_iw_p2_speculative_child = stq_uop_10_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_12_iw_p1_bypass_hint = stq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_p1_bypass_hint = stq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_12_iw_p2_bypass_hint = stq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_p2_bypass_hint = stq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_12_iw_p3_bypass_hint = stq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_p3_bypass_hint = stq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_12_dis_col_sel = stq_uop_10_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_dis_col_sel = stq_uop_10_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_10_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_12_br_mask = stq_uop_10_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_11_br_mask = stq_uop_10_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_10_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_12_br_tag = stq_uop_10_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_11_br_tag = stq_uop_10_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_10_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_12_br_type = stq_uop_10_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_11_br_type = stq_uop_10_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_sfb; // @[lsu.scala:252:32] wire s_uop_12_is_sfb = stq_uop_10_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_sfb = stq_uop_10_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_fence; // @[lsu.scala:252:32] wire s_uop_12_is_fence = stq_uop_10_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_fence = stq_uop_10_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_fencei; // @[lsu.scala:252:32] wire s_uop_12_is_fencei = stq_uop_10_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_fencei = stq_uop_10_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_sfence; // @[lsu.scala:252:32] wire s_uop_12_is_sfence = stq_uop_10_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_sfence = stq_uop_10_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_amo; // @[lsu.scala:252:32] wire s_uop_12_is_amo = stq_uop_10_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_amo = stq_uop_10_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_eret; // @[lsu.scala:252:32] wire s_uop_12_is_eret = stq_uop_10_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_eret = stq_uop_10_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_12_is_sys_pc2epc = stq_uop_10_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_sys_pc2epc = stq_uop_10_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_rocc; // @[lsu.scala:252:32] wire s_uop_12_is_rocc = stq_uop_10_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_rocc = stq_uop_10_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_mov; // @[lsu.scala:252:32] wire s_uop_12_is_mov = stq_uop_10_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_mov = stq_uop_10_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_12_ftq_idx = stq_uop_10_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_ftq_idx = stq_uop_10_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_edge_inst; // @[lsu.scala:252:32] wire s_uop_12_edge_inst = stq_uop_10_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_11_edge_inst = stq_uop_10_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_12_pc_lob = stq_uop_10_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_pc_lob = stq_uop_10_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_taken; // @[lsu.scala:252:32] wire s_uop_12_taken = stq_uop_10_taken; // @[lsu.scala:252:32, :1324:37] wire uop_11_taken = stq_uop_10_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_imm_rename; // @[lsu.scala:252:32] wire s_uop_12_imm_rename = stq_uop_10_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_11_imm_rename = stq_uop_10_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_12_imm_sel = stq_uop_10_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_imm_sel = stq_uop_10_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_12_pimm = stq_uop_10_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_pimm = stq_uop_10_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_10_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_12_imm_packed = stq_uop_10_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_11_imm_packed = stq_uop_10_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_12_op1_sel = stq_uop_10_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_op1_sel = stq_uop_10_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_12_op2_sel = stq_uop_10_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_op2_sel = stq_uop_10_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ldst = stq_uop_10_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ldst = stq_uop_10_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_wen = stq_uop_10_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_wen = stq_uop_10_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ren1 = stq_uop_10_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ren1 = stq_uop_10_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ren2 = stq_uop_10_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ren2 = stq_uop_10_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ren3 = stq_uop_10_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ren3 = stq_uop_10_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_swap12 = stq_uop_10_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_swap12 = stq_uop_10_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_swap23 = stq_uop_10_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_swap23 = stq_uop_10_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_12_fp_ctrl_typeTagIn = stq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_fp_ctrl_typeTagIn = stq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_12_fp_ctrl_typeTagOut = stq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_fp_ctrl_typeTagOut = stq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_fromint = stq_uop_10_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_fromint = stq_uop_10_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_toint = stq_uop_10_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_toint = stq_uop_10_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_fastpipe = stq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_fastpipe = stq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_fma = stq_uop_10_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_fma = stq_uop_10_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_div = stq_uop_10_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_div = stq_uop_10_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_sqrt = stq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_sqrt = stq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_wflags = stq_uop_10_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_wflags = stq_uop_10_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_vec = stq_uop_10_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_vec = stq_uop_10_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_12_rob_idx = stq_uop_10_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_rob_idx = stq_uop_10_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_10_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_12_ldq_idx = stq_uop_10_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_11_ldq_idx = stq_uop_10_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_10_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_12_stq_idx = stq_uop_10_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_11_stq_idx = stq_uop_10_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_12_rxq_idx = stq_uop_10_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_rxq_idx = stq_uop_10_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_12_pdst = stq_uop_10_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_pdst = stq_uop_10_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_12_prs1 = stq_uop_10_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_prs1 = stq_uop_10_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_12_prs2 = stq_uop_10_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_prs2 = stq_uop_10_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_12_prs3 = stq_uop_10_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_prs3 = stq_uop_10_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_12_ppred = stq_uop_10_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_ppred = stq_uop_10_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_prs1_busy; // @[lsu.scala:252:32] wire s_uop_12_prs1_busy = stq_uop_10_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_prs1_busy = stq_uop_10_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_prs2_busy; // @[lsu.scala:252:32] wire s_uop_12_prs2_busy = stq_uop_10_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_prs2_busy = stq_uop_10_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_prs3_busy; // @[lsu.scala:252:32] wire s_uop_12_prs3_busy = stq_uop_10_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_prs3_busy = stq_uop_10_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_ppred_busy; // @[lsu.scala:252:32] wire s_uop_12_ppred_busy = stq_uop_10_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_ppred_busy = stq_uop_10_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_12_stale_pdst = stq_uop_10_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_stale_pdst = stq_uop_10_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_exception; // @[lsu.scala:252:32] wire s_uop_12_exception = stq_uop_10_exception; // @[lsu.scala:252:32, :1324:37] wire uop_11_exception = stq_uop_10_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_10_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_12_exc_cause = stq_uop_10_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_11_exc_cause = stq_uop_10_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_12_mem_cmd = stq_uop_10_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_mem_cmd = stq_uop_10_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_12_mem_size = stq_uop_10_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_mem_size = stq_uop_10_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_mem_signed; // @[lsu.scala:252:32] wire s_uop_12_mem_signed = stq_uop_10_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_11_mem_signed = stq_uop_10_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_uses_ldq; // @[lsu.scala:252:32] wire s_uop_12_uses_ldq = stq_uop_10_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_11_uses_ldq = stq_uop_10_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_uses_stq; // @[lsu.scala:252:32] wire s_uop_12_uses_stq = stq_uop_10_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_11_uses_stq = stq_uop_10_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_unique; // @[lsu.scala:252:32] wire s_uop_12_is_unique = stq_uop_10_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_unique = stq_uop_10_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_12_flush_on_commit = stq_uop_10_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_11_flush_on_commit = stq_uop_10_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_12_csr_cmd = stq_uop_10_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_csr_cmd = stq_uop_10_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_12_ldst_is_rs1 = stq_uop_10_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_11_ldst_is_rs1 = stq_uop_10_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_12_ldst = stq_uop_10_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_ldst = stq_uop_10_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_12_lrs1 = stq_uop_10_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_lrs1 = stq_uop_10_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_12_lrs2 = stq_uop_10_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_lrs2 = stq_uop_10_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_12_lrs3 = stq_uop_10_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_lrs3 = stq_uop_10_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_12_dst_rtype = stq_uop_10_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_dst_rtype = stq_uop_10_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_12_lrs1_rtype = stq_uop_10_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_lrs1_rtype = stq_uop_10_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_12_lrs2_rtype = stq_uop_10_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_lrs2_rtype = stq_uop_10_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_frs3_en; // @[lsu.scala:252:32] wire s_uop_12_frs3_en = stq_uop_10_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_11_frs3_en = stq_uop_10_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fcn_dw; // @[lsu.scala:252:32] wire s_uop_12_fcn_dw = stq_uop_10_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_11_fcn_dw = stq_uop_10_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_12_fcn_op = stq_uop_10_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_fcn_op = stq_uop_10_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_val; // @[lsu.scala:252:32] wire s_uop_12_fp_val = stq_uop_10_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_val = stq_uop_10_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_12_fp_rm = stq_uop_10_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_fp_rm = stq_uop_10_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_12_fp_typ = stq_uop_10_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_fp_typ = stq_uop_10_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_12_xcpt_pf_if = stq_uop_10_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_xcpt_pf_if = stq_uop_10_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_12_xcpt_ae_if = stq_uop_10_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_xcpt_ae_if = stq_uop_10_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_12_xcpt_ma_if = stq_uop_10_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_xcpt_ma_if = stq_uop_10_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_12_bp_debug_if = stq_uop_10_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_bp_debug_if = stq_uop_10_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_12_bp_xcpt_if = stq_uop_10_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_bp_xcpt_if = stq_uop_10_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_12_debug_fsrc = stq_uop_10_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_debug_fsrc = stq_uop_10_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_12_debug_tsrc = stq_uop_10_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_debug_tsrc = stq_uop_10_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_11_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_13_inst = stq_uop_11_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_12_inst = stq_uop_11_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_11_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_13_debug_inst = stq_uop_11_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_12_debug_inst = stq_uop_11_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_rvc; // @[lsu.scala:252:32] wire s_uop_13_is_rvc = stq_uop_11_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_rvc = stq_uop_11_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_11_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_13_debug_pc = stq_uop_11_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_12_debug_pc = stq_uop_11_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_0; // @[lsu.scala:252:32] wire s_uop_13_iq_type_0 = stq_uop_11_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_0 = stq_uop_11_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_1; // @[lsu.scala:252:32] wire s_uop_13_iq_type_1 = stq_uop_11_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_1 = stq_uop_11_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_2; // @[lsu.scala:252:32] wire s_uop_13_iq_type_2 = stq_uop_11_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_2 = stq_uop_11_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_3; // @[lsu.scala:252:32] wire s_uop_13_iq_type_3 = stq_uop_11_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_3 = stq_uop_11_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_0; // @[lsu.scala:252:32] wire s_uop_13_fu_code_0 = stq_uop_11_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_0 = stq_uop_11_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_1; // @[lsu.scala:252:32] wire s_uop_13_fu_code_1 = stq_uop_11_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_1 = stq_uop_11_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_2; // @[lsu.scala:252:32] wire s_uop_13_fu_code_2 = stq_uop_11_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_2 = stq_uop_11_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_3; // @[lsu.scala:252:32] wire s_uop_13_fu_code_3 = stq_uop_11_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_3 = stq_uop_11_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_4; // @[lsu.scala:252:32] wire s_uop_13_fu_code_4 = stq_uop_11_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_4 = stq_uop_11_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_5; // @[lsu.scala:252:32] wire s_uop_13_fu_code_5 = stq_uop_11_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_5 = stq_uop_11_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_6; // @[lsu.scala:252:32] wire s_uop_13_fu_code_6 = stq_uop_11_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_6 = stq_uop_11_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_7; // @[lsu.scala:252:32] wire s_uop_13_fu_code_7 = stq_uop_11_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_7 = stq_uop_11_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_8; // @[lsu.scala:252:32] wire s_uop_13_fu_code_8 = stq_uop_11_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_8 = stq_uop_11_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_9; // @[lsu.scala:252:32] wire s_uop_13_fu_code_9 = stq_uop_11_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_9 = stq_uop_11_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_issued; // @[lsu.scala:252:32] wire s_uop_13_iw_issued = stq_uop_11_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_issued = stq_uop_11_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_13_iw_issued_partial_agen = stq_uop_11_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_issued_partial_agen = stq_uop_11_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_13_iw_issued_partial_dgen = stq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_issued_partial_dgen = stq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_13_iw_p1_speculative_child = stq_uop_11_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_iw_p1_speculative_child = stq_uop_11_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_13_iw_p2_speculative_child = stq_uop_11_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_iw_p2_speculative_child = stq_uop_11_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_13_iw_p1_bypass_hint = stq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_p1_bypass_hint = stq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_13_iw_p2_bypass_hint = stq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_p2_bypass_hint = stq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_13_iw_p3_bypass_hint = stq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_p3_bypass_hint = stq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_13_dis_col_sel = stq_uop_11_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_dis_col_sel = stq_uop_11_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_11_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_13_br_mask = stq_uop_11_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_12_br_mask = stq_uop_11_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_11_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_13_br_tag = stq_uop_11_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_12_br_tag = stq_uop_11_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_11_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_13_br_type = stq_uop_11_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_12_br_type = stq_uop_11_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_sfb; // @[lsu.scala:252:32] wire s_uop_13_is_sfb = stq_uop_11_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_sfb = stq_uop_11_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_fence; // @[lsu.scala:252:32] wire s_uop_13_is_fence = stq_uop_11_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_fence = stq_uop_11_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_fencei; // @[lsu.scala:252:32] wire s_uop_13_is_fencei = stq_uop_11_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_fencei = stq_uop_11_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_sfence; // @[lsu.scala:252:32] wire s_uop_13_is_sfence = stq_uop_11_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_sfence = stq_uop_11_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_amo; // @[lsu.scala:252:32] wire s_uop_13_is_amo = stq_uop_11_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_amo = stq_uop_11_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_eret; // @[lsu.scala:252:32] wire s_uop_13_is_eret = stq_uop_11_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_eret = stq_uop_11_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_13_is_sys_pc2epc = stq_uop_11_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_sys_pc2epc = stq_uop_11_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_rocc; // @[lsu.scala:252:32] wire s_uop_13_is_rocc = stq_uop_11_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_rocc = stq_uop_11_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_mov; // @[lsu.scala:252:32] wire s_uop_13_is_mov = stq_uop_11_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_mov = stq_uop_11_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_13_ftq_idx = stq_uop_11_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_ftq_idx = stq_uop_11_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_edge_inst; // @[lsu.scala:252:32] wire s_uop_13_edge_inst = stq_uop_11_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_12_edge_inst = stq_uop_11_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_13_pc_lob = stq_uop_11_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_pc_lob = stq_uop_11_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_taken; // @[lsu.scala:252:32] wire s_uop_13_taken = stq_uop_11_taken; // @[lsu.scala:252:32, :1324:37] wire uop_12_taken = stq_uop_11_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_imm_rename; // @[lsu.scala:252:32] wire s_uop_13_imm_rename = stq_uop_11_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_12_imm_rename = stq_uop_11_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_13_imm_sel = stq_uop_11_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_imm_sel = stq_uop_11_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_13_pimm = stq_uop_11_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_pimm = stq_uop_11_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_11_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_13_imm_packed = stq_uop_11_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_12_imm_packed = stq_uop_11_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_13_op1_sel = stq_uop_11_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_op1_sel = stq_uop_11_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_13_op2_sel = stq_uop_11_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_op2_sel = stq_uop_11_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ldst = stq_uop_11_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ldst = stq_uop_11_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_wen = stq_uop_11_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_wen = stq_uop_11_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ren1 = stq_uop_11_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ren1 = stq_uop_11_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ren2 = stq_uop_11_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ren2 = stq_uop_11_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ren3 = stq_uop_11_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ren3 = stq_uop_11_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_swap12 = stq_uop_11_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_swap12 = stq_uop_11_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_swap23 = stq_uop_11_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_swap23 = stq_uop_11_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_13_fp_ctrl_typeTagIn = stq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_fp_ctrl_typeTagIn = stq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_13_fp_ctrl_typeTagOut = stq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_fp_ctrl_typeTagOut = stq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_fromint = stq_uop_11_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_fromint = stq_uop_11_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_toint = stq_uop_11_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_toint = stq_uop_11_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_fastpipe = stq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_fastpipe = stq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_fma = stq_uop_11_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_fma = stq_uop_11_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_div = stq_uop_11_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_div = stq_uop_11_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_sqrt = stq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_sqrt = stq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_wflags = stq_uop_11_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_wflags = stq_uop_11_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_vec = stq_uop_11_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_vec = stq_uop_11_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_13_rob_idx = stq_uop_11_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_rob_idx = stq_uop_11_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_11_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_13_ldq_idx = stq_uop_11_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_12_ldq_idx = stq_uop_11_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_11_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_13_stq_idx = stq_uop_11_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_12_stq_idx = stq_uop_11_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_13_rxq_idx = stq_uop_11_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_rxq_idx = stq_uop_11_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_13_pdst = stq_uop_11_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_pdst = stq_uop_11_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_13_prs1 = stq_uop_11_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_prs1 = stq_uop_11_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_13_prs2 = stq_uop_11_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_prs2 = stq_uop_11_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_13_prs3 = stq_uop_11_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_prs3 = stq_uop_11_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_13_ppred = stq_uop_11_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_ppred = stq_uop_11_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_prs1_busy; // @[lsu.scala:252:32] wire s_uop_13_prs1_busy = stq_uop_11_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_prs1_busy = stq_uop_11_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_prs2_busy; // @[lsu.scala:252:32] wire s_uop_13_prs2_busy = stq_uop_11_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_prs2_busy = stq_uop_11_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_prs3_busy; // @[lsu.scala:252:32] wire s_uop_13_prs3_busy = stq_uop_11_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_prs3_busy = stq_uop_11_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_ppred_busy; // @[lsu.scala:252:32] wire s_uop_13_ppred_busy = stq_uop_11_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_ppred_busy = stq_uop_11_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_13_stale_pdst = stq_uop_11_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_stale_pdst = stq_uop_11_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_exception; // @[lsu.scala:252:32] wire s_uop_13_exception = stq_uop_11_exception; // @[lsu.scala:252:32, :1324:37] wire uop_12_exception = stq_uop_11_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_11_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_13_exc_cause = stq_uop_11_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_12_exc_cause = stq_uop_11_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_13_mem_cmd = stq_uop_11_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_mem_cmd = stq_uop_11_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_13_mem_size = stq_uop_11_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_mem_size = stq_uop_11_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_mem_signed; // @[lsu.scala:252:32] wire s_uop_13_mem_signed = stq_uop_11_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_12_mem_signed = stq_uop_11_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_uses_ldq; // @[lsu.scala:252:32] wire s_uop_13_uses_ldq = stq_uop_11_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_12_uses_ldq = stq_uop_11_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_uses_stq; // @[lsu.scala:252:32] wire s_uop_13_uses_stq = stq_uop_11_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_12_uses_stq = stq_uop_11_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_unique; // @[lsu.scala:252:32] wire s_uop_13_is_unique = stq_uop_11_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_unique = stq_uop_11_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_13_flush_on_commit = stq_uop_11_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_12_flush_on_commit = stq_uop_11_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_13_csr_cmd = stq_uop_11_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_csr_cmd = stq_uop_11_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_13_ldst_is_rs1 = stq_uop_11_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_12_ldst_is_rs1 = stq_uop_11_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_13_ldst = stq_uop_11_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_ldst = stq_uop_11_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_13_lrs1 = stq_uop_11_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_lrs1 = stq_uop_11_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_13_lrs2 = stq_uop_11_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_lrs2 = stq_uop_11_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_13_lrs3 = stq_uop_11_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_lrs3 = stq_uop_11_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_13_dst_rtype = stq_uop_11_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_dst_rtype = stq_uop_11_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_13_lrs1_rtype = stq_uop_11_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_lrs1_rtype = stq_uop_11_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_13_lrs2_rtype = stq_uop_11_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_lrs2_rtype = stq_uop_11_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_frs3_en; // @[lsu.scala:252:32] wire s_uop_13_frs3_en = stq_uop_11_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_12_frs3_en = stq_uop_11_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fcn_dw; // @[lsu.scala:252:32] wire s_uop_13_fcn_dw = stq_uop_11_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_12_fcn_dw = stq_uop_11_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_13_fcn_op = stq_uop_11_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_fcn_op = stq_uop_11_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_val; // @[lsu.scala:252:32] wire s_uop_13_fp_val = stq_uop_11_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_val = stq_uop_11_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_13_fp_rm = stq_uop_11_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_fp_rm = stq_uop_11_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_13_fp_typ = stq_uop_11_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_fp_typ = stq_uop_11_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_13_xcpt_pf_if = stq_uop_11_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_xcpt_pf_if = stq_uop_11_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_13_xcpt_ae_if = stq_uop_11_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_xcpt_ae_if = stq_uop_11_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_13_xcpt_ma_if = stq_uop_11_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_xcpt_ma_if = stq_uop_11_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_13_bp_debug_if = stq_uop_11_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_bp_debug_if = stq_uop_11_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_13_bp_xcpt_if = stq_uop_11_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_bp_xcpt_if = stq_uop_11_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_13_debug_fsrc = stq_uop_11_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_debug_fsrc = stq_uop_11_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_13_debug_tsrc = stq_uop_11_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_debug_tsrc = stq_uop_11_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_12_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_14_inst = stq_uop_12_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_13_inst = stq_uop_12_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_12_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_14_debug_inst = stq_uop_12_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_13_debug_inst = stq_uop_12_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_rvc; // @[lsu.scala:252:32] wire s_uop_14_is_rvc = stq_uop_12_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_rvc = stq_uop_12_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_12_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_14_debug_pc = stq_uop_12_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_13_debug_pc = stq_uop_12_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_0; // @[lsu.scala:252:32] wire s_uop_14_iq_type_0 = stq_uop_12_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_0 = stq_uop_12_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_1; // @[lsu.scala:252:32] wire s_uop_14_iq_type_1 = stq_uop_12_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_1 = stq_uop_12_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_2; // @[lsu.scala:252:32] wire s_uop_14_iq_type_2 = stq_uop_12_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_2 = stq_uop_12_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_3; // @[lsu.scala:252:32] wire s_uop_14_iq_type_3 = stq_uop_12_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_3 = stq_uop_12_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_0; // @[lsu.scala:252:32] wire s_uop_14_fu_code_0 = stq_uop_12_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_0 = stq_uop_12_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_1; // @[lsu.scala:252:32] wire s_uop_14_fu_code_1 = stq_uop_12_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_1 = stq_uop_12_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_2; // @[lsu.scala:252:32] wire s_uop_14_fu_code_2 = stq_uop_12_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_2 = stq_uop_12_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_3; // @[lsu.scala:252:32] wire s_uop_14_fu_code_3 = stq_uop_12_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_3 = stq_uop_12_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_4; // @[lsu.scala:252:32] wire s_uop_14_fu_code_4 = stq_uop_12_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_4 = stq_uop_12_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_5; // @[lsu.scala:252:32] wire s_uop_14_fu_code_5 = stq_uop_12_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_5 = stq_uop_12_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_6; // @[lsu.scala:252:32] wire s_uop_14_fu_code_6 = stq_uop_12_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_6 = stq_uop_12_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_7; // @[lsu.scala:252:32] wire s_uop_14_fu_code_7 = stq_uop_12_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_7 = stq_uop_12_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_8; // @[lsu.scala:252:32] wire s_uop_14_fu_code_8 = stq_uop_12_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_8 = stq_uop_12_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_9; // @[lsu.scala:252:32] wire s_uop_14_fu_code_9 = stq_uop_12_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_9 = stq_uop_12_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_issued; // @[lsu.scala:252:32] wire s_uop_14_iw_issued = stq_uop_12_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_issued = stq_uop_12_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_14_iw_issued_partial_agen = stq_uop_12_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_issued_partial_agen = stq_uop_12_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_14_iw_issued_partial_dgen = stq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_issued_partial_dgen = stq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_14_iw_p1_speculative_child = stq_uop_12_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_iw_p1_speculative_child = stq_uop_12_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_14_iw_p2_speculative_child = stq_uop_12_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_iw_p2_speculative_child = stq_uop_12_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_14_iw_p1_bypass_hint = stq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_p1_bypass_hint = stq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_14_iw_p2_bypass_hint = stq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_p2_bypass_hint = stq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_14_iw_p3_bypass_hint = stq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_p3_bypass_hint = stq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_14_dis_col_sel = stq_uop_12_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_dis_col_sel = stq_uop_12_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_12_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_14_br_mask = stq_uop_12_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_13_br_mask = stq_uop_12_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_12_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_14_br_tag = stq_uop_12_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_13_br_tag = stq_uop_12_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_12_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_14_br_type = stq_uop_12_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_13_br_type = stq_uop_12_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_sfb; // @[lsu.scala:252:32] wire s_uop_14_is_sfb = stq_uop_12_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_sfb = stq_uop_12_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_fence; // @[lsu.scala:252:32] wire s_uop_14_is_fence = stq_uop_12_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_fence = stq_uop_12_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_fencei; // @[lsu.scala:252:32] wire s_uop_14_is_fencei = stq_uop_12_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_fencei = stq_uop_12_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_sfence; // @[lsu.scala:252:32] wire s_uop_14_is_sfence = stq_uop_12_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_sfence = stq_uop_12_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_amo; // @[lsu.scala:252:32] wire s_uop_14_is_amo = stq_uop_12_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_amo = stq_uop_12_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_eret; // @[lsu.scala:252:32] wire s_uop_14_is_eret = stq_uop_12_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_eret = stq_uop_12_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_14_is_sys_pc2epc = stq_uop_12_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_sys_pc2epc = stq_uop_12_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_rocc; // @[lsu.scala:252:32] wire s_uop_14_is_rocc = stq_uop_12_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_rocc = stq_uop_12_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_mov; // @[lsu.scala:252:32] wire s_uop_14_is_mov = stq_uop_12_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_mov = stq_uop_12_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_14_ftq_idx = stq_uop_12_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_ftq_idx = stq_uop_12_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_edge_inst; // @[lsu.scala:252:32] wire s_uop_14_edge_inst = stq_uop_12_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_13_edge_inst = stq_uop_12_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_14_pc_lob = stq_uop_12_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_pc_lob = stq_uop_12_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_taken; // @[lsu.scala:252:32] wire s_uop_14_taken = stq_uop_12_taken; // @[lsu.scala:252:32, :1324:37] wire uop_13_taken = stq_uop_12_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_imm_rename; // @[lsu.scala:252:32] wire s_uop_14_imm_rename = stq_uop_12_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_13_imm_rename = stq_uop_12_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_14_imm_sel = stq_uop_12_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_imm_sel = stq_uop_12_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_14_pimm = stq_uop_12_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_pimm = stq_uop_12_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_12_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_14_imm_packed = stq_uop_12_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_13_imm_packed = stq_uop_12_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_14_op1_sel = stq_uop_12_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_op1_sel = stq_uop_12_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_14_op2_sel = stq_uop_12_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_op2_sel = stq_uop_12_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ldst = stq_uop_12_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ldst = stq_uop_12_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_wen = stq_uop_12_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_wen = stq_uop_12_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ren1 = stq_uop_12_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ren1 = stq_uop_12_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ren2 = stq_uop_12_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ren2 = stq_uop_12_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ren3 = stq_uop_12_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ren3 = stq_uop_12_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_swap12 = stq_uop_12_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_swap12 = stq_uop_12_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_swap23 = stq_uop_12_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_swap23 = stq_uop_12_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_14_fp_ctrl_typeTagIn = stq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_fp_ctrl_typeTagIn = stq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_14_fp_ctrl_typeTagOut = stq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_fp_ctrl_typeTagOut = stq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_fromint = stq_uop_12_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_fromint = stq_uop_12_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_toint = stq_uop_12_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_toint = stq_uop_12_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_fastpipe = stq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_fastpipe = stq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_fma = stq_uop_12_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_fma = stq_uop_12_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_div = stq_uop_12_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_div = stq_uop_12_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_sqrt = stq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_sqrt = stq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_wflags = stq_uop_12_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_wflags = stq_uop_12_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_vec = stq_uop_12_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_vec = stq_uop_12_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_14_rob_idx = stq_uop_12_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_rob_idx = stq_uop_12_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_12_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_14_ldq_idx = stq_uop_12_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_13_ldq_idx = stq_uop_12_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_12_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_14_stq_idx = stq_uop_12_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_13_stq_idx = stq_uop_12_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_14_rxq_idx = stq_uop_12_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_rxq_idx = stq_uop_12_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_14_pdst = stq_uop_12_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_pdst = stq_uop_12_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_14_prs1 = stq_uop_12_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_prs1 = stq_uop_12_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_14_prs2 = stq_uop_12_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_prs2 = stq_uop_12_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_14_prs3 = stq_uop_12_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_prs3 = stq_uop_12_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_14_ppred = stq_uop_12_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_ppred = stq_uop_12_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_prs1_busy; // @[lsu.scala:252:32] wire s_uop_14_prs1_busy = stq_uop_12_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_prs1_busy = stq_uop_12_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_prs2_busy; // @[lsu.scala:252:32] wire s_uop_14_prs2_busy = stq_uop_12_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_prs2_busy = stq_uop_12_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_prs3_busy; // @[lsu.scala:252:32] wire s_uop_14_prs3_busy = stq_uop_12_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_prs3_busy = stq_uop_12_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_ppred_busy; // @[lsu.scala:252:32] wire s_uop_14_ppred_busy = stq_uop_12_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_ppred_busy = stq_uop_12_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_14_stale_pdst = stq_uop_12_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_stale_pdst = stq_uop_12_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_exception; // @[lsu.scala:252:32] wire s_uop_14_exception = stq_uop_12_exception; // @[lsu.scala:252:32, :1324:37] wire uop_13_exception = stq_uop_12_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_12_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_14_exc_cause = stq_uop_12_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_13_exc_cause = stq_uop_12_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_14_mem_cmd = stq_uop_12_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_mem_cmd = stq_uop_12_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_14_mem_size = stq_uop_12_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_mem_size = stq_uop_12_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_mem_signed; // @[lsu.scala:252:32] wire s_uop_14_mem_signed = stq_uop_12_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_13_mem_signed = stq_uop_12_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_uses_ldq; // @[lsu.scala:252:32] wire s_uop_14_uses_ldq = stq_uop_12_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_13_uses_ldq = stq_uop_12_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_uses_stq; // @[lsu.scala:252:32] wire s_uop_14_uses_stq = stq_uop_12_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_13_uses_stq = stq_uop_12_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_unique; // @[lsu.scala:252:32] wire s_uop_14_is_unique = stq_uop_12_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_unique = stq_uop_12_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_14_flush_on_commit = stq_uop_12_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_13_flush_on_commit = stq_uop_12_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_14_csr_cmd = stq_uop_12_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_csr_cmd = stq_uop_12_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_14_ldst_is_rs1 = stq_uop_12_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_13_ldst_is_rs1 = stq_uop_12_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_14_ldst = stq_uop_12_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_ldst = stq_uop_12_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_14_lrs1 = stq_uop_12_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_lrs1 = stq_uop_12_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_14_lrs2 = stq_uop_12_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_lrs2 = stq_uop_12_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_14_lrs3 = stq_uop_12_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_lrs3 = stq_uop_12_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_14_dst_rtype = stq_uop_12_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_dst_rtype = stq_uop_12_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_14_lrs1_rtype = stq_uop_12_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_lrs1_rtype = stq_uop_12_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_14_lrs2_rtype = stq_uop_12_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_lrs2_rtype = stq_uop_12_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_frs3_en; // @[lsu.scala:252:32] wire s_uop_14_frs3_en = stq_uop_12_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_13_frs3_en = stq_uop_12_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fcn_dw; // @[lsu.scala:252:32] wire s_uop_14_fcn_dw = stq_uop_12_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_13_fcn_dw = stq_uop_12_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_14_fcn_op = stq_uop_12_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_fcn_op = stq_uop_12_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_val; // @[lsu.scala:252:32] wire s_uop_14_fp_val = stq_uop_12_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_val = stq_uop_12_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_14_fp_rm = stq_uop_12_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_fp_rm = stq_uop_12_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_14_fp_typ = stq_uop_12_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_fp_typ = stq_uop_12_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_14_xcpt_pf_if = stq_uop_12_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_xcpt_pf_if = stq_uop_12_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_14_xcpt_ae_if = stq_uop_12_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_xcpt_ae_if = stq_uop_12_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_14_xcpt_ma_if = stq_uop_12_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_xcpt_ma_if = stq_uop_12_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_14_bp_debug_if = stq_uop_12_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_bp_debug_if = stq_uop_12_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_14_bp_xcpt_if = stq_uop_12_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_bp_xcpt_if = stq_uop_12_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_14_debug_fsrc = stq_uop_12_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_debug_fsrc = stq_uop_12_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_14_debug_tsrc = stq_uop_12_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_debug_tsrc = stq_uop_12_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_13_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_15_inst = stq_uop_13_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_14_inst = stq_uop_13_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_13_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_15_debug_inst = stq_uop_13_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_14_debug_inst = stq_uop_13_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_rvc; // @[lsu.scala:252:32] wire s_uop_15_is_rvc = stq_uop_13_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_rvc = stq_uop_13_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_13_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_15_debug_pc = stq_uop_13_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_14_debug_pc = stq_uop_13_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_0; // @[lsu.scala:252:32] wire s_uop_15_iq_type_0 = stq_uop_13_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_0 = stq_uop_13_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_1; // @[lsu.scala:252:32] wire s_uop_15_iq_type_1 = stq_uop_13_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_1 = stq_uop_13_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_2; // @[lsu.scala:252:32] wire s_uop_15_iq_type_2 = stq_uop_13_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_2 = stq_uop_13_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_3; // @[lsu.scala:252:32] wire s_uop_15_iq_type_3 = stq_uop_13_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_3 = stq_uop_13_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_0; // @[lsu.scala:252:32] wire s_uop_15_fu_code_0 = stq_uop_13_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_0 = stq_uop_13_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_1; // @[lsu.scala:252:32] wire s_uop_15_fu_code_1 = stq_uop_13_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_1 = stq_uop_13_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_2; // @[lsu.scala:252:32] wire s_uop_15_fu_code_2 = stq_uop_13_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_2 = stq_uop_13_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_3; // @[lsu.scala:252:32] wire s_uop_15_fu_code_3 = stq_uop_13_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_3 = stq_uop_13_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_4; // @[lsu.scala:252:32] wire s_uop_15_fu_code_4 = stq_uop_13_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_4 = stq_uop_13_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_5; // @[lsu.scala:252:32] wire s_uop_15_fu_code_5 = stq_uop_13_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_5 = stq_uop_13_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_6; // @[lsu.scala:252:32] wire s_uop_15_fu_code_6 = stq_uop_13_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_6 = stq_uop_13_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_7; // @[lsu.scala:252:32] wire s_uop_15_fu_code_7 = stq_uop_13_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_7 = stq_uop_13_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_8; // @[lsu.scala:252:32] wire s_uop_15_fu_code_8 = stq_uop_13_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_8 = stq_uop_13_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_9; // @[lsu.scala:252:32] wire s_uop_15_fu_code_9 = stq_uop_13_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_9 = stq_uop_13_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_issued; // @[lsu.scala:252:32] wire s_uop_15_iw_issued = stq_uop_13_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_issued = stq_uop_13_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_15_iw_issued_partial_agen = stq_uop_13_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_issued_partial_agen = stq_uop_13_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_15_iw_issued_partial_dgen = stq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_issued_partial_dgen = stq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_15_iw_p1_speculative_child = stq_uop_13_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_iw_p1_speculative_child = stq_uop_13_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_15_iw_p2_speculative_child = stq_uop_13_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_iw_p2_speculative_child = stq_uop_13_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_15_iw_p1_bypass_hint = stq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_p1_bypass_hint = stq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_15_iw_p2_bypass_hint = stq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_p2_bypass_hint = stq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_15_iw_p3_bypass_hint = stq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_p3_bypass_hint = stq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_15_dis_col_sel = stq_uop_13_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_dis_col_sel = stq_uop_13_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_13_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_15_br_mask = stq_uop_13_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_14_br_mask = stq_uop_13_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_13_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_15_br_tag = stq_uop_13_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_14_br_tag = stq_uop_13_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_13_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_15_br_type = stq_uop_13_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_14_br_type = stq_uop_13_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_sfb; // @[lsu.scala:252:32] wire s_uop_15_is_sfb = stq_uop_13_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_sfb = stq_uop_13_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_fence; // @[lsu.scala:252:32] wire s_uop_15_is_fence = stq_uop_13_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_fence = stq_uop_13_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_fencei; // @[lsu.scala:252:32] wire s_uop_15_is_fencei = stq_uop_13_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_fencei = stq_uop_13_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_sfence; // @[lsu.scala:252:32] wire s_uop_15_is_sfence = stq_uop_13_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_sfence = stq_uop_13_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_amo; // @[lsu.scala:252:32] wire s_uop_15_is_amo = stq_uop_13_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_amo = stq_uop_13_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_eret; // @[lsu.scala:252:32] wire s_uop_15_is_eret = stq_uop_13_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_eret = stq_uop_13_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_15_is_sys_pc2epc = stq_uop_13_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_sys_pc2epc = stq_uop_13_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_rocc; // @[lsu.scala:252:32] wire s_uop_15_is_rocc = stq_uop_13_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_rocc = stq_uop_13_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_mov; // @[lsu.scala:252:32] wire s_uop_15_is_mov = stq_uop_13_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_mov = stq_uop_13_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_15_ftq_idx = stq_uop_13_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_ftq_idx = stq_uop_13_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_edge_inst; // @[lsu.scala:252:32] wire s_uop_15_edge_inst = stq_uop_13_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_14_edge_inst = stq_uop_13_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_15_pc_lob = stq_uop_13_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_pc_lob = stq_uop_13_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_taken; // @[lsu.scala:252:32] wire s_uop_15_taken = stq_uop_13_taken; // @[lsu.scala:252:32, :1324:37] wire uop_14_taken = stq_uop_13_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_imm_rename; // @[lsu.scala:252:32] wire s_uop_15_imm_rename = stq_uop_13_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_14_imm_rename = stq_uop_13_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_15_imm_sel = stq_uop_13_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_imm_sel = stq_uop_13_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_15_pimm = stq_uop_13_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_pimm = stq_uop_13_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_13_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_15_imm_packed = stq_uop_13_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_14_imm_packed = stq_uop_13_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_15_op1_sel = stq_uop_13_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_op1_sel = stq_uop_13_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_15_op2_sel = stq_uop_13_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_op2_sel = stq_uop_13_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ldst = stq_uop_13_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ldst = stq_uop_13_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_wen = stq_uop_13_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_wen = stq_uop_13_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ren1 = stq_uop_13_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ren1 = stq_uop_13_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ren2 = stq_uop_13_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ren2 = stq_uop_13_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ren3 = stq_uop_13_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ren3 = stq_uop_13_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_swap12 = stq_uop_13_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_swap12 = stq_uop_13_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_swap23 = stq_uop_13_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_swap23 = stq_uop_13_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_15_fp_ctrl_typeTagIn = stq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_fp_ctrl_typeTagIn = stq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_15_fp_ctrl_typeTagOut = stq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_fp_ctrl_typeTagOut = stq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_fromint = stq_uop_13_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_fromint = stq_uop_13_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_toint = stq_uop_13_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_toint = stq_uop_13_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_fastpipe = stq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_fastpipe = stq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_fma = stq_uop_13_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_fma = stq_uop_13_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_div = stq_uop_13_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_div = stq_uop_13_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_sqrt = stq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_sqrt = stq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_wflags = stq_uop_13_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_wflags = stq_uop_13_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_vec = stq_uop_13_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_vec = stq_uop_13_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_15_rob_idx = stq_uop_13_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_rob_idx = stq_uop_13_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_13_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_15_ldq_idx = stq_uop_13_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_14_ldq_idx = stq_uop_13_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_13_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_15_stq_idx = stq_uop_13_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_14_stq_idx = stq_uop_13_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_15_rxq_idx = stq_uop_13_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_rxq_idx = stq_uop_13_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_15_pdst = stq_uop_13_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_pdst = stq_uop_13_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_15_prs1 = stq_uop_13_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_prs1 = stq_uop_13_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_15_prs2 = stq_uop_13_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_prs2 = stq_uop_13_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_15_prs3 = stq_uop_13_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_prs3 = stq_uop_13_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_15_ppred = stq_uop_13_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_ppred = stq_uop_13_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_prs1_busy; // @[lsu.scala:252:32] wire s_uop_15_prs1_busy = stq_uop_13_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_prs1_busy = stq_uop_13_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_prs2_busy; // @[lsu.scala:252:32] wire s_uop_15_prs2_busy = stq_uop_13_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_prs2_busy = stq_uop_13_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_prs3_busy; // @[lsu.scala:252:32] wire s_uop_15_prs3_busy = stq_uop_13_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_prs3_busy = stq_uop_13_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_ppred_busy; // @[lsu.scala:252:32] wire s_uop_15_ppred_busy = stq_uop_13_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_ppred_busy = stq_uop_13_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_15_stale_pdst = stq_uop_13_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_stale_pdst = stq_uop_13_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_exception; // @[lsu.scala:252:32] wire s_uop_15_exception = stq_uop_13_exception; // @[lsu.scala:252:32, :1324:37] wire uop_14_exception = stq_uop_13_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_13_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_15_exc_cause = stq_uop_13_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_14_exc_cause = stq_uop_13_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_15_mem_cmd = stq_uop_13_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_mem_cmd = stq_uop_13_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_15_mem_size = stq_uop_13_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_mem_size = stq_uop_13_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_mem_signed; // @[lsu.scala:252:32] wire s_uop_15_mem_signed = stq_uop_13_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_14_mem_signed = stq_uop_13_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_uses_ldq; // @[lsu.scala:252:32] wire s_uop_15_uses_ldq = stq_uop_13_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_14_uses_ldq = stq_uop_13_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_uses_stq; // @[lsu.scala:252:32] wire s_uop_15_uses_stq = stq_uop_13_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_14_uses_stq = stq_uop_13_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_unique; // @[lsu.scala:252:32] wire s_uop_15_is_unique = stq_uop_13_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_unique = stq_uop_13_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_15_flush_on_commit = stq_uop_13_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_14_flush_on_commit = stq_uop_13_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_15_csr_cmd = stq_uop_13_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_csr_cmd = stq_uop_13_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_15_ldst_is_rs1 = stq_uop_13_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_14_ldst_is_rs1 = stq_uop_13_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_15_ldst = stq_uop_13_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_ldst = stq_uop_13_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_15_lrs1 = stq_uop_13_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_lrs1 = stq_uop_13_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_15_lrs2 = stq_uop_13_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_lrs2 = stq_uop_13_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_15_lrs3 = stq_uop_13_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_lrs3 = stq_uop_13_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_15_dst_rtype = stq_uop_13_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_dst_rtype = stq_uop_13_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_15_lrs1_rtype = stq_uop_13_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_lrs1_rtype = stq_uop_13_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_15_lrs2_rtype = stq_uop_13_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_lrs2_rtype = stq_uop_13_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_frs3_en; // @[lsu.scala:252:32] wire s_uop_15_frs3_en = stq_uop_13_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_14_frs3_en = stq_uop_13_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fcn_dw; // @[lsu.scala:252:32] wire s_uop_15_fcn_dw = stq_uop_13_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_14_fcn_dw = stq_uop_13_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_15_fcn_op = stq_uop_13_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_fcn_op = stq_uop_13_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_val; // @[lsu.scala:252:32] wire s_uop_15_fp_val = stq_uop_13_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_val = stq_uop_13_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_15_fp_rm = stq_uop_13_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_fp_rm = stq_uop_13_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_15_fp_typ = stq_uop_13_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_fp_typ = stq_uop_13_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_15_xcpt_pf_if = stq_uop_13_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_xcpt_pf_if = stq_uop_13_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_15_xcpt_ae_if = stq_uop_13_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_xcpt_ae_if = stq_uop_13_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_15_xcpt_ma_if = stq_uop_13_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_xcpt_ma_if = stq_uop_13_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_15_bp_debug_if = stq_uop_13_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_bp_debug_if = stq_uop_13_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_15_bp_xcpt_if = stq_uop_13_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_bp_xcpt_if = stq_uop_13_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_15_debug_fsrc = stq_uop_13_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_debug_fsrc = stq_uop_13_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_15_debug_tsrc = stq_uop_13_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_debug_tsrc = stq_uop_13_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_14_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_16_inst = stq_uop_14_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_15_inst = stq_uop_14_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_14_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_16_debug_inst = stq_uop_14_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_15_debug_inst = stq_uop_14_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_rvc; // @[lsu.scala:252:32] wire s_uop_16_is_rvc = stq_uop_14_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_rvc = stq_uop_14_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_14_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_16_debug_pc = stq_uop_14_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_15_debug_pc = stq_uop_14_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_0; // @[lsu.scala:252:32] wire s_uop_16_iq_type_0 = stq_uop_14_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_0 = stq_uop_14_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_1; // @[lsu.scala:252:32] wire s_uop_16_iq_type_1 = stq_uop_14_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_1 = stq_uop_14_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_2; // @[lsu.scala:252:32] wire s_uop_16_iq_type_2 = stq_uop_14_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_2 = stq_uop_14_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_3; // @[lsu.scala:252:32] wire s_uop_16_iq_type_3 = stq_uop_14_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_3 = stq_uop_14_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_0; // @[lsu.scala:252:32] wire s_uop_16_fu_code_0 = stq_uop_14_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_0 = stq_uop_14_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_1; // @[lsu.scala:252:32] wire s_uop_16_fu_code_1 = stq_uop_14_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_1 = stq_uop_14_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_2; // @[lsu.scala:252:32] wire s_uop_16_fu_code_2 = stq_uop_14_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_2 = stq_uop_14_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_3; // @[lsu.scala:252:32] wire s_uop_16_fu_code_3 = stq_uop_14_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_3 = stq_uop_14_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_4; // @[lsu.scala:252:32] wire s_uop_16_fu_code_4 = stq_uop_14_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_4 = stq_uop_14_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_5; // @[lsu.scala:252:32] wire s_uop_16_fu_code_5 = stq_uop_14_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_5 = stq_uop_14_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_6; // @[lsu.scala:252:32] wire s_uop_16_fu_code_6 = stq_uop_14_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_6 = stq_uop_14_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_7; // @[lsu.scala:252:32] wire s_uop_16_fu_code_7 = stq_uop_14_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_7 = stq_uop_14_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_8; // @[lsu.scala:252:32] wire s_uop_16_fu_code_8 = stq_uop_14_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_8 = stq_uop_14_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_9; // @[lsu.scala:252:32] wire s_uop_16_fu_code_9 = stq_uop_14_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_9 = stq_uop_14_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_issued; // @[lsu.scala:252:32] wire s_uop_16_iw_issued = stq_uop_14_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_issued = stq_uop_14_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_16_iw_issued_partial_agen = stq_uop_14_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_issued_partial_agen = stq_uop_14_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_16_iw_issued_partial_dgen = stq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_issued_partial_dgen = stq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_16_iw_p1_speculative_child = stq_uop_14_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_iw_p1_speculative_child = stq_uop_14_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_16_iw_p2_speculative_child = stq_uop_14_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_iw_p2_speculative_child = stq_uop_14_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_16_iw_p1_bypass_hint = stq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_p1_bypass_hint = stq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_16_iw_p2_bypass_hint = stq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_p2_bypass_hint = stq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_16_iw_p3_bypass_hint = stq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_p3_bypass_hint = stq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_16_dis_col_sel = stq_uop_14_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_dis_col_sel = stq_uop_14_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_14_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_16_br_mask = stq_uop_14_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_15_br_mask = stq_uop_14_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_14_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_16_br_tag = stq_uop_14_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_15_br_tag = stq_uop_14_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_14_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_16_br_type = stq_uop_14_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_15_br_type = stq_uop_14_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_sfb; // @[lsu.scala:252:32] wire s_uop_16_is_sfb = stq_uop_14_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_sfb = stq_uop_14_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_fence; // @[lsu.scala:252:32] wire s_uop_16_is_fence = stq_uop_14_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_fence = stq_uop_14_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_fencei; // @[lsu.scala:252:32] wire s_uop_16_is_fencei = stq_uop_14_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_fencei = stq_uop_14_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_sfence; // @[lsu.scala:252:32] wire s_uop_16_is_sfence = stq_uop_14_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_sfence = stq_uop_14_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_amo; // @[lsu.scala:252:32] wire s_uop_16_is_amo = stq_uop_14_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_amo = stq_uop_14_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_eret; // @[lsu.scala:252:32] wire s_uop_16_is_eret = stq_uop_14_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_eret = stq_uop_14_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_16_is_sys_pc2epc = stq_uop_14_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_sys_pc2epc = stq_uop_14_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_rocc; // @[lsu.scala:252:32] wire s_uop_16_is_rocc = stq_uop_14_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_rocc = stq_uop_14_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_mov; // @[lsu.scala:252:32] wire s_uop_16_is_mov = stq_uop_14_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_mov = stq_uop_14_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_16_ftq_idx = stq_uop_14_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_ftq_idx = stq_uop_14_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_edge_inst; // @[lsu.scala:252:32] wire s_uop_16_edge_inst = stq_uop_14_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_15_edge_inst = stq_uop_14_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_16_pc_lob = stq_uop_14_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_pc_lob = stq_uop_14_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_taken; // @[lsu.scala:252:32] wire s_uop_16_taken = stq_uop_14_taken; // @[lsu.scala:252:32, :1324:37] wire uop_15_taken = stq_uop_14_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_imm_rename; // @[lsu.scala:252:32] wire s_uop_16_imm_rename = stq_uop_14_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_15_imm_rename = stq_uop_14_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_16_imm_sel = stq_uop_14_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_imm_sel = stq_uop_14_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_16_pimm = stq_uop_14_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_pimm = stq_uop_14_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_14_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_16_imm_packed = stq_uop_14_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_15_imm_packed = stq_uop_14_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_16_op1_sel = stq_uop_14_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_op1_sel = stq_uop_14_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_16_op2_sel = stq_uop_14_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_op2_sel = stq_uop_14_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ldst = stq_uop_14_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ldst = stq_uop_14_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_wen = stq_uop_14_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_wen = stq_uop_14_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ren1 = stq_uop_14_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ren1 = stq_uop_14_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ren2 = stq_uop_14_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ren2 = stq_uop_14_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ren3 = stq_uop_14_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ren3 = stq_uop_14_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_swap12 = stq_uop_14_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_swap12 = stq_uop_14_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_swap23 = stq_uop_14_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_swap23 = stq_uop_14_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_16_fp_ctrl_typeTagIn = stq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_fp_ctrl_typeTagIn = stq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_16_fp_ctrl_typeTagOut = stq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_fp_ctrl_typeTagOut = stq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_fromint = stq_uop_14_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_fromint = stq_uop_14_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_toint = stq_uop_14_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_toint = stq_uop_14_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_fastpipe = stq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_fastpipe = stq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_fma = stq_uop_14_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_fma = stq_uop_14_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_div = stq_uop_14_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_div = stq_uop_14_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_sqrt = stq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_sqrt = stq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_wflags = stq_uop_14_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_wflags = stq_uop_14_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_vec = stq_uop_14_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_vec = stq_uop_14_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_16_rob_idx = stq_uop_14_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_rob_idx = stq_uop_14_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_14_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_16_ldq_idx = stq_uop_14_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_15_ldq_idx = stq_uop_14_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_14_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_16_stq_idx = stq_uop_14_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_15_stq_idx = stq_uop_14_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_16_rxq_idx = stq_uop_14_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_rxq_idx = stq_uop_14_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_16_pdst = stq_uop_14_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_pdst = stq_uop_14_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_16_prs1 = stq_uop_14_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_prs1 = stq_uop_14_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_16_prs2 = stq_uop_14_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_prs2 = stq_uop_14_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_16_prs3 = stq_uop_14_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_prs3 = stq_uop_14_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_16_ppred = stq_uop_14_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_ppred = stq_uop_14_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_prs1_busy; // @[lsu.scala:252:32] wire s_uop_16_prs1_busy = stq_uop_14_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_prs1_busy = stq_uop_14_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_prs2_busy; // @[lsu.scala:252:32] wire s_uop_16_prs2_busy = stq_uop_14_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_prs2_busy = stq_uop_14_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_prs3_busy; // @[lsu.scala:252:32] wire s_uop_16_prs3_busy = stq_uop_14_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_prs3_busy = stq_uop_14_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_ppred_busy; // @[lsu.scala:252:32] wire s_uop_16_ppred_busy = stq_uop_14_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_ppred_busy = stq_uop_14_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_16_stale_pdst = stq_uop_14_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_stale_pdst = stq_uop_14_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_exception; // @[lsu.scala:252:32] wire s_uop_16_exception = stq_uop_14_exception; // @[lsu.scala:252:32, :1324:37] wire uop_15_exception = stq_uop_14_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_14_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_16_exc_cause = stq_uop_14_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_15_exc_cause = stq_uop_14_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_16_mem_cmd = stq_uop_14_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_mem_cmd = stq_uop_14_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_16_mem_size = stq_uop_14_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_mem_size = stq_uop_14_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_mem_signed; // @[lsu.scala:252:32] wire s_uop_16_mem_signed = stq_uop_14_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_15_mem_signed = stq_uop_14_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_uses_ldq; // @[lsu.scala:252:32] wire s_uop_16_uses_ldq = stq_uop_14_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_15_uses_ldq = stq_uop_14_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_uses_stq; // @[lsu.scala:252:32] wire s_uop_16_uses_stq = stq_uop_14_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_15_uses_stq = stq_uop_14_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_unique; // @[lsu.scala:252:32] wire s_uop_16_is_unique = stq_uop_14_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_unique = stq_uop_14_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_16_flush_on_commit = stq_uop_14_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_15_flush_on_commit = stq_uop_14_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_16_csr_cmd = stq_uop_14_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_csr_cmd = stq_uop_14_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_16_ldst_is_rs1 = stq_uop_14_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_15_ldst_is_rs1 = stq_uop_14_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_16_ldst = stq_uop_14_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_ldst = stq_uop_14_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_16_lrs1 = stq_uop_14_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_lrs1 = stq_uop_14_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_16_lrs2 = stq_uop_14_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_lrs2 = stq_uop_14_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_16_lrs3 = stq_uop_14_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_lrs3 = stq_uop_14_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_16_dst_rtype = stq_uop_14_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_dst_rtype = stq_uop_14_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_16_lrs1_rtype = stq_uop_14_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_lrs1_rtype = stq_uop_14_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_16_lrs2_rtype = stq_uop_14_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_lrs2_rtype = stq_uop_14_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_frs3_en; // @[lsu.scala:252:32] wire s_uop_16_frs3_en = stq_uop_14_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_15_frs3_en = stq_uop_14_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fcn_dw; // @[lsu.scala:252:32] wire s_uop_16_fcn_dw = stq_uop_14_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_15_fcn_dw = stq_uop_14_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_16_fcn_op = stq_uop_14_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_fcn_op = stq_uop_14_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_val; // @[lsu.scala:252:32] wire s_uop_16_fp_val = stq_uop_14_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_val = stq_uop_14_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_16_fp_rm = stq_uop_14_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_fp_rm = stq_uop_14_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_16_fp_typ = stq_uop_14_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_fp_typ = stq_uop_14_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_16_xcpt_pf_if = stq_uop_14_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_xcpt_pf_if = stq_uop_14_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_16_xcpt_ae_if = stq_uop_14_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_xcpt_ae_if = stq_uop_14_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_16_xcpt_ma_if = stq_uop_14_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_xcpt_ma_if = stq_uop_14_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_16_bp_debug_if = stq_uop_14_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_bp_debug_if = stq_uop_14_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_16_bp_xcpt_if = stq_uop_14_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_bp_xcpt_if = stq_uop_14_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_16_debug_fsrc = stq_uop_14_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_debug_fsrc = stq_uop_14_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_16_debug_tsrc = stq_uop_14_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_debug_tsrc = stq_uop_14_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_15_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_17_inst = stq_uop_15_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_16_inst = stq_uop_15_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_15_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_17_debug_inst = stq_uop_15_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_16_debug_inst = stq_uop_15_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_rvc; // @[lsu.scala:252:32] wire s_uop_17_is_rvc = stq_uop_15_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_rvc = stq_uop_15_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_15_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_17_debug_pc = stq_uop_15_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_16_debug_pc = stq_uop_15_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_0; // @[lsu.scala:252:32] wire s_uop_17_iq_type_0 = stq_uop_15_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_0 = stq_uop_15_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_1; // @[lsu.scala:252:32] wire s_uop_17_iq_type_1 = stq_uop_15_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_1 = stq_uop_15_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_2; // @[lsu.scala:252:32] wire s_uop_17_iq_type_2 = stq_uop_15_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_2 = stq_uop_15_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_3; // @[lsu.scala:252:32] wire s_uop_17_iq_type_3 = stq_uop_15_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_3 = stq_uop_15_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_0; // @[lsu.scala:252:32] wire s_uop_17_fu_code_0 = stq_uop_15_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_0 = stq_uop_15_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_1; // @[lsu.scala:252:32] wire s_uop_17_fu_code_1 = stq_uop_15_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_1 = stq_uop_15_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_2; // @[lsu.scala:252:32] wire s_uop_17_fu_code_2 = stq_uop_15_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_2 = stq_uop_15_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_3; // @[lsu.scala:252:32] wire s_uop_17_fu_code_3 = stq_uop_15_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_3 = stq_uop_15_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_4; // @[lsu.scala:252:32] wire s_uop_17_fu_code_4 = stq_uop_15_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_4 = stq_uop_15_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_5; // @[lsu.scala:252:32] wire s_uop_17_fu_code_5 = stq_uop_15_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_5 = stq_uop_15_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_6; // @[lsu.scala:252:32] wire s_uop_17_fu_code_6 = stq_uop_15_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_6 = stq_uop_15_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_7; // @[lsu.scala:252:32] wire s_uop_17_fu_code_7 = stq_uop_15_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_7 = stq_uop_15_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_8; // @[lsu.scala:252:32] wire s_uop_17_fu_code_8 = stq_uop_15_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_8 = stq_uop_15_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_9; // @[lsu.scala:252:32] wire s_uop_17_fu_code_9 = stq_uop_15_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_9 = stq_uop_15_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_issued; // @[lsu.scala:252:32] wire s_uop_17_iw_issued = stq_uop_15_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_issued = stq_uop_15_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_17_iw_issued_partial_agen = stq_uop_15_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_issued_partial_agen = stq_uop_15_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_17_iw_issued_partial_dgen = stq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_issued_partial_dgen = stq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_17_iw_p1_speculative_child = stq_uop_15_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_iw_p1_speculative_child = stq_uop_15_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_17_iw_p2_speculative_child = stq_uop_15_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_iw_p2_speculative_child = stq_uop_15_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_17_iw_p1_bypass_hint = stq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_p1_bypass_hint = stq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_17_iw_p2_bypass_hint = stq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_p2_bypass_hint = stq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_17_iw_p3_bypass_hint = stq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_p3_bypass_hint = stq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_17_dis_col_sel = stq_uop_15_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_dis_col_sel = stq_uop_15_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_15_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_17_br_mask = stq_uop_15_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_16_br_mask = stq_uop_15_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_15_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_17_br_tag = stq_uop_15_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_16_br_tag = stq_uop_15_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_15_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_17_br_type = stq_uop_15_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_16_br_type = stq_uop_15_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_sfb; // @[lsu.scala:252:32] wire s_uop_17_is_sfb = stq_uop_15_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_sfb = stq_uop_15_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_fence; // @[lsu.scala:252:32] wire s_uop_17_is_fence = stq_uop_15_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_fence = stq_uop_15_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_fencei; // @[lsu.scala:252:32] wire s_uop_17_is_fencei = stq_uop_15_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_fencei = stq_uop_15_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_sfence; // @[lsu.scala:252:32] wire s_uop_17_is_sfence = stq_uop_15_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_sfence = stq_uop_15_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_amo; // @[lsu.scala:252:32] wire s_uop_17_is_amo = stq_uop_15_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_amo = stq_uop_15_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_eret; // @[lsu.scala:252:32] wire s_uop_17_is_eret = stq_uop_15_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_eret = stq_uop_15_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_17_is_sys_pc2epc = stq_uop_15_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_sys_pc2epc = stq_uop_15_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_rocc; // @[lsu.scala:252:32] wire s_uop_17_is_rocc = stq_uop_15_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_rocc = stq_uop_15_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_mov; // @[lsu.scala:252:32] wire s_uop_17_is_mov = stq_uop_15_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_mov = stq_uop_15_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_17_ftq_idx = stq_uop_15_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_ftq_idx = stq_uop_15_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_edge_inst; // @[lsu.scala:252:32] wire s_uop_17_edge_inst = stq_uop_15_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_16_edge_inst = stq_uop_15_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_17_pc_lob = stq_uop_15_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_pc_lob = stq_uop_15_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_taken; // @[lsu.scala:252:32] wire s_uop_17_taken = stq_uop_15_taken; // @[lsu.scala:252:32, :1324:37] wire uop_16_taken = stq_uop_15_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_imm_rename; // @[lsu.scala:252:32] wire s_uop_17_imm_rename = stq_uop_15_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_16_imm_rename = stq_uop_15_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_17_imm_sel = stq_uop_15_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_imm_sel = stq_uop_15_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_17_pimm = stq_uop_15_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_pimm = stq_uop_15_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_15_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_17_imm_packed = stq_uop_15_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_16_imm_packed = stq_uop_15_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_17_op1_sel = stq_uop_15_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_op1_sel = stq_uop_15_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_17_op2_sel = stq_uop_15_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_op2_sel = stq_uop_15_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ldst = stq_uop_15_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ldst = stq_uop_15_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_wen = stq_uop_15_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_wen = stq_uop_15_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ren1 = stq_uop_15_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ren1 = stq_uop_15_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ren2 = stq_uop_15_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ren2 = stq_uop_15_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ren3 = stq_uop_15_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ren3 = stq_uop_15_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_swap12 = stq_uop_15_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_swap12 = stq_uop_15_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_swap23 = stq_uop_15_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_swap23 = stq_uop_15_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_17_fp_ctrl_typeTagIn = stq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_fp_ctrl_typeTagIn = stq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_17_fp_ctrl_typeTagOut = stq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_fp_ctrl_typeTagOut = stq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_fromint = stq_uop_15_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_fromint = stq_uop_15_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_toint = stq_uop_15_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_toint = stq_uop_15_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_fastpipe = stq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_fastpipe = stq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_fma = stq_uop_15_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_fma = stq_uop_15_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_div = stq_uop_15_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_div = stq_uop_15_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_sqrt = stq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_sqrt = stq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_wflags = stq_uop_15_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_wflags = stq_uop_15_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_vec = stq_uop_15_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_vec = stq_uop_15_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_17_rob_idx = stq_uop_15_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_rob_idx = stq_uop_15_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_15_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_17_ldq_idx = stq_uop_15_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_16_ldq_idx = stq_uop_15_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_15_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_17_stq_idx = stq_uop_15_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_16_stq_idx = stq_uop_15_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_17_rxq_idx = stq_uop_15_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_rxq_idx = stq_uop_15_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_17_pdst = stq_uop_15_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_pdst = stq_uop_15_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_17_prs1 = stq_uop_15_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_prs1 = stq_uop_15_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_17_prs2 = stq_uop_15_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_prs2 = stq_uop_15_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_17_prs3 = stq_uop_15_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_prs3 = stq_uop_15_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_17_ppred = stq_uop_15_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_ppred = stq_uop_15_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_prs1_busy; // @[lsu.scala:252:32] wire s_uop_17_prs1_busy = stq_uop_15_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_prs1_busy = stq_uop_15_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_prs2_busy; // @[lsu.scala:252:32] wire s_uop_17_prs2_busy = stq_uop_15_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_prs2_busy = stq_uop_15_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_prs3_busy; // @[lsu.scala:252:32] wire s_uop_17_prs3_busy = stq_uop_15_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_prs3_busy = stq_uop_15_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_ppred_busy; // @[lsu.scala:252:32] wire s_uop_17_ppred_busy = stq_uop_15_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_ppred_busy = stq_uop_15_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_17_stale_pdst = stq_uop_15_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_stale_pdst = stq_uop_15_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_exception; // @[lsu.scala:252:32] wire s_uop_17_exception = stq_uop_15_exception; // @[lsu.scala:252:32, :1324:37] wire uop_16_exception = stq_uop_15_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_15_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_17_exc_cause = stq_uop_15_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_16_exc_cause = stq_uop_15_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_17_mem_cmd = stq_uop_15_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_mem_cmd = stq_uop_15_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_17_mem_size = stq_uop_15_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_mem_size = stq_uop_15_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_mem_signed; // @[lsu.scala:252:32] wire s_uop_17_mem_signed = stq_uop_15_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_16_mem_signed = stq_uop_15_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_uses_ldq; // @[lsu.scala:252:32] wire s_uop_17_uses_ldq = stq_uop_15_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_16_uses_ldq = stq_uop_15_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_uses_stq; // @[lsu.scala:252:32] wire s_uop_17_uses_stq = stq_uop_15_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_16_uses_stq = stq_uop_15_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_unique; // @[lsu.scala:252:32] wire s_uop_17_is_unique = stq_uop_15_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_unique = stq_uop_15_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_17_flush_on_commit = stq_uop_15_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_16_flush_on_commit = stq_uop_15_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_17_csr_cmd = stq_uop_15_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_csr_cmd = stq_uop_15_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_17_ldst_is_rs1 = stq_uop_15_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_16_ldst_is_rs1 = stq_uop_15_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_17_ldst = stq_uop_15_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_ldst = stq_uop_15_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_17_lrs1 = stq_uop_15_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_lrs1 = stq_uop_15_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_17_lrs2 = stq_uop_15_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_lrs2 = stq_uop_15_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_17_lrs3 = stq_uop_15_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_lrs3 = stq_uop_15_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_17_dst_rtype = stq_uop_15_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_dst_rtype = stq_uop_15_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_17_lrs1_rtype = stq_uop_15_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_lrs1_rtype = stq_uop_15_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_17_lrs2_rtype = stq_uop_15_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_lrs2_rtype = stq_uop_15_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_frs3_en; // @[lsu.scala:252:32] wire s_uop_17_frs3_en = stq_uop_15_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_16_frs3_en = stq_uop_15_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fcn_dw; // @[lsu.scala:252:32] wire s_uop_17_fcn_dw = stq_uop_15_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_16_fcn_dw = stq_uop_15_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_17_fcn_op = stq_uop_15_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_fcn_op = stq_uop_15_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_val; // @[lsu.scala:252:32] wire s_uop_17_fp_val = stq_uop_15_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_val = stq_uop_15_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_17_fp_rm = stq_uop_15_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_fp_rm = stq_uop_15_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_17_fp_typ = stq_uop_15_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_fp_typ = stq_uop_15_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_17_xcpt_pf_if = stq_uop_15_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_xcpt_pf_if = stq_uop_15_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_17_xcpt_ae_if = stq_uop_15_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_xcpt_ae_if = stq_uop_15_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_17_xcpt_ma_if = stq_uop_15_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_xcpt_ma_if = stq_uop_15_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_17_bp_debug_if = stq_uop_15_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_bp_debug_if = stq_uop_15_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_17_bp_xcpt_if = stq_uop_15_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_bp_xcpt_if = stq_uop_15_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_17_debug_fsrc = stq_uop_15_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_debug_fsrc = stq_uop_15_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_17_debug_tsrc = stq_uop_15_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_debug_tsrc = stq_uop_15_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg stq_addr_0_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_0_bits; // @[lsu.scala:253:32] reg stq_addr_1_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_1_bits; // @[lsu.scala:253:32] reg stq_addr_2_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_2_bits; // @[lsu.scala:253:32] reg stq_addr_3_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_3_bits; // @[lsu.scala:253:32] reg stq_addr_4_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_4_bits; // @[lsu.scala:253:32] reg stq_addr_5_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_5_bits; // @[lsu.scala:253:32] reg stq_addr_6_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_6_bits; // @[lsu.scala:253:32] reg stq_addr_7_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_7_bits; // @[lsu.scala:253:32] reg stq_addr_8_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_8_bits; // @[lsu.scala:253:32] reg stq_addr_9_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_9_bits; // @[lsu.scala:253:32] reg stq_addr_10_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_10_bits; // @[lsu.scala:253:32] reg stq_addr_11_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_11_bits; // @[lsu.scala:253:32] reg stq_addr_12_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_12_bits; // @[lsu.scala:253:32] reg stq_addr_13_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_13_bits; // @[lsu.scala:253:32] reg stq_addr_14_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_14_bits; // @[lsu.scala:253:32] reg stq_addr_15_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_15_bits; // @[lsu.scala:253:32] reg stq_addr_is_virtual_0; // @[lsu.scala:254:32] reg stq_addr_is_virtual_1; // @[lsu.scala:254:32] reg stq_addr_is_virtual_2; // @[lsu.scala:254:32] reg stq_addr_is_virtual_3; // @[lsu.scala:254:32] reg stq_addr_is_virtual_4; // @[lsu.scala:254:32] reg stq_addr_is_virtual_5; // @[lsu.scala:254:32] reg stq_addr_is_virtual_6; // @[lsu.scala:254:32] reg stq_addr_is_virtual_7; // @[lsu.scala:254:32] reg stq_addr_is_virtual_8; // @[lsu.scala:254:32] reg stq_addr_is_virtual_9; // @[lsu.scala:254:32] reg stq_addr_is_virtual_10; // @[lsu.scala:254:32] reg stq_addr_is_virtual_11; // @[lsu.scala:254:32] reg stq_addr_is_virtual_12; // @[lsu.scala:254:32] reg stq_addr_is_virtual_13; // @[lsu.scala:254:32] reg stq_addr_is_virtual_14; // @[lsu.scala:254:32] reg stq_addr_is_virtual_15; // @[lsu.scala:254:32] reg stq_data_0_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_0_bits; // @[lsu.scala:255:32] reg stq_data_1_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_1_bits; // @[lsu.scala:255:32] reg stq_data_2_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_2_bits; // @[lsu.scala:255:32] reg stq_data_3_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_3_bits; // @[lsu.scala:255:32] reg stq_data_4_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_4_bits; // @[lsu.scala:255:32] reg stq_data_5_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_5_bits; // @[lsu.scala:255:32] reg stq_data_6_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_6_bits; // @[lsu.scala:255:32] reg stq_data_7_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_7_bits; // @[lsu.scala:255:32] reg stq_data_8_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_8_bits; // @[lsu.scala:255:32] reg stq_data_9_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_9_bits; // @[lsu.scala:255:32] reg stq_data_10_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_10_bits; // @[lsu.scala:255:32] reg stq_data_11_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_11_bits; // @[lsu.scala:255:32] reg stq_data_12_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_12_bits; // @[lsu.scala:255:32] reg stq_data_13_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_13_bits; // @[lsu.scala:255:32] reg stq_data_14_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_14_bits; // @[lsu.scala:255:32] reg stq_data_15_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_15_bits; // @[lsu.scala:255:32] reg stq_committed_0; // @[lsu.scala:256:32] reg stq_committed_1; // @[lsu.scala:256:32] reg stq_committed_2; // @[lsu.scala:256:32] reg stq_committed_3; // @[lsu.scala:256:32] reg stq_committed_4; // @[lsu.scala:256:32] reg stq_committed_5; // @[lsu.scala:256:32] reg stq_committed_6; // @[lsu.scala:256:32] reg stq_committed_7; // @[lsu.scala:256:32] reg stq_committed_8; // @[lsu.scala:256:32] reg stq_committed_9; // @[lsu.scala:256:32] reg stq_committed_10; // @[lsu.scala:256:32] reg stq_committed_11; // @[lsu.scala:256:32] reg stq_committed_12; // @[lsu.scala:256:32] reg stq_committed_13; // @[lsu.scala:256:32] reg stq_committed_14; // @[lsu.scala:256:32] reg stq_committed_15; // @[lsu.scala:256:32] reg stq_succeeded_0; // @[lsu.scala:257:32] reg stq_succeeded_1; // @[lsu.scala:257:32] reg stq_succeeded_2; // @[lsu.scala:257:32] reg stq_succeeded_3; // @[lsu.scala:257:32] reg stq_succeeded_4; // @[lsu.scala:257:32] reg stq_succeeded_5; // @[lsu.scala:257:32] reg stq_succeeded_6; // @[lsu.scala:257:32] reg stq_succeeded_7; // @[lsu.scala:257:32] reg stq_succeeded_8; // @[lsu.scala:257:32] reg stq_succeeded_9; // @[lsu.scala:257:32] reg stq_succeeded_10; // @[lsu.scala:257:32] reg stq_succeeded_11; // @[lsu.scala:257:32] reg stq_succeeded_12; // @[lsu.scala:257:32] reg stq_succeeded_13; // @[lsu.scala:257:32] reg stq_succeeded_14; // @[lsu.scala:257:32] reg stq_succeeded_15; // @[lsu.scala:257:32] reg stq_can_execute_0; // @[lsu.scala:258:32] reg stq_can_execute_1; // @[lsu.scala:258:32] reg stq_can_execute_2; // @[lsu.scala:258:32] reg stq_can_execute_3; // @[lsu.scala:258:32] reg stq_can_execute_4; // @[lsu.scala:258:32] reg stq_can_execute_5; // @[lsu.scala:258:32] reg stq_can_execute_6; // @[lsu.scala:258:32] reg stq_can_execute_7; // @[lsu.scala:258:32] reg stq_can_execute_8; // @[lsu.scala:258:32] reg stq_can_execute_9; // @[lsu.scala:258:32] reg stq_can_execute_10; // @[lsu.scala:258:32] reg stq_can_execute_11; // @[lsu.scala:258:32] reg stq_can_execute_12; // @[lsu.scala:258:32] reg stq_can_execute_13; // @[lsu.scala:258:32] reg stq_can_execute_14; // @[lsu.scala:258:32] reg stq_can_execute_15; // @[lsu.scala:258:32] reg stq_cleared_0; // @[lsu.scala:259:32] reg stq_cleared_1; // @[lsu.scala:259:32] reg stq_cleared_2; // @[lsu.scala:259:32] reg stq_cleared_3; // @[lsu.scala:259:32] reg stq_cleared_4; // @[lsu.scala:259:32] reg stq_cleared_5; // @[lsu.scala:259:32] reg stq_cleared_6; // @[lsu.scala:259:32] reg stq_cleared_7; // @[lsu.scala:259:32] reg stq_cleared_8; // @[lsu.scala:259:32] reg stq_cleared_9; // @[lsu.scala:259:32] reg stq_cleared_10; // @[lsu.scala:259:32] reg stq_cleared_11; // @[lsu.scala:259:32] reg stq_cleared_12; // @[lsu.scala:259:32] reg stq_cleared_13; // @[lsu.scala:259:32] reg stq_cleared_14; // @[lsu.scala:259:32] reg stq_cleared_15; // @[lsu.scala:259:32] reg [63:0] stq_debug_wb_data_0; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_1; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_2; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_3; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_4; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_5; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_6; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_7; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_8; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_9; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_10; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_11; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_12; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_13; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_14; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_15; // @[lsu.scala:260:32] reg [3:0] ldq_head; // @[lsu.scala:278:29] reg [3:0] ldq_tail; // @[lsu.scala:279:29] assign io_core_dis_ldq_idx_0_0 = ldq_tail; // @[lsu.scala:211:7, :279:29] reg [3:0] stq_head; // @[lsu.scala:280:29] reg [3:0] stq_tail; // @[lsu.scala:281:29] assign io_core_dis_stq_idx_0_0 = stq_tail; // @[lsu.scala:211:7, :281:29] reg [3:0] stq_commit_head; // @[lsu.scala:282:29] reg [3:0] stq_execute_head; // @[lsu.scala:283:29] reg [2:0] hella_state; // @[lsu.scala:301:38] reg [39:0] hella_req_addr; // @[lsu.scala:302:34] assign io_hellacache_resp_bits_addr_0 = hella_req_addr; // @[lsu.scala:211:7, :302:34] reg hella_req_dv; // @[lsu.scala:302:34] reg [63:0] hella_data_data; // @[lsu.scala:303:34] wire [63:0] _dmem_req_0_bits_data_T_42 = hella_data_data; // @[AMOALU.scala:29:13] reg [7:0] hella_data_mask; // @[lsu.scala:303:34] reg [31:0] hella_paddr; // @[lsu.scala:304:34] reg hella_xcpt_ma_ld; // @[lsu.scala:305:34] reg hella_xcpt_ma_st; // @[lsu.scala:305:34] reg hella_xcpt_pf_ld; // @[lsu.scala:305:34] reg hella_xcpt_pf_st; // @[lsu.scala:305:34] reg hella_xcpt_gf_ld; // @[lsu.scala:305:34] reg hella_xcpt_gf_st; // @[lsu.scala:305:34] reg hella_xcpt_ae_ld; // @[lsu.scala:305:34] reg hella_xcpt_ae_st; // @[lsu.scala:305:34] assign _io_core_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] assign io_core_perf_tlbMiss_0 = _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire clear_store; // @[lsu.scala:318:33] wire ldq_will_succeed_0; // @[lsu.scala:325:44] wire ldq_will_succeed_1; // @[lsu.scala:325:44] wire ldq_will_succeed_2; // @[lsu.scala:325:44] wire ldq_will_succeed_3; // @[lsu.scala:325:44] wire ldq_will_succeed_4; // @[lsu.scala:325:44] wire ldq_will_succeed_5; // @[lsu.scala:325:44] wire ldq_will_succeed_6; // @[lsu.scala:325:44] wire ldq_will_succeed_7; // @[lsu.scala:325:44] wire ldq_will_succeed_8; // @[lsu.scala:325:44] wire ldq_will_succeed_9; // @[lsu.scala:325:44] wire ldq_will_succeed_10; // @[lsu.scala:325:44] wire ldq_will_succeed_11; // @[lsu.scala:325:44] wire ldq_will_succeed_12; // @[lsu.scala:325:44] wire ldq_will_succeed_13; // @[lsu.scala:325:44] wire ldq_will_succeed_14; // @[lsu.scala:325:44] wire ldq_will_succeed_15; // @[lsu.scala:325:44] wire [15:0] _GEN = 16'h1 << stq_head; // @[lsu.scala:280:29, :340:56] wire [15:0] _ldq_st_dep_mask_0_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_0_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_1_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_1_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_2_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_2_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_3_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_3_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_4_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_4_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_5_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_5_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_6_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_6_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_7_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_7_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_8_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_8_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_9_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_9_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_10_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_10_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_11_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_11_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_12_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_12_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_13_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_13_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_14_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_14_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_15_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_15_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _next_live_store_mask_T; // @[lsu.scala:355:71] assign _next_live_store_mask_T = _GEN; // @[lsu.scala:340:56, :355:71] wire [15:0] _ldq_st_dep_mask_0_T_1 = ~_ldq_st_dep_mask_0_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_0_T_2 = ldq_st_dep_mask_0 & _ldq_st_dep_mask_0_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_1_T_1 = ~_ldq_st_dep_mask_1_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_1_T_2 = ldq_st_dep_mask_1 & _ldq_st_dep_mask_1_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_2_T_1 = ~_ldq_st_dep_mask_2_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_2_T_2 = ldq_st_dep_mask_2 & _ldq_st_dep_mask_2_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_3_T_1 = ~_ldq_st_dep_mask_3_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_3_T_2 = ldq_st_dep_mask_3 & _ldq_st_dep_mask_3_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_4_T_1 = ~_ldq_st_dep_mask_4_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_4_T_2 = ldq_st_dep_mask_4 & _ldq_st_dep_mask_4_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_5_T_1 = ~_ldq_st_dep_mask_5_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_5_T_2 = ldq_st_dep_mask_5 & _ldq_st_dep_mask_5_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_6_T_1 = ~_ldq_st_dep_mask_6_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_6_T_2 = ldq_st_dep_mask_6 & _ldq_st_dep_mask_6_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_7_T_1 = ~_ldq_st_dep_mask_7_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_7_T_2 = ldq_st_dep_mask_7 & _ldq_st_dep_mask_7_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_8_T_1 = ~_ldq_st_dep_mask_8_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_8_T_2 = ldq_st_dep_mask_8 & _ldq_st_dep_mask_8_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_9_T_1 = ~_ldq_st_dep_mask_9_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_9_T_2 = ldq_st_dep_mask_9 & _ldq_st_dep_mask_9_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_10_T_1 = ~_ldq_st_dep_mask_10_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_10_T_2 = ldq_st_dep_mask_10 & _ldq_st_dep_mask_10_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_11_T_1 = ~_ldq_st_dep_mask_11_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_11_T_2 = ldq_st_dep_mask_11 & _ldq_st_dep_mask_11_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_12_T_1 = ~_ldq_st_dep_mask_12_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_12_T_2 = ldq_st_dep_mask_12 & _ldq_st_dep_mask_12_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_13_T_1 = ~_ldq_st_dep_mask_13_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_13_T_2 = ldq_st_dep_mask_13 & _ldq_st_dep_mask_13_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_14_T_1 = ~_ldq_st_dep_mask_14_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_14_T_2 = ldq_st_dep_mask_14 & _ldq_st_dep_mask_14_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_15_T_1 = ~_ldq_st_dep_mask_15_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_15_T_2 = ldq_st_dep_mask_15 & _ldq_st_dep_mask_15_T_1; // @[lsu.scala:227:36, :340:{48,50}] reg dis_ldq_oh_0; // @[lsu.scala:348:23] reg dis_ldq_oh_1; // @[lsu.scala:348:23] reg dis_ldq_oh_2; // @[lsu.scala:348:23] reg dis_ldq_oh_3; // @[lsu.scala:348:23] reg dis_ldq_oh_4; // @[lsu.scala:348:23] reg dis_ldq_oh_5; // @[lsu.scala:348:23] reg dis_ldq_oh_6; // @[lsu.scala:348:23] reg dis_ldq_oh_7; // @[lsu.scala:348:23] reg dis_ldq_oh_8; // @[lsu.scala:348:23] reg dis_ldq_oh_9; // @[lsu.scala:348:23] reg dis_ldq_oh_10; // @[lsu.scala:348:23] reg dis_ldq_oh_11; // @[lsu.scala:348:23] reg dis_ldq_oh_12; // @[lsu.scala:348:23] reg dis_ldq_oh_13; // @[lsu.scala:348:23] reg dis_ldq_oh_14; // @[lsu.scala:348:23] reg dis_ldq_oh_15; // @[lsu.scala:348:23] reg dis_stq_oh_0; // @[lsu.scala:349:23] reg dis_stq_oh_1; // @[lsu.scala:349:23] reg dis_stq_oh_2; // @[lsu.scala:349:23] reg dis_stq_oh_3; // @[lsu.scala:349:23] reg dis_stq_oh_4; // @[lsu.scala:349:23] reg dis_stq_oh_5; // @[lsu.scala:349:23] reg dis_stq_oh_6; // @[lsu.scala:349:23] reg dis_stq_oh_7; // @[lsu.scala:349:23] reg dis_stq_oh_8; // @[lsu.scala:349:23] reg dis_stq_oh_9; // @[lsu.scala:349:23] reg dis_stq_oh_10; // @[lsu.scala:349:23] reg dis_stq_oh_11; // @[lsu.scala:349:23] reg dis_stq_oh_12; // @[lsu.scala:349:23] reg dis_stq_oh_13; // @[lsu.scala:349:23] reg dis_stq_oh_14; // @[lsu.scala:349:23] reg dis_stq_oh_15; // @[lsu.scala:349:23] reg dis_uops_0_valid; // @[lsu.scala:352:23] reg [31:0] dis_uops_0_bits_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_inst = dis_uops_0_bits_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_inst = dis_uops_0_bits_inst; // @[util.scala:104:23] reg [31:0] dis_uops_0_bits_debug_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_debug_inst = dis_uops_0_bits_debug_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_debug_inst = dis_uops_0_bits_debug_inst; // @[util.scala:104:23] reg dis_uops_0_bits_is_rvc; // @[lsu.scala:352:23] wire ldq_uop_out_is_rvc = dis_uops_0_bits_is_rvc; // @[util.scala:104:23] wire stq_uop_out_is_rvc = dis_uops_0_bits_is_rvc; // @[util.scala:104:23] reg [39:0] dis_uops_0_bits_debug_pc; // @[lsu.scala:352:23] wire [39:0] ldq_uop_out_debug_pc = dis_uops_0_bits_debug_pc; // @[util.scala:104:23] wire [39:0] stq_uop_out_debug_pc = dis_uops_0_bits_debug_pc; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_0; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_0 = dis_uops_0_bits_iq_type_0; // @[util.scala:104:23] wire stq_uop_out_iq_type_0 = dis_uops_0_bits_iq_type_0; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_1; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_1 = dis_uops_0_bits_iq_type_1; // @[util.scala:104:23] wire stq_uop_out_iq_type_1 = dis_uops_0_bits_iq_type_1; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_2; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_2 = dis_uops_0_bits_iq_type_2; // @[util.scala:104:23] wire stq_uop_out_iq_type_2 = dis_uops_0_bits_iq_type_2; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_3; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_3 = dis_uops_0_bits_iq_type_3; // @[util.scala:104:23] wire stq_uop_out_iq_type_3 = dis_uops_0_bits_iq_type_3; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_0; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_0 = dis_uops_0_bits_fu_code_0; // @[util.scala:104:23] wire stq_uop_out_fu_code_0 = dis_uops_0_bits_fu_code_0; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_1; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_1 = dis_uops_0_bits_fu_code_1; // @[util.scala:104:23] wire stq_uop_out_fu_code_1 = dis_uops_0_bits_fu_code_1; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_2; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_2 = dis_uops_0_bits_fu_code_2; // @[util.scala:104:23] wire stq_uop_out_fu_code_2 = dis_uops_0_bits_fu_code_2; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_3; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_3 = dis_uops_0_bits_fu_code_3; // @[util.scala:104:23] wire stq_uop_out_fu_code_3 = dis_uops_0_bits_fu_code_3; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_4; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_4 = dis_uops_0_bits_fu_code_4; // @[util.scala:104:23] wire stq_uop_out_fu_code_4 = dis_uops_0_bits_fu_code_4; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_5; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_5 = dis_uops_0_bits_fu_code_5; // @[util.scala:104:23] wire stq_uop_out_fu_code_5 = dis_uops_0_bits_fu_code_5; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_6; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_6 = dis_uops_0_bits_fu_code_6; // @[util.scala:104:23] wire stq_uop_out_fu_code_6 = dis_uops_0_bits_fu_code_6; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_7; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_7 = dis_uops_0_bits_fu_code_7; // @[util.scala:104:23] wire stq_uop_out_fu_code_7 = dis_uops_0_bits_fu_code_7; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_8; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_8 = dis_uops_0_bits_fu_code_8; // @[util.scala:104:23] wire stq_uop_out_fu_code_8 = dis_uops_0_bits_fu_code_8; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_9; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_9 = dis_uops_0_bits_fu_code_9; // @[util.scala:104:23] wire stq_uop_out_fu_code_9 = dis_uops_0_bits_fu_code_9; // @[util.scala:104:23] reg dis_uops_0_bits_iw_issued; // @[lsu.scala:352:23] wire ldq_uop_out_iw_issued = dis_uops_0_bits_iw_issued; // @[util.scala:104:23] wire stq_uop_out_iw_issued = dis_uops_0_bits_iw_issued; // @[util.scala:104:23] reg dis_uops_0_bits_iw_issued_partial_agen; // @[lsu.scala:352:23] wire ldq_uop_out_iw_issued_partial_agen = dis_uops_0_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire stq_uop_out_iw_issued_partial_agen = dis_uops_0_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg dis_uops_0_bits_iw_issued_partial_dgen; // @[lsu.scala:352:23] wire ldq_uop_out_iw_issued_partial_dgen = dis_uops_0_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire stq_uop_out_iw_issued_partial_dgen = dis_uops_0_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_iw_p1_speculative_child; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_iw_p1_speculative_child = dis_uops_0_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] stq_uop_out_iw_p1_speculative_child = dis_uops_0_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_iw_p2_speculative_child; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_iw_p2_speculative_child = dis_uops_0_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire [1:0] stq_uop_out_iw_p2_speculative_child = dis_uops_0_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg dis_uops_0_bits_iw_p1_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_iw_p1_bypass_hint = dis_uops_0_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_iw_p1_bypass_hint = dis_uops_0_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg dis_uops_0_bits_iw_p2_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_iw_p2_bypass_hint = dis_uops_0_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_iw_p2_bypass_hint = dis_uops_0_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg dis_uops_0_bits_iw_p3_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_iw_p3_bypass_hint = dis_uops_0_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_iw_p3_bypass_hint = dis_uops_0_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_dis_col_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_dis_col_sel = dis_uops_0_bits_dis_col_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_dis_col_sel = dis_uops_0_bits_dis_col_sel; // @[util.scala:104:23] reg [11:0] dis_uops_0_bits_br_mask; // @[lsu.scala:352:23] reg [3:0] dis_uops_0_bits_br_tag; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_br_tag = dis_uops_0_bits_br_tag; // @[util.scala:104:23] wire [3:0] stq_uop_out_br_tag = dis_uops_0_bits_br_tag; // @[util.scala:104:23] reg [3:0] dis_uops_0_bits_br_type; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_br_type = dis_uops_0_bits_br_type; // @[util.scala:104:23] wire [3:0] stq_uop_out_br_type = dis_uops_0_bits_br_type; // @[util.scala:104:23] reg dis_uops_0_bits_is_sfb; // @[lsu.scala:352:23] wire ldq_uop_out_is_sfb = dis_uops_0_bits_is_sfb; // @[util.scala:104:23] wire stq_uop_out_is_sfb = dis_uops_0_bits_is_sfb; // @[util.scala:104:23] reg dis_uops_0_bits_is_fence; // @[lsu.scala:352:23] wire ldq_uop_out_is_fence = dis_uops_0_bits_is_fence; // @[util.scala:104:23] wire stq_uop_out_is_fence = dis_uops_0_bits_is_fence; // @[util.scala:104:23] reg dis_uops_0_bits_is_fencei; // @[lsu.scala:352:23] wire ldq_uop_out_is_fencei = dis_uops_0_bits_is_fencei; // @[util.scala:104:23] wire stq_uop_out_is_fencei = dis_uops_0_bits_is_fencei; // @[util.scala:104:23] reg dis_uops_0_bits_is_sfence; // @[lsu.scala:352:23] wire ldq_uop_out_is_sfence = dis_uops_0_bits_is_sfence; // @[util.scala:104:23] wire stq_uop_out_is_sfence = dis_uops_0_bits_is_sfence; // @[util.scala:104:23] reg dis_uops_0_bits_is_amo; // @[lsu.scala:352:23] wire ldq_uop_out_is_amo = dis_uops_0_bits_is_amo; // @[util.scala:104:23] wire stq_uop_out_is_amo = dis_uops_0_bits_is_amo; // @[util.scala:104:23] reg dis_uops_0_bits_is_eret; // @[lsu.scala:352:23] wire ldq_uop_out_is_eret = dis_uops_0_bits_is_eret; // @[util.scala:104:23] wire stq_uop_out_is_eret = dis_uops_0_bits_is_eret; // @[util.scala:104:23] reg dis_uops_0_bits_is_sys_pc2epc; // @[lsu.scala:352:23] wire ldq_uop_out_is_sys_pc2epc = dis_uops_0_bits_is_sys_pc2epc; // @[util.scala:104:23] wire stq_uop_out_is_sys_pc2epc = dis_uops_0_bits_is_sys_pc2epc; // @[util.scala:104:23] reg dis_uops_0_bits_is_rocc; // @[lsu.scala:352:23] wire ldq_uop_out_is_rocc = dis_uops_0_bits_is_rocc; // @[util.scala:104:23] wire stq_uop_out_is_rocc = dis_uops_0_bits_is_rocc; // @[util.scala:104:23] reg dis_uops_0_bits_is_mov; // @[lsu.scala:352:23] wire ldq_uop_out_is_mov = dis_uops_0_bits_is_mov; // @[util.scala:104:23] wire stq_uop_out_is_mov = dis_uops_0_bits_is_mov; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_ftq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_ftq_idx = dis_uops_0_bits_ftq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_ftq_idx = dis_uops_0_bits_ftq_idx; // @[util.scala:104:23] reg dis_uops_0_bits_edge_inst; // @[lsu.scala:352:23] wire ldq_uop_out_edge_inst = dis_uops_0_bits_edge_inst; // @[util.scala:104:23] wire stq_uop_out_edge_inst = dis_uops_0_bits_edge_inst; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_pc_lob; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_pc_lob = dis_uops_0_bits_pc_lob; // @[util.scala:104:23] wire [5:0] stq_uop_out_pc_lob = dis_uops_0_bits_pc_lob; // @[util.scala:104:23] reg dis_uops_0_bits_taken; // @[lsu.scala:352:23] wire ldq_uop_out_taken = dis_uops_0_bits_taken; // @[util.scala:104:23] wire stq_uop_out_taken = dis_uops_0_bits_taken; // @[util.scala:104:23] reg dis_uops_0_bits_imm_rename; // @[lsu.scala:352:23] wire ldq_uop_out_imm_rename = dis_uops_0_bits_imm_rename; // @[util.scala:104:23] wire stq_uop_out_imm_rename = dis_uops_0_bits_imm_rename; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_imm_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_imm_sel = dis_uops_0_bits_imm_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_imm_sel = dis_uops_0_bits_imm_sel; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_pimm; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_pimm = dis_uops_0_bits_pimm; // @[util.scala:104:23] wire [4:0] stq_uop_out_pimm = dis_uops_0_bits_pimm; // @[util.scala:104:23] reg [19:0] dis_uops_0_bits_imm_packed; // @[lsu.scala:352:23] wire [19:0] ldq_uop_out_imm_packed = dis_uops_0_bits_imm_packed; // @[util.scala:104:23] wire [19:0] stq_uop_out_imm_packed = dis_uops_0_bits_imm_packed; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_op1_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_op1_sel = dis_uops_0_bits_op1_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_op1_sel = dis_uops_0_bits_op1_sel; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_op2_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_op2_sel = dis_uops_0_bits_op2_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_op2_sel = dis_uops_0_bits_op2_sel; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ldst; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ldst = dis_uops_0_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ldst = dis_uops_0_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_wen; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_wen = dis_uops_0_bits_fp_ctrl_wen; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_wen = dis_uops_0_bits_fp_ctrl_wen; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ren1; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ren1 = dis_uops_0_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ren1 = dis_uops_0_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ren2; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ren2 = dis_uops_0_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ren2 = dis_uops_0_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ren3; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ren3 = dis_uops_0_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ren3 = dis_uops_0_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_swap12; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_swap12 = dis_uops_0_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_swap12 = dis_uops_0_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_swap23; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_swap23 = dis_uops_0_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_swap23 = dis_uops_0_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_fp_ctrl_typeTagIn; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_fp_ctrl_typeTagIn = dis_uops_0_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] stq_uop_out_fp_ctrl_typeTagIn = dis_uops_0_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_fp_ctrl_typeTagOut; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_fp_ctrl_typeTagOut = dis_uops_0_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire [1:0] stq_uop_out_fp_ctrl_typeTagOut = dis_uops_0_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_fromint; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_fromint = dis_uops_0_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_fromint = dis_uops_0_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_toint; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_toint = dis_uops_0_bits_fp_ctrl_toint; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_toint = dis_uops_0_bits_fp_ctrl_toint; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_fastpipe; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_fastpipe = dis_uops_0_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_fastpipe = dis_uops_0_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_fma; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_fma = dis_uops_0_bits_fp_ctrl_fma; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_fma = dis_uops_0_bits_fp_ctrl_fma; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_div; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_div = dis_uops_0_bits_fp_ctrl_div; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_div = dis_uops_0_bits_fp_ctrl_div; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_sqrt; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_sqrt = dis_uops_0_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_sqrt = dis_uops_0_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_wflags; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_wflags = dis_uops_0_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_wflags = dis_uops_0_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_vec; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_vec = dis_uops_0_bits_fp_ctrl_vec; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_vec = dis_uops_0_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_rob_idx; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_rob_idx = dis_uops_0_bits_rob_idx; // @[util.scala:104:23] wire [5:0] stq_uop_out_rob_idx = dis_uops_0_bits_rob_idx; // @[util.scala:104:23] reg [3:0] dis_uops_0_bits_ldq_idx; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_ldq_idx = dis_uops_0_bits_ldq_idx; // @[util.scala:104:23] wire [3:0] stq_uop_out_ldq_idx = dis_uops_0_bits_ldq_idx; // @[util.scala:104:23] reg [3:0] dis_uops_0_bits_stq_idx; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_stq_idx = dis_uops_0_bits_stq_idx; // @[util.scala:104:23] wire [3:0] stq_uop_out_stq_idx = dis_uops_0_bits_stq_idx; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_rxq_idx; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_rxq_idx = dis_uops_0_bits_rxq_idx; // @[util.scala:104:23] wire [1:0] stq_uop_out_rxq_idx = dis_uops_0_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_pdst = dis_uops_0_bits_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_pdst = dis_uops_0_bits_pdst; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_prs1; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_prs1 = dis_uops_0_bits_prs1; // @[util.scala:104:23] wire [6:0] stq_uop_out_prs1 = dis_uops_0_bits_prs1; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_prs2; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_prs2 = dis_uops_0_bits_prs2; // @[util.scala:104:23] wire [6:0] stq_uop_out_prs2 = dis_uops_0_bits_prs2; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_prs3; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_prs3 = dis_uops_0_bits_prs3; // @[util.scala:104:23] wire [6:0] stq_uop_out_prs3 = dis_uops_0_bits_prs3; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_ppred; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_ppred = dis_uops_0_bits_ppred; // @[util.scala:104:23] wire [4:0] stq_uop_out_ppred = dis_uops_0_bits_ppred; // @[util.scala:104:23] reg dis_uops_0_bits_prs1_busy; // @[lsu.scala:352:23] wire ldq_uop_out_prs1_busy = dis_uops_0_bits_prs1_busy; // @[util.scala:104:23] wire stq_uop_out_prs1_busy = dis_uops_0_bits_prs1_busy; // @[util.scala:104:23] reg dis_uops_0_bits_prs2_busy; // @[lsu.scala:352:23] wire ldq_uop_out_prs2_busy = dis_uops_0_bits_prs2_busy; // @[util.scala:104:23] wire stq_uop_out_prs2_busy = dis_uops_0_bits_prs2_busy; // @[util.scala:104:23] reg dis_uops_0_bits_prs3_busy; // @[lsu.scala:352:23] wire ldq_uop_out_prs3_busy = dis_uops_0_bits_prs3_busy; // @[util.scala:104:23] wire stq_uop_out_prs3_busy = dis_uops_0_bits_prs3_busy; // @[util.scala:104:23] reg dis_uops_0_bits_ppred_busy; // @[lsu.scala:352:23] wire ldq_uop_out_ppred_busy = dis_uops_0_bits_ppred_busy; // @[util.scala:104:23] wire stq_uop_out_ppred_busy = dis_uops_0_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_stale_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_stale_pdst = dis_uops_0_bits_stale_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_stale_pdst = dis_uops_0_bits_stale_pdst; // @[util.scala:104:23] reg dis_uops_0_bits_exception; // @[lsu.scala:352:23] wire ldq_uop_out_exception = dis_uops_0_bits_exception; // @[util.scala:104:23] wire stq_uop_out_exception = dis_uops_0_bits_exception; // @[util.scala:104:23] reg [63:0] dis_uops_0_bits_exc_cause; // @[lsu.scala:352:23] wire [63:0] ldq_uop_out_exc_cause = dis_uops_0_bits_exc_cause; // @[util.scala:104:23] wire [63:0] stq_uop_out_exc_cause = dis_uops_0_bits_exc_cause; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_mem_cmd; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_mem_cmd = dis_uops_0_bits_mem_cmd; // @[util.scala:104:23] wire [4:0] stq_uop_out_mem_cmd = dis_uops_0_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_mem_size; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_mem_size = dis_uops_0_bits_mem_size; // @[util.scala:104:23] wire [1:0] stq_uop_out_mem_size = dis_uops_0_bits_mem_size; // @[util.scala:104:23] reg dis_uops_0_bits_mem_signed; // @[lsu.scala:352:23] wire ldq_uop_out_mem_signed = dis_uops_0_bits_mem_signed; // @[util.scala:104:23] wire stq_uop_out_mem_signed = dis_uops_0_bits_mem_signed; // @[util.scala:104:23] reg dis_uops_0_bits_uses_ldq; // @[lsu.scala:352:23] wire ldq_uop_out_uses_ldq = dis_uops_0_bits_uses_ldq; // @[util.scala:104:23] wire stq_uop_out_uses_ldq = dis_uops_0_bits_uses_ldq; // @[util.scala:104:23] reg dis_uops_0_bits_uses_stq; // @[lsu.scala:352:23] wire ldq_uop_out_uses_stq = dis_uops_0_bits_uses_stq; // @[util.scala:104:23] wire stq_uop_out_uses_stq = dis_uops_0_bits_uses_stq; // @[util.scala:104:23] reg dis_uops_0_bits_is_unique; // @[lsu.scala:352:23] wire ldq_uop_out_is_unique = dis_uops_0_bits_is_unique; // @[util.scala:104:23] wire stq_uop_out_is_unique = dis_uops_0_bits_is_unique; // @[util.scala:104:23] reg dis_uops_0_bits_flush_on_commit; // @[lsu.scala:352:23] wire ldq_uop_out_flush_on_commit = dis_uops_0_bits_flush_on_commit; // @[util.scala:104:23] wire stq_uop_out_flush_on_commit = dis_uops_0_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_csr_cmd; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_csr_cmd = dis_uops_0_bits_csr_cmd; // @[util.scala:104:23] wire [2:0] stq_uop_out_csr_cmd = dis_uops_0_bits_csr_cmd; // @[util.scala:104:23] reg dis_uops_0_bits_ldst_is_rs1; // @[lsu.scala:352:23] wire ldq_uop_out_ldst_is_rs1 = dis_uops_0_bits_ldst_is_rs1; // @[util.scala:104:23] wire stq_uop_out_ldst_is_rs1 = dis_uops_0_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_ldst; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_ldst = dis_uops_0_bits_ldst; // @[util.scala:104:23] wire [5:0] stq_uop_out_ldst = dis_uops_0_bits_ldst; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_lrs1; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_lrs1 = dis_uops_0_bits_lrs1; // @[util.scala:104:23] wire [5:0] stq_uop_out_lrs1 = dis_uops_0_bits_lrs1; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_lrs2; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_lrs2 = dis_uops_0_bits_lrs2; // @[util.scala:104:23] wire [5:0] stq_uop_out_lrs2 = dis_uops_0_bits_lrs2; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_lrs3; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_lrs3 = dis_uops_0_bits_lrs3; // @[util.scala:104:23] wire [5:0] stq_uop_out_lrs3 = dis_uops_0_bits_lrs3; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_dst_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_dst_rtype = dis_uops_0_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_dst_rtype = dis_uops_0_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_lrs1_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_lrs1_rtype = dis_uops_0_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_lrs1_rtype = dis_uops_0_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_lrs2_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_lrs2_rtype = dis_uops_0_bits_lrs2_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_lrs2_rtype = dis_uops_0_bits_lrs2_rtype; // @[util.scala:104:23] reg dis_uops_0_bits_frs3_en; // @[lsu.scala:352:23] wire ldq_uop_out_frs3_en = dis_uops_0_bits_frs3_en; // @[util.scala:104:23] wire stq_uop_out_frs3_en = dis_uops_0_bits_frs3_en; // @[util.scala:104:23] reg dis_uops_0_bits_fcn_dw; // @[lsu.scala:352:23] wire ldq_uop_out_fcn_dw = dis_uops_0_bits_fcn_dw; // @[util.scala:104:23] wire stq_uop_out_fcn_dw = dis_uops_0_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_fcn_op; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_fcn_op = dis_uops_0_bits_fcn_op; // @[util.scala:104:23] wire [4:0] stq_uop_out_fcn_op = dis_uops_0_bits_fcn_op; // @[util.scala:104:23] reg dis_uops_0_bits_fp_val; // @[lsu.scala:352:23] wire ldq_uop_out_fp_val = dis_uops_0_bits_fp_val; // @[util.scala:104:23] wire stq_uop_out_fp_val = dis_uops_0_bits_fp_val; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_fp_rm; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_fp_rm = dis_uops_0_bits_fp_rm; // @[util.scala:104:23] wire [2:0] stq_uop_out_fp_rm = dis_uops_0_bits_fp_rm; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_fp_typ; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_fp_typ = dis_uops_0_bits_fp_typ; // @[util.scala:104:23] wire [1:0] stq_uop_out_fp_typ = dis_uops_0_bits_fp_typ; // @[util.scala:104:23] reg dis_uops_0_bits_xcpt_pf_if; // @[lsu.scala:352:23] wire ldq_uop_out_xcpt_pf_if = dis_uops_0_bits_xcpt_pf_if; // @[util.scala:104:23] wire stq_uop_out_xcpt_pf_if = dis_uops_0_bits_xcpt_pf_if; // @[util.scala:104:23] reg dis_uops_0_bits_xcpt_ae_if; // @[lsu.scala:352:23] wire ldq_uop_out_xcpt_ae_if = dis_uops_0_bits_xcpt_ae_if; // @[util.scala:104:23] wire stq_uop_out_xcpt_ae_if = dis_uops_0_bits_xcpt_ae_if; // @[util.scala:104:23] reg dis_uops_0_bits_xcpt_ma_if; // @[lsu.scala:352:23] wire ldq_uop_out_xcpt_ma_if = dis_uops_0_bits_xcpt_ma_if; // @[util.scala:104:23] wire stq_uop_out_xcpt_ma_if = dis_uops_0_bits_xcpt_ma_if; // @[util.scala:104:23] reg dis_uops_0_bits_bp_debug_if; // @[lsu.scala:352:23] wire ldq_uop_out_bp_debug_if = dis_uops_0_bits_bp_debug_if; // @[util.scala:104:23] wire stq_uop_out_bp_debug_if = dis_uops_0_bits_bp_debug_if; // @[util.scala:104:23] reg dis_uops_0_bits_bp_xcpt_if; // @[lsu.scala:352:23] wire ldq_uop_out_bp_xcpt_if = dis_uops_0_bits_bp_xcpt_if; // @[util.scala:104:23] wire stq_uop_out_bp_xcpt_if = dis_uops_0_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_debug_fsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_debug_fsrc = dis_uops_0_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_debug_fsrc = dis_uops_0_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_debug_tsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_debug_tsrc = dis_uops_0_bits_debug_tsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_debug_tsrc = dis_uops_0_bits_debug_tsrc; // @[util.scala:104:23] reg dis_uops_1_valid; // @[lsu.scala:352:23] reg [31:0] dis_uops_1_bits_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_1_inst = dis_uops_1_bits_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_1_inst = dis_uops_1_bits_inst; // @[util.scala:104:23] reg [31:0] dis_uops_1_bits_debug_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_1_debug_inst = dis_uops_1_bits_debug_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_1_debug_inst = dis_uops_1_bits_debug_inst; // @[util.scala:104:23] reg dis_uops_1_bits_is_rvc; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_rvc = dis_uops_1_bits_is_rvc; // @[util.scala:104:23] wire stq_uop_out_1_is_rvc = dis_uops_1_bits_is_rvc; // @[util.scala:104:23] reg [39:0] dis_uops_1_bits_debug_pc; // @[lsu.scala:352:23] wire [39:0] ldq_uop_out_1_debug_pc = dis_uops_1_bits_debug_pc; // @[util.scala:104:23] wire [39:0] stq_uop_out_1_debug_pc = dis_uops_1_bits_debug_pc; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_0; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_0 = dis_uops_1_bits_iq_type_0; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_0 = dis_uops_1_bits_iq_type_0; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_1; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_1 = dis_uops_1_bits_iq_type_1; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_1 = dis_uops_1_bits_iq_type_1; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_2; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_2 = dis_uops_1_bits_iq_type_2; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_2 = dis_uops_1_bits_iq_type_2; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_3; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_3 = dis_uops_1_bits_iq_type_3; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_3 = dis_uops_1_bits_iq_type_3; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_0; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_0 = dis_uops_1_bits_fu_code_0; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_0 = dis_uops_1_bits_fu_code_0; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_1; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_1 = dis_uops_1_bits_fu_code_1; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_1 = dis_uops_1_bits_fu_code_1; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_2; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_2 = dis_uops_1_bits_fu_code_2; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_2 = dis_uops_1_bits_fu_code_2; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_3; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_3 = dis_uops_1_bits_fu_code_3; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_3 = dis_uops_1_bits_fu_code_3; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_4; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_4 = dis_uops_1_bits_fu_code_4; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_4 = dis_uops_1_bits_fu_code_4; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_5; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_5 = dis_uops_1_bits_fu_code_5; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_5 = dis_uops_1_bits_fu_code_5; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_6; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_6 = dis_uops_1_bits_fu_code_6; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_6 = dis_uops_1_bits_fu_code_6; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_7; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_7 = dis_uops_1_bits_fu_code_7; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_7 = dis_uops_1_bits_fu_code_7; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_8; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_8 = dis_uops_1_bits_fu_code_8; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_8 = dis_uops_1_bits_fu_code_8; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_9; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_9 = dis_uops_1_bits_fu_code_9; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_9 = dis_uops_1_bits_fu_code_9; // @[util.scala:104:23] reg dis_uops_1_bits_iw_issued; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_issued = dis_uops_1_bits_iw_issued; // @[util.scala:104:23] wire stq_uop_out_1_iw_issued = dis_uops_1_bits_iw_issued; // @[util.scala:104:23] reg dis_uops_1_bits_iw_issued_partial_agen; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_issued_partial_agen = dis_uops_1_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire stq_uop_out_1_iw_issued_partial_agen = dis_uops_1_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg dis_uops_1_bits_iw_issued_partial_dgen; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_issued_partial_dgen = dis_uops_1_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire stq_uop_out_1_iw_issued_partial_dgen = dis_uops_1_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_iw_p1_speculative_child; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_iw_p1_speculative_child = dis_uops_1_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_iw_p1_speculative_child = dis_uops_1_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_iw_p2_speculative_child; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_iw_p2_speculative_child = dis_uops_1_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_iw_p2_speculative_child = dis_uops_1_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg dis_uops_1_bits_iw_p1_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_p1_bypass_hint = dis_uops_1_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_1_iw_p1_bypass_hint = dis_uops_1_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg dis_uops_1_bits_iw_p2_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_p2_bypass_hint = dis_uops_1_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_1_iw_p2_bypass_hint = dis_uops_1_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg dis_uops_1_bits_iw_p3_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_p3_bypass_hint = dis_uops_1_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_1_iw_p3_bypass_hint = dis_uops_1_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_dis_col_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_dis_col_sel = dis_uops_1_bits_dis_col_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_dis_col_sel = dis_uops_1_bits_dis_col_sel; // @[util.scala:104:23] reg [11:0] dis_uops_1_bits_br_mask; // @[lsu.scala:352:23] reg [3:0] dis_uops_1_bits_br_tag; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_1_br_tag = dis_uops_1_bits_br_tag; // @[util.scala:104:23] wire [3:0] stq_uop_out_1_br_tag = dis_uops_1_bits_br_tag; // @[util.scala:104:23] reg [3:0] dis_uops_1_bits_br_type; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_1_br_type = dis_uops_1_bits_br_type; // @[util.scala:104:23] wire [3:0] stq_uop_out_1_br_type = dis_uops_1_bits_br_type; // @[util.scala:104:23] reg dis_uops_1_bits_is_sfb; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_sfb = dis_uops_1_bits_is_sfb; // @[util.scala:104:23] wire stq_uop_out_1_is_sfb = dis_uops_1_bits_is_sfb; // @[util.scala:104:23] reg dis_uops_1_bits_is_fence; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_fence = dis_uops_1_bits_is_fence; // @[util.scala:104:23] wire stq_uop_out_1_is_fence = dis_uops_1_bits_is_fence; // @[util.scala:104:23] reg dis_uops_1_bits_is_fencei; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_fencei = dis_uops_1_bits_is_fencei; // @[util.scala:104:23] wire stq_uop_out_1_is_fencei = dis_uops_1_bits_is_fencei; // @[util.scala:104:23] reg dis_uops_1_bits_is_sfence; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_sfence = dis_uops_1_bits_is_sfence; // @[util.scala:104:23] wire stq_uop_out_1_is_sfence = dis_uops_1_bits_is_sfence; // @[util.scala:104:23] reg dis_uops_1_bits_is_amo; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_amo = dis_uops_1_bits_is_amo; // @[util.scala:104:23] wire stq_uop_out_1_is_amo = dis_uops_1_bits_is_amo; // @[util.scala:104:23] reg dis_uops_1_bits_is_eret; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_eret = dis_uops_1_bits_is_eret; // @[util.scala:104:23] wire stq_uop_out_1_is_eret = dis_uops_1_bits_is_eret; // @[util.scala:104:23] reg dis_uops_1_bits_is_sys_pc2epc; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_sys_pc2epc = dis_uops_1_bits_is_sys_pc2epc; // @[util.scala:104:23] wire stq_uop_out_1_is_sys_pc2epc = dis_uops_1_bits_is_sys_pc2epc; // @[util.scala:104:23] reg dis_uops_1_bits_is_rocc; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_rocc = dis_uops_1_bits_is_rocc; // @[util.scala:104:23] wire stq_uop_out_1_is_rocc = dis_uops_1_bits_is_rocc; // @[util.scala:104:23] reg dis_uops_1_bits_is_mov; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_mov = dis_uops_1_bits_is_mov; // @[util.scala:104:23] wire stq_uop_out_1_is_mov = dis_uops_1_bits_is_mov; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_ftq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_ftq_idx = dis_uops_1_bits_ftq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_ftq_idx = dis_uops_1_bits_ftq_idx; // @[util.scala:104:23] reg dis_uops_1_bits_edge_inst; // @[lsu.scala:352:23] wire ldq_uop_out_1_edge_inst = dis_uops_1_bits_edge_inst; // @[util.scala:104:23] wire stq_uop_out_1_edge_inst = dis_uops_1_bits_edge_inst; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_pc_lob; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_pc_lob = dis_uops_1_bits_pc_lob; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_pc_lob = dis_uops_1_bits_pc_lob; // @[util.scala:104:23] reg dis_uops_1_bits_taken; // @[lsu.scala:352:23] wire ldq_uop_out_1_taken = dis_uops_1_bits_taken; // @[util.scala:104:23] wire stq_uop_out_1_taken = dis_uops_1_bits_taken; // @[util.scala:104:23] reg dis_uops_1_bits_imm_rename; // @[lsu.scala:352:23] wire ldq_uop_out_1_imm_rename = dis_uops_1_bits_imm_rename; // @[util.scala:104:23] wire stq_uop_out_1_imm_rename = dis_uops_1_bits_imm_rename; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_imm_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_imm_sel = dis_uops_1_bits_imm_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_imm_sel = dis_uops_1_bits_imm_sel; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_pimm; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_pimm = dis_uops_1_bits_pimm; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_pimm = dis_uops_1_bits_pimm; // @[util.scala:104:23] reg [19:0] dis_uops_1_bits_imm_packed; // @[lsu.scala:352:23] wire [19:0] ldq_uop_out_1_imm_packed = dis_uops_1_bits_imm_packed; // @[util.scala:104:23] wire [19:0] stq_uop_out_1_imm_packed = dis_uops_1_bits_imm_packed; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_op1_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_op1_sel = dis_uops_1_bits_op1_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_op1_sel = dis_uops_1_bits_op1_sel; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_op2_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_op2_sel = dis_uops_1_bits_op2_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_op2_sel = dis_uops_1_bits_op2_sel; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ldst; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ldst = dis_uops_1_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ldst = dis_uops_1_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_wen; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_wen = dis_uops_1_bits_fp_ctrl_wen; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_wen = dis_uops_1_bits_fp_ctrl_wen; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ren1; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ren1 = dis_uops_1_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ren1 = dis_uops_1_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ren2; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ren2 = dis_uops_1_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ren2 = dis_uops_1_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ren3; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ren3 = dis_uops_1_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ren3 = dis_uops_1_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_swap12; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_swap12 = dis_uops_1_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_swap12 = dis_uops_1_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_swap23; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_swap23 = dis_uops_1_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_swap23 = dis_uops_1_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_fp_ctrl_typeTagIn; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_fp_ctrl_typeTagIn = dis_uops_1_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_fp_ctrl_typeTagIn = dis_uops_1_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_fp_ctrl_typeTagOut; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_fp_ctrl_typeTagOut = dis_uops_1_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_fp_ctrl_typeTagOut = dis_uops_1_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_fromint; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_fromint = dis_uops_1_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_fromint = dis_uops_1_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_toint; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_toint = dis_uops_1_bits_fp_ctrl_toint; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_toint = dis_uops_1_bits_fp_ctrl_toint; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_fastpipe; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_fastpipe = dis_uops_1_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_fastpipe = dis_uops_1_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_fma; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_fma = dis_uops_1_bits_fp_ctrl_fma; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_fma = dis_uops_1_bits_fp_ctrl_fma; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_div; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_div = dis_uops_1_bits_fp_ctrl_div; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_div = dis_uops_1_bits_fp_ctrl_div; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_sqrt; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_sqrt = dis_uops_1_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_sqrt = dis_uops_1_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_wflags; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_wflags = dis_uops_1_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_wflags = dis_uops_1_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_vec; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_vec = dis_uops_1_bits_fp_ctrl_vec; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_vec = dis_uops_1_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_rob_idx; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_rob_idx = dis_uops_1_bits_rob_idx; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_rob_idx = dis_uops_1_bits_rob_idx; // @[util.scala:104:23] reg [3:0] dis_uops_1_bits_ldq_idx; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_1_ldq_idx = dis_uops_1_bits_ldq_idx; // @[util.scala:104:23] wire [3:0] stq_uop_out_1_ldq_idx = dis_uops_1_bits_ldq_idx; // @[util.scala:104:23] reg [3:0] dis_uops_1_bits_stq_idx; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_1_stq_idx = dis_uops_1_bits_stq_idx; // @[util.scala:104:23] wire [3:0] stq_uop_out_1_stq_idx = dis_uops_1_bits_stq_idx; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_rxq_idx; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_rxq_idx = dis_uops_1_bits_rxq_idx; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_rxq_idx = dis_uops_1_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_pdst = dis_uops_1_bits_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_pdst = dis_uops_1_bits_pdst; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_prs1; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_prs1 = dis_uops_1_bits_prs1; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_prs1 = dis_uops_1_bits_prs1; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_prs2; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_prs2 = dis_uops_1_bits_prs2; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_prs2 = dis_uops_1_bits_prs2; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_prs3; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_prs3 = dis_uops_1_bits_prs3; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_prs3 = dis_uops_1_bits_prs3; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_ppred; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_ppred = dis_uops_1_bits_ppred; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_ppred = dis_uops_1_bits_ppred; // @[util.scala:104:23] reg dis_uops_1_bits_prs1_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_prs1_busy = dis_uops_1_bits_prs1_busy; // @[util.scala:104:23] wire stq_uop_out_1_prs1_busy = dis_uops_1_bits_prs1_busy; // @[util.scala:104:23] reg dis_uops_1_bits_prs2_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_prs2_busy = dis_uops_1_bits_prs2_busy; // @[util.scala:104:23] wire stq_uop_out_1_prs2_busy = dis_uops_1_bits_prs2_busy; // @[util.scala:104:23] reg dis_uops_1_bits_prs3_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_prs3_busy = dis_uops_1_bits_prs3_busy; // @[util.scala:104:23] wire stq_uop_out_1_prs3_busy = dis_uops_1_bits_prs3_busy; // @[util.scala:104:23] reg dis_uops_1_bits_ppred_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_ppred_busy = dis_uops_1_bits_ppred_busy; // @[util.scala:104:23] wire stq_uop_out_1_ppred_busy = dis_uops_1_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_stale_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_stale_pdst = dis_uops_1_bits_stale_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_stale_pdst = dis_uops_1_bits_stale_pdst; // @[util.scala:104:23] reg dis_uops_1_bits_exception; // @[lsu.scala:352:23] wire ldq_uop_out_1_exception = dis_uops_1_bits_exception; // @[util.scala:104:23] wire stq_uop_out_1_exception = dis_uops_1_bits_exception; // @[util.scala:104:23] reg [63:0] dis_uops_1_bits_exc_cause; // @[lsu.scala:352:23] wire [63:0] ldq_uop_out_1_exc_cause = dis_uops_1_bits_exc_cause; // @[util.scala:104:23] wire [63:0] stq_uop_out_1_exc_cause = dis_uops_1_bits_exc_cause; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_mem_cmd; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_mem_cmd = dis_uops_1_bits_mem_cmd; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_mem_cmd = dis_uops_1_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_mem_size; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_mem_size = dis_uops_1_bits_mem_size; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_mem_size = dis_uops_1_bits_mem_size; // @[util.scala:104:23] reg dis_uops_1_bits_mem_signed; // @[lsu.scala:352:23] wire ldq_uop_out_1_mem_signed = dis_uops_1_bits_mem_signed; // @[util.scala:104:23] wire stq_uop_out_1_mem_signed = dis_uops_1_bits_mem_signed; // @[util.scala:104:23] reg dis_uops_1_bits_uses_ldq; // @[lsu.scala:352:23] wire ldq_uop_out_1_uses_ldq = dis_uops_1_bits_uses_ldq; // @[util.scala:104:23] wire stq_uop_out_1_uses_ldq = dis_uops_1_bits_uses_ldq; // @[util.scala:104:23] reg dis_uops_1_bits_uses_stq; // @[lsu.scala:352:23] wire ldq_uop_out_1_uses_stq = dis_uops_1_bits_uses_stq; // @[util.scala:104:23] wire stq_uop_out_1_uses_stq = dis_uops_1_bits_uses_stq; // @[util.scala:104:23] reg dis_uops_1_bits_is_unique; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_unique = dis_uops_1_bits_is_unique; // @[util.scala:104:23] wire stq_uop_out_1_is_unique = dis_uops_1_bits_is_unique; // @[util.scala:104:23] reg dis_uops_1_bits_flush_on_commit; // @[lsu.scala:352:23] wire ldq_uop_out_1_flush_on_commit = dis_uops_1_bits_flush_on_commit; // @[util.scala:104:23] wire stq_uop_out_1_flush_on_commit = dis_uops_1_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_csr_cmd; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_csr_cmd = dis_uops_1_bits_csr_cmd; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_csr_cmd = dis_uops_1_bits_csr_cmd; // @[util.scala:104:23] reg dis_uops_1_bits_ldst_is_rs1; // @[lsu.scala:352:23] wire ldq_uop_out_1_ldst_is_rs1 = dis_uops_1_bits_ldst_is_rs1; // @[util.scala:104:23] wire stq_uop_out_1_ldst_is_rs1 = dis_uops_1_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_ldst; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_ldst = dis_uops_1_bits_ldst; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_ldst = dis_uops_1_bits_ldst; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_lrs1; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_lrs1 = dis_uops_1_bits_lrs1; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_lrs1 = dis_uops_1_bits_lrs1; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_lrs2; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_lrs2 = dis_uops_1_bits_lrs2; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_lrs2 = dis_uops_1_bits_lrs2; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_lrs3; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_lrs3 = dis_uops_1_bits_lrs3; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_lrs3 = dis_uops_1_bits_lrs3; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_dst_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_dst_rtype = dis_uops_1_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_dst_rtype = dis_uops_1_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_lrs1_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_lrs1_rtype = dis_uops_1_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_lrs1_rtype = dis_uops_1_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_lrs2_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_lrs2_rtype = dis_uops_1_bits_lrs2_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_lrs2_rtype = dis_uops_1_bits_lrs2_rtype; // @[util.scala:104:23] reg dis_uops_1_bits_frs3_en; // @[lsu.scala:352:23] wire ldq_uop_out_1_frs3_en = dis_uops_1_bits_frs3_en; // @[util.scala:104:23] wire stq_uop_out_1_frs3_en = dis_uops_1_bits_frs3_en; // @[util.scala:104:23] reg dis_uops_1_bits_fcn_dw; // @[lsu.scala:352:23] wire ldq_uop_out_1_fcn_dw = dis_uops_1_bits_fcn_dw; // @[util.scala:104:23] wire stq_uop_out_1_fcn_dw = dis_uops_1_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_fcn_op; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_fcn_op = dis_uops_1_bits_fcn_op; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_fcn_op = dis_uops_1_bits_fcn_op; // @[util.scala:104:23] reg dis_uops_1_bits_fp_val; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_val = dis_uops_1_bits_fp_val; // @[util.scala:104:23] wire stq_uop_out_1_fp_val = dis_uops_1_bits_fp_val; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_fp_rm; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_fp_rm = dis_uops_1_bits_fp_rm; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_fp_rm = dis_uops_1_bits_fp_rm; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_fp_typ; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_fp_typ = dis_uops_1_bits_fp_typ; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_fp_typ = dis_uops_1_bits_fp_typ; // @[util.scala:104:23] reg dis_uops_1_bits_xcpt_pf_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_xcpt_pf_if = dis_uops_1_bits_xcpt_pf_if; // @[util.scala:104:23] wire stq_uop_out_1_xcpt_pf_if = dis_uops_1_bits_xcpt_pf_if; // @[util.scala:104:23] reg dis_uops_1_bits_xcpt_ae_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_xcpt_ae_if = dis_uops_1_bits_xcpt_ae_if; // @[util.scala:104:23] wire stq_uop_out_1_xcpt_ae_if = dis_uops_1_bits_xcpt_ae_if; // @[util.scala:104:23] reg dis_uops_1_bits_xcpt_ma_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_xcpt_ma_if = dis_uops_1_bits_xcpt_ma_if; // @[util.scala:104:23] wire stq_uop_out_1_xcpt_ma_if = dis_uops_1_bits_xcpt_ma_if; // @[util.scala:104:23] reg dis_uops_1_bits_bp_debug_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_bp_debug_if = dis_uops_1_bits_bp_debug_if; // @[util.scala:104:23] wire stq_uop_out_1_bp_debug_if = dis_uops_1_bits_bp_debug_if; // @[util.scala:104:23] reg dis_uops_1_bits_bp_xcpt_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_bp_xcpt_if = dis_uops_1_bits_bp_xcpt_if; // @[util.scala:104:23] wire stq_uop_out_1_bp_xcpt_if = dis_uops_1_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_debug_fsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_debug_fsrc = dis_uops_1_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_debug_fsrc = dis_uops_1_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_debug_tsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_debug_tsrc = dis_uops_1_bits_debug_tsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_debug_tsrc = dis_uops_1_bits_debug_tsrc; // @[util.scala:104:23] wire [1:0] _GEN_0 = {stq_valid_1, stq_valid_0}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_lo_lo; // @[lsu.scala:354:35] assign live_store_mask_lo_lo_lo = _GEN_0; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_lo_lo; // @[lsu.scala:362:31] assign stq_valids_lo_lo_lo = _GEN_0; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_lo_lo; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_lo_lo = _GEN_0; // @[lsu.scala:354:35, :1342:35] wire [1:0] _GEN_1 = {stq_valid_3, stq_valid_2}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_lo_hi; // @[lsu.scala:354:35] assign live_store_mask_lo_lo_hi = _GEN_1; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_lo_hi; // @[lsu.scala:362:31] assign stq_valids_lo_lo_hi = _GEN_1; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_lo_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_lo_hi = _GEN_1; // @[lsu.scala:354:35, :1342:35] wire [3:0] live_store_mask_lo_lo = {live_store_mask_lo_lo_hi, live_store_mask_lo_lo_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_2 = {stq_valid_5, stq_valid_4}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_hi_lo; // @[lsu.scala:354:35] assign live_store_mask_lo_hi_lo = _GEN_2; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_hi_lo; // @[lsu.scala:362:31] assign stq_valids_lo_hi_lo = _GEN_2; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_hi_lo; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_hi_lo = _GEN_2; // @[lsu.scala:354:35, :1342:35] wire [1:0] _GEN_3 = {stq_valid_7, stq_valid_6}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_hi_hi; // @[lsu.scala:354:35] assign live_store_mask_lo_hi_hi = _GEN_3; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_hi_hi; // @[lsu.scala:362:31] assign stq_valids_lo_hi_hi = _GEN_3; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_hi_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_hi_hi = _GEN_3; // @[lsu.scala:354:35, :1342:35] wire [3:0] live_store_mask_lo_hi = {live_store_mask_lo_hi_hi, live_store_mask_lo_hi_lo}; // @[lsu.scala:354:35] wire [7:0] live_store_mask_lo = {live_store_mask_lo_hi, live_store_mask_lo_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_4 = {stq_valid_9, stq_valid_8}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_lo_lo; // @[lsu.scala:354:35] assign live_store_mask_hi_lo_lo = _GEN_4; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_lo_lo; // @[lsu.scala:362:31] assign stq_valids_hi_lo_lo = _GEN_4; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_lo_lo; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_lo_lo = _GEN_4; // @[lsu.scala:354:35, :1342:35] wire [1:0] _GEN_5 = {stq_valid_11, stq_valid_10}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_lo_hi; // @[lsu.scala:354:35] assign live_store_mask_hi_lo_hi = _GEN_5; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_lo_hi; // @[lsu.scala:362:31] assign stq_valids_hi_lo_hi = _GEN_5; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_lo_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_lo_hi = _GEN_5; // @[lsu.scala:354:35, :1342:35] wire [3:0] live_store_mask_hi_lo = {live_store_mask_hi_lo_hi, live_store_mask_hi_lo_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_6 = {stq_valid_13, stq_valid_12}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_hi_lo; // @[lsu.scala:354:35] assign live_store_mask_hi_hi_lo = _GEN_6; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_hi_lo; // @[lsu.scala:362:31] assign stq_valids_hi_hi_lo = _GEN_6; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_hi_lo; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_hi_lo = _GEN_6; // @[lsu.scala:354:35, :1342:35] wire [1:0] _GEN_7 = {stq_valid_15, stq_valid_14}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_hi_hi; // @[lsu.scala:354:35] assign live_store_mask_hi_hi_hi = _GEN_7; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_hi_hi; // @[lsu.scala:362:31] assign stq_valids_hi_hi_hi = _GEN_7; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_hi_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_hi_hi = _GEN_7; // @[lsu.scala:354:35, :1342:35] wire [3:0] live_store_mask_hi_hi = {live_store_mask_hi_hi_hi, live_store_mask_hi_hi_lo}; // @[lsu.scala:354:35] wire [7:0] live_store_mask_hi = {live_store_mask_hi_hi, live_store_mask_hi_lo}; // @[lsu.scala:354:35] wire [15:0] _live_store_mask_T = {live_store_mask_hi, live_store_mask_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_8 = {dis_stq_oh_1, dis_stq_oh_0}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_lo_lo_1; // @[lsu.scala:354:55] assign live_store_mask_lo_lo_lo_1 = _GEN_8; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_lo_lo_1; // @[lsu.scala:362:51] assign stq_valids_lo_lo_lo_1 = _GEN_8; // @[lsu.scala:354:55, :362:51] wire [1:0] _GEN_9 = {dis_stq_oh_3, dis_stq_oh_2}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_lo_hi_1; // @[lsu.scala:354:55] assign live_store_mask_lo_lo_hi_1 = _GEN_9; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_lo_hi_1; // @[lsu.scala:362:51] assign stq_valids_lo_lo_hi_1 = _GEN_9; // @[lsu.scala:354:55, :362:51] wire [3:0] live_store_mask_lo_lo_1 = {live_store_mask_lo_lo_hi_1, live_store_mask_lo_lo_lo_1}; // @[lsu.scala:354:55] wire [1:0] _GEN_10 = {dis_stq_oh_5, dis_stq_oh_4}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_hi_lo_1; // @[lsu.scala:354:55] assign live_store_mask_lo_hi_lo_1 = _GEN_10; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_hi_lo_1; // @[lsu.scala:362:51] assign stq_valids_lo_hi_lo_1 = _GEN_10; // @[lsu.scala:354:55, :362:51] wire [1:0] _GEN_11 = {dis_stq_oh_7, dis_stq_oh_6}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_hi_hi_1; // @[lsu.scala:354:55] assign live_store_mask_lo_hi_hi_1 = _GEN_11; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_hi_hi_1; // @[lsu.scala:362:51] assign stq_valids_lo_hi_hi_1 = _GEN_11; // @[lsu.scala:354:55, :362:51] wire [3:0] live_store_mask_lo_hi_1 = {live_store_mask_lo_hi_hi_1, live_store_mask_lo_hi_lo_1}; // @[lsu.scala:354:55] wire [7:0] live_store_mask_lo_1 = {live_store_mask_lo_hi_1, live_store_mask_lo_lo_1}; // @[lsu.scala:354:55] wire [1:0] _GEN_12 = {dis_stq_oh_9, dis_stq_oh_8}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_lo_lo_1; // @[lsu.scala:354:55] assign live_store_mask_hi_lo_lo_1 = _GEN_12; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_lo_lo_1; // @[lsu.scala:362:51] assign stq_valids_hi_lo_lo_1 = _GEN_12; // @[lsu.scala:354:55, :362:51] wire [1:0] _GEN_13 = {dis_stq_oh_11, dis_stq_oh_10}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_lo_hi_1; // @[lsu.scala:354:55] assign live_store_mask_hi_lo_hi_1 = _GEN_13; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_lo_hi_1; // @[lsu.scala:362:51] assign stq_valids_hi_lo_hi_1 = _GEN_13; // @[lsu.scala:354:55, :362:51] wire [3:0] live_store_mask_hi_lo_1 = {live_store_mask_hi_lo_hi_1, live_store_mask_hi_lo_lo_1}; // @[lsu.scala:354:55] wire [1:0] _GEN_14 = {dis_stq_oh_13, dis_stq_oh_12}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_hi_lo_1; // @[lsu.scala:354:55] assign live_store_mask_hi_hi_lo_1 = _GEN_14; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_hi_lo_1; // @[lsu.scala:362:51] assign stq_valids_hi_hi_lo_1 = _GEN_14; // @[lsu.scala:354:55, :362:51] wire [1:0] _GEN_15 = {dis_stq_oh_15, dis_stq_oh_14}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_hi_hi_1; // @[lsu.scala:354:55] assign live_store_mask_hi_hi_hi_1 = _GEN_15; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_hi_hi_1; // @[lsu.scala:362:51] assign stq_valids_hi_hi_hi_1 = _GEN_15; // @[lsu.scala:354:55, :362:51] wire [3:0] live_store_mask_hi_hi_1 = {live_store_mask_hi_hi_hi_1, live_store_mask_hi_hi_lo_1}; // @[lsu.scala:354:55] wire [7:0] live_store_mask_hi_1 = {live_store_mask_hi_hi_1, live_store_mask_hi_lo_1}; // @[lsu.scala:354:55] wire [15:0] _live_store_mask_T_1 = {live_store_mask_hi_1, live_store_mask_lo_1}; // @[lsu.scala:354:55] wire [15:0] live_store_mask = _live_store_mask_T \| _live_store_mask_T_1; // @[lsu.scala:354:{35,42,55}] wire [15:0] _next_live_store_mask_T_1 = ~_next_live_store_mask_T; // @[lsu.scala:355:{65,71}] wire [15:0] _next_live_store_mask_T_2 = live_store_mask & _next_live_store_mask_T_1; // @[lsu.scala:354:42, :355:{63,65}] wire [15:0] next_live_store_mask = clear_store ? _next_live_store_mask_T_2 : live_store_mask; // @[lsu.scala:318:33, :354:42, :355:{33,63}] wire [15:0] _ldq_tail_oh_T = 16'h1 << ldq_tail; // @[OneHot.scala:58:35] wire [15:0] ldq_tail_oh = _ldq_tail_oh_T; // @[OneHot.scala:58:35] wire [1:0] _GEN_16 = {ldq_valid_1, ldq_valid_0}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_lo_lo; // @[lsu.scala:360:31] assign ldq_valids_lo_lo_lo = _GEN_16; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_lo_lo_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_lo_lo_1 = _GEN_16; // @[lsu.scala:360:31, :1437:58] wire [1:0] _GEN_17 = {ldq_valid_3, ldq_valid_2}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_lo_hi; // @[lsu.scala:360:31] assign ldq_valids_lo_lo_hi = _GEN_17; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_lo_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_lo_hi_1 = _GEN_17; // @[lsu.scala:360:31, :1437:58] wire [3:0] ldq_valids_lo_lo = {ldq_valids_lo_lo_hi, ldq_valids_lo_lo_lo}; // @[lsu.scala:360:31] wire [1:0] _GEN_18 = {ldq_valid_5, ldq_valid_4}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_hi_lo; // @[lsu.scala:360:31] assign ldq_valids_lo_hi_lo = _GEN_18; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_hi_lo_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_hi_lo_1 = _GEN_18; // @[lsu.scala:360:31, :1437:58] wire [1:0] _GEN_19 = {ldq_valid_7, ldq_valid_6}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_hi_hi; // @[lsu.scala:360:31] assign ldq_valids_lo_hi_hi = _GEN_19; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_hi_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_hi_hi_1 = _GEN_19; // @[lsu.scala:360:31, :1437:58] wire [3:0] ldq_valids_lo_hi = {ldq_valids_lo_hi_hi, ldq_valids_lo_hi_lo}; // @[lsu.scala:360:31] wire [7:0] ldq_valids_lo = {ldq_valids_lo_hi, ldq_valids_lo_lo}; // @[lsu.scala:360:31] wire [1:0] _GEN_20 = {ldq_valid_9, ldq_valid_8}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_lo_lo; // @[lsu.scala:360:31] assign ldq_valids_hi_lo_lo = _GEN_20; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_lo_lo_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_lo_lo_1 = _GEN_20; // @[lsu.scala:360:31, :1437:58] wire [1:0] _GEN_21 = {ldq_valid_11, ldq_valid_10}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_lo_hi; // @[lsu.scala:360:31] assign ldq_valids_hi_lo_hi = _GEN_21; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_lo_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_lo_hi_1 = _GEN_21; // @[lsu.scala:360:31, :1437:58] wire [3:0] ldq_valids_hi_lo = {ldq_valids_hi_lo_hi, ldq_valids_hi_lo_lo}; // @[lsu.scala:360:31] wire [1:0] _GEN_22 = {ldq_valid_13, ldq_valid_12}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_hi_lo; // @[lsu.scala:360:31] assign ldq_valids_hi_hi_lo = _GEN_22; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_hi_lo_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_hi_lo_1 = _GEN_22; // @[lsu.scala:360:31, :1437:58] wire [1:0] _GEN_23 = {ldq_valid_15, ldq_valid_14}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_hi_hi; // @[lsu.scala:360:31] assign ldq_valids_hi_hi_hi = _GEN_23; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_hi_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_hi_hi_1 = _GEN_23; // @[lsu.scala:360:31, :1437:58] wire [3:0] ldq_valids_hi_hi = {ldq_valids_hi_hi_hi, ldq_valids_hi_hi_lo}; // @[lsu.scala:360:31] wire [7:0] ldq_valids_hi = {ldq_valids_hi_hi, ldq_valids_hi_lo}; // @[lsu.scala:360:31] wire [15:0] _ldq_valids_T = {ldq_valids_hi, ldq_valids_lo}; // @[lsu.scala:360:31] wire [1:0] ldq_valids_lo_lo_lo_1 = {dis_ldq_oh_1, dis_ldq_oh_0}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_lo_lo_hi_1 = {dis_ldq_oh_3, dis_ldq_oh_2}; // @[lsu.scala:348:23, :360:51] wire [3:0] ldq_valids_lo_lo_1 = {ldq_valids_lo_lo_hi_1, ldq_valids_lo_lo_lo_1}; // @[lsu.scala:360:51] wire [1:0] ldq_valids_lo_hi_lo_1 = {dis_ldq_oh_5, dis_ldq_oh_4}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_lo_hi_hi_1 = {dis_ldq_oh_7, dis_ldq_oh_6}; // @[lsu.scala:348:23, :360:51] wire [3:0] ldq_valids_lo_hi_1 = {ldq_valids_lo_hi_hi_1, ldq_valids_lo_hi_lo_1}; // @[lsu.scala:360:51] wire [7:0] ldq_valids_lo_1 = {ldq_valids_lo_hi_1, ldq_valids_lo_lo_1}; // @[lsu.scala:360:51] wire [1:0] ldq_valids_hi_lo_lo_1 = {dis_ldq_oh_9, dis_ldq_oh_8}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_hi_lo_hi_1 = {dis_ldq_oh_11, dis_ldq_oh_10}; // @[lsu.scala:348:23, :360:51] wire [3:0] ldq_valids_hi_lo_1 = {ldq_valids_hi_lo_hi_1, ldq_valids_hi_lo_lo_1}; // @[lsu.scala:360:51] wire [1:0] ldq_valids_hi_hi_lo_1 = {dis_ldq_oh_13, dis_ldq_oh_12}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_hi_hi_hi_1 = {dis_ldq_oh_15, dis_ldq_oh_14}; // @[lsu.scala:348:23, :360:51] wire [3:0] ldq_valids_hi_hi_1 = {ldq_valids_hi_hi_hi_1, ldq_valids_hi_hi_lo_1}; // @[lsu.scala:360:51] wire [7:0] ldq_valids_hi_1 = {ldq_valids_hi_hi_1, ldq_valids_hi_lo_1}; // @[lsu.scala:360:51] wire [15:0] _ldq_valids_T_1 = {ldq_valids_hi_1, ldq_valids_lo_1}; // @[lsu.scala:360:51] wire [15:0] ldq_valids = _ldq_valids_T \| _ldq_valids_T_1; // @[lsu.scala:360:{31,38,51}] wire [15:0] _stq_tail_oh_T = 16'h1 << stq_tail; // @[OneHot.scala:58:35] wire [15:0] stq_tail_oh = _stq_tail_oh_T; // @[OneHot.scala:58:35] wire [3:0] stq_valids_lo_lo = {stq_valids_lo_lo_hi, stq_valids_lo_lo_lo}; // @[lsu.scala:362:31] wire [3:0] stq_valids_lo_hi = {stq_valids_lo_hi_hi, stq_valids_lo_hi_lo}; // @[lsu.scala:362:31] wire [7:0] stq_valids_lo = {stq_valids_lo_hi, stq_valids_lo_lo}; // @[lsu.scala:362:31] wire [3:0] stq_valids_hi_lo = {stq_valids_hi_lo_hi, stq_valids_hi_lo_lo}; // @[lsu.scala:362:31] wire [3:0] stq_valids_hi_hi = {stq_valids_hi_hi_hi, stq_valids_hi_hi_lo}; // @[lsu.scala:362:31] wire [7:0] stq_valids_hi = {stq_valids_hi_hi, stq_valids_hi_lo}; // @[lsu.scala:362:31] wire [15:0] _stq_valids_T = {stq_valids_hi, stq_valids_lo}; // @[lsu.scala:362:31] wire [3:0] stq_valids_lo_lo_1 = {stq_valids_lo_lo_hi_1, stq_valids_lo_lo_lo_1}; // @[lsu.scala:362:51] wire [3:0] stq_valids_lo_hi_1 = {stq_valids_lo_hi_hi_1, stq_valids_lo_hi_lo_1}; // @[lsu.scala:362:51] wire [7:0] stq_valids_lo_1 = {stq_valids_lo_hi_1, stq_valids_lo_lo_1}; // @[lsu.scala:362:51] wire [3:0] stq_valids_hi_lo_1 = {stq_valids_hi_lo_hi_1, stq_valids_hi_lo_lo_1}; // @[lsu.scala:362:51] wire [3:0] stq_valids_hi_hi_1 = {stq_valids_hi_hi_hi_1, stq_valids_hi_hi_lo_1}; // @[lsu.scala:362:51] wire [7:0] stq_valids_hi_1 = {stq_valids_hi_hi_1, stq_valids_hi_lo_1}; // @[lsu.scala:362:51] wire [15:0] _stq_valids_T_1 = {stq_valids_hi_1, stq_valids_lo_1}; // @[lsu.scala:362:51] wire [15:0] stq_valids = _stq_valids_T \| _stq_valids_T_1; // @[lsu.scala:362:{31,38,51}] wire _GEN_24 = stq_valid_0 \| stq_valid_1; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T; // @[lsu.scala:364:40] assign _stq_nonempty_T = _GEN_24; // @[lsu.scala:364:40] wire _io_hellacache_store_pending_T; // @[lsu.scala:1804:52] assign _io_hellacache_store_pending_T = _GEN_24; // @[lsu.scala:364:40, :1804:52] wire _stq_nonempty_T_1 = _stq_nonempty_T \| stq_valid_2; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_2 = _stq_nonempty_T_1 \| stq_valid_3; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_3 = _stq_nonempty_T_2 \| stq_valid_4; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_4 = _stq_nonempty_T_3 \| stq_valid_5; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_5 = _stq_nonempty_T_4 \| stq_valid_6; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_6 = _stq_nonempty_T_5 \| stq_valid_7; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_7 = _stq_nonempty_T_6 \| stq_valid_8; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_8 = _stq_nonempty_T_7 \| stq_valid_9; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_9 = _stq_nonempty_T_8 \| stq_valid_10; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_10 = _stq_nonempty_T_9 \| stq_valid_11; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_11 = _stq_nonempty_T_10 \| stq_valid_12; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_12 = _stq_nonempty_T_11 \| stq_valid_13; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_13 = _stq_nonempty_T_12 \| stq_valid_14; // @[lsu.scala:251:32, :364:40] wire stq_nonempty = _stq_nonempty_T_13 \| stq_valid_15; // @[lsu.scala:251:32, :364:40] wire [15:0] _ldq_full_T = ldq_tail_oh & ldq_valids; // @[lsu.scala:359:39, :360:38, :369:33] assign ldq_full = \|_ldq_full_T; // @[lsu.scala:369:{33,47}] assign io_core_ldq_full_0_0 = ldq_full; // @[lsu.scala:211:7, :369:47] wire [15:0] _stq_full_T = stq_tail_oh & stq_valids; // @[lsu.scala:361:39, :362:38, :373:33] assign stq_full = \|_stq_full_T; // @[lsu.scala:373:{33,47}] assign io_core_stq_full_0_0 = stq_full; // @[lsu.scala:211:7, :373:47] wire _dis_ld_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_ldq_0; // @[lsu.scala:211:7, :377:48] wire _dis_ld_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:211:7, :377:88] wire dis_ld_val = _dis_ld_val_T & _dis_ld_val_T_1; // @[lsu.scala:377:{48,85,88}] wire _dis_st_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_stq_0; // @[lsu.scala:211:7, :378:48] wire _dis_st_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:211:7, :377:88, :378:88] wire dis_st_val = _dis_st_val_T & _dis_st_val_T_1; // @[lsu.scala:378:{48,85,88}] wire _dis_uops_0_valid_T = dis_ld_val \| dis_st_val; // @[lsu.scala:377:85, :378:85, :380:37] wire [15:0] _GEN_25 = {{ldq_valid_15}, {ldq_valid_14}, {ldq_valid_13}, {ldq_valid_12}, {ldq_valid_11}, {ldq_valid_10}, {ldq_valid_9}, {ldq_valid_8}, {ldq_valid_7}, {ldq_valid_6}, {ldq_valid_5}, {ldq_valid_4}, {ldq_valid_3}, {ldq_valid_2}, {ldq_valid_1}, {ldq_valid_0}}; // @[lsu.scala:218:36, :387:15] wire [15:0] _GEN_26 = {{stq_valid_15}, {stq_valid_14}, {stq_valid_13}, {stq_valid_12}, {stq_valid_11}, {stq_valid_10}, {stq_valid_9}, {stq_valid_8}, {stq_valid_7}, {stq_valid_6}, {stq_valid_5}, {stq_valid_4}, {stq_valid_3}, {stq_valid_2}, {stq_valid_1}, {stq_valid_0}}; // @[lsu.scala:251:32, :392:15] wire _T_16 = dis_uops_0_valid & dis_uops_0_bits_uses_ldq; // @[lsu.scala:352:23, :394:29] wire [11:0] _GEN_27 = io_core_brupdate_b1_mispredict_mask_0 & dis_uops_0_bits_br_mask; // @[util.scala:126:51] wire [11:0] _ldq_valid_T; // @[util.scala:126:51] assign _ldq_valid_T = _GEN_27; // @[util.scala:126:51] wire [11:0] _stq_valid_T; // @[util.scala:126:51] assign _stq_valid_T = _GEN_27; // @[util.scala:126:51] wire _ldq_valid_T_1 = \|_ldq_valid_T; // @[util.scala:126:{51,59}] wire _ldq_valid_T_2 = _ldq_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _ldq_valid_T_3 = ~_ldq_valid_T_2; // @[util.scala:61:61] wire _GEN_28 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h0; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_29 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h1; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_30 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h2; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_31 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h3; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_32 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h4; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_33 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h5; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_34 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h6; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_35 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h7; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_36 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h8; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_37 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h9; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_38 = _T_16 & dis_uops_0_bits_ldq_idx == 4'hA; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_39 = _T_16 & dis_uops_0_bits_ldq_idx == 4'hB; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_40 = _T_16 & dis_uops_0_bits_ldq_idx == 4'hC; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_41 = _T_16 & dis_uops_0_bits_ldq_idx == 4'hD; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_42 = _T_16 & dis_uops_0_bits_ldq_idx == 4'hE; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_43 = _T_16 & (&dis_uops_0_bits_ldq_idx); // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire [11:0] _ldq_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] ldq_uop_out_br_mask; // @[util.scala:104:23] wire [11:0] _ldq_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _ldq_uop_out_br_mask_T_1 = dis_uops_0_bits_br_mask & _ldq_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign ldq_uop_out_br_mask = _ldq_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire _stq_valid_T_1 = \|_stq_valid_T; // @[util.scala:126:{51,59}] wire _stq_valid_T_2 = _stq_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _stq_valid_T_3 = ~_stq_valid_T_2; // @[util.scala:61:61] wire [11:0] _stq_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] stq_uop_out_br_mask; // @[util.scala:104:23] wire [11:0] _stq_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _stq_uop_out_br_mask_T_1 = dis_uops_0_bits_br_mask & _stq_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign stq_uop_out_br_mask = _stq_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire [3:0] _T_18 = ldq_tail + 4'h1; // @[util.scala:211:14] assign io_core_dis_ldq_idx_1_0 = dis_ld_val ? _T_18 : ldq_tail; // @[util.scala:211:14] wire [3:0] _T_25 = stq_tail + 4'h1; // @[util.scala:211:14] assign io_core_dis_stq_idx_1_0 = dis_st_val ? _T_25 : stq_tail; // @[util.scala:211:14] wire [14:0] _out_T = ldq_tail_oh[14:0]; // @[util.scala:256:25] wire _out_T_1 = ldq_tail_oh[15]; // @[util.scala:256:40] wire [15:0] out = {_out_T, _out_T_1}; // @[util.scala:256:{18,25,40}] wire [15:0] _T_38 = io_core_dis_uops_0_bits_uses_ldq_0 & ~io_core_dis_uops_0_bits_exception_0 ? out : ldq_tail_oh; // @[util.scala:256:18] wire [14:0] _out_T_2 = stq_tail_oh[14:0]; // @[util.scala:256:25] wire _out_T_3 = stq_tail_oh[15]; // @[util.scala:256:40] wire [15:0] out_1 = {_out_T_2, _out_T_3}; // @[util.scala:256:{18,25,40}] wire [15:0] _T_43 = io_core_dis_uops_0_bits_uses_stq_0 & ~io_core_dis_uops_0_bits_exception_0 ? out_1 : stq_tail_oh; // @[util.scala:256:18] wire [15:0] _ldq_full_T_1 = _T_38 & ldq_valids; // @[lsu.scala:360:38, :369:33, :428:22] assign ldq_full_1 = \|_ldq_full_T_1; // @[lsu.scala:369:{33,47}] assign io_core_ldq_full_1_0 = ldq_full_1; // @[lsu.scala:211:7, :369:47] wire [15:0] _stq_full_T_1 = _T_43 & stq_valids; // @[lsu.scala:362:38, :373:33, :430:22] assign stq_full_1 = \|_stq_full_T_1; // @[lsu.scala:373:{33,47}] assign io_core_stq_full_1_0 = stq_full_1; // @[lsu.scala:211:7, :373:47] wire _dis_ld_val_T_2 = io_core_dis_uops_1_valid_0 & io_core_dis_uops_1_bits_uses_ldq_0; // @[lsu.scala:211:7, :377:48] wire _dis_ld_val_T_3 = ~io_core_dis_uops_1_bits_exception_0; // @[lsu.scala:211:7, :377:88] wire dis_ld_val_1 = _dis_ld_val_T_2 & _dis_ld_val_T_3; // @[lsu.scala:377:{48,85,88}] wire _dis_st_val_T_2 = io_core_dis_uops_1_valid_0 & io_core_dis_uops_1_bits_uses_stq_0; // @[lsu.scala:211:7, :378:48] wire _dis_st_val_T_3 = ~io_core_dis_uops_1_bits_exception_0; // @[lsu.scala:211:7, :377:88, :378:88] wire dis_st_val_1 = _dis_st_val_T_2 & _dis_st_val_T_3; // @[lsu.scala:378:{48,85,88}] wire _dis_uops_1_valid_T = dis_ld_val_1 \| dis_st_val_1; // @[lsu.scala:377:85, :378:85, :380:37] wire _T_60 = dis_uops_1_valid & dis_uops_1_bits_uses_ldq; // @[lsu.scala:352:23, :394:29] wire [11:0] _GEN_44 = io_core_brupdate_b1_mispredict_mask_0 & dis_uops_1_bits_br_mask; // @[util.scala:126:51] wire [11:0] _ldq_valid_T_4; // @[util.scala:126:51] assign _ldq_valid_T_4 = _GEN_44; // @[util.scala:126:51] wire [11:0] _stq_valid_T_4; // @[util.scala:126:51] assign _stq_valid_T_4 = _GEN_44; // @[util.scala:126:51] wire _ldq_valid_T_5 = \|_ldq_valid_T_4; // @[util.scala:126:{51,59}] wire _ldq_valid_T_6 = _ldq_valid_T_5 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _ldq_valid_T_7 = ~_ldq_valid_T_6; // @[util.scala:61:61] wire _GEN_45 = dis_uops_1_bits_ldq_idx == 4'h0; // @[lsu.scala:352:23, :396:42] wire _GEN_46 = dis_uops_1_bits_ldq_idx == 4'h1; // @[lsu.scala:352:23, :396:42] wire _GEN_47 = dis_uops_1_bits_ldq_idx == 4'h2; // @[lsu.scala:352:23, :396:42] wire _GEN_48 = dis_uops_1_bits_ldq_idx == 4'h3; // @[lsu.scala:352:23, :396:42] wire _GEN_49 = dis_uops_1_bits_ldq_idx == 4'h4; // @[lsu.scala:352:23, :396:42] wire _GEN_50 = dis_uops_1_bits_ldq_idx == 4'h5; // @[lsu.scala:352:23, :396:42] wire _GEN_51 = dis_uops_1_bits_ldq_idx == 4'h6; // @[lsu.scala:352:23, :396:42] wire _GEN_52 = dis_uops_1_bits_ldq_idx == 4'h7; // @[lsu.scala:352:23, :396:42] wire _GEN_53 = dis_uops_1_bits_ldq_idx == 4'h8; // @[lsu.scala:352:23, :396:42] wire _GEN_54 = dis_uops_1_bits_ldq_idx == 4'h9; // @[lsu.scala:352:23, :396:42] wire _GEN_55 = dis_uops_1_bits_ldq_idx == 4'hA; // @[lsu.scala:352:23, :396:42] wire _GEN_56 = dis_uops_1_bits_ldq_idx == 4'hB; // @[lsu.scala:352:23, :396:42] wire _GEN_57 = dis_uops_1_bits_ldq_idx == 4'hC; // @[lsu.scala:352:23, :396:42] wire _GEN_58 = dis_uops_1_bits_ldq_idx == 4'hD; // @[lsu.scala:352:23, :396:42] wire _GEN_59 = dis_uops_1_bits_ldq_idx == 4'hE; // @[lsu.scala:352:23, :396:42] wire [11:0] _ldq_uop_out_br_mask_T_3; // @[util.scala:93:25] wire [11:0] ldq_uop_out_1_br_mask; // @[util.scala:104:23] wire [11:0] _ldq_uop_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _ldq_uop_out_br_mask_T_3 = dis_uops_1_bits_br_mask & _ldq_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign ldq_uop_out_1_br_mask = _ldq_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire _GEN_60 = _GEN_45 \| _GEN_28; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_61 = _GEN_46 \| _GEN_29; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_62 = _GEN_47 \| _GEN_30; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_63 = _GEN_48 \| _GEN_31; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_64 = _GEN_49 \| _GEN_32; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_65 = _GEN_50 \| _GEN_33; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_66 = _GEN_51 \| _GEN_34; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_67 = _GEN_52 \| _GEN_35; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_68 = _GEN_53 \| _GEN_36; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_69 = _GEN_54 \| _GEN_37; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_70 = _GEN_55 \| _GEN_38; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_71 = _GEN_56 \| _GEN_39; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_72 = _GEN_57 \| _GEN_40; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_73 = _GEN_58 \| _GEN_41; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_74 = _GEN_59 \| _GEN_42; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_75 = (&dis_uops_1_bits_ldq_idx) \| _GEN_43; // @[lsu.scala:218:36, :220:36, :352:23, :394:59, :396:42, :399:42] wire _stq_valid_T_5 = \|_stq_valid_T_4; // @[util.scala:126:{51,59}] wire _stq_valid_T_6 = _stq_valid_T_5 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _stq_valid_T_7 = ~_stq_valid_T_6; // @[util.scala:61:61] wire [11:0] _stq_uop_out_br_mask_T_3; // @[util.scala:93:25] wire [11:0] stq_uop_out_1_br_mask; // @[util.scala:104:23] wire [11:0] _stq_uop_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _stq_uop_out_br_mask_T_3 = dis_uops_1_bits_br_mask & _stq_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign stq_uop_out_1_br_mask = _stq_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire [14:0] _out_T_4 = _T_38[14:0]; // @[util.scala:256:25] wire _out_T_5 = _T_38[15]; // @[util.scala:256:40] wire [15:0] out_2 = {_out_T_4, _out_T_5}; // @[util.scala:256:{18,25,40}] wire [14:0] _out_T_6 = _T_43[14:0]; // @[util.scala:256:25] wire _out_T_7 = _T_43[15]; // @[util.scala:256:40] wire [15:0] out_3 = {_out_T_6, _out_T_7}; // @[util.scala:256:{18,25,40}] wire stq_enq_e_e_valid = _GEN_26[stq_execute_head]; // @[lsu.scala:262:17, :283:29, :392:15, :438:42] wire _io_core_fencei_rdy_T = ~stq_nonempty; // @[lsu.scala:364:40, :446:28] assign _io_core_fencei_rdy_T_1 = _io_core_fencei_rdy_T & io_dmem_ordered_0; // @[lsu.scala:211:7, :446:{28,42}] assign io_core_fencei_rdy_0 = _io_core_fencei_rdy_T_1; // @[lsu.scala:211:7, :446:42] wire mem_xcpt_valid; // @[lsu.scala:457:29] wire [3:0] mem_xcpt_cause; // @[lsu.scala:458:29] wire mem_xcpt_uop_iq_type_0; // @[lsu.scala:459:29] wire mem_xcpt_uop_iq_type_1; // @[lsu.scala:459:29] wire mem_xcpt_uop_iq_type_2; // @[lsu.scala:459:29] wire mem_xcpt_uop_iq_type_3; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_0; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_1; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_2; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_3; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_4; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_5; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_6; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_7; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_8; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_9; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_div; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:459:29] wire [31:0] mem_xcpt_uop_inst; // @[lsu.scala:459:29] wire [31:0] mem_xcpt_uop_debug_inst; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_rvc; // @[lsu.scala:459:29] wire [39:0] mem_xcpt_uop_debug_pc; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_issued; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_dis_col_sel; // @[lsu.scala:459:29] wire [11:0] mem_xcpt_uop_br_mask; // @[lsu.scala:459:29] wire [3:0] mem_xcpt_uop_br_tag; // @[lsu.scala:459:29] wire [3:0] mem_xcpt_uop_br_type; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_sfb; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_fence; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_fencei; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_sfence; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_amo; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_eret; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_rocc; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_mov; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_ftq_idx; // @[lsu.scala:459:29] wire mem_xcpt_uop_edge_inst; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_pc_lob; // @[lsu.scala:459:29] wire mem_xcpt_uop_taken; // @[lsu.scala:459:29] wire mem_xcpt_uop_imm_rename; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_imm_sel; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_pimm; // @[lsu.scala:459:29] wire [19:0] mem_xcpt_uop_imm_packed; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_op1_sel; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_op2_sel; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_rob_idx; // @[lsu.scala:459:29] wire [3:0] mem_xcpt_uop_ldq_idx; // @[lsu.scala:459:29] wire [3:0] mem_xcpt_uop_stq_idx; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_rxq_idx; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_pdst; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_prs1; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_prs2; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_prs3; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_ppred; // @[lsu.scala:459:29] wire mem_xcpt_uop_prs1_busy; // @[lsu.scala:459:29] wire mem_xcpt_uop_prs2_busy; // @[lsu.scala:459:29] wire mem_xcpt_uop_prs3_busy; // @[lsu.scala:459:29] wire mem_xcpt_uop_ppred_busy; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_stale_pdst; // @[lsu.scala:459:29] wire mem_xcpt_uop_exception; // @[lsu.scala:459:29] wire [63:0] mem_xcpt_uop_exc_cause; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_mem_cmd; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_mem_size; // @[lsu.scala:459:29] wire mem_xcpt_uop_mem_signed; // @[lsu.scala:459:29] wire mem_xcpt_uop_uses_ldq; // @[lsu.scala:459:29] wire mem_xcpt_uop_uses_stq; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_unique; // @[lsu.scala:459:29] wire mem_xcpt_uop_flush_on_commit; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_csr_cmd; // @[lsu.scala:459:29] wire mem_xcpt_uop_ldst_is_rs1; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_ldst; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_lrs1; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_lrs2; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_lrs3; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_dst_rtype; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_lrs1_rtype; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_lrs2_rtype; // @[lsu.scala:459:29] wire mem_xcpt_uop_frs3_en; // @[lsu.scala:459:29] wire mem_xcpt_uop_fcn_dw; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_fcn_op; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_val; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_fp_rm; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_fp_typ; // @[lsu.scala:459:29] wire mem_xcpt_uop_xcpt_pf_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_xcpt_ae_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_xcpt_ma_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_bp_debug_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_bp_xcpt_if; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_debug_fsrc; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_debug_tsrc; // @[lsu.scala:459:29] wire [63:0] mem_xcpt_vaddr; // @[lsu.scala:460:29] wire will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_agen_exec_0; // @[lsu.scala:469:39] wire will_fire_load_agen_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_agen_0; // @[lsu.scala:470:41] wire will_fire_store_agen_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_agen_0; // @[lsu.scala:471:41] wire will_fire_sfence_0_will_fire; // @[lsu.scala:657:65] wire will_fire_sfence_0; // @[lsu.scala:472:41] wire will_fire_hella_incoming_0_will_fire; // @[lsu.scala:657:65] wire will_fire_hella_incoming_0; // @[lsu.scala:473:41] wire _exe_passthr_T = will_fire_hella_incoming_0; // @[lsu.scala:473:41, :756:23] wire will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:657:65] wire will_fire_hella_wakeup_0; // @[lsu.scala:474:41] wire will_fire_release_0_will_fire; // @[lsu.scala:657:65] assign io_dmem_release_ready_0 = will_fire_release_0; // @[lsu.scala:211:7, :475:41] wire will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_retry_0; // @[lsu.scala:476:41] wire will_fire_store_retry_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_retry_0; // @[lsu.scala:477:41] wire will_fire_store_commit_fast_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_commit_fast_0; // @[lsu.scala:478:41] wire will_fire_store_commit_slow_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_commit_slow_0; // @[lsu.scala:479:41] wire will_fire_load_wakeup_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_wakeup_0; // @[lsu.scala:480:41] wire block_load_mask_0; // @[lsu.scala:488:36] wire block_load_mask_1; // @[lsu.scala:488:36] wire block_load_mask_2; // @[lsu.scala:488:36] wire block_load_mask_3; // @[lsu.scala:488:36] wire block_load_mask_4; // @[lsu.scala:488:36] wire block_load_mask_5; // @[lsu.scala:488:36] wire block_load_mask_6; // @[lsu.scala:488:36] wire block_load_mask_7; // @[lsu.scala:488:36] wire block_load_mask_8; // @[lsu.scala:488:36] wire block_load_mask_9; // @[lsu.scala:488:36] wire block_load_mask_10; // @[lsu.scala:488:36] wire block_load_mask_11; // @[lsu.scala:488:36] wire block_load_mask_12; // @[lsu.scala:488:36] wire block_load_mask_13; // @[lsu.scala:488:36] wire block_load_mask_14; // @[lsu.scala:488:36] wire block_load_mask_15; // @[lsu.scala:488:36] reg p1_block_load_mask_0; // @[lsu.scala:489:35] reg p1_block_load_mask_1; // @[lsu.scala:489:35] reg p1_block_load_mask_2; // @[lsu.scala:489:35] reg p1_block_load_mask_3; // @[lsu.scala:489:35] reg p1_block_load_mask_4; // @[lsu.scala:489:35] reg p1_block_load_mask_5; // @[lsu.scala:489:35] reg p1_block_load_mask_6; // @[lsu.scala:489:35] reg p1_block_load_mask_7; // @[lsu.scala:489:35] reg p1_block_load_mask_8; // @[lsu.scala:489:35] reg p1_block_load_mask_9; // @[lsu.scala:489:35] reg p1_block_load_mask_10; // @[lsu.scala:489:35] reg p1_block_load_mask_11; // @[lsu.scala:489:35] reg p1_block_load_mask_12; // @[lsu.scala:489:35] reg p1_block_load_mask_13; // @[lsu.scala:489:35] reg p1_block_load_mask_14; // @[lsu.scala:489:35] reg p1_block_load_mask_15; // @[lsu.scala:489:35] reg p2_block_load_mask_0; // @[lsu.scala:490:35] reg p2_block_load_mask_1; // @[lsu.scala:490:35] reg p2_block_load_mask_2; // @[lsu.scala:490:35] reg p2_block_load_mask_3; // @[lsu.scala:490:35] reg p2_block_load_mask_4; // @[lsu.scala:490:35] reg p2_block_load_mask_5; // @[lsu.scala:490:35] reg p2_block_load_mask_6; // @[lsu.scala:490:35] reg p2_block_load_mask_7; // @[lsu.scala:490:35] reg p2_block_load_mask_8; // @[lsu.scala:490:35] reg p2_block_load_mask_9; // @[lsu.scala:490:35] reg p2_block_load_mask_10; // @[lsu.scala:490:35] reg p2_block_load_mask_11; // @[lsu.scala:490:35] reg p2_block_load_mask_12; // @[lsu.scala:490:35] reg p2_block_load_mask_13; // @[lsu.scala:490:35] reg p2_block_load_mask_14; // @[lsu.scala:490:35] reg p2_block_load_mask_15; // @[lsu.scala:490:35] wire [4:0] _stq_tail_plus_T = {1'h0, stq_tail} + 5'h4; // @[util.scala:172:14, :211:14] wire [3:0] _stq_tail_plus_T_1 = _stq_tail_plus_T[3:0]; // @[util.scala:172:14] wire [3:0] stq_tail_plus = _stq_tail_plus_T_1; // @[util.scala:172:{14,20}] wire _stq_almost_full_T = stq_head < stq_tail_plus; // @[util.scala:172:20, :364:52] wire _stq_almost_full_T_1 = stq_head < stq_tail; // @[util.scala:364:64] wire _stq_almost_full_T_2 = _stq_almost_full_T ^ _stq_almost_full_T_1; // @[util.scala:364:{52,58,64}] wire _stq_almost_full_T_3 = stq_tail_plus < stq_tail; // @[util.scala:172:20, :364:78] wire _stq_almost_full_T_4 = _stq_almost_full_T_2 ^ _stq_almost_full_T_3; // @[util.scala:364:{58,72,78}] reg stq_almost_full; // @[lsu.scala:494:32] wire store_needs_order; // @[lsu.scala:498:35] wire _ldq_incoming_e_WIRE_valid = ldq_incoming_e_e_valid; // @[lsu.scala:233:17, :501:48] wire [31:0] _ldq_incoming_e_WIRE_bits_uop_inst = ldq_incoming_e_e_bits_uop_inst; // @[lsu.scala:233:17, :501:48] wire [31:0] _ldq_incoming_e_WIRE_bits_uop_debug_inst = ldq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_rvc = ldq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17, :501:48] wire [39:0] _ldq_incoming_e_WIRE_bits_uop_debug_pc = ldq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_0 = ldq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_1 = ldq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_2 = ldq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_3 = ldq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_0 = ldq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_1 = ldq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_2 = ldq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_3 = ldq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_4 = ldq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_5 = ldq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_6 = ldq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_7 = ldq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_8 = ldq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_9 = ldq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_issued = ldq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen = ldq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen = ldq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child = ldq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child = ldq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint = ldq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint = ldq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint = ldq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_dis_col_sel = ldq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17, :501:48] wire [11:0] _ldq_incoming_e_WIRE_bits_uop_br_mask = ldq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_uop_br_tag = ldq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_uop_br_type = ldq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_sfb = ldq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_fence = ldq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_fencei = ldq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_sfence = ldq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_amo = ldq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_eret = ldq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_sys_pc2epc = ldq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_rocc = ldq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_mov = ldq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_ftq_idx = ldq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_edge_inst = ldq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_pc_lob = ldq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_taken = ldq_incoming_e_e_bits_uop_taken; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_imm_rename = ldq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_imm_sel = ldq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_pimm = ldq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:233:17, :501:48] wire [19:0] _ldq_incoming_e_WIRE_bits_uop_imm_packed = ldq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_op1_sel = ldq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_op2_sel = ldq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst = ldq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wen = ldq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1 = ldq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2 = ldq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3 = ldq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12 = ldq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23 = ldq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn = ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut = ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint = ldq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_toint = ldq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe = ldq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fma = ldq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_div = ldq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt = ldq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags = ldq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_vec = ldq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_rob_idx = ldq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_uop_ldq_idx = ldq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_uop_stq_idx = ldq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_rxq_idx = ldq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_pdst = ldq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_prs1 = ldq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_prs2 = ldq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_prs3 = ldq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_ppred = ldq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_prs1_busy = ldq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_prs2_busy = ldq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_prs3_busy = ldq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_ppred_busy = ldq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_stale_pdst = ldq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_exception = ldq_incoming_e_e_bits_uop_exception; // @[lsu.scala:233:17, :501:48] wire [63:0] _ldq_incoming_e_WIRE_bits_uop_exc_cause = ldq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_mem_cmd = ldq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_mem_size = ldq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_mem_signed = ldq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_uses_ldq = ldq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_uses_stq = ldq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_unique = ldq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_flush_on_commit = ldq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_csr_cmd = ldq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_ldst_is_rs1 = ldq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_ldst = ldq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_lrs1 = ldq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_lrs2 = ldq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_lrs3 = ldq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_dst_rtype = ldq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_lrs1_rtype = ldq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_lrs2_rtype = ldq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_frs3_en = ldq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fcn_dw = ldq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_fcn_op = ldq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_val = ldq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_fp_rm = ldq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_fp_typ = ldq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_xcpt_pf_if = ldq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_xcpt_ae_if = ldq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_xcpt_ma_if = ldq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_bp_debug_if = ldq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_bp_xcpt_if = ldq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_debug_fsrc = ldq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_debug_tsrc = ldq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_addr_valid = ldq_incoming_e_e_bits_addr_valid; // @[lsu.scala:233:17, :501:48] wire [39:0] _ldq_incoming_e_WIRE_bits_addr_bits = ldq_incoming_e_e_bits_addr_bits; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_addr_is_virtual = ldq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_addr_is_uncacheable = ldq_incoming_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_executed = ldq_incoming_e_e_bits_executed; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_succeeded = ldq_incoming_e_e_bits_succeeded; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_order_fail = ldq_incoming_e_e_bits_order_fail; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_observed = ldq_incoming_e_e_bits_observed; // @[lsu.scala:233:17, :501:48] wire [15:0] _ldq_incoming_e_WIRE_bits_st_dep_mask = ldq_incoming_e_e_bits_st_dep_mask; // @[lsu.scala:233:17, :501:48] wire [7:0] _ldq_incoming_e_WIRE_bits_ld_byte_mask = ldq_incoming_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_forward_std_val = ldq_incoming_e_e_bits_forward_std_val; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_forward_stq_idx = ldq_incoming_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17, :501:48] wire [63:0] _ldq_incoming_e_WIRE_bits_debug_wb_data = ldq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:233:17, :501:48] assign ldq_incoming_e_e_valid = _GEN_25[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :234:32, :321:49, :387:15] wire [15:0][31:0] _GEN_76 = {{ldq_uop_15_inst}, {ldq_uop_14_inst}, {ldq_uop_13_inst}, {ldq_uop_12_inst}, {ldq_uop_11_inst}, {ldq_uop_10_inst}, {ldq_uop_9_inst}, {ldq_uop_8_inst}, {ldq_uop_7_inst}, {ldq_uop_6_inst}, {ldq_uop_5_inst}, {ldq_uop_4_inst}, {ldq_uop_3_inst}, {ldq_uop_2_inst}, {ldq_uop_1_inst}, {ldq_uop_0_inst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_inst = _GEN_76[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][31:0] _GEN_77 = {{ldq_uop_15_debug_inst}, {ldq_uop_14_debug_inst}, {ldq_uop_13_debug_inst}, {ldq_uop_12_debug_inst}, {ldq_uop_11_debug_inst}, {ldq_uop_10_debug_inst}, {ldq_uop_9_debug_inst}, {ldq_uop_8_debug_inst}, {ldq_uop_7_debug_inst}, {ldq_uop_6_debug_inst}, {ldq_uop_5_debug_inst}, {ldq_uop_4_debug_inst}, {ldq_uop_3_debug_inst}, {ldq_uop_2_debug_inst}, {ldq_uop_1_debug_inst}, {ldq_uop_0_debug_inst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_inst = _GEN_77[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_78 = {{ldq_uop_15_is_rvc}, {ldq_uop_14_is_rvc}, {ldq_uop_13_is_rvc}, {ldq_uop_12_is_rvc}, {ldq_uop_11_is_rvc}, {ldq_uop_10_is_rvc}, {ldq_uop_9_is_rvc}, {ldq_uop_8_is_rvc}, {ldq_uop_7_is_rvc}, {ldq_uop_6_is_rvc}, {ldq_uop_5_is_rvc}, {ldq_uop_4_is_rvc}, {ldq_uop_3_is_rvc}, {ldq_uop_2_is_rvc}, {ldq_uop_1_is_rvc}, {ldq_uop_0_is_rvc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_rvc = _GEN_78[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][39:0] _GEN_79 = {{ldq_uop_15_debug_pc}, {ldq_uop_14_debug_pc}, {ldq_uop_13_debug_pc}, {ldq_uop_12_debug_pc}, {ldq_uop_11_debug_pc}, {ldq_uop_10_debug_pc}, {ldq_uop_9_debug_pc}, {ldq_uop_8_debug_pc}, {ldq_uop_7_debug_pc}, {ldq_uop_6_debug_pc}, {ldq_uop_5_debug_pc}, {ldq_uop_4_debug_pc}, {ldq_uop_3_debug_pc}, {ldq_uop_2_debug_pc}, {ldq_uop_1_debug_pc}, {ldq_uop_0_debug_pc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_pc = _GEN_79[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_80 = {{ldq_uop_15_iq_type_0}, {ldq_uop_14_iq_type_0}, {ldq_uop_13_iq_type_0}, {ldq_uop_12_iq_type_0}, {ldq_uop_11_iq_type_0}, {ldq_uop_10_iq_type_0}, {ldq_uop_9_iq_type_0}, {ldq_uop_8_iq_type_0}, {ldq_uop_7_iq_type_0}, {ldq_uop_6_iq_type_0}, {ldq_uop_5_iq_type_0}, {ldq_uop_4_iq_type_0}, {ldq_uop_3_iq_type_0}, {ldq_uop_2_iq_type_0}, {ldq_uop_1_iq_type_0}, {ldq_uop_0_iq_type_0}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_0 = _GEN_80[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_81 = {{ldq_uop_15_iq_type_1}, {ldq_uop_14_iq_type_1}, {ldq_uop_13_iq_type_1}, {ldq_uop_12_iq_type_1}, {ldq_uop_11_iq_type_1}, {ldq_uop_10_iq_type_1}, {ldq_uop_9_iq_type_1}, {ldq_uop_8_iq_type_1}, {ldq_uop_7_iq_type_1}, {ldq_uop_6_iq_type_1}, {ldq_uop_5_iq_type_1}, {ldq_uop_4_iq_type_1}, {ldq_uop_3_iq_type_1}, {ldq_uop_2_iq_type_1}, {ldq_uop_1_iq_type_1}, {ldq_uop_0_iq_type_1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_1 = _GEN_81[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_82 = {{ldq_uop_15_iq_type_2}, {ldq_uop_14_iq_type_2}, {ldq_uop_13_iq_type_2}, {ldq_uop_12_iq_type_2}, {ldq_uop_11_iq_type_2}, {ldq_uop_10_iq_type_2}, {ldq_uop_9_iq_type_2}, {ldq_uop_8_iq_type_2}, {ldq_uop_7_iq_type_2}, {ldq_uop_6_iq_type_2}, {ldq_uop_5_iq_type_2}, {ldq_uop_4_iq_type_2}, {ldq_uop_3_iq_type_2}, {ldq_uop_2_iq_type_2}, {ldq_uop_1_iq_type_2}, {ldq_uop_0_iq_type_2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_2 = _GEN_82[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_83 = {{ldq_uop_15_iq_type_3}, {ldq_uop_14_iq_type_3}, {ldq_uop_13_iq_type_3}, {ldq_uop_12_iq_type_3}, {ldq_uop_11_iq_type_3}, {ldq_uop_10_iq_type_3}, {ldq_uop_9_iq_type_3}, {ldq_uop_8_iq_type_3}, {ldq_uop_7_iq_type_3}, {ldq_uop_6_iq_type_3}, {ldq_uop_5_iq_type_3}, {ldq_uop_4_iq_type_3}, {ldq_uop_3_iq_type_3}, {ldq_uop_2_iq_type_3}, {ldq_uop_1_iq_type_3}, {ldq_uop_0_iq_type_3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_3 = _GEN_83[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_84 = {{ldq_uop_15_fu_code_0}, {ldq_uop_14_fu_code_0}, {ldq_uop_13_fu_code_0}, {ldq_uop_12_fu_code_0}, {ldq_uop_11_fu_code_0}, {ldq_uop_10_fu_code_0}, {ldq_uop_9_fu_code_0}, {ldq_uop_8_fu_code_0}, {ldq_uop_7_fu_code_0}, {ldq_uop_6_fu_code_0}, {ldq_uop_5_fu_code_0}, {ldq_uop_4_fu_code_0}, {ldq_uop_3_fu_code_0}, {ldq_uop_2_fu_code_0}, {ldq_uop_1_fu_code_0}, {ldq_uop_0_fu_code_0}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_0 = _GEN_84[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_85 = {{ldq_uop_15_fu_code_1}, {ldq_uop_14_fu_code_1}, {ldq_uop_13_fu_code_1}, {ldq_uop_12_fu_code_1}, {ldq_uop_11_fu_code_1}, {ldq_uop_10_fu_code_1}, {ldq_uop_9_fu_code_1}, {ldq_uop_8_fu_code_1}, {ldq_uop_7_fu_code_1}, {ldq_uop_6_fu_code_1}, {ldq_uop_5_fu_code_1}, {ldq_uop_4_fu_code_1}, {ldq_uop_3_fu_code_1}, {ldq_uop_2_fu_code_1}, {ldq_uop_1_fu_code_1}, {ldq_uop_0_fu_code_1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_1 = _GEN_85[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_86 = {{ldq_uop_15_fu_code_2}, {ldq_uop_14_fu_code_2}, {ldq_uop_13_fu_code_2}, {ldq_uop_12_fu_code_2}, {ldq_uop_11_fu_code_2}, {ldq_uop_10_fu_code_2}, {ldq_uop_9_fu_code_2}, {ldq_uop_8_fu_code_2}, {ldq_uop_7_fu_code_2}, {ldq_uop_6_fu_code_2}, {ldq_uop_5_fu_code_2}, {ldq_uop_4_fu_code_2}, {ldq_uop_3_fu_code_2}, {ldq_uop_2_fu_code_2}, {ldq_uop_1_fu_code_2}, {ldq_uop_0_fu_code_2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_2 = _GEN_86[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_87 = {{ldq_uop_15_fu_code_3}, {ldq_uop_14_fu_code_3}, {ldq_uop_13_fu_code_3}, {ldq_uop_12_fu_code_3}, {ldq_uop_11_fu_code_3}, {ldq_uop_10_fu_code_3}, {ldq_uop_9_fu_code_3}, {ldq_uop_8_fu_code_3}, {ldq_uop_7_fu_code_3}, {ldq_uop_6_fu_code_3}, {ldq_uop_5_fu_code_3}, {ldq_uop_4_fu_code_3}, {ldq_uop_3_fu_code_3}, {ldq_uop_2_fu_code_3}, {ldq_uop_1_fu_code_3}, {ldq_uop_0_fu_code_3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_3 = _GEN_87[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_88 = {{ldq_uop_15_fu_code_4}, {ldq_uop_14_fu_code_4}, {ldq_uop_13_fu_code_4}, {ldq_uop_12_fu_code_4}, {ldq_uop_11_fu_code_4}, {ldq_uop_10_fu_code_4}, {ldq_uop_9_fu_code_4}, {ldq_uop_8_fu_code_4}, {ldq_uop_7_fu_code_4}, {ldq_uop_6_fu_code_4}, {ldq_uop_5_fu_code_4}, {ldq_uop_4_fu_code_4}, {ldq_uop_3_fu_code_4}, {ldq_uop_2_fu_code_4}, {ldq_uop_1_fu_code_4}, {ldq_uop_0_fu_code_4}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_4 = _GEN_88[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_89 = {{ldq_uop_15_fu_code_5}, {ldq_uop_14_fu_code_5}, {ldq_uop_13_fu_code_5}, {ldq_uop_12_fu_code_5}, {ldq_uop_11_fu_code_5}, {ldq_uop_10_fu_code_5}, {ldq_uop_9_fu_code_5}, {ldq_uop_8_fu_code_5}, {ldq_uop_7_fu_code_5}, {ldq_uop_6_fu_code_5}, {ldq_uop_5_fu_code_5}, {ldq_uop_4_fu_code_5}, {ldq_uop_3_fu_code_5}, {ldq_uop_2_fu_code_5}, {ldq_uop_1_fu_code_5}, {ldq_uop_0_fu_code_5}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_5 = _GEN_89[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_90 = {{ldq_uop_15_fu_code_6}, {ldq_uop_14_fu_code_6}, {ldq_uop_13_fu_code_6}, {ldq_uop_12_fu_code_6}, {ldq_uop_11_fu_code_6}, {ldq_uop_10_fu_code_6}, {ldq_uop_9_fu_code_6}, {ldq_uop_8_fu_code_6}, {ldq_uop_7_fu_code_6}, {ldq_uop_6_fu_code_6}, {ldq_uop_5_fu_code_6}, {ldq_uop_4_fu_code_6}, {ldq_uop_3_fu_code_6}, {ldq_uop_2_fu_code_6}, {ldq_uop_1_fu_code_6}, {ldq_uop_0_fu_code_6}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_6 = _GEN_90[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_91 = {{ldq_uop_15_fu_code_7}, {ldq_uop_14_fu_code_7}, {ldq_uop_13_fu_code_7}, {ldq_uop_12_fu_code_7}, {ldq_uop_11_fu_code_7}, {ldq_uop_10_fu_code_7}, {ldq_uop_9_fu_code_7}, {ldq_uop_8_fu_code_7}, {ldq_uop_7_fu_code_7}, {ldq_uop_6_fu_code_7}, {ldq_uop_5_fu_code_7}, {ldq_uop_4_fu_code_7}, {ldq_uop_3_fu_code_7}, {ldq_uop_2_fu_code_7}, {ldq_uop_1_fu_code_7}, {ldq_uop_0_fu_code_7}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_7 = _GEN_91[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_92 = {{ldq_uop_15_fu_code_8}, {ldq_uop_14_fu_code_8}, {ldq_uop_13_fu_code_8}, {ldq_uop_12_fu_code_8}, {ldq_uop_11_fu_code_8}, {ldq_uop_10_fu_code_8}, {ldq_uop_9_fu_code_8}, {ldq_uop_8_fu_code_8}, {ldq_uop_7_fu_code_8}, {ldq_uop_6_fu_code_8}, {ldq_uop_5_fu_code_8}, {ldq_uop_4_fu_code_8}, {ldq_uop_3_fu_code_8}, {ldq_uop_2_fu_code_8}, {ldq_uop_1_fu_code_8}, {ldq_uop_0_fu_code_8}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_8 = _GEN_92[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_93 = {{ldq_uop_15_fu_code_9}, {ldq_uop_14_fu_code_9}, {ldq_uop_13_fu_code_9}, {ldq_uop_12_fu_code_9}, {ldq_uop_11_fu_code_9}, {ldq_uop_10_fu_code_9}, {ldq_uop_9_fu_code_9}, {ldq_uop_8_fu_code_9}, {ldq_uop_7_fu_code_9}, {ldq_uop_6_fu_code_9}, {ldq_uop_5_fu_code_9}, {ldq_uop_4_fu_code_9}, {ldq_uop_3_fu_code_9}, {ldq_uop_2_fu_code_9}, {ldq_uop_1_fu_code_9}, {ldq_uop_0_fu_code_9}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_9 = _GEN_93[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_94 = {{ldq_uop_15_iw_issued}, {ldq_uop_14_iw_issued}, {ldq_uop_13_iw_issued}, {ldq_uop_12_iw_issued}, {ldq_uop_11_iw_issued}, {ldq_uop_10_iw_issued}, {ldq_uop_9_iw_issued}, {ldq_uop_8_iw_issued}, {ldq_uop_7_iw_issued}, {ldq_uop_6_iw_issued}, {ldq_uop_5_iw_issued}, {ldq_uop_4_iw_issued}, {ldq_uop_3_iw_issued}, {ldq_uop_2_iw_issued}, {ldq_uop_1_iw_issued}, {ldq_uop_0_iw_issued}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_issued = _GEN_94[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_95 = {{ldq_uop_15_iw_issued_partial_agen}, {ldq_uop_14_iw_issued_partial_agen}, {ldq_uop_13_iw_issued_partial_agen}, {ldq_uop_12_iw_issued_partial_agen}, {ldq_uop_11_iw_issued_partial_agen}, {ldq_uop_10_iw_issued_partial_agen}, {ldq_uop_9_iw_issued_partial_agen}, {ldq_uop_8_iw_issued_partial_agen}, {ldq_uop_7_iw_issued_partial_agen}, {ldq_uop_6_iw_issued_partial_agen}, {ldq_uop_5_iw_issued_partial_agen}, {ldq_uop_4_iw_issued_partial_agen}, {ldq_uop_3_iw_issued_partial_agen}, {ldq_uop_2_iw_issued_partial_agen}, {ldq_uop_1_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_issued_partial_agen = _GEN_95[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_96 = {{ldq_uop_15_iw_issued_partial_dgen}, {ldq_uop_14_iw_issued_partial_dgen}, {ldq_uop_13_iw_issued_partial_dgen}, {ldq_uop_12_iw_issued_partial_dgen}, {ldq_uop_11_iw_issued_partial_dgen}, {ldq_uop_10_iw_issued_partial_dgen}, {ldq_uop_9_iw_issued_partial_dgen}, {ldq_uop_8_iw_issued_partial_dgen}, {ldq_uop_7_iw_issued_partial_dgen}, {ldq_uop_6_iw_issued_partial_dgen}, {ldq_uop_5_iw_issued_partial_dgen}, {ldq_uop_4_iw_issued_partial_dgen}, {ldq_uop_3_iw_issued_partial_dgen}, {ldq_uop_2_iw_issued_partial_dgen}, {ldq_uop_1_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_issued_partial_dgen = _GEN_96[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_97 = {{ldq_uop_15_iw_p1_speculative_child}, {ldq_uop_14_iw_p1_speculative_child}, {ldq_uop_13_iw_p1_speculative_child}, {ldq_uop_12_iw_p1_speculative_child}, {ldq_uop_11_iw_p1_speculative_child}, {ldq_uop_10_iw_p1_speculative_child}, {ldq_uop_9_iw_p1_speculative_child}, {ldq_uop_8_iw_p1_speculative_child}, {ldq_uop_7_iw_p1_speculative_child}, {ldq_uop_6_iw_p1_speculative_child}, {ldq_uop_5_iw_p1_speculative_child}, {ldq_uop_4_iw_p1_speculative_child}, {ldq_uop_3_iw_p1_speculative_child}, {ldq_uop_2_iw_p1_speculative_child}, {ldq_uop_1_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p1_speculative_child = _GEN_97[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_98 = {{ldq_uop_15_iw_p2_speculative_child}, {ldq_uop_14_iw_p2_speculative_child}, {ldq_uop_13_iw_p2_speculative_child}, {ldq_uop_12_iw_p2_speculative_child}, {ldq_uop_11_iw_p2_speculative_child}, {ldq_uop_10_iw_p2_speculative_child}, {ldq_uop_9_iw_p2_speculative_child}, {ldq_uop_8_iw_p2_speculative_child}, {ldq_uop_7_iw_p2_speculative_child}, {ldq_uop_6_iw_p2_speculative_child}, {ldq_uop_5_iw_p2_speculative_child}, {ldq_uop_4_iw_p2_speculative_child}, {ldq_uop_3_iw_p2_speculative_child}, {ldq_uop_2_iw_p2_speculative_child}, {ldq_uop_1_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p2_speculative_child = _GEN_98[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_99 = {{ldq_uop_15_iw_p1_bypass_hint}, {ldq_uop_14_iw_p1_bypass_hint}, {ldq_uop_13_iw_p1_bypass_hint}, {ldq_uop_12_iw_p1_bypass_hint}, {ldq_uop_11_iw_p1_bypass_hint}, {ldq_uop_10_iw_p1_bypass_hint}, {ldq_uop_9_iw_p1_bypass_hint}, {ldq_uop_8_iw_p1_bypass_hint}, {ldq_uop_7_iw_p1_bypass_hint}, {ldq_uop_6_iw_p1_bypass_hint}, {ldq_uop_5_iw_p1_bypass_hint}, {ldq_uop_4_iw_p1_bypass_hint}, {ldq_uop_3_iw_p1_bypass_hint}, {ldq_uop_2_iw_p1_bypass_hint}, {ldq_uop_1_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p1_bypass_hint = _GEN_99[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_100 = {{ldq_uop_15_iw_p2_bypass_hint}, {ldq_uop_14_iw_p2_bypass_hint}, {ldq_uop_13_iw_p2_bypass_hint}, {ldq_uop_12_iw_p2_bypass_hint}, {ldq_uop_11_iw_p2_bypass_hint}, {ldq_uop_10_iw_p2_bypass_hint}, {ldq_uop_9_iw_p2_bypass_hint}, {ldq_uop_8_iw_p2_bypass_hint}, {ldq_uop_7_iw_p2_bypass_hint}, {ldq_uop_6_iw_p2_bypass_hint}, {ldq_uop_5_iw_p2_bypass_hint}, {ldq_uop_4_iw_p2_bypass_hint}, {ldq_uop_3_iw_p2_bypass_hint}, {ldq_uop_2_iw_p2_bypass_hint}, {ldq_uop_1_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p2_bypass_hint = _GEN_100[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_101 = {{ldq_uop_15_iw_p3_bypass_hint}, {ldq_uop_14_iw_p3_bypass_hint}, {ldq_uop_13_iw_p3_bypass_hint}, {ldq_uop_12_iw_p3_bypass_hint}, {ldq_uop_11_iw_p3_bypass_hint}, {ldq_uop_10_iw_p3_bypass_hint}, {ldq_uop_9_iw_p3_bypass_hint}, {ldq_uop_8_iw_p3_bypass_hint}, {ldq_uop_7_iw_p3_bypass_hint}, {ldq_uop_6_iw_p3_bypass_hint}, {ldq_uop_5_iw_p3_bypass_hint}, {ldq_uop_4_iw_p3_bypass_hint}, {ldq_uop_3_iw_p3_bypass_hint}, {ldq_uop_2_iw_p3_bypass_hint}, {ldq_uop_1_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p3_bypass_hint = _GEN_101[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_102 = {{ldq_uop_15_dis_col_sel}, {ldq_uop_14_dis_col_sel}, {ldq_uop_13_dis_col_sel}, {ldq_uop_12_dis_col_sel}, {ldq_uop_11_dis_col_sel}, {ldq_uop_10_dis_col_sel}, {ldq_uop_9_dis_col_sel}, {ldq_uop_8_dis_col_sel}, {ldq_uop_7_dis_col_sel}, {ldq_uop_6_dis_col_sel}, {ldq_uop_5_dis_col_sel}, {ldq_uop_4_dis_col_sel}, {ldq_uop_3_dis_col_sel}, {ldq_uop_2_dis_col_sel}, {ldq_uop_1_dis_col_sel}, {ldq_uop_0_dis_col_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_dis_col_sel = _GEN_102[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][11:0] _GEN_103 = {{ldq_uop_15_br_mask}, {ldq_uop_14_br_mask}, {ldq_uop_13_br_mask}, {ldq_uop_12_br_mask}, {ldq_uop_11_br_mask}, {ldq_uop_10_br_mask}, {ldq_uop_9_br_mask}, {ldq_uop_8_br_mask}, {ldq_uop_7_br_mask}, {ldq_uop_6_br_mask}, {ldq_uop_5_br_mask}, {ldq_uop_4_br_mask}, {ldq_uop_3_br_mask}, {ldq_uop_2_br_mask}, {ldq_uop_1_br_mask}, {ldq_uop_0_br_mask}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_br_mask = _GEN_103[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][3:0] _GEN_104 = {{ldq_uop_15_br_tag}, {ldq_uop_14_br_tag}, {ldq_uop_13_br_tag}, {ldq_uop_12_br_tag}, {ldq_uop_11_br_tag}, {ldq_uop_10_br_tag}, {ldq_uop_9_br_tag}, {ldq_uop_8_br_tag}, {ldq_uop_7_br_tag}, {ldq_uop_6_br_tag}, {ldq_uop_5_br_tag}, {ldq_uop_4_br_tag}, {ldq_uop_3_br_tag}, {ldq_uop_2_br_tag}, {ldq_uop_1_br_tag}, {ldq_uop_0_br_tag}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_br_tag = _GEN_104[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][3:0] _GEN_105 = {{ldq_uop_15_br_type}, {ldq_uop_14_br_type}, {ldq_uop_13_br_type}, {ldq_uop_12_br_type}, {ldq_uop_11_br_type}, {ldq_uop_10_br_type}, {ldq_uop_9_br_type}, {ldq_uop_8_br_type}, {ldq_uop_7_br_type}, {ldq_uop_6_br_type}, {ldq_uop_5_br_type}, {ldq_uop_4_br_type}, {ldq_uop_3_br_type}, {ldq_uop_2_br_type}, {ldq_uop_1_br_type}, {ldq_uop_0_br_type}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_br_type = _GEN_105[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_106 = {{ldq_uop_15_is_sfb}, {ldq_uop_14_is_sfb}, {ldq_uop_13_is_sfb}, {ldq_uop_12_is_sfb}, {ldq_uop_11_is_sfb}, {ldq_uop_10_is_sfb}, {ldq_uop_9_is_sfb}, {ldq_uop_8_is_sfb}, {ldq_uop_7_is_sfb}, {ldq_uop_6_is_sfb}, {ldq_uop_5_is_sfb}, {ldq_uop_4_is_sfb}, {ldq_uop_3_is_sfb}, {ldq_uop_2_is_sfb}, {ldq_uop_1_is_sfb}, {ldq_uop_0_is_sfb}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_sfb = _GEN_106[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_107 = {{ldq_uop_15_is_fence}, {ldq_uop_14_is_fence}, {ldq_uop_13_is_fence}, {ldq_uop_12_is_fence}, {ldq_uop_11_is_fence}, {ldq_uop_10_is_fence}, {ldq_uop_9_is_fence}, {ldq_uop_8_is_fence}, {ldq_uop_7_is_fence}, {ldq_uop_6_is_fence}, {ldq_uop_5_is_fence}, {ldq_uop_4_is_fence}, {ldq_uop_3_is_fence}, {ldq_uop_2_is_fence}, {ldq_uop_1_is_fence}, {ldq_uop_0_is_fence}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_fence = _GEN_107[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_108 = {{ldq_uop_15_is_fencei}, {ldq_uop_14_is_fencei}, {ldq_uop_13_is_fencei}, {ldq_uop_12_is_fencei}, {ldq_uop_11_is_fencei}, {ldq_uop_10_is_fencei}, {ldq_uop_9_is_fencei}, {ldq_uop_8_is_fencei}, {ldq_uop_7_is_fencei}, {ldq_uop_6_is_fencei}, {ldq_uop_5_is_fencei}, {ldq_uop_4_is_fencei}, {ldq_uop_3_is_fencei}, {ldq_uop_2_is_fencei}, {ldq_uop_1_is_fencei}, {ldq_uop_0_is_fencei}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_fencei = _GEN_108[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_109 = {{ldq_uop_15_is_sfence}, {ldq_uop_14_is_sfence}, {ldq_uop_13_is_sfence}, {ldq_uop_12_is_sfence}, {ldq_uop_11_is_sfence}, {ldq_uop_10_is_sfence}, {ldq_uop_9_is_sfence}, {ldq_uop_8_is_sfence}, {ldq_uop_7_is_sfence}, {ldq_uop_6_is_sfence}, {ldq_uop_5_is_sfence}, {ldq_uop_4_is_sfence}, {ldq_uop_3_is_sfence}, {ldq_uop_2_is_sfence}, {ldq_uop_1_is_sfence}, {ldq_uop_0_is_sfence}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_sfence = _GEN_109[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_110 = {{ldq_uop_15_is_amo}, {ldq_uop_14_is_amo}, {ldq_uop_13_is_amo}, {ldq_uop_12_is_amo}, {ldq_uop_11_is_amo}, {ldq_uop_10_is_amo}, {ldq_uop_9_is_amo}, {ldq_uop_8_is_amo}, {ldq_uop_7_is_amo}, {ldq_uop_6_is_amo}, {ldq_uop_5_is_amo}, {ldq_uop_4_is_amo}, {ldq_uop_3_is_amo}, {ldq_uop_2_is_amo}, {ldq_uop_1_is_amo}, {ldq_uop_0_is_amo}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_amo = _GEN_110[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_111 = {{ldq_uop_15_is_eret}, {ldq_uop_14_is_eret}, {ldq_uop_13_is_eret}, {ldq_uop_12_is_eret}, {ldq_uop_11_is_eret}, {ldq_uop_10_is_eret}, {ldq_uop_9_is_eret}, {ldq_uop_8_is_eret}, {ldq_uop_7_is_eret}, {ldq_uop_6_is_eret}, {ldq_uop_5_is_eret}, {ldq_uop_4_is_eret}, {ldq_uop_3_is_eret}, {ldq_uop_2_is_eret}, {ldq_uop_1_is_eret}, {ldq_uop_0_is_eret}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_eret = _GEN_111[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_112 = {{ldq_uop_15_is_sys_pc2epc}, {ldq_uop_14_is_sys_pc2epc}, {ldq_uop_13_is_sys_pc2epc}, {ldq_uop_12_is_sys_pc2epc}, {ldq_uop_11_is_sys_pc2epc}, {ldq_uop_10_is_sys_pc2epc}, {ldq_uop_9_is_sys_pc2epc}, {ldq_uop_8_is_sys_pc2epc}, {ldq_uop_7_is_sys_pc2epc}, {ldq_uop_6_is_sys_pc2epc}, {ldq_uop_5_is_sys_pc2epc}, {ldq_uop_4_is_sys_pc2epc}, {ldq_uop_3_is_sys_pc2epc}, {ldq_uop_2_is_sys_pc2epc}, {ldq_uop_1_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_sys_pc2epc = _GEN_112[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_113 = {{ldq_uop_15_is_rocc}, {ldq_uop_14_is_rocc}, {ldq_uop_13_is_rocc}, {ldq_uop_12_is_rocc}, {ldq_uop_11_is_rocc}, {ldq_uop_10_is_rocc}, {ldq_uop_9_is_rocc}, {ldq_uop_8_is_rocc}, {ldq_uop_7_is_rocc}, {ldq_uop_6_is_rocc}, {ldq_uop_5_is_rocc}, {ldq_uop_4_is_rocc}, {ldq_uop_3_is_rocc}, {ldq_uop_2_is_rocc}, {ldq_uop_1_is_rocc}, {ldq_uop_0_is_rocc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_rocc = _GEN_113[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_114 = {{ldq_uop_15_is_mov}, {ldq_uop_14_is_mov}, {ldq_uop_13_is_mov}, {ldq_uop_12_is_mov}, {ldq_uop_11_is_mov}, {ldq_uop_10_is_mov}, {ldq_uop_9_is_mov}, {ldq_uop_8_is_mov}, {ldq_uop_7_is_mov}, {ldq_uop_6_is_mov}, {ldq_uop_5_is_mov}, {ldq_uop_4_is_mov}, {ldq_uop_3_is_mov}, {ldq_uop_2_is_mov}, {ldq_uop_1_is_mov}, {ldq_uop_0_is_mov}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_mov = _GEN_114[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][4:0] _GEN_115 = {{ldq_uop_15_ftq_idx}, {ldq_uop_14_ftq_idx}, {ldq_uop_13_ftq_idx}, {ldq_uop_12_ftq_idx}, {ldq_uop_11_ftq_idx}, {ldq_uop_10_ftq_idx}, {ldq_uop_9_ftq_idx}, {ldq_uop_8_ftq_idx}, {ldq_uop_7_ftq_idx}, {ldq_uop_6_ftq_idx}, {ldq_uop_5_ftq_idx}, {ldq_uop_4_ftq_idx}, {ldq_uop_3_ftq_idx}, {ldq_uop_2_ftq_idx}, {ldq_uop_1_ftq_idx}, {ldq_uop_0_ftq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ftq_idx = _GEN_115[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_116 = {{ldq_uop_15_edge_inst}, {ldq_uop_14_edge_inst}, {ldq_uop_13_edge_inst}, {ldq_uop_12_edge_inst}, {ldq_uop_11_edge_inst}, {ldq_uop_10_edge_inst}, {ldq_uop_9_edge_inst}, {ldq_uop_8_edge_inst}, {ldq_uop_7_edge_inst}, {ldq_uop_6_edge_inst}, {ldq_uop_5_edge_inst}, {ldq_uop_4_edge_inst}, {ldq_uop_3_edge_inst}, {ldq_uop_2_edge_inst}, {ldq_uop_1_edge_inst}, {ldq_uop_0_edge_inst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_edge_inst = _GEN_116[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][5:0] _GEN_117 = {{ldq_uop_15_pc_lob}, {ldq_uop_14_pc_lob}, {ldq_uop_13_pc_lob}, {ldq_uop_12_pc_lob}, {ldq_uop_11_pc_lob}, {ldq_uop_10_pc_lob}, {ldq_uop_9_pc_lob}, {ldq_uop_8_pc_lob}, {ldq_uop_7_pc_lob}, {ldq_uop_6_pc_lob}, {ldq_uop_5_pc_lob}, {ldq_uop_4_pc_lob}, {ldq_uop_3_pc_lob}, {ldq_uop_2_pc_lob}, {ldq_uop_1_pc_lob}, {ldq_uop_0_pc_lob}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_pc_lob = _GEN_117[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_118 = {{ldq_uop_15_taken}, {ldq_uop_14_taken}, {ldq_uop_13_taken}, {ldq_uop_12_taken}, {ldq_uop_11_taken}, {ldq_uop_10_taken}, {ldq_uop_9_taken}, {ldq_uop_8_taken}, {ldq_uop_7_taken}, {ldq_uop_6_taken}, {ldq_uop_5_taken}, {ldq_uop_4_taken}, {ldq_uop_3_taken}, {ldq_uop_2_taken}, {ldq_uop_1_taken}, {ldq_uop_0_taken}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_taken = _GEN_118[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_119 = {{ldq_uop_15_imm_rename}, {ldq_uop_14_imm_rename}, {ldq_uop_13_imm_rename}, {ldq_uop_12_imm_rename}, {ldq_uop_11_imm_rename}, {ldq_uop_10_imm_rename}, {ldq_uop_9_imm_rename}, {ldq_uop_8_imm_rename}, {ldq_uop_7_imm_rename}, {ldq_uop_6_imm_rename}, {ldq_uop_5_imm_rename}, {ldq_uop_4_imm_rename}, {ldq_uop_3_imm_rename}, {ldq_uop_2_imm_rename}, {ldq_uop_1_imm_rename}, {ldq_uop_0_imm_rename}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_imm_rename = _GEN_119[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][2:0] _GEN_120 = {{ldq_uop_15_imm_sel}, {ldq_uop_14_imm_sel}, {ldq_uop_13_imm_sel}, {ldq_uop_12_imm_sel}, {ldq_uop_11_imm_sel}, {ldq_uop_10_imm_sel}, {ldq_uop_9_imm_sel}, {ldq_uop_8_imm_sel}, {ldq_uop_7_imm_sel}, {ldq_uop_6_imm_sel}, {ldq_uop_5_imm_sel}, {ldq_uop_4_imm_sel}, {ldq_uop_3_imm_sel}, {ldq_uop_2_imm_sel}, {ldq_uop_1_imm_sel}, {ldq_uop_0_imm_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_imm_sel = _GEN_120[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][4:0] _GEN_121 = {{ldq_uop_15_pimm}, {ldq_uop_14_pimm}, {ldq_uop_13_pimm}, {ldq_uop_12_pimm}, {ldq_uop_11_pimm}, {ldq_uop_10_pimm}, {ldq_uop_9_pimm}, {ldq_uop_8_pimm}, {ldq_uop_7_pimm}, {ldq_uop_6_pimm}, {ldq_uop_5_pimm}, {ldq_uop_4_pimm}, {ldq_uop_3_pimm}, {ldq_uop_2_pimm}, {ldq_uop_1_pimm}, {ldq_uop_0_pimm}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_pimm = _GEN_121[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][19:0] _GEN_122 = {{ldq_uop_15_imm_packed}, {ldq_uop_14_imm_packed}, {ldq_uop_13_imm_packed}, {ldq_uop_12_imm_packed}, {ldq_uop_11_imm_packed}, {ldq_uop_10_imm_packed}, {ldq_uop_9_imm_packed}, {ldq_uop_8_imm_packed}, {ldq_uop_7_imm_packed}, {ldq_uop_6_imm_packed}, {ldq_uop_5_imm_packed}, {ldq_uop_4_imm_packed}, {ldq_uop_3_imm_packed}, {ldq_uop_2_imm_packed}, {ldq_uop_1_imm_packed}, {ldq_uop_0_imm_packed}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_imm_packed = _GEN_122[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_123 = {{ldq_uop_15_op1_sel}, {ldq_uop_14_op1_sel}, {ldq_uop_13_op1_sel}, {ldq_uop_12_op1_sel}, {ldq_uop_11_op1_sel}, {ldq_uop_10_op1_sel}, {ldq_uop_9_op1_sel}, {ldq_uop_8_op1_sel}, {ldq_uop_7_op1_sel}, {ldq_uop_6_op1_sel}, {ldq_uop_5_op1_sel}, {ldq_uop_4_op1_sel}, {ldq_uop_3_op1_sel}, {ldq_uop_2_op1_sel}, {ldq_uop_1_op1_sel}, {ldq_uop_0_op1_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_op1_sel = _GEN_123[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][2:0] _GEN_124 = {{ldq_uop_15_op2_sel}, {ldq_uop_14_op2_sel}, {ldq_uop_13_op2_sel}, {ldq_uop_12_op2_sel}, {ldq_uop_11_op2_sel}, {ldq_uop_10_op2_sel}, {ldq_uop_9_op2_sel}, {ldq_uop_8_op2_sel}, {ldq_uop_7_op2_sel}, {ldq_uop_6_op2_sel}, {ldq_uop_5_op2_sel}, {ldq_uop_4_op2_sel}, {ldq_uop_3_op2_sel}, {ldq_uop_2_op2_sel}, {ldq_uop_1_op2_sel}, {ldq_uop_0_op2_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_op2_sel = _GEN_124[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_125 = {{ldq_uop_15_fp_ctrl_ldst}, {ldq_uop_14_fp_ctrl_ldst}, {ldq_uop_13_fp_ctrl_ldst}, {ldq_uop_12_fp_ctrl_ldst}, {ldq_uop_11_fp_ctrl_ldst}, {ldq_uop_10_fp_ctrl_ldst}, {ldq_uop_9_fp_ctrl_ldst}, {ldq_uop_8_fp_ctrl_ldst}, {ldq_uop_7_fp_ctrl_ldst}, {ldq_uop_6_fp_ctrl_ldst}, {ldq_uop_5_fp_ctrl_ldst}, {ldq_uop_4_fp_ctrl_ldst}, {ldq_uop_3_fp_ctrl_ldst}, {ldq_uop_2_fp_ctrl_ldst}, {ldq_uop_1_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ldst = _GEN_125[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_126 = {{ldq_uop_15_fp_ctrl_wen}, {ldq_uop_14_fp_ctrl_wen}, {ldq_uop_13_fp_ctrl_wen}, {ldq_uop_12_fp_ctrl_wen}, {ldq_uop_11_fp_ctrl_wen}, {ldq_uop_10_fp_ctrl_wen}, {ldq_uop_9_fp_ctrl_wen}, {ldq_uop_8_fp_ctrl_wen}, {ldq_uop_7_fp_ctrl_wen}, {ldq_uop_6_fp_ctrl_wen}, {ldq_uop_5_fp_ctrl_wen}, {ldq_uop_4_fp_ctrl_wen}, {ldq_uop_3_fp_ctrl_wen}, {ldq_uop_2_fp_ctrl_wen}, {ldq_uop_1_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_wen = _GEN_126[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_127 = {{ldq_uop_15_fp_ctrl_ren1}, {ldq_uop_14_fp_ctrl_ren1}, {ldq_uop_13_fp_ctrl_ren1}, {ldq_uop_12_fp_ctrl_ren1}, {ldq_uop_11_fp_ctrl_ren1}, {ldq_uop_10_fp_ctrl_ren1}, {ldq_uop_9_fp_ctrl_ren1}, {ldq_uop_8_fp_ctrl_ren1}, {ldq_uop_7_fp_ctrl_ren1}, {ldq_uop_6_fp_ctrl_ren1}, {ldq_uop_5_fp_ctrl_ren1}, {ldq_uop_4_fp_ctrl_ren1}, {ldq_uop_3_fp_ctrl_ren1}, {ldq_uop_2_fp_ctrl_ren1}, {ldq_uop_1_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ren1 = _GEN_127[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_128 = {{ldq_uop_15_fp_ctrl_ren2}, {ldq_uop_14_fp_ctrl_ren2}, {ldq_uop_13_fp_ctrl_ren2}, {ldq_uop_12_fp_ctrl_ren2}, {ldq_uop_11_fp_ctrl_ren2}, {ldq_uop_10_fp_ctrl_ren2}, {ldq_uop_9_fp_ctrl_ren2}, {ldq_uop_8_fp_ctrl_ren2}, {ldq_uop_7_fp_ctrl_ren2}, {ldq_uop_6_fp_ctrl_ren2}, {ldq_uop_5_fp_ctrl_ren2}, {ldq_uop_4_fp_ctrl_ren2}, {ldq_uop_3_fp_ctrl_ren2}, {ldq_uop_2_fp_ctrl_ren2}, {ldq_uop_1_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ren2 = _GEN_128[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_129 = {{ldq_uop_15_fp_ctrl_ren3}, {ldq_uop_14_fp_ctrl_ren3}, {ldq_uop_13_fp_ctrl_ren3}, {ldq_uop_12_fp_ctrl_ren3}, {ldq_uop_11_fp_ctrl_ren3}, {ldq_uop_10_fp_ctrl_ren3}, {ldq_uop_9_fp_ctrl_ren3}, {ldq_uop_8_fp_ctrl_ren3}, {ldq_uop_7_fp_ctrl_ren3}, {ldq_uop_6_fp_ctrl_ren3}, {ldq_uop_5_fp_ctrl_ren3}, {ldq_uop_4_fp_ctrl_ren3}, {ldq_uop_3_fp_ctrl_ren3}, {ldq_uop_2_fp_ctrl_ren3}, {ldq_uop_1_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ren3 = _GEN_129[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_130 = {{ldq_uop_15_fp_ctrl_swap12}, {ldq_uop_14_fp_ctrl_swap12}, {ldq_uop_13_fp_ctrl_swap12}, {ldq_uop_12_fp_ctrl_swap12}, {ldq_uop_11_fp_ctrl_swap12}, {ldq_uop_10_fp_ctrl_swap12}, {ldq_uop_9_fp_ctrl_swap12}, {ldq_uop_8_fp_ctrl_swap12}, {ldq_uop_7_fp_ctrl_swap12}, {ldq_uop_6_fp_ctrl_swap12}, {ldq_uop_5_fp_ctrl_swap12}, {ldq_uop_4_fp_ctrl_swap12}, {ldq_uop_3_fp_ctrl_swap12}, {ldq_uop_2_fp_ctrl_swap12}, {ldq_uop_1_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_swap12 = _GEN_130[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_131 = {{ldq_uop_15_fp_ctrl_swap23}, {ldq_uop_14_fp_ctrl_swap23}, {ldq_uop_13_fp_ctrl_swap23}, {ldq_uop_12_fp_ctrl_swap23}, {ldq_uop_11_fp_ctrl_swap23}, {ldq_uop_10_fp_ctrl_swap23}, {ldq_uop_9_fp_ctrl_swap23}, {ldq_uop_8_fp_ctrl_swap23}, {ldq_uop_7_fp_ctrl_swap23}, {ldq_uop_6_fp_ctrl_swap23}, {ldq_uop_5_fp_ctrl_swap23}, {ldq_uop_4_fp_ctrl_swap23}, {ldq_uop_3_fp_ctrl_swap23}, {ldq_uop_2_fp_ctrl_swap23}, {ldq_uop_1_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_swap23 = _GEN_131[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_132 = {{ldq_uop_15_fp_ctrl_typeTagIn}, {ldq_uop_14_fp_ctrl_typeTagIn}, {ldq_uop_13_fp_ctrl_typeTagIn}, {ldq_uop_12_fp_ctrl_typeTagIn}, {ldq_uop_11_fp_ctrl_typeTagIn}, {ldq_uop_10_fp_ctrl_typeTagIn}, {ldq_uop_9_fp_ctrl_typeTagIn}, {ldq_uop_8_fp_ctrl_typeTagIn}, {ldq_uop_7_fp_ctrl_typeTagIn}, {ldq_uop_6_fp_ctrl_typeTagIn}, {ldq_uop_5_fp_ctrl_typeTagIn}, {ldq_uop_4_fp_ctrl_typeTagIn}, {ldq_uop_3_fp_ctrl_typeTagIn}, {ldq_uop_2_fp_ctrl_typeTagIn}, {ldq_uop_1_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_132[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_133 = {{ldq_uop_15_fp_ctrl_typeTagOut}, {ldq_uop_14_fp_ctrl_typeTagOut}, {ldq_uop_13_fp_ctrl_typeTagOut}, {ldq_uop_12_fp_ctrl_typeTagOut}, {ldq_uop_11_fp_ctrl_typeTagOut}, {ldq_uop_10_fp_ctrl_typeTagOut}, {ldq_uop_9_fp_ctrl_typeTagOut}, {ldq_uop_8_fp_ctrl_typeTagOut}, {ldq_uop_7_fp_ctrl_typeTagOut}, {ldq_uop_6_fp_ctrl_typeTagOut}, {ldq_uop_5_fp_ctrl_typeTagOut}, {ldq_uop_4_fp_ctrl_typeTagOut}, {ldq_uop_3_fp_ctrl_typeTagOut}, {ldq_uop_2_fp_ctrl_typeTagOut}, {ldq_uop_1_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_133[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_134 = {{ldq_uop_15_fp_ctrl_fromint}, {ldq_uop_14_fp_ctrl_fromint}, {ldq_uop_13_fp_ctrl_fromint}, {ldq_uop_12_fp_ctrl_fromint}, {ldq_uop_11_fp_ctrl_fromint}, {ldq_uop_10_fp_ctrl_fromint}, {ldq_uop_9_fp_ctrl_fromint}, {ldq_uop_8_fp_ctrl_fromint}, {ldq_uop_7_fp_ctrl_fromint}, {ldq_uop_6_fp_ctrl_fromint}, {ldq_uop_5_fp_ctrl_fromint}, {ldq_uop_4_fp_ctrl_fromint}, {ldq_uop_3_fp_ctrl_fromint}, {ldq_uop_2_fp_ctrl_fromint}, {ldq_uop_1_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_fromint = _GEN_134[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_135 = {{ldq_uop_15_fp_ctrl_toint}, {ldq_uop_14_fp_ctrl_toint}, {ldq_uop_13_fp_ctrl_toint}, {ldq_uop_12_fp_ctrl_toint}, {ldq_uop_11_fp_ctrl_toint}, {ldq_uop_10_fp_ctrl_toint}, {ldq_uop_9_fp_ctrl_toint}, {ldq_uop_8_fp_ctrl_toint}, {ldq_uop_7_fp_ctrl_toint}, {ldq_uop_6_fp_ctrl_toint}, {ldq_uop_5_fp_ctrl_toint}, {ldq_uop_4_fp_ctrl_toint}, {ldq_uop_3_fp_ctrl_toint}, {ldq_uop_2_fp_ctrl_toint}, {ldq_uop_1_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_toint = _GEN_135[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_136 = {{ldq_uop_15_fp_ctrl_fastpipe}, {ldq_uop_14_fp_ctrl_fastpipe}, {ldq_uop_13_fp_ctrl_fastpipe}, {ldq_uop_12_fp_ctrl_fastpipe}, {ldq_uop_11_fp_ctrl_fastpipe}, {ldq_uop_10_fp_ctrl_fastpipe}, {ldq_uop_9_fp_ctrl_fastpipe}, {ldq_uop_8_fp_ctrl_fastpipe}, {ldq_uop_7_fp_ctrl_fastpipe}, {ldq_uop_6_fp_ctrl_fastpipe}, {ldq_uop_5_fp_ctrl_fastpipe}, {ldq_uop_4_fp_ctrl_fastpipe}, {ldq_uop_3_fp_ctrl_fastpipe}, {ldq_uop_2_fp_ctrl_fastpipe}, {ldq_uop_1_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_136[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_137 = {{ldq_uop_15_fp_ctrl_fma}, {ldq_uop_14_fp_ctrl_fma}, {ldq_uop_13_fp_ctrl_fma}, {ldq_uop_12_fp_ctrl_fma}, {ldq_uop_11_fp_ctrl_fma}, {ldq_uop_10_fp_ctrl_fma}, {ldq_uop_9_fp_ctrl_fma}, {ldq_uop_8_fp_ctrl_fma}, {ldq_uop_7_fp_ctrl_fma}, {ldq_uop_6_fp_ctrl_fma}, {ldq_uop_5_fp_ctrl_fma}, {ldq_uop_4_fp_ctrl_fma}, {ldq_uop_3_fp_ctrl_fma}, {ldq_uop_2_fp_ctrl_fma}, {ldq_uop_1_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_fma = _GEN_137[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_138 = {{ldq_uop_15_fp_ctrl_div}, {ldq_uop_14_fp_ctrl_div}, {ldq_uop_13_fp_ctrl_div}, {ldq_uop_12_fp_ctrl_div}, {ldq_uop_11_fp_ctrl_div}, {ldq_uop_10_fp_ctrl_div}, {ldq_uop_9_fp_ctrl_div}, {ldq_uop_8_fp_ctrl_div}, {ldq_uop_7_fp_ctrl_div}, {ldq_uop_6_fp_ctrl_div}, {ldq_uop_5_fp_ctrl_div}, {ldq_uop_4_fp_ctrl_div}, {ldq_uop_3_fp_ctrl_div}, {ldq_uop_2_fp_ctrl_div}, {ldq_uop_1_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_div = _GEN_138[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_139 = {{ldq_uop_15_fp_ctrl_sqrt}, {ldq_uop_14_fp_ctrl_sqrt}, {ldq_uop_13_fp_ctrl_sqrt}, {ldq_uop_12_fp_ctrl_sqrt}, {ldq_uop_11_fp_ctrl_sqrt}, {ldq_uop_10_fp_ctrl_sqrt}, {ldq_uop_9_fp_ctrl_sqrt}, {ldq_uop_8_fp_ctrl_sqrt}, {ldq_uop_7_fp_ctrl_sqrt}, {ldq_uop_6_fp_ctrl_sqrt}, {ldq_uop_5_fp_ctrl_sqrt}, {ldq_uop_4_fp_ctrl_sqrt}, {ldq_uop_3_fp_ctrl_sqrt}, {ldq_uop_2_fp_ctrl_sqrt}, {ldq_uop_1_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_sqrt = _GEN_139[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_140 = {{ldq_uop_15_fp_ctrl_wflags}, {ldq_uop_14_fp_ctrl_wflags}, {ldq_uop_13_fp_ctrl_wflags}, {ldq_uop_12_fp_ctrl_wflags}, {ldq_uop_11_fp_ctrl_wflags}, {ldq_uop_10_fp_ctrl_wflags}, {ldq_uop_9_fp_ctrl_wflags}, {ldq_uop_8_fp_ctrl_wflags}, {ldq_uop_7_fp_ctrl_wflags}, {ldq_uop_6_fp_ctrl_wflags}, {ldq_uop_5_fp_ctrl_wflags}, {ldq_uop_4_fp_ctrl_wflags}, {ldq_uop_3_fp_ctrl_wflags}, {ldq_uop_2_fp_ctrl_wflags}, {ldq_uop_1_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_wflags = _GEN_140[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_141 = {{ldq_uop_15_fp_ctrl_vec}, {ldq_uop_14_fp_ctrl_vec}, {ldq_uop_13_fp_ctrl_vec}, {ldq_uop_12_fp_ctrl_vec}, {ldq_uop_11_fp_ctrl_vec}, {ldq_uop_10_fp_ctrl_vec}, {ldq_uop_9_fp_ctrl_vec}, {ldq_uop_8_fp_ctrl_vec}, {ldq_uop_7_fp_ctrl_vec}, {ldq_uop_6_fp_ctrl_vec}, {ldq_uop_5_fp_ctrl_vec}, {ldq_uop_4_fp_ctrl_vec}, {ldq_uop_3_fp_ctrl_vec}, {ldq_uop_2_fp_ctrl_vec}, {ldq_uop_1_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_vec = _GEN_141[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][5:0] _GEN_142 = {{ldq_uop_15_rob_idx}, {ldq_uop_14_rob_idx}, {ldq_uop_13_rob_idx}, {ldq_uop_12_rob_idx}, {ldq_uop_11_rob_idx}, {ldq_uop_10_rob_idx}, {ldq_uop_9_rob_idx}, {ldq_uop_8_rob_idx}, {ldq_uop_7_rob_idx}, {ldq_uop_6_rob_idx}, {ldq_uop_5_rob_idx}, {ldq_uop_4_rob_idx}, {ldq_uop_3_rob_idx}, {ldq_uop_2_rob_idx}, {ldq_uop_1_rob_idx}, {ldq_uop_0_rob_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_rob_idx = _GEN_142[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][3:0] _GEN_143 = {{ldq_uop_15_ldq_idx}, {ldq_uop_14_ldq_idx}, {ldq_uop_13_ldq_idx}, {ldq_uop_12_ldq_idx}, {ldq_uop_11_ldq_idx}, {ldq_uop_10_ldq_idx}, {ldq_uop_9_ldq_idx}, {ldq_uop_8_ldq_idx}, {ldq_uop_7_ldq_idx}, {ldq_uop_6_ldq_idx}, {ldq_uop_5_ldq_idx}, {ldq_uop_4_ldq_idx}, {ldq_uop_3_ldq_idx}, {ldq_uop_2_ldq_idx}, {ldq_uop_1_ldq_idx}, {ldq_uop_0_ldq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ldq_idx = _GEN_143[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][3:0] _GEN_144 = {{ldq_uop_15_stq_idx}, {ldq_uop_14_stq_idx}, {ldq_uop_13_stq_idx}, {ldq_uop_12_stq_idx}, {ldq_uop_11_stq_idx}, {ldq_uop_10_stq_idx}, {ldq_uop_9_stq_idx}, {ldq_uop_8_stq_idx}, {ldq_uop_7_stq_idx}, {ldq_uop_6_stq_idx}, {ldq_uop_5_stq_idx}, {ldq_uop_4_stq_idx}, {ldq_uop_3_stq_idx}, {ldq_uop_2_stq_idx}, {ldq_uop_1_stq_idx}, {ldq_uop_0_stq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_stq_idx = _GEN_144[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_145 = {{ldq_uop_15_rxq_idx}, {ldq_uop_14_rxq_idx}, {ldq_uop_13_rxq_idx}, {ldq_uop_12_rxq_idx}, {ldq_uop_11_rxq_idx}, {ldq_uop_10_rxq_idx}, {ldq_uop_9_rxq_idx}, {ldq_uop_8_rxq_idx}, {ldq_uop_7_rxq_idx}, {ldq_uop_6_rxq_idx}, {ldq_uop_5_rxq_idx}, {ldq_uop_4_rxq_idx}, {ldq_uop_3_rxq_idx}, {ldq_uop_2_rxq_idx}, {ldq_uop_1_rxq_idx}, {ldq_uop_0_rxq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_rxq_idx = _GEN_145[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][6:0] _GEN_146 = {{ldq_uop_15_pdst}, {ldq_uop_14_pdst}, {ldq_uop_13_pdst}, {ldq_uop_12_pdst}, {ldq_uop_11_pdst}, {ldq_uop_10_pdst}, {ldq_uop_9_pdst}, {ldq_uop_8_pdst}, {ldq_uop_7_pdst}, {ldq_uop_6_pdst}, {ldq_uop_5_pdst}, {ldq_uop_4_pdst}, {ldq_uop_3_pdst}, {ldq_uop_2_pdst}, {ldq_uop_1_pdst}, {ldq_uop_0_pdst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_pdst = _GEN_146[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][6:0] _GEN_147 = {{ldq_uop_15_prs1}, {ldq_uop_14_prs1}, {ldq_uop_13_prs1}, {ldq_uop_12_prs1}, {ldq_uop_11_prs1}, {ldq_uop_10_prs1}, {ldq_uop_9_prs1}, {ldq_uop_8_prs1}, {ldq_uop_7_prs1}, {ldq_uop_6_prs1}, {ldq_uop_5_prs1}, {ldq_uop_4_prs1}, {ldq_uop_3_prs1}, {ldq_uop_2_prs1}, {ldq_uop_1_prs1}, {ldq_uop_0_prs1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs1 = _GEN_147[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][6:0] _GEN_148 = {{ldq_uop_15_prs2}, {ldq_uop_14_prs2}, {ldq_uop_13_prs2}, {ldq_uop_12_prs2}, {ldq_uop_11_prs2}, {ldq_uop_10_prs2}, {ldq_uop_9_prs2}, {ldq_uop_8_prs2}, {ldq_uop_7_prs2}, {ldq_uop_6_prs2}, {ldq_uop_5_prs2}, {ldq_uop_4_prs2}, {ldq_uop_3_prs2}, {ldq_uop_2_prs2}, {ldq_uop_1_prs2}, {ldq_uop_0_prs2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs2 = _GEN_148[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][6:0] _GEN_149 = {{ldq_uop_15_prs3}, {ldq_uop_14_prs3}, {ldq_uop_13_prs3}, {ldq_uop_12_prs3}, {ldq_uop_11_prs3}, {ldq_uop_10_prs3}, {ldq_uop_9_prs3}, {ldq_uop_8_prs3}, {ldq_uop_7_prs3}, {ldq_uop_6_prs3}, {ldq_uop_5_prs3}, {ldq_uop_4_prs3}, {ldq_uop_3_prs3}, {ldq_uop_2_prs3}, {ldq_uop_1_prs3}, {ldq_uop_0_prs3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs3 = _GEN_149[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][4:0] _GEN_150 = {{ldq_uop_15_ppred}, {ldq_uop_14_ppred}, {ldq_uop_13_ppred}, {ldq_uop_12_ppred}, {ldq_uop_11_ppred}, {ldq_uop_10_ppred}, {ldq_uop_9_ppred}, {ldq_uop_8_ppred}, {ldq_uop_7_ppred}, {ldq_uop_6_ppred}, {ldq_uop_5_ppred}, {ldq_uop_4_ppred}, {ldq_uop_3_ppred}, {ldq_uop_2_ppred}, {ldq_uop_1_ppred}, {ldq_uop_0_ppred}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ppred = _GEN_150[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_151 = {{ldq_uop_15_prs1_busy}, {ldq_uop_14_prs1_busy}, {ldq_uop_13_prs1_busy}, {ldq_uop_12_prs1_busy}, {ldq_uop_11_prs1_busy}, {ldq_uop_10_prs1_busy}, {ldq_uop_9_prs1_busy}, {ldq_uop_8_prs1_busy}, {ldq_uop_7_prs1_busy}, {ldq_uop_6_prs1_busy}, {ldq_uop_5_prs1_busy}, {ldq_uop_4_prs1_busy}, {ldq_uop_3_prs1_busy}, {ldq_uop_2_prs1_busy}, {ldq_uop_1_prs1_busy}, {ldq_uop_0_prs1_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs1_busy = _GEN_151[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_152 = {{ldq_uop_15_prs2_busy}, {ldq_uop_14_prs2_busy}, {ldq_uop_13_prs2_busy}, {ldq_uop_12_prs2_busy}, {ldq_uop_11_prs2_busy}, {ldq_uop_10_prs2_busy}, {ldq_uop_9_prs2_busy}, {ldq_uop_8_prs2_busy}, {ldq_uop_7_prs2_busy}, {ldq_uop_6_prs2_busy}, {ldq_uop_5_prs2_busy}, {ldq_uop_4_prs2_busy}, {ldq_uop_3_prs2_busy}, {ldq_uop_2_prs2_busy}, {ldq_uop_1_prs2_busy}, {ldq_uop_0_prs2_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs2_busy = _GEN_152[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_153 = {{ldq_uop_15_prs3_busy}, {ldq_uop_14_prs3_busy}, {ldq_uop_13_prs3_busy}, {ldq_uop_12_prs3_busy}, {ldq_uop_11_prs3_busy}, {ldq_uop_10_prs3_busy}, {ldq_uop_9_prs3_busy}, {ldq_uop_8_prs3_busy}, {ldq_uop_7_prs3_busy}, {ldq_uop_6_prs3_busy}, {ldq_uop_5_prs3_busy}, {ldq_uop_4_prs3_busy}, {ldq_uop_3_prs3_busy}, {ldq_uop_2_prs3_busy}, {ldq_uop_1_prs3_busy}, {ldq_uop_0_prs3_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs3_busy = _GEN_153[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_154 = {{ldq_uop_15_ppred_busy}, {ldq_uop_14_ppred_busy}, {ldq_uop_13_ppred_busy}, {ldq_uop_12_ppred_busy}, {ldq_uop_11_ppred_busy}, {ldq_uop_10_ppred_busy}, {ldq_uop_9_ppred_busy}, {ldq_uop_8_ppred_busy}, {ldq_uop_7_ppred_busy}, {ldq_uop_6_ppred_busy}, {ldq_uop_5_ppred_busy}, {ldq_uop_4_ppred_busy}, {ldq_uop_3_ppred_busy}, {ldq_uop_2_ppred_busy}, {ldq_uop_1_ppred_busy}, {ldq_uop_0_ppred_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ppred_busy = _GEN_154[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][6:0] _GEN_155 = {{ldq_uop_15_stale_pdst}, {ldq_uop_14_stale_pdst}, {ldq_uop_13_stale_pdst}, {ldq_uop_12_stale_pdst}, {ldq_uop_11_stale_pdst}, {ldq_uop_10_stale_pdst}, {ldq_uop_9_stale_pdst}, {ldq_uop_8_stale_pdst}, {ldq_uop_7_stale_pdst}, {ldq_uop_6_stale_pdst}, {ldq_uop_5_stale_pdst}, {ldq_uop_4_stale_pdst}, {ldq_uop_3_stale_pdst}, {ldq_uop_2_stale_pdst}, {ldq_uop_1_stale_pdst}, {ldq_uop_0_stale_pdst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_stale_pdst = _GEN_155[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_156 = {{ldq_uop_15_exception}, {ldq_uop_14_exception}, {ldq_uop_13_exception}, {ldq_uop_12_exception}, {ldq_uop_11_exception}, {ldq_uop_10_exception}, {ldq_uop_9_exception}, {ldq_uop_8_exception}, {ldq_uop_7_exception}, {ldq_uop_6_exception}, {ldq_uop_5_exception}, {ldq_uop_4_exception}, {ldq_uop_3_exception}, {ldq_uop_2_exception}, {ldq_uop_1_exception}, {ldq_uop_0_exception}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_exception = _GEN_156[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][63:0] _GEN_157 = {{ldq_uop_15_exc_cause}, {ldq_uop_14_exc_cause}, {ldq_uop_13_exc_cause}, {ldq_uop_12_exc_cause}, {ldq_uop_11_exc_cause}, {ldq_uop_10_exc_cause}, {ldq_uop_9_exc_cause}, {ldq_uop_8_exc_cause}, {ldq_uop_7_exc_cause}, {ldq_uop_6_exc_cause}, {ldq_uop_5_exc_cause}, {ldq_uop_4_exc_cause}, {ldq_uop_3_exc_cause}, {ldq_uop_2_exc_cause}, {ldq_uop_1_exc_cause}, {ldq_uop_0_exc_cause}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_exc_cause = _GEN_157[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][4:0] _GEN_158 = {{ldq_uop_15_mem_cmd}, {ldq_uop_14_mem_cmd}, {ldq_uop_13_mem_cmd}, {ldq_uop_12_mem_cmd}, {ldq_uop_11_mem_cmd}, {ldq_uop_10_mem_cmd}, {ldq_uop_9_mem_cmd}, {ldq_uop_8_mem_cmd}, {ldq_uop_7_mem_cmd}, {ldq_uop_6_mem_cmd}, {ldq_uop_5_mem_cmd}, {ldq_uop_4_mem_cmd}, {ldq_uop_3_mem_cmd}, {ldq_uop_2_mem_cmd}, {ldq_uop_1_mem_cmd}, {ldq_uop_0_mem_cmd}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_mem_cmd = _GEN_158[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_159 = {{ldq_uop_15_mem_size}, {ldq_uop_14_mem_size}, {ldq_uop_13_mem_size}, {ldq_uop_12_mem_size}, {ldq_uop_11_mem_size}, {ldq_uop_10_mem_size}, {ldq_uop_9_mem_size}, {ldq_uop_8_mem_size}, {ldq_uop_7_mem_size}, {ldq_uop_6_mem_size}, {ldq_uop_5_mem_size}, {ldq_uop_4_mem_size}, {ldq_uop_3_mem_size}, {ldq_uop_2_mem_size}, {ldq_uop_1_mem_size}, {ldq_uop_0_mem_size}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_mem_size = _GEN_159[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_160 = {{ldq_uop_15_mem_signed}, {ldq_uop_14_mem_signed}, {ldq_uop_13_mem_signed}, {ldq_uop_12_mem_signed}, {ldq_uop_11_mem_signed}, {ldq_uop_10_mem_signed}, {ldq_uop_9_mem_signed}, {ldq_uop_8_mem_signed}, {ldq_uop_7_mem_signed}, {ldq_uop_6_mem_signed}, {ldq_uop_5_mem_signed}, {ldq_uop_4_mem_signed}, {ldq_uop_3_mem_signed}, {ldq_uop_2_mem_signed}, {ldq_uop_1_mem_signed}, {ldq_uop_0_mem_signed}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_mem_signed = _GEN_160[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_161 = {{ldq_uop_15_uses_ldq}, {ldq_uop_14_uses_ldq}, {ldq_uop_13_uses_ldq}, {ldq_uop_12_uses_ldq}, {ldq_uop_11_uses_ldq}, {ldq_uop_10_uses_ldq}, {ldq_uop_9_uses_ldq}, {ldq_uop_8_uses_ldq}, {ldq_uop_7_uses_ldq}, {ldq_uop_6_uses_ldq}, {ldq_uop_5_uses_ldq}, {ldq_uop_4_uses_ldq}, {ldq_uop_3_uses_ldq}, {ldq_uop_2_uses_ldq}, {ldq_uop_1_uses_ldq}, {ldq_uop_0_uses_ldq}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_uses_ldq = _GEN_161[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_162 = {{ldq_uop_15_uses_stq}, {ldq_uop_14_uses_stq}, {ldq_uop_13_uses_stq}, {ldq_uop_12_uses_stq}, {ldq_uop_11_uses_stq}, {ldq_uop_10_uses_stq}, {ldq_uop_9_uses_stq}, {ldq_uop_8_uses_stq}, {ldq_uop_7_uses_stq}, {ldq_uop_6_uses_stq}, {ldq_uop_5_uses_stq}, {ldq_uop_4_uses_stq}, {ldq_uop_3_uses_stq}, {ldq_uop_2_uses_stq}, {ldq_uop_1_uses_stq}, {ldq_uop_0_uses_stq}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_uses_stq = _GEN_162[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_163 = {{ldq_uop_15_is_unique}, {ldq_uop_14_is_unique}, {ldq_uop_13_is_unique}, {ldq_uop_12_is_unique}, {ldq_uop_11_is_unique}, {ldq_uop_10_is_unique}, {ldq_uop_9_is_unique}, {ldq_uop_8_is_unique}, {ldq_uop_7_is_unique}, {ldq_uop_6_is_unique}, {ldq_uop_5_is_unique}, {ldq_uop_4_is_unique}, {ldq_uop_3_is_unique}, {ldq_uop_2_is_unique}, {ldq_uop_1_is_unique}, {ldq_uop_0_is_unique}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_unique = _GEN_163[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_164 = {{ldq_uop_15_flush_on_commit}, {ldq_uop_14_flush_on_commit}, {ldq_uop_13_flush_on_commit}, {ldq_uop_12_flush_on_commit}, {ldq_uop_11_flush_on_commit}, {ldq_uop_10_flush_on_commit}, {ldq_uop_9_flush_on_commit}, {ldq_uop_8_flush_on_commit}, {ldq_uop_7_flush_on_commit}, {ldq_uop_6_flush_on_commit}, {ldq_uop_5_flush_on_commit}, {ldq_uop_4_flush_on_commit}, {ldq_uop_3_flush_on_commit}, {ldq_uop_2_flush_on_commit}, {ldq_uop_1_flush_on_commit}, {ldq_uop_0_flush_on_commit}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_flush_on_commit = _GEN_164[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][2:0] _GEN_165 = {{ldq_uop_15_csr_cmd}, {ldq_uop_14_csr_cmd}, {ldq_uop_13_csr_cmd}, {ldq_uop_12_csr_cmd}, {ldq_uop_11_csr_cmd}, {ldq_uop_10_csr_cmd}, {ldq_uop_9_csr_cmd}, {ldq_uop_8_csr_cmd}, {ldq_uop_7_csr_cmd}, {ldq_uop_6_csr_cmd}, {ldq_uop_5_csr_cmd}, {ldq_uop_4_csr_cmd}, {ldq_uop_3_csr_cmd}, {ldq_uop_2_csr_cmd}, {ldq_uop_1_csr_cmd}, {ldq_uop_0_csr_cmd}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_csr_cmd = _GEN_165[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_166 = {{ldq_uop_15_ldst_is_rs1}, {ldq_uop_14_ldst_is_rs1}, {ldq_uop_13_ldst_is_rs1}, {ldq_uop_12_ldst_is_rs1}, {ldq_uop_11_ldst_is_rs1}, {ldq_uop_10_ldst_is_rs1}, {ldq_uop_9_ldst_is_rs1}, {ldq_uop_8_ldst_is_rs1}, {ldq_uop_7_ldst_is_rs1}, {ldq_uop_6_ldst_is_rs1}, {ldq_uop_5_ldst_is_rs1}, {ldq_uop_4_ldst_is_rs1}, {ldq_uop_3_ldst_is_rs1}, {ldq_uop_2_ldst_is_rs1}, {ldq_uop_1_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ldst_is_rs1 = _GEN_166[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][5:0] _GEN_167 = {{ldq_uop_15_ldst}, {ldq_uop_14_ldst}, {ldq_uop_13_ldst}, {ldq_uop_12_ldst}, {ldq_uop_11_ldst}, {ldq_uop_10_ldst}, {ldq_uop_9_ldst}, {ldq_uop_8_ldst}, {ldq_uop_7_ldst}, {ldq_uop_6_ldst}, {ldq_uop_5_ldst}, {ldq_uop_4_ldst}, {ldq_uop_3_ldst}, {ldq_uop_2_ldst}, {ldq_uop_1_ldst}, {ldq_uop_0_ldst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ldst = _GEN_167[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][5:0] _GEN_168 = {{ldq_uop_15_lrs1}, {ldq_uop_14_lrs1}, {ldq_uop_13_lrs1}, {ldq_uop_12_lrs1}, {ldq_uop_11_lrs1}, {ldq_uop_10_lrs1}, {ldq_uop_9_lrs1}, {ldq_uop_8_lrs1}, {ldq_uop_7_lrs1}, {ldq_uop_6_lrs1}, {ldq_uop_5_lrs1}, {ldq_uop_4_lrs1}, {ldq_uop_3_lrs1}, {ldq_uop_2_lrs1}, {ldq_uop_1_lrs1}, {ldq_uop_0_lrs1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs1 = _GEN_168[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][5:0] _GEN_169 = {{ldq_uop_15_lrs2}, {ldq_uop_14_lrs2}, {ldq_uop_13_lrs2}, {ldq_uop_12_lrs2}, {ldq_uop_11_lrs2}, {ldq_uop_10_lrs2}, {ldq_uop_9_lrs2}, {ldq_uop_8_lrs2}, {ldq_uop_7_lrs2}, {ldq_uop_6_lrs2}, {ldq_uop_5_lrs2}, {ldq_uop_4_lrs2}, {ldq_uop_3_lrs2}, {ldq_uop_2_lrs2}, {ldq_uop_1_lrs2}, {ldq_uop_0_lrs2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs2 = _GEN_169[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][5:0] _GEN_170 = {{ldq_uop_15_lrs3}, {ldq_uop_14_lrs3}, {ldq_uop_13_lrs3}, {ldq_uop_12_lrs3}, {ldq_uop_11_lrs3}, {ldq_uop_10_lrs3}, {ldq_uop_9_lrs3}, {ldq_uop_8_lrs3}, {ldq_uop_7_lrs3}, {ldq_uop_6_lrs3}, {ldq_uop_5_lrs3}, {ldq_uop_4_lrs3}, {ldq_uop_3_lrs3}, {ldq_uop_2_lrs3}, {ldq_uop_1_lrs3}, {ldq_uop_0_lrs3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs3 = _GEN_170[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_171 = {{ldq_uop_15_dst_rtype}, {ldq_uop_14_dst_rtype}, {ldq_uop_13_dst_rtype}, {ldq_uop_12_dst_rtype}, {ldq_uop_11_dst_rtype}, {ldq_uop_10_dst_rtype}, {ldq_uop_9_dst_rtype}, {ldq_uop_8_dst_rtype}, {ldq_uop_7_dst_rtype}, {ldq_uop_6_dst_rtype}, {ldq_uop_5_dst_rtype}, {ldq_uop_4_dst_rtype}, {ldq_uop_3_dst_rtype}, {ldq_uop_2_dst_rtype}, {ldq_uop_1_dst_rtype}, {ldq_uop_0_dst_rtype}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_dst_rtype = _GEN_171[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_172 = {{ldq_uop_15_lrs1_rtype}, {ldq_uop_14_lrs1_rtype}, {ldq_uop_13_lrs1_rtype}, {ldq_uop_12_lrs1_rtype}, {ldq_uop_11_lrs1_rtype}, {ldq_uop_10_lrs1_rtype}, {ldq_uop_9_lrs1_rtype}, {ldq_uop_8_lrs1_rtype}, {ldq_uop_7_lrs1_rtype}, {ldq_uop_6_lrs1_rtype}, {ldq_uop_5_lrs1_rtype}, {ldq_uop_4_lrs1_rtype}, {ldq_uop_3_lrs1_rtype}, {ldq_uop_2_lrs1_rtype}, {ldq_uop_1_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs1_rtype = _GEN_172[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_173 = {{ldq_uop_15_lrs2_rtype}, {ldq_uop_14_lrs2_rtype}, {ldq_uop_13_lrs2_rtype}, {ldq_uop_12_lrs2_rtype}, {ldq_uop_11_lrs2_rtype}, {ldq_uop_10_lrs2_rtype}, {ldq_uop_9_lrs2_rtype}, {ldq_uop_8_lrs2_rtype}, {ldq_uop_7_lrs2_rtype}, {ldq_uop_6_lrs2_rtype}, {ldq_uop_5_lrs2_rtype}, {ldq_uop_4_lrs2_rtype}, {ldq_uop_3_lrs2_rtype}, {ldq_uop_2_lrs2_rtype}, {ldq_uop_1_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs2_rtype = _GEN_173[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_174 = {{ldq_uop_15_frs3_en}, {ldq_uop_14_frs3_en}, {ldq_uop_13_frs3_en}, {ldq_uop_12_frs3_en}, {ldq_uop_11_frs3_en}, {ldq_uop_10_frs3_en}, {ldq_uop_9_frs3_en}, {ldq_uop_8_frs3_en}, {ldq_uop_7_frs3_en}, {ldq_uop_6_frs3_en}, {ldq_uop_5_frs3_en}, {ldq_uop_4_frs3_en}, {ldq_uop_3_frs3_en}, {ldq_uop_2_frs3_en}, {ldq_uop_1_frs3_en}, {ldq_uop_0_frs3_en}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_frs3_en = _GEN_174[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_175 = {{ldq_uop_15_fcn_dw}, {ldq_uop_14_fcn_dw}, {ldq_uop_13_fcn_dw}, {ldq_uop_12_fcn_dw}, {ldq_uop_11_fcn_dw}, {ldq_uop_10_fcn_dw}, {ldq_uop_9_fcn_dw}, {ldq_uop_8_fcn_dw}, {ldq_uop_7_fcn_dw}, {ldq_uop_6_fcn_dw}, {ldq_uop_5_fcn_dw}, {ldq_uop_4_fcn_dw}, {ldq_uop_3_fcn_dw}, {ldq_uop_2_fcn_dw}, {ldq_uop_1_fcn_dw}, {ldq_uop_0_fcn_dw}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fcn_dw = _GEN_175[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][4:0] _GEN_176 = {{ldq_uop_15_fcn_op}, {ldq_uop_14_fcn_op}, {ldq_uop_13_fcn_op}, {ldq_uop_12_fcn_op}, {ldq_uop_11_fcn_op}, {ldq_uop_10_fcn_op}, {ldq_uop_9_fcn_op}, {ldq_uop_8_fcn_op}, {ldq_uop_7_fcn_op}, {ldq_uop_6_fcn_op}, {ldq_uop_5_fcn_op}, {ldq_uop_4_fcn_op}, {ldq_uop_3_fcn_op}, {ldq_uop_2_fcn_op}, {ldq_uop_1_fcn_op}, {ldq_uop_0_fcn_op}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fcn_op = _GEN_176[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_177 = {{ldq_uop_15_fp_val}, {ldq_uop_14_fp_val}, {ldq_uop_13_fp_val}, {ldq_uop_12_fp_val}, {ldq_uop_11_fp_val}, {ldq_uop_10_fp_val}, {ldq_uop_9_fp_val}, {ldq_uop_8_fp_val}, {ldq_uop_7_fp_val}, {ldq_uop_6_fp_val}, {ldq_uop_5_fp_val}, {ldq_uop_4_fp_val}, {ldq_uop_3_fp_val}, {ldq_uop_2_fp_val}, {ldq_uop_1_fp_val}, {ldq_uop_0_fp_val}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_val = _GEN_177[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][2:0] _GEN_178 = {{ldq_uop_15_fp_rm}, {ldq_uop_14_fp_rm}, {ldq_uop_13_fp_rm}, {ldq_uop_12_fp_rm}, {ldq_uop_11_fp_rm}, {ldq_uop_10_fp_rm}, {ldq_uop_9_fp_rm}, {ldq_uop_8_fp_rm}, {ldq_uop_7_fp_rm}, {ldq_uop_6_fp_rm}, {ldq_uop_5_fp_rm}, {ldq_uop_4_fp_rm}, {ldq_uop_3_fp_rm}, {ldq_uop_2_fp_rm}, {ldq_uop_1_fp_rm}, {ldq_uop_0_fp_rm}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_rm = _GEN_178[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_179 = {{ldq_uop_15_fp_typ}, {ldq_uop_14_fp_typ}, {ldq_uop_13_fp_typ}, {ldq_uop_12_fp_typ}, {ldq_uop_11_fp_typ}, {ldq_uop_10_fp_typ}, {ldq_uop_9_fp_typ}, {ldq_uop_8_fp_typ}, {ldq_uop_7_fp_typ}, {ldq_uop_6_fp_typ}, {ldq_uop_5_fp_typ}, {ldq_uop_4_fp_typ}, {ldq_uop_3_fp_typ}, {ldq_uop_2_fp_typ}, {ldq_uop_1_fp_typ}, {ldq_uop_0_fp_typ}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_typ = _GEN_179[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_180 = {{ldq_uop_15_xcpt_pf_if}, {ldq_uop_14_xcpt_pf_if}, {ldq_uop_13_xcpt_pf_if}, {ldq_uop_12_xcpt_pf_if}, {ldq_uop_11_xcpt_pf_if}, {ldq_uop_10_xcpt_pf_if}, {ldq_uop_9_xcpt_pf_if}, {ldq_uop_8_xcpt_pf_if}, {ldq_uop_7_xcpt_pf_if}, {ldq_uop_6_xcpt_pf_if}, {ldq_uop_5_xcpt_pf_if}, {ldq_uop_4_xcpt_pf_if}, {ldq_uop_3_xcpt_pf_if}, {ldq_uop_2_xcpt_pf_if}, {ldq_uop_1_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_xcpt_pf_if = _GEN_180[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_181 = {{ldq_uop_15_xcpt_ae_if}, {ldq_uop_14_xcpt_ae_if}, {ldq_uop_13_xcpt_ae_if}, {ldq_uop_12_xcpt_ae_if}, {ldq_uop_11_xcpt_ae_if}, {ldq_uop_10_xcpt_ae_if}, {ldq_uop_9_xcpt_ae_if}, {ldq_uop_8_xcpt_ae_if}, {ldq_uop_7_xcpt_ae_if}, {ldq_uop_6_xcpt_ae_if}, {ldq_uop_5_xcpt_ae_if}, {ldq_uop_4_xcpt_ae_if}, {ldq_uop_3_xcpt_ae_if}, {ldq_uop_2_xcpt_ae_if}, {ldq_uop_1_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_xcpt_ae_if = _GEN_181[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_182 = {{ldq_uop_15_xcpt_ma_if}, {ldq_uop_14_xcpt_ma_if}, {ldq_uop_13_xcpt_ma_if}, {ldq_uop_12_xcpt_ma_if}, {ldq_uop_11_xcpt_ma_if}, {ldq_uop_10_xcpt_ma_if}, {ldq_uop_9_xcpt_ma_if}, {ldq_uop_8_xcpt_ma_if}, {ldq_uop_7_xcpt_ma_if}, {ldq_uop_6_xcpt_ma_if}, {ldq_uop_5_xcpt_ma_if}, {ldq_uop_4_xcpt_ma_if}, {ldq_uop_3_xcpt_ma_if}, {ldq_uop_2_xcpt_ma_if}, {ldq_uop_1_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_xcpt_ma_if = _GEN_182[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_183 = {{ldq_uop_15_bp_debug_if}, {ldq_uop_14_bp_debug_if}, {ldq_uop_13_bp_debug_if}, {ldq_uop_12_bp_debug_if}, {ldq_uop_11_bp_debug_if}, {ldq_uop_10_bp_debug_if}, {ldq_uop_9_bp_debug_if}, {ldq_uop_8_bp_debug_if}, {ldq_uop_7_bp_debug_if}, {ldq_uop_6_bp_debug_if}, {ldq_uop_5_bp_debug_if}, {ldq_uop_4_bp_debug_if}, {ldq_uop_3_bp_debug_if}, {ldq_uop_2_bp_debug_if}, {ldq_uop_1_bp_debug_if}, {ldq_uop_0_bp_debug_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_bp_debug_if = _GEN_183[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_184 = {{ldq_uop_15_bp_xcpt_if}, {ldq_uop_14_bp_xcpt_if}, {ldq_uop_13_bp_xcpt_if}, {ldq_uop_12_bp_xcpt_if}, {ldq_uop_11_bp_xcpt_if}, {ldq_uop_10_bp_xcpt_if}, {ldq_uop_9_bp_xcpt_if}, {ldq_uop_8_bp_xcpt_if}, {ldq_uop_7_bp_xcpt_if}, {ldq_uop_6_bp_xcpt_if}, {ldq_uop_5_bp_xcpt_if}, {ldq_uop_4_bp_xcpt_if}, {ldq_uop_3_bp_xcpt_if}, {ldq_uop_2_bp_xcpt_if}, {ldq_uop_1_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_bp_xcpt_if = _GEN_184[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][2:0] _GEN_185 = {{ldq_uop_15_debug_fsrc}, {ldq_uop_14_debug_fsrc}, {ldq_uop_13_debug_fsrc}, {ldq_uop_12_debug_fsrc}, {ldq_uop_11_debug_fsrc}, {ldq_uop_10_debug_fsrc}, {ldq_uop_9_debug_fsrc}, {ldq_uop_8_debug_fsrc}, {ldq_uop_7_debug_fsrc}, {ldq_uop_6_debug_fsrc}, {ldq_uop_5_debug_fsrc}, {ldq_uop_4_debug_fsrc}, {ldq_uop_3_debug_fsrc}, {ldq_uop_2_debug_fsrc}, {ldq_uop_1_debug_fsrc}, {ldq_uop_0_debug_fsrc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_fsrc = _GEN_185[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][2:0] _GEN_186 = {{ldq_uop_15_debug_tsrc}, {ldq_uop_14_debug_tsrc}, {ldq_uop_13_debug_tsrc}, {ldq_uop_12_debug_tsrc}, {ldq_uop_11_debug_tsrc}, {ldq_uop_10_debug_tsrc}, {ldq_uop_9_debug_tsrc}, {ldq_uop_8_debug_tsrc}, {ldq_uop_7_debug_tsrc}, {ldq_uop_6_debug_tsrc}, {ldq_uop_5_debug_tsrc}, {ldq_uop_4_debug_tsrc}, {ldq_uop_3_debug_tsrc}, {ldq_uop_2_debug_tsrc}, {ldq_uop_1_debug_tsrc}, {ldq_uop_0_debug_tsrc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_tsrc = _GEN_186[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_187 = {{ldq_addr_15_valid}, {ldq_addr_14_valid}, {ldq_addr_13_valid}, {ldq_addr_12_valid}, {ldq_addr_11_valid}, {ldq_addr_10_valid}, {ldq_addr_9_valid}, {ldq_addr_8_valid}, {ldq_addr_7_valid}, {ldq_addr_6_valid}, {ldq_addr_5_valid}, {ldq_addr_4_valid}, {ldq_addr_3_valid}, {ldq_addr_2_valid}, {ldq_addr_1_valid}, {ldq_addr_0_valid}}; // @[lsu.scala:220:36, :236:32] assign ldq_incoming_e_e_bits_addr_valid = _GEN_187[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :236:32, :321:49] wire [15:0][39:0] _GEN_188 = {{ldq_addr_15_bits}, {ldq_addr_14_bits}, {ldq_addr_13_bits}, {ldq_addr_12_bits}, {ldq_addr_11_bits}, {ldq_addr_10_bits}, {ldq_addr_9_bits}, {ldq_addr_8_bits}, {ldq_addr_7_bits}, {ldq_addr_6_bits}, {ldq_addr_5_bits}, {ldq_addr_4_bits}, {ldq_addr_3_bits}, {ldq_addr_2_bits}, {ldq_addr_1_bits}, {ldq_addr_0_bits}}; // @[lsu.scala:220:36, :236:32] assign ldq_incoming_e_e_bits_addr_bits = _GEN_188[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :236:32, :321:49] wire [15:0] _GEN_189 = {{ldq_addr_is_virtual_15}, {ldq_addr_is_virtual_14}, {ldq_addr_is_virtual_13}, {ldq_addr_is_virtual_12}, {ldq_addr_is_virtual_11}, {ldq_addr_is_virtual_10}, {ldq_addr_is_virtual_9}, {ldq_addr_is_virtual_8}, {ldq_addr_is_virtual_7}, {ldq_addr_is_virtual_6}, {ldq_addr_is_virtual_5}, {ldq_addr_is_virtual_4}, {ldq_addr_is_virtual_3}, {ldq_addr_is_virtual_2}, {ldq_addr_is_virtual_1}, {ldq_addr_is_virtual_0}}; // @[lsu.scala:221:36, :237:32] assign ldq_incoming_e_e_bits_addr_is_virtual = _GEN_189[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :237:32, :321:49] wire [15:0] _GEN_190 = {{ldq_addr_is_uncacheable_15}, {ldq_addr_is_uncacheable_14}, {ldq_addr_is_uncacheable_13}, {ldq_addr_is_uncacheable_12}, {ldq_addr_is_uncacheable_11}, {ldq_addr_is_uncacheable_10}, {ldq_addr_is_uncacheable_9}, {ldq_addr_is_uncacheable_8}, {ldq_addr_is_uncacheable_7}, {ldq_addr_is_uncacheable_6}, {ldq_addr_is_uncacheable_5}, {ldq_addr_is_uncacheable_4}, {ldq_addr_is_uncacheable_3}, {ldq_addr_is_uncacheable_2}, {ldq_addr_is_uncacheable_1}, {ldq_addr_is_uncacheable_0}}; // @[lsu.scala:222:36, :238:32] assign ldq_incoming_e_e_bits_addr_is_uncacheable = _GEN_190[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :238:32, :321:49] wire [15:0] _GEN_191 = {{ldq_executed_15}, {ldq_executed_14}, {ldq_executed_13}, {ldq_executed_12}, {ldq_executed_11}, {ldq_executed_10}, {ldq_executed_9}, {ldq_executed_8}, {ldq_executed_7}, {ldq_executed_6}, {ldq_executed_5}, {ldq_executed_4}, {ldq_executed_3}, {ldq_executed_2}, {ldq_executed_1}, {ldq_executed_0}}; // @[lsu.scala:223:36, :239:32] assign ldq_incoming_e_e_bits_executed = _GEN_191[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :239:32, :321:49] wire [15:0] _GEN_192 = {{ldq_succeeded_15}, {ldq_succeeded_14}, {ldq_succeeded_13}, {ldq_succeeded_12}, {ldq_succeeded_11}, {ldq_succeeded_10}, {ldq_succeeded_9}, {ldq_succeeded_8}, {ldq_succeeded_7}, {ldq_succeeded_6}, {ldq_succeeded_5}, {ldq_succeeded_4}, {ldq_succeeded_3}, {ldq_succeeded_2}, {ldq_succeeded_1}, {ldq_succeeded_0}}; // @[lsu.scala:224:36, :240:32] assign ldq_incoming_e_e_bits_succeeded = _GEN_192[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :240:32, :321:49] wire [15:0] _GEN_193 = {{ldq_order_fail_15}, {ldq_order_fail_14}, {ldq_order_fail_13}, {ldq_order_fail_12}, {ldq_order_fail_11}, {ldq_order_fail_10}, {ldq_order_fail_9}, {ldq_order_fail_8}, {ldq_order_fail_7}, {ldq_order_fail_6}, {ldq_order_fail_5}, {ldq_order_fail_4}, {ldq_order_fail_3}, {ldq_order_fail_2}, {ldq_order_fail_1}, {ldq_order_fail_0}}; // @[lsu.scala:225:36, :241:32] assign ldq_incoming_e_e_bits_order_fail = _GEN_193[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :241:32, :321:49] wire [15:0] _GEN_194 = {{ldq_observed_15}, {ldq_observed_14}, {ldq_observed_13}, {ldq_observed_12}, {ldq_observed_11}, {ldq_observed_10}, {ldq_observed_9}, {ldq_observed_8}, {ldq_observed_7}, {ldq_observed_6}, {ldq_observed_5}, {ldq_observed_4}, {ldq_observed_3}, {ldq_observed_2}, {ldq_observed_1}, {ldq_observed_0}}; // @[lsu.scala:226:36, :242:32] assign ldq_incoming_e_e_bits_observed = _GEN_194[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :242:32, :321:49] wire [15:0][15:0] _GEN_195 = {{ldq_st_dep_mask_15}, {ldq_st_dep_mask_14}, {ldq_st_dep_mask_13}, {ldq_st_dep_mask_12}, {ldq_st_dep_mask_11}, {ldq_st_dep_mask_10}, {ldq_st_dep_mask_9}, {ldq_st_dep_mask_8}, {ldq_st_dep_mask_7}, {ldq_st_dep_mask_6}, {ldq_st_dep_mask_5}, {ldq_st_dep_mask_4}, {ldq_st_dep_mask_3}, {ldq_st_dep_mask_2}, {ldq_st_dep_mask_1}, {ldq_st_dep_mask_0}}; // @[lsu.scala:227:36, :243:32] assign ldq_incoming_e_e_bits_st_dep_mask = _GEN_195[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :243:32, :321:49] wire [15:0][7:0] _GEN_196 = {{ldq_ld_byte_mask_15}, {ldq_ld_byte_mask_14}, {ldq_ld_byte_mask_13}, {ldq_ld_byte_mask_12}, {ldq_ld_byte_mask_11}, {ldq_ld_byte_mask_10}, {ldq_ld_byte_mask_9}, {ldq_ld_byte_mask_8}, {ldq_ld_byte_mask_7}, {ldq_ld_byte_mask_6}, {ldq_ld_byte_mask_5}, {ldq_ld_byte_mask_4}, {ldq_ld_byte_mask_3}, {ldq_ld_byte_mask_2}, {ldq_ld_byte_mask_1}, {ldq_ld_byte_mask_0}}; // @[lsu.scala:228:36, :244:32] assign ldq_incoming_e_e_bits_ld_byte_mask = _GEN_196[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :244:32, :321:49] wire [15:0] _GEN_197 = {{ldq_forward_std_val_15}, {ldq_forward_std_val_14}, {ldq_forward_std_val_13}, {ldq_forward_std_val_12}, {ldq_forward_std_val_11}, {ldq_forward_std_val_10}, {ldq_forward_std_val_9}, {ldq_forward_std_val_8}, {ldq_forward_std_val_7}, {ldq_forward_std_val_6}, {ldq_forward_std_val_5}, {ldq_forward_std_val_4}, {ldq_forward_std_val_3}, {ldq_forward_std_val_2}, {ldq_forward_std_val_1}, {ldq_forward_std_val_0}}; // @[lsu.scala:229:36, :245:32] assign ldq_incoming_e_e_bits_forward_std_val = _GEN_197[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :245:32, :321:49] wire [15:0][3:0] _GEN_198 = {{ldq_forward_stq_idx_15}, {ldq_forward_stq_idx_14}, {ldq_forward_stq_idx_13}, {ldq_forward_stq_idx_12}, {ldq_forward_stq_idx_11}, {ldq_forward_stq_idx_10}, {ldq_forward_stq_idx_9}, {ldq_forward_stq_idx_8}, {ldq_forward_stq_idx_7}, {ldq_forward_stq_idx_6}, {ldq_forward_stq_idx_5}, {ldq_forward_stq_idx_4}, {ldq_forward_stq_idx_3}, {ldq_forward_stq_idx_2}, {ldq_forward_stq_idx_1}, {ldq_forward_stq_idx_0}}; // @[lsu.scala:230:36, :246:32] assign ldq_incoming_e_e_bits_forward_stq_idx = _GEN_198[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :246:32, :321:49] wire [15:0][63:0] _GEN_199 = {{ldq_debug_wb_data_15}, {ldq_debug_wb_data_14}, {ldq_debug_wb_data_13}, {ldq_debug_wb_data_12}, {ldq_debug_wb_data_11}, {ldq_debug_wb_data_10}, {ldq_debug_wb_data_9}, {ldq_debug_wb_data_8}, {ldq_debug_wb_data_7}, {ldq_debug_wb_data_6}, {ldq_debug_wb_data_5}, {ldq_debug_wb_data_4}, {ldq_debug_wb_data_3}, {ldq_debug_wb_data_2}, {ldq_debug_wb_data_1}, {ldq_debug_wb_data_0}}; // @[lsu.scala:231:36, :247:32] assign ldq_incoming_e_e_bits_debug_wb_data = _GEN_199[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :247:32, :321:49] wire ldq_incoming_e_0_valid = _ldq_incoming_e_WIRE_valid; // @[lsu.scala:321:49, :501:48] wire [31:0] ldq_incoming_e_0_bits_uop_inst = _ldq_incoming_e_WIRE_bits_uop_inst; // @[lsu.scala:321:49, :501:48] wire [31:0] ldq_incoming_e_0_bits_uop_debug_inst = _ldq_incoming_e_WIRE_bits_uop_debug_inst; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_rvc = _ldq_incoming_e_WIRE_bits_uop_is_rvc; // @[lsu.scala:321:49, :501:48] wire [39:0] ldq_incoming_e_0_bits_uop_debug_pc = _ldq_incoming_e_WIRE_bits_uop_debug_pc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_0 = _ldq_incoming_e_WIRE_bits_uop_iq_type_0; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_1 = _ldq_incoming_e_WIRE_bits_uop_iq_type_1; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_2 = _ldq_incoming_e_WIRE_bits_uop_iq_type_2; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_3 = _ldq_incoming_e_WIRE_bits_uop_iq_type_3; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_0 = _ldq_incoming_e_WIRE_bits_uop_fu_code_0; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_1 = _ldq_incoming_e_WIRE_bits_uop_fu_code_1; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_2 = _ldq_incoming_e_WIRE_bits_uop_fu_code_2; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_3 = _ldq_incoming_e_WIRE_bits_uop_fu_code_3; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_4 = _ldq_incoming_e_WIRE_bits_uop_fu_code_4; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_5 = _ldq_incoming_e_WIRE_bits_uop_fu_code_5; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_6 = _ldq_incoming_e_WIRE_bits_uop_fu_code_6; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_7 = _ldq_incoming_e_WIRE_bits_uop_fu_code_7; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_8 = _ldq_incoming_e_WIRE_bits_uop_fu_code_8; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_9 = _ldq_incoming_e_WIRE_bits_uop_fu_code_9; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_issued = _ldq_incoming_e_WIRE_bits_uop_iw_issued; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_issued_partial_agen = _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen = _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_iw_p1_speculative_child = _ldq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_iw_p2_speculative_child = _ldq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint = _ldq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint = _ldq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint = _ldq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_dis_col_sel = _ldq_incoming_e_WIRE_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :501:48] wire [11:0] ldq_incoming_e_0_bits_uop_br_mask = _ldq_incoming_e_WIRE_bits_uop_br_mask; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_uop_br_tag = _ldq_incoming_e_WIRE_bits_uop_br_tag; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_uop_br_type = _ldq_incoming_e_WIRE_bits_uop_br_type; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_sfb = _ldq_incoming_e_WIRE_bits_uop_is_sfb; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_fence = _ldq_incoming_e_WIRE_bits_uop_is_fence; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_fencei = _ldq_incoming_e_WIRE_bits_uop_is_fencei; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_sfence = _ldq_incoming_e_WIRE_bits_uop_is_sfence; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_amo = _ldq_incoming_e_WIRE_bits_uop_is_amo; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_eret = _ldq_incoming_e_WIRE_bits_uop_is_eret; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_sys_pc2epc = _ldq_incoming_e_WIRE_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_rocc = _ldq_incoming_e_WIRE_bits_uop_is_rocc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_mov = _ldq_incoming_e_WIRE_bits_uop_is_mov; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_ftq_idx = _ldq_incoming_e_WIRE_bits_uop_ftq_idx; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_edge_inst = _ldq_incoming_e_WIRE_bits_uop_edge_inst; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_pc_lob = _ldq_incoming_e_WIRE_bits_uop_pc_lob; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_taken = _ldq_incoming_e_WIRE_bits_uop_taken; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_imm_rename = _ldq_incoming_e_WIRE_bits_uop_imm_rename; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_imm_sel = _ldq_incoming_e_WIRE_bits_uop_imm_sel; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_pimm = _ldq_incoming_e_WIRE_bits_uop_pimm; // @[lsu.scala:321:49, :501:48] wire [19:0] ldq_incoming_e_0_bits_uop_imm_packed = _ldq_incoming_e_WIRE_bits_uop_imm_packed; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_op1_sel = _ldq_incoming_e_WIRE_bits_uop_op1_sel; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_op2_sel = _ldq_incoming_e_WIRE_bits_uop_op2_sel; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ldst = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_wen = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ren1 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ren2 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ren3 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_swap12 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_swap23 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_fromint = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_toint = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_fma = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_div = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_wflags = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_vec = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_rob_idx = _ldq_incoming_e_WIRE_bits_uop_rob_idx; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_uop_ldq_idx = _ldq_incoming_e_WIRE_bits_uop_ldq_idx; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_uop_stq_idx = _ldq_incoming_e_WIRE_bits_uop_stq_idx; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_rxq_idx = _ldq_incoming_e_WIRE_bits_uop_rxq_idx; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_pdst = _ldq_incoming_e_WIRE_bits_uop_pdst; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_prs1 = _ldq_incoming_e_WIRE_bits_uop_prs1; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_prs2 = _ldq_incoming_e_WIRE_bits_uop_prs2; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_prs3 = _ldq_incoming_e_WIRE_bits_uop_prs3; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_ppred = _ldq_incoming_e_WIRE_bits_uop_ppred; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_prs1_busy = _ldq_incoming_e_WIRE_bits_uop_prs1_busy; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_prs2_busy = _ldq_incoming_e_WIRE_bits_uop_prs2_busy; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_prs3_busy = _ldq_incoming_e_WIRE_bits_uop_prs3_busy; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_ppred_busy = _ldq_incoming_e_WIRE_bits_uop_ppred_busy; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_stale_pdst = _ldq_incoming_e_WIRE_bits_uop_stale_pdst; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_exception = _ldq_incoming_e_WIRE_bits_uop_exception; // @[lsu.scala:321:49, :501:48] wire [63:0] ldq_incoming_e_0_bits_uop_exc_cause = _ldq_incoming_e_WIRE_bits_uop_exc_cause; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_mem_cmd = _ldq_incoming_e_WIRE_bits_uop_mem_cmd; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_mem_size = _ldq_incoming_e_WIRE_bits_uop_mem_size; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_mem_signed = _ldq_incoming_e_WIRE_bits_uop_mem_signed; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_uses_ldq = _ldq_incoming_e_WIRE_bits_uop_uses_ldq; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_uses_stq = _ldq_incoming_e_WIRE_bits_uop_uses_stq; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_unique = _ldq_incoming_e_WIRE_bits_uop_is_unique; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_flush_on_commit = _ldq_incoming_e_WIRE_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_csr_cmd = _ldq_incoming_e_WIRE_bits_uop_csr_cmd; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_ldst_is_rs1 = _ldq_incoming_e_WIRE_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_ldst = _ldq_incoming_e_WIRE_bits_uop_ldst; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_lrs1 = _ldq_incoming_e_WIRE_bits_uop_lrs1; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_lrs2 = _ldq_incoming_e_WIRE_bits_uop_lrs2; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_lrs3 = _ldq_incoming_e_WIRE_bits_uop_lrs3; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_dst_rtype = _ldq_incoming_e_WIRE_bits_uop_dst_rtype; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_lrs1_rtype = _ldq_incoming_e_WIRE_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_lrs2_rtype = _ldq_incoming_e_WIRE_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_frs3_en = _ldq_incoming_e_WIRE_bits_uop_frs3_en; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fcn_dw = _ldq_incoming_e_WIRE_bits_uop_fcn_dw; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_fcn_op = _ldq_incoming_e_WIRE_bits_uop_fcn_op; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_val = _ldq_incoming_e_WIRE_bits_uop_fp_val; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_fp_rm = _ldq_incoming_e_WIRE_bits_uop_fp_rm; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_fp_typ = _ldq_incoming_e_WIRE_bits_uop_fp_typ; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_xcpt_pf_if = _ldq_incoming_e_WIRE_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_xcpt_ae_if = _ldq_incoming_e_WIRE_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_xcpt_ma_if = _ldq_incoming_e_WIRE_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_bp_debug_if = _ldq_incoming_e_WIRE_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_bp_xcpt_if = _ldq_incoming_e_WIRE_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_debug_fsrc = _ldq_incoming_e_WIRE_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_debug_tsrc = _ldq_incoming_e_WIRE_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_addr_valid = _ldq_incoming_e_WIRE_bits_addr_valid; // @[lsu.scala:321:49, :501:48] wire [39:0] ldq_incoming_e_0_bits_addr_bits = _ldq_incoming_e_WIRE_bits_addr_bits; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_addr_is_virtual = _ldq_incoming_e_WIRE_bits_addr_is_virtual; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_addr_is_uncacheable = _ldq_incoming_e_WIRE_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_executed = _ldq_incoming_e_WIRE_bits_executed; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_succeeded = _ldq_incoming_e_WIRE_bits_succeeded; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_order_fail = _ldq_incoming_e_WIRE_bits_order_fail; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_observed = _ldq_incoming_e_WIRE_bits_observed; // @[lsu.scala:321:49, :501:48] wire [15:0] ldq_incoming_e_0_bits_st_dep_mask = _ldq_incoming_e_WIRE_bits_st_dep_mask; // @[lsu.scala:321:49, :501:48] wire [7:0] ldq_incoming_e_0_bits_ld_byte_mask = _ldq_incoming_e_WIRE_bits_ld_byte_mask; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_forward_std_val = _ldq_incoming_e_WIRE_bits_forward_std_val; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_forward_stq_idx = _ldq_incoming_e_WIRE_bits_forward_stq_idx; // @[lsu.scala:321:49, :501:48] wire [63:0] ldq_incoming_e_0_bits_debug_wb_data = _ldq_incoming_e_WIRE_bits_debug_wb_data; // @[lsu.scala:321:49, :501:48] wire [31:0] mem_ldq_incoming_e_out_bits_uop_inst = ldq_incoming_e_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_ldq_incoming_e_out_bits_uop_debug_inst = ldq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_rvc = ldq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_ldq_incoming_e_out_bits_uop_debug_pc = ldq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_0 = ldq_incoming_e_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_1 = ldq_incoming_e_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_2 = ldq_incoming_e_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_3 = ldq_incoming_e_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_0 = ldq_incoming_e_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_1 = ldq_incoming_e_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_2 = ldq_incoming_e_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_3 = ldq_incoming_e_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_4 = ldq_incoming_e_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_5 = ldq_incoming_e_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_6 = ldq_incoming_e_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_7 = ldq_incoming_e_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_8 = ldq_incoming_e_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_9 = ldq_incoming_e_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_issued = ldq_incoming_e_0_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_agen = ldq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_dgen = ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_iw_p1_speculative_child = ldq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_iw_p2_speculative_child = ldq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p1_bypass_hint = ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p2_bypass_hint = ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p3_bypass_hint = ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_dis_col_sel = ldq_incoming_e_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_br_tag = ldq_incoming_e_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_br_type = ldq_incoming_e_0_bits_uop_br_type; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_sfb = ldq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_fence = ldq_incoming_e_0_bits_uop_is_fence; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_fencei = ldq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_sfence = ldq_incoming_e_0_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_amo = ldq_incoming_e_0_bits_uop_is_amo; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_eret = ldq_incoming_e_0_bits_uop_is_eret; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc = ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_rocc = ldq_incoming_e_0_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_mov = ldq_incoming_e_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ftq_idx = ldq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_edge_inst = ldq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_pc_lob = ldq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_taken = ldq_incoming_e_0_bits_uop_taken; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_imm_rename = ldq_incoming_e_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_imm_sel = ldq_incoming_e_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_pimm = ldq_incoming_e_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_ldq_incoming_e_out_bits_uop_imm_packed = ldq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_op1_sel = ldq_incoming_e_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_op2_sel = ldq_incoming_e_0_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ldst = ldq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wen = ldq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren1 = ldq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren2 = ldq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren3 = ldq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap12 = ldq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap23 = ldq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn = ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut = ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fromint = ldq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_toint = ldq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fastpipe = ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fma = ldq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_div = ldq_incoming_e_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_sqrt = ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wflags = ldq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_vec = ldq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_rob_idx = ldq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_ldq_idx = ldq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_stq_idx = ldq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_rxq_idx = ldq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_pdst = ldq_incoming_e_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs1 = ldq_incoming_e_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs2 = ldq_incoming_e_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs3 = ldq_incoming_e_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ppred = ldq_incoming_e_0_bits_uop_ppred; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_prs1_busy = ldq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_prs2_busy = ldq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_prs3_busy = ldq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_ppred_busy = ldq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_stale_pdst = ldq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_exception = ldq_incoming_e_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_ldq_incoming_e_out_bits_uop_exc_cause = ldq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_mem_cmd = ldq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_mem_size = ldq_incoming_e_0_bits_uop_mem_size; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_mem_signed = ldq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_uses_ldq = ldq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_uses_stq = ldq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_unique = ldq_incoming_e_0_bits_uop_is_unique; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_flush_on_commit = ldq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_csr_cmd = ldq_incoming_e_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1 = ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_ldst = ldq_incoming_e_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs1 = ldq_incoming_e_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs2 = ldq_incoming_e_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs3 = ldq_incoming_e_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_dst_rtype = ldq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs1_rtype = ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs2_rtype = ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_frs3_en = ldq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fcn_dw = ldq_incoming_e_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_fcn_op = ldq_incoming_e_0_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_val = ldq_incoming_e_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_fp_rm = ldq_incoming_e_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_fp_typ = ldq_incoming_e_0_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if = ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if = ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if = ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_bp_debug_if = ldq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if = ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_debug_fsrc = ldq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_debug_tsrc = ldq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_addr_valid = ldq_incoming_e_0_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_ldq_incoming_e_out_bits_addr_bits = ldq_incoming_e_0_bits_addr_bits; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_addr_is_virtual = ldq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_addr_is_uncacheable = ldq_incoming_e_0_bits_addr_is_uncacheable; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_executed = ldq_incoming_e_0_bits_executed; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_succeeded = ldq_incoming_e_0_bits_succeeded; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_order_fail = ldq_incoming_e_0_bits_order_fail; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_observed = ldq_incoming_e_0_bits_observed; // @[util.scala:114:23] wire [15:0] mem_ldq_incoming_e_out_bits_st_dep_mask = ldq_incoming_e_0_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] mem_ldq_incoming_e_out_bits_ld_byte_mask = ldq_incoming_e_0_bits_ld_byte_mask; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_forward_std_val = ldq_incoming_e_0_bits_forward_std_val; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_forward_stq_idx = ldq_incoming_e_0_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] mem_ldq_incoming_e_out_bits_debug_wb_data = ldq_incoming_e_0_bits_debug_wb_data; // @[util.scala:114:23] wire _stq_incoming_e_WIRE_valid = stq_incoming_e_e_valid; // @[lsu.scala:262:17, :504:48] wire [31:0] _stq_incoming_e_WIRE_bits_uop_inst = stq_incoming_e_e_bits_uop_inst; // @[lsu.scala:262:17, :504:48] wire [31:0] _stq_incoming_e_WIRE_bits_uop_debug_inst = stq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_rvc = stq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17, :504:48] wire [39:0] _stq_incoming_e_WIRE_bits_uop_debug_pc = stq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_0 = stq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_1 = stq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_2 = stq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_3 = stq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_0 = stq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_1 = stq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_2 = stq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_3 = stq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_4 = stq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_5 = stq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_6 = stq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_7 = stq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_8 = stq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_9 = stq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_issued = stq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen = stq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen = stq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child = stq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child = stq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint = stq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint = stq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint = stq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_dis_col_sel = stq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17, :504:48] wire [11:0] _stq_incoming_e_WIRE_bits_uop_br_mask = stq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:262:17, :504:48] wire [3:0] _stq_incoming_e_WIRE_bits_uop_br_tag = stq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:262:17, :504:48] wire [3:0] _stq_incoming_e_WIRE_bits_uop_br_type = stq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_sfb = stq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_fence = stq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_fencei = stq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_sfence = stq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_amo = stq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_eret = stq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_sys_pc2epc = stq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_rocc = stq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_mov = stq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_ftq_idx = stq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_edge_inst = stq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_pc_lob = stq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_taken = stq_incoming_e_e_bits_uop_taken; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_imm_rename = stq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_imm_sel = stq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_pimm = stq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:262:17, :504:48] wire [19:0] _stq_incoming_e_WIRE_bits_uop_imm_packed = stq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_op1_sel = stq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_op2_sel = stq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst = stq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wen = stq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1 = stq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2 = stq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3 = stq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12 = stq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23 = stq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn = stq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut = stq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint = stq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_toint = stq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe = stq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fma = stq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_div = stq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt = stq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags = stq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_vec = stq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_rob_idx = stq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17, :504:48] wire [3:0] _stq_incoming_e_WIRE_bits_uop_ldq_idx = stq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17, :504:48] wire [3:0] _stq_incoming_e_WIRE_bits_uop_stq_idx = stq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_rxq_idx = stq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_pdst = stq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_prs1 = stq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_prs2 = stq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_prs3 = stq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_ppred = stq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_prs1_busy = stq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_prs2_busy = stq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_prs3_busy = stq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_ppred_busy = stq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_stale_pdst = stq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_exception = stq_incoming_e_e_bits_uop_exception; // @[lsu.scala:262:17, :504:48] wire [63:0] _stq_incoming_e_WIRE_bits_uop_exc_cause = stq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_mem_cmd = stq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_mem_size = stq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_mem_signed = stq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_uses_ldq = stq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_uses_stq = stq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_unique = stq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_flush_on_commit = stq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_csr_cmd = stq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_ldst_is_rs1 = stq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_ldst = stq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_lrs1 = stq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_lrs2 = stq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_lrs3 = stq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_dst_rtype = stq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_lrs1_rtype = stq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_lrs2_rtype = stq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_frs3_en = stq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fcn_dw = stq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_fcn_op = stq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_val = stq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_fp_rm = stq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_fp_typ = stq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_xcpt_pf_if = stq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_xcpt_ae_if = stq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_xcpt_ma_if = stq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_bp_debug_if = stq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_bp_xcpt_if = stq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_debug_fsrc = stq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_debug_tsrc = stq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_addr_valid = stq_incoming_e_e_bits_addr_valid; // @[lsu.scala:262:17, :504:48] wire [39:0] _stq_incoming_e_WIRE_bits_addr_bits = stq_incoming_e_e_bits_addr_bits; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_addr_is_virtual = stq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_data_valid = stq_incoming_e_e_bits_data_valid; // @[lsu.scala:262:17, :504:48] wire [63:0] _stq_incoming_e_WIRE_bits_data_bits = stq_incoming_e_e_bits_data_bits; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_committed = stq_incoming_e_e_bits_committed; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_succeeded = stq_incoming_e_e_bits_succeeded; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_can_execute = stq_incoming_e_e_bits_can_execute; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_cleared = stq_incoming_e_e_bits_cleared; // @[lsu.scala:262:17, :504:48] wire [63:0] _stq_incoming_e_WIRE_bits_debug_wb_data = stq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:262:17, :504:48] assign stq_incoming_e_e_valid = _GEN_26[stq_incoming_idx_0]; // @[lsu.scala:262:17, :263:32, :321:49, :392:15] wire [15:0][31:0] _GEN_200 = {{stq_uop_15_inst}, {stq_uop_14_inst}, {stq_uop_13_inst}, {stq_uop_12_inst}, {stq_uop_11_inst}, {stq_uop_10_inst}, {stq_uop_9_inst}, {stq_uop_8_inst}, {stq_uop_7_inst}, {stq_uop_6_inst}, {stq_uop_5_inst}, {stq_uop_4_inst}, {stq_uop_3_inst}, {stq_uop_2_inst}, {stq_uop_1_inst}, {stq_uop_0_inst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_inst = _GEN_200[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][31:0] _GEN_201 = {{stq_uop_15_debug_inst}, {stq_uop_14_debug_inst}, {stq_uop_13_debug_inst}, {stq_uop_12_debug_inst}, {stq_uop_11_debug_inst}, {stq_uop_10_debug_inst}, {stq_uop_9_debug_inst}, {stq_uop_8_debug_inst}, {stq_uop_7_debug_inst}, {stq_uop_6_debug_inst}, {stq_uop_5_debug_inst}, {stq_uop_4_debug_inst}, {stq_uop_3_debug_inst}, {stq_uop_2_debug_inst}, {stq_uop_1_debug_inst}, {stq_uop_0_debug_inst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_inst = _GEN_201[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_202 = {{stq_uop_15_is_rvc}, {stq_uop_14_is_rvc}, {stq_uop_13_is_rvc}, {stq_uop_12_is_rvc}, {stq_uop_11_is_rvc}, {stq_uop_10_is_rvc}, {stq_uop_9_is_rvc}, {stq_uop_8_is_rvc}, {stq_uop_7_is_rvc}, {stq_uop_6_is_rvc}, {stq_uop_5_is_rvc}, {stq_uop_4_is_rvc}, {stq_uop_3_is_rvc}, {stq_uop_2_is_rvc}, {stq_uop_1_is_rvc}, {stq_uop_0_is_rvc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_rvc = _GEN_202[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][39:0] _GEN_203 = {{stq_uop_15_debug_pc}, {stq_uop_14_debug_pc}, {stq_uop_13_debug_pc}, {stq_uop_12_debug_pc}, {stq_uop_11_debug_pc}, {stq_uop_10_debug_pc}, {stq_uop_9_debug_pc}, {stq_uop_8_debug_pc}, {stq_uop_7_debug_pc}, {stq_uop_6_debug_pc}, {stq_uop_5_debug_pc}, {stq_uop_4_debug_pc}, {stq_uop_3_debug_pc}, {stq_uop_2_debug_pc}, {stq_uop_1_debug_pc}, {stq_uop_0_debug_pc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_pc = _GEN_203[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_204 = {{stq_uop_15_iq_type_0}, {stq_uop_14_iq_type_0}, {stq_uop_13_iq_type_0}, {stq_uop_12_iq_type_0}, {stq_uop_11_iq_type_0}, {stq_uop_10_iq_type_0}, {stq_uop_9_iq_type_0}, {stq_uop_8_iq_type_0}, {stq_uop_7_iq_type_0}, {stq_uop_6_iq_type_0}, {stq_uop_5_iq_type_0}, {stq_uop_4_iq_type_0}, {stq_uop_3_iq_type_0}, {stq_uop_2_iq_type_0}, {stq_uop_1_iq_type_0}, {stq_uop_0_iq_type_0}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_0 = _GEN_204[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_205 = {{stq_uop_15_iq_type_1}, {stq_uop_14_iq_type_1}, {stq_uop_13_iq_type_1}, {stq_uop_12_iq_type_1}, {stq_uop_11_iq_type_1}, {stq_uop_10_iq_type_1}, {stq_uop_9_iq_type_1}, {stq_uop_8_iq_type_1}, {stq_uop_7_iq_type_1}, {stq_uop_6_iq_type_1}, {stq_uop_5_iq_type_1}, {stq_uop_4_iq_type_1}, {stq_uop_3_iq_type_1}, {stq_uop_2_iq_type_1}, {stq_uop_1_iq_type_1}, {stq_uop_0_iq_type_1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_1 = _GEN_205[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_206 = {{stq_uop_15_iq_type_2}, {stq_uop_14_iq_type_2}, {stq_uop_13_iq_type_2}, {stq_uop_12_iq_type_2}, {stq_uop_11_iq_type_2}, {stq_uop_10_iq_type_2}, {stq_uop_9_iq_type_2}, {stq_uop_8_iq_type_2}, {stq_uop_7_iq_type_2}, {stq_uop_6_iq_type_2}, {stq_uop_5_iq_type_2}, {stq_uop_4_iq_type_2}, {stq_uop_3_iq_type_2}, {stq_uop_2_iq_type_2}, {stq_uop_1_iq_type_2}, {stq_uop_0_iq_type_2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_2 = _GEN_206[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_207 = {{stq_uop_15_iq_type_3}, {stq_uop_14_iq_type_3}, {stq_uop_13_iq_type_3}, {stq_uop_12_iq_type_3}, {stq_uop_11_iq_type_3}, {stq_uop_10_iq_type_3}, {stq_uop_9_iq_type_3}, {stq_uop_8_iq_type_3}, {stq_uop_7_iq_type_3}, {stq_uop_6_iq_type_3}, {stq_uop_5_iq_type_3}, {stq_uop_4_iq_type_3}, {stq_uop_3_iq_type_3}, {stq_uop_2_iq_type_3}, {stq_uop_1_iq_type_3}, {stq_uop_0_iq_type_3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_3 = _GEN_207[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_208 = {{stq_uop_15_fu_code_0}, {stq_uop_14_fu_code_0}, {stq_uop_13_fu_code_0}, {stq_uop_12_fu_code_0}, {stq_uop_11_fu_code_0}, {stq_uop_10_fu_code_0}, {stq_uop_9_fu_code_0}, {stq_uop_8_fu_code_0}, {stq_uop_7_fu_code_0}, {stq_uop_6_fu_code_0}, {stq_uop_5_fu_code_0}, {stq_uop_4_fu_code_0}, {stq_uop_3_fu_code_0}, {stq_uop_2_fu_code_0}, {stq_uop_1_fu_code_0}, {stq_uop_0_fu_code_0}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_0 = _GEN_208[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_209 = {{stq_uop_15_fu_code_1}, {stq_uop_14_fu_code_1}, {stq_uop_13_fu_code_1}, {stq_uop_12_fu_code_1}, {stq_uop_11_fu_code_1}, {stq_uop_10_fu_code_1}, {stq_uop_9_fu_code_1}, {stq_uop_8_fu_code_1}, {stq_uop_7_fu_code_1}, {stq_uop_6_fu_code_1}, {stq_uop_5_fu_code_1}, {stq_uop_4_fu_code_1}, {stq_uop_3_fu_code_1}, {stq_uop_2_fu_code_1}, {stq_uop_1_fu_code_1}, {stq_uop_0_fu_code_1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_1 = _GEN_209[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_210 = {{stq_uop_15_fu_code_2}, {stq_uop_14_fu_code_2}, {stq_uop_13_fu_code_2}, {stq_uop_12_fu_code_2}, {stq_uop_11_fu_code_2}, {stq_uop_10_fu_code_2}, {stq_uop_9_fu_code_2}, {stq_uop_8_fu_code_2}, {stq_uop_7_fu_code_2}, {stq_uop_6_fu_code_2}, {stq_uop_5_fu_code_2}, {stq_uop_4_fu_code_2}, {stq_uop_3_fu_code_2}, {stq_uop_2_fu_code_2}, {stq_uop_1_fu_code_2}, {stq_uop_0_fu_code_2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_2 = _GEN_210[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_211 = {{stq_uop_15_fu_code_3}, {stq_uop_14_fu_code_3}, {stq_uop_13_fu_code_3}, {stq_uop_12_fu_code_3}, {stq_uop_11_fu_code_3}, {stq_uop_10_fu_code_3}, {stq_uop_9_fu_code_3}, {stq_uop_8_fu_code_3}, {stq_uop_7_fu_code_3}, {stq_uop_6_fu_code_3}, {stq_uop_5_fu_code_3}, {stq_uop_4_fu_code_3}, {stq_uop_3_fu_code_3}, {stq_uop_2_fu_code_3}, {stq_uop_1_fu_code_3}, {stq_uop_0_fu_code_3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_3 = _GEN_211[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_212 = {{stq_uop_15_fu_code_4}, {stq_uop_14_fu_code_4}, {stq_uop_13_fu_code_4}, {stq_uop_12_fu_code_4}, {stq_uop_11_fu_code_4}, {stq_uop_10_fu_code_4}, {stq_uop_9_fu_code_4}, {stq_uop_8_fu_code_4}, {stq_uop_7_fu_code_4}, {stq_uop_6_fu_code_4}, {stq_uop_5_fu_code_4}, {stq_uop_4_fu_code_4}, {stq_uop_3_fu_code_4}, {stq_uop_2_fu_code_4}, {stq_uop_1_fu_code_4}, {stq_uop_0_fu_code_4}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_4 = _GEN_212[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_213 = {{stq_uop_15_fu_code_5}, {stq_uop_14_fu_code_5}, {stq_uop_13_fu_code_5}, {stq_uop_12_fu_code_5}, {stq_uop_11_fu_code_5}, {stq_uop_10_fu_code_5}, {stq_uop_9_fu_code_5}, {stq_uop_8_fu_code_5}, {stq_uop_7_fu_code_5}, {stq_uop_6_fu_code_5}, {stq_uop_5_fu_code_5}, {stq_uop_4_fu_code_5}, {stq_uop_3_fu_code_5}, {stq_uop_2_fu_code_5}, {stq_uop_1_fu_code_5}, {stq_uop_0_fu_code_5}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_5 = _GEN_213[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_214 = {{stq_uop_15_fu_code_6}, {stq_uop_14_fu_code_6}, {stq_uop_13_fu_code_6}, {stq_uop_12_fu_code_6}, {stq_uop_11_fu_code_6}, {stq_uop_10_fu_code_6}, {stq_uop_9_fu_code_6}, {stq_uop_8_fu_code_6}, {stq_uop_7_fu_code_6}, {stq_uop_6_fu_code_6}, {stq_uop_5_fu_code_6}, {stq_uop_4_fu_code_6}, {stq_uop_3_fu_code_6}, {stq_uop_2_fu_code_6}, {stq_uop_1_fu_code_6}, {stq_uop_0_fu_code_6}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_6 = _GEN_214[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_215 = {{stq_uop_15_fu_code_7}, {stq_uop_14_fu_code_7}, {stq_uop_13_fu_code_7}, {stq_uop_12_fu_code_7}, {stq_uop_11_fu_code_7}, {stq_uop_10_fu_code_7}, {stq_uop_9_fu_code_7}, {stq_uop_8_fu_code_7}, {stq_uop_7_fu_code_7}, {stq_uop_6_fu_code_7}, {stq_uop_5_fu_code_7}, {stq_uop_4_fu_code_7}, {stq_uop_3_fu_code_7}, {stq_uop_2_fu_code_7}, {stq_uop_1_fu_code_7}, {stq_uop_0_fu_code_7}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_7 = _GEN_215[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_216 = {{stq_uop_15_fu_code_8}, {stq_uop_14_fu_code_8}, {stq_uop_13_fu_code_8}, {stq_uop_12_fu_code_8}, {stq_uop_11_fu_code_8}, {stq_uop_10_fu_code_8}, {stq_uop_9_fu_code_8}, {stq_uop_8_fu_code_8}, {stq_uop_7_fu_code_8}, {stq_uop_6_fu_code_8}, {stq_uop_5_fu_code_8}, {stq_uop_4_fu_code_8}, {stq_uop_3_fu_code_8}, {stq_uop_2_fu_code_8}, {stq_uop_1_fu_code_8}, {stq_uop_0_fu_code_8}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_8 = _GEN_216[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_217 = {{stq_uop_15_fu_code_9}, {stq_uop_14_fu_code_9}, {stq_uop_13_fu_code_9}, {stq_uop_12_fu_code_9}, {stq_uop_11_fu_code_9}, {stq_uop_10_fu_code_9}, {stq_uop_9_fu_code_9}, {stq_uop_8_fu_code_9}, {stq_uop_7_fu_code_9}, {stq_uop_6_fu_code_9}, {stq_uop_5_fu_code_9}, {stq_uop_4_fu_code_9}, {stq_uop_3_fu_code_9}, {stq_uop_2_fu_code_9}, {stq_uop_1_fu_code_9}, {stq_uop_0_fu_code_9}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_9 = _GEN_217[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_218 = {{stq_uop_15_iw_issued}, {stq_uop_14_iw_issued}, {stq_uop_13_iw_issued}, {stq_uop_12_iw_issued}, {stq_uop_11_iw_issued}, {stq_uop_10_iw_issued}, {stq_uop_9_iw_issued}, {stq_uop_8_iw_issued}, {stq_uop_7_iw_issued}, {stq_uop_6_iw_issued}, {stq_uop_5_iw_issued}, {stq_uop_4_iw_issued}, {stq_uop_3_iw_issued}, {stq_uop_2_iw_issued}, {stq_uop_1_iw_issued}, {stq_uop_0_iw_issued}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_issued = _GEN_218[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_219 = {{stq_uop_15_iw_issued_partial_agen}, {stq_uop_14_iw_issued_partial_agen}, {stq_uop_13_iw_issued_partial_agen}, {stq_uop_12_iw_issued_partial_agen}, {stq_uop_11_iw_issued_partial_agen}, {stq_uop_10_iw_issued_partial_agen}, {stq_uop_9_iw_issued_partial_agen}, {stq_uop_8_iw_issued_partial_agen}, {stq_uop_7_iw_issued_partial_agen}, {stq_uop_6_iw_issued_partial_agen}, {stq_uop_5_iw_issued_partial_agen}, {stq_uop_4_iw_issued_partial_agen}, {stq_uop_3_iw_issued_partial_agen}, {stq_uop_2_iw_issued_partial_agen}, {stq_uop_1_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_issued_partial_agen = _GEN_219[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_220 = {{stq_uop_15_iw_issued_partial_dgen}, {stq_uop_14_iw_issued_partial_dgen}, {stq_uop_13_iw_issued_partial_dgen}, {stq_uop_12_iw_issued_partial_dgen}, {stq_uop_11_iw_issued_partial_dgen}, {stq_uop_10_iw_issued_partial_dgen}, {stq_uop_9_iw_issued_partial_dgen}, {stq_uop_8_iw_issued_partial_dgen}, {stq_uop_7_iw_issued_partial_dgen}, {stq_uop_6_iw_issued_partial_dgen}, {stq_uop_5_iw_issued_partial_dgen}, {stq_uop_4_iw_issued_partial_dgen}, {stq_uop_3_iw_issued_partial_dgen}, {stq_uop_2_iw_issued_partial_dgen}, {stq_uop_1_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_issued_partial_dgen = _GEN_220[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_221 = {{stq_uop_15_iw_p1_speculative_child}, {stq_uop_14_iw_p1_speculative_child}, {stq_uop_13_iw_p1_speculative_child}, {stq_uop_12_iw_p1_speculative_child}, {stq_uop_11_iw_p1_speculative_child}, {stq_uop_10_iw_p1_speculative_child}, {stq_uop_9_iw_p1_speculative_child}, {stq_uop_8_iw_p1_speculative_child}, {stq_uop_7_iw_p1_speculative_child}, {stq_uop_6_iw_p1_speculative_child}, {stq_uop_5_iw_p1_speculative_child}, {stq_uop_4_iw_p1_speculative_child}, {stq_uop_3_iw_p1_speculative_child}, {stq_uop_2_iw_p1_speculative_child}, {stq_uop_1_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p1_speculative_child = _GEN_221[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_222 = {{stq_uop_15_iw_p2_speculative_child}, {stq_uop_14_iw_p2_speculative_child}, {stq_uop_13_iw_p2_speculative_child}, {stq_uop_12_iw_p2_speculative_child}, {stq_uop_11_iw_p2_speculative_child}, {stq_uop_10_iw_p2_speculative_child}, {stq_uop_9_iw_p2_speculative_child}, {stq_uop_8_iw_p2_speculative_child}, {stq_uop_7_iw_p2_speculative_child}, {stq_uop_6_iw_p2_speculative_child}, {stq_uop_5_iw_p2_speculative_child}, {stq_uop_4_iw_p2_speculative_child}, {stq_uop_3_iw_p2_speculative_child}, {stq_uop_2_iw_p2_speculative_child}, {stq_uop_1_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p2_speculative_child = _GEN_222[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_223 = {{stq_uop_15_iw_p1_bypass_hint}, {stq_uop_14_iw_p1_bypass_hint}, {stq_uop_13_iw_p1_bypass_hint}, {stq_uop_12_iw_p1_bypass_hint}, {stq_uop_11_iw_p1_bypass_hint}, {stq_uop_10_iw_p1_bypass_hint}, {stq_uop_9_iw_p1_bypass_hint}, {stq_uop_8_iw_p1_bypass_hint}, {stq_uop_7_iw_p1_bypass_hint}, {stq_uop_6_iw_p1_bypass_hint}, {stq_uop_5_iw_p1_bypass_hint}, {stq_uop_4_iw_p1_bypass_hint}, {stq_uop_3_iw_p1_bypass_hint}, {stq_uop_2_iw_p1_bypass_hint}, {stq_uop_1_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p1_bypass_hint = _GEN_223[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_224 = {{stq_uop_15_iw_p2_bypass_hint}, {stq_uop_14_iw_p2_bypass_hint}, {stq_uop_13_iw_p2_bypass_hint}, {stq_uop_12_iw_p2_bypass_hint}, {stq_uop_11_iw_p2_bypass_hint}, {stq_uop_10_iw_p2_bypass_hint}, {stq_uop_9_iw_p2_bypass_hint}, {stq_uop_8_iw_p2_bypass_hint}, {stq_uop_7_iw_p2_bypass_hint}, {stq_uop_6_iw_p2_bypass_hint}, {stq_uop_5_iw_p2_bypass_hint}, {stq_uop_4_iw_p2_bypass_hint}, {stq_uop_3_iw_p2_bypass_hint}, {stq_uop_2_iw_p2_bypass_hint}, {stq_uop_1_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p2_bypass_hint = _GEN_224[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_225 = {{stq_uop_15_iw_p3_bypass_hint}, {stq_uop_14_iw_p3_bypass_hint}, {stq_uop_13_iw_p3_bypass_hint}, {stq_uop_12_iw_p3_bypass_hint}, {stq_uop_11_iw_p3_bypass_hint}, {stq_uop_10_iw_p3_bypass_hint}, {stq_uop_9_iw_p3_bypass_hint}, {stq_uop_8_iw_p3_bypass_hint}, {stq_uop_7_iw_p3_bypass_hint}, {stq_uop_6_iw_p3_bypass_hint}, {stq_uop_5_iw_p3_bypass_hint}, {stq_uop_4_iw_p3_bypass_hint}, {stq_uop_3_iw_p3_bypass_hint}, {stq_uop_2_iw_p3_bypass_hint}, {stq_uop_1_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p3_bypass_hint = _GEN_225[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_226 = {{stq_uop_15_dis_col_sel}, {stq_uop_14_dis_col_sel}, {stq_uop_13_dis_col_sel}, {stq_uop_12_dis_col_sel}, {stq_uop_11_dis_col_sel}, {stq_uop_10_dis_col_sel}, {stq_uop_9_dis_col_sel}, {stq_uop_8_dis_col_sel}, {stq_uop_7_dis_col_sel}, {stq_uop_6_dis_col_sel}, {stq_uop_5_dis_col_sel}, {stq_uop_4_dis_col_sel}, {stq_uop_3_dis_col_sel}, {stq_uop_2_dis_col_sel}, {stq_uop_1_dis_col_sel}, {stq_uop_0_dis_col_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_dis_col_sel = _GEN_226[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][11:0] _GEN_227 = {{stq_uop_15_br_mask}, {stq_uop_14_br_mask}, {stq_uop_13_br_mask}, {stq_uop_12_br_mask}, {stq_uop_11_br_mask}, {stq_uop_10_br_mask}, {stq_uop_9_br_mask}, {stq_uop_8_br_mask}, {stq_uop_7_br_mask}, {stq_uop_6_br_mask}, {stq_uop_5_br_mask}, {stq_uop_4_br_mask}, {stq_uop_3_br_mask}, {stq_uop_2_br_mask}, {stq_uop_1_br_mask}, {stq_uop_0_br_mask}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_br_mask = _GEN_227[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][3:0] _GEN_228 = {{stq_uop_15_br_tag}, {stq_uop_14_br_tag}, {stq_uop_13_br_tag}, {stq_uop_12_br_tag}, {stq_uop_11_br_tag}, {stq_uop_10_br_tag}, {stq_uop_9_br_tag}, {stq_uop_8_br_tag}, {stq_uop_7_br_tag}, {stq_uop_6_br_tag}, {stq_uop_5_br_tag}, {stq_uop_4_br_tag}, {stq_uop_3_br_tag}, {stq_uop_2_br_tag}, {stq_uop_1_br_tag}, {stq_uop_0_br_tag}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_br_tag = _GEN_228[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][3:0] _GEN_229 = {{stq_uop_15_br_type}, {stq_uop_14_br_type}, {stq_uop_13_br_type}, {stq_uop_12_br_type}, {stq_uop_11_br_type}, {stq_uop_10_br_type}, {stq_uop_9_br_type}, {stq_uop_8_br_type}, {stq_uop_7_br_type}, {stq_uop_6_br_type}, {stq_uop_5_br_type}, {stq_uop_4_br_type}, {stq_uop_3_br_type}, {stq_uop_2_br_type}, {stq_uop_1_br_type}, {stq_uop_0_br_type}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_br_type = _GEN_229[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_230 = {{stq_uop_15_is_sfb}, {stq_uop_14_is_sfb}, {stq_uop_13_is_sfb}, {stq_uop_12_is_sfb}, {stq_uop_11_is_sfb}, {stq_uop_10_is_sfb}, {stq_uop_9_is_sfb}, {stq_uop_8_is_sfb}, {stq_uop_7_is_sfb}, {stq_uop_6_is_sfb}, {stq_uop_5_is_sfb}, {stq_uop_4_is_sfb}, {stq_uop_3_is_sfb}, {stq_uop_2_is_sfb}, {stq_uop_1_is_sfb}, {stq_uop_0_is_sfb}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_sfb = _GEN_230[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_231 = {{stq_uop_15_is_fence}, {stq_uop_14_is_fence}, {stq_uop_13_is_fence}, {stq_uop_12_is_fence}, {stq_uop_11_is_fence}, {stq_uop_10_is_fence}, {stq_uop_9_is_fence}, {stq_uop_8_is_fence}, {stq_uop_7_is_fence}, {stq_uop_6_is_fence}, {stq_uop_5_is_fence}, {stq_uop_4_is_fence}, {stq_uop_3_is_fence}, {stq_uop_2_is_fence}, {stq_uop_1_is_fence}, {stq_uop_0_is_fence}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_fence = _GEN_231[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_232 = {{stq_uop_15_is_fencei}, {stq_uop_14_is_fencei}, {stq_uop_13_is_fencei}, {stq_uop_12_is_fencei}, {stq_uop_11_is_fencei}, {stq_uop_10_is_fencei}, {stq_uop_9_is_fencei}, {stq_uop_8_is_fencei}, {stq_uop_7_is_fencei}, {stq_uop_6_is_fencei}, {stq_uop_5_is_fencei}, {stq_uop_4_is_fencei}, {stq_uop_3_is_fencei}, {stq_uop_2_is_fencei}, {stq_uop_1_is_fencei}, {stq_uop_0_is_fencei}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_fencei = _GEN_232[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_233 = {{stq_uop_15_is_sfence}, {stq_uop_14_is_sfence}, {stq_uop_13_is_sfence}, {stq_uop_12_is_sfence}, {stq_uop_11_is_sfence}, {stq_uop_10_is_sfence}, {stq_uop_9_is_sfence}, {stq_uop_8_is_sfence}, {stq_uop_7_is_sfence}, {stq_uop_6_is_sfence}, {stq_uop_5_is_sfence}, {stq_uop_4_is_sfence}, {stq_uop_3_is_sfence}, {stq_uop_2_is_sfence}, {stq_uop_1_is_sfence}, {stq_uop_0_is_sfence}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_sfence = _GEN_233[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_234 = {{stq_uop_15_is_amo}, {stq_uop_14_is_amo}, {stq_uop_13_is_amo}, {stq_uop_12_is_amo}, {stq_uop_11_is_amo}, {stq_uop_10_is_amo}, {stq_uop_9_is_amo}, {stq_uop_8_is_amo}, {stq_uop_7_is_amo}, {stq_uop_6_is_amo}, {stq_uop_5_is_amo}, {stq_uop_4_is_amo}, {stq_uop_3_is_amo}, {stq_uop_2_is_amo}, {stq_uop_1_is_amo}, {stq_uop_0_is_amo}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_amo = _GEN_234[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_235 = {{stq_uop_15_is_eret}, {stq_uop_14_is_eret}, {stq_uop_13_is_eret}, {stq_uop_12_is_eret}, {stq_uop_11_is_eret}, {stq_uop_10_is_eret}, {stq_uop_9_is_eret}, {stq_uop_8_is_eret}, {stq_uop_7_is_eret}, {stq_uop_6_is_eret}, {stq_uop_5_is_eret}, {stq_uop_4_is_eret}, {stq_uop_3_is_eret}, {stq_uop_2_is_eret}, {stq_uop_1_is_eret}, {stq_uop_0_is_eret}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_eret = _GEN_235[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_236 = {{stq_uop_15_is_sys_pc2epc}, {stq_uop_14_is_sys_pc2epc}, {stq_uop_13_is_sys_pc2epc}, {stq_uop_12_is_sys_pc2epc}, {stq_uop_11_is_sys_pc2epc}, {stq_uop_10_is_sys_pc2epc}, {stq_uop_9_is_sys_pc2epc}, {stq_uop_8_is_sys_pc2epc}, {stq_uop_7_is_sys_pc2epc}, {stq_uop_6_is_sys_pc2epc}, {stq_uop_5_is_sys_pc2epc}, {stq_uop_4_is_sys_pc2epc}, {stq_uop_3_is_sys_pc2epc}, {stq_uop_2_is_sys_pc2epc}, {stq_uop_1_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_sys_pc2epc = _GEN_236[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_237 = {{stq_uop_15_is_rocc}, {stq_uop_14_is_rocc}, {stq_uop_13_is_rocc}, {stq_uop_12_is_rocc}, {stq_uop_11_is_rocc}, {stq_uop_10_is_rocc}, {stq_uop_9_is_rocc}, {stq_uop_8_is_rocc}, {stq_uop_7_is_rocc}, {stq_uop_6_is_rocc}, {stq_uop_5_is_rocc}, {stq_uop_4_is_rocc}, {stq_uop_3_is_rocc}, {stq_uop_2_is_rocc}, {stq_uop_1_is_rocc}, {stq_uop_0_is_rocc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_rocc = _GEN_237[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_238 = {{stq_uop_15_is_mov}, {stq_uop_14_is_mov}, {stq_uop_13_is_mov}, {stq_uop_12_is_mov}, {stq_uop_11_is_mov}, {stq_uop_10_is_mov}, {stq_uop_9_is_mov}, {stq_uop_8_is_mov}, {stq_uop_7_is_mov}, {stq_uop_6_is_mov}, {stq_uop_5_is_mov}, {stq_uop_4_is_mov}, {stq_uop_3_is_mov}, {stq_uop_2_is_mov}, {stq_uop_1_is_mov}, {stq_uop_0_is_mov}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_mov = _GEN_238[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][4:0] _GEN_239 = {{stq_uop_15_ftq_idx}, {stq_uop_14_ftq_idx}, {stq_uop_13_ftq_idx}, {stq_uop_12_ftq_idx}, {stq_uop_11_ftq_idx}, {stq_uop_10_ftq_idx}, {stq_uop_9_ftq_idx}, {stq_uop_8_ftq_idx}, {stq_uop_7_ftq_idx}, {stq_uop_6_ftq_idx}, {stq_uop_5_ftq_idx}, {stq_uop_4_ftq_idx}, {stq_uop_3_ftq_idx}, {stq_uop_2_ftq_idx}, {stq_uop_1_ftq_idx}, {stq_uop_0_ftq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ftq_idx = _GEN_239[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_240 = {{stq_uop_15_edge_inst}, {stq_uop_14_edge_inst}, {stq_uop_13_edge_inst}, {stq_uop_12_edge_inst}, {stq_uop_11_edge_inst}, {stq_uop_10_edge_inst}, {stq_uop_9_edge_inst}, {stq_uop_8_edge_inst}, {stq_uop_7_edge_inst}, {stq_uop_6_edge_inst}, {stq_uop_5_edge_inst}, {stq_uop_4_edge_inst}, {stq_uop_3_edge_inst}, {stq_uop_2_edge_inst}, {stq_uop_1_edge_inst}, {stq_uop_0_edge_inst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_edge_inst = _GEN_240[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][5:0] _GEN_241 = {{stq_uop_15_pc_lob}, {stq_uop_14_pc_lob}, {stq_uop_13_pc_lob}, {stq_uop_12_pc_lob}, {stq_uop_11_pc_lob}, {stq_uop_10_pc_lob}, {stq_uop_9_pc_lob}, {stq_uop_8_pc_lob}, {stq_uop_7_pc_lob}, {stq_uop_6_pc_lob}, {stq_uop_5_pc_lob}, {stq_uop_4_pc_lob}, {stq_uop_3_pc_lob}, {stq_uop_2_pc_lob}, {stq_uop_1_pc_lob}, {stq_uop_0_pc_lob}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_pc_lob = _GEN_241[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_242 = {{stq_uop_15_taken}, {stq_uop_14_taken}, {stq_uop_13_taken}, {stq_uop_12_taken}, {stq_uop_11_taken}, {stq_uop_10_taken}, {stq_uop_9_taken}, {stq_uop_8_taken}, {stq_uop_7_taken}, {stq_uop_6_taken}, {stq_uop_5_taken}, {stq_uop_4_taken}, {stq_uop_3_taken}, {stq_uop_2_taken}, {stq_uop_1_taken}, {stq_uop_0_taken}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_taken = _GEN_242[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_243 = {{stq_uop_15_imm_rename}, {stq_uop_14_imm_rename}, {stq_uop_13_imm_rename}, {stq_uop_12_imm_rename}, {stq_uop_11_imm_rename}, {stq_uop_10_imm_rename}, {stq_uop_9_imm_rename}, {stq_uop_8_imm_rename}, {stq_uop_7_imm_rename}, {stq_uop_6_imm_rename}, {stq_uop_5_imm_rename}, {stq_uop_4_imm_rename}, {stq_uop_3_imm_rename}, {stq_uop_2_imm_rename}, {stq_uop_1_imm_rename}, {stq_uop_0_imm_rename}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_imm_rename = _GEN_243[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][2:0] _GEN_244 = {{stq_uop_15_imm_sel}, {stq_uop_14_imm_sel}, {stq_uop_13_imm_sel}, {stq_uop_12_imm_sel}, {stq_uop_11_imm_sel}, {stq_uop_10_imm_sel}, {stq_uop_9_imm_sel}, {stq_uop_8_imm_sel}, {stq_uop_7_imm_sel}, {stq_uop_6_imm_sel}, {stq_uop_5_imm_sel}, {stq_uop_4_imm_sel}, {stq_uop_3_imm_sel}, {stq_uop_2_imm_sel}, {stq_uop_1_imm_sel}, {stq_uop_0_imm_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_imm_sel = _GEN_244[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][4:0] _GEN_245 = {{stq_uop_15_pimm}, {stq_uop_14_pimm}, {stq_uop_13_pimm}, {stq_uop_12_pimm}, {stq_uop_11_pimm}, {stq_uop_10_pimm}, {stq_uop_9_pimm}, {stq_uop_8_pimm}, {stq_uop_7_pimm}, {stq_uop_6_pimm}, {stq_uop_5_pimm}, {stq_uop_4_pimm}, {stq_uop_3_pimm}, {stq_uop_2_pimm}, {stq_uop_1_pimm}, {stq_uop_0_pimm}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_pimm = _GEN_245[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][19:0] _GEN_246 = {{stq_uop_15_imm_packed}, {stq_uop_14_imm_packed}, {stq_uop_13_imm_packed}, {stq_uop_12_imm_packed}, {stq_uop_11_imm_packed}, {stq_uop_10_imm_packed}, {stq_uop_9_imm_packed}, {stq_uop_8_imm_packed}, {stq_uop_7_imm_packed}, {stq_uop_6_imm_packed}, {stq_uop_5_imm_packed}, {stq_uop_4_imm_packed}, {stq_uop_3_imm_packed}, {stq_uop_2_imm_packed}, {stq_uop_1_imm_packed}, {stq_uop_0_imm_packed}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_imm_packed = _GEN_246[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_247 = {{stq_uop_15_op1_sel}, {stq_uop_14_op1_sel}, {stq_uop_13_op1_sel}, {stq_uop_12_op1_sel}, {stq_uop_11_op1_sel}, {stq_uop_10_op1_sel}, {stq_uop_9_op1_sel}, {stq_uop_8_op1_sel}, {stq_uop_7_op1_sel}, {stq_uop_6_op1_sel}, {stq_uop_5_op1_sel}, {stq_uop_4_op1_sel}, {stq_uop_3_op1_sel}, {stq_uop_2_op1_sel}, {stq_uop_1_op1_sel}, {stq_uop_0_op1_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_op1_sel = _GEN_247[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][2:0] _GEN_248 = {{stq_uop_15_op2_sel}, {stq_uop_14_op2_sel}, {stq_uop_13_op2_sel}, {stq_uop_12_op2_sel}, {stq_uop_11_op2_sel}, {stq_uop_10_op2_sel}, {stq_uop_9_op2_sel}, {stq_uop_8_op2_sel}, {stq_uop_7_op2_sel}, {stq_uop_6_op2_sel}, {stq_uop_5_op2_sel}, {stq_uop_4_op2_sel}, {stq_uop_3_op2_sel}, {stq_uop_2_op2_sel}, {stq_uop_1_op2_sel}, {stq_uop_0_op2_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_op2_sel = _GEN_248[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_249 = {{stq_uop_15_fp_ctrl_ldst}, {stq_uop_14_fp_ctrl_ldst}, {stq_uop_13_fp_ctrl_ldst}, {stq_uop_12_fp_ctrl_ldst}, {stq_uop_11_fp_ctrl_ldst}, {stq_uop_10_fp_ctrl_ldst}, {stq_uop_9_fp_ctrl_ldst}, {stq_uop_8_fp_ctrl_ldst}, {stq_uop_7_fp_ctrl_ldst}, {stq_uop_6_fp_ctrl_ldst}, {stq_uop_5_fp_ctrl_ldst}, {stq_uop_4_fp_ctrl_ldst}, {stq_uop_3_fp_ctrl_ldst}, {stq_uop_2_fp_ctrl_ldst}, {stq_uop_1_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ldst = _GEN_249[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_250 = {{stq_uop_15_fp_ctrl_wen}, {stq_uop_14_fp_ctrl_wen}, {stq_uop_13_fp_ctrl_wen}, {stq_uop_12_fp_ctrl_wen}, {stq_uop_11_fp_ctrl_wen}, {stq_uop_10_fp_ctrl_wen}, {stq_uop_9_fp_ctrl_wen}, {stq_uop_8_fp_ctrl_wen}, {stq_uop_7_fp_ctrl_wen}, {stq_uop_6_fp_ctrl_wen}, {stq_uop_5_fp_ctrl_wen}, {stq_uop_4_fp_ctrl_wen}, {stq_uop_3_fp_ctrl_wen}, {stq_uop_2_fp_ctrl_wen}, {stq_uop_1_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_wen = _GEN_250[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_251 = {{stq_uop_15_fp_ctrl_ren1}, {stq_uop_14_fp_ctrl_ren1}, {stq_uop_13_fp_ctrl_ren1}, {stq_uop_12_fp_ctrl_ren1}, {stq_uop_11_fp_ctrl_ren1}, {stq_uop_10_fp_ctrl_ren1}, {stq_uop_9_fp_ctrl_ren1}, {stq_uop_8_fp_ctrl_ren1}, {stq_uop_7_fp_ctrl_ren1}, {stq_uop_6_fp_ctrl_ren1}, {stq_uop_5_fp_ctrl_ren1}, {stq_uop_4_fp_ctrl_ren1}, {stq_uop_3_fp_ctrl_ren1}, {stq_uop_2_fp_ctrl_ren1}, {stq_uop_1_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ren1 = _GEN_251[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_252 = {{stq_uop_15_fp_ctrl_ren2}, {stq_uop_14_fp_ctrl_ren2}, {stq_uop_13_fp_ctrl_ren2}, {stq_uop_12_fp_ctrl_ren2}, {stq_uop_11_fp_ctrl_ren2}, {stq_uop_10_fp_ctrl_ren2}, {stq_uop_9_fp_ctrl_ren2}, {stq_uop_8_fp_ctrl_ren2}, {stq_uop_7_fp_ctrl_ren2}, {stq_uop_6_fp_ctrl_ren2}, {stq_uop_5_fp_ctrl_ren2}, {stq_uop_4_fp_ctrl_ren2}, {stq_uop_3_fp_ctrl_ren2}, {stq_uop_2_fp_ctrl_ren2}, {stq_uop_1_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ren2 = _GEN_252[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_253 = {{stq_uop_15_fp_ctrl_ren3}, {stq_uop_14_fp_ctrl_ren3}, {stq_uop_13_fp_ctrl_ren3}, {stq_uop_12_fp_ctrl_ren3}, {stq_uop_11_fp_ctrl_ren3}, {stq_uop_10_fp_ctrl_ren3}, {stq_uop_9_fp_ctrl_ren3}, {stq_uop_8_fp_ctrl_ren3}, {stq_uop_7_fp_ctrl_ren3}, {stq_uop_6_fp_ctrl_ren3}, {stq_uop_5_fp_ctrl_ren3}, {stq_uop_4_fp_ctrl_ren3}, {stq_uop_3_fp_ctrl_ren3}, {stq_uop_2_fp_ctrl_ren3}, {stq_uop_1_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ren3 = _GEN_253[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_254 = {{stq_uop_15_fp_ctrl_swap12}, {stq_uop_14_fp_ctrl_swap12}, {stq_uop_13_fp_ctrl_swap12}, {stq_uop_12_fp_ctrl_swap12}, {stq_uop_11_fp_ctrl_swap12}, {stq_uop_10_fp_ctrl_swap12}, {stq_uop_9_fp_ctrl_swap12}, {stq_uop_8_fp_ctrl_swap12}, {stq_uop_7_fp_ctrl_swap12}, {stq_uop_6_fp_ctrl_swap12}, {stq_uop_5_fp_ctrl_swap12}, {stq_uop_4_fp_ctrl_swap12}, {stq_uop_3_fp_ctrl_swap12}, {stq_uop_2_fp_ctrl_swap12}, {stq_uop_1_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_swap12 = _GEN_254[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_255 = {{stq_uop_15_fp_ctrl_swap23}, {stq_uop_14_fp_ctrl_swap23}, {stq_uop_13_fp_ctrl_swap23}, {stq_uop_12_fp_ctrl_swap23}, {stq_uop_11_fp_ctrl_swap23}, {stq_uop_10_fp_ctrl_swap23}, {stq_uop_9_fp_ctrl_swap23}, {stq_uop_8_fp_ctrl_swap23}, {stq_uop_7_fp_ctrl_swap23}, {stq_uop_6_fp_ctrl_swap23}, {stq_uop_5_fp_ctrl_swap23}, {stq_uop_4_fp_ctrl_swap23}, {stq_uop_3_fp_ctrl_swap23}, {stq_uop_2_fp_ctrl_swap23}, {stq_uop_1_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_swap23 = _GEN_255[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_256 = {{stq_uop_15_fp_ctrl_typeTagIn}, {stq_uop_14_fp_ctrl_typeTagIn}, {stq_uop_13_fp_ctrl_typeTagIn}, {stq_uop_12_fp_ctrl_typeTagIn}, {stq_uop_11_fp_ctrl_typeTagIn}, {stq_uop_10_fp_ctrl_typeTagIn}, {stq_uop_9_fp_ctrl_typeTagIn}, {stq_uop_8_fp_ctrl_typeTagIn}, {stq_uop_7_fp_ctrl_typeTagIn}, {stq_uop_6_fp_ctrl_typeTagIn}, {stq_uop_5_fp_ctrl_typeTagIn}, {stq_uop_4_fp_ctrl_typeTagIn}, {stq_uop_3_fp_ctrl_typeTagIn}, {stq_uop_2_fp_ctrl_typeTagIn}, {stq_uop_1_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_256[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_257 = {{stq_uop_15_fp_ctrl_typeTagOut}, {stq_uop_14_fp_ctrl_typeTagOut}, {stq_uop_13_fp_ctrl_typeTagOut}, {stq_uop_12_fp_ctrl_typeTagOut}, {stq_uop_11_fp_ctrl_typeTagOut}, {stq_uop_10_fp_ctrl_typeTagOut}, {stq_uop_9_fp_ctrl_typeTagOut}, {stq_uop_8_fp_ctrl_typeTagOut}, {stq_uop_7_fp_ctrl_typeTagOut}, {stq_uop_6_fp_ctrl_typeTagOut}, {stq_uop_5_fp_ctrl_typeTagOut}, {stq_uop_4_fp_ctrl_typeTagOut}, {stq_uop_3_fp_ctrl_typeTagOut}, {stq_uop_2_fp_ctrl_typeTagOut}, {stq_uop_1_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_257[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_258 = {{stq_uop_15_fp_ctrl_fromint}, {stq_uop_14_fp_ctrl_fromint}, {stq_uop_13_fp_ctrl_fromint}, {stq_uop_12_fp_ctrl_fromint}, {stq_uop_11_fp_ctrl_fromint}, {stq_uop_10_fp_ctrl_fromint}, {stq_uop_9_fp_ctrl_fromint}, {stq_uop_8_fp_ctrl_fromint}, {stq_uop_7_fp_ctrl_fromint}, {stq_uop_6_fp_ctrl_fromint}, {stq_uop_5_fp_ctrl_fromint}, {stq_uop_4_fp_ctrl_fromint}, {stq_uop_3_fp_ctrl_fromint}, {stq_uop_2_fp_ctrl_fromint}, {stq_uop_1_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_fromint = _GEN_258[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_259 = {{stq_uop_15_fp_ctrl_toint}, {stq_uop_14_fp_ctrl_toint}, {stq_uop_13_fp_ctrl_toint}, {stq_uop_12_fp_ctrl_toint}, {stq_uop_11_fp_ctrl_toint}, {stq_uop_10_fp_ctrl_toint}, {stq_uop_9_fp_ctrl_toint}, {stq_uop_8_fp_ctrl_toint}, {stq_uop_7_fp_ctrl_toint}, {stq_uop_6_fp_ctrl_toint}, {stq_uop_5_fp_ctrl_toint}, {stq_uop_4_fp_ctrl_toint}, {stq_uop_3_fp_ctrl_toint}, {stq_uop_2_fp_ctrl_toint}, {stq_uop_1_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_toint = _GEN_259[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_260 = {{stq_uop_15_fp_ctrl_fastpipe}, {stq_uop_14_fp_ctrl_fastpipe}, {stq_uop_13_fp_ctrl_fastpipe}, {stq_uop_12_fp_ctrl_fastpipe}, {stq_uop_11_fp_ctrl_fastpipe}, {stq_uop_10_fp_ctrl_fastpipe}, {stq_uop_9_fp_ctrl_fastpipe}, {stq_uop_8_fp_ctrl_fastpipe}, {stq_uop_7_fp_ctrl_fastpipe}, {stq_uop_6_fp_ctrl_fastpipe}, {stq_uop_5_fp_ctrl_fastpipe}, {stq_uop_4_fp_ctrl_fastpipe}, {stq_uop_3_fp_ctrl_fastpipe}, {stq_uop_2_fp_ctrl_fastpipe}, {stq_uop_1_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_260[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_261 = {{stq_uop_15_fp_ctrl_fma}, {stq_uop_14_fp_ctrl_fma}, {stq_uop_13_fp_ctrl_fma}, {stq_uop_12_fp_ctrl_fma}, {stq_uop_11_fp_ctrl_fma}, {stq_uop_10_fp_ctrl_fma}, {stq_uop_9_fp_ctrl_fma}, {stq_uop_8_fp_ctrl_fma}, {stq_uop_7_fp_ctrl_fma}, {stq_uop_6_fp_ctrl_fma}, {stq_uop_5_fp_ctrl_fma}, {stq_uop_4_fp_ctrl_fma}, {stq_uop_3_fp_ctrl_fma}, {stq_uop_2_fp_ctrl_fma}, {stq_uop_1_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_fma = _GEN_261[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_262 = {{stq_uop_15_fp_ctrl_div}, {stq_uop_14_fp_ctrl_div}, {stq_uop_13_fp_ctrl_div}, {stq_uop_12_fp_ctrl_div}, {stq_uop_11_fp_ctrl_div}, {stq_uop_10_fp_ctrl_div}, {stq_uop_9_fp_ctrl_div}, {stq_uop_8_fp_ctrl_div}, {stq_uop_7_fp_ctrl_div}, {stq_uop_6_fp_ctrl_div}, {stq_uop_5_fp_ctrl_div}, {stq_uop_4_fp_ctrl_div}, {stq_uop_3_fp_ctrl_div}, {stq_uop_2_fp_ctrl_div}, {stq_uop_1_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_div = _GEN_262[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_263 = {{stq_uop_15_fp_ctrl_sqrt}, {stq_uop_14_fp_ctrl_sqrt}, {stq_uop_13_fp_ctrl_sqrt}, {stq_uop_12_fp_ctrl_sqrt}, {stq_uop_11_fp_ctrl_sqrt}, {stq_uop_10_fp_ctrl_sqrt}, {stq_uop_9_fp_ctrl_sqrt}, {stq_uop_8_fp_ctrl_sqrt}, {stq_uop_7_fp_ctrl_sqrt}, {stq_uop_6_fp_ctrl_sqrt}, {stq_uop_5_fp_ctrl_sqrt}, {stq_uop_4_fp_ctrl_sqrt}, {stq_uop_3_fp_ctrl_sqrt}, {stq_uop_2_fp_ctrl_sqrt}, {stq_uop_1_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_sqrt = _GEN_263[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_264 = {{stq_uop_15_fp_ctrl_wflags}, {stq_uop_14_fp_ctrl_wflags}, {stq_uop_13_fp_ctrl_wflags}, {stq_uop_12_fp_ctrl_wflags}, {stq_uop_11_fp_ctrl_wflags}, {stq_uop_10_fp_ctrl_wflags}, {stq_uop_9_fp_ctrl_wflags}, {stq_uop_8_fp_ctrl_wflags}, {stq_uop_7_fp_ctrl_wflags}, {stq_uop_6_fp_ctrl_wflags}, {stq_uop_5_fp_ctrl_wflags}, {stq_uop_4_fp_ctrl_wflags}, {stq_uop_3_fp_ctrl_wflags}, {stq_uop_2_fp_ctrl_wflags}, {stq_uop_1_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_wflags = _GEN_264[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_265 = {{stq_uop_15_fp_ctrl_vec}, {stq_uop_14_fp_ctrl_vec}, {stq_uop_13_fp_ctrl_vec}, {stq_uop_12_fp_ctrl_vec}, {stq_uop_11_fp_ctrl_vec}, {stq_uop_10_fp_ctrl_vec}, {stq_uop_9_fp_ctrl_vec}, {stq_uop_8_fp_ctrl_vec}, {stq_uop_7_fp_ctrl_vec}, {stq_uop_6_fp_ctrl_vec}, {stq_uop_5_fp_ctrl_vec}, {stq_uop_4_fp_ctrl_vec}, {stq_uop_3_fp_ctrl_vec}, {stq_uop_2_fp_ctrl_vec}, {stq_uop_1_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_vec = _GEN_265[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][5:0] _GEN_266 = {{stq_uop_15_rob_idx}, {stq_uop_14_rob_idx}, {stq_uop_13_rob_idx}, {stq_uop_12_rob_idx}, {stq_uop_11_rob_idx}, {stq_uop_10_rob_idx}, {stq_uop_9_rob_idx}, {stq_uop_8_rob_idx}, {stq_uop_7_rob_idx}, {stq_uop_6_rob_idx}, {stq_uop_5_rob_idx}, {stq_uop_4_rob_idx}, {stq_uop_3_rob_idx}, {stq_uop_2_rob_idx}, {stq_uop_1_rob_idx}, {stq_uop_0_rob_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_rob_idx = _GEN_266[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][3:0] _GEN_267 = {{stq_uop_15_ldq_idx}, {stq_uop_14_ldq_idx}, {stq_uop_13_ldq_idx}, {stq_uop_12_ldq_idx}, {stq_uop_11_ldq_idx}, {stq_uop_10_ldq_idx}, {stq_uop_9_ldq_idx}, {stq_uop_8_ldq_idx}, {stq_uop_7_ldq_idx}, {stq_uop_6_ldq_idx}, {stq_uop_5_ldq_idx}, {stq_uop_4_ldq_idx}, {stq_uop_3_ldq_idx}, {stq_uop_2_ldq_idx}, {stq_uop_1_ldq_idx}, {stq_uop_0_ldq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ldq_idx = _GEN_267[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][3:0] _GEN_268 = {{stq_uop_15_stq_idx}, {stq_uop_14_stq_idx}, {stq_uop_13_stq_idx}, {stq_uop_12_stq_idx}, {stq_uop_11_stq_idx}, {stq_uop_10_stq_idx}, {stq_uop_9_stq_idx}, {stq_uop_8_stq_idx}, {stq_uop_7_stq_idx}, {stq_uop_6_stq_idx}, {stq_uop_5_stq_idx}, {stq_uop_4_stq_idx}, {stq_uop_3_stq_idx}, {stq_uop_2_stq_idx}, {stq_uop_1_stq_idx}, {stq_uop_0_stq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_stq_idx = _GEN_268[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_269 = {{stq_uop_15_rxq_idx}, {stq_uop_14_rxq_idx}, {stq_uop_13_rxq_idx}, {stq_uop_12_rxq_idx}, {stq_uop_11_rxq_idx}, {stq_uop_10_rxq_idx}, {stq_uop_9_rxq_idx}, {stq_uop_8_rxq_idx}, {stq_uop_7_rxq_idx}, {stq_uop_6_rxq_idx}, {stq_uop_5_rxq_idx}, {stq_uop_4_rxq_idx}, {stq_uop_3_rxq_idx}, {stq_uop_2_rxq_idx}, {stq_uop_1_rxq_idx}, {stq_uop_0_rxq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_rxq_idx = _GEN_269[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][6:0] _GEN_270 = {{stq_uop_15_pdst}, {stq_uop_14_pdst}, {stq_uop_13_pdst}, {stq_uop_12_pdst}, {stq_uop_11_pdst}, {stq_uop_10_pdst}, {stq_uop_9_pdst}, {stq_uop_8_pdst}, {stq_uop_7_pdst}, {stq_uop_6_pdst}, {stq_uop_5_pdst}, {stq_uop_4_pdst}, {stq_uop_3_pdst}, {stq_uop_2_pdst}, {stq_uop_1_pdst}, {stq_uop_0_pdst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_pdst = _GEN_270[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][6:0] _GEN_271 = {{stq_uop_15_prs1}, {stq_uop_14_prs1}, {stq_uop_13_prs1}, {stq_uop_12_prs1}, {stq_uop_11_prs1}, {stq_uop_10_prs1}, {stq_uop_9_prs1}, {stq_uop_8_prs1}, {stq_uop_7_prs1}, {stq_uop_6_prs1}, {stq_uop_5_prs1}, {stq_uop_4_prs1}, {stq_uop_3_prs1}, {stq_uop_2_prs1}, {stq_uop_1_prs1}, {stq_uop_0_prs1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs1 = _GEN_271[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][6:0] _GEN_272 = {{stq_uop_15_prs2}, {stq_uop_14_prs2}, {stq_uop_13_prs2}, {stq_uop_12_prs2}, {stq_uop_11_prs2}, {stq_uop_10_prs2}, {stq_uop_9_prs2}, {stq_uop_8_prs2}, {stq_uop_7_prs2}, {stq_uop_6_prs2}, {stq_uop_5_prs2}, {stq_uop_4_prs2}, {stq_uop_3_prs2}, {stq_uop_2_prs2}, {stq_uop_1_prs2}, {stq_uop_0_prs2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs2 = _GEN_272[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][6:0] _GEN_273 = {{stq_uop_15_prs3}, {stq_uop_14_prs3}, {stq_uop_13_prs3}, {stq_uop_12_prs3}, {stq_uop_11_prs3}, {stq_uop_10_prs3}, {stq_uop_9_prs3}, {stq_uop_8_prs3}, {stq_uop_7_prs3}, {stq_uop_6_prs3}, {stq_uop_5_prs3}, {stq_uop_4_prs3}, {stq_uop_3_prs3}, {stq_uop_2_prs3}, {stq_uop_1_prs3}, {stq_uop_0_prs3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs3 = _GEN_273[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][4:0] _GEN_274 = {{stq_uop_15_ppred}, {stq_uop_14_ppred}, {stq_uop_13_ppred}, {stq_uop_12_ppred}, {stq_uop_11_ppred}, {stq_uop_10_ppred}, {stq_uop_9_ppred}, {stq_uop_8_ppred}, {stq_uop_7_ppred}, {stq_uop_6_ppred}, {stq_uop_5_ppred}, {stq_uop_4_ppred}, {stq_uop_3_ppred}, {stq_uop_2_ppred}, {stq_uop_1_ppred}, {stq_uop_0_ppred}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ppred = _GEN_274[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_275 = {{stq_uop_15_prs1_busy}, {stq_uop_14_prs1_busy}, {stq_uop_13_prs1_busy}, {stq_uop_12_prs1_busy}, {stq_uop_11_prs1_busy}, {stq_uop_10_prs1_busy}, {stq_uop_9_prs1_busy}, {stq_uop_8_prs1_busy}, {stq_uop_7_prs1_busy}, {stq_uop_6_prs1_busy}, {stq_uop_5_prs1_busy}, {stq_uop_4_prs1_busy}, {stq_uop_3_prs1_busy}, {stq_uop_2_prs1_busy}, {stq_uop_1_prs1_busy}, {stq_uop_0_prs1_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs1_busy = _GEN_275[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_276 = {{stq_uop_15_prs2_busy}, {stq_uop_14_prs2_busy}, {stq_uop_13_prs2_busy}, {stq_uop_12_prs2_busy}, {stq_uop_11_prs2_busy}, {stq_uop_10_prs2_busy}, {stq_uop_9_prs2_busy}, {stq_uop_8_prs2_busy}, {stq_uop_7_prs2_busy}, {stq_uop_6_prs2_busy}, {stq_uop_5_prs2_busy}, {stq_uop_4_prs2_busy}, {stq_uop_3_prs2_busy}, {stq_uop_2_prs2_busy}, {stq_uop_1_prs2_busy}, {stq_uop_0_prs2_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs2_busy = _GEN_276[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_277 = {{stq_uop_15_prs3_busy}, {stq_uop_14_prs3_busy}, {stq_uop_13_prs3_busy}, {stq_uop_12_prs3_busy}, {stq_uop_11_prs3_busy}, {stq_uop_10_prs3_busy}, {stq_uop_9_prs3_busy}, {stq_uop_8_prs3_busy}, {stq_uop_7_prs3_busy}, {stq_uop_6_prs3_busy}, {stq_uop_5_prs3_busy}, {stq_uop_4_prs3_busy}, {stq_uop_3_prs3_busy}, {stq_uop_2_prs3_busy}, {stq_uop_1_prs3_busy}, {stq_uop_0_prs3_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs3_busy = _GEN_277[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_278 = {{stq_uop_15_ppred_busy}, {stq_uop_14_ppred_busy}, {stq_uop_13_ppred_busy}, {stq_uop_12_ppred_busy}, {stq_uop_11_ppred_busy}, {stq_uop_10_ppred_busy}, {stq_uop_9_ppred_busy}, {stq_uop_8_ppred_busy}, {stq_uop_7_ppred_busy}, {stq_uop_6_ppred_busy}, {stq_uop_5_ppred_busy}, {stq_uop_4_ppred_busy}, {stq_uop_3_ppred_busy}, {stq_uop_2_ppred_busy}, {stq_uop_1_ppred_busy}, {stq_uop_0_ppred_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ppred_busy = _GEN_278[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][6:0] _GEN_279 = {{stq_uop_15_stale_pdst}, {stq_uop_14_stale_pdst}, {stq_uop_13_stale_pdst}, {stq_uop_12_stale_pdst}, {stq_uop_11_stale_pdst}, {stq_uop_10_stale_pdst}, {stq_uop_9_stale_pdst}, {stq_uop_8_stale_pdst}, {stq_uop_7_stale_pdst}, {stq_uop_6_stale_pdst}, {stq_uop_5_stale_pdst}, {stq_uop_4_stale_pdst}, {stq_uop_3_stale_pdst}, {stq_uop_2_stale_pdst}, {stq_uop_1_stale_pdst}, {stq_uop_0_stale_pdst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_stale_pdst = _GEN_279[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_280 = {{stq_uop_15_exception}, {stq_uop_14_exception}, {stq_uop_13_exception}, {stq_uop_12_exception}, {stq_uop_11_exception}, {stq_uop_10_exception}, {stq_uop_9_exception}, {stq_uop_8_exception}, {stq_uop_7_exception}, {stq_uop_6_exception}, {stq_uop_5_exception}, {stq_uop_4_exception}, {stq_uop_3_exception}, {stq_uop_2_exception}, {stq_uop_1_exception}, {stq_uop_0_exception}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_exception = _GEN_280[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][63:0] _GEN_281 = {{stq_uop_15_exc_cause}, {stq_uop_14_exc_cause}, {stq_uop_13_exc_cause}, {stq_uop_12_exc_cause}, {stq_uop_11_exc_cause}, {stq_uop_10_exc_cause}, {stq_uop_9_exc_cause}, {stq_uop_8_exc_cause}, {stq_uop_7_exc_cause}, {stq_uop_6_exc_cause}, {stq_uop_5_exc_cause}, {stq_uop_4_exc_cause}, {stq_uop_3_exc_cause}, {stq_uop_2_exc_cause}, {stq_uop_1_exc_cause}, {stq_uop_0_exc_cause}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_exc_cause = _GEN_281[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][4:0] _GEN_282 = {{stq_uop_15_mem_cmd}, {stq_uop_14_mem_cmd}, {stq_uop_13_mem_cmd}, {stq_uop_12_mem_cmd}, {stq_uop_11_mem_cmd}, {stq_uop_10_mem_cmd}, {stq_uop_9_mem_cmd}, {stq_uop_8_mem_cmd}, {stq_uop_7_mem_cmd}, {stq_uop_6_mem_cmd}, {stq_uop_5_mem_cmd}, {stq_uop_4_mem_cmd}, {stq_uop_3_mem_cmd}, {stq_uop_2_mem_cmd}, {stq_uop_1_mem_cmd}, {stq_uop_0_mem_cmd}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_mem_cmd = _GEN_282[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_283 = {{stq_uop_15_mem_size}, {stq_uop_14_mem_size}, {stq_uop_13_mem_size}, {stq_uop_12_mem_size}, {stq_uop_11_mem_size}, {stq_uop_10_mem_size}, {stq_uop_9_mem_size}, {stq_uop_8_mem_size}, {stq_uop_7_mem_size}, {stq_uop_6_mem_size}, {stq_uop_5_mem_size}, {stq_uop_4_mem_size}, {stq_uop_3_mem_size}, {stq_uop_2_mem_size}, {stq_uop_1_mem_size}, {stq_uop_0_mem_size}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_mem_size = _GEN_283[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_284 = {{stq_uop_15_mem_signed}, {stq_uop_14_mem_signed}, {stq_uop_13_mem_signed}, {stq_uop_12_mem_signed}, {stq_uop_11_mem_signed}, {stq_uop_10_mem_signed}, {stq_uop_9_mem_signed}, {stq_uop_8_mem_signed}, {stq_uop_7_mem_signed}, {stq_uop_6_mem_signed}, {stq_uop_5_mem_signed}, {stq_uop_4_mem_signed}, {stq_uop_3_mem_signed}, {stq_uop_2_mem_signed}, {stq_uop_1_mem_signed}, {stq_uop_0_mem_signed}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_mem_signed = _GEN_284[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_285 = {{stq_uop_15_uses_ldq}, {stq_uop_14_uses_ldq}, {stq_uop_13_uses_ldq}, {stq_uop_12_uses_ldq}, {stq_uop_11_uses_ldq}, {stq_uop_10_uses_ldq}, {stq_uop_9_uses_ldq}, {stq_uop_8_uses_ldq}, {stq_uop_7_uses_ldq}, {stq_uop_6_uses_ldq}, {stq_uop_5_uses_ldq}, {stq_uop_4_uses_ldq}, {stq_uop_3_uses_ldq}, {stq_uop_2_uses_ldq}, {stq_uop_1_uses_ldq}, {stq_uop_0_uses_ldq}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_uses_ldq = _GEN_285[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_286 = {{stq_uop_15_uses_stq}, {stq_uop_14_uses_stq}, {stq_uop_13_uses_stq}, {stq_uop_12_uses_stq}, {stq_uop_11_uses_stq}, {stq_uop_10_uses_stq}, {stq_uop_9_uses_stq}, {stq_uop_8_uses_stq}, {stq_uop_7_uses_stq}, {stq_uop_6_uses_stq}, {stq_uop_5_uses_stq}, {stq_uop_4_uses_stq}, {stq_uop_3_uses_stq}, {stq_uop_2_uses_stq}, {stq_uop_1_uses_stq}, {stq_uop_0_uses_stq}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_uses_stq = _GEN_286[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_287 = {{stq_uop_15_is_unique}, {stq_uop_14_is_unique}, {stq_uop_13_is_unique}, {stq_uop_12_is_unique}, {stq_uop_11_is_unique}, {stq_uop_10_is_unique}, {stq_uop_9_is_unique}, {stq_uop_8_is_unique}, {stq_uop_7_is_unique}, {stq_uop_6_is_unique}, {stq_uop_5_is_unique}, {stq_uop_4_is_unique}, {stq_uop_3_is_unique}, {stq_uop_2_is_unique}, {stq_uop_1_is_unique}, {stq_uop_0_is_unique}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_unique = _GEN_287[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_288 = {{stq_uop_15_flush_on_commit}, {stq_uop_14_flush_on_commit}, {stq_uop_13_flush_on_commit}, {stq_uop_12_flush_on_commit}, {stq_uop_11_flush_on_commit}, {stq_uop_10_flush_on_commit}, {stq_uop_9_flush_on_commit}, {stq_uop_8_flush_on_commit}, {stq_uop_7_flush_on_commit}, {stq_uop_6_flush_on_commit}, {stq_uop_5_flush_on_commit}, {stq_uop_4_flush_on_commit}, {stq_uop_3_flush_on_commit}, {stq_uop_2_flush_on_commit}, {stq_uop_1_flush_on_commit}, {stq_uop_0_flush_on_commit}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_flush_on_commit = _GEN_288[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][2:0] _GEN_289 = {{stq_uop_15_csr_cmd}, {stq_uop_14_csr_cmd}, {stq_uop_13_csr_cmd}, {stq_uop_12_csr_cmd}, {stq_uop_11_csr_cmd}, {stq_uop_10_csr_cmd}, {stq_uop_9_csr_cmd}, {stq_uop_8_csr_cmd}, {stq_uop_7_csr_cmd}, {stq_uop_6_csr_cmd}, {stq_uop_5_csr_cmd}, {stq_uop_4_csr_cmd}, {stq_uop_3_csr_cmd}, {stq_uop_2_csr_cmd}, {stq_uop_1_csr_cmd}, {stq_uop_0_csr_cmd}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_csr_cmd = _GEN_289[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_290 = {{stq_uop_15_ldst_is_rs1}, {stq_uop_14_ldst_is_rs1}, {stq_uop_13_ldst_is_rs1}, {stq_uop_12_ldst_is_rs1}, {stq_uop_11_ldst_is_rs1}, {stq_uop_10_ldst_is_rs1}, {stq_uop_9_ldst_is_rs1}, {stq_uop_8_ldst_is_rs1}, {stq_uop_7_ldst_is_rs1}, {stq_uop_6_ldst_is_rs1}, {stq_uop_5_ldst_is_rs1}, {stq_uop_4_ldst_is_rs1}, {stq_uop_3_ldst_is_rs1}, {stq_uop_2_ldst_is_rs1}, {stq_uop_1_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ldst_is_rs1 = _GEN_290[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][5:0] _GEN_291 = {{stq_uop_15_ldst}, {stq_uop_14_ldst}, {stq_uop_13_ldst}, {stq_uop_12_ldst}, {stq_uop_11_ldst}, {stq_uop_10_ldst}, {stq_uop_9_ldst}, {stq_uop_8_ldst}, {stq_uop_7_ldst}, {stq_uop_6_ldst}, {stq_uop_5_ldst}, {stq_uop_4_ldst}, {stq_uop_3_ldst}, {stq_uop_2_ldst}, {stq_uop_1_ldst}, {stq_uop_0_ldst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ldst = _GEN_291[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][5:0] _GEN_292 = {{stq_uop_15_lrs1}, {stq_uop_14_lrs1}, {stq_uop_13_lrs1}, {stq_uop_12_lrs1}, {stq_uop_11_lrs1}, {stq_uop_10_lrs1}, {stq_uop_9_lrs1}, {stq_uop_8_lrs1}, {stq_uop_7_lrs1}, {stq_uop_6_lrs1}, {stq_uop_5_lrs1}, {stq_uop_4_lrs1}, {stq_uop_3_lrs1}, {stq_uop_2_lrs1}, {stq_uop_1_lrs1}, {stq_uop_0_lrs1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs1 = _GEN_292[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][5:0] _GEN_293 = {{stq_uop_15_lrs2}, {stq_uop_14_lrs2}, {stq_uop_13_lrs2}, {stq_uop_12_lrs2}, {stq_uop_11_lrs2}, {stq_uop_10_lrs2}, {stq_uop_9_lrs2}, {stq_uop_8_lrs2}, {stq_uop_7_lrs2}, {stq_uop_6_lrs2}, {stq_uop_5_lrs2}, {stq_uop_4_lrs2}, {stq_uop_3_lrs2}, {stq_uop_2_lrs2}, {stq_uop_1_lrs2}, {stq_uop_0_lrs2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs2 = _GEN_293[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][5:0] _GEN_294 = {{stq_uop_15_lrs3}, {stq_uop_14_lrs3}, {stq_uop_13_lrs3}, {stq_uop_12_lrs3}, {stq_uop_11_lrs3}, {stq_uop_10_lrs3}, {stq_uop_9_lrs3}, {stq_uop_8_lrs3}, {stq_uop_7_lrs3}, {stq_uop_6_lrs3}, {stq_uop_5_lrs3}, {stq_uop_4_lrs3}, {stq_uop_3_lrs3}, {stq_uop_2_lrs3}, {stq_uop_1_lrs3}, {stq_uop_0_lrs3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs3 = _GEN_294[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_295 = {{stq_uop_15_dst_rtype}, {stq_uop_14_dst_rtype}, {stq_uop_13_dst_rtype}, {stq_uop_12_dst_rtype}, {stq_uop_11_dst_rtype}, {stq_uop_10_dst_rtype}, {stq_uop_9_dst_rtype}, {stq_uop_8_dst_rtype}, {stq_uop_7_dst_rtype}, {stq_uop_6_dst_rtype}, {stq_uop_5_dst_rtype}, {stq_uop_4_dst_rtype}, {stq_uop_3_dst_rtype}, {stq_uop_2_dst_rtype}, {stq_uop_1_dst_rtype}, {stq_uop_0_dst_rtype}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_dst_rtype = _GEN_295[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_296 = {{stq_uop_15_lrs1_rtype}, {stq_uop_14_lrs1_rtype}, {stq_uop_13_lrs1_rtype}, {stq_uop_12_lrs1_rtype}, {stq_uop_11_lrs1_rtype}, {stq_uop_10_lrs1_rtype}, {stq_uop_9_lrs1_rtype}, {stq_uop_8_lrs1_rtype}, {stq_uop_7_lrs1_rtype}, {stq_uop_6_lrs1_rtype}, {stq_uop_5_lrs1_rtype}, {stq_uop_4_lrs1_rtype}, {stq_uop_3_lrs1_rtype}, {stq_uop_2_lrs1_rtype}, {stq_uop_1_lrs1_rtype}, {stq_uop_0_lrs1_rtype}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs1_rtype = _GEN_296[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_297 = {{stq_uop_15_lrs2_rtype}, {stq_uop_14_lrs2_rtype}, {stq_uop_13_lrs2_rtype}, {stq_uop_12_lrs2_rtype}, {stq_uop_11_lrs2_rtype}, {stq_uop_10_lrs2_rtype}, {stq_uop_9_lrs2_rtype}, {stq_uop_8_lrs2_rtype}, {stq_uop_7_lrs2_rtype}, {stq_uop_6_lrs2_rtype}, {stq_uop_5_lrs2_rtype}, {stq_uop_4_lrs2_rtype}, {stq_uop_3_lrs2_rtype}, {stq_uop_2_lrs2_rtype}, {stq_uop_1_lrs2_rtype}, {stq_uop_0_lrs2_rtype}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs2_rtype = _GEN_297[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_298 = {{stq_uop_15_frs3_en}, {stq_uop_14_frs3_en}, {stq_uop_13_frs3_en}, {stq_uop_12_frs3_en}, {stq_uop_11_frs3_en}, {stq_uop_10_frs3_en}, {stq_uop_9_frs3_en}, {stq_uop_8_frs3_en}, {stq_uop_7_frs3_en}, {stq_uop_6_frs3_en}, {stq_uop_5_frs3_en}, {stq_uop_4_frs3_en}, {stq_uop_3_frs3_en}, {stq_uop_2_frs3_en}, {stq_uop_1_frs3_en}, {stq_uop_0_frs3_en}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_frs3_en = _GEN_298[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_299 = {{stq_uop_15_fcn_dw}, {stq_uop_14_fcn_dw}, {stq_uop_13_fcn_dw}, {stq_uop_12_fcn_dw}, {stq_uop_11_fcn_dw}, {stq_uop_10_fcn_dw}, {stq_uop_9_fcn_dw}, {stq_uop_8_fcn_dw}, {stq_uop_7_fcn_dw}, {stq_uop_6_fcn_dw}, {stq_uop_5_fcn_dw}, {stq_uop_4_fcn_dw}, {stq_uop_3_fcn_dw}, {stq_uop_2_fcn_dw}, {stq_uop_1_fcn_dw}, {stq_uop_0_fcn_dw}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fcn_dw = _GEN_299[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][4:0] _GEN_300 = {{stq_uop_15_fcn_op}, {stq_uop_14_fcn_op}, {stq_uop_13_fcn_op}, {stq_uop_12_fcn_op}, {stq_uop_11_fcn_op}, {stq_uop_10_fcn_op}, {stq_uop_9_fcn_op}, {stq_uop_8_fcn_op}, {stq_uop_7_fcn_op}, {stq_uop_6_fcn_op}, {stq_uop_5_fcn_op}, {stq_uop_4_fcn_op}, {stq_uop_3_fcn_op}, {stq_uop_2_fcn_op}, {stq_uop_1_fcn_op}, {stq_uop_0_fcn_op}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fcn_op = _GEN_300[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_301 = {{stq_uop_15_fp_val}, {stq_uop_14_fp_val}, {stq_uop_13_fp_val}, {stq_uop_12_fp_val}, {stq_uop_11_fp_val}, {stq_uop_10_fp_val}, {stq_uop_9_fp_val}, {stq_uop_8_fp_val}, {stq_uop_7_fp_val}, {stq_uop_6_fp_val}, {stq_uop_5_fp_val}, {stq_uop_4_fp_val}, {stq_uop_3_fp_val}, {stq_uop_2_fp_val}, {stq_uop_1_fp_val}, {stq_uop_0_fp_val}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_val = _GEN_301[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][2:0] _GEN_302 = {{stq_uop_15_fp_rm}, {stq_uop_14_fp_rm}, {stq_uop_13_fp_rm}, {stq_uop_12_fp_rm}, {stq_uop_11_fp_rm}, {stq_uop_10_fp_rm}, {stq_uop_9_fp_rm}, {stq_uop_8_fp_rm}, {stq_uop_7_fp_rm}, {stq_uop_6_fp_rm}, {stq_uop_5_fp_rm}, {stq_uop_4_fp_rm}, {stq_uop_3_fp_rm}, {stq_uop_2_fp_rm}, {stq_uop_1_fp_rm}, {stq_uop_0_fp_rm}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_rm = _GEN_302[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_303 = {{stq_uop_15_fp_typ}, {stq_uop_14_fp_typ}, {stq_uop_13_fp_typ}, {stq_uop_12_fp_typ}, {stq_uop_11_fp_typ}, {stq_uop_10_fp_typ}, {stq_uop_9_fp_typ}, {stq_uop_8_fp_typ}, {stq_uop_7_fp_typ}, {stq_uop_6_fp_typ}, {stq_uop_5_fp_typ}, {stq_uop_4_fp_typ}, {stq_uop_3_fp_typ}, {stq_uop_2_fp_typ}, {stq_uop_1_fp_typ}, {stq_uop_0_fp_typ}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_typ = _GEN_303[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_304 = {{stq_uop_15_xcpt_pf_if}, {stq_uop_14_xcpt_pf_if}, {stq_uop_13_xcpt_pf_if}, {stq_uop_12_xcpt_pf_if}, {stq_uop_11_xcpt_pf_if}, {stq_uop_10_xcpt_pf_if}, {stq_uop_9_xcpt_pf_if}, {stq_uop_8_xcpt_pf_if}, {stq_uop_7_xcpt_pf_if}, {stq_uop_6_xcpt_pf_if}, {stq_uop_5_xcpt_pf_if}, {stq_uop_4_xcpt_pf_if}, {stq_uop_3_xcpt_pf_if}, {stq_uop_2_xcpt_pf_if}, {stq_uop_1_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_xcpt_pf_if = _GEN_304[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_305 = {{stq_uop_15_xcpt_ae_if}, {stq_uop_14_xcpt_ae_if}, {stq_uop_13_xcpt_ae_if}, {stq_uop_12_xcpt_ae_if}, {stq_uop_11_xcpt_ae_if}, {stq_uop_10_xcpt_ae_if}, {stq_uop_9_xcpt_ae_if}, {stq_uop_8_xcpt_ae_if}, {stq_uop_7_xcpt_ae_if}, {stq_uop_6_xcpt_ae_if}, {stq_uop_5_xcpt_ae_if}, {stq_uop_4_xcpt_ae_if}, {stq_uop_3_xcpt_ae_if}, {stq_uop_2_xcpt_ae_if}, {stq_uop_1_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_xcpt_ae_if = _GEN_305[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_306 = {{stq_uop_15_xcpt_ma_if}, {stq_uop_14_xcpt_ma_if}, {stq_uop_13_xcpt_ma_if}, {stq_uop_12_xcpt_ma_if}, {stq_uop_11_xcpt_ma_if}, {stq_uop_10_xcpt_ma_if}, {stq_uop_9_xcpt_ma_if}, {stq_uop_8_xcpt_ma_if}, {stq_uop_7_xcpt_ma_if}, {stq_uop_6_xcpt_ma_if}, {stq_uop_5_xcpt_ma_if}, {stq_uop_4_xcpt_ma_if}, {stq_uop_3_xcpt_ma_if}, {stq_uop_2_xcpt_ma_if}, {stq_uop_1_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_xcpt_ma_if = _GEN_306[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_307 = {{stq_uop_15_bp_debug_if}, {stq_uop_14_bp_debug_if}, {stq_uop_13_bp_debug_if}, {stq_uop_12_bp_debug_if}, {stq_uop_11_bp_debug_if}, {stq_uop_10_bp_debug_if}, {stq_uop_9_bp_debug_if}, {stq_uop_8_bp_debug_if}, {stq_uop_7_bp_debug_if}, {stq_uop_6_bp_debug_if}, {stq_uop_5_bp_debug_if}, {stq_uop_4_bp_debug_if}, {stq_uop_3_bp_debug_if}, {stq_uop_2_bp_debug_if}, {stq_uop_1_bp_debug_if}, {stq_uop_0_bp_debug_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_bp_debug_if = _GEN_307[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_308 = {{stq_uop_15_bp_xcpt_if}, {stq_uop_14_bp_xcpt_if}, {stq_uop_13_bp_xcpt_if}, {stq_uop_12_bp_xcpt_if}, {stq_uop_11_bp_xcpt_if}, {stq_uop_10_bp_xcpt_if}, {stq_uop_9_bp_xcpt_if}, {stq_uop_8_bp_xcpt_if}, {stq_uop_7_bp_xcpt_if}, {stq_uop_6_bp_xcpt_if}, {stq_uop_5_bp_xcpt_if}, {stq_uop_4_bp_xcpt_if}, {stq_uop_3_bp_xcpt_if}, {stq_uop_2_bp_xcpt_if}, {stq_uop_1_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_bp_xcpt_if = _GEN_308[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][2:0] _GEN_309 = {{stq_uop_15_debug_fsrc}, {stq_uop_14_debug_fsrc}, {stq_uop_13_debug_fsrc}, {stq_uop_12_debug_fsrc}, {stq_uop_11_debug_fsrc}, {stq_uop_10_debug_fsrc}, {stq_uop_9_debug_fsrc}, {stq_uop_8_debug_fsrc}, {stq_uop_7_debug_fsrc}, {stq_uop_6_debug_fsrc}, {stq_uop_5_debug_fsrc}, {stq_uop_4_debug_fsrc}, {stq_uop_3_debug_fsrc}, {stq_uop_2_debug_fsrc}, {stq_uop_1_debug_fsrc}, {stq_uop_0_debug_fsrc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_fsrc = _GEN_309[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][2:0] _GEN_310 = {{stq_uop_15_debug_tsrc}, {stq_uop_14_debug_tsrc}, {stq_uop_13_debug_tsrc}, {stq_uop_12_debug_tsrc}, {stq_uop_11_debug_tsrc}, {stq_uop_10_debug_tsrc}, {stq_uop_9_debug_tsrc}, {stq_uop_8_debug_tsrc}, {stq_uop_7_debug_tsrc}, {stq_uop_6_debug_tsrc}, {stq_uop_5_debug_tsrc}, {stq_uop_4_debug_tsrc}, {stq_uop_3_debug_tsrc}, {stq_uop_2_debug_tsrc}, {stq_uop_1_debug_tsrc}, {stq_uop_0_debug_tsrc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_tsrc = _GEN_310[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_311 = {{stq_addr_15_valid}, {stq_addr_14_valid}, {stq_addr_13_valid}, {stq_addr_12_valid}, {stq_addr_11_valid}, {stq_addr_10_valid}, {stq_addr_9_valid}, {stq_addr_8_valid}, {stq_addr_7_valid}, {stq_addr_6_valid}, {stq_addr_5_valid}, {stq_addr_4_valid}, {stq_addr_3_valid}, {stq_addr_2_valid}, {stq_addr_1_valid}, {stq_addr_0_valid}}; // @[lsu.scala:253:32, :265:32] assign stq_incoming_e_e_bits_addr_valid = _GEN_311[stq_incoming_idx_0]; // @[lsu.scala:262:17, :265:32, :321:49] wire [15:0][39:0] _GEN_312 = {{stq_addr_15_bits}, {stq_addr_14_bits}, {stq_addr_13_bits}, {stq_addr_12_bits}, {stq_addr_11_bits}, {stq_addr_10_bits}, {stq_addr_9_bits}, {stq_addr_8_bits}, {stq_addr_7_bits}, {stq_addr_6_bits}, {stq_addr_5_bits}, {stq_addr_4_bits}, {stq_addr_3_bits}, {stq_addr_2_bits}, {stq_addr_1_bits}, {stq_addr_0_bits}}; // @[lsu.scala:253:32, :265:32] assign stq_incoming_e_e_bits_addr_bits = _GEN_312[stq_incoming_idx_0]; // @[lsu.scala:262:17, :265:32, :321:49] wire [15:0] _GEN_313 = {{stq_addr_is_virtual_15}, {stq_addr_is_virtual_14}, {stq_addr_is_virtual_13}, {stq_addr_is_virtual_12}, {stq_addr_is_virtual_11}, {stq_addr_is_virtual_10}, {stq_addr_is_virtual_9}, {stq_addr_is_virtual_8}, {stq_addr_is_virtual_7}, {stq_addr_is_virtual_6}, {stq_addr_is_virtual_5}, {stq_addr_is_virtual_4}, {stq_addr_is_virtual_3}, {stq_addr_is_virtual_2}, {stq_addr_is_virtual_1}, {stq_addr_is_virtual_0}}; // @[lsu.scala:254:32, :266:32] assign stq_incoming_e_e_bits_addr_is_virtual = _GEN_313[stq_incoming_idx_0]; // @[lsu.scala:262:17, :266:32, :321:49] wire [15:0] _GEN_314 = {{stq_data_15_valid}, {stq_data_14_valid}, {stq_data_13_valid}, {stq_data_12_valid}, {stq_data_11_valid}, {stq_data_10_valid}, {stq_data_9_valid}, {stq_data_8_valid}, {stq_data_7_valid}, {stq_data_6_valid}, {stq_data_5_valid}, {stq_data_4_valid}, {stq_data_3_valid}, {stq_data_2_valid}, {stq_data_1_valid}, {stq_data_0_valid}}; // @[lsu.scala:255:32, :267:32] assign stq_incoming_e_e_bits_data_valid = _GEN_314[stq_incoming_idx_0]; // @[lsu.scala:262:17, :267:32, :321:49] wire [15:0][63:0] _GEN_315 = {{stq_data_15_bits}, {stq_data_14_bits}, {stq_data_13_bits}, {stq_data_12_bits}, {stq_data_11_bits}, {stq_data_10_bits}, {stq_data_9_bits}, {stq_data_8_bits}, {stq_data_7_bits}, {stq_data_6_bits}, {stq_data_5_bits}, {stq_data_4_bits}, {stq_data_3_bits}, {stq_data_2_bits}, {stq_data_1_bits}, {stq_data_0_bits}}; // @[lsu.scala:255:32, :267:32] assign stq_incoming_e_e_bits_data_bits = _GEN_315[stq_incoming_idx_0]; // @[lsu.scala:262:17, :267:32, :321:49] wire [15:0] _GEN_316 = {{stq_committed_15}, {stq_committed_14}, {stq_committed_13}, {stq_committed_12}, {stq_committed_11}, {stq_committed_10}, {stq_committed_9}, {stq_committed_8}, {stq_committed_7}, {stq_committed_6}, {stq_committed_5}, {stq_committed_4}, {stq_committed_3}, {stq_committed_2}, {stq_committed_1}, {stq_committed_0}}; // @[lsu.scala:256:32, :268:32] assign stq_incoming_e_e_bits_committed = _GEN_316[stq_incoming_idx_0]; // @[lsu.scala:262:17, :268:32, :321:49] wire [15:0] _GEN_317 = {{stq_succeeded_15}, {stq_succeeded_14}, {stq_succeeded_13}, {stq_succeeded_12}, {stq_succeeded_11}, {stq_succeeded_10}, {stq_succeeded_9}, {stq_succeeded_8}, {stq_succeeded_7}, {stq_succeeded_6}, {stq_succeeded_5}, {stq_succeeded_4}, {stq_succeeded_3}, {stq_succeeded_2}, {stq_succeeded_1}, {stq_succeeded_0}}; // @[lsu.scala:257:32, :269:32] assign stq_incoming_e_e_bits_succeeded = _GEN_317[stq_incoming_idx_0]; // @[lsu.scala:262:17, :269:32, :321:49] wire [15:0] _GEN_318 = {{stq_can_execute_15}, {stq_can_execute_14}, {stq_can_execute_13}, {stq_can_execute_12}, {stq_can_execute_11}, {stq_can_execute_10}, {stq_can_execute_9}, {stq_can_execute_8}, {stq_can_execute_7}, {stq_can_execute_6}, {stq_can_execute_5}, {stq_can_execute_4}, {stq_can_execute_3}, {stq_can_execute_2}, {stq_can_execute_1}, {stq_can_execute_0}}; // @[lsu.scala:258:32, :270:32] assign stq_incoming_e_e_bits_can_execute = _GEN_318[stq_incoming_idx_0]; // @[lsu.scala:262:17, :270:32, :321:49] wire [15:0] _GEN_319 = {{stq_cleared_15}, {stq_cleared_14}, {stq_cleared_13}, {stq_cleared_12}, {stq_cleared_11}, {stq_cleared_10}, {stq_cleared_9}, {stq_cleared_8}, {stq_cleared_7}, {stq_cleared_6}, {stq_cleared_5}, {stq_cleared_4}, {stq_cleared_3}, {stq_cleared_2}, {stq_cleared_1}, {stq_cleared_0}}; // @[lsu.scala:259:32, :271:32] assign stq_incoming_e_e_bits_cleared = _GEN_319[stq_incoming_idx_0]; // @[lsu.scala:262:17, :271:32, :321:49] wire [15:0][63:0] _GEN_320 = {{stq_debug_wb_data_15}, {stq_debug_wb_data_14}, {stq_debug_wb_data_13}, {stq_debug_wb_data_12}, {stq_debug_wb_data_11}, {stq_debug_wb_data_10}, {stq_debug_wb_data_9}, {stq_debug_wb_data_8}, {stq_debug_wb_data_7}, {stq_debug_wb_data_6}, {stq_debug_wb_data_5}, {stq_debug_wb_data_4}, {stq_debug_wb_data_3}, {stq_debug_wb_data_2}, {stq_debug_wb_data_1}, {stq_debug_wb_data_0}}; // @[lsu.scala:260:32, :272:32] assign stq_incoming_e_e_bits_debug_wb_data = _GEN_320[stq_incoming_idx_0]; // @[lsu.scala:262:17, :272:32, :321:49] wire stq_incoming_e_0_valid = _stq_incoming_e_WIRE_valid; // @[lsu.scala:321:49, :504:48] wire [31:0] stq_incoming_e_0_bits_uop_inst = _stq_incoming_e_WIRE_bits_uop_inst; // @[lsu.scala:321:49, :504:48] wire [31:0] stq_incoming_e_0_bits_uop_debug_inst = _stq_incoming_e_WIRE_bits_uop_debug_inst; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_rvc = _stq_incoming_e_WIRE_bits_uop_is_rvc; // @[lsu.scala:321:49, :504:48] wire [39:0] stq_incoming_e_0_bits_uop_debug_pc = _stq_incoming_e_WIRE_bits_uop_debug_pc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_0 = _stq_incoming_e_WIRE_bits_uop_iq_type_0; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_1 = _stq_incoming_e_WIRE_bits_uop_iq_type_1; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_2 = _stq_incoming_e_WIRE_bits_uop_iq_type_2; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_3 = _stq_incoming_e_WIRE_bits_uop_iq_type_3; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_0 = _stq_incoming_e_WIRE_bits_uop_fu_code_0; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_1 = _stq_incoming_e_WIRE_bits_uop_fu_code_1; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_2 = _stq_incoming_e_WIRE_bits_uop_fu_code_2; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_3 = _stq_incoming_e_WIRE_bits_uop_fu_code_3; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_4 = _stq_incoming_e_WIRE_bits_uop_fu_code_4; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_5 = _stq_incoming_e_WIRE_bits_uop_fu_code_5; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_6 = _stq_incoming_e_WIRE_bits_uop_fu_code_6; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_7 = _stq_incoming_e_WIRE_bits_uop_fu_code_7; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_8 = _stq_incoming_e_WIRE_bits_uop_fu_code_8; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_9 = _stq_incoming_e_WIRE_bits_uop_fu_code_9; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_issued = _stq_incoming_e_WIRE_bits_uop_iw_issued; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_issued_partial_agen = _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_issued_partial_dgen = _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_iw_p1_speculative_child = _stq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_iw_p2_speculative_child = _stq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_p1_bypass_hint = _stq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_p2_bypass_hint = _stq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_p3_bypass_hint = _stq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_dis_col_sel = _stq_incoming_e_WIRE_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :504:48] wire [11:0] stq_incoming_e_0_bits_uop_br_mask = _stq_incoming_e_WIRE_bits_uop_br_mask; // @[lsu.scala:321:49, :504:48] wire [3:0] stq_incoming_e_0_bits_uop_br_tag = _stq_incoming_e_WIRE_bits_uop_br_tag; // @[lsu.scala:321:49, :504:48] wire [3:0] stq_incoming_e_0_bits_uop_br_type = _stq_incoming_e_WIRE_bits_uop_br_type; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_sfb = _stq_incoming_e_WIRE_bits_uop_is_sfb; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_fence = _stq_incoming_e_WIRE_bits_uop_is_fence; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_fencei = _stq_incoming_e_WIRE_bits_uop_is_fencei; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_sfence = _stq_incoming_e_WIRE_bits_uop_is_sfence; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_amo = _stq_incoming_e_WIRE_bits_uop_is_amo; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_eret = _stq_incoming_e_WIRE_bits_uop_is_eret; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_sys_pc2epc = _stq_incoming_e_WIRE_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_rocc = _stq_incoming_e_WIRE_bits_uop_is_rocc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_mov = _stq_incoming_e_WIRE_bits_uop_is_mov; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_ftq_idx = _stq_incoming_e_WIRE_bits_uop_ftq_idx; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_edge_inst = _stq_incoming_e_WIRE_bits_uop_edge_inst; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_pc_lob = _stq_incoming_e_WIRE_bits_uop_pc_lob; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_taken = _stq_incoming_e_WIRE_bits_uop_taken; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_imm_rename = _stq_incoming_e_WIRE_bits_uop_imm_rename; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_imm_sel = _stq_incoming_e_WIRE_bits_uop_imm_sel; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_pimm = _stq_incoming_e_WIRE_bits_uop_pimm; // @[lsu.scala:321:49, :504:48] wire [19:0] stq_incoming_e_0_bits_uop_imm_packed = _stq_incoming_e_WIRE_bits_uop_imm_packed; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_op1_sel = _stq_incoming_e_WIRE_bits_uop_op1_sel; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_op2_sel = _stq_incoming_e_WIRE_bits_uop_op2_sel; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ldst = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_wen = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ren1 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ren2 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ren3 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_swap12 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_swap23 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_fromint = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_toint = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_fma = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_div = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_sqrt = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_wflags = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_vec = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_rob_idx = _stq_incoming_e_WIRE_bits_uop_rob_idx; // @[lsu.scala:321:49, :504:48] wire [3:0] stq_incoming_e_0_bits_uop_ldq_idx = _stq_incoming_e_WIRE_bits_uop_ldq_idx; // @[lsu.scala:321:49, :504:48] wire [3:0] stq_incoming_e_0_bits_uop_stq_idx = _stq_incoming_e_WIRE_bits_uop_stq_idx; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_rxq_idx = _stq_incoming_e_WIRE_bits_uop_rxq_idx; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_pdst = _stq_incoming_e_WIRE_bits_uop_pdst; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_prs1 = _stq_incoming_e_WIRE_bits_uop_prs1; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_prs2 = _stq_incoming_e_WIRE_bits_uop_prs2; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_prs3 = _stq_incoming_e_WIRE_bits_uop_prs3; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_ppred = _stq_incoming_e_WIRE_bits_uop_ppred; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_prs1_busy = _stq_incoming_e_WIRE_bits_uop_prs1_busy; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_prs2_busy = _stq_incoming_e_WIRE_bits_uop_prs2_busy; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_prs3_busy = _stq_incoming_e_WIRE_bits_uop_prs3_busy; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_ppred_busy = _stq_incoming_e_WIRE_bits_uop_ppred_busy; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_stale_pdst = _stq_incoming_e_WIRE_bits_uop_stale_pdst; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_exception = _stq_incoming_e_WIRE_bits_uop_exception; // @[lsu.scala:321:49, :504:48] wire [63:0] stq_incoming_e_0_bits_uop_exc_cause = _stq_incoming_e_WIRE_bits_uop_exc_cause; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_mem_cmd = _stq_incoming_e_WIRE_bits_uop_mem_cmd; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_mem_size = _stq_incoming_e_WIRE_bits_uop_mem_size; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_mem_signed = _stq_incoming_e_WIRE_bits_uop_mem_signed; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_uses_ldq = _stq_incoming_e_WIRE_bits_uop_uses_ldq; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_uses_stq = _stq_incoming_e_WIRE_bits_uop_uses_stq; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_unique = _stq_incoming_e_WIRE_bits_uop_is_unique; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_flush_on_commit = _stq_incoming_e_WIRE_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_csr_cmd = _stq_incoming_e_WIRE_bits_uop_csr_cmd; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_ldst_is_rs1 = _stq_incoming_e_WIRE_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_ldst = _stq_incoming_e_WIRE_bits_uop_ldst; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_lrs1 = _stq_incoming_e_WIRE_bits_uop_lrs1; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_lrs2 = _stq_incoming_e_WIRE_bits_uop_lrs2; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_lrs3 = _stq_incoming_e_WIRE_bits_uop_lrs3; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_dst_rtype = _stq_incoming_e_WIRE_bits_uop_dst_rtype; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_lrs1_rtype = _stq_incoming_e_WIRE_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_lrs2_rtype = _stq_incoming_e_WIRE_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_frs3_en = _stq_incoming_e_WIRE_bits_uop_frs3_en; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fcn_dw = _stq_incoming_e_WIRE_bits_uop_fcn_dw; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_fcn_op = _stq_incoming_e_WIRE_bits_uop_fcn_op; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_val = _stq_incoming_e_WIRE_bits_uop_fp_val; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_fp_rm = _stq_incoming_e_WIRE_bits_uop_fp_rm; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_fp_typ = _stq_incoming_e_WIRE_bits_uop_fp_typ; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_xcpt_pf_if = _stq_incoming_e_WIRE_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_xcpt_ae_if = _stq_incoming_e_WIRE_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_xcpt_ma_if = _stq_incoming_e_WIRE_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_bp_debug_if = _stq_incoming_e_WIRE_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_bp_xcpt_if = _stq_incoming_e_WIRE_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_debug_fsrc = _stq_incoming_e_WIRE_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_debug_tsrc = _stq_incoming_e_WIRE_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_addr_valid = _stq_incoming_e_WIRE_bits_addr_valid; // @[lsu.scala:321:49, :504:48] wire [39:0] stq_incoming_e_0_bits_addr_bits = _stq_incoming_e_WIRE_bits_addr_bits; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_addr_is_virtual = _stq_incoming_e_WIRE_bits_addr_is_virtual; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_data_valid = _stq_incoming_e_WIRE_bits_data_valid; // @[lsu.scala:321:49, :504:48] wire [63:0] stq_incoming_e_0_bits_data_bits = _stq_incoming_e_WIRE_bits_data_bits; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_committed = _stq_incoming_e_WIRE_bits_committed; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_succeeded = _stq_incoming_e_WIRE_bits_succeeded; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_can_execute = _stq_incoming_e_WIRE_bits_can_execute; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_cleared = _stq_incoming_e_WIRE_bits_cleared; // @[lsu.scala:321:49, :504:48] wire [63:0] stq_incoming_e_0_bits_debug_wb_data = _stq_incoming_e_WIRE_bits_debug_wb_data; // @[lsu.scala:321:49, :504:48] wire [31:0] mem_stq_incoming_e_out_bits_uop_inst = stq_incoming_e_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_stq_incoming_e_out_bits_uop_debug_inst = stq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_rvc = stq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_stq_incoming_e_out_bits_uop_debug_pc = stq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_0 = stq_incoming_e_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_1 = stq_incoming_e_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_2 = stq_incoming_e_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_3 = stq_incoming_e_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_0 = stq_incoming_e_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_1 = stq_incoming_e_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_2 = stq_incoming_e_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_3 = stq_incoming_e_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_4 = stq_incoming_e_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_5 = stq_incoming_e_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_6 = stq_incoming_e_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_7 = stq_incoming_e_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_8 = stq_incoming_e_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_9 = stq_incoming_e_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_issued = stq_incoming_e_0_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_issued_partial_agen = stq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_issued_partial_dgen = stq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_iw_p1_speculative_child = stq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_iw_p2_speculative_child = stq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_p1_bypass_hint = stq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_p2_bypass_hint = stq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_p3_bypass_hint = stq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_dis_col_sel = stq_incoming_e_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_br_tag = stq_incoming_e_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_br_type = stq_incoming_e_0_bits_uop_br_type; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_sfb = stq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_fence = stq_incoming_e_0_bits_uop_is_fence; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_fencei = stq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_sfence = stq_incoming_e_0_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_amo = stq_incoming_e_0_bits_uop_is_amo; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_eret = stq_incoming_e_0_bits_uop_is_eret; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc = stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_rocc = stq_incoming_e_0_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_mov = stq_incoming_e_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ftq_idx = stq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_edge_inst = stq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_pc_lob = stq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_taken = stq_incoming_e_0_bits_uop_taken; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_imm_rename = stq_incoming_e_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_imm_sel = stq_incoming_e_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_pimm = stq_incoming_e_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_stq_incoming_e_out_bits_uop_imm_packed = stq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_op1_sel = stq_incoming_e_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_op2_sel = stq_incoming_e_0_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ldst = stq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_wen = stq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren1 = stq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren2 = stq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren3 = stq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap12 = stq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap23 = stq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn = stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut = stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_fromint = stq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_toint = stq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_fastpipe = stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_fma = stq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_div = stq_incoming_e_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_sqrt = stq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_wflags = stq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_vec = stq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_rob_idx = stq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_ldq_idx = stq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_stq_idx = stq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_rxq_idx = stq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_pdst = stq_incoming_e_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs1 = stq_incoming_e_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs2 = stq_incoming_e_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs3 = stq_incoming_e_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ppred = stq_incoming_e_0_bits_uop_ppred; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_prs1_busy = stq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_prs2_busy = stq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_prs3_busy = stq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_ppred_busy = stq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_stale_pdst = stq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_exception = stq_incoming_e_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_stq_incoming_e_out_bits_uop_exc_cause = stq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_mem_cmd = stq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_mem_size = stq_incoming_e_0_bits_uop_mem_size; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_mem_signed = stq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_uses_ldq = stq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_uses_stq = stq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_unique = stq_incoming_e_0_bits_uop_is_unique; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_flush_on_commit = stq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_csr_cmd = stq_incoming_e_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_ldst_is_rs1 = stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_ldst = stq_incoming_e_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs1 = stq_incoming_e_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs2 = stq_incoming_e_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs3 = stq_incoming_e_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_dst_rtype = stq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs1_rtype = stq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs2_rtype = stq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_frs3_en = stq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fcn_dw = stq_incoming_e_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_fcn_op = stq_incoming_e_0_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_val = stq_incoming_e_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_fp_rm = stq_incoming_e_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_fp_typ = stq_incoming_e_0_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_pf_if = stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ae_if = stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ma_if = stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_bp_debug_if = stq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_bp_xcpt_if = stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_debug_fsrc = stq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_debug_tsrc = stq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_addr_valid = stq_incoming_e_0_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_stq_incoming_e_out_bits_addr_bits = stq_incoming_e_0_bits_addr_bits; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_addr_is_virtual = stq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_data_valid = stq_incoming_e_0_bits_data_valid; // @[util.scala:114:23] wire [63:0] mem_stq_incoming_e_out_bits_data_bits = stq_incoming_e_0_bits_data_bits; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_committed = stq_incoming_e_0_bits_committed; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_succeeded = stq_incoming_e_0_bits_succeeded; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_can_execute = stq_incoming_e_0_bits_can_execute; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_cleared = stq_incoming_e_0_bits_cleared; // @[util.scala:114:23] wire [63:0] mem_stq_incoming_e_out_bits_debug_wb_data = stq_incoming_e_0_bits_debug_wb_data; // @[util.scala:114:23] wire ldq_wakeup_idx_block = block_load_mask_0 \| p1_block_load_mask_0; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T = ~ldq_executed_0; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_1 = ldq_addr_0_valid & _ldq_wakeup_idx_T; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_2 = ~ldq_succeeded_0; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_3 = _ldq_wakeup_idx_T_1 & _ldq_wakeup_idx_T_2; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_4 = ~ldq_addr_is_virtual_0; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_5 = _ldq_wakeup_idx_T_3 & _ldq_wakeup_idx_T_4; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_6 = ~ldq_wakeup_idx_block; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_7 = _ldq_wakeup_idx_T_5 & _ldq_wakeup_idx_T_6; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_1 = block_load_mask_1 \| p1_block_load_mask_1; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_8 = ~ldq_executed_1; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_9 = ldq_addr_1_valid & _ldq_wakeup_idx_T_8; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_10 = ~ldq_succeeded_1; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_11 = _ldq_wakeup_idx_T_9 & _ldq_wakeup_idx_T_10; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_12 = ~ldq_addr_is_virtual_1; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_13 = _ldq_wakeup_idx_T_11 & _ldq_wakeup_idx_T_12; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_14 = ~ldq_wakeup_idx_block_1; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_15 = _ldq_wakeup_idx_T_13 & _ldq_wakeup_idx_T_14; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_2 = block_load_mask_2 \| p1_block_load_mask_2; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_16 = ~ldq_executed_2; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_17 = ldq_addr_2_valid & _ldq_wakeup_idx_T_16; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_18 = ~ldq_succeeded_2; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_19 = _ldq_wakeup_idx_T_17 & _ldq_wakeup_idx_T_18; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_20 = ~ldq_addr_is_virtual_2; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_21 = _ldq_wakeup_idx_T_19 & _ldq_wakeup_idx_T_20; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_22 = ~ldq_wakeup_idx_block_2; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_23 = _ldq_wakeup_idx_T_21 & _ldq_wakeup_idx_T_22; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_3 = block_load_mask_3 \| p1_block_load_mask_3; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_24 = ~ldq_executed_3; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_25 = ldq_addr_3_valid & _ldq_wakeup_idx_T_24; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_26 = ~ldq_succeeded_3; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_27 = _ldq_wakeup_idx_T_25 & _ldq_wakeup_idx_T_26; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_28 = ~ldq_addr_is_virtual_3; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_29 = _ldq_wakeup_idx_T_27 & _ldq_wakeup_idx_T_28; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_30 = ~ldq_wakeup_idx_block_3; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_31 = _ldq_wakeup_idx_T_29 & _ldq_wakeup_idx_T_30; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_4 = block_load_mask_4 \| p1_block_load_mask_4; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_32 = ~ldq_executed_4; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_33 = ldq_addr_4_valid & _ldq_wakeup_idx_T_32; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_34 = ~ldq_succeeded_4; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_35 = _ldq_wakeup_idx_T_33 & _ldq_wakeup_idx_T_34; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_36 = ~ldq_addr_is_virtual_4; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_37 = _ldq_wakeup_idx_T_35 & _ldq_wakeup_idx_T_36; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_38 = ~ldq_wakeup_idx_block_4; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_39 = _ldq_wakeup_idx_T_37 & _ldq_wakeup_idx_T_38; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_5 = block_load_mask_5 \| p1_block_load_mask_5; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_40 = ~ldq_executed_5; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_41 = ldq_addr_5_valid & _ldq_wakeup_idx_T_40; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_42 = ~ldq_succeeded_5; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_43 = _ldq_wakeup_idx_T_41 & _ldq_wakeup_idx_T_42; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_44 = ~ldq_addr_is_virtual_5; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_45 = _ldq_wakeup_idx_T_43 & _ldq_wakeup_idx_T_44; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_46 = ~ldq_wakeup_idx_block_5; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_47 = _ldq_wakeup_idx_T_45 & _ldq_wakeup_idx_T_46; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_6 = block_load_mask_6 \| p1_block_load_mask_6; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_48 = ~ldq_executed_6; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_49 = ldq_addr_6_valid & _ldq_wakeup_idx_T_48; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_50 = ~ldq_succeeded_6; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_51 = _ldq_wakeup_idx_T_49 & _ldq_wakeup_idx_T_50; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_52 = ~ldq_addr_is_virtual_6; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_53 = _ldq_wakeup_idx_T_51 & _ldq_wakeup_idx_T_52; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_54 = ~ldq_wakeup_idx_block_6; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_55 = _ldq_wakeup_idx_T_53 & _ldq_wakeup_idx_T_54; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_7 = block_load_mask_7 \| p1_block_load_mask_7; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_56 = ~ldq_executed_7; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_57 = ldq_addr_7_valid & _ldq_wakeup_idx_T_56; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_58 = ~ldq_succeeded_7; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_59 = _ldq_wakeup_idx_T_57 & _ldq_wakeup_idx_T_58; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_60 = ~ldq_addr_is_virtual_7; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_61 = _ldq_wakeup_idx_T_59 & _ldq_wakeup_idx_T_60; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_62 = ~ldq_wakeup_idx_block_7; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_63 = _ldq_wakeup_idx_T_61 & _ldq_wakeup_idx_T_62; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_8 = block_load_mask_8 \| p1_block_load_mask_8; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_64 = ~ldq_executed_8; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_65 = ldq_addr_8_valid & _ldq_wakeup_idx_T_64; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_66 = ~ldq_succeeded_8; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_67 = _ldq_wakeup_idx_T_65 & _ldq_wakeup_idx_T_66; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_68 = ~ldq_addr_is_virtual_8; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_69 = _ldq_wakeup_idx_T_67 & _ldq_wakeup_idx_T_68; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_70 = ~ldq_wakeup_idx_block_8; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_71 = _ldq_wakeup_idx_T_69 & _ldq_wakeup_idx_T_70; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_9 = block_load_mask_9 \| p1_block_load_mask_9; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_72 = ~ldq_executed_9; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_73 = ldq_addr_9_valid & _ldq_wakeup_idx_T_72; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_74 = ~ldq_succeeded_9; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_75 = _ldq_wakeup_idx_T_73 & _ldq_wakeup_idx_T_74; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_76 = ~ldq_addr_is_virtual_9; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_77 = _ldq_wakeup_idx_T_75 & _ldq_wakeup_idx_T_76; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_78 = ~ldq_wakeup_idx_block_9; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_79 = _ldq_wakeup_idx_T_77 & _ldq_wakeup_idx_T_78; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_10 = block_load_mask_10 \| p1_block_load_mask_10; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_80 = ~ldq_executed_10; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_81 = ldq_addr_10_valid & _ldq_wakeup_idx_T_80; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_82 = ~ldq_succeeded_10; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_83 = _ldq_wakeup_idx_T_81 & _ldq_wakeup_idx_T_82; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_84 = ~ldq_addr_is_virtual_10; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_85 = _ldq_wakeup_idx_T_83 & _ldq_wakeup_idx_T_84; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_86 = ~ldq_wakeup_idx_block_10; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_87 = _ldq_wakeup_idx_T_85 & _ldq_wakeup_idx_T_86; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_11 = block_load_mask_11 \| p1_block_load_mask_11; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_88 = ~ldq_executed_11; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_89 = ldq_addr_11_valid & _ldq_wakeup_idx_T_88; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_90 = ~ldq_succeeded_11; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_91 = _ldq_wakeup_idx_T_89 & _ldq_wakeup_idx_T_90; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_92 = ~ldq_addr_is_virtual_11; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_93 = _ldq_wakeup_idx_T_91 & _ldq_wakeup_idx_T_92; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_94 = ~ldq_wakeup_idx_block_11; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_95 = _ldq_wakeup_idx_T_93 & _ldq_wakeup_idx_T_94; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_12 = block_load_mask_12 \| p1_block_load_mask_12; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_96 = ~ldq_executed_12; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_97 = ldq_addr_12_valid & _ldq_wakeup_idx_T_96; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_98 = ~ldq_succeeded_12; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_99 = _ldq_wakeup_idx_T_97 & _ldq_wakeup_idx_T_98; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_100 = ~ldq_addr_is_virtual_12; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_101 = _ldq_wakeup_idx_T_99 & _ldq_wakeup_idx_T_100; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_102 = ~ldq_wakeup_idx_block_12; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_103 = _ldq_wakeup_idx_T_101 & _ldq_wakeup_idx_T_102; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_13 = block_load_mask_13 \| p1_block_load_mask_13; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_104 = ~ldq_executed_13; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_105 = ldq_addr_13_valid & _ldq_wakeup_idx_T_104; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_106 = ~ldq_succeeded_13; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_107 = _ldq_wakeup_idx_T_105 & _ldq_wakeup_idx_T_106; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_108 = ~ldq_addr_is_virtual_13; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_109 = _ldq_wakeup_idx_T_107 & _ldq_wakeup_idx_T_108; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_110 = ~ldq_wakeup_idx_block_13; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_111 = _ldq_wakeup_idx_T_109 & _ldq_wakeup_idx_T_110; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_14 = block_load_mask_14 \| p1_block_load_mask_14; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_112 = ~ldq_executed_14; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_113 = ldq_addr_14_valid & _ldq_wakeup_idx_T_112; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_114 = ~ldq_succeeded_14; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_115 = _ldq_wakeup_idx_T_113 & _ldq_wakeup_idx_T_114; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_116 = ~ldq_addr_is_virtual_14; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_117 = _ldq_wakeup_idx_T_115 & _ldq_wakeup_idx_T_116; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_118 = ~ldq_wakeup_idx_block_14; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_119 = _ldq_wakeup_idx_T_117 & _ldq_wakeup_idx_T_118; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_15 = block_load_mask_15 \| p1_block_load_mask_15; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_120 = ~ldq_executed_15; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_121 = ldq_addr_15_valid & _ldq_wakeup_idx_T_120; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_122 = ~ldq_succeeded_15; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_123 = _ldq_wakeup_idx_T_121 & _ldq_wakeup_idx_T_122; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_124 = ~ldq_addr_is_virtual_15; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_125 = _ldq_wakeup_idx_T_123 & _ldq_wakeup_idx_T_124; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_126 = ~ldq_wakeup_idx_block_15; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_127 = _ldq_wakeup_idx_T_125 & _ldq_wakeup_idx_T_126; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_temp_vec_15 = _ldq_wakeup_idx_T_127; // @[util.scala:352:65] wire _GEN_321 = ldq_head == 4'h0; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T = _GEN_321; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T = _GEN_321; // @[util.scala:352:72] wire _l_idx_temp_vec_T; // @[util.scala:352:72] assign _l_idx_temp_vec_T = _GEN_321; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_0 = _ldq_wakeup_idx_T_7 & _ldq_wakeup_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire _GEN_322 = ldq_head < 4'h2; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_1 = _GEN_322; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_1 = _GEN_322; // @[util.scala:352:72] wire _l_idx_temp_vec_T_1; // @[util.scala:352:72] assign _l_idx_temp_vec_T_1 = _GEN_322; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_1 = _ldq_wakeup_idx_T_15 & _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire _GEN_323 = ldq_head < 4'h3; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_2 = _GEN_323; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_2 = _GEN_323; // @[util.scala:352:72] wire _l_idx_temp_vec_T_2; // @[util.scala:352:72] assign _l_idx_temp_vec_T_2 = _GEN_323; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_2 = _ldq_wakeup_idx_T_23 & _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire _GEN_324 = ldq_head < 4'h4; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_3 = _GEN_324; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_3 = _GEN_324; // @[util.scala:352:72] wire _l_idx_temp_vec_T_3; // @[util.scala:352:72] assign _l_idx_temp_vec_T_3 = _GEN_324; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_3 = _ldq_wakeup_idx_T_31 & _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire _GEN_325 = ldq_head < 4'h5; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_4 = _GEN_325; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_4 = _GEN_325; // @[util.scala:352:72] wire _l_idx_temp_vec_T_4; // @[util.scala:352:72] assign _l_idx_temp_vec_T_4 = _GEN_325; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_4 = _ldq_wakeup_idx_T_39 & _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire _GEN_326 = ldq_head < 4'h6; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_5 = _GEN_326; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_5 = _GEN_326; // @[util.scala:352:72] wire _l_idx_temp_vec_T_5; // @[util.scala:352:72] assign _l_idx_temp_vec_T_5 = _GEN_326; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_5 = _ldq_wakeup_idx_T_47 & _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire _GEN_327 = ldq_head < 4'h7; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_6 = _GEN_327; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_6 = _GEN_327; // @[util.scala:352:72] wire _l_idx_temp_vec_T_6; // @[util.scala:352:72] assign _l_idx_temp_vec_T_6 = _GEN_327; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_6 = _ldq_wakeup_idx_T_55 & _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _ldq_wakeup_idx_temp_vec_T_7 = ~(ldq_head[3]); // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_7 = _ldq_wakeup_idx_T_63 & _ldq_wakeup_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire _GEN_328 = ldq_head < 4'h9; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_8; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_8 = _GEN_328; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_8 = _GEN_328; // @[util.scala:352:72] wire _l_idx_temp_vec_T_8; // @[util.scala:352:72] assign _l_idx_temp_vec_T_8 = _GEN_328; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_8 = _ldq_wakeup_idx_T_71 & _ldq_wakeup_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire _GEN_329 = ldq_head < 4'hA; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_9; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_9 = _GEN_329; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_9 = _GEN_329; // @[util.scala:352:72] wire _l_idx_temp_vec_T_9; // @[util.scala:352:72] assign _l_idx_temp_vec_T_9 = _GEN_329; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_9 = _ldq_wakeup_idx_T_79 & _ldq_wakeup_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire _GEN_330 = ldq_head < 4'hB; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_10; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_10 = _GEN_330; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_10 = _GEN_330; // @[util.scala:352:72] wire _l_idx_temp_vec_T_10; // @[util.scala:352:72] assign _l_idx_temp_vec_T_10 = _GEN_330; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_10 = _ldq_wakeup_idx_T_87 & _ldq_wakeup_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire _GEN_331 = ldq_head[3:2] != 2'h3; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_11; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_11 = _GEN_331; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_11 = _GEN_331; // @[util.scala:352:72] wire _l_idx_temp_vec_T_11; // @[util.scala:352:72] assign _l_idx_temp_vec_T_11 = _GEN_331; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_11 = _ldq_wakeup_idx_T_95 & _ldq_wakeup_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire _GEN_332 = ldq_head < 4'hD; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_12; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_12 = _GEN_332; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_12 = _GEN_332; // @[util.scala:352:72] wire _l_idx_temp_vec_T_12; // @[util.scala:352:72] assign _l_idx_temp_vec_T_12 = _GEN_332; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_12 = _ldq_wakeup_idx_T_103 & _ldq_wakeup_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire _GEN_333 = ldq_head[3:1] != 3'h7; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_13; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_13 = _GEN_333; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_13 = _GEN_333; // @[util.scala:352:72] wire _l_idx_temp_vec_T_13; // @[util.scala:352:72] assign _l_idx_temp_vec_T_13 = _GEN_333; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_13 = _ldq_wakeup_idx_T_111 & _ldq_wakeup_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire _GEN_334 = ldq_head != 4'hF; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_14; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_14 = _GEN_334; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_14 = _GEN_334; // @[util.scala:352:72] wire _l_idx_temp_vec_T_14; // @[util.scala:352:72] assign _l_idx_temp_vec_T_14 = _GEN_334; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_14 = _ldq_wakeup_idx_T_119 & _ldq_wakeup_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire [4:0] _ldq_wakeup_idx_idx_T = {4'hF, ~_ldq_wakeup_idx_T_119}; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_1 = _ldq_wakeup_idx_T_111 ? 5'h1D : _ldq_wakeup_idx_idx_T; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_2 = _ldq_wakeup_idx_T_103 ? 5'h1C : _ldq_wakeup_idx_idx_T_1; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_3 = _ldq_wakeup_idx_T_95 ? 5'h1B : _ldq_wakeup_idx_idx_T_2; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_4 = _ldq_wakeup_idx_T_87 ? 5'h1A : _ldq_wakeup_idx_idx_T_3; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_5 = _ldq_wakeup_idx_T_79 ? 5'h19 : _ldq_wakeup_idx_idx_T_4; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_6 = _ldq_wakeup_idx_T_71 ? 5'h18 : _ldq_wakeup_idx_idx_T_5; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_7 = _ldq_wakeup_idx_T_63 ? 5'h17 : _ldq_wakeup_idx_idx_T_6; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_8 = _ldq_wakeup_idx_T_55 ? 5'h16 : _ldq_wakeup_idx_idx_T_7; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_9 = _ldq_wakeup_idx_T_47 ? 5'h15 : _ldq_wakeup_idx_idx_T_8; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_10 = _ldq_wakeup_idx_T_39 ? 5'h14 : _ldq_wakeup_idx_idx_T_9; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_11 = _ldq_wakeup_idx_T_31 ? 5'h13 : _ldq_wakeup_idx_idx_T_10; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_12 = _ldq_wakeup_idx_T_23 ? 5'h12 : _ldq_wakeup_idx_idx_T_11; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_13 = _ldq_wakeup_idx_T_15 ? 5'h11 : _ldq_wakeup_idx_idx_T_12; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_14 = _ldq_wakeup_idx_T_7 ? 5'h10 : _ldq_wakeup_idx_idx_T_13; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_15 = ldq_wakeup_idx_temp_vec_15 ? 5'hF : _ldq_wakeup_idx_idx_T_14; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_16 = ldq_wakeup_idx_temp_vec_14 ? 5'hE : _ldq_wakeup_idx_idx_T_15; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_17 = ldq_wakeup_idx_temp_vec_13 ? 5'hD : _ldq_wakeup_idx_idx_T_16; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_18 = ldq_wakeup_idx_temp_vec_12 ? 5'hC : _ldq_wakeup_idx_idx_T_17; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_19 = ldq_wakeup_idx_temp_vec_11 ? 5'hB : _ldq_wakeup_idx_idx_T_18; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_20 = ldq_wakeup_idx_temp_vec_10 ? 5'hA : _ldq_wakeup_idx_idx_T_19; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_21 = ldq_wakeup_idx_temp_vec_9 ? 5'h9 : _ldq_wakeup_idx_idx_T_20; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_22 = ldq_wakeup_idx_temp_vec_8 ? 5'h8 : _ldq_wakeup_idx_idx_T_21; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_23 = ldq_wakeup_idx_temp_vec_7 ? 5'h7 : _ldq_wakeup_idx_idx_T_22; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_24 = ldq_wakeup_idx_temp_vec_6 ? 5'h6 : _ldq_wakeup_idx_idx_T_23; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_25 = ldq_wakeup_idx_temp_vec_5 ? 5'h5 : _ldq_wakeup_idx_idx_T_24; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_26 = ldq_wakeup_idx_temp_vec_4 ? 5'h4 : _ldq_wakeup_idx_idx_T_25; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_27 = ldq_wakeup_idx_temp_vec_3 ? 5'h3 : _ldq_wakeup_idx_idx_T_26; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_28 = ldq_wakeup_idx_temp_vec_2 ? 5'h2 : _ldq_wakeup_idx_idx_T_27; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_29 = ldq_wakeup_idx_temp_vec_1 ? 5'h1 : _ldq_wakeup_idx_idx_T_28; // @[Mux.scala:50:70] wire [4:0] ldq_wakeup_idx_idx = ldq_wakeup_idx_temp_vec_0 ? 5'h0 : _ldq_wakeup_idx_idx_T_29; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_T_128 = ldq_wakeup_idx_idx[3:0]; // @[Mux.scala:50:70] reg [3:0] ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_valid_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_uop_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_addr_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_addr_is_virtual_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_addr_is_uncacheable_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_executed_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_succeeded_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_order_fail_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_observed_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_st_dep_mask_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_ld_byte_mask_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_forward_std_val_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_forward_stq_idx_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_debug_wb_data_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _can_fire_load_wakeup_T_9 = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _can_fire_load_wakeup_T_13 = ldq_wakeup_idx; // @[lsu.scala:506:31] wire ldq_wakeup_e_valid = ldq_wakeup_e_e_valid; // @[lsu.scala:233:17, :510:32] wire [31:0] ldq_wakeup_e_bits_uop_inst = ldq_wakeup_e_e_bits_uop_inst; // @[lsu.scala:233:17, :510:32] wire [31:0] ldq_wakeup_e_bits_uop_debug_inst = ldq_wakeup_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_rvc = ldq_wakeup_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17, :510:32] wire [39:0] ldq_wakeup_e_bits_uop_debug_pc = ldq_wakeup_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_0 = ldq_wakeup_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_1 = ldq_wakeup_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_2 = ldq_wakeup_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_3 = ldq_wakeup_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_0 = ldq_wakeup_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_1 = ldq_wakeup_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_2 = ldq_wakeup_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_3 = ldq_wakeup_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_4 = ldq_wakeup_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_5 = ldq_wakeup_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_6 = ldq_wakeup_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_7 = ldq_wakeup_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_8 = ldq_wakeup_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_9 = ldq_wakeup_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_issued = ldq_wakeup_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_issued_partial_agen = ldq_wakeup_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_issued_partial_dgen = ldq_wakeup_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_iw_p1_speculative_child = ldq_wakeup_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_iw_p2_speculative_child = ldq_wakeup_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_p1_bypass_hint = ldq_wakeup_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_p2_bypass_hint = ldq_wakeup_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_p3_bypass_hint = ldq_wakeup_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_dis_col_sel = ldq_wakeup_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17, :510:32] wire [11:0] ldq_wakeup_e_bits_uop_br_mask = ldq_wakeup_e_e_bits_uop_br_mask; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_uop_br_tag = ldq_wakeup_e_e_bits_uop_br_tag; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_uop_br_type = ldq_wakeup_e_e_bits_uop_br_type; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_sfb = ldq_wakeup_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_fence = ldq_wakeup_e_e_bits_uop_is_fence; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_fencei = ldq_wakeup_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_sfence = ldq_wakeup_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_amo = ldq_wakeup_e_e_bits_uop_is_amo; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_eret = ldq_wakeup_e_e_bits_uop_is_eret; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_sys_pc2epc = ldq_wakeup_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_rocc = ldq_wakeup_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_mov = ldq_wakeup_e_e_bits_uop_is_mov; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_ftq_idx = ldq_wakeup_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_edge_inst = ldq_wakeup_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_pc_lob = ldq_wakeup_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_taken = ldq_wakeup_e_e_bits_uop_taken; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_imm_rename = ldq_wakeup_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_imm_sel = ldq_wakeup_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_pimm = ldq_wakeup_e_e_bits_uop_pimm; // @[lsu.scala:233:17, :510:32] wire [19:0] ldq_wakeup_e_bits_uop_imm_packed = ldq_wakeup_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_op1_sel = ldq_wakeup_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_op2_sel = ldq_wakeup_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ldst = ldq_wakeup_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_wen = ldq_wakeup_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ren1 = ldq_wakeup_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ren2 = ldq_wakeup_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ren3 = ldq_wakeup_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_swap12 = ldq_wakeup_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_swap23 = ldq_wakeup_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn = ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut = ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_fromint = ldq_wakeup_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_toint = ldq_wakeup_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe = ldq_wakeup_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_fma = ldq_wakeup_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_div = ldq_wakeup_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_sqrt = ldq_wakeup_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_wflags = ldq_wakeup_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_vec = ldq_wakeup_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_rob_idx = ldq_wakeup_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_uop_ldq_idx = ldq_wakeup_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_uop_stq_idx = ldq_wakeup_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_rxq_idx = ldq_wakeup_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_pdst = ldq_wakeup_e_e_bits_uop_pdst; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_prs1 = ldq_wakeup_e_e_bits_uop_prs1; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_prs2 = ldq_wakeup_e_e_bits_uop_prs2; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_prs3 = ldq_wakeup_e_e_bits_uop_prs3; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_ppred = ldq_wakeup_e_e_bits_uop_ppred; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_prs1_busy = ldq_wakeup_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_prs2_busy = ldq_wakeup_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_prs3_busy = ldq_wakeup_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_ppred_busy = ldq_wakeup_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_stale_pdst = ldq_wakeup_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_exception = ldq_wakeup_e_e_bits_uop_exception; // @[lsu.scala:233:17, :510:32] wire [63:0] ldq_wakeup_e_bits_uop_exc_cause = ldq_wakeup_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_mem_cmd = ldq_wakeup_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_mem_size = ldq_wakeup_e_e_bits_uop_mem_size; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_mem_signed = ldq_wakeup_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_uses_ldq = ldq_wakeup_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_uses_stq = ldq_wakeup_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_unique = ldq_wakeup_e_e_bits_uop_is_unique; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_flush_on_commit = ldq_wakeup_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_csr_cmd = ldq_wakeup_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_ldst_is_rs1 = ldq_wakeup_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_ldst = ldq_wakeup_e_e_bits_uop_ldst; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_lrs1 = ldq_wakeup_e_e_bits_uop_lrs1; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_lrs2 = ldq_wakeup_e_e_bits_uop_lrs2; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_lrs3 = ldq_wakeup_e_e_bits_uop_lrs3; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_dst_rtype = ldq_wakeup_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_lrs1_rtype = ldq_wakeup_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_lrs2_rtype = ldq_wakeup_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_frs3_en = ldq_wakeup_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fcn_dw = ldq_wakeup_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_fcn_op = ldq_wakeup_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_val = ldq_wakeup_e_e_bits_uop_fp_val; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_fp_rm = ldq_wakeup_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_fp_typ = ldq_wakeup_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_xcpt_pf_if = ldq_wakeup_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_xcpt_ae_if = ldq_wakeup_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_xcpt_ma_if = ldq_wakeup_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_bp_debug_if = ldq_wakeup_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_bp_xcpt_if = ldq_wakeup_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_debug_fsrc = ldq_wakeup_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_debug_tsrc = ldq_wakeup_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_addr_valid = ldq_wakeup_e_e_bits_addr_valid; // @[lsu.scala:233:17, :510:32] wire [39:0] ldq_wakeup_e_bits_addr_bits = ldq_wakeup_e_e_bits_addr_bits; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_addr_is_virtual = ldq_wakeup_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_addr_is_uncacheable = ldq_wakeup_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_executed = ldq_wakeup_e_e_bits_executed; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_succeeded = ldq_wakeup_e_e_bits_succeeded; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_order_fail = ldq_wakeup_e_e_bits_order_fail; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_observed = ldq_wakeup_e_e_bits_observed; // @[lsu.scala:233:17, :510:32] wire [15:0] ldq_wakeup_e_bits_st_dep_mask = ldq_wakeup_e_e_bits_st_dep_mask; // @[lsu.scala:233:17, :510:32] wire [7:0] ldq_wakeup_e_bits_ld_byte_mask = ldq_wakeup_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_forward_std_val = ldq_wakeup_e_e_bits_forward_std_val; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_forward_stq_idx = ldq_wakeup_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17, :510:32] wire [63:0] ldq_wakeup_e_bits_debug_wb_data = ldq_wakeup_e_e_bits_debug_wb_data; // @[lsu.scala:233:17, :510:32] wire [3:0] _ldq_wakeup_e_e_valid_T_1 = _ldq_wakeup_e_e_valid_T; assign ldq_wakeup_e_e_valid = _GEN_25[_ldq_wakeup_e_e_valid_T_1]; // @[lsu.scala:233:17, :234:32, :387:15] wire [3:0] _ldq_wakeup_e_e_bits_uop_T_1 = _ldq_wakeup_e_e_bits_uop_T; assign ldq_wakeup_e_e_bits_uop_inst = _GEN_76[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_inst = _GEN_77[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_rvc = _GEN_78[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_pc = _GEN_79[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_0 = _GEN_80[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_1 = _GEN_81[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_2 = _GEN_82[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_3 = _GEN_83[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_0 = _GEN_84[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_1 = _GEN_85[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_2 = _GEN_86[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_3 = _GEN_87[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_4 = _GEN_88[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_5 = _GEN_89[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_6 = _GEN_90[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_7 = _GEN_91[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_8 = _GEN_92[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_9 = _GEN_93[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_issued = _GEN_94[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_issued_partial_agen = _GEN_95[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_issued_partial_dgen = _GEN_96[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p1_speculative_child = _GEN_97[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p2_speculative_child = _GEN_98[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p1_bypass_hint = _GEN_99[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p2_bypass_hint = _GEN_100[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p3_bypass_hint = _GEN_101[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_dis_col_sel = _GEN_102[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_br_mask = _GEN_103[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_br_tag = _GEN_104[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_br_type = _GEN_105[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_sfb = _GEN_106[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_fence = _GEN_107[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_fencei = _GEN_108[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_sfence = _GEN_109[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_amo = _GEN_110[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_eret = _GEN_111[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_sys_pc2epc = _GEN_112[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_rocc = _GEN_113[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_mov = _GEN_114[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ftq_idx = _GEN_115[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_edge_inst = _GEN_116[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_pc_lob = _GEN_117[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_taken = _GEN_118[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_imm_rename = _GEN_119[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_imm_sel = _GEN_120[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_pimm = _GEN_121[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_imm_packed = _GEN_122[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_op1_sel = _GEN_123[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_op2_sel = _GEN_124[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ldst = _GEN_125[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_wen = _GEN_126[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ren1 = _GEN_127[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ren2 = _GEN_128[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ren3 = _GEN_129[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_swap12 = _GEN_130[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_swap23 = _GEN_131[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_132[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_133[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_fromint = _GEN_134[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_toint = _GEN_135[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_136[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_fma = _GEN_137[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_div = _GEN_138[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_sqrt = _GEN_139[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_wflags = _GEN_140[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_vec = _GEN_141[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_rob_idx = _GEN_142[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ldq_idx = _GEN_143[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_stq_idx = _GEN_144[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_rxq_idx = _GEN_145[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_pdst = _GEN_146[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs1 = _GEN_147[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs2 = _GEN_148[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs3 = _GEN_149[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ppred = _GEN_150[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs1_busy = _GEN_151[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs2_busy = _GEN_152[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs3_busy = _GEN_153[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ppred_busy = _GEN_154[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_stale_pdst = _GEN_155[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_exception = _GEN_156[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_exc_cause = _GEN_157[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_mem_cmd = _GEN_158[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_mem_size = _GEN_159[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_mem_signed = _GEN_160[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_uses_ldq = _GEN_161[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_uses_stq = _GEN_162[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_unique = _GEN_163[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_flush_on_commit = _GEN_164[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_csr_cmd = _GEN_165[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ldst_is_rs1 = _GEN_166[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ldst = _GEN_167[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs1 = _GEN_168[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs2 = _GEN_169[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs3 = _GEN_170[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_dst_rtype = _GEN_171[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs1_rtype = _GEN_172[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs2_rtype = _GEN_173[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_frs3_en = _GEN_174[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fcn_dw = _GEN_175[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fcn_op = _GEN_176[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_val = _GEN_177[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_rm = _GEN_178[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_typ = _GEN_179[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_xcpt_pf_if = _GEN_180[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_xcpt_ae_if = _GEN_181[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_xcpt_ma_if = _GEN_182[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_bp_debug_if = _GEN_183[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_bp_xcpt_if = _GEN_184[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_fsrc = _GEN_185[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_tsrc = _GEN_186[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] wire [3:0] _ldq_wakeup_e_e_bits_addr_T_1 = _ldq_wakeup_e_e_bits_addr_T; assign ldq_wakeup_e_e_bits_addr_valid = _GEN_187[_ldq_wakeup_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] assign ldq_wakeup_e_e_bits_addr_bits = _GEN_188[_ldq_wakeup_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] wire [3:0] _ldq_wakeup_e_e_bits_addr_is_virtual_T_1 = _ldq_wakeup_e_e_bits_addr_is_virtual_T; assign ldq_wakeup_e_e_bits_addr_is_virtual = _GEN_189[_ldq_wakeup_e_e_bits_addr_is_virtual_T_1]; // @[lsu.scala:233:17, :237:32] wire [3:0] _ldq_wakeup_e_e_bits_addr_is_uncacheable_T_1 = _ldq_wakeup_e_e_bits_addr_is_uncacheable_T; assign ldq_wakeup_e_e_bits_addr_is_uncacheable = _GEN_190[_ldq_wakeup_e_e_bits_addr_is_uncacheable_T_1]; // @[lsu.scala:233:17, :238:32] wire [3:0] _ldq_wakeup_e_e_bits_executed_T_1 = _ldq_wakeup_e_e_bits_executed_T; assign ldq_wakeup_e_e_bits_executed = _GEN_191[_ldq_wakeup_e_e_bits_executed_T_1]; // @[lsu.scala:233:17, :239:32] wire [3:0] _ldq_wakeup_e_e_bits_succeeded_T_1 = _ldq_wakeup_e_e_bits_succeeded_T; assign ldq_wakeup_e_e_bits_succeeded = _GEN_192[_ldq_wakeup_e_e_bits_succeeded_T_1]; // @[lsu.scala:233:17, :240:32] wire [3:0] _ldq_wakeup_e_e_bits_order_fail_T_1 = _ldq_wakeup_e_e_bits_order_fail_T; assign ldq_wakeup_e_e_bits_order_fail = _GEN_193[_ldq_wakeup_e_e_bits_order_fail_T_1]; // @[lsu.scala:233:17, :241:32] wire [3:0] _ldq_wakeup_e_e_bits_observed_T_1 = _ldq_wakeup_e_e_bits_observed_T; assign ldq_wakeup_e_e_bits_observed = _GEN_194[_ldq_wakeup_e_e_bits_observed_T_1]; // @[lsu.scala:233:17, :242:32] wire [3:0] _ldq_wakeup_e_e_bits_st_dep_mask_T_1 = _ldq_wakeup_e_e_bits_st_dep_mask_T; assign ldq_wakeup_e_e_bits_st_dep_mask = _GEN_195[_ldq_wakeup_e_e_bits_st_dep_mask_T_1]; // @[lsu.scala:233:17, :243:32] wire [3:0] _ldq_wakeup_e_e_bits_ld_byte_mask_T_1 = _ldq_wakeup_e_e_bits_ld_byte_mask_T; assign ldq_wakeup_e_e_bits_ld_byte_mask = _GEN_196[_ldq_wakeup_e_e_bits_ld_byte_mask_T_1]; // @[lsu.scala:233:17, :244:32] wire [3:0] _ldq_wakeup_e_e_bits_forward_std_val_T_1 = _ldq_wakeup_e_e_bits_forward_std_val_T; assign ldq_wakeup_e_e_bits_forward_std_val = _GEN_197[_ldq_wakeup_e_e_bits_forward_std_val_T_1]; // @[lsu.scala:233:17, :245:32] wire [3:0] _ldq_wakeup_e_e_bits_forward_stq_idx_T_1 = _ldq_wakeup_e_e_bits_forward_stq_idx_T; assign ldq_wakeup_e_e_bits_forward_stq_idx = _GEN_198[_ldq_wakeup_e_e_bits_forward_stq_idx_T_1]; // @[lsu.scala:233:17, :246:32] wire [3:0] _ldq_wakeup_e_e_bits_debug_wb_data_T_1 = _ldq_wakeup_e_e_bits_debug_wb_data_T; assign ldq_wakeup_e_e_bits_debug_wb_data = _GEN_199[_ldq_wakeup_e_e_bits_debug_wb_data_T_1]; // @[lsu.scala:233:17, :247:32] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_inst = ldq_wakeup_e_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_debug_inst = ldq_wakeup_e_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_rvc = ldq_wakeup_e_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_ldq_wakeup_e_out_bits_uop_debug_pc = ldq_wakeup_e_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_0 = ldq_wakeup_e_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_1 = ldq_wakeup_e_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_2 = ldq_wakeup_e_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_3 = ldq_wakeup_e_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_0 = ldq_wakeup_e_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_1 = ldq_wakeup_e_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_2 = ldq_wakeup_e_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_3 = ldq_wakeup_e_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_4 = ldq_wakeup_e_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_5 = ldq_wakeup_e_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_6 = ldq_wakeup_e_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_7 = ldq_wakeup_e_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_8 = ldq_wakeup_e_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_9 = ldq_wakeup_e_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_issued = ldq_wakeup_e_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_issued_partial_agen = ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_issued_partial_dgen = ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_iw_p1_speculative_child = ldq_wakeup_e_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_iw_p2_speculative_child = ldq_wakeup_e_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p1_bypass_hint = ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p2_bypass_hint = ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p3_bypass_hint = ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_dis_col_sel = ldq_wakeup_e_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_br_tag = ldq_wakeup_e_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_br_type = ldq_wakeup_e_bits_uop_br_type; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sfb = ldq_wakeup_e_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fence = ldq_wakeup_e_bits_uop_is_fence; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fencei = ldq_wakeup_e_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sfence = ldq_wakeup_e_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_amo = ldq_wakeup_e_bits_uop_is_amo; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_eret = ldq_wakeup_e_bits_uop_is_eret; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sys_pc2epc = ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_rocc = ldq_wakeup_e_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_mov = ldq_wakeup_e_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ftq_idx = ldq_wakeup_e_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_edge_inst = ldq_wakeup_e_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_pc_lob = ldq_wakeup_e_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_taken = ldq_wakeup_e_bits_uop_taken; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_imm_rename = ldq_wakeup_e_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_imm_sel = ldq_wakeup_e_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_pimm = ldq_wakeup_e_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_ldq_wakeup_e_out_bits_uop_imm_packed = ldq_wakeup_e_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_op1_sel = ldq_wakeup_e_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_op2_sel = ldq_wakeup_e_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ldst = ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_wen = ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ren1 = ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ren2 = ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ren3 = ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_swap12 = ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_swap23 = ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_typeTagIn = ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_typeTagOut = ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_fromint = ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_toint = ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_fastpipe = ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_fma = ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_div = ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_sqrt = ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_wflags = ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_vec = ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_rob_idx = ldq_wakeup_e_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_ldq_idx = ldq_wakeup_e_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_stq_idx = ldq_wakeup_e_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_rxq_idx = ldq_wakeup_e_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_pdst = ldq_wakeup_e_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs1 = ldq_wakeup_e_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs2 = ldq_wakeup_e_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs3 = ldq_wakeup_e_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ppred = ldq_wakeup_e_bits_uop_ppred; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_prs1_busy = ldq_wakeup_e_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_prs2_busy = ldq_wakeup_e_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_prs3_busy = ldq_wakeup_e_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_ppred_busy = ldq_wakeup_e_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_stale_pdst = ldq_wakeup_e_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_exception = ldq_wakeup_e_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_ldq_wakeup_e_out_bits_uop_exc_cause = ldq_wakeup_e_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_mem_cmd = ldq_wakeup_e_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_mem_size = ldq_wakeup_e_bits_uop_mem_size; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_mem_signed = ldq_wakeup_e_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_ldq = ldq_wakeup_e_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_stq = ldq_wakeup_e_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_unique = ldq_wakeup_e_bits_uop_is_unique; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_flush_on_commit = ldq_wakeup_e_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_csr_cmd = ldq_wakeup_e_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_ldst_is_rs1 = ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_ldst = ldq_wakeup_e_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs1 = ldq_wakeup_e_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs2 = ldq_wakeup_e_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs3 = ldq_wakeup_e_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_dst_rtype = ldq_wakeup_e_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs1_rtype = ldq_wakeup_e_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs2_rtype = ldq_wakeup_e_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_frs3_en = ldq_wakeup_e_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fcn_dw = ldq_wakeup_e_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_fcn_op = ldq_wakeup_e_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_val = ldq_wakeup_e_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_fp_rm = ldq_wakeup_e_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_fp_typ = ldq_wakeup_e_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_pf_if = ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ae_if = ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ma_if = ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_debug_if = ldq_wakeup_e_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_xcpt_if = ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_debug_fsrc = ldq_wakeup_e_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_debug_tsrc = ldq_wakeup_e_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_addr_valid = ldq_wakeup_e_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_ldq_wakeup_e_out_bits_addr_bits = ldq_wakeup_e_bits_addr_bits; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_addr_is_virtual = ldq_wakeup_e_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_addr_is_uncacheable = ldq_wakeup_e_bits_addr_is_uncacheable; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_executed = ldq_wakeup_e_bits_executed; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_succeeded = ldq_wakeup_e_bits_succeeded; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_order_fail = ldq_wakeup_e_bits_order_fail; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_observed = ldq_wakeup_e_bits_observed; // @[util.scala:114:23] wire [15:0] mem_ldq_wakeup_e_out_bits_st_dep_mask = ldq_wakeup_e_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] mem_ldq_wakeup_e_out_bits_ld_byte_mask = ldq_wakeup_e_bits_ld_byte_mask; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_forward_std_val = ldq_wakeup_e_bits_forward_std_val; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_forward_stq_idx = ldq_wakeup_e_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] mem_ldq_wakeup_e_out_bits_debug_wb_data = ldq_wakeup_e_bits_debug_wb_data; // @[util.scala:114:23] reg [3:0] ldq_enq_retry_idx; // @[lsu.scala:514:30] wire _ldq_enq_retry_idx_T = ldq_addr_0_valid & ldq_addr_is_virtual_0; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_1 = \|ldq_enq_retry_idx; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_2 = _ldq_enq_retry_idx_T & _ldq_enq_retry_idx_T_1; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_3 = ldq_addr_1_valid & ldq_addr_is_virtual_1; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_4 = ldq_enq_retry_idx != 4'h1; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_5 = _ldq_enq_retry_idx_T_3 & _ldq_enq_retry_idx_T_4; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_6 = ldq_addr_2_valid & ldq_addr_is_virtual_2; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_7 = ldq_enq_retry_idx != 4'h2; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_8 = _ldq_enq_retry_idx_T_6 & _ldq_enq_retry_idx_T_7; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_9 = ldq_addr_3_valid & ldq_addr_is_virtual_3; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_10 = ldq_enq_retry_idx != 4'h3; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_11 = _ldq_enq_retry_idx_T_9 & _ldq_enq_retry_idx_T_10; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_12 = ldq_addr_4_valid & ldq_addr_is_virtual_4; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_13 = ldq_enq_retry_idx != 4'h4; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_14 = _ldq_enq_retry_idx_T_12 & _ldq_enq_retry_idx_T_13; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_15 = ldq_addr_5_valid & ldq_addr_is_virtual_5; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_16 = ldq_enq_retry_idx != 4'h5; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_17 = _ldq_enq_retry_idx_T_15 & _ldq_enq_retry_idx_T_16; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_18 = ldq_addr_6_valid & ldq_addr_is_virtual_6; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_19 = ldq_enq_retry_idx != 4'h6; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_20 = _ldq_enq_retry_idx_T_18 & _ldq_enq_retry_idx_T_19; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_21 = ldq_addr_7_valid & ldq_addr_is_virtual_7; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_22 = ldq_enq_retry_idx != 4'h7; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_23 = _ldq_enq_retry_idx_T_21 & _ldq_enq_retry_idx_T_22; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_24 = ldq_addr_8_valid & ldq_addr_is_virtual_8; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_25 = ldq_enq_retry_idx != 4'h8; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_26 = _ldq_enq_retry_idx_T_24 & _ldq_enq_retry_idx_T_25; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_27 = ldq_addr_9_valid & ldq_addr_is_virtual_9; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_28 = ldq_enq_retry_idx != 4'h9; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_29 = _ldq_enq_retry_idx_T_27 & _ldq_enq_retry_idx_T_28; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_30 = ldq_addr_10_valid & ldq_addr_is_virtual_10; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_31 = ldq_enq_retry_idx != 4'hA; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_32 = _ldq_enq_retry_idx_T_30 & _ldq_enq_retry_idx_T_31; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_33 = ldq_addr_11_valid & ldq_addr_is_virtual_11; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_34 = ldq_enq_retry_idx != 4'hB; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_35 = _ldq_enq_retry_idx_T_33 & _ldq_enq_retry_idx_T_34; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_36 = ldq_addr_12_valid & ldq_addr_is_virtual_12; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_37 = ldq_enq_retry_idx != 4'hC; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_38 = _ldq_enq_retry_idx_T_36 & _ldq_enq_retry_idx_T_37; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_39 = ldq_addr_13_valid & ldq_addr_is_virtual_13; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_40 = ldq_enq_retry_idx != 4'hD; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_41 = _ldq_enq_retry_idx_T_39 & _ldq_enq_retry_idx_T_40; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_42 = ldq_addr_14_valid & ldq_addr_is_virtual_14; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_43 = ldq_enq_retry_idx != 4'hE; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_44 = _ldq_enq_retry_idx_T_42 & _ldq_enq_retry_idx_T_43; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_45 = ldq_addr_15_valid & ldq_addr_is_virtual_15; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_46 = ~(&ldq_enq_retry_idx); // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_47 = _ldq_enq_retry_idx_T_45 & _ldq_enq_retry_idx_T_46; // @[lsu.scala:516:{23,49,57}] wire ldq_enq_retry_idx_temp_vec_15 = _ldq_enq_retry_idx_T_47; // @[util.scala:352:65] wire ldq_enq_retry_idx_temp_vec_0 = _ldq_enq_retry_idx_T_2 & _ldq_enq_retry_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_1 = _ldq_enq_retry_idx_T_5 & _ldq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_2 = _ldq_enq_retry_idx_T_8 & _ldq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_3 = _ldq_enq_retry_idx_T_11 & _ldq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_4 = _ldq_enq_retry_idx_T_14 & _ldq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_5 = _ldq_enq_retry_idx_T_17 & _ldq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_6 = _ldq_enq_retry_idx_T_20 & _ldq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _ldq_enq_retry_idx_temp_vec_T_7 = ~(ldq_head[3]); // @[util.scala:352:72] wire ldq_enq_retry_idx_temp_vec_7 = _ldq_enq_retry_idx_T_23 & _ldq_enq_retry_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_8 = _ldq_enq_retry_idx_T_26 & _ldq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_9 = _ldq_enq_retry_idx_T_29 & _ldq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_10 = _ldq_enq_retry_idx_T_32 & _ldq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_11 = _ldq_enq_retry_idx_T_35 & _ldq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_12 = _ldq_enq_retry_idx_T_38 & _ldq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_13 = _ldq_enq_retry_idx_T_41 & _ldq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_14 = _ldq_enq_retry_idx_T_44 & _ldq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire [4:0] _ldq_enq_retry_idx_idx_T = {4'hF, ~_ldq_enq_retry_idx_T_44}; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_1 = _ldq_enq_retry_idx_T_41 ? 5'h1D : _ldq_enq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_2 = _ldq_enq_retry_idx_T_38 ? 5'h1C : _ldq_enq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_3 = _ldq_enq_retry_idx_T_35 ? 5'h1B : _ldq_enq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_4 = _ldq_enq_retry_idx_T_32 ? 5'h1A : _ldq_enq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_5 = _ldq_enq_retry_idx_T_29 ? 5'h19 : _ldq_enq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_6 = _ldq_enq_retry_idx_T_26 ? 5'h18 : _ldq_enq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_7 = _ldq_enq_retry_idx_T_23 ? 5'h17 : _ldq_enq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_8 = _ldq_enq_retry_idx_T_20 ? 5'h16 : _ldq_enq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_9 = _ldq_enq_retry_idx_T_17 ? 5'h15 : _ldq_enq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_10 = _ldq_enq_retry_idx_T_14 ? 5'h14 : _ldq_enq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_11 = _ldq_enq_retry_idx_T_11 ? 5'h13 : _ldq_enq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_12 = _ldq_enq_retry_idx_T_8 ? 5'h12 : _ldq_enq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_13 = _ldq_enq_retry_idx_T_5 ? 5'h11 : _ldq_enq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_14 = _ldq_enq_retry_idx_T_2 ? 5'h10 : _ldq_enq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_15 = ldq_enq_retry_idx_temp_vec_15 ? 5'hF : _ldq_enq_retry_idx_idx_T_14; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_16 = ldq_enq_retry_idx_temp_vec_14 ? 5'hE : _ldq_enq_retry_idx_idx_T_15; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_17 = ldq_enq_retry_idx_temp_vec_13 ? 5'hD : _ldq_enq_retry_idx_idx_T_16; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_18 = ldq_enq_retry_idx_temp_vec_12 ? 5'hC : _ldq_enq_retry_idx_idx_T_17; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_19 = ldq_enq_retry_idx_temp_vec_11 ? 5'hB : _ldq_enq_retry_idx_idx_T_18; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_20 = ldq_enq_retry_idx_temp_vec_10 ? 5'hA : _ldq_enq_retry_idx_idx_T_19; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_21 = ldq_enq_retry_idx_temp_vec_9 ? 5'h9 : _ldq_enq_retry_idx_idx_T_20; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_22 = ldq_enq_retry_idx_temp_vec_8 ? 5'h8 : _ldq_enq_retry_idx_idx_T_21; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_23 = ldq_enq_retry_idx_temp_vec_7 ? 5'h7 : _ldq_enq_retry_idx_idx_T_22; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_24 = ldq_enq_retry_idx_temp_vec_6 ? 5'h6 : _ldq_enq_retry_idx_idx_T_23; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_25 = ldq_enq_retry_idx_temp_vec_5 ? 5'h5 : _ldq_enq_retry_idx_idx_T_24; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_26 = ldq_enq_retry_idx_temp_vec_4 ? 5'h4 : _ldq_enq_retry_idx_idx_T_25; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_27 = ldq_enq_retry_idx_temp_vec_3 ? 5'h3 : _ldq_enq_retry_idx_idx_T_26; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_28 = ldq_enq_retry_idx_temp_vec_2 ? 5'h2 : _ldq_enq_retry_idx_idx_T_27; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_29 = ldq_enq_retry_idx_temp_vec_1 ? 5'h1 : _ldq_enq_retry_idx_idx_T_28; // @[Mux.scala:50:70] wire [4:0] ldq_enq_retry_idx_idx = ldq_enq_retry_idx_temp_vec_0 ? 5'h0 : _ldq_enq_retry_idx_idx_T_29; // @[Mux.scala:50:70] wire [3:0] _ldq_enq_retry_idx_T_48 = ldq_enq_retry_idx_idx[3:0]; // @[Mux.scala:50:70] wire ldq_enq_retry_e_valid = ldq_enq_retry_e_e_valid; // @[lsu.scala:233:17, :518:33] wire [31:0] ldq_enq_retry_e_bits_uop_inst = ldq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:233:17, :518:33] wire [31:0] ldq_enq_retry_e_bits_uop_debug_inst = ldq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_rvc = ldq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17, :518:33] wire [39:0] ldq_enq_retry_e_bits_uop_debug_pc = ldq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_0 = ldq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_1 = ldq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_2 = ldq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_3 = ldq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_0 = ldq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_1 = ldq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_2 = ldq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_3 = ldq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_4 = ldq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_5 = ldq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_6 = ldq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_7 = ldq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_8 = ldq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_9 = ldq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_issued = ldq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_issued_partial_agen = ldq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_issued_partial_dgen = ldq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_iw_p1_speculative_child = ldq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_iw_p2_speculative_child = ldq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_p1_bypass_hint = ldq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_p2_bypass_hint = ldq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_p3_bypass_hint = ldq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_dis_col_sel = ldq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17, :518:33] wire [11:0] ldq_enq_retry_e_bits_uop_br_mask = ldq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_uop_br_tag = ldq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_uop_br_type = ldq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_sfb = ldq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_fence = ldq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_fencei = ldq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_sfence = ldq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_amo = ldq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_eret = ldq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_sys_pc2epc = ldq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_rocc = ldq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_mov = ldq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_ftq_idx = ldq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_edge_inst = ldq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_pc_lob = ldq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_taken = ldq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_imm_rename = ldq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_imm_sel = ldq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_pimm = ldq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:233:17, :518:33] wire [19:0] ldq_enq_retry_e_bits_uop_imm_packed = ldq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_op1_sel = ldq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_op2_sel = ldq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ldst = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_wen = ldq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ren1 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ren2 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ren3 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_swap12 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_swap23 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn = ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut = ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_fromint = ldq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_toint = ldq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_fastpipe = ldq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_fma = ldq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_div = ldq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_sqrt = ldq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_wflags = ldq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_vec = ldq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_rob_idx = ldq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_uop_ldq_idx = ldq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_uop_stq_idx = ldq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_rxq_idx = ldq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_pdst = ldq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_prs1 = ldq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_prs2 = ldq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_prs3 = ldq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_ppred = ldq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_prs1_busy = ldq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_prs2_busy = ldq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_prs3_busy = ldq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_ppred_busy = ldq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_stale_pdst = ldq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_exception = ldq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:233:17, :518:33] wire [63:0] ldq_enq_retry_e_bits_uop_exc_cause = ldq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_mem_cmd = ldq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_mem_size = ldq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_mem_signed = ldq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_uses_ldq = ldq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_uses_stq = ldq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_unique = ldq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_flush_on_commit = ldq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_csr_cmd = ldq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_ldst_is_rs1 = ldq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_ldst = ldq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_lrs1 = ldq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_lrs2 = ldq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_lrs3 = ldq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_dst_rtype = ldq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_lrs1_rtype = ldq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_lrs2_rtype = ldq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_frs3_en = ldq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fcn_dw = ldq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_fcn_op = ldq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_val = ldq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_fp_rm = ldq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_fp_typ = ldq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_xcpt_pf_if = ldq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_xcpt_ae_if = ldq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_xcpt_ma_if = ldq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_bp_debug_if = ldq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_bp_xcpt_if = ldq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_debug_fsrc = ldq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_debug_tsrc = ldq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_addr_valid = ldq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:233:17, :518:33] wire [39:0] ldq_enq_retry_e_bits_addr_bits = ldq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_addr_is_virtual = ldq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_addr_is_uncacheable = ldq_enq_retry_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_executed = ldq_enq_retry_e_e_bits_executed; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_succeeded = ldq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_order_fail = ldq_enq_retry_e_e_bits_order_fail; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_observed = ldq_enq_retry_e_e_bits_observed; // @[lsu.scala:233:17, :518:33] wire [15:0] ldq_enq_retry_e_bits_st_dep_mask = ldq_enq_retry_e_e_bits_st_dep_mask; // @[lsu.scala:233:17, :518:33] wire [7:0] ldq_enq_retry_e_bits_ld_byte_mask = ldq_enq_retry_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_forward_std_val = ldq_enq_retry_e_e_bits_forward_std_val; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_forward_stq_idx = ldq_enq_retry_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17, :518:33] wire [63:0] ldq_enq_retry_e_bits_debug_wb_data = ldq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:233:17, :518:33] assign ldq_enq_retry_e_e_valid = _GEN_25[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :234:32, :387:15, :514:30] assign ldq_enq_retry_e_e_bits_uop_inst = _GEN_76[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_inst = _GEN_77[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_rvc = _GEN_78[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_pc = _GEN_79[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_0 = _GEN_80[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_1 = _GEN_81[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_2 = _GEN_82[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_3 = _GEN_83[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_0 = _GEN_84[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_1 = _GEN_85[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_2 = _GEN_86[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_3 = _GEN_87[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_4 = _GEN_88[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_5 = _GEN_89[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_6 = _GEN_90[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_7 = _GEN_91[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_8 = _GEN_92[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_9 = _GEN_93[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_issued = _GEN_94[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_95[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_96[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_97[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_98[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_99[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_100[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_101[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_dis_col_sel = _GEN_102[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_br_mask = _GEN_103[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_br_tag = _GEN_104[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_br_type = _GEN_105[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_sfb = _GEN_106[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_fence = _GEN_107[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_fencei = _GEN_108[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_sfence = _GEN_109[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_amo = _GEN_110[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_eret = _GEN_111[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_112[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_rocc = _GEN_113[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_mov = _GEN_114[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ftq_idx = _GEN_115[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_edge_inst = _GEN_116[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_pc_lob = _GEN_117[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_taken = _GEN_118[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_imm_rename = _GEN_119[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_imm_sel = _GEN_120[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_pimm = _GEN_121[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_imm_packed = _GEN_122[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_op1_sel = _GEN_123[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_op2_sel = _GEN_124[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_125[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_126[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_127[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_128[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_129[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_130[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_131[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_132[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_133[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_134[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_135[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_136[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_137[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_138[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_139[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_140[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_141[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_rob_idx = _GEN_142[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ldq_idx = _GEN_143[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_stq_idx = _GEN_144[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_rxq_idx = _GEN_145[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_pdst = _GEN_146[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs1 = _GEN_147[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs2 = _GEN_148[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs3 = _GEN_149[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ppred = _GEN_150[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs1_busy = _GEN_151[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs2_busy = _GEN_152[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs3_busy = _GEN_153[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ppred_busy = _GEN_154[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_stale_pdst = _GEN_155[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_exception = _GEN_156[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_exc_cause = _GEN_157[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_mem_cmd = _GEN_158[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_mem_size = _GEN_159[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_mem_signed = _GEN_160[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_uses_ldq = _GEN_161[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_uses_stq = _GEN_162[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_unique = _GEN_163[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_flush_on_commit = _GEN_164[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_csr_cmd = _GEN_165[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_166[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ldst = _GEN_167[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs1 = _GEN_168[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs2 = _GEN_169[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs3 = _GEN_170[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_dst_rtype = _GEN_171[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs1_rtype = _GEN_172[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs2_rtype = _GEN_173[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_frs3_en = _GEN_174[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fcn_dw = _GEN_175[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fcn_op = _GEN_176[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_val = _GEN_177[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_rm = _GEN_178[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_typ = _GEN_179[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_180[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_181[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_182[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_bp_debug_if = _GEN_183[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_184[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_fsrc = _GEN_185[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_tsrc = _GEN_186[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_valid = _GEN_187[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :236:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_bits = _GEN_188[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :236:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_is_virtual = _GEN_189[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :237:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_is_uncacheable = _GEN_190[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :238:32, :514:30] assign ldq_enq_retry_e_e_bits_executed = _GEN_191[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :239:32, :514:30] assign ldq_enq_retry_e_e_bits_succeeded = _GEN_192[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :240:32, :514:30] assign ldq_enq_retry_e_e_bits_order_fail = _GEN_193[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :241:32, :514:30] assign ldq_enq_retry_e_e_bits_observed = _GEN_194[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :242:32, :514:30] assign ldq_enq_retry_e_e_bits_st_dep_mask = _GEN_195[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :243:32, :514:30] assign ldq_enq_retry_e_e_bits_ld_byte_mask = _GEN_196[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :244:32, :514:30] assign ldq_enq_retry_e_e_bits_forward_std_val = _GEN_197[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :245:32, :514:30] assign ldq_enq_retry_e_e_bits_forward_stq_idx = _GEN_198[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :246:32, :514:30] assign ldq_enq_retry_e_e_bits_debug_wb_data = _GEN_199[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :247:32, :514:30] reg [3:0] stq_enq_retry_idx; // @[lsu.scala:520:30] wire _stq_enq_retry_idx_T = stq_addr_0_valid & stq_addr_is_virtual_0; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_1 = \|stq_enq_retry_idx; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_2 = _stq_enq_retry_idx_T & _stq_enq_retry_idx_T_1; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_3 = stq_addr_1_valid & stq_addr_is_virtual_1; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_4 = stq_enq_retry_idx != 4'h1; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_5 = _stq_enq_retry_idx_T_3 & _stq_enq_retry_idx_T_4; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_6 = stq_addr_2_valid & stq_addr_is_virtual_2; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_7 = stq_enq_retry_idx != 4'h2; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_8 = _stq_enq_retry_idx_T_6 & _stq_enq_retry_idx_T_7; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_9 = stq_addr_3_valid & stq_addr_is_virtual_3; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_10 = stq_enq_retry_idx != 4'h3; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_11 = _stq_enq_retry_idx_T_9 & _stq_enq_retry_idx_T_10; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_12 = stq_addr_4_valid & stq_addr_is_virtual_4; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_13 = stq_enq_retry_idx != 4'h4; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_14 = _stq_enq_retry_idx_T_12 & _stq_enq_retry_idx_T_13; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_15 = stq_addr_5_valid & stq_addr_is_virtual_5; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_16 = stq_enq_retry_idx != 4'h5; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_17 = _stq_enq_retry_idx_T_15 & _stq_enq_retry_idx_T_16; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_18 = stq_addr_6_valid & stq_addr_is_virtual_6; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_19 = stq_enq_retry_idx != 4'h6; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_20 = _stq_enq_retry_idx_T_18 & _stq_enq_retry_idx_T_19; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_21 = stq_addr_7_valid & stq_addr_is_virtual_7; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_22 = stq_enq_retry_idx != 4'h7; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_23 = _stq_enq_retry_idx_T_21 & _stq_enq_retry_idx_T_22; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_24 = stq_addr_8_valid & stq_addr_is_virtual_8; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_25 = stq_enq_retry_idx != 4'h8; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_26 = _stq_enq_retry_idx_T_24 & _stq_enq_retry_idx_T_25; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_27 = stq_addr_9_valid & stq_addr_is_virtual_9; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_28 = stq_enq_retry_idx != 4'h9; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_29 = _stq_enq_retry_idx_T_27 & _stq_enq_retry_idx_T_28; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_30 = stq_addr_10_valid & stq_addr_is_virtual_10; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_31 = stq_enq_retry_idx != 4'hA; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_32 = _stq_enq_retry_idx_T_30 & _stq_enq_retry_idx_T_31; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_33 = stq_addr_11_valid & stq_addr_is_virtual_11; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_34 = stq_enq_retry_idx != 4'hB; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_35 = _stq_enq_retry_idx_T_33 & _stq_enq_retry_idx_T_34; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_36 = stq_addr_12_valid & stq_addr_is_virtual_12; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_37 = stq_enq_retry_idx != 4'hC; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_38 = _stq_enq_retry_idx_T_36 & _stq_enq_retry_idx_T_37; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_39 = stq_addr_13_valid & stq_addr_is_virtual_13; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_40 = stq_enq_retry_idx != 4'hD; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_41 = _stq_enq_retry_idx_T_39 & _stq_enq_retry_idx_T_40; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_42 = stq_addr_14_valid & stq_addr_is_virtual_14; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_43 = stq_enq_retry_idx != 4'hE; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_44 = _stq_enq_retry_idx_T_42 & _stq_enq_retry_idx_T_43; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_45 = stq_addr_15_valid & stq_addr_is_virtual_15; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_46 = ~(&stq_enq_retry_idx); // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_47 = _stq_enq_retry_idx_T_45 & _stq_enq_retry_idx_T_46; // @[lsu.scala:522:{23,49,57}] wire stq_enq_retry_idx_temp_vec_15 = _stq_enq_retry_idx_T_47; // @[util.scala:352:65] wire _GEN_335 = stq_commit_head == 4'h0; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T = _GEN_335; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T = _GEN_335; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_0 = _stq_enq_retry_idx_T_2 & _stq_enq_retry_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire _GEN_336 = stq_commit_head < 4'h2; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_1 = _GEN_336; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_1; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_1 = _GEN_336; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_1 = _stq_enq_retry_idx_T_5 & _stq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire _GEN_337 = stq_commit_head < 4'h3; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_2 = _GEN_337; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_2; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_2 = _GEN_337; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_2 = _stq_enq_retry_idx_T_8 & _stq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire _GEN_338 = stq_commit_head < 4'h4; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_3 = _GEN_338; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_3; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_3 = _GEN_338; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_3 = _stq_enq_retry_idx_T_11 & _stq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire _GEN_339 = stq_commit_head < 4'h5; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_4 = _GEN_339; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_4; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_4 = _GEN_339; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_4 = _stq_enq_retry_idx_T_14 & _stq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire _GEN_340 = stq_commit_head < 4'h6; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_5 = _GEN_340; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_5; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_5 = _GEN_340; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_5 = _stq_enq_retry_idx_T_17 & _stq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire _GEN_341 = stq_commit_head < 4'h7; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_6 = _GEN_341; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_6; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_6 = _GEN_341; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_6 = _stq_enq_retry_idx_T_20 & _stq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _stq_enq_retry_idx_temp_vec_T_7 = ~(stq_commit_head[3]); // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_7 = _stq_enq_retry_idx_T_23 & _stq_enq_retry_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire _GEN_342 = stq_commit_head < 4'h9; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_8 = _GEN_342; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_8; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_8 = _GEN_342; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_8 = _stq_enq_retry_idx_T_26 & _stq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire _GEN_343 = stq_commit_head < 4'hA; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_9 = _GEN_343; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_9; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_9 = _GEN_343; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_9 = _stq_enq_retry_idx_T_29 & _stq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire _GEN_344 = stq_commit_head < 4'hB; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_10 = _GEN_344; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_10; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_10 = _GEN_344; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_10 = _stq_enq_retry_idx_T_32 & _stq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire _GEN_345 = stq_commit_head[3:2] != 2'h3; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_11 = _GEN_345; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_11; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_11 = _GEN_345; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_11 = _stq_enq_retry_idx_T_35 & _stq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire _GEN_346 = stq_commit_head < 4'hD; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_12 = _GEN_346; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_12; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_12 = _GEN_346; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_12 = _stq_enq_retry_idx_T_38 & _stq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire _GEN_347 = stq_commit_head[3:1] != 3'h7; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_13 = _GEN_347; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_13; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_13 = _GEN_347; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_13 = _stq_enq_retry_idx_T_41 & _stq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire _GEN_348 = stq_commit_head != 4'hF; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_14 = _GEN_348; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_14; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_14 = _GEN_348; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_14 = _stq_enq_retry_idx_T_44 & _stq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire [4:0] _stq_enq_retry_idx_idx_T = {4'hF, ~_stq_enq_retry_idx_T_44}; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_1 = _stq_enq_retry_idx_T_41 ? 5'h1D : _stq_enq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_2 = _stq_enq_retry_idx_T_38 ? 5'h1C : _stq_enq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_3 = _stq_enq_retry_idx_T_35 ? 5'h1B : _stq_enq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_4 = _stq_enq_retry_idx_T_32 ? 5'h1A : _stq_enq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_5 = _stq_enq_retry_idx_T_29 ? 5'h19 : _stq_enq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_6 = _stq_enq_retry_idx_T_26 ? 5'h18 : _stq_enq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_7 = _stq_enq_retry_idx_T_23 ? 5'h17 : _stq_enq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_8 = _stq_enq_retry_idx_T_20 ? 5'h16 : _stq_enq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_9 = _stq_enq_retry_idx_T_17 ? 5'h15 : _stq_enq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_10 = _stq_enq_retry_idx_T_14 ? 5'h14 : _stq_enq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_11 = _stq_enq_retry_idx_T_11 ? 5'h13 : _stq_enq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_12 = _stq_enq_retry_idx_T_8 ? 5'h12 : _stq_enq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_13 = _stq_enq_retry_idx_T_5 ? 5'h11 : _stq_enq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_14 = _stq_enq_retry_idx_T_2 ? 5'h10 : _stq_enq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_15 = stq_enq_retry_idx_temp_vec_15 ? 5'hF : _stq_enq_retry_idx_idx_T_14; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_16 = stq_enq_retry_idx_temp_vec_14 ? 5'hE : _stq_enq_retry_idx_idx_T_15; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_17 = stq_enq_retry_idx_temp_vec_13 ? 5'hD : _stq_enq_retry_idx_idx_T_16; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_18 = stq_enq_retry_idx_temp_vec_12 ? 5'hC : _stq_enq_retry_idx_idx_T_17; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_19 = stq_enq_retry_idx_temp_vec_11 ? 5'hB : _stq_enq_retry_idx_idx_T_18; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_20 = stq_enq_retry_idx_temp_vec_10 ? 5'hA : _stq_enq_retry_idx_idx_T_19; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_21 = stq_enq_retry_idx_temp_vec_9 ? 5'h9 : _stq_enq_retry_idx_idx_T_20; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_22 = stq_enq_retry_idx_temp_vec_8 ? 5'h8 : _stq_enq_retry_idx_idx_T_21; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_23 = stq_enq_retry_idx_temp_vec_7 ? 5'h7 : _stq_enq_retry_idx_idx_T_22; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_24 = stq_enq_retry_idx_temp_vec_6 ? 5'h6 : _stq_enq_retry_idx_idx_T_23; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_25 = stq_enq_retry_idx_temp_vec_5 ? 5'h5 : _stq_enq_retry_idx_idx_T_24; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_26 = stq_enq_retry_idx_temp_vec_4 ? 5'h4 : _stq_enq_retry_idx_idx_T_25; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_27 = stq_enq_retry_idx_temp_vec_3 ? 5'h3 : _stq_enq_retry_idx_idx_T_26; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_28 = stq_enq_retry_idx_temp_vec_2 ? 5'h2 : _stq_enq_retry_idx_idx_T_27; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_29 = stq_enq_retry_idx_temp_vec_1 ? 5'h1 : _stq_enq_retry_idx_idx_T_28; // @[Mux.scala:50:70] wire [4:0] stq_enq_retry_idx_idx = stq_enq_retry_idx_temp_vec_0 ? 5'h0 : _stq_enq_retry_idx_idx_T_29; // @[Mux.scala:50:70] wire [3:0] _stq_enq_retry_idx_T_48 = stq_enq_retry_idx_idx[3:0]; // @[Mux.scala:50:70] wire stq_enq_retry_e_valid = stq_enq_retry_e_e_valid; // @[lsu.scala:262:17, :524:35] wire [31:0] stq_enq_retry_e_bits_uop_inst = stq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:262:17, :524:35] wire [31:0] stq_enq_retry_e_bits_uop_debug_inst = stq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_rvc = stq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17, :524:35] wire [39:0] stq_enq_retry_e_bits_uop_debug_pc = stq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_0 = stq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_1 = stq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_2 = stq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_3 = stq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_0 = stq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_1 = stq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_2 = stq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_3 = stq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_4 = stq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_5 = stq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_6 = stq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_7 = stq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_8 = stq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_9 = stq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_issued = stq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_issued_partial_agen = stq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_issued_partial_dgen = stq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_iw_p1_speculative_child = stq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_iw_p2_speculative_child = stq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_p1_bypass_hint = stq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_p2_bypass_hint = stq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_p3_bypass_hint = stq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_dis_col_sel = stq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17, :524:35] wire [11:0] stq_enq_retry_e_bits_uop_br_mask = stq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:262:17, :524:35] wire [3:0] stq_enq_retry_e_bits_uop_br_tag = stq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:262:17, :524:35] wire [3:0] stq_enq_retry_e_bits_uop_br_type = stq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_sfb = stq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_fence = stq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_fencei = stq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_sfence = stq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_amo = stq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_eret = stq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_sys_pc2epc = stq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_rocc = stq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_mov = stq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_ftq_idx = stq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_edge_inst = stq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_pc_lob = stq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_taken = stq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_imm_rename = stq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_imm_sel = stq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_pimm = stq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:262:17, :524:35] wire [19:0] stq_enq_retry_e_bits_uop_imm_packed = stq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_op1_sel = stq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_op2_sel = stq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ldst = stq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_wen = stq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ren1 = stq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ren2 = stq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ren3 = stq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_swap12 = stq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_swap23 = stq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn = stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut = stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_fromint = stq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_toint = stq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_fastpipe = stq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_fma = stq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_div = stq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_sqrt = stq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_wflags = stq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_vec = stq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_rob_idx = stq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17, :524:35] wire [3:0] stq_enq_retry_e_bits_uop_ldq_idx = stq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17, :524:35] wire [3:0] stq_enq_retry_e_bits_uop_stq_idx = stq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_rxq_idx = stq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_pdst = stq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_prs1 = stq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_prs2 = stq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_prs3 = stq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_ppred = stq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_prs1_busy = stq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_prs2_busy = stq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_prs3_busy = stq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_ppred_busy = stq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_stale_pdst = stq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_exception = stq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:262:17, :524:35] wire [63:0] stq_enq_retry_e_bits_uop_exc_cause = stq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_mem_cmd = stq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_mem_size = stq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_mem_signed = stq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_uses_ldq = stq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_uses_stq = stq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_unique = stq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_flush_on_commit = stq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_csr_cmd = stq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_ldst_is_rs1 = stq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_ldst = stq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_lrs1 = stq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_lrs2 = stq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_lrs3 = stq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_dst_rtype = stq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_lrs1_rtype = stq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_lrs2_rtype = stq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_frs3_en = stq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fcn_dw = stq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_fcn_op = stq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_val = stq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_fp_rm = stq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_fp_typ = stq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_xcpt_pf_if = stq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_xcpt_ae_if = stq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_xcpt_ma_if = stq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_bp_debug_if = stq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_bp_xcpt_if = stq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_debug_fsrc = stq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_debug_tsrc = stq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_addr_valid = stq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:262:17, :524:35] wire [39:0] stq_enq_retry_e_bits_addr_bits = stq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_addr_is_virtual = stq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_data_valid = stq_enq_retry_e_e_bits_data_valid; // @[lsu.scala:262:17, :524:35] wire [63:0] stq_enq_retry_e_bits_data_bits = stq_enq_retry_e_e_bits_data_bits; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_committed = stq_enq_retry_e_e_bits_committed; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_succeeded = stq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_can_execute = stq_enq_retry_e_e_bits_can_execute; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_cleared = stq_enq_retry_e_e_bits_cleared; // @[lsu.scala:262:17, :524:35] wire [63:0] stq_enq_retry_e_bits_debug_wb_data = stq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:262:17, :524:35] assign stq_enq_retry_e_e_valid = _GEN_26[stq_enq_retry_idx]; // @[lsu.scala:262:17, :263:32, :392:15, :520:30] assign stq_enq_retry_e_e_bits_uop_inst = _GEN_200[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_inst = _GEN_201[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_rvc = _GEN_202[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_pc = _GEN_203[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_0 = _GEN_204[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_1 = _GEN_205[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_2 = _GEN_206[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_3 = _GEN_207[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_0 = _GEN_208[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_1 = _GEN_209[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_2 = _GEN_210[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_3 = _GEN_211[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_4 = _GEN_212[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_5 = _GEN_213[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_6 = _GEN_214[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_7 = _GEN_215[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_8 = _GEN_216[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_9 = _GEN_217[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_issued = _GEN_218[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_219[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_220[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_221[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_222[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_223[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_224[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_225[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_dis_col_sel = _GEN_226[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_br_mask = _GEN_227[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_br_tag = _GEN_228[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_br_type = _GEN_229[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_sfb = _GEN_230[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_fence = _GEN_231[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_fencei = _GEN_232[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_sfence = _GEN_233[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_amo = _GEN_234[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_eret = _GEN_235[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_236[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_rocc = _GEN_237[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_mov = _GEN_238[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ftq_idx = _GEN_239[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_edge_inst = _GEN_240[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_pc_lob = _GEN_241[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_taken = _GEN_242[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_imm_rename = _GEN_243[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_imm_sel = _GEN_244[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_pimm = _GEN_245[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_imm_packed = _GEN_246[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_op1_sel = _GEN_247[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_op2_sel = _GEN_248[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_249[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_250[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_251[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_252[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_253[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_254[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_255[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_256[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_257[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_258[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_259[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_260[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_261[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_262[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_263[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_264[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_265[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_rob_idx = _GEN_266[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ldq_idx = _GEN_267[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_stq_idx = _GEN_268[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_rxq_idx = _GEN_269[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_pdst = _GEN_270[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs1 = _GEN_271[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs2 = _GEN_272[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs3 = _GEN_273[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ppred = _GEN_274[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs1_busy = _GEN_275[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs2_busy = _GEN_276[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs3_busy = _GEN_277[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ppred_busy = _GEN_278[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_stale_pdst = _GEN_279[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_exception = _GEN_280[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_exc_cause = _GEN_281[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_mem_cmd = _GEN_282[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_mem_size = _GEN_283[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_mem_signed = _GEN_284[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_uses_ldq = _GEN_285[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_uses_stq = _GEN_286[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_unique = _GEN_287[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_flush_on_commit = _GEN_288[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_csr_cmd = _GEN_289[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_290[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ldst = _GEN_291[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs1 = _GEN_292[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs2 = _GEN_293[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs3 = _GEN_294[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_dst_rtype = _GEN_295[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs1_rtype = _GEN_296[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs2_rtype = _GEN_297[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_frs3_en = _GEN_298[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fcn_dw = _GEN_299[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fcn_op = _GEN_300[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_val = _GEN_301[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_rm = _GEN_302[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_typ = _GEN_303[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_304[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_305[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_306[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_bp_debug_if = _GEN_307[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_308[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_fsrc = _GEN_309[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_tsrc = _GEN_310[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_addr_valid = _GEN_311[stq_enq_retry_idx]; // @[lsu.scala:262:17, :265:32, :520:30] assign stq_enq_retry_e_e_bits_addr_bits = _GEN_312[stq_enq_retry_idx]; // @[lsu.scala:262:17, :265:32, :520:30] assign stq_enq_retry_e_e_bits_addr_is_virtual = _GEN_313[stq_enq_retry_idx]; // @[lsu.scala:262:17, :266:32, :520:30] assign stq_enq_retry_e_e_bits_data_valid = _GEN_314[stq_enq_retry_idx]; // @[lsu.scala:262:17, :267:32, :520:30] assign stq_enq_retry_e_e_bits_data_bits = _GEN_315[stq_enq_retry_idx]; // @[lsu.scala:262:17, :267:32, :520:30] assign stq_enq_retry_e_e_bits_committed = _GEN_316[stq_enq_retry_idx]; // @[lsu.scala:262:17, :268:32, :520:30] assign stq_enq_retry_e_e_bits_succeeded = _GEN_317[stq_enq_retry_idx]; // @[lsu.scala:262:17, :269:32, :520:30] assign stq_enq_retry_e_e_bits_can_execute = _GEN_318[stq_enq_retry_idx]; // @[lsu.scala:262:17, :270:32, :520:30] assign stq_enq_retry_e_e_bits_cleared = _GEN_319[stq_enq_retry_idx]; // @[lsu.scala:262:17, :271:32, :520:30] assign stq_enq_retry_e_e_bits_debug_wb_data = _GEN_320[stq_enq_retry_idx]; // @[lsu.scala:262:17, :272:32, :520:30] wire _can_enq_load_retry_T = ldq_enq_retry_e_valid & ldq_enq_retry_e_bits_addr_valid; // @[lsu.scala:518:33, :526:81] wire can_enq_load_retry = _can_enq_load_retry_T & ldq_enq_retry_e_bits_addr_is_virtual; // @[lsu.scala:518:33, :526:81, :527:81] wire _can_enq_store_retry_T = stq_enq_retry_e_valid & stq_enq_retry_e_bits_addr_valid; // @[lsu.scala:524:35, :529:81] wire can_enq_store_retry = _can_enq_store_retry_T & stq_enq_retry_e_bits_addr_is_virtual; // @[lsu.scala:524:35, :529:81, :530:81] wire _retry_queue_io_enq_valid_T = can_enq_store_retry \| can_enq_load_retry; // @[lsu.scala:527:81, :530:81, :537:55] wire [39:0] _retry_queue_io_enq_bits_data_T = can_enq_store_retry ? stq_enq_retry_e_bits_addr_bits : ldq_enq_retry_e_bits_addr_bits; // @[lsu.scala:518:33, :524:35, :530:81, :539:38] wire [31:0] _retry_queue_io_enq_bits_uop_T_inst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_inst : ldq_enq_retry_e_bits_uop_inst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [31:0] _retry_queue_io_enq_bits_uop_T_debug_inst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_inst : ldq_enq_retry_e_bits_uop_debug_inst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_rvc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_rvc : ldq_enq_retry_e_bits_uop_is_rvc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [39:0] _retry_queue_io_enq_bits_uop_T_debug_pc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_pc : ldq_enq_retry_e_bits_uop_debug_pc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_0 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_0 : ldq_enq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_1 : ldq_enq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_2 : ldq_enq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_3 : ldq_enq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_0 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_0 : ldq_enq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_1 : ldq_enq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_2 : ldq_enq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_3 : ldq_enq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_4 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_4 : ldq_enq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_5 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_5 : ldq_enq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_6 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_6 : ldq_enq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_7 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_7 : ldq_enq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_8 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_8 : ldq_enq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_9 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_9 : ldq_enq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_issued = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_issued : ldq_enq_retry_e_bits_uop_iw_issued; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_issued_partial_agen = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_issued_partial_agen : ldq_enq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_issued_partial_dgen = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_issued_partial_dgen : ldq_enq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_iw_p1_speculative_child = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p1_speculative_child : ldq_enq_retry_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_iw_p2_speculative_child = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p2_speculative_child : ldq_enq_retry_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_p1_bypass_hint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p1_bypass_hint : ldq_enq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_p2_bypass_hint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p2_bypass_hint : ldq_enq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_p3_bypass_hint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p3_bypass_hint : ldq_enq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_dis_col_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_dis_col_sel : ldq_enq_retry_e_bits_uop_dis_col_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [11:0] _retry_queue_io_enq_bits_uop_T_br_mask = can_enq_store_retry ? stq_enq_retry_e_bits_uop_br_mask : ldq_enq_retry_e_bits_uop_br_mask; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [3:0] _retry_queue_io_enq_bits_uop_T_br_tag = can_enq_store_retry ? stq_enq_retry_e_bits_uop_br_tag : ldq_enq_retry_e_bits_uop_br_tag; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [3:0] _retry_queue_io_enq_bits_uop_T_br_type = can_enq_store_retry ? stq_enq_retry_e_bits_uop_br_type : ldq_enq_retry_e_bits_uop_br_type; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_sfb = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_sfb : ldq_enq_retry_e_bits_uop_is_sfb; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_fence = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_fence : ldq_enq_retry_e_bits_uop_is_fence; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_fencei = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_fencei : ldq_enq_retry_e_bits_uop_is_fencei; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_sfence = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_sfence : ldq_enq_retry_e_bits_uop_is_sfence; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_amo = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_amo : ldq_enq_retry_e_bits_uop_is_amo; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_eret = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_eret : ldq_enq_retry_e_bits_uop_is_eret; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_sys_pc2epc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_sys_pc2epc : ldq_enq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_rocc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_rocc : ldq_enq_retry_e_bits_uop_is_rocc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_mov = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_mov : ldq_enq_retry_e_bits_uop_is_mov; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_ftq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ftq_idx : ldq_enq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_edge_inst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_edge_inst : ldq_enq_retry_e_bits_uop_edge_inst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_pc_lob = can_enq_store_retry ? stq_enq_retry_e_bits_uop_pc_lob : ldq_enq_retry_e_bits_uop_pc_lob; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_taken = can_enq_store_retry ? stq_enq_retry_e_bits_uop_taken : ldq_enq_retry_e_bits_uop_taken; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_imm_rename = can_enq_store_retry ? stq_enq_retry_e_bits_uop_imm_rename : ldq_enq_retry_e_bits_uop_imm_rename; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_imm_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_imm_sel : ldq_enq_retry_e_bits_uop_imm_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_pimm = can_enq_store_retry ? stq_enq_retry_e_bits_uop_pimm : ldq_enq_retry_e_bits_uop_pimm; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [19:0] _retry_queue_io_enq_bits_uop_T_imm_packed = can_enq_store_retry ? stq_enq_retry_e_bits_uop_imm_packed : ldq_enq_retry_e_bits_uop_imm_packed; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_op1_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_op1_sel : ldq_enq_retry_e_bits_uop_op1_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_op2_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_op2_sel : ldq_enq_retry_e_bits_uop_op2_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ldst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ldst : ldq_enq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_wen = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_wen : ldq_enq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ren1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ren1 : ldq_enq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ren2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ren2 : ldq_enq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ren3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ren3 : ldq_enq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_swap12 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_swap12 : ldq_enq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_swap23 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_swap23 : ldq_enq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_fp_ctrl_typeTagIn = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn : ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_fp_ctrl_typeTagOut = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut : ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_fromint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_fromint : ldq_enq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_toint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_toint : ldq_enq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_fastpipe = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_fastpipe : ldq_enq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_fma = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_fma : ldq_enq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_div = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_div : ldq_enq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_sqrt = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_sqrt : ldq_enq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_wflags = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_wflags : ldq_enq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_vec = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_vec : ldq_enq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_rob_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_rob_idx : ldq_enq_retry_e_bits_uop_rob_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [3:0] _retry_queue_io_enq_bits_uop_T_ldq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ldq_idx : ldq_enq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [3:0] _retry_queue_io_enq_bits_uop_T_stq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_stq_idx : ldq_enq_retry_e_bits_uop_stq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_rxq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_rxq_idx : ldq_enq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_pdst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_pdst : ldq_enq_retry_e_bits_uop_pdst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_prs1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs1 : ldq_enq_retry_e_bits_uop_prs1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_prs2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs2 : ldq_enq_retry_e_bits_uop_prs2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_prs3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs3 : ldq_enq_retry_e_bits_uop_prs3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_ppred = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ppred : ldq_enq_retry_e_bits_uop_ppred; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_prs1_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs1_busy : ldq_enq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_prs2_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs2_busy : ldq_enq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_prs3_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs3_busy : ldq_enq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_ppred_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ppred_busy : ldq_enq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_stale_pdst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_stale_pdst : ldq_enq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_exception = can_enq_store_retry ? stq_enq_retry_e_bits_uop_exception : ldq_enq_retry_e_bits_uop_exception; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [63:0] _retry_queue_io_enq_bits_uop_T_exc_cause = can_enq_store_retry ? stq_enq_retry_e_bits_uop_exc_cause : ldq_enq_retry_e_bits_uop_exc_cause; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_mem_cmd = can_enq_store_retry ? stq_enq_retry_e_bits_uop_mem_cmd : ldq_enq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_mem_size = can_enq_store_retry ? stq_enq_retry_e_bits_uop_mem_size : ldq_enq_retry_e_bits_uop_mem_size; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_mem_signed = can_enq_store_retry ? stq_enq_retry_e_bits_uop_mem_signed : ldq_enq_retry_e_bits_uop_mem_signed; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_uses_ldq = can_enq_store_retry ? stq_enq_retry_e_bits_uop_uses_ldq : ldq_enq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_uses_stq = can_enq_store_retry ? stq_enq_retry_e_bits_uop_uses_stq : ldq_enq_retry_e_bits_uop_uses_stq; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_unique = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_unique : ldq_enq_retry_e_bits_uop_is_unique; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_flush_on_commit = can_enq_store_retry ? stq_enq_retry_e_bits_uop_flush_on_commit : ldq_enq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_csr_cmd = can_enq_store_retry ? stq_enq_retry_e_bits_uop_csr_cmd : ldq_enq_retry_e_bits_uop_csr_cmd; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_ldst_is_rs1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ldst_is_rs1 : ldq_enq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_ldst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ldst : ldq_enq_retry_e_bits_uop_ldst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_lrs1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs1 : ldq_enq_retry_e_bits_uop_lrs1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_lrs2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs2 : ldq_enq_retry_e_bits_uop_lrs2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_lrs3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs3 : ldq_enq_retry_e_bits_uop_lrs3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_dst_rtype = can_enq_store_retry ? stq_enq_retry_e_bits_uop_dst_rtype : ldq_enq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_lrs1_rtype = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs1_rtype : ldq_enq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_lrs2_rtype = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs2_rtype : ldq_enq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_frs3_en = can_enq_store_retry ? stq_enq_retry_e_bits_uop_frs3_en : ldq_enq_retry_e_bits_uop_frs3_en; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fcn_dw = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fcn_dw : ldq_enq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_fcn_op = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fcn_op : ldq_enq_retry_e_bits_uop_fcn_op; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_val = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_val : ldq_enq_retry_e_bits_uop_fp_val; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_fp_rm = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_rm : ldq_enq_retry_e_bits_uop_fp_rm; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_fp_typ = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_typ : ldq_enq_retry_e_bits_uop_fp_typ; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_xcpt_pf_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_xcpt_pf_if : ldq_enq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_xcpt_ae_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_xcpt_ae_if : ldq_enq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_xcpt_ma_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_xcpt_ma_if : ldq_enq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_bp_debug_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_bp_debug_if : ldq_enq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_bp_xcpt_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_bp_xcpt_if : ldq_enq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_debug_fsrc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_fsrc : ldq_enq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_debug_tsrc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_tsrc : ldq_enq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_uses_ldq_T = ~can_enq_store_retry; // @[lsu.scala:530:81, :541:65] wire _retry_queue_io_enq_bits_uop_uses_ldq_T_1 = can_enq_load_retry & _retry_queue_io_enq_bits_uop_uses_ldq_T; // @[lsu.scala:527:81, :541:{62,65}] wire _GEN_349 = will_fire_load_retry_0 \| will_fire_store_retry_0; // @[lsu.scala:476:41, :477:41, :554:65] wire _retry_queue_io_deq_ready_T; // @[lsu.scala:554:65] assign _retry_queue_io_deq_ready_T = _GEN_349; // @[lsu.scala:554:65] wire _exe_tlb_uop_T_1; // @[lsu.scala:720:53] assign _exe_tlb_uop_T_1 = _GEN_349; // @[lsu.scala:554:65, :720:53] wire _exe_tlb_vaddr_T_2; // @[lsu.scala:730:53] assign _exe_tlb_vaddr_T_2 = _GEN_349; // @[lsu.scala:554:65, :730:53] wire stq_execute_queue_flush; // @[lsu.scala:556:41] wire stq_enq_e_valid = stq_enq_e_e_valid; // @[lsu.scala:262:17, :561:27] wire [31:0] stq_enq_e_bits_uop_inst = stq_enq_e_e_bits_uop_inst; // @[lsu.scala:262:17, :561:27] wire [31:0] stq_enq_e_bits_uop_debug_inst = stq_enq_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_rvc = stq_enq_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17, :561:27] wire [39:0] stq_enq_e_bits_uop_debug_pc = stq_enq_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_0 = stq_enq_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_1 = stq_enq_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_2 = stq_enq_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_3 = stq_enq_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_0 = stq_enq_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_1 = stq_enq_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_2 = stq_enq_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_3 = stq_enq_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_4 = stq_enq_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_5 = stq_enq_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_6 = stq_enq_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_7 = stq_enq_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_8 = stq_enq_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_9 = stq_enq_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_issued = stq_enq_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_issued_partial_agen = stq_enq_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_issued_partial_dgen = stq_enq_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_iw_p1_speculative_child = stq_enq_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_iw_p2_speculative_child = stq_enq_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_p1_bypass_hint = stq_enq_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_p2_bypass_hint = stq_enq_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_p3_bypass_hint = stq_enq_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_dis_col_sel = stq_enq_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17, :561:27] wire [11:0] stq_enq_e_bits_uop_br_mask = stq_enq_e_e_bits_uop_br_mask; // @[lsu.scala:262:17, :561:27] wire [3:0] stq_enq_e_bits_uop_br_tag = stq_enq_e_e_bits_uop_br_tag; // @[lsu.scala:262:17, :561:27] wire [3:0] stq_enq_e_bits_uop_br_type = stq_enq_e_e_bits_uop_br_type; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_sfb = stq_enq_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_fence = stq_enq_e_e_bits_uop_is_fence; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_fencei = stq_enq_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_sfence = stq_enq_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_amo = stq_enq_e_e_bits_uop_is_amo; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_eret = stq_enq_e_e_bits_uop_is_eret; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_sys_pc2epc = stq_enq_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_rocc = stq_enq_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_mov = stq_enq_e_e_bits_uop_is_mov; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_ftq_idx = stq_enq_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_edge_inst = stq_enq_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_pc_lob = stq_enq_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_taken = stq_enq_e_e_bits_uop_taken; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_imm_rename = stq_enq_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_imm_sel = stq_enq_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_pimm = stq_enq_e_e_bits_uop_pimm; // @[lsu.scala:262:17, :561:27] wire [19:0] stq_enq_e_bits_uop_imm_packed = stq_enq_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_op1_sel = stq_enq_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_op2_sel = stq_enq_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ldst = stq_enq_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_wen = stq_enq_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ren1 = stq_enq_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ren2 = stq_enq_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ren3 = stq_enq_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_swap12 = stq_enq_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_swap23 = stq_enq_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_fp_ctrl_typeTagIn = stq_enq_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_fp_ctrl_typeTagOut = stq_enq_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_fromint = stq_enq_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_toint = stq_enq_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_fastpipe = stq_enq_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_fma = stq_enq_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_div = stq_enq_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_sqrt = stq_enq_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_wflags = stq_enq_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_vec = stq_enq_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_rob_idx = stq_enq_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17, :561:27] wire [3:0] stq_enq_e_bits_uop_ldq_idx = stq_enq_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17, :561:27] wire [3:0] stq_enq_e_bits_uop_stq_idx = stq_enq_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_rxq_idx = stq_enq_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_pdst = stq_enq_e_e_bits_uop_pdst; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_prs1 = stq_enq_e_e_bits_uop_prs1; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_prs2 = stq_enq_e_e_bits_uop_prs2; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_prs3 = stq_enq_e_e_bits_uop_prs3; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_ppred = stq_enq_e_e_bits_uop_ppred; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_prs1_busy = stq_enq_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_prs2_busy = stq_enq_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_prs3_busy = stq_enq_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_ppred_busy = stq_enq_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_stale_pdst = stq_enq_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_exception = stq_enq_e_e_bits_uop_exception; // @[lsu.scala:262:17, :561:27] wire [63:0] stq_enq_e_bits_uop_exc_cause = stq_enq_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_mem_cmd = stq_enq_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_mem_size = stq_enq_e_e_bits_uop_mem_size; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_mem_signed = stq_enq_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_uses_ldq = stq_enq_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_uses_stq = stq_enq_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_unique = stq_enq_e_e_bits_uop_is_unique; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_flush_on_commit = stq_enq_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_csr_cmd = stq_enq_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_ldst_is_rs1 = stq_enq_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_ldst = stq_enq_e_e_bits_uop_ldst; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_lrs1 = stq_enq_e_e_bits_uop_lrs1; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_lrs2 = stq_enq_e_e_bits_uop_lrs2; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_lrs3 = stq_enq_e_e_bits_uop_lrs3; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_dst_rtype = stq_enq_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_lrs1_rtype = stq_enq_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_lrs2_rtype = stq_enq_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_frs3_en = stq_enq_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fcn_dw = stq_enq_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_fcn_op = stq_enq_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_val = stq_enq_e_e_bits_uop_fp_val; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_fp_rm = stq_enq_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_fp_typ = stq_enq_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_xcpt_pf_if = stq_enq_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_xcpt_ae_if = stq_enq_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_xcpt_ma_if = stq_enq_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_bp_debug_if = stq_enq_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_bp_xcpt_if = stq_enq_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_debug_fsrc = stq_enq_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_debug_tsrc = stq_enq_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_addr_valid = stq_enq_e_e_bits_addr_valid; // @[lsu.scala:262:17, :561:27] wire [39:0] stq_enq_e_bits_addr_bits = stq_enq_e_e_bits_addr_bits; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_addr_is_virtual = stq_enq_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_data_valid = stq_enq_e_e_bits_data_valid; // @[lsu.scala:262:17, :561:27] wire [63:0] stq_enq_e_bits_data_bits = stq_enq_e_e_bits_data_bits; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_committed = stq_enq_e_e_bits_committed; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_succeeded = stq_enq_e_e_bits_succeeded; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_can_execute = stq_enq_e_e_bits_can_execute; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_cleared = stq_enq_e_e_bits_cleared; // @[lsu.scala:262:17, :561:27] wire [63:0] stq_enq_e_bits_debug_wb_data = stq_enq_e_e_bits_debug_wb_data; // @[lsu.scala:262:17, :561:27] assign stq_enq_e_e_bits_uop_inst = _GEN_200[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_inst = _GEN_201[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_rvc = _GEN_202[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_pc = _GEN_203[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_0 = _GEN_204[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_1 = _GEN_205[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_2 = _GEN_206[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_3 = _GEN_207[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_0 = _GEN_208[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_1 = _GEN_209[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_2 = _GEN_210[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_3 = _GEN_211[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_4 = _GEN_212[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_5 = _GEN_213[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_6 = _GEN_214[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_7 = _GEN_215[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_8 = _GEN_216[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_9 = _GEN_217[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_issued = _GEN_218[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_issued_partial_agen = _GEN_219[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_issued_partial_dgen = _GEN_220[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p1_speculative_child = _GEN_221[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p2_speculative_child = _GEN_222[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p1_bypass_hint = _GEN_223[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p2_bypass_hint = _GEN_224[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p3_bypass_hint = _GEN_225[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_dis_col_sel = _GEN_226[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_br_mask = _GEN_227[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_br_tag = _GEN_228[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_br_type = _GEN_229[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_sfb = _GEN_230[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_fence = _GEN_231[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_fencei = _GEN_232[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_sfence = _GEN_233[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_amo = _GEN_234[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_eret = _GEN_235[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_sys_pc2epc = _GEN_236[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_rocc = _GEN_237[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_mov = _GEN_238[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ftq_idx = _GEN_239[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_edge_inst = _GEN_240[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_pc_lob = _GEN_241[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_taken = _GEN_242[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_imm_rename = _GEN_243[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_imm_sel = _GEN_244[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_pimm = _GEN_245[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_imm_packed = _GEN_246[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_op1_sel = _GEN_247[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_op2_sel = _GEN_248[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ldst = _GEN_249[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_wen = _GEN_250[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ren1 = _GEN_251[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ren2 = _GEN_252[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ren3 = _GEN_253[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_swap12 = _GEN_254[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_swap23 = _GEN_255[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_256[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_257[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_fromint = _GEN_258[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_toint = _GEN_259[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_260[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_fma = _GEN_261[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_div = _GEN_262[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_sqrt = _GEN_263[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_wflags = _GEN_264[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_vec = _GEN_265[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_rob_idx = _GEN_266[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ldq_idx = _GEN_267[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_stq_idx = _GEN_268[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_rxq_idx = _GEN_269[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_pdst = _GEN_270[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs1 = _GEN_271[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs2 = _GEN_272[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs3 = _GEN_273[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ppred = _GEN_274[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs1_busy = _GEN_275[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs2_busy = _GEN_276[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs3_busy = _GEN_277[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ppred_busy = _GEN_278[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_stale_pdst = _GEN_279[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_exception = _GEN_280[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_exc_cause = _GEN_281[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_mem_cmd = _GEN_282[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_mem_size = _GEN_283[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_mem_signed = _GEN_284[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_uses_ldq = _GEN_285[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_uses_stq = _GEN_286[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_unique = _GEN_287[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_flush_on_commit = _GEN_288[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_csr_cmd = _GEN_289[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ldst_is_rs1 = _GEN_290[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ldst = _GEN_291[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs1 = _GEN_292[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs2 = _GEN_293[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs3 = _GEN_294[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_dst_rtype = _GEN_295[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs1_rtype = _GEN_296[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs2_rtype = _GEN_297[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_frs3_en = _GEN_298[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fcn_dw = _GEN_299[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fcn_op = _GEN_300[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_val = _GEN_301[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_rm = _GEN_302[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_typ = _GEN_303[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_xcpt_pf_if = _GEN_304[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_xcpt_ae_if = _GEN_305[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_xcpt_ma_if = _GEN_306[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_bp_debug_if = _GEN_307[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_bp_xcpt_if = _GEN_308[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_fsrc = _GEN_309[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_tsrc = _GEN_310[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_addr_valid = _GEN_311[stq_execute_head]; // @[lsu.scala:262:17, :265:32, :283:29] assign stq_enq_e_e_bits_addr_bits = _GEN_312[stq_execute_head]; // @[lsu.scala:262:17, :265:32, :283:29] assign stq_enq_e_e_bits_addr_is_virtual = _GEN_313[stq_execute_head]; // @[lsu.scala:262:17, :266:32, :283:29] assign stq_enq_e_e_bits_data_valid = _GEN_314[stq_execute_head]; // @[lsu.scala:262:17, :267:32, :283:29] assign stq_enq_e_e_bits_data_bits = _GEN_315[stq_execute_head]; // @[lsu.scala:262:17, :267:32, :283:29] assign stq_enq_e_e_bits_committed = _GEN_316[stq_execute_head]; // @[lsu.scala:262:17, :268:32, :283:29] assign stq_enq_e_e_bits_succeeded = _GEN_317[stq_execute_head]; // @[lsu.scala:262:17, :269:32, :283:29] assign stq_enq_e_e_bits_can_execute = _GEN_318[stq_execute_head]; // @[lsu.scala:262:17, :270:32, :283:29] assign stq_enq_e_e_bits_cleared = _GEN_319[stq_execute_head]; // @[lsu.scala:262:17, :271:32, :283:29] assign stq_enq_e_e_bits_debug_wb_data = _GEN_320[stq_execute_head]; // @[lsu.scala:262:17, :272:32, :283:29] wire _T_1139 = will_fire_store_commit_fast_0 \| will_fire_store_commit_slow_0; // @[lsu.scala:478:41, :479:41, :565:78] wire _stq_execute_queue_io_deq_ready_T; // @[lsu.scala:565:78] assign _stq_execute_queue_io_deq_ready_T = _T_1139; // @[lsu.scala:565:78] wire _fired_store_commit_T; // @[lsu.scala:1048:83] assign _fired_store_commit_T = _T_1139; // @[lsu.scala:565:78, :1048:83] wire _can_enq_store_execute_T = stq_enq_e_valid & stq_enq_e_bits_addr_valid; // @[lsu.scala:561:27, :568:21] wire _can_enq_store_execute_T_1 = _can_enq_store_execute_T & stq_enq_e_bits_data_valid; // @[lsu.scala:561:27, :568:21, :569:31] wire _can_enq_store_execute_T_2 = ~stq_enq_e_bits_addr_is_virtual; // @[lsu.scala:561:27, :571:4] wire _can_enq_store_execute_T_3 = _can_enq_store_execute_T_1 & _can_enq_store_execute_T_2; // @[lsu.scala:569:31, :570:31, :571:4] wire _can_enq_store_execute_T_4 = ~stq_enq_e_bits_uop_exception; // @[lsu.scala:561:27, :572:4] wire _can_enq_store_execute_T_5 = _can_enq_store_execute_T_3 & _can_enq_store_execute_T_4; // @[lsu.scala:570:31, :571:36, :572:4] wire _can_enq_store_execute_T_6 = ~stq_enq_e_bits_uop_is_fence; // @[lsu.scala:561:27, :573:4] wire _can_enq_store_execute_T_7 = _can_enq_store_execute_T_5 & _can_enq_store_execute_T_6; // @[lsu.scala:571:36, :572:34, :573:4] wire _can_enq_store_execute_T_8 = stq_enq_e_bits_committed \| stq_enq_e_bits_uop_is_amo; // @[lsu.scala:561:27, :574:30] wire can_enq_store_execute = _can_enq_store_execute_T_7 & _can_enq_store_execute_T_8; // @[lsu.scala:572:34, :573:33, :574:30] wire [4:0] _GEN_350 = {1'h0, stq_execute_head} + 5'h1; // @[util.scala:211:14] wire [4:0] _stq_execute_head_T; // @[util.scala:211:14] assign _stq_execute_head_T = _GEN_350; // @[util.scala:211:14] wire [4:0] _stq_execute_head_T_3; // @[util.scala:211:14] assign _stq_execute_head_T_3 = _GEN_350; // @[util.scala:211:14] wire [3:0] _stq_execute_head_T_1 = _stq_execute_head_T[3:0]; // @[util.scala:211:14] wire [3:0] _stq_execute_head_T_2 = _stq_execute_head_T_1; // @[util.scala:211:{14,20}] wire _can_fire_load_agen_exec_T = io_core_agen_0_valid_0 & io_core_agen_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7, :586:61] wire can_fire_load_agen_exec_0 = _can_fire_load_agen_exec_T; // @[lsu.scala:321:49, :586:61] wire _can_fire_store_agen_T = io_core_agen_0_valid_0 & io_core_agen_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7, :590:61] wire can_fire_store_agen_0 = _can_fire_store_agen_T; // @[lsu.scala:321:49, :590:61] wire _will_fire_sfence_0_will_fire_T_3 = can_fire_sfence_0; // @[lsu.scala:321:49, :656:32] wire can_fire_release_0 = _can_fire_release_T; // @[lsu.scala:321:49, :598:66] wire _will_fire_release_0_will_fire_T_3 = can_fire_release_0; // @[lsu.scala:321:49, :656:32] wire _can_fire_load_retry_T = _retry_queue_io_deq_valid & _retry_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:533:27, :603:79] reg can_fire_load_retry_REG; // @[lsu.scala:605:41] wire _can_fire_load_retry_T_1 = ~can_fire_load_retry_REG; // @[lsu.scala:605:{33,41}] wire _can_fire_load_retry_T_2 = _can_fire_load_retry_T & _can_fire_load_retry_T_1; // @[lsu.scala:603:79, :604:79, :605:33] wire _can_fire_load_retry_T_3 = _can_fire_load_retry_T_2; // @[lsu.scala:604:79, :605:79] wire can_fire_load_retry_0 = _can_fire_load_retry_T_3; // @[lsu.scala:321:49, :605:79] wire _can_fire_store_retry_T = _retry_queue_io_deq_valid & _retry_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:533:27, :610:79] wire _can_fire_store_retry_T_1 = _can_fire_store_retry_T; // @[lsu.scala:610:79, :611:79] wire can_fire_store_retry_0 = _can_fire_store_retry_T_1; // @[lsu.scala:321:49, :611:79] wire _can_fire_store_commit_slow_T = ~mem_xcpt_valid; // @[lsu.scala:457:29, :617:38] wire _can_fire_store_commit_slow_T_1 = _stq_execute_queue_io_deq_valid & _can_fire_store_commit_slow_T; // @[lsu.scala:558:11, :616:84, :617:38] wire _can_fire_store_commit_slow_T_2 = _can_fire_store_commit_slow_T_1; // @[lsu.scala:616:84, :617:84] wire can_fire_store_commit_slow_0 = _can_fire_store_commit_slow_T_2; // @[lsu.scala:321:49, :617:84] wire _will_fire_store_commit_slow_0_will_fire_T_3 = can_fire_store_commit_slow_0; // @[lsu.scala:321:49, :656:32] wire _can_fire_store_commit_fast_T = can_fire_store_commit_slow_0 & stq_almost_full; // @[lsu.scala:321:49, :494:32, :620:80] wire can_fire_store_commit_fast_0 = _can_fire_store_commit_fast_T; // @[lsu.scala:321:49, :620:80] wire _will_fire_store_commit_fast_0_will_fire_T_3 = can_fire_store_commit_fast_0; // @[lsu.scala:321:49, :656:32] wire block_load_wakeup; // @[lsu.scala:623:35] wire _can_fire_load_wakeup_T = ldq_wakeup_e_valid & ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:510:32, :625:88] wire _can_fire_load_wakeup_T_1 = ~ldq_wakeup_e_bits_succeeded; // @[lsu.scala:510:32, :627:31] wire _can_fire_load_wakeup_T_2 = _can_fire_load_wakeup_T & _can_fire_load_wakeup_T_1; // @[lsu.scala:625:88, :626:88, :627:31] wire _can_fire_load_wakeup_T_3 = ~ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:510:32, :628:31] wire _can_fire_load_wakeup_T_4 = _can_fire_load_wakeup_T_2 & _can_fire_load_wakeup_T_3; // @[lsu.scala:626:88, :627:88, :628:31] wire _can_fire_load_wakeup_T_5 = ~ldq_wakeup_e_bits_executed; // @[lsu.scala:510:32, :629:31] wire _can_fire_load_wakeup_T_6 = _can_fire_load_wakeup_T_4 & _can_fire_load_wakeup_T_5; // @[lsu.scala:627:88, :628:88, :629:31] wire _can_fire_load_wakeup_T_7 = ~ldq_wakeup_e_bits_order_fail; // @[lsu.scala:510:32, :630:31] wire _can_fire_load_wakeup_T_8 = _can_fire_load_wakeup_T_6 & _can_fire_load_wakeup_T_7; // @[lsu.scala:628:88, :629:88, :630:31] wire [3:0] _can_fire_load_wakeup_T_10 = _can_fire_load_wakeup_T_9; wire [15:0] _GEN_351 = {{p1_block_load_mask_15}, {p1_block_load_mask_14}, {p1_block_load_mask_13}, {p1_block_load_mask_12}, {p1_block_load_mask_11}, {p1_block_load_mask_10}, {p1_block_load_mask_9}, {p1_block_load_mask_8}, {p1_block_load_mask_7}, {p1_block_load_mask_6}, {p1_block_load_mask_5}, {p1_block_load_mask_4}, {p1_block_load_mask_3}, {p1_block_load_mask_2}, {p1_block_load_mask_1}, {p1_block_load_mask_0}}; // @[lsu.scala:489:35, :631:31] wire _can_fire_load_wakeup_T_11 = ~_GEN_351[_can_fire_load_wakeup_T_10]; // @[lsu.scala:631:31] wire _can_fire_load_wakeup_T_12 = _can_fire_load_wakeup_T_8 & _can_fire_load_wakeup_T_11; // @[lsu.scala:629:88, :630:88, :631:31] wire [3:0] _can_fire_load_wakeup_T_14 = _can_fire_load_wakeup_T_13; wire [15:0] _GEN_352 = {{p2_block_load_mask_15}, {p2_block_load_mask_14}, {p2_block_load_mask_13}, {p2_block_load_mask_12}, {p2_block_load_mask_11}, {p2_block_load_mask_10}, {p2_block_load_mask_9}, {p2_block_load_mask_8}, {p2_block_load_mask_7}, {p2_block_load_mask_6}, {p2_block_load_mask_5}, {p2_block_load_mask_4}, {p2_block_load_mask_3}, {p2_block_load_mask_2}, {p2_block_load_mask_1}, {p2_block_load_mask_0}}; // @[lsu.scala:490:35, :632:31] wire _can_fire_load_wakeup_T_15 = ~_GEN_352[_can_fire_load_wakeup_T_14]; // @[lsu.scala:632:31] wire _can_fire_load_wakeup_T_16 = _can_fire_load_wakeup_T_12 & _can_fire_load_wakeup_T_15; // @[lsu.scala:630:88, :631:88, :632:31] reg can_fire_load_wakeup_REG; // @[lsu.scala:633:39] wire _can_fire_load_wakeup_T_17 = ~can_fire_load_wakeup_REG; // @[lsu.scala:633:{31,39}] wire _can_fire_load_wakeup_T_18 = _can_fire_load_wakeup_T_16 & _can_fire_load_wakeup_T_17; // @[lsu.scala:631:88, :632:88, :633:31] wire _can_fire_load_wakeup_T_19 = ~block_load_wakeup; // @[lsu.scala:623:35, :634:31] wire _can_fire_load_wakeup_T_20 = _can_fire_load_wakeup_T_18 & _can_fire_load_wakeup_T_19; // @[lsu.scala:632:88, :633:88, :634:31] wire _can_fire_load_wakeup_T_21 = _can_fire_load_wakeup_T_20; // @[lsu.scala:633:88, :634:88] wire _can_fire_load_wakeup_T_22 = ~ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:510:32, :636:32] wire _can_fire_load_wakeup_T_23 = ldq_head == ldq_wakeup_idx; // @[lsu.scala:278:29, :506:31, :637:84] wire _can_fire_load_wakeup_T_24 = io_core_commit_load_at_rob_head_0 & _can_fire_load_wakeup_T_23; // @[lsu.scala:211:7, :636:107, :637:84] wire _can_fire_load_wakeup_T_25 = ldq_wakeup_e_bits_st_dep_mask == 16'h0; // @[lsu.scala:510:32, :638:112] wire _can_fire_load_wakeup_T_26 = _can_fire_load_wakeup_T_24 & _can_fire_load_wakeup_T_25; // @[lsu.scala:636:107, :637:103, :638:112] wire _can_fire_load_wakeup_T_27 = _can_fire_load_wakeup_T_22 \| _can_fire_load_wakeup_T_26; // @[lsu.scala:636:{32,71}, :637:103] wire _can_fire_load_wakeup_T_28 = _can_fire_load_wakeup_T_21 & _can_fire_load_wakeup_T_27; // @[lsu.scala:634:88, :635:88, :636:71] wire can_fire_load_wakeup_0 = _can_fire_load_wakeup_T_28; // @[lsu.scala:321:49, :635:88] wire _will_fire_load_wakeup_0_will_fire_T_3 = can_fire_load_wakeup_0; // @[lsu.scala:321:49, :656:32] wire can_fire_hella_incoming_0; // @[lsu.scala:641:42] wire can_fire_hella_wakeup_0; // @[lsu.scala:644:42] wire _will_fire_hella_wakeup_0_will_fire_T_3 = can_fire_hella_wakeup_0; // @[lsu.scala:644:42, :656:32] wire _exe_tlb_valid_0_T; // @[lsu.scala:696:25] wire exe_tlb_valid_0; // @[lsu.scala:649:27] wire _will_fire_sfence_0_will_fire_T_7 = _will_fire_sfence_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] assign will_fire_sfence_0_will_fire = _will_fire_sfence_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] assign will_fire_sfence_0 = will_fire_sfence_0_will_fire; // @[lsu.scala:472:41, :657:65] wire _will_fire_sfence_0_T = will_fire_sfence_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_sfence_0_T_1 = ~_will_fire_sfence_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_sfence_0_T_2 = _will_fire_sfence_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_store_commit_fast_0_T_2 = _will_fire_sfence_0_T_2; // @[lsu.scala:659:31] wire _will_fire_store_commit_fast_0_will_fire_T = ~_will_fire_sfence_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_commit_fast_0_will_fire_T_7 = _will_fire_store_commit_fast_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] assign will_fire_store_commit_fast_0_will_fire = _will_fire_store_commit_fast_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] assign will_fire_store_commit_fast_0 = will_fire_store_commit_fast_0_will_fire; // @[lsu.scala:478:41, :657:65] wire _will_fire_store_commit_fast_0_T_6 = will_fire_store_commit_fast_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_store_commit_fast_0_T_7 = ~_will_fire_store_commit_fast_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_store_commit_fast_0_T_8 = _will_fire_store_commit_fast_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_load_agen_exec_0_will_fire_T = ~_will_fire_store_commit_fast_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_agen_exec_0_will_fire_T_1 = _will_fire_load_agen_exec_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_load_agen_exec_0_will_fire_T_2 = ~_will_fire_load_agen_exec_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_load_agen_exec_0_will_fire_T_3 = can_fire_load_agen_exec_0 & _will_fire_load_agen_exec_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_load_agen_exec_0_will_fire_T_7 = _will_fire_load_agen_exec_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_load_agen_exec_0_will_fire_T_8 = ~_will_fire_store_commit_fast_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_load_agen_exec_0_will_fire_T_9 = _will_fire_load_agen_exec_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_load_agen_exec_0_will_fire_T_10 = ~_will_fire_load_agen_exec_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_load_agen_exec_0_will_fire = _will_fire_load_agen_exec_0_will_fire_T_7 & _will_fire_load_agen_exec_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_load_agen_exec_0 = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:469:39, :657:65] wire _will_fire_load_agen_exec_0_T = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_load_agen_exec_0_T_3 = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_agen_exec_0_T_6 = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_load_agen_exec_0_T_1 = ~_will_fire_load_agen_exec_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_load_agen_exec_0_T_2 = _will_fire_store_commit_fast_0_T_2 & _will_fire_load_agen_exec_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_load_agen_exec_0_T_4 = ~_will_fire_load_agen_exec_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_agen_exec_0_T_5 = _will_fire_load_agen_exec_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_load_agen_exec_0_T_7 = ~_will_fire_load_agen_exec_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_load_agen_exec_0_T_8 = _will_fire_store_commit_fast_0_T_8 & _will_fire_load_agen_exec_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_load_agen_0_T_8 = _will_fire_load_agen_exec_0_T_8; // @[lsu.scala:661:31] wire _will_fire_load_agen_0_will_fire_T = ~_will_fire_load_agen_exec_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_agen_0_will_fire_T_1 = _will_fire_load_agen_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_load_agen_0_will_fire_T_2 = ~_will_fire_load_agen_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_load_agen_0_will_fire_T_3 = can_fire_load_agen_exec_0 & _will_fire_load_agen_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_load_agen_0_will_fire_T_4 = ~_will_fire_load_agen_exec_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_load_agen_0_will_fire_T_5 = _will_fire_load_agen_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_load_agen_0_will_fire_T_6 = ~_will_fire_load_agen_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_load_agen_0_will_fire_T_7 = _will_fire_load_agen_0_will_fire_T_3 & _will_fire_load_agen_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_load_agen_0_will_fire = _will_fire_load_agen_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_load_agen_0_will_fire_T_8 = ~_will_fire_load_agen_exec_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_load_agen_0 = will_fire_load_agen_0_will_fire; // @[lsu.scala:470:41, :657:65] wire _will_fire_load_agen_0_T = will_fire_load_agen_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_load_agen_0_T_3 = will_fire_load_agen_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_agen_0_T_1 = ~_will_fire_load_agen_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_load_agen_0_T_2 = _will_fire_load_agen_exec_0_T_2 & _will_fire_load_agen_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_load_agen_0_T_4 = ~_will_fire_load_agen_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_agen_0_T_5 = _will_fire_load_agen_exec_0_T_5 & _will_fire_load_agen_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_store_agen_0_T_8 = _will_fire_load_agen_0_T_8; // @[lsu.scala:661:31] wire _will_fire_store_agen_0_will_fire_T = ~_will_fire_load_agen_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_agen_0_will_fire_T_1 = _will_fire_store_agen_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_store_agen_0_will_fire_T_2 = ~_will_fire_store_agen_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_store_agen_0_will_fire_T_3 = can_fire_store_agen_0 & _will_fire_store_agen_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_store_agen_0_will_fire_T_4 = ~_will_fire_load_agen_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_store_agen_0_will_fire_T_5 = _will_fire_store_agen_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_store_agen_0_will_fire_T_6 = ~_will_fire_store_agen_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_store_agen_0_will_fire_T_7 = _will_fire_store_agen_0_will_fire_T_3 & _will_fire_store_agen_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_store_agen_0_will_fire = _will_fire_store_agen_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_store_agen_0_will_fire_T_8 = ~_will_fire_load_agen_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_store_agen_0 = will_fire_store_agen_0_will_fire; // @[lsu.scala:471:41, :657:65] wire _will_fire_store_agen_0_T = will_fire_store_agen_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_store_agen_0_T_3 = will_fire_store_agen_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_store_agen_0_T_1 = ~_will_fire_store_agen_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_store_agen_0_T_2 = _will_fire_load_agen_0_T_2 & _will_fire_store_agen_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_release_0_T_2 = _will_fire_store_agen_0_T_2; // @[lsu.scala:659:31] wire _will_fire_store_agen_0_T_4 = ~_will_fire_store_agen_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_store_agen_0_T_5 = _will_fire_load_agen_0_T_5 & _will_fire_store_agen_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_release_0_T_8 = _will_fire_store_agen_0_T_8; // @[lsu.scala:661:31] wire _will_fire_release_0_will_fire_T = ~_will_fire_store_agen_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_release_0_will_fire_T_4 = ~_will_fire_store_agen_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_release_0_will_fire_T_5 = _will_fire_release_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_release_0_will_fire_T_6 = ~_will_fire_release_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_release_0_will_fire_T_7 = _will_fire_release_0_will_fire_T_3 & _will_fire_release_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_release_0_will_fire = _will_fire_release_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_release_0_will_fire_T_8 = ~_will_fire_store_agen_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_release_0 = will_fire_release_0_will_fire; // @[lsu.scala:475:41, :657:65] wire _will_fire_release_0_T_3 = will_fire_release_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_release_0_T_4 = ~_will_fire_release_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_release_0_T_5 = _will_fire_store_agen_0_T_5 & _will_fire_release_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_hella_incoming_0_T_5 = _will_fire_release_0_T_5; // @[lsu.scala:660:31] wire _will_fire_hella_incoming_0_will_fire_T = ~_will_fire_release_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_hella_incoming_0_will_fire_T_1 = _will_fire_hella_incoming_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_hella_incoming_0_will_fire_T_2 = ~_will_fire_hella_incoming_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_hella_incoming_0_will_fire_T_3 = can_fire_hella_incoming_0 & _will_fire_hella_incoming_0_will_fire_T_2; // @[lsu.scala:641:42, :656:{32,35}] wire _will_fire_hella_incoming_0_will_fire_T_7 = _will_fire_hella_incoming_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_hella_incoming_0_will_fire_T_4 = ~_will_fire_release_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_hella_incoming_0_will_fire_T_8 = ~_will_fire_release_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_hella_incoming_0_will_fire_T_9 = _will_fire_hella_incoming_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_hella_incoming_0_will_fire_T_10 = ~_will_fire_hella_incoming_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_hella_incoming_0_will_fire = _will_fire_hella_incoming_0_will_fire_T_7 & _will_fire_hella_incoming_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_hella_incoming_0 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:473:41, :657:65] wire _will_fire_hella_incoming_0_T = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_hella_incoming_0_T_6 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_hella_incoming_0_T_1 = ~_will_fire_hella_incoming_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_hella_incoming_0_T_2 = _will_fire_release_0_T_2 & _will_fire_hella_incoming_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_hella_wakeup_0_T_2 = _will_fire_hella_incoming_0_T_2; // @[lsu.scala:659:31] wire _will_fire_hella_wakeup_0_T_5 = _will_fire_hella_incoming_0_T_5; // @[lsu.scala:660:31] wire _will_fire_hella_incoming_0_T_7 = ~_will_fire_hella_incoming_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_hella_incoming_0_T_8 = _will_fire_release_0_T_8 & _will_fire_hella_incoming_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_hella_wakeup_0_will_fire_T = ~_will_fire_hella_incoming_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_hella_wakeup_0_will_fire_T_7 = _will_fire_hella_wakeup_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_hella_wakeup_0_will_fire_T_4 = ~_will_fire_hella_incoming_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_hella_wakeup_0_will_fire_T_8 = ~_will_fire_hella_incoming_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_hella_wakeup_0_will_fire_T_9 = _will_fire_hella_wakeup_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_hella_wakeup_0_will_fire_T_10 = ~_will_fire_hella_wakeup_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_hella_wakeup_0_will_fire = _will_fire_hella_wakeup_0_will_fire_T_7 & _will_fire_hella_wakeup_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_hella_wakeup_0 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:474:41, :657:65] wire _will_fire_hella_wakeup_0_T_6 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_hella_wakeup_0_T_7 = ~_will_fire_hella_wakeup_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_hella_wakeup_0_T_8 = _will_fire_hella_incoming_0_T_8 & _will_fire_hella_wakeup_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_store_retry_0_T_8 = _will_fire_hella_wakeup_0_T_8; // @[lsu.scala:661:31] wire _will_fire_store_retry_0_will_fire_T = ~_will_fire_hella_wakeup_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_retry_0_will_fire_T_1 = _will_fire_store_retry_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_store_retry_0_will_fire_T_2 = ~_will_fire_store_retry_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_store_retry_0_will_fire_T_3 = can_fire_store_retry_0 & _will_fire_store_retry_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_store_retry_0_will_fire_T_4 = ~_will_fire_hella_wakeup_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_store_retry_0_will_fire_T_5 = _will_fire_store_retry_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_store_retry_0_will_fire_T_6 = ~_will_fire_store_retry_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_store_retry_0_will_fire_T_7 = _will_fire_store_retry_0_will_fire_T_3 & _will_fire_store_retry_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_store_retry_0_will_fire = _will_fire_store_retry_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_store_retry_0_will_fire_T_8 = ~_will_fire_hella_wakeup_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_store_retry_0 = will_fire_store_retry_0_will_fire; // @[lsu.scala:477:41, :657:65] wire _will_fire_store_retry_0_T = will_fire_store_retry_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_store_retry_0_T_3 = will_fire_store_retry_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_store_retry_0_T_1 = ~_will_fire_store_retry_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_store_retry_0_T_2 = _will_fire_hella_wakeup_0_T_2 & _will_fire_store_retry_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_store_retry_0_T_4 = ~_will_fire_store_retry_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_store_retry_0_T_5 = _will_fire_hella_wakeup_0_T_5 & _will_fire_store_retry_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_load_retry_0_will_fire_T = ~_will_fire_store_retry_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_retry_0_will_fire_T_1 = _will_fire_load_retry_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_load_retry_0_will_fire_T_2 = ~_will_fire_load_retry_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_load_retry_0_will_fire_T_3 = can_fire_load_retry_0 & _will_fire_load_retry_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_load_retry_0_will_fire_T_4 = ~_will_fire_store_retry_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_load_retry_0_will_fire_T_5 = _will_fire_load_retry_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_load_retry_0_will_fire_T_6 = ~_will_fire_load_retry_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_load_retry_0_will_fire_T_7 = _will_fire_load_retry_0_will_fire_T_3 & _will_fire_load_retry_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] wire _will_fire_load_retry_0_will_fire_T_8 = ~_will_fire_store_retry_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_load_retry_0_will_fire_T_9 = _will_fire_load_retry_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_load_retry_0_will_fire_T_10 = ~_will_fire_load_retry_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_load_retry_0_will_fire = _will_fire_load_retry_0_will_fire_T_7 & _will_fire_load_retry_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_load_retry_0 = will_fire_load_retry_0_will_fire; // @[lsu.scala:476:41, :657:65] wire _will_fire_load_retry_0_T = will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_load_retry_0_T_3 = will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_retry_0_T_6 = will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_load_retry_0_T_1 = ~_will_fire_load_retry_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_load_retry_0_T_2 = _will_fire_store_retry_0_T_2 & _will_fire_load_retry_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_load_wakeup_0_T_2 = _will_fire_load_retry_0_T_2; // @[lsu.scala:659:31] wire _will_fire_load_retry_0_T_4 = ~_will_fire_load_retry_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_retry_0_T_5 = _will_fire_store_retry_0_T_5 & _will_fire_load_retry_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_load_retry_0_T_7 = ~_will_fire_load_retry_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_load_retry_0_T_8 = _will_fire_store_retry_0_T_8 & _will_fire_load_retry_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_load_wakeup_0_will_fire_T = ~_will_fire_load_retry_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_wakeup_0_will_fire_T_4 = ~_will_fire_load_retry_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_load_wakeup_0_will_fire_T_5 = _will_fire_load_wakeup_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_load_wakeup_0_will_fire_T_6 = ~_will_fire_load_wakeup_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_load_wakeup_0_will_fire_T_7 = _will_fire_load_wakeup_0_will_fire_T_3 & _will_fire_load_wakeup_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] wire _will_fire_load_wakeup_0_will_fire_T_8 = ~_will_fire_load_retry_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_load_wakeup_0_will_fire_T_9 = _will_fire_load_wakeup_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_load_wakeup_0_will_fire_T_10 = ~_will_fire_load_wakeup_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_load_wakeup_0_will_fire = _will_fire_load_wakeup_0_will_fire_T_7 & _will_fire_load_wakeup_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_load_wakeup_0 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:480:41, :657:65] wire _will_fire_load_wakeup_0_T_3 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_wakeup_0_T_6 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_store_commit_slow_0_T_2 = _will_fire_load_wakeup_0_T_2; // @[lsu.scala:659:31] wire _will_fire_load_wakeup_0_T_4 = ~_will_fire_load_wakeup_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_wakeup_0_T_5 = _will_fire_load_retry_0_T_5 & _will_fire_load_wakeup_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_store_commit_slow_0_T_5 = _will_fire_load_wakeup_0_T_5; // @[lsu.scala:660:31] wire _will_fire_load_wakeup_0_T_7 = ~_will_fire_load_wakeup_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_load_wakeup_0_T_8 = _will_fire_load_retry_0_T_8 & _will_fire_load_wakeup_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_store_commit_slow_0_will_fire_T = ~_will_fire_load_wakeup_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_commit_slow_0_will_fire_T_7 = _will_fire_store_commit_slow_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_store_commit_slow_0_will_fire_T_4 = ~_will_fire_load_wakeup_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_store_commit_slow_0_will_fire_T_8 = ~_will_fire_load_wakeup_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_store_commit_slow_0_will_fire_T_9 = _will_fire_store_commit_slow_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_store_commit_slow_0_will_fire_T_10 = ~_will_fire_store_commit_slow_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_store_commit_slow_0_will_fire = _will_fire_store_commit_slow_0_will_fire_T_7 & _will_fire_store_commit_slow_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_store_commit_slow_0 = will_fire_store_commit_slow_0_will_fire; // @[lsu.scala:479:41, :657:65] wire _will_fire_store_commit_slow_0_T_6 = will_fire_store_commit_slow_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_store_commit_slow_0_T_7 = ~_will_fire_store_commit_slow_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_store_commit_slow_0_T_8 = _will_fire_load_wakeup_0_T_8 & _will_fire_store_commit_slow_0_T_7; // @[lsu.scala:661:{31,34}] wire _T_182 = will_fire_load_agen_exec_0 \| will_fire_load_agen_0; // @[lsu.scala:469:39, :470:41, :687:61] wire _exe_tlb_uop_T; // @[lsu.scala:717:53] assign _exe_tlb_uop_T = _T_182; // @[lsu.scala:687:61, :717:53] wire _exe_tlb_vaddr_T; // @[lsu.scala:726:53] assign _exe_tlb_vaddr_T = _T_182; // @[lsu.scala:687:61, :726:53] wire _exe_size_T; // @[lsu.scala:738:52] assign _exe_size_T = _T_182; // @[lsu.scala:687:61, :738:52] wire _exe_cmd_T; // @[lsu.scala:746:52] assign _exe_cmd_T = _T_182; // @[lsu.scala:687:61, :746:52] wire _ldq_idx_T; // @[lsu.scala:969:48] assign _ldq_idx_T = _T_182; // @[lsu.scala:687:61, :969:48] wire _GEN_353 = ldq_wakeup_idx == 4'h0; // @[lsu.scala:506:31, :690:49] wire _GEN_354 = ldq_wakeup_idx == 4'h1; // @[lsu.scala:506:31, :690:49] wire _GEN_355 = ldq_wakeup_idx == 4'h2; // @[lsu.scala:506:31, :690:49] wire _GEN_356 = ldq_wakeup_idx == 4'h3; // @[lsu.scala:506:31, :690:49] wire _GEN_357 = ldq_wakeup_idx == 4'h4; // @[lsu.scala:506:31, :690:49] wire _GEN_358 = ldq_wakeup_idx == 4'h5; // @[lsu.scala:506:31, :690:49] wire _GEN_359 = ldq_wakeup_idx == 4'h6; // @[lsu.scala:506:31, :690:49] wire _GEN_360 = ldq_wakeup_idx == 4'h7; // @[lsu.scala:506:31, :690:49] wire _GEN_361 = ldq_wakeup_idx == 4'h8; // @[lsu.scala:506:31, :690:49] wire _GEN_362 = ldq_wakeup_idx == 4'h9; // @[lsu.scala:506:31, :690:49] wire _GEN_363 = ldq_wakeup_idx == 4'hA; // @[lsu.scala:506:31, :690:49] wire _GEN_364 = ldq_wakeup_idx == 4'hB; // @[lsu.scala:506:31, :690:49] wire _GEN_365 = ldq_wakeup_idx == 4'hC; // @[lsu.scala:506:31, :690:49] wire _GEN_366 = ldq_wakeup_idx == 4'hD; // @[lsu.scala:506:31, :690:49] wire _GEN_367 = ldq_wakeup_idx == 4'hE; // @[lsu.scala:506:31, :690:49] wire _GEN_368 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h0; // @[lsu.scala:533:27, :694:49] assign block_load_mask_0 = will_fire_load_wakeup_0 ? _GEN_353 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h0 : will_fire_load_retry_0 & _GEN_368; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_369 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h1; // @[lsu.scala:533:27, :694:49] assign block_load_mask_1 = will_fire_load_wakeup_0 ? _GEN_354 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h1 : will_fire_load_retry_0 & _GEN_369; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_370 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h2; // @[lsu.scala:533:27, :694:49] assign block_load_mask_2 = will_fire_load_wakeup_0 ? _GEN_355 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h2 : will_fire_load_retry_0 & _GEN_370; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_371 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h3; // @[lsu.scala:533:27, :694:49] assign block_load_mask_3 = will_fire_load_wakeup_0 ? _GEN_356 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h3 : will_fire_load_retry_0 & _GEN_371; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_372 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h4; // @[lsu.scala:533:27, :694:49] assign block_load_mask_4 = will_fire_load_wakeup_0 ? _GEN_357 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h4 : will_fire_load_retry_0 & _GEN_372; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_373 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h5; // @[lsu.scala:533:27, :694:49] assign block_load_mask_5 = will_fire_load_wakeup_0 ? _GEN_358 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h5 : will_fire_load_retry_0 & _GEN_373; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_374 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h6; // @[lsu.scala:533:27, :694:49] assign block_load_mask_6 = will_fire_load_wakeup_0 ? _GEN_359 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h6 : will_fire_load_retry_0 & _GEN_374; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_375 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h7; // @[lsu.scala:533:27, :694:49] assign block_load_mask_7 = will_fire_load_wakeup_0 ? _GEN_360 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h7 : will_fire_load_retry_0 & _GEN_375; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_376 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h8; // @[lsu.scala:533:27, :694:49] assign block_load_mask_8 = will_fire_load_wakeup_0 ? _GEN_361 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h8 : will_fire_load_retry_0 & _GEN_376; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_377 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h9; // @[lsu.scala:533:27, :694:49] assign block_load_mask_9 = will_fire_load_wakeup_0 ? _GEN_362 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h9 : will_fire_load_retry_0 & _GEN_377; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_378 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'hA; // @[lsu.scala:533:27, :694:49] assign block_load_mask_10 = will_fire_load_wakeup_0 ? _GEN_363 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'hA : will_fire_load_retry_0 & _GEN_378; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_379 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'hB; // @[lsu.scala:533:27, :694:49] assign block_load_mask_11 = will_fire_load_wakeup_0 ? _GEN_364 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'hB : will_fire_load_retry_0 & _GEN_379; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_380 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'hC; // @[lsu.scala:533:27, :694:49] assign block_load_mask_12 = will_fire_load_wakeup_0 ? _GEN_365 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'hC : will_fire_load_retry_0 & _GEN_380; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_381 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'hD; // @[lsu.scala:533:27, :694:49] assign block_load_mask_13 = will_fire_load_wakeup_0 ? _GEN_366 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'hD : will_fire_load_retry_0 & _GEN_381; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_382 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'hE; // @[lsu.scala:533:27, :694:49] assign block_load_mask_14 = will_fire_load_wakeup_0 ? _GEN_367 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'hE : will_fire_load_retry_0 & _GEN_382; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] assign block_load_mask_15 = will_fire_load_wakeup_0 ? (&ldq_wakeup_idx) : _T_182 ? (&io_core_agen_0_bits_uop_ldq_idx_0) : will_fire_load_retry_0 & (&_retry_queue_io_deq_bits_uop_ldq_idx); // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :506:31, :533:27, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] assign _exe_tlb_valid_0_T = ~_will_fire_store_commit_slow_0_T_2; // @[lsu.scala:659:31, :696:25] assign exe_tlb_valid_0 = _exe_tlb_valid_0_T; // @[lsu.scala:649:27, :696:25] wire [31:0] _exe_tlb_uop_T_3_inst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_inst : 32'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [31:0] _exe_tlb_uop_T_3_debug_inst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_inst : 32'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_rvc = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_rvc; // @[lsu.scala:533:27, :720:{24,53}] wire [39:0] _exe_tlb_uop_T_3_debug_pc = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_pc : 40'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_0 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_1; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_2 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_2; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_3 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_3; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_0 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_1; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_2 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_2; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_3 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_3; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_4 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_4; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_5 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_5; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_6 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_6; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_7 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_7; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_8 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_8; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_9 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_9; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_issued = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_issued; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_issued_partial_agen = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_issued_partial_agen; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_issued_partial_dgen = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_iw_p1_speculative_child = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_iw_p1_speculative_child : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_iw_p2_speculative_child = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_iw_p2_speculative_child : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_p1_bypass_hint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_p2_bypass_hint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_p3_bypass_hint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_dis_col_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_dis_col_sel : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [11:0] _exe_tlb_uop_T_3_br_mask = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_br_mask : 12'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [3:0] _exe_tlb_uop_T_3_br_tag = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_br_tag : 4'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [3:0] _exe_tlb_uop_T_3_br_type = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_br_type : 4'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_sfb = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_sfb; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_fence = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_fence; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_fencei = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_fencei; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_sfence = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_sfence; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_amo = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_amo; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_eret = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_eret; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_sys_pc2epc = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_sys_pc2epc; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_rocc = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_rocc; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_mov = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_mov; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_ftq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_edge_inst = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_edge_inst; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_pc_lob = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_pc_lob : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_taken = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_taken; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_imm_rename = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_imm_rename; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_imm_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_imm_sel : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_pimm = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_pimm : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [19:0] _exe_tlb_uop_T_3_imm_packed = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_imm_packed : 20'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_op1_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_op1_sel : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_op2_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_op2_sel : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ldst = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ldst; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_wen = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_wen; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ren1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ren1; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ren2 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ren2; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ren3 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ren3; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_swap12 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_swap12; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_swap23 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_swap23; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_fp_ctrl_typeTagIn = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_fp_ctrl_typeTagOut = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_fromint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_fromint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_toint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_toint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_fastpipe = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_fma = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_fma; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_div = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_div; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_sqrt = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_wflags = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_wflags; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_vec = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_vec; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_rob_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_rob_idx : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [3:0] _exe_tlb_uop_T_3_ldq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ldq_idx : 4'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [3:0] _exe_tlb_uop_T_3_stq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_stq_idx : 4'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_rxq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_pdst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_pdst : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_prs1 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_prs1 : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_prs2 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_prs2 : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_prs3 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_prs3 : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_ppred = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ppred : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_prs1_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_prs1_busy; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_prs2_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_prs2_busy; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_prs3_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_prs3_busy; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_ppred_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_ppred_busy; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_stale_pdst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_exception = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_exception; // @[lsu.scala:533:27, :720:{24,53}] wire [63:0] _exe_tlb_uop_T_3_exc_cause = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_exc_cause : 64'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_mem_cmd = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_mem_size = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_mem_size : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_mem_signed = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_mem_signed; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_uses_ldq = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_uses_stq = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_unique = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_unique; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_flush_on_commit = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_flush_on_commit; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_csr_cmd = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_ldst_is_rs1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_ldst_is_rs1; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_ldst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ldst : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_lrs1 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs1 : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_lrs2 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs2 : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_lrs3 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs3 : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_dst_rtype = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_lrs1_rtype = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_lrs2_rtype = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_frs3_en = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_frs3_en; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fcn_dw = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fcn_dw; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_fcn_op = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fcn_op : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_val = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_val; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_fp_rm = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_rm : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_fp_typ = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_typ : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_xcpt_pf_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_xcpt_pf_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_xcpt_ae_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_xcpt_ae_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_xcpt_ma_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_xcpt_ma_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_bp_debug_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_bp_debug_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_bp_xcpt_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_bp_xcpt_if; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_debug_fsrc = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_debug_tsrc = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [31:0] _exe_tlb_uop_T_4_inst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_inst : _exe_tlb_uop_T_3_inst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [31:0] _exe_tlb_uop_T_4_debug_inst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_inst : _exe_tlb_uop_T_3_debug_inst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_rvc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_rvc : _exe_tlb_uop_T_3_is_rvc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [39:0] _exe_tlb_uop_T_4_debug_pc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_pc : _exe_tlb_uop_T_3_debug_pc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_0 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_0 : _exe_tlb_uop_T_3_iq_type_0; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_1 : _exe_tlb_uop_T_3_iq_type_1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_2 : _exe_tlb_uop_T_3_iq_type_2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_3 : _exe_tlb_uop_T_3_iq_type_3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_0 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_0 : _exe_tlb_uop_T_3_fu_code_0; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_1 : _exe_tlb_uop_T_3_fu_code_1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_2 : _exe_tlb_uop_T_3_fu_code_2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_3 : _exe_tlb_uop_T_3_fu_code_3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_4 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_4 : _exe_tlb_uop_T_3_fu_code_4; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_5 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_5 : _exe_tlb_uop_T_3_fu_code_5; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_6 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_6 : _exe_tlb_uop_T_3_fu_code_6; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_7 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_7 : _exe_tlb_uop_T_3_fu_code_7; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_8 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_8 : _exe_tlb_uop_T_3_fu_code_8; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_9 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_9 : _exe_tlb_uop_T_3_fu_code_9; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_issued = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_issued : _exe_tlb_uop_T_3_iw_issued; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_issued_partial_agen = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_issued_partial_agen : _exe_tlb_uop_T_3_iw_issued_partial_agen; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_issued_partial_dgen = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _exe_tlb_uop_T_3_iw_issued_partial_dgen; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_iw_p1_speculative_child = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p1_speculative_child : _exe_tlb_uop_T_3_iw_p1_speculative_child; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_iw_p2_speculative_child = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p2_speculative_child : _exe_tlb_uop_T_3_iw_p2_speculative_child; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_p1_bypass_hint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _exe_tlb_uop_T_3_iw_p1_bypass_hint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_p2_bypass_hint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _exe_tlb_uop_T_3_iw_p2_bypass_hint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_p3_bypass_hint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _exe_tlb_uop_T_3_iw_p3_bypass_hint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_dis_col_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_dis_col_sel : _exe_tlb_uop_T_3_dis_col_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [11:0] _exe_tlb_uop_T_4_br_mask = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_br_mask : _exe_tlb_uop_T_3_br_mask; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [3:0] _exe_tlb_uop_T_4_br_tag = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_br_tag : _exe_tlb_uop_T_3_br_tag; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [3:0] _exe_tlb_uop_T_4_br_type = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_br_type : _exe_tlb_uop_T_3_br_type; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_sfb = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_sfb : _exe_tlb_uop_T_3_is_sfb; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_fence = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_fence : _exe_tlb_uop_T_3_is_fence; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_fencei = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_fencei : _exe_tlb_uop_T_3_is_fencei; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_sfence = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_sfence : _exe_tlb_uop_T_3_is_sfence; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_amo = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_amo : _exe_tlb_uop_T_3_is_amo; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_eret = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_eret : _exe_tlb_uop_T_3_is_eret; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_sys_pc2epc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_3_is_sys_pc2epc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_rocc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_rocc : _exe_tlb_uop_T_3_is_rocc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_mov = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_mov : _exe_tlb_uop_T_3_is_mov; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_ftq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ftq_idx : _exe_tlb_uop_T_3_ftq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_edge_inst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_edge_inst : _exe_tlb_uop_T_3_edge_inst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_pc_lob = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_pc_lob : _exe_tlb_uop_T_3_pc_lob; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_taken = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_taken : _exe_tlb_uop_T_3_taken; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_imm_rename = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_imm_rename : _exe_tlb_uop_T_3_imm_rename; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_imm_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_imm_sel : _exe_tlb_uop_T_3_imm_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_pimm = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_pimm : _exe_tlb_uop_T_3_pimm; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [19:0] _exe_tlb_uop_T_4_imm_packed = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_imm_packed : _exe_tlb_uop_T_3_imm_packed; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_op1_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_op1_sel : _exe_tlb_uop_T_3_op1_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_op2_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_op2_sel : _exe_tlb_uop_T_3_op2_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ldst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ldst : _exe_tlb_uop_T_3_fp_ctrl_ldst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_wen = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_wen : _exe_tlb_uop_T_3_fp_ctrl_wen; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ren1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _exe_tlb_uop_T_3_fp_ctrl_ren1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ren2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _exe_tlb_uop_T_3_fp_ctrl_ren2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ren3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _exe_tlb_uop_T_3_fp_ctrl_ren3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_swap12 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _exe_tlb_uop_T_3_fp_ctrl_swap12; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_swap23 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _exe_tlb_uop_T_3_fp_ctrl_swap23; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_fp_ctrl_typeTagIn = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _exe_tlb_uop_T_3_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_fp_ctrl_typeTagOut = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _exe_tlb_uop_T_3_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_fromint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_fromint : _exe_tlb_uop_T_3_fp_ctrl_fromint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_toint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_toint : _exe_tlb_uop_T_3_fp_ctrl_toint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_fastpipe = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _exe_tlb_uop_T_3_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_fma = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_fma : _exe_tlb_uop_T_3_fp_ctrl_fma; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_div = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_div : _exe_tlb_uop_T_3_fp_ctrl_div; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_sqrt = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _exe_tlb_uop_T_3_fp_ctrl_sqrt; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_wflags = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_wflags : _exe_tlb_uop_T_3_fp_ctrl_wflags; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_vec = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_vec : _exe_tlb_uop_T_3_fp_ctrl_vec; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_rob_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_rob_idx : _exe_tlb_uop_T_3_rob_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [3:0] _exe_tlb_uop_T_4_ldq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ldq_idx : _exe_tlb_uop_T_3_ldq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [3:0] _exe_tlb_uop_T_4_stq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_stq_idx : _exe_tlb_uop_T_3_stq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_rxq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_rxq_idx : _exe_tlb_uop_T_3_rxq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_pdst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_pdst : _exe_tlb_uop_T_3_pdst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_prs1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs1 : _exe_tlb_uop_T_3_prs1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_prs2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs2 : _exe_tlb_uop_T_3_prs2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_prs3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs3 : _exe_tlb_uop_T_3_prs3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_ppred = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ppred : _exe_tlb_uop_T_3_ppred; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_prs1_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs1_busy : _exe_tlb_uop_T_3_prs1_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_prs2_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs2_busy : _exe_tlb_uop_T_3_prs2_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_prs3_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs3_busy : _exe_tlb_uop_T_3_prs3_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_ppred_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ppred_busy : _exe_tlb_uop_T_3_ppred_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_stale_pdst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_stale_pdst : _exe_tlb_uop_T_3_stale_pdst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_exception = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_exception : _exe_tlb_uop_T_3_exception; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [63:0] _exe_tlb_uop_T_4_exc_cause = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_exc_cause : _exe_tlb_uop_T_3_exc_cause; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_mem_cmd = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_mem_cmd : _exe_tlb_uop_T_3_mem_cmd; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_mem_size = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_mem_size : _exe_tlb_uop_T_3_mem_size; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_mem_signed = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_mem_signed : _exe_tlb_uop_T_3_mem_signed; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_uses_ldq = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_uses_ldq : _exe_tlb_uop_T_3_uses_ldq; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_uses_stq = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_uses_stq : _exe_tlb_uop_T_3_uses_stq; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_unique = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_unique : _exe_tlb_uop_T_3_is_unique; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_flush_on_commit = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_flush_on_commit : _exe_tlb_uop_T_3_flush_on_commit; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_csr_cmd = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_csr_cmd : _exe_tlb_uop_T_3_csr_cmd; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_ldst_is_rs1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_3_ldst_is_rs1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_ldst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ldst : _exe_tlb_uop_T_3_ldst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_lrs1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs1 : _exe_tlb_uop_T_3_lrs1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_lrs2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs2 : _exe_tlb_uop_T_3_lrs2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_lrs3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs3 : _exe_tlb_uop_T_3_lrs3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_dst_rtype = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_dst_rtype : _exe_tlb_uop_T_3_dst_rtype; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_lrs1_rtype = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs1_rtype : _exe_tlb_uop_T_3_lrs1_rtype; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_lrs2_rtype = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs2_rtype : _exe_tlb_uop_T_3_lrs2_rtype; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_frs3_en = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_frs3_en : _exe_tlb_uop_T_3_frs3_en; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fcn_dw = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fcn_dw : _exe_tlb_uop_T_3_fcn_dw; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_fcn_op = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fcn_op : _exe_tlb_uop_T_3_fcn_op; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_val = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_val : _exe_tlb_uop_T_3_fp_val; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_fp_rm = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_rm : _exe_tlb_uop_T_3_fp_rm; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_fp_typ = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_typ : _exe_tlb_uop_T_3_fp_typ; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_xcpt_pf_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_3_xcpt_pf_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_xcpt_ae_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_3_xcpt_ae_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_xcpt_ma_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_3_xcpt_ma_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_bp_debug_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_bp_debug_if : _exe_tlb_uop_T_3_bp_debug_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_bp_xcpt_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_3_bp_xcpt_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_debug_fsrc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_fsrc : _exe_tlb_uop_T_3_debug_fsrc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_debug_tsrc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_tsrc : _exe_tlb_uop_T_3_debug_tsrc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [31:0] _exe_tlb_uop_T_5_inst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_inst : _exe_tlb_uop_T_4_inst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [31:0] _exe_tlb_uop_T_5_debug_inst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_inst : _exe_tlb_uop_T_4_debug_inst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_rvc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_rvc : _exe_tlb_uop_T_4_is_rvc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [39:0] _exe_tlb_uop_T_5_debug_pc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_pc : _exe_tlb_uop_T_4_debug_pc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_0 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_0 : _exe_tlb_uop_T_4_iq_type_0; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_1 : _exe_tlb_uop_T_4_iq_type_1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_2 : _exe_tlb_uop_T_4_iq_type_2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_3 : _exe_tlb_uop_T_4_iq_type_3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_0 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_0 : _exe_tlb_uop_T_4_fu_code_0; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_1 : _exe_tlb_uop_T_4_fu_code_1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_2 : _exe_tlb_uop_T_4_fu_code_2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_3 : _exe_tlb_uop_T_4_fu_code_3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_4 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_4 : _exe_tlb_uop_T_4_fu_code_4; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_5 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_5 : _exe_tlb_uop_T_4_fu_code_5; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_6 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_6 : _exe_tlb_uop_T_4_fu_code_6; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_7 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_7 : _exe_tlb_uop_T_4_fu_code_7; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_8 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_8 : _exe_tlb_uop_T_4_fu_code_8; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_9 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_9 : _exe_tlb_uop_T_4_fu_code_9; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_issued = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_issued : _exe_tlb_uop_T_4_iw_issued; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_issued_partial_agen = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_issued_partial_agen : _exe_tlb_uop_T_4_iw_issued_partial_agen; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_issued_partial_dgen = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _exe_tlb_uop_T_4_iw_issued_partial_dgen; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_iw_p1_speculative_child = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p1_speculative_child : _exe_tlb_uop_T_4_iw_p1_speculative_child; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_iw_p2_speculative_child = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p2_speculative_child : _exe_tlb_uop_T_4_iw_p2_speculative_child; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_p1_bypass_hint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _exe_tlb_uop_T_4_iw_p1_bypass_hint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_p2_bypass_hint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _exe_tlb_uop_T_4_iw_p2_bypass_hint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_p3_bypass_hint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _exe_tlb_uop_T_4_iw_p3_bypass_hint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_dis_col_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_dis_col_sel : _exe_tlb_uop_T_4_dis_col_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [11:0] _exe_tlb_uop_T_5_br_mask = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_br_mask : _exe_tlb_uop_T_4_br_mask; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [3:0] _exe_tlb_uop_T_5_br_tag = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_br_tag : _exe_tlb_uop_T_4_br_tag; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [3:0] _exe_tlb_uop_T_5_br_type = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_br_type : _exe_tlb_uop_T_4_br_type; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_sfb = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_sfb : _exe_tlb_uop_T_4_is_sfb; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_fence = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_fence : _exe_tlb_uop_T_4_is_fence; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_fencei = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_fencei : _exe_tlb_uop_T_4_is_fencei; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_sfence = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_sfence : _exe_tlb_uop_T_4_is_sfence; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_amo = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_amo : _exe_tlb_uop_T_4_is_amo; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_eret = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_eret : _exe_tlb_uop_T_4_is_eret; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_sys_pc2epc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_4_is_sys_pc2epc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_rocc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_rocc : _exe_tlb_uop_T_4_is_rocc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_mov = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_mov : _exe_tlb_uop_T_4_is_mov; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_ftq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ftq_idx : _exe_tlb_uop_T_4_ftq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_edge_inst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_edge_inst : _exe_tlb_uop_T_4_edge_inst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_pc_lob = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_pc_lob : _exe_tlb_uop_T_4_pc_lob; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_taken = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_taken : _exe_tlb_uop_T_4_taken; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_imm_rename = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_imm_rename : _exe_tlb_uop_T_4_imm_rename; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_imm_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_imm_sel : _exe_tlb_uop_T_4_imm_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_pimm = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_pimm : _exe_tlb_uop_T_4_pimm; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [19:0] _exe_tlb_uop_T_5_imm_packed = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_imm_packed : _exe_tlb_uop_T_4_imm_packed; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_op1_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_op1_sel : _exe_tlb_uop_T_4_op1_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_op2_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_op2_sel : _exe_tlb_uop_T_4_op2_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ldst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ldst : _exe_tlb_uop_T_4_fp_ctrl_ldst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_wen = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_wen : _exe_tlb_uop_T_4_fp_ctrl_wen; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ren1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _exe_tlb_uop_T_4_fp_ctrl_ren1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ren2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _exe_tlb_uop_T_4_fp_ctrl_ren2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ren3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _exe_tlb_uop_T_4_fp_ctrl_ren3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_swap12 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _exe_tlb_uop_T_4_fp_ctrl_swap12; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_swap23 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _exe_tlb_uop_T_4_fp_ctrl_swap23; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_fp_ctrl_typeTagIn = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _exe_tlb_uop_T_4_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_fp_ctrl_typeTagOut = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _exe_tlb_uop_T_4_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_fromint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_fromint : _exe_tlb_uop_T_4_fp_ctrl_fromint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_toint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_toint : _exe_tlb_uop_T_4_fp_ctrl_toint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_fastpipe = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _exe_tlb_uop_T_4_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_fma = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_fma : _exe_tlb_uop_T_4_fp_ctrl_fma; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_div = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_div : _exe_tlb_uop_T_4_fp_ctrl_div; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_sqrt = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _exe_tlb_uop_T_4_fp_ctrl_sqrt; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_wflags = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_wflags : _exe_tlb_uop_T_4_fp_ctrl_wflags; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_vec = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_vec : _exe_tlb_uop_T_4_fp_ctrl_vec; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_rob_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_rob_idx : _exe_tlb_uop_T_4_rob_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [3:0] _exe_tlb_uop_T_5_ldq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ldq_idx : _exe_tlb_uop_T_4_ldq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [3:0] _exe_tlb_uop_T_5_stq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_stq_idx : _exe_tlb_uop_T_4_stq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_rxq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_rxq_idx : _exe_tlb_uop_T_4_rxq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_pdst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_pdst : _exe_tlb_uop_T_4_pdst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_prs1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs1 : _exe_tlb_uop_T_4_prs1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_prs2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs2 : _exe_tlb_uop_T_4_prs2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_prs3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs3 : _exe_tlb_uop_T_4_prs3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_ppred = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ppred : _exe_tlb_uop_T_4_ppred; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_prs1_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs1_busy : _exe_tlb_uop_T_4_prs1_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_prs2_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs2_busy : _exe_tlb_uop_T_4_prs2_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_prs3_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs3_busy : _exe_tlb_uop_T_4_prs3_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_ppred_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ppred_busy : _exe_tlb_uop_T_4_ppred_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_stale_pdst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_stale_pdst : _exe_tlb_uop_T_4_stale_pdst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_exception = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_exception : _exe_tlb_uop_T_4_exception; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [63:0] _exe_tlb_uop_T_5_exc_cause = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_exc_cause : _exe_tlb_uop_T_4_exc_cause; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_mem_cmd = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_mem_cmd : _exe_tlb_uop_T_4_mem_cmd; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_mem_size = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_mem_size : _exe_tlb_uop_T_4_mem_size; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_mem_signed = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_mem_signed : _exe_tlb_uop_T_4_mem_signed; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_uses_ldq = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_uses_ldq : _exe_tlb_uop_T_4_uses_ldq; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_uses_stq = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_uses_stq : _exe_tlb_uop_T_4_uses_stq; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_unique = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_unique : _exe_tlb_uop_T_4_is_unique; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_flush_on_commit = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_flush_on_commit : _exe_tlb_uop_T_4_flush_on_commit; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_csr_cmd = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_csr_cmd : _exe_tlb_uop_T_4_csr_cmd; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_ldst_is_rs1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_4_ldst_is_rs1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_ldst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ldst : _exe_tlb_uop_T_4_ldst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_lrs1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs1 : _exe_tlb_uop_T_4_lrs1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_lrs2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs2 : _exe_tlb_uop_T_4_lrs2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_lrs3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs3 : _exe_tlb_uop_T_4_lrs3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_dst_rtype = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_dst_rtype : _exe_tlb_uop_T_4_dst_rtype; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_lrs1_rtype = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs1_rtype : _exe_tlb_uop_T_4_lrs1_rtype; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_lrs2_rtype = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs2_rtype : _exe_tlb_uop_T_4_lrs2_rtype; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_frs3_en = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_frs3_en : _exe_tlb_uop_T_4_frs3_en; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fcn_dw = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fcn_dw : _exe_tlb_uop_T_4_fcn_dw; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_fcn_op = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fcn_op : _exe_tlb_uop_T_4_fcn_op; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_val = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_val : _exe_tlb_uop_T_4_fp_val; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_fp_rm = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_rm : _exe_tlb_uop_T_4_fp_rm; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_fp_typ = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_typ : _exe_tlb_uop_T_4_fp_typ; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_xcpt_pf_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_4_xcpt_pf_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_xcpt_ae_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_4_xcpt_ae_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_xcpt_ma_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_4_xcpt_ma_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_bp_debug_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_bp_debug_if : _exe_tlb_uop_T_4_bp_debug_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_bp_xcpt_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_4_bp_xcpt_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_debug_fsrc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_fsrc : _exe_tlb_uop_T_4_debug_fsrc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_debug_tsrc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_tsrc : _exe_tlb_uop_T_4_debug_tsrc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [31:0] exe_tlb_uop_0_inst = _exe_tlb_uop_T_5_inst; // @[lsu.scala:321:49, :717:24] wire [31:0] exe_tlb_uop_0_debug_inst = _exe_tlb_uop_T_5_debug_inst; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_rvc = _exe_tlb_uop_T_5_is_rvc; // @[lsu.scala:321:49, :717:24] wire [39:0] exe_tlb_uop_0_debug_pc = _exe_tlb_uop_T_5_debug_pc; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_0 = _exe_tlb_uop_T_5_iq_type_0; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_1 = _exe_tlb_uop_T_5_iq_type_1; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_2 = _exe_tlb_uop_T_5_iq_type_2; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_3 = _exe_tlb_uop_T_5_iq_type_3; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_0 = _exe_tlb_uop_T_5_fu_code_0; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_1 = _exe_tlb_uop_T_5_fu_code_1; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_2 = _exe_tlb_uop_T_5_fu_code_2; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_3 = _exe_tlb_uop_T_5_fu_code_3; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_4 = _exe_tlb_uop_T_5_fu_code_4; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_5 = _exe_tlb_uop_T_5_fu_code_5; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_6 = _exe_tlb_uop_T_5_fu_code_6; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_7 = _exe_tlb_uop_T_5_fu_code_7; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_8 = _exe_tlb_uop_T_5_fu_code_8; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_9 = _exe_tlb_uop_T_5_fu_code_9; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_issued = _exe_tlb_uop_T_5_iw_issued; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_issued_partial_agen = _exe_tlb_uop_T_5_iw_issued_partial_agen; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_issued_partial_dgen = _exe_tlb_uop_T_5_iw_issued_partial_dgen; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_iw_p1_speculative_child = _exe_tlb_uop_T_5_iw_p1_speculative_child; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_iw_p2_speculative_child = _exe_tlb_uop_T_5_iw_p2_speculative_child; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_p1_bypass_hint = _exe_tlb_uop_T_5_iw_p1_bypass_hint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_p2_bypass_hint = _exe_tlb_uop_T_5_iw_p2_bypass_hint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_p3_bypass_hint = _exe_tlb_uop_T_5_iw_p3_bypass_hint; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_dis_col_sel = _exe_tlb_uop_T_5_dis_col_sel; // @[lsu.scala:321:49, :717:24] wire [11:0] exe_tlb_uop_0_br_mask = _exe_tlb_uop_T_5_br_mask; // @[lsu.scala:321:49, :717:24] wire [3:0] exe_tlb_uop_0_br_tag = _exe_tlb_uop_T_5_br_tag; // @[lsu.scala:321:49, :717:24] wire [3:0] exe_tlb_uop_0_br_type = _exe_tlb_uop_T_5_br_type; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_sfb = _exe_tlb_uop_T_5_is_sfb; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_fence = _exe_tlb_uop_T_5_is_fence; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_fencei = _exe_tlb_uop_T_5_is_fencei; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_sfence = _exe_tlb_uop_T_5_is_sfence; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_amo = _exe_tlb_uop_T_5_is_amo; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_eret = _exe_tlb_uop_T_5_is_eret; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_sys_pc2epc = _exe_tlb_uop_T_5_is_sys_pc2epc; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_rocc = _exe_tlb_uop_T_5_is_rocc; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_mov = _exe_tlb_uop_T_5_is_mov; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_ftq_idx = _exe_tlb_uop_T_5_ftq_idx; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_edge_inst = _exe_tlb_uop_T_5_edge_inst; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_pc_lob = _exe_tlb_uop_T_5_pc_lob; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_taken = _exe_tlb_uop_T_5_taken; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_imm_rename = _exe_tlb_uop_T_5_imm_rename; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_imm_sel = _exe_tlb_uop_T_5_imm_sel; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_pimm = _exe_tlb_uop_T_5_pimm; // @[lsu.scala:321:49, :717:24] wire [19:0] exe_tlb_uop_0_imm_packed = _exe_tlb_uop_T_5_imm_packed; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_op1_sel = _exe_tlb_uop_T_5_op1_sel; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_op2_sel = _exe_tlb_uop_T_5_op2_sel; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ldst = _exe_tlb_uop_T_5_fp_ctrl_ldst; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_wen = _exe_tlb_uop_T_5_fp_ctrl_wen; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ren1 = _exe_tlb_uop_T_5_fp_ctrl_ren1; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ren2 = _exe_tlb_uop_T_5_fp_ctrl_ren2; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ren3 = _exe_tlb_uop_T_5_fp_ctrl_ren3; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_swap12 = _exe_tlb_uop_T_5_fp_ctrl_swap12; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_swap23 = _exe_tlb_uop_T_5_fp_ctrl_swap23; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_fp_ctrl_typeTagIn = _exe_tlb_uop_T_5_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_fp_ctrl_typeTagOut = _exe_tlb_uop_T_5_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_fromint = _exe_tlb_uop_T_5_fp_ctrl_fromint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_toint = _exe_tlb_uop_T_5_fp_ctrl_toint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_fastpipe = _exe_tlb_uop_T_5_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_fma = _exe_tlb_uop_T_5_fp_ctrl_fma; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_div = _exe_tlb_uop_T_5_fp_ctrl_div; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_sqrt = _exe_tlb_uop_T_5_fp_ctrl_sqrt; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_wflags = _exe_tlb_uop_T_5_fp_ctrl_wflags; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_vec = _exe_tlb_uop_T_5_fp_ctrl_vec; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_rob_idx = _exe_tlb_uop_T_5_rob_idx; // @[lsu.scala:321:49, :717:24] wire [3:0] exe_tlb_uop_0_ldq_idx = _exe_tlb_uop_T_5_ldq_idx; // @[lsu.scala:321:49, :717:24] wire [3:0] exe_tlb_uop_0_stq_idx = _exe_tlb_uop_T_5_stq_idx; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_rxq_idx = _exe_tlb_uop_T_5_rxq_idx; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_pdst = _exe_tlb_uop_T_5_pdst; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_prs1 = _exe_tlb_uop_T_5_prs1; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_prs2 = _exe_tlb_uop_T_5_prs2; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_prs3 = _exe_tlb_uop_T_5_prs3; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_ppred = _exe_tlb_uop_T_5_ppred; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_prs1_busy = _exe_tlb_uop_T_5_prs1_busy; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_prs2_busy = _exe_tlb_uop_T_5_prs2_busy; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_prs3_busy = _exe_tlb_uop_T_5_prs3_busy; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_ppred_busy = _exe_tlb_uop_T_5_ppred_busy; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_stale_pdst = _exe_tlb_uop_T_5_stale_pdst; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_exception = _exe_tlb_uop_T_5_exception; // @[lsu.scala:321:49, :717:24] wire [63:0] exe_tlb_uop_0_exc_cause = _exe_tlb_uop_T_5_exc_cause; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_mem_cmd = _exe_tlb_uop_T_5_mem_cmd; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_mem_size = _exe_tlb_uop_T_5_mem_size; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_mem_signed = _exe_tlb_uop_T_5_mem_signed; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_uses_ldq = _exe_tlb_uop_T_5_uses_ldq; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_uses_stq = _exe_tlb_uop_T_5_uses_stq; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_unique = _exe_tlb_uop_T_5_is_unique; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_flush_on_commit = _exe_tlb_uop_T_5_flush_on_commit; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_csr_cmd = _exe_tlb_uop_T_5_csr_cmd; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_ldst_is_rs1 = _exe_tlb_uop_T_5_ldst_is_rs1; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_ldst = _exe_tlb_uop_T_5_ldst; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_lrs1 = _exe_tlb_uop_T_5_lrs1; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_lrs2 = _exe_tlb_uop_T_5_lrs2; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_lrs3 = _exe_tlb_uop_T_5_lrs3; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_dst_rtype = _exe_tlb_uop_T_5_dst_rtype; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_lrs1_rtype = _exe_tlb_uop_T_5_lrs1_rtype; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_lrs2_rtype = _exe_tlb_uop_T_5_lrs2_rtype; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_frs3_en = _exe_tlb_uop_T_5_frs3_en; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fcn_dw = _exe_tlb_uop_T_5_fcn_dw; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_fcn_op = _exe_tlb_uop_T_5_fcn_op; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_val = _exe_tlb_uop_T_5_fp_val; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_fp_rm = _exe_tlb_uop_T_5_fp_rm; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_fp_typ = _exe_tlb_uop_T_5_fp_typ; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_xcpt_pf_if = _exe_tlb_uop_T_5_xcpt_pf_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_xcpt_ae_if = _exe_tlb_uop_T_5_xcpt_ae_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_xcpt_ma_if = _exe_tlb_uop_T_5_xcpt_ma_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_bp_debug_if = _exe_tlb_uop_T_5_bp_debug_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_bp_xcpt_if = _exe_tlb_uop_T_5_bp_xcpt_if; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_debug_fsrc = _exe_tlb_uop_T_5_debug_fsrc; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_debug_tsrc = _exe_tlb_uop_T_5_debug_tsrc; // @[lsu.scala:321:49, :717:24] wire [31:0] mem_xcpt_uops_out_inst = exe_tlb_uop_0_inst; // @[util.scala:104:23] wire [31:0] mem_xcpt_uops_out_debug_inst = exe_tlb_uop_0_debug_inst; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_rvc = exe_tlb_uop_0_is_rvc; // @[util.scala:104:23] wire [39:0] mem_xcpt_uops_out_debug_pc = exe_tlb_uop_0_debug_pc; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_0 = exe_tlb_uop_0_iq_type_0; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_1 = exe_tlb_uop_0_iq_type_1; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_2 = exe_tlb_uop_0_iq_type_2; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_3 = exe_tlb_uop_0_iq_type_3; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_0 = exe_tlb_uop_0_fu_code_0; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_1 = exe_tlb_uop_0_fu_code_1; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_2 = exe_tlb_uop_0_fu_code_2; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_3 = exe_tlb_uop_0_fu_code_3; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_4 = exe_tlb_uop_0_fu_code_4; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_5 = exe_tlb_uop_0_fu_code_5; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_6 = exe_tlb_uop_0_fu_code_6; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_7 = exe_tlb_uop_0_fu_code_7; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_8 = exe_tlb_uop_0_fu_code_8; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_9 = exe_tlb_uop_0_fu_code_9; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_issued = exe_tlb_uop_0_iw_issued; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_issued_partial_agen = exe_tlb_uop_0_iw_issued_partial_agen; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_issued_partial_dgen = exe_tlb_uop_0_iw_issued_partial_dgen; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_iw_p1_speculative_child = exe_tlb_uop_0_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_iw_p2_speculative_child = exe_tlb_uop_0_iw_p2_speculative_child; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_p1_bypass_hint = exe_tlb_uop_0_iw_p1_bypass_hint; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_p2_bypass_hint = exe_tlb_uop_0_iw_p2_bypass_hint; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_p3_bypass_hint = exe_tlb_uop_0_iw_p3_bypass_hint; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_dis_col_sel = exe_tlb_uop_0_dis_col_sel; // @[util.scala:104:23] wire [3:0] mem_xcpt_uops_out_br_tag = exe_tlb_uop_0_br_tag; // @[util.scala:104:23] wire [3:0] mem_xcpt_uops_out_br_type = exe_tlb_uop_0_br_type; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_sfb = exe_tlb_uop_0_is_sfb; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_fence = exe_tlb_uop_0_is_fence; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_fencei = exe_tlb_uop_0_is_fencei; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_sfence = exe_tlb_uop_0_is_sfence; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_amo = exe_tlb_uop_0_is_amo; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_eret = exe_tlb_uop_0_is_eret; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_sys_pc2epc = exe_tlb_uop_0_is_sys_pc2epc; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_rocc = exe_tlb_uop_0_is_rocc; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_mov = exe_tlb_uop_0_is_mov; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_ftq_idx = exe_tlb_uop_0_ftq_idx; // @[util.scala:104:23] wire mem_xcpt_uops_out_edge_inst = exe_tlb_uop_0_edge_inst; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_pc_lob = exe_tlb_uop_0_pc_lob; // @[util.scala:104:23] wire mem_xcpt_uops_out_taken = exe_tlb_uop_0_taken; // @[util.scala:104:23] wire mem_xcpt_uops_out_imm_rename = exe_tlb_uop_0_imm_rename; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_imm_sel = exe_tlb_uop_0_imm_sel; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_pimm = exe_tlb_uop_0_pimm; // @[util.scala:104:23] wire [19:0] mem_xcpt_uops_out_imm_packed = exe_tlb_uop_0_imm_packed; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_op1_sel = exe_tlb_uop_0_op1_sel; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_op2_sel = exe_tlb_uop_0_op2_sel; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ldst = exe_tlb_uop_0_fp_ctrl_ldst; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_wen = exe_tlb_uop_0_fp_ctrl_wen; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ren1 = exe_tlb_uop_0_fp_ctrl_ren1; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ren2 = exe_tlb_uop_0_fp_ctrl_ren2; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ren3 = exe_tlb_uop_0_fp_ctrl_ren3; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_swap12 = exe_tlb_uop_0_fp_ctrl_swap12; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_swap23 = exe_tlb_uop_0_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_fp_ctrl_typeTagIn = exe_tlb_uop_0_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_fp_ctrl_typeTagOut = exe_tlb_uop_0_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_fromint = exe_tlb_uop_0_fp_ctrl_fromint; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_toint = exe_tlb_uop_0_fp_ctrl_toint; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_fastpipe = exe_tlb_uop_0_fp_ctrl_fastpipe; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_fma = exe_tlb_uop_0_fp_ctrl_fma; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_div = exe_tlb_uop_0_fp_ctrl_div; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_sqrt = exe_tlb_uop_0_fp_ctrl_sqrt; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_wflags = exe_tlb_uop_0_fp_ctrl_wflags; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_vec = exe_tlb_uop_0_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_rob_idx = exe_tlb_uop_0_rob_idx; // @[util.scala:104:23] wire [3:0] mem_xcpt_uops_out_ldq_idx = exe_tlb_uop_0_ldq_idx; // @[util.scala:104:23] wire [3:0] mem_xcpt_uops_out_stq_idx = exe_tlb_uop_0_stq_idx; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_rxq_idx = exe_tlb_uop_0_rxq_idx; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_pdst = exe_tlb_uop_0_pdst; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_prs1 = exe_tlb_uop_0_prs1; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_prs2 = exe_tlb_uop_0_prs2; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_prs3 = exe_tlb_uop_0_prs3; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_ppred = exe_tlb_uop_0_ppred; // @[util.scala:104:23] wire mem_xcpt_uops_out_prs1_busy = exe_tlb_uop_0_prs1_busy; // @[util.scala:104:23] wire mem_xcpt_uops_out_prs2_busy = exe_tlb_uop_0_prs2_busy; // @[util.scala:104:23] wire mem_xcpt_uops_out_prs3_busy = exe_tlb_uop_0_prs3_busy; // @[util.scala:104:23] wire mem_xcpt_uops_out_ppred_busy = exe_tlb_uop_0_ppred_busy; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_stale_pdst = exe_tlb_uop_0_stale_pdst; // @[util.scala:104:23] wire mem_xcpt_uops_out_exception = exe_tlb_uop_0_exception; // @[util.scala:104:23] wire [63:0] mem_xcpt_uops_out_exc_cause = exe_tlb_uop_0_exc_cause; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_mem_cmd = exe_tlb_uop_0_mem_cmd; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_mem_size = exe_tlb_uop_0_mem_size; // @[util.scala:104:23] wire mem_xcpt_uops_out_mem_signed = exe_tlb_uop_0_mem_signed; // @[util.scala:104:23] wire mem_xcpt_uops_out_uses_ldq = exe_tlb_uop_0_uses_ldq; // @[util.scala:104:23] wire mem_xcpt_uops_out_uses_stq = exe_tlb_uop_0_uses_stq; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_unique = exe_tlb_uop_0_is_unique; // @[util.scala:104:23] wire mem_xcpt_uops_out_flush_on_commit = exe_tlb_uop_0_flush_on_commit; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_csr_cmd = exe_tlb_uop_0_csr_cmd; // @[util.scala:104:23] wire mem_xcpt_uops_out_ldst_is_rs1 = exe_tlb_uop_0_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_ldst = exe_tlb_uop_0_ldst; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_lrs1 = exe_tlb_uop_0_lrs1; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_lrs2 = exe_tlb_uop_0_lrs2; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_lrs3 = exe_tlb_uop_0_lrs3; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_dst_rtype = exe_tlb_uop_0_dst_rtype; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_lrs1_rtype = exe_tlb_uop_0_lrs1_rtype; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_lrs2_rtype = exe_tlb_uop_0_lrs2_rtype; // @[util.scala:104:23] wire mem_xcpt_uops_out_frs3_en = exe_tlb_uop_0_frs3_en; // @[util.scala:104:23] wire mem_xcpt_uops_out_fcn_dw = exe_tlb_uop_0_fcn_dw; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_fcn_op = exe_tlb_uop_0_fcn_op; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_val = exe_tlb_uop_0_fp_val; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_fp_rm = exe_tlb_uop_0_fp_rm; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_fp_typ = exe_tlb_uop_0_fp_typ; // @[util.scala:104:23] wire mem_xcpt_uops_out_xcpt_pf_if = exe_tlb_uop_0_xcpt_pf_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_xcpt_ae_if = exe_tlb_uop_0_xcpt_ae_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_xcpt_ma_if = exe_tlb_uop_0_xcpt_ma_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_bp_debug_if = exe_tlb_uop_0_bp_debug_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_bp_xcpt_if = exe_tlb_uop_0_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_debug_fsrc = exe_tlb_uop_0_debug_fsrc; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_debug_tsrc = exe_tlb_uop_0_debug_tsrc; // @[util.scala:104:23] wire _exe_tlb_vaddr_T_1 = _exe_tlb_vaddr_T \| will_fire_store_agen_0; // @[lsu.scala:471:41, :726:53, :727:53] wire [39:0] _exe_tlb_vaddr_T_3 = will_fire_hella_incoming_0 ? hella_req_addr : 40'h0; // @[lsu.scala:302:34, :473:41, :732:24] wire [63:0] _exe_tlb_vaddr_T_4 = _exe_tlb_vaddr_T_2 ? _retry_queue_io_deq_bits_data : {24'h0, _exe_tlb_vaddr_T_3}; // @[lsu.scala:533:27, :539:32, :730:{24,53}, :732:24] wire [63:0] _exe_tlb_vaddr_T_5 = will_fire_sfence_0 ? {25'h0, io_core_sfence_bits_addr_0} : _exe_tlb_vaddr_T_4; // @[lsu.scala:211:7, :472:41, :729:24, :730:24] wire [63:0] _exe_tlb_vaddr_T_6 = _exe_tlb_vaddr_T_1 ? io_core_agen_0_bits_data_0 : _exe_tlb_vaddr_T_5; // @[lsu.scala:211:7, :726:24, :727:53, :729:24] wire [63:0] exe_tlb_vaddr_0 = _exe_tlb_vaddr_T_6; // @[lsu.scala:321:49, :726:24] wire _exe_size_T_1 = _exe_size_T \| will_fire_store_agen_0; // @[lsu.scala:471:41, :738:52, :739:52] wire _exe_size_T_2 = _exe_size_T_1 \| will_fire_load_retry_0; // @[lsu.scala:476:41, :739:52, :740:52] wire _exe_size_T_3 = _exe_size_T_2 \| will_fire_store_retry_0; // @[lsu.scala:477:41, :740:52, :741:52] wire [1:0] _exe_size_T_4 = {2{will_fire_hella_incoming_0}}; // @[lsu.scala:473:41, :743:23] wire [1:0] _exe_size_T_5 = _exe_size_T_3 ? exe_tlb_uop_0_mem_size : _exe_size_T_4; // @[lsu.scala:321:49, :738:23, :741:52, :743:23] wire [1:0] exe_size_0 = _exe_size_T_5; // @[lsu.scala:321:49, :738:23] wire _exe_cmd_T_1 = _exe_cmd_T \| will_fire_store_agen_0; // @[lsu.scala:471:41, :746:52, :747:52] wire _exe_cmd_T_2 = _exe_cmd_T_1 \| will_fire_load_retry_0; // @[lsu.scala:476:41, :747:52, :748:52] wire _exe_cmd_T_3 = _exe_cmd_T_2 \| will_fire_store_retry_0; // @[lsu.scala:477:41, :748:52, :749:52] wire [4:0] _exe_cmd_T_4 = will_fire_sfence_0 ? 5'h14 : 5'h0; // @[lsu.scala:472:41, :752:23] wire [4:0] _exe_cmd_T_5 = will_fire_hella_incoming_0 ? 5'h0 : _exe_cmd_T_4; // @[lsu.scala:473:41, :751:23, :752:23] wire [4:0] _exe_cmd_T_6 = _exe_cmd_T_3 ? exe_tlb_uop_0_mem_cmd : _exe_cmd_T_5; // @[lsu.scala:321:49, :746:23, :749:52, :751:23] wire [4:0] exe_cmd_0 = _exe_cmd_T_6; // @[lsu.scala:321:49, :746:23] wire exe_passthr_0 = _exe_passthr_T; // @[lsu.scala:321:49, :756:23] wire _exe_kill_T = will_fire_hella_incoming_0 & io_hellacache_s1_kill_0; // @[lsu.scala:211:7, :473:41, :759:23] wire exe_kill_0 = _exe_kill_T; // @[lsu.scala:321:49, :759:23] wire _ma_ld_T = _dtlb_io_resp_0_ma_ld & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:308:20, :321:49, :782:52] wire ma_ld_0 = _ma_ld_T; // @[lsu.scala:321:49, :782:52] wire _ma_st_T = _dtlb_io_resp_0_ma_st & exe_tlb_uop_0_uses_stq; // @[lsu.scala:308:20, :321:49, :783:52] wire _ma_st_T_1 = ~exe_tlb_uop_0_is_fence; // @[lsu.scala:321:49, :783:82] wire _ma_st_T_2 = _ma_st_T & _ma_st_T_1; // @[lsu.scala:783:{52,79,82}] wire ma_st_0 = _ma_st_T_2; // @[lsu.scala:321:49, :783:79] wire _pf_ld_T = _dtlb_io_resp_0_pf_ld & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:308:20, :321:49, :784:52] wire pf_ld_0 = _pf_ld_T; // @[lsu.scala:321:49, :784:52] wire _pf_st_T = _dtlb_io_resp_0_pf_st & exe_tlb_uop_0_uses_stq; // @[lsu.scala:308:20, :321:49, :785:52] wire pf_st_0 = _pf_st_T; // @[lsu.scala:321:49, :785:52] wire _ae_ld_T = _dtlb_io_resp_0_ae_ld & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:308:20, :321:49, :786:52] wire ae_ld_0 = _ae_ld_T; // @[lsu.scala:321:49, :786:52] wire _ae_st_T = _dtlb_io_resp_0_ae_st & exe_tlb_uop_0_uses_stq; // @[lsu.scala:308:20, :321:49, :787:52] wire ae_st_0 = _ae_st_T; // @[lsu.scala:321:49, :787:52] wire _dbg_bp_T_2 = ~exe_tlb_uop_0_is_fence; // @[lsu.scala:321:49, :783:82, :789:107] wire _bp_T_2 = ~exe_tlb_uop_0_is_fence; // @[lsu.scala:321:49, :783:82, :791:106] wire _mem_xcpt_valids_T = pf_ld_0 \| pf_st_0; // @[lsu.scala:321:49, :797:32] wire _mem_xcpt_valids_T_1 = _mem_xcpt_valids_T \| ae_ld_0; // @[lsu.scala:321:49, :797:{32,44}] wire _mem_xcpt_valids_T_2 = _mem_xcpt_valids_T_1 \| ae_st_0; // @[lsu.scala:321:49, :797:{44,56}] wire _mem_xcpt_valids_T_3 = _mem_xcpt_valids_T_2 \| ma_ld_0; // @[lsu.scala:321:49, :797:{56,68}] wire _mem_xcpt_valids_T_4 = _mem_xcpt_valids_T_3 \| ma_st_0; // @[lsu.scala:321:49, :797:{68,80}] wire _mem_xcpt_valids_T_5 = _mem_xcpt_valids_T_4; // @[lsu.scala:797:{80,92}] wire _mem_xcpt_valids_T_6 = _mem_xcpt_valids_T_5; // @[lsu.scala:797:{92,105}] wire _mem_xcpt_valids_T_7 = exe_tlb_valid_0 & _mem_xcpt_valids_T_6; // @[lsu.scala:649:27, :796:39, :797:105] wire [11:0] _mem_xcpt_valids_T_8 = io_core_brupdate_b1_mispredict_mask_0 & exe_tlb_uop_0_br_mask; // @[util.scala:126:51] wire _mem_xcpt_valids_T_9 = \|_mem_xcpt_valids_T_8; // @[util.scala:126:{51,59}] wire _mem_xcpt_valids_T_10 = _mem_xcpt_valids_T_9 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_xcpt_valids_T_11 = ~_mem_xcpt_valids_T_10; // @[util.scala:61:61] wire _mem_xcpt_valids_T_12 = _mem_xcpt_valids_T_7 & _mem_xcpt_valids_T_11; // @[lsu.scala:796:39, :797:115, :798:22] wire _mem_xcpt_valids_WIRE_0 = _mem_xcpt_valids_T_12; // @[lsu.scala:321:49, :797:115] reg mem_xcpt_valids_0; // @[lsu.scala:795:32] assign mem_xcpt_valid = mem_xcpt_valids_0; // @[lsu.scala:457:29, :795:32] wire [31:0] _mem_xcpt_uops_WIRE_0_inst = mem_xcpt_uops_out_inst; // @[util.scala:104:23] wire [31:0] _mem_xcpt_uops_WIRE_0_debug_inst = mem_xcpt_uops_out_debug_inst; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_rvc = mem_xcpt_uops_out_is_rvc; // @[util.scala:104:23] wire [39:0] _mem_xcpt_uops_WIRE_0_debug_pc = mem_xcpt_uops_out_debug_pc; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_0 = mem_xcpt_uops_out_iq_type_0; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_1 = mem_xcpt_uops_out_iq_type_1; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_2 = mem_xcpt_uops_out_iq_type_2; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_3 = mem_xcpt_uops_out_iq_type_3; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_0 = mem_xcpt_uops_out_fu_code_0; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_1 = mem_xcpt_uops_out_fu_code_1; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_2 = mem_xcpt_uops_out_fu_code_2; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_3 = mem_xcpt_uops_out_fu_code_3; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_4 = mem_xcpt_uops_out_fu_code_4; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_5 = mem_xcpt_uops_out_fu_code_5; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_6 = mem_xcpt_uops_out_fu_code_6; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_7 = mem_xcpt_uops_out_fu_code_7; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_8 = mem_xcpt_uops_out_fu_code_8; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_9 = mem_xcpt_uops_out_fu_code_9; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_issued = mem_xcpt_uops_out_iw_issued; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_issued_partial_agen = mem_xcpt_uops_out_iw_issued_partial_agen; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_issued_partial_dgen = mem_xcpt_uops_out_iw_issued_partial_dgen; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_iw_p1_speculative_child = mem_xcpt_uops_out_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_iw_p2_speculative_child = mem_xcpt_uops_out_iw_p2_speculative_child; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_p1_bypass_hint = mem_xcpt_uops_out_iw_p1_bypass_hint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_p2_bypass_hint = mem_xcpt_uops_out_iw_p2_bypass_hint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_p3_bypass_hint = mem_xcpt_uops_out_iw_p3_bypass_hint; // @[util.scala:104:23] wire [11:0] _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:93:25] wire [1:0] _mem_xcpt_uops_WIRE_0_dis_col_sel = mem_xcpt_uops_out_dis_col_sel; // @[util.scala:104:23] wire [11:0] _mem_xcpt_uops_WIRE_0_br_mask = mem_xcpt_uops_out_br_mask; // @[util.scala:104:23] wire [3:0] _mem_xcpt_uops_WIRE_0_br_tag = mem_xcpt_uops_out_br_tag; // @[util.scala:104:23] wire [3:0] _mem_xcpt_uops_WIRE_0_br_type = mem_xcpt_uops_out_br_type; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_sfb = mem_xcpt_uops_out_is_sfb; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_fence = mem_xcpt_uops_out_is_fence; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_fencei = mem_xcpt_uops_out_is_fencei; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_sfence = mem_xcpt_uops_out_is_sfence; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_amo = mem_xcpt_uops_out_is_amo; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_eret = mem_xcpt_uops_out_is_eret; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_sys_pc2epc = mem_xcpt_uops_out_is_sys_pc2epc; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_rocc = mem_xcpt_uops_out_is_rocc; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_mov = mem_xcpt_uops_out_is_mov; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ftq_idx = mem_xcpt_uops_out_ftq_idx; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_edge_inst = mem_xcpt_uops_out_edge_inst; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_pc_lob = mem_xcpt_uops_out_pc_lob; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_taken = mem_xcpt_uops_out_taken; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_imm_rename = mem_xcpt_uops_out_imm_rename; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_imm_sel = mem_xcpt_uops_out_imm_sel; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_pimm = mem_xcpt_uops_out_pimm; // @[util.scala:104:23] wire [19:0] _mem_xcpt_uops_WIRE_0_imm_packed = mem_xcpt_uops_out_imm_packed; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_op1_sel = mem_xcpt_uops_out_op1_sel; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_op2_sel = mem_xcpt_uops_out_op2_sel; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ldst = mem_xcpt_uops_out_fp_ctrl_ldst; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_wen = mem_xcpt_uops_out_fp_ctrl_wen; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ren1 = mem_xcpt_uops_out_fp_ctrl_ren1; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ren2 = mem_xcpt_uops_out_fp_ctrl_ren2; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ren3 = mem_xcpt_uops_out_fp_ctrl_ren3; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_swap12 = mem_xcpt_uops_out_fp_ctrl_swap12; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_swap23 = mem_xcpt_uops_out_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_fp_ctrl_typeTagIn = mem_xcpt_uops_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_fp_ctrl_typeTagOut = mem_xcpt_uops_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_fromint = mem_xcpt_uops_out_fp_ctrl_fromint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_toint = mem_xcpt_uops_out_fp_ctrl_toint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_fastpipe = mem_xcpt_uops_out_fp_ctrl_fastpipe; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_fma = mem_xcpt_uops_out_fp_ctrl_fma; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_div = mem_xcpt_uops_out_fp_ctrl_div; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_sqrt = mem_xcpt_uops_out_fp_ctrl_sqrt; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_wflags = mem_xcpt_uops_out_fp_ctrl_wflags; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_vec = mem_xcpt_uops_out_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_rob_idx = mem_xcpt_uops_out_rob_idx; // @[util.scala:104:23] wire [3:0] _mem_xcpt_uops_WIRE_0_ldq_idx = mem_xcpt_uops_out_ldq_idx; // @[util.scala:104:23] wire [3:0] _mem_xcpt_uops_WIRE_0_stq_idx = mem_xcpt_uops_out_stq_idx; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_rxq_idx = mem_xcpt_uops_out_rxq_idx; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_pdst = mem_xcpt_uops_out_pdst; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs1 = mem_xcpt_uops_out_prs1; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs2 = mem_xcpt_uops_out_prs2; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs3 = mem_xcpt_uops_out_prs3; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ppred = mem_xcpt_uops_out_ppred; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_prs1_busy = mem_xcpt_uops_out_prs1_busy; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_prs2_busy = mem_xcpt_uops_out_prs2_busy; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_prs3_busy = mem_xcpt_uops_out_prs3_busy; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_ppred_busy = mem_xcpt_uops_out_ppred_busy; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_stale_pdst = mem_xcpt_uops_out_stale_pdst; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_exception = mem_xcpt_uops_out_exception; // @[util.scala:104:23] wire [63:0] _mem_xcpt_uops_WIRE_0_exc_cause = mem_xcpt_uops_out_exc_cause; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_mem_cmd = mem_xcpt_uops_out_mem_cmd; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_mem_size = mem_xcpt_uops_out_mem_size; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_mem_signed = mem_xcpt_uops_out_mem_signed; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_uses_ldq = mem_xcpt_uops_out_uses_ldq; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_uses_stq = mem_xcpt_uops_out_uses_stq; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_unique = mem_xcpt_uops_out_is_unique; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_flush_on_commit = mem_xcpt_uops_out_flush_on_commit; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_csr_cmd = mem_xcpt_uops_out_csr_cmd; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_ldst_is_rs1 = mem_xcpt_uops_out_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_ldst = mem_xcpt_uops_out_ldst; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs1 = mem_xcpt_uops_out_lrs1; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs2 = mem_xcpt_uops_out_lrs2; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs3 = mem_xcpt_uops_out_lrs3; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_dst_rtype = mem_xcpt_uops_out_dst_rtype; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs1_rtype = mem_xcpt_uops_out_lrs1_rtype; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs2_rtype = mem_xcpt_uops_out_lrs2_rtype; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_frs3_en = mem_xcpt_uops_out_frs3_en; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fcn_dw = mem_xcpt_uops_out_fcn_dw; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_fcn_op = mem_xcpt_uops_out_fcn_op; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_val = mem_xcpt_uops_out_fp_val; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_fp_rm = mem_xcpt_uops_out_fp_rm; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_fp_typ = mem_xcpt_uops_out_fp_typ; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_xcpt_pf_if = mem_xcpt_uops_out_xcpt_pf_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ae_if = mem_xcpt_uops_out_xcpt_ae_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ma_if = mem_xcpt_uops_out_xcpt_ma_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_bp_debug_if = mem_xcpt_uops_out_bp_debug_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_bp_xcpt_if = mem_xcpt_uops_out_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_debug_fsrc = mem_xcpt_uops_out_debug_fsrc; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_debug_tsrc = mem_xcpt_uops_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _mem_xcpt_uops_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _mem_xcpt_uops_out_br_mask_T_1 = exe_tlb_uop_0_br_mask & _mem_xcpt_uops_out_br_mask_T; // @[util.scala:93:{25,27}] assign mem_xcpt_uops_out_br_mask = _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg [31:0] mem_xcpt_uops_0_inst; // @[lsu.scala:799:32] assign mem_xcpt_uop_inst = mem_xcpt_uops_0_inst; // @[lsu.scala:459:29, :799:32] reg [31:0] mem_xcpt_uops_0_debug_inst; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_inst = mem_xcpt_uops_0_debug_inst; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_rvc; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_rvc = mem_xcpt_uops_0_is_rvc; // @[lsu.scala:459:29, :799:32] reg [39:0] mem_xcpt_uops_0_debug_pc; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_pc = mem_xcpt_uops_0_debug_pc; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_0; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_0 = mem_xcpt_uops_0_iq_type_0; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_1; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_1 = mem_xcpt_uops_0_iq_type_1; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_2; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_2 = mem_xcpt_uops_0_iq_type_2; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_3; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_3 = mem_xcpt_uops_0_iq_type_3; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_0; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_0 = mem_xcpt_uops_0_fu_code_0; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_1; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_1 = mem_xcpt_uops_0_fu_code_1; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_2; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_2 = mem_xcpt_uops_0_fu_code_2; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_3; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_3 = mem_xcpt_uops_0_fu_code_3; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_4; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_4 = mem_xcpt_uops_0_fu_code_4; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_5; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_5 = mem_xcpt_uops_0_fu_code_5; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_6; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_6 = mem_xcpt_uops_0_fu_code_6; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_7; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_7 = mem_xcpt_uops_0_fu_code_7; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_8; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_8 = mem_xcpt_uops_0_fu_code_8; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_9; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_9 = mem_xcpt_uops_0_fu_code_9; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_issued; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_issued = mem_xcpt_uops_0_iw_issued; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_issued_partial_agen; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_issued_partial_agen = mem_xcpt_uops_0_iw_issued_partial_agen; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_issued_partial_dgen; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_issued_partial_dgen = mem_xcpt_uops_0_iw_issued_partial_dgen; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_iw_p1_speculative_child; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p1_speculative_child = mem_xcpt_uops_0_iw_p1_speculative_child; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_iw_p2_speculative_child; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p2_speculative_child = mem_xcpt_uops_0_iw_p2_speculative_child; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_p1_bypass_hint; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p1_bypass_hint = mem_xcpt_uops_0_iw_p1_bypass_hint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_p2_bypass_hint; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p2_bypass_hint = mem_xcpt_uops_0_iw_p2_bypass_hint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_p3_bypass_hint; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p3_bypass_hint = mem_xcpt_uops_0_iw_p3_bypass_hint; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_dis_col_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_dis_col_sel = mem_xcpt_uops_0_dis_col_sel; // @[lsu.scala:459:29, :799:32] reg [11:0] mem_xcpt_uops_0_br_mask; // @[lsu.scala:799:32] assign mem_xcpt_uop_br_mask = mem_xcpt_uops_0_br_mask; // @[lsu.scala:459:29, :799:32] reg [3:0] mem_xcpt_uops_0_br_tag; // @[lsu.scala:799:32] assign mem_xcpt_uop_br_tag = mem_xcpt_uops_0_br_tag; // @[lsu.scala:459:29, :799:32] reg [3:0] mem_xcpt_uops_0_br_type; // @[lsu.scala:799:32] assign mem_xcpt_uop_br_type = mem_xcpt_uops_0_br_type; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_sfb; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_sfb = mem_xcpt_uops_0_is_sfb; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_fence; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_fence = mem_xcpt_uops_0_is_fence; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_fencei; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_fencei = mem_xcpt_uops_0_is_fencei; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_sfence; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_sfence = mem_xcpt_uops_0_is_sfence; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_amo; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_amo = mem_xcpt_uops_0_is_amo; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_eret; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_eret = mem_xcpt_uops_0_is_eret; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_sys_pc2epc = mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_rocc; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_rocc = mem_xcpt_uops_0_is_rocc; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_mov; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_mov = mem_xcpt_uops_0_is_mov; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_ftq_idx = mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_edge_inst; // @[lsu.scala:799:32] assign mem_xcpt_uop_edge_inst = mem_xcpt_uops_0_edge_inst; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_pc_lob; // @[lsu.scala:799:32] assign mem_xcpt_uop_pc_lob = mem_xcpt_uops_0_pc_lob; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_taken; // @[lsu.scala:799:32] assign mem_xcpt_uop_taken = mem_xcpt_uops_0_taken; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_imm_rename; // @[lsu.scala:799:32] assign mem_xcpt_uop_imm_rename = mem_xcpt_uops_0_imm_rename; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_imm_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_imm_sel = mem_xcpt_uops_0_imm_sel; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_pimm; // @[lsu.scala:799:32] assign mem_xcpt_uop_pimm = mem_xcpt_uops_0_pimm; // @[lsu.scala:459:29, :799:32] reg [19:0] mem_xcpt_uops_0_imm_packed; // @[lsu.scala:799:32] assign mem_xcpt_uop_imm_packed = mem_xcpt_uops_0_imm_packed; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_op1_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_op1_sel = mem_xcpt_uops_0_op1_sel; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_op2_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_op2_sel = mem_xcpt_uops_0_op2_sel; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ldst; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ldst = mem_xcpt_uops_0_fp_ctrl_ldst; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_wen; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_wen = mem_xcpt_uops_0_fp_ctrl_wen; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ren1; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ren1 = mem_xcpt_uops_0_fp_ctrl_ren1; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ren2; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ren2 = mem_xcpt_uops_0_fp_ctrl_ren2; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ren3; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ren3 = mem_xcpt_uops_0_fp_ctrl_ren3; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_swap12; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_swap12 = mem_xcpt_uops_0_fp_ctrl_swap12; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_swap23; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_swap23 = mem_xcpt_uops_0_fp_ctrl_swap23; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_fp_ctrl_typeTagIn; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_typeTagIn = mem_xcpt_uops_0_fp_ctrl_typeTagIn; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_fp_ctrl_typeTagOut; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_typeTagOut = mem_xcpt_uops_0_fp_ctrl_typeTagOut; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_fromint; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_fromint = mem_xcpt_uops_0_fp_ctrl_fromint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_toint; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_toint = mem_xcpt_uops_0_fp_ctrl_toint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_fastpipe; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_fastpipe = mem_xcpt_uops_0_fp_ctrl_fastpipe; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_fma; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_fma = mem_xcpt_uops_0_fp_ctrl_fma; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_div; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_div = mem_xcpt_uops_0_fp_ctrl_div; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_sqrt; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_sqrt = mem_xcpt_uops_0_fp_ctrl_sqrt; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_wflags; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_wflags = mem_xcpt_uops_0_fp_ctrl_wflags; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_vec; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_vec = mem_xcpt_uops_0_fp_ctrl_vec; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_rob_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_rob_idx = mem_xcpt_uops_0_rob_idx; // @[lsu.scala:459:29, :799:32] reg [3:0] mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_ldq_idx = mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:459:29, :799:32] reg [3:0] mem_xcpt_uops_0_stq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_stq_idx = mem_xcpt_uops_0_stq_idx; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_rxq_idx = mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_pdst; // @[lsu.scala:799:32] assign mem_xcpt_uop_pdst = mem_xcpt_uops_0_pdst; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_prs1; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs1 = mem_xcpt_uops_0_prs1; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_prs2; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs2 = mem_xcpt_uops_0_prs2; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_prs3; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs3 = mem_xcpt_uops_0_prs3; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_ppred; // @[lsu.scala:799:32] assign mem_xcpt_uop_ppred = mem_xcpt_uops_0_ppred; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs1_busy = mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs2_busy = mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs3_busy = mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_ppred_busy = mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:799:32] assign mem_xcpt_uop_stale_pdst = mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_exception; // @[lsu.scala:799:32] assign mem_xcpt_uop_exception = mem_xcpt_uops_0_exception; // @[lsu.scala:459:29, :799:32] reg [63:0] mem_xcpt_uops_0_exc_cause; // @[lsu.scala:799:32] assign mem_xcpt_uop_exc_cause = mem_xcpt_uops_0_exc_cause; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:799:32] assign mem_xcpt_uop_mem_cmd = mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_mem_size; // @[lsu.scala:799:32] assign mem_xcpt_uop_mem_size = mem_xcpt_uops_0_mem_size; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_mem_signed; // @[lsu.scala:799:32] assign mem_xcpt_uop_mem_signed = mem_xcpt_uops_0_mem_signed; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:799:32] assign mem_xcpt_uop_uses_ldq = mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_uses_stq; // @[lsu.scala:799:32] assign mem_xcpt_uop_uses_stq = mem_xcpt_uops_0_uses_stq; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_unique; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_unique = mem_xcpt_uops_0_is_unique; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:799:32] assign mem_xcpt_uop_flush_on_commit = mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_csr_cmd; // @[lsu.scala:799:32] assign mem_xcpt_uop_csr_cmd = mem_xcpt_uops_0_csr_cmd; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:799:32] assign mem_xcpt_uop_ldst_is_rs1 = mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_ldst; // @[lsu.scala:799:32] assign mem_xcpt_uop_ldst = mem_xcpt_uops_0_ldst; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_lrs1; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs1 = mem_xcpt_uops_0_lrs1; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_lrs2; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs2 = mem_xcpt_uops_0_lrs2; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_lrs3; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs3 = mem_xcpt_uops_0_lrs3; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:799:32] assign mem_xcpt_uop_dst_rtype = mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs1_rtype = mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs2_rtype = mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_frs3_en; // @[lsu.scala:799:32] assign mem_xcpt_uop_frs3_en = mem_xcpt_uops_0_frs3_en; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fcn_dw; // @[lsu.scala:799:32] assign mem_xcpt_uop_fcn_dw = mem_xcpt_uops_0_fcn_dw; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_fcn_op; // @[lsu.scala:799:32] assign mem_xcpt_uop_fcn_op = mem_xcpt_uops_0_fcn_op; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_val; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_val = mem_xcpt_uops_0_fp_val; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_fp_rm; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_rm = mem_xcpt_uops_0_fp_rm; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_fp_typ; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_typ = mem_xcpt_uops_0_fp_typ; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_xcpt_pf_if = mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_xcpt_ae_if = mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_xcpt_ma_if = mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_bp_debug_if = mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_bp_xcpt_if = mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_fsrc = mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_tsrc = mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:459:29, :799:32] wire [2:0] _mem_xcpt_causes_T = ae_ld_0 ? 3'h5 : 3'h0; // @[lsu.scala:321:49, :808:8] wire [2:0] _mem_xcpt_causes_T_1 = ae_st_0 ? 3'h7 : _mem_xcpt_causes_T; // @[lsu.scala:321:49, :807:8, :808:8] wire [3:0] _mem_xcpt_causes_T_2 = pf_ld_0 ? 4'hD : {1'h0, _mem_xcpt_causes_T_1}; // @[lsu.scala:321:49, :806:8, :807:8] wire [3:0] _mem_xcpt_causes_T_3 = pf_st_0 ? 4'hF : _mem_xcpt_causes_T_2; // @[lsu.scala:321:49, :805:8, :806:8] wire [3:0] _mem_xcpt_causes_T_4 = ma_ld_0 ? 4'h4 : _mem_xcpt_causes_T_3; // @[lsu.scala:321:49, :804:8, :805:8] wire [3:0] _mem_xcpt_causes_T_5 = ma_st_0 ? 4'h6 : _mem_xcpt_causes_T_4; // @[lsu.scala:321:49, :803:8, :804:8] wire [3:0] _mem_xcpt_causes_T_6 = _mem_xcpt_causes_T_5; // @[lsu.scala:802:8, :803:8] wire [3:0] _mem_xcpt_causes_T_7 = _mem_xcpt_causes_T_6; // @[lsu.scala:801:8, :802:8] wire [3:0] _mem_xcpt_causes_WIRE_0 = _mem_xcpt_causes_T_7; // @[lsu.scala:321:49, :801:8] reg [3:0] mem_xcpt_causes_0; // @[lsu.scala:800:32] assign mem_xcpt_cause = mem_xcpt_causes_0; // @[lsu.scala:458:29, :800:32] reg [63:0] mem_xcpt_vaddrs_0; // @[lsu.scala:810:32] assign mem_xcpt_vaddr = mem_xcpt_vaddrs_0; // @[lsu.scala:460:29, :810:32] wire _exe_tlb_miss_T_1; // @[lsu.scala:835:83] wire _exe_tlb_miss_T_2 = exe_tlb_valid_0 & _exe_tlb_miss_T_1; // @[lsu.scala:649:27, :835:{58,83}] wire exe_tlb_miss_0 = _exe_tlb_miss_T_2; // @[lsu.scala:321:49, :835:58] wire [19:0] _exe_tlb_paddr_T = _dtlb_io_resp_0_paddr[31:12]; // @[lsu.scala:308:20, :836:62] wire [11:0] _exe_tlb_paddr_T_1 = exe_tlb_vaddr_0[11:0]; // @[lsu.scala:321:49, :837:57] wire [31:0] _exe_tlb_paddr_T_2 = {_exe_tlb_paddr_T, _exe_tlb_paddr_T_1}; // @[lsu.scala:836:{40,62}, :837:57] wire [31:0] exe_tlb_paddr_0 = _exe_tlb_paddr_T_2; // @[lsu.scala:321:49, :836:40] wire _exe_tlb_uncacheable_T = ~_dtlb_io_resp_0_cacheable; // @[lsu.scala:308:20, :838:43] wire exe_tlb_uncacheable_0 = _exe_tlb_uncacheable_T; // @[lsu.scala:321:49, :838:43] reg REG; // @[lsu.scala:845:21] wire [11:0] _exe_agen_killed_T = io_core_brupdate_b1_mispredict_mask_0 & io_core_agen_0_bits_uop_br_mask_0; // @[util.scala:126:51] wire _exe_agen_killed_T_1 = \|_exe_agen_killed_T; // @[util.scala:126:{51,59}] wire _exe_agen_killed_T_2 = _exe_agen_killed_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire exe_agen_killed_0 = _exe_agen_killed_T_2; // @[util.scala:61:61] assign io_dmem_req_valid_0 = dmem_req_0_valid; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_valid_0 = dmem_req_0_valid; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_inst_0 = dmem_req_0_bits_uop_inst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_inst_0 = dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_rvc_0 = dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_pc_0 = dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_0_0 = dmem_req_0_bits_uop_iq_type_0; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_1_0 = dmem_req_0_bits_uop_iq_type_1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_2_0 = dmem_req_0_bits_uop_iq_type_2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_3_0 = dmem_req_0_bits_uop_iq_type_3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_0_0 = dmem_req_0_bits_uop_fu_code_0; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_1_0 = dmem_req_0_bits_uop_fu_code_1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_2_0 = dmem_req_0_bits_uop_fu_code_2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_3_0 = dmem_req_0_bits_uop_fu_code_3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_4_0 = dmem_req_0_bits_uop_fu_code_4; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_5_0 = dmem_req_0_bits_uop_fu_code_5; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_6_0 = dmem_req_0_bits_uop_fu_code_6; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_7_0 = dmem_req_0_bits_uop_fu_code_7; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_8_0 = dmem_req_0_bits_uop_fu_code_8; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_9_0 = dmem_req_0_bits_uop_fu_code_9; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_issued_0 = dmem_req_0_bits_uop_iw_issued; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen_0 = dmem_req_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen_0 = dmem_req_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child_0 = dmem_req_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child_0 = dmem_req_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint_0 = dmem_req_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint_0 = dmem_req_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint_0 = dmem_req_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_dis_col_sel_0 = dmem_req_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_br_mask_0 = dmem_req_0_bits_uop_br_mask; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_br_tag_0 = dmem_req_0_bits_uop_br_tag; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_br_type_0 = dmem_req_0_bits_uop_br_type; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_sfb_0 = dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_fence_0 = dmem_req_0_bits_uop_is_fence; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_fencei_0 = dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_sfence_0 = dmem_req_0_bits_uop_is_sfence; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_amo_0 = dmem_req_0_bits_uop_is_amo; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_eret_0 = dmem_req_0_bits_uop_is_eret; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0 = dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_rocc_0 = dmem_req_0_bits_uop_is_rocc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_mov_0 = dmem_req_0_bits_uop_is_mov; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ftq_idx_0 = dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_edge_inst_0 = dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_pc_lob_0 = dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_taken_0 = dmem_req_0_bits_uop_taken; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_imm_rename_0 = dmem_req_0_bits_uop_imm_rename; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_imm_sel_0 = dmem_req_0_bits_uop_imm_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_pimm_0 = dmem_req_0_bits_uop_pimm; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_imm_packed_0 = dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_op1_sel_0 = dmem_req_0_bits_uop_op1_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_op2_sel_0 = dmem_req_0_bits_uop_op2_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst_0 = dmem_req_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_wen_0 = dmem_req_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1_0 = dmem_req_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2_0 = dmem_req_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3_0 = dmem_req_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12_0 = dmem_req_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23_0 = dmem_req_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn_0 = dmem_req_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut_0 = dmem_req_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint_0 = dmem_req_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_toint_0 = dmem_req_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe_0 = dmem_req_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_fma_0 = dmem_req_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_div_0 = dmem_req_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt_0 = dmem_req_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags_0 = dmem_req_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_vec_0 = dmem_req_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_rob_idx_0 = dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ldq_idx_0 = dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_stq_idx_0 = dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_rxq_idx_0 = dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_pdst_0 = dmem_req_0_bits_uop_pdst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs1_0 = dmem_req_0_bits_uop_prs1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs2_0 = dmem_req_0_bits_uop_prs2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs3_0 = dmem_req_0_bits_uop_prs3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ppred_0 = dmem_req_0_bits_uop_ppred; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs1_busy_0 = dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs2_busy_0 = dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs3_busy_0 = dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ppred_busy_0 = dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_stale_pdst_0 = dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_exception_0 = dmem_req_0_bits_uop_exception; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_exc_cause_0 = dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_mem_cmd_0 = dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_mem_size_0 = dmem_req_0_bits_uop_mem_size; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_mem_signed_0 = dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_uses_ldq_0 = dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_uses_stq_0 = dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_unique_0 = dmem_req_0_bits_uop_is_unique; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_flush_on_commit_0 = dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_csr_cmd_0 = dmem_req_0_bits_uop_csr_cmd; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0 = dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ldst_0 = dmem_req_0_bits_uop_ldst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs1_0 = dmem_req_0_bits_uop_lrs1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs2_0 = dmem_req_0_bits_uop_lrs2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs3_0 = dmem_req_0_bits_uop_lrs3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_dst_rtype_0 = dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs1_rtype_0 = dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs2_rtype_0 = dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_frs3_en_0 = dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fcn_dw_0 = dmem_req_0_bits_uop_fcn_dw; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fcn_op_0 = dmem_req_0_bits_uop_fcn_op; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_val_0 = dmem_req_0_bits_uop_fp_val; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_rm_0 = dmem_req_0_bits_uop_fp_rm; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_typ_0 = dmem_req_0_bits_uop_fp_typ; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0 = dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0 = dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0 = dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_bp_debug_if_0 = dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0 = dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_fsrc_0 = dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_tsrc_0 = dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_addr_0 = dmem_req_0_bits_addr; // @[lsu.scala:211:7, :877:22] wire [39:0] _mem_paddr_WIRE_0 = dmem_req_0_bits_addr; // @[lsu.scala:321:49, :877:22] assign io_dmem_req_bits_0_bits_data_0 = dmem_req_0_bits_data; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_is_hella_0 = dmem_req_0_bits_is_hella; // @[lsu.scala:211:7, :877:22] wire _dmem_req_fire_T = io_dmem_req_ready_0 & io_dmem_req_valid_0; // @[Decoupled.scala:51:35] wire _dmem_req_fire_T_1 = dmem_req_0_valid & _dmem_req_fire_T; // @[Decoupled.scala:51:35] wire dmem_req_fire_0 = _dmem_req_fire_T_1; // @[lsu.scala:321:49, :880:55] wire s0_executing_loads_0; // @[lsu.scala:882:36] wire s0_executing_loads_1; // @[lsu.scala:882:36] wire s0_executing_loads_2; // @[lsu.scala:882:36] wire s0_executing_loads_3; // @[lsu.scala:882:36] wire s0_executing_loads_4; // @[lsu.scala:882:36] wire s0_executing_loads_5; // @[lsu.scala:882:36] wire s0_executing_loads_6; // @[lsu.scala:882:36] wire s0_executing_loads_7; // @[lsu.scala:882:36] wire s0_executing_loads_8; // @[lsu.scala:882:36] wire s0_executing_loads_9; // @[lsu.scala:882:36] wire s0_executing_loads_10; // @[lsu.scala:882:36] wire s0_executing_loads_11; // @[lsu.scala:882:36] wire s0_executing_loads_12; // @[lsu.scala:882:36] wire s0_executing_loads_13; // @[lsu.scala:882:36] wire s0_executing_loads_14; // @[lsu.scala:882:36] wire s0_executing_loads_15; // @[lsu.scala:882:36] wire s0_kills_0; // @[lsu.scala:883:22] wire _io_dmem_s1_kill_0_T = s0_kills_0 & dmem_req_fire_0; // @[lsu.scala:321:49, :883:22, :893:47] reg io_dmem_s1_kill_0_REG; // @[lsu.scala:893:34] wire [39:0] _GEN_383 = {8'h0, exe_tlb_paddr_0}; // @[lsu.scala:321:49, :897:30] wire _GEN_384 = exe_tlb_miss_0 \| exe_tlb_uncacheable_0; // @[lsu.scala:321:49, :900:49] wire _s0_kills_0_T; // @[lsu.scala:900:49] assign _s0_kills_0_T = _GEN_384; // @[lsu.scala:900:49] wire _s0_kills_0_T_4; // @[lsu.scala:909:38] assign _s0_kills_0_T_4 = _GEN_384; // @[lsu.scala:900:49, :909:38] wire _s0_kills_0_T_1 = _s0_kills_0_T \| ma_ld_0; // @[lsu.scala:321:49, :900:{49,75}] wire _s0_kills_0_T_2 = _s0_kills_0_T_1 \| ae_ld_0; // @[lsu.scala:321:49, :900:{75,87}] wire _s0_kills_0_T_3 = _s0_kills_0_T_2 \| pf_ld_0; // @[lsu.scala:321:49, :900:{87,99}] wire _s0_executing_loads_T = ~s0_kills_0; // @[lsu.scala:883:22, :901:70] wire _s0_executing_loads_T_1 = dmem_req_fire_0 & _s0_executing_loads_T; // @[lsu.scala:321:49, :901:{67,70}] wire _s0_kills_0_T_5 = _s0_kills_0_T_4 \| ma_ld_0; // @[lsu.scala:321:49, :909:{38,64}] wire _s0_kills_0_T_6 = _s0_kills_0_T_5 \| ae_ld_0; // @[lsu.scala:321:49, :909:{64,76}] wire _s0_kills_0_T_7 = _s0_kills_0_T_6 \| pf_ld_0; // @[lsu.scala:321:49, :909:{76,88}] assign s0_kills_0 = will_fire_load_agen_exec_0 ? _s0_kills_0_T_3 : will_fire_load_retry_0 & _s0_kills_0_T_7; // @[lsu.scala:469:39, :476:41, :883:22, :892:17, :895:40, :900:{30,99}, :904:43, :909:{19,88}] wire _s0_executing_loads_T_2 = ~s0_kills_0; // @[lsu.scala:883:22, :901:70, :910:64] wire _s0_executing_loads_T_3 = dmem_req_fire_0 & _s0_executing_loads_T_2; // @[lsu.scala:321:49, :910:{61,64}] wire [1:0] dmem_req_0_bits_data_size; // @[AMOALU.scala:11:18] wire _dmem_req_0_bits_data_T = dmem_req_0_bits_data_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _dmem_req_0_bits_data_T_1 = _stq_execute_queue_io_deq_bits_data_bits[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_2 = {2{_dmem_req_0_bits_data_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_3 = {2{_dmem_req_0_bits_data_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_4 = {2{_dmem_req_0_bits_data_T_3}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_5 = dmem_req_0_bits_data_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _dmem_req_0_bits_data_T_6 = _stq_execute_queue_io_deq_bits_data_bits[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_7 = {2{_dmem_req_0_bits_data_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_8 = {2{_dmem_req_0_bits_data_T_7}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_9 = dmem_req_0_bits_data_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _dmem_req_0_bits_data_T_10 = _stq_execute_queue_io_deq_bits_data_bits[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_11 = {2{_dmem_req_0_bits_data_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_12 = _dmem_req_0_bits_data_T_9 ? _dmem_req_0_bits_data_T_11 : _stq_execute_queue_io_deq_bits_data_bits; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_13 = _dmem_req_0_bits_data_T_5 ? _dmem_req_0_bits_data_T_8 : _dmem_req_0_bits_data_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_14 = _dmem_req_0_bits_data_T ? _dmem_req_0_bits_data_T_4 : _dmem_req_0_bits_data_T_13; // @[AMOALU.scala:29:{13,19,32}] wire _GEN_385 = will_fire_load_agen_exec_0 \| will_fire_load_retry_0; // @[lsu.scala:469:39, :476:41, :556:41, :895:40, :904:43, :911:84] assign dmem_req_0_bits_uop_inst = _GEN_385 ? exe_tlb_uop_0_inst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_inst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_inst = _GEN_385 ? exe_tlb_uop_0_debug_inst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_debug_inst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_rvc = _GEN_385 ? exe_tlb_uop_0_is_rvc : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_rvc : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_pc = _GEN_385 ? exe_tlb_uop_0_debug_pc : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_debug_pc : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_0 = _GEN_385 ? exe_tlb_uop_0_iq_type_0 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iq_type_0 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_1 = _GEN_385 ? exe_tlb_uop_0_iq_type_1 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iq_type_1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_2 = _GEN_385 ? exe_tlb_uop_0_iq_type_2 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iq_type_2 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_2; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_3 = _GEN_385 ? exe_tlb_uop_0_iq_type_3 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iq_type_3 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_3; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_0 = _GEN_385 ? exe_tlb_uop_0_fu_code_0 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_0 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_1 = _GEN_385 ? exe_tlb_uop_0_fu_code_1 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_2 = _GEN_385 ? exe_tlb_uop_0_fu_code_2 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_2 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_2; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_3 = _GEN_385 ? exe_tlb_uop_0_fu_code_3 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_3 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_3; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_4 = _GEN_385 ? exe_tlb_uop_0_fu_code_4 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_4 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_4; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_5 = _GEN_385 ? exe_tlb_uop_0_fu_code_5 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_5 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_5; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_6 = _GEN_385 ? exe_tlb_uop_0_fu_code_6 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_6 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_6; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_7 = _GEN_385 ? exe_tlb_uop_0_fu_code_7 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_7 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_7; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_8 = _GEN_385 ? exe_tlb_uop_0_fu_code_8 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_8 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_8; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_9 = _GEN_385 ? exe_tlb_uop_0_fu_code_9 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_9 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_9; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_issued = _GEN_385 ? exe_tlb_uop_0_iw_issued : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_issued : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_issued; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_issued_partial_agen = _GEN_385 ? exe_tlb_uop_0_iw_issued_partial_agen : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_agen : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_issued_partial_dgen = _GEN_385 ? exe_tlb_uop_0_iw_issued_partial_dgen : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_dgen : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p1_speculative_child = _GEN_385 ? exe_tlb_uop_0_iw_p1_speculative_child : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_p1_speculative_child : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_iw_p1_speculative_child : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p2_speculative_child = _GEN_385 ? exe_tlb_uop_0_iw_p2_speculative_child : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_p2_speculative_child : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_iw_p2_speculative_child : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p1_bypass_hint = _GEN_385 ? exe_tlb_uop_0_iw_p1_bypass_hint : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_p1_bypass_hint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p2_bypass_hint = _GEN_385 ? exe_tlb_uop_0_iw_p2_bypass_hint : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_p2_bypass_hint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p3_bypass_hint = _GEN_385 ? exe_tlb_uop_0_iw_p3_bypass_hint : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_p3_bypass_hint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_dis_col_sel = _GEN_385 ? exe_tlb_uop_0_dis_col_sel : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_dis_col_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_dis_col_sel : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_br_mask = _GEN_385 ? exe_tlb_uop_0_br_mask : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_br_mask : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_br_mask : 12'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_br_tag = _GEN_385 ? exe_tlb_uop_0_br_tag : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_br_tag : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_br_type = _GEN_385 ? exe_tlb_uop_0_br_type : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_br_type : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_sfb = _GEN_385 ? exe_tlb_uop_0_is_sfb : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_sfb : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_fence = _GEN_385 ? exe_tlb_uop_0_is_fence : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_fence : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_fencei = _GEN_385 ? exe_tlb_uop_0_is_fencei : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_fencei : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_sfence = _GEN_385 ? exe_tlb_uop_0_is_sfence : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_sfence : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_sfence; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_amo = _GEN_385 ? exe_tlb_uop_0_is_amo : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_amo : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_eret = _GEN_385 ? exe_tlb_uop_0_is_eret : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_eret : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_eret; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_sys_pc2epc = _GEN_385 ? exe_tlb_uop_0_is_sys_pc2epc : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_sys_pc2epc : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_rocc = _GEN_385 ? exe_tlb_uop_0_is_rocc : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_rocc : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_rocc; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_mov = _GEN_385 ? exe_tlb_uop_0_is_mov : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_mov : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_mov; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ftq_idx = _GEN_385 ? exe_tlb_uop_0_ftq_idx : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_ftq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_edge_inst = _GEN_385 ? exe_tlb_uop_0_edge_inst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_edge_inst : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_pc_lob = _GEN_385 ? exe_tlb_uop_0_pc_lob : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_pc_lob : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_taken = _GEN_385 ? exe_tlb_uop_0_taken : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_taken : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_imm_rename = _GEN_385 ? exe_tlb_uop_0_imm_rename : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_imm_rename : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_imm_rename; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_imm_sel = _GEN_385 ? exe_tlb_uop_0_imm_sel : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_imm_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_pimm = _GEN_385 ? exe_tlb_uop_0_pimm : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_pimm : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_imm_packed = _GEN_385 ? exe_tlb_uop_0_imm_packed : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_imm_packed : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_op1_sel = _GEN_385 ? exe_tlb_uop_0_op1_sel : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_op1_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_op2_sel = _GEN_385 ? exe_tlb_uop_0_op2_sel : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_op2_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ldst = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_ldst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ldst : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_wen = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_wen : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wen : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ren1 = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_ren1 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ren2 = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_ren2 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren2 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ren3 = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_ren3 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren3 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_swap12 = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_swap12 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap12 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_swap23 = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_swap23 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap23 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_typeTagIn = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_typeTagIn : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagIn : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_typeTagOut = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_typeTagOut : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagOut : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_fromint = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_fromint : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fromint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_toint = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_toint : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_toint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_fastpipe = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_fastpipe : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fastpipe : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_fma = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_fma : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fma : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_div = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_div : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_div : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_sqrt = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_sqrt : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_sqrt : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_wflags = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_wflags : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wflags : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_vec = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_vec : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_vec : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_rob_idx = _GEN_385 ? exe_tlb_uop_0_rob_idx : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_rob_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_rob_idx : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ldq_idx = _GEN_385 ? exe_tlb_uop_0_ldq_idx : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_ldq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ldq_idx : 4'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_stq_idx = _GEN_385 ? exe_tlb_uop_0_stq_idx : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_stq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_stq_idx : 4'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_rxq_idx = _GEN_385 ? exe_tlb_uop_0_rxq_idx : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_rxq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_pdst = _GEN_385 ? exe_tlb_uop_0_pdst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_pdst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs1 = _GEN_385 ? exe_tlb_uop_0_prs1 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_prs1 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs2 = _GEN_385 ? exe_tlb_uop_0_prs2 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_prs2 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs3 = _GEN_385 ? exe_tlb_uop_0_prs3 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_prs3 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ppred = _GEN_385 ? exe_tlb_uop_0_ppred : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_ppred : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs1_busy = _GEN_385 ? exe_tlb_uop_0_prs1_busy : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_prs1_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs2_busy = _GEN_385 ? exe_tlb_uop_0_prs2_busy : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_prs2_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs3_busy = _GEN_385 ? exe_tlb_uop_0_prs3_busy : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_prs3_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ppred_busy = _GEN_385 ? exe_tlb_uop_0_ppred_busy : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_ppred_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_stale_pdst = _GEN_385 ? exe_tlb_uop_0_stale_pdst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_stale_pdst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_exception = _GEN_385 ? exe_tlb_uop_0_exception : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_exception : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_exc_cause = _GEN_385 ? exe_tlb_uop_0_exc_cause : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_exc_cause : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_uses_ldq = _GEN_385 ? exe_tlb_uop_0_uses_ldq : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_uses_ldq : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_uses_stq = _GEN_385 ? exe_tlb_uop_0_uses_stq : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_uses_stq : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_unique = _GEN_385 ? exe_tlb_uop_0_is_unique : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_unique : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_flush_on_commit = _GEN_385 ? exe_tlb_uop_0_flush_on_commit : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_flush_on_commit : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_csr_cmd = _GEN_385 ? exe_tlb_uop_0_csr_cmd : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_csr_cmd : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ldst_is_rs1 = _GEN_385 ? exe_tlb_uop_0_ldst_is_rs1 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_ldst_is_rs1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ldst = _GEN_385 ? exe_tlb_uop_0_ldst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_ldst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs1 = _GEN_385 ? exe_tlb_uop_0_lrs1 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_lrs1 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs2 = _GEN_385 ? exe_tlb_uop_0_lrs2 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_lrs2 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs3 = _GEN_385 ? exe_tlb_uop_0_lrs3 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_lrs3 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_dst_rtype = _GEN_385 ? exe_tlb_uop_0_dst_rtype : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_dst_rtype : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs1_rtype = _GEN_385 ? exe_tlb_uop_0_lrs1_rtype : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_lrs1_rtype : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs2_rtype = _GEN_385 ? exe_tlb_uop_0_lrs2_rtype : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_lrs2_rtype : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_frs3_en = _GEN_385 ? exe_tlb_uop_0_frs3_en : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_frs3_en : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fcn_dw = _GEN_385 ? exe_tlb_uop_0_fcn_dw : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fcn_dw : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fcn_dw; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fcn_op = _GEN_385 ? exe_tlb_uop_0_fcn_op : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fcn_op : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_val = _GEN_385 ? exe_tlb_uop_0_fp_val : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_val : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_rm = _GEN_385 ? exe_tlb_uop_0_fp_rm : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_rm : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_typ = _GEN_385 ? exe_tlb_uop_0_fp_typ : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_typ : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_xcpt_pf_if = _GEN_385 ? exe_tlb_uop_0_xcpt_pf_if : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_xcpt_pf_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_xcpt_ae_if = _GEN_385 ? exe_tlb_uop_0_xcpt_ae_if : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_xcpt_ae_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_xcpt_ma_if = _GEN_385 ? exe_tlb_uop_0_xcpt_ma_if : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_xcpt_ma_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_bp_debug_if = _GEN_385 ? exe_tlb_uop_0_bp_debug_if : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_bp_debug_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_bp_xcpt_if = _GEN_385 ? exe_tlb_uop_0_bp_xcpt_if : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_bp_xcpt_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_fsrc = _GEN_385 ? exe_tlb_uop_0_debug_fsrc : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_debug_fsrc : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_tsrc = _GEN_385 ? exe_tlb_uop_0_debug_tsrc : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_debug_tsrc : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign s0_executing_loads_0 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h0 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_368 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_353 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_1 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h1 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_369 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_354 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_2 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h2 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_370 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_355 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_3 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h3 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_371 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_356 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_4 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h4 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_372 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_357 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_5 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h5 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_373 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_358 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_6 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h6 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_374 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_359 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_7 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h7 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_375 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_360 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_8 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h8 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_376 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_361 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_9 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h9 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_377 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_362 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_10 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'hA & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_378 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_363 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_11 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'hB & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_379 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_364 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_12 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'hC & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_380 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_365 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_13 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'hD & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_381 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_366 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_14 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'hE & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_382 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_367 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_15 = will_fire_load_agen_exec_0 ? (&ldq_incoming_idx_0) & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? (&_retry_queue_io_deq_bits_uop_ldq_idx) & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & (&ldq_wakeup_idx) & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :506:31, :533:27, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] wire _dmem_req_0_valid_T = ~io_hellacache_s1_kill_0; // @[lsu.scala:211:7, :937:42] wire _dmem_req_0_valid_T_3 = _dmem_req_0_valid_T; // @[lsu.scala:937:{42,65}] wire _dmem_req_0_valid_T_1 = ~exe_tlb_miss_0; // @[lsu.scala:321:49, :937:69] wire _GEN_386 = will_fire_load_agen_exec_0 \| will_fire_load_retry_0 \| _T_1139 \| will_fire_load_wakeup_0; // @[lsu.scala:304:34, :469:39, :476:41, :480:41, :565:78, :895:40, :904:43, :911:84, :926:44, :934:47] assign dmem_req_0_valid = _GEN_386 \| (will_fire_hella_incoming_0 ? _dmem_req_0_valid_T_3 : will_fire_hella_wakeup_0); // @[lsu.scala:304:34, :473:41, :474:41, :877:22, :895:40, :896:30, :904:43, :905:30, :911:84, :912:33, :926:44, :927:30, :934:47, :937:{39,65}, :951:5] assign dmem_req_0_bits_addr = will_fire_load_agen_exec_0 \| will_fire_load_retry_0 ? _GEN_383 : _T_1139 ? _stq_execute_queue_io_deq_bits_addr_bits : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_addr_bits : will_fire_hella_incoming_0 ? _GEN_383 : will_fire_hella_wakeup_0 ? {8'h0, hella_paddr} : 40'h0; // @[lsu.scala:304:34, :469:39, :473:41, :474:41, :476:41, :480:41, :510:32, :558:11, :565:78, :877:22, :888:28, :895:40, :897:30, :904:43, :911:84, :913:33, :926:44, :928:30, :934:47, :938:39, :951:5, :954:39] wire [7:0] _dmem_req_0_bits_data_T_31 = hella_data_data[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_32 = {2{_dmem_req_0_bits_data_T_31}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_33 = {2{_dmem_req_0_bits_data_T_32}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_34 = {2{_dmem_req_0_bits_data_T_33}}; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_36 = hella_data_data[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_37 = {2{_dmem_req_0_bits_data_T_36}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_38 = {2{_dmem_req_0_bits_data_T_37}}; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_40 = hella_data_data[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_41 = {2{_dmem_req_0_bits_data_T_40}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_43 = _dmem_req_0_bits_data_T_42; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_44 = _dmem_req_0_bits_data_T_43; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_data = _GEN_385 ? 64'h0 : _T_1139 ? _dmem_req_0_bits_data_T_14 : will_fire_load_wakeup_0 \| will_fire_hella_incoming_0 \| ~will_fire_hella_wakeup_0 ? 64'h0 : _dmem_req_0_bits_data_T_44; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_uop_mem_cmd = _GEN_385 ? exe_tlb_uop_0_mem_cmd : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_mem_cmd : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30, :934:47] assign dmem_req_0_bits_uop_mem_size = _GEN_385 ? exe_tlb_uop_0_mem_size : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_mem_size : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_mem_size : {2{will_fire_hella_incoming_0 \| will_fire_hella_wakeup_0}}; // @[lsu.scala:321:49, :473:41, :474:41, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30, :934:47, :944:39, :951:5, :960:39] assign dmem_req_0_bits_uop_mem_signed = _GEN_385 ? exe_tlb_uop_0_mem_signed : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_mem_signed : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30, :934:47] assign dmem_req_0_bits_is_hella = ~_GEN_386 & (will_fire_hella_incoming_0 \| will_fire_hella_wakeup_0); // @[lsu.scala:304:34, :473:41, :474:41, :877:22, :890:31, :895:40, :904:43, :911:84, :926:44, :934:47, :946:39, :951:5] wire _T_183 = _T_182 \| will_fire_load_retry_0; // @[lsu.scala:476:41, :687:61, :967:65] wire [3:0] ldq_idx = _ldq_idx_T ? ldq_incoming_idx_0 : _retry_queue_io_deq_bits_uop_ldq_idx; // @[lsu.scala:321:49, :533:27, :969:{24,48}] wire _ldq_addr_valid_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50] wire _ldq_addr_valid_T_1 = _ldq_addr_valid_T \| will_fire_load_retry_0; // @[lsu.scala:476:41, :970:{50,70}] wire [63:0] _GEN_387 = exe_tlb_miss_0 ? exe_tlb_vaddr_0 : {32'h0, exe_tlb_paddr_0}; // @[lsu.scala:321:49, :971:53] wire [63:0] _ldq_addr_bits_T; // @[lsu.scala:971:53] assign _ldq_addr_bits_T = _GEN_387; // @[lsu.scala:971:53] wire [63:0] _stq_addr_bits_T; // @[lsu.scala:987:48] assign _stq_addr_bits_T = _GEN_387; // @[lsu.scala:971:53, :987:48] wire [7:0] ldq_ld_byte_mask_mask; // @[lsu.scala:1951:22] wire _ldq_ld_byte_mask_mask_T = exe_tlb_uop_0_mem_size == 2'h0; // @[lsu.scala:321:49, :1953:26] wire [2:0] _ldq_ld_byte_mask_mask_T_1 = exe_tlb_vaddr_0[2:0]; // @[lsu.scala:321:49, :1953:55] wire [14:0] _ldq_ld_byte_mask_mask_T_2 = 15'h1 << _ldq_ld_byte_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _ldq_ld_byte_mask_mask_T_3 = exe_tlb_uop_0_mem_size == 2'h1; // @[lsu.scala:321:49, :1954:26] wire [1:0] _ldq_ld_byte_mask_mask_T_4 = exe_tlb_vaddr_0[2:1]; // @[lsu.scala:321:49, :1954:56] wire [2:0] _ldq_ld_byte_mask_mask_T_5 = {_ldq_ld_byte_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _ldq_ld_byte_mask_mask_T_6 = 15'h3 << _ldq_ld_byte_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _ldq_ld_byte_mask_mask_T_7 = exe_tlb_uop_0_mem_size == 2'h2; // @[lsu.scala:321:49, :1955:26] wire _ldq_ld_byte_mask_mask_T_8 = exe_tlb_vaddr_0[2]; // @[lsu.scala:321:49, :1955:46] wire [7:0] _ldq_ld_byte_mask_mask_T_9 = _ldq_ld_byte_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _ldq_ld_byte_mask_mask_T_10 = &exe_tlb_uop_0_mem_size; // @[lsu.scala:321:49, :1956:26] wire [7:0] _ldq_ld_byte_mask_mask_T_12 = _ldq_ld_byte_mask_mask_T_7 ? _ldq_ld_byte_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _ldq_ld_byte_mask_mask_T_13 = _ldq_ld_byte_mask_mask_T_3 ? _ldq_ld_byte_mask_mask_T_6 : {7'h0, _ldq_ld_byte_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _ldq_ld_byte_mask_mask_T_14 = _ldq_ld_byte_mask_mask_T ? _ldq_ld_byte_mask_mask_T_2 : _ldq_ld_byte_mask_mask_T_13; // @[Mux.scala:126:16] assign ldq_ld_byte_mask_mask = _ldq_ld_byte_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _ldq_addr_is_uncacheable_T = ~exe_tlb_miss_0; // @[lsu.scala:321:49, :937:69, :975:76] wire _ldq_addr_is_uncacheable_T_1 = exe_tlb_uncacheable_0 & _ldq_addr_is_uncacheable_T; // @[lsu.scala:321:49, :975:{73,76}] wire _T_188 = will_fire_store_agen_0 \| will_fire_store_retry_0; // @[lsu.scala:471:41, :477:41, :981:35] wire [3:0] stq_idx = will_fire_store_agen_0 ? stq_incoming_idx_0 : _retry_queue_io_deq_bits_uop_stq_idx; // @[lsu.scala:321:49, :471:41, :533:27, :983:24] wire _stq_addr_valid_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :986:46] wire _stq_addr_valid_T_1 = _stq_addr_valid_T \| will_fire_store_retry_0; // @[lsu.scala:477:41, :986:{46,66}] wire _stq_addr_valid_T_2 = ~pf_st_0; // @[lsu.scala:321:49, :986:98] wire _stq_addr_valid_T_3 = _stq_addr_valid_T_1 & _stq_addr_valid_T_2; // @[lsu.scala:986:{66,95,98}] wire slow_wakeups_0_valid; // @[lsu.scala:1495:26] wire _fired_load_agen_exec_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :1041:83] wire _fired_load_agen_exec_T_1 = will_fire_load_agen_exec_0 & _fired_load_agen_exec_T; // @[lsu.scala:469:39, :1041:{80,83}] reg fired_load_agen_exec_REG; // @[lsu.scala:1041:51] wire fired_load_agen_exec_0 = fired_load_agen_exec_REG; // @[lsu.scala:321:49, :1041:51] wire _fired_load_agen_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :1042:83] wire _fired_load_agen_T_1 = will_fire_load_agen_0 & _fired_load_agen_T; // @[lsu.scala:470:41, :1042:{80,83}] reg fired_load_agen_REG; // @[lsu.scala:1042:51] wire fired_load_agen_0 = fired_load_agen_REG; // @[lsu.scala:321:49, :1042:51] wire _fired_store_agen_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :1043:83] wire _fired_store_agen_T_1 = will_fire_store_agen_0 & _fired_store_agen_T; // @[lsu.scala:471:41, :1043:{80,83}] reg fired_store_agen_REG; // @[lsu.scala:1043:51] wire fired_store_agen_0 = fired_store_agen_REG; // @[lsu.scala:321:49, :1043:51] reg fired_sfence_0; // @[lsu.scala:1044:37] reg fired_release_0; // @[lsu.scala:1045:37] wire do_release_search_0 = fired_release_0; // @[lsu.scala:321:49, :1045:37] wire lcam_is_release_0 = fired_release_0; // @[lsu.scala:321:49, :1045:37] wire [11:0] _GEN_388 = io_core_brupdate_b1_mispredict_mask_0 & _retry_queue_io_deq_bits_uop_br_mask; // @[util.scala:126:51] wire [11:0] _fired_load_retry_T; // @[util.scala:126:51] assign _fired_load_retry_T = _GEN_388; // @[util.scala:126:51] wire [11:0] _fired_store_retry_T; // @[util.scala:126:51] assign _fired_store_retry_T = _GEN_388; // @[util.scala:126:51] wire _fired_load_retry_T_1 = \|_fired_load_retry_T; // @[util.scala:126:{51,59}] wire _fired_load_retry_T_2 = _fired_load_retry_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _fired_load_retry_T_3 = ~_fired_load_retry_T_2; // @[util.scala:61:61] wire _fired_load_retry_T_4 = will_fire_load_retry_0 & _fired_load_retry_T_3; // @[lsu.scala:476:41, :1046:{79,82}] reg fired_load_retry_REG; // @[lsu.scala:1046:51] wire fired_load_retry_0 = fired_load_retry_REG; // @[lsu.scala:321:49, :1046:51] wire _fired_store_retry_T_1 = \|_fired_store_retry_T; // @[util.scala:126:{51,59}] wire _fired_store_retry_T_2 = _fired_store_retry_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _fired_store_retry_T_3 = ~_fired_store_retry_T_2; // @[util.scala:61:61] wire _fired_store_retry_T_4 = will_fire_store_retry_0 & _fired_store_retry_T_3; // @[lsu.scala:477:41, :1047:{79,82}] reg fired_store_retry_REG; // @[lsu.scala:1047:51] wire fired_store_retry_0 = fired_store_retry_REG; // @[lsu.scala:321:49, :1047:51] reg fired_store_commit_REG; // @[lsu.scala:1048:51] wire fired_store_commit_0 = fired_store_commit_REG; // @[lsu.scala:321:49, :1048:51] wire [11:0] _GEN_389 = io_core_brupdate_b1_mispredict_mask_0 & ldq_wakeup_e_bits_uop_br_mask; // @[util.scala:126:51] wire [11:0] _fired_load_wakeup_T; // @[util.scala:126:51] assign _fired_load_wakeup_T = _GEN_389; // @[util.scala:126:51] wire [11:0] _mem_ldq_wakeup_e_out_valid_T; // @[util.scala:126:51] assign _mem_ldq_wakeup_e_out_valid_T = _GEN_389; // @[util.scala:126:51] wire _fired_load_wakeup_T_1 = \|_fired_load_wakeup_T; // @[util.scala:126:{51,59}] wire _fired_load_wakeup_T_2 = _fired_load_wakeup_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _fired_load_wakeup_T_3 = ~_fired_load_wakeup_T_2; // @[util.scala:61:61] wire _fired_load_wakeup_T_4 = will_fire_load_wakeup_0 & _fired_load_wakeup_T_3; // @[lsu.scala:480:41, :1049:{79,82}] reg fired_load_wakeup_REG; // @[lsu.scala:1049:51] wire fired_load_wakeup_0 = fired_load_wakeup_REG; // @[lsu.scala:321:49, :1049:51] reg fired_hella_incoming_0; // @[lsu.scala:1050:37] reg fired_hella_wakeup_0; // @[lsu.scala:1051:37] wire [31:0] _mem_incoming_uop_WIRE_0_inst = mem_incoming_uop_out_inst; // @[util.scala:104:23] wire [31:0] _mem_incoming_uop_WIRE_0_debug_inst = mem_incoming_uop_out_debug_inst; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_rvc = mem_incoming_uop_out_is_rvc; // @[util.scala:104:23] wire [39:0] _mem_incoming_uop_WIRE_0_debug_pc = mem_incoming_uop_out_debug_pc; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_0 = mem_incoming_uop_out_iq_type_0; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_1 = mem_incoming_uop_out_iq_type_1; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_2 = mem_incoming_uop_out_iq_type_2; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_3 = mem_incoming_uop_out_iq_type_3; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_0 = mem_incoming_uop_out_fu_code_0; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_1 = mem_incoming_uop_out_fu_code_1; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_2 = mem_incoming_uop_out_fu_code_2; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_3 = mem_incoming_uop_out_fu_code_3; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_4 = mem_incoming_uop_out_fu_code_4; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_5 = mem_incoming_uop_out_fu_code_5; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_6 = mem_incoming_uop_out_fu_code_6; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_7 = mem_incoming_uop_out_fu_code_7; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_8 = mem_incoming_uop_out_fu_code_8; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_9 = mem_incoming_uop_out_fu_code_9; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_issued = mem_incoming_uop_out_iw_issued; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_issued_partial_agen = mem_incoming_uop_out_iw_issued_partial_agen; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_issued_partial_dgen = mem_incoming_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_iw_p1_speculative_child = mem_incoming_uop_out_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_iw_p2_speculative_child = mem_incoming_uop_out_iw_p2_speculative_child; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_p1_bypass_hint = mem_incoming_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_p2_bypass_hint = mem_incoming_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_p3_bypass_hint = mem_incoming_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23] wire [11:0] _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [1:0] _mem_incoming_uop_WIRE_0_dis_col_sel = mem_incoming_uop_out_dis_col_sel; // @[util.scala:104:23] wire [11:0] _mem_incoming_uop_WIRE_0_br_mask = mem_incoming_uop_out_br_mask; // @[util.scala:104:23] wire [3:0] _mem_incoming_uop_WIRE_0_br_tag = mem_incoming_uop_out_br_tag; // @[util.scala:104:23] wire [3:0] _mem_incoming_uop_WIRE_0_br_type = mem_incoming_uop_out_br_type; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_sfb = mem_incoming_uop_out_is_sfb; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_fence = mem_incoming_uop_out_is_fence; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_fencei = mem_incoming_uop_out_is_fencei; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_sfence = mem_incoming_uop_out_is_sfence; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_amo = mem_incoming_uop_out_is_amo; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_eret = mem_incoming_uop_out_is_eret; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_sys_pc2epc = mem_incoming_uop_out_is_sys_pc2epc; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_rocc = mem_incoming_uop_out_is_rocc; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_mov = mem_incoming_uop_out_is_mov; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_ftq_idx = mem_incoming_uop_out_ftq_idx; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_edge_inst = mem_incoming_uop_out_edge_inst; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_pc_lob = mem_incoming_uop_out_pc_lob; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_taken = mem_incoming_uop_out_taken; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_imm_rename = mem_incoming_uop_out_imm_rename; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_imm_sel = mem_incoming_uop_out_imm_sel; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_pimm = mem_incoming_uop_out_pimm; // @[util.scala:104:23] wire [19:0] _mem_incoming_uop_WIRE_0_imm_packed = mem_incoming_uop_out_imm_packed; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_op1_sel = mem_incoming_uop_out_op1_sel; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_op2_sel = mem_incoming_uop_out_op2_sel; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ldst = mem_incoming_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_wen = mem_incoming_uop_out_fp_ctrl_wen; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ren1 = mem_incoming_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ren2 = mem_incoming_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ren3 = mem_incoming_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_swap12 = mem_incoming_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_swap23 = mem_incoming_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_fp_ctrl_typeTagIn = mem_incoming_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_fp_ctrl_typeTagOut = mem_incoming_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_fromint = mem_incoming_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_toint = mem_incoming_uop_out_fp_ctrl_toint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_fastpipe = mem_incoming_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_fma = mem_incoming_uop_out_fp_ctrl_fma; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_div = mem_incoming_uop_out_fp_ctrl_div; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_sqrt = mem_incoming_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_wflags = mem_incoming_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_vec = mem_incoming_uop_out_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_rob_idx = mem_incoming_uop_out_rob_idx; // @[util.scala:104:23] wire [3:0] _mem_incoming_uop_WIRE_0_ldq_idx = mem_incoming_uop_out_ldq_idx; // @[util.scala:104:23] wire [3:0] _mem_incoming_uop_WIRE_0_stq_idx = mem_incoming_uop_out_stq_idx; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_rxq_idx = mem_incoming_uop_out_rxq_idx; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_pdst = mem_incoming_uop_out_pdst; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs1 = mem_incoming_uop_out_prs1; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs2 = mem_incoming_uop_out_prs2; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs3 = mem_incoming_uop_out_prs3; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_ppred = mem_incoming_uop_out_ppred; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_prs1_busy = mem_incoming_uop_out_prs1_busy; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_prs2_busy = mem_incoming_uop_out_prs2_busy; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_prs3_busy = mem_incoming_uop_out_prs3_busy; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_ppred_busy = mem_incoming_uop_out_ppred_busy; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_stale_pdst = mem_incoming_uop_out_stale_pdst; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_exception = mem_incoming_uop_out_exception; // @[util.scala:104:23] wire [63:0] _mem_incoming_uop_WIRE_0_exc_cause = mem_incoming_uop_out_exc_cause; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_mem_cmd = mem_incoming_uop_out_mem_cmd; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_mem_size = mem_incoming_uop_out_mem_size; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_mem_signed = mem_incoming_uop_out_mem_signed; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_uses_ldq = mem_incoming_uop_out_uses_ldq; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_uses_stq = mem_incoming_uop_out_uses_stq; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_unique = mem_incoming_uop_out_is_unique; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_flush_on_commit = mem_incoming_uop_out_flush_on_commit; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_csr_cmd = mem_incoming_uop_out_csr_cmd; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_ldst_is_rs1 = mem_incoming_uop_out_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_ldst = mem_incoming_uop_out_ldst; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs1 = mem_incoming_uop_out_lrs1; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs2 = mem_incoming_uop_out_lrs2; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs3 = mem_incoming_uop_out_lrs3; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_dst_rtype = mem_incoming_uop_out_dst_rtype; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs1_rtype = mem_incoming_uop_out_lrs1_rtype; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs2_rtype = mem_incoming_uop_out_lrs2_rtype; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_frs3_en = mem_incoming_uop_out_frs3_en; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fcn_dw = mem_incoming_uop_out_fcn_dw; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_fcn_op = mem_incoming_uop_out_fcn_op; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_val = mem_incoming_uop_out_fp_val; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_fp_rm = mem_incoming_uop_out_fp_rm; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_fp_typ = mem_incoming_uop_out_fp_typ; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_xcpt_pf_if = mem_incoming_uop_out_xcpt_pf_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_xcpt_ae_if = mem_incoming_uop_out_xcpt_ae_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_xcpt_ma_if = mem_incoming_uop_out_xcpt_ma_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_bp_debug_if = mem_incoming_uop_out_bp_debug_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_bp_xcpt_if = mem_incoming_uop_out_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_debug_fsrc = mem_incoming_uop_out_debug_fsrc; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_debug_tsrc = mem_incoming_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _mem_incoming_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _mem_incoming_uop_out_br_mask_T_1 = io_core_agen_0_bits_uop_br_mask_0 & _mem_incoming_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign mem_incoming_uop_out_br_mask = _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg [31:0] mem_incoming_uop_0_inst; // @[lsu.scala:1053:37] wire [31:0] w1_bits_out_uop_inst = mem_incoming_uop_0_inst; // @[util.scala:109:23] reg [31:0] mem_incoming_uop_0_debug_inst; // @[lsu.scala:1053:37] wire [31:0] w1_bits_out_uop_debug_inst = mem_incoming_uop_0_debug_inst; // @[util.scala:109:23] reg mem_incoming_uop_0_is_rvc; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_rvc = mem_incoming_uop_0_is_rvc; // @[util.scala:109:23] reg [39:0] mem_incoming_uop_0_debug_pc; // @[lsu.scala:1053:37] wire [39:0] w1_bits_out_uop_debug_pc = mem_incoming_uop_0_debug_pc; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_0; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_0 = mem_incoming_uop_0_iq_type_0; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_1 = mem_incoming_uop_0_iq_type_1; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_2; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_2 = mem_incoming_uop_0_iq_type_2; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_3; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_3 = mem_incoming_uop_0_iq_type_3; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_0; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_0 = mem_incoming_uop_0_fu_code_0; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_1 = mem_incoming_uop_0_fu_code_1; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_2; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_2 = mem_incoming_uop_0_fu_code_2; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_3; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_3 = mem_incoming_uop_0_fu_code_3; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_4; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_4 = mem_incoming_uop_0_fu_code_4; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_5; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_5 = mem_incoming_uop_0_fu_code_5; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_6; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_6 = mem_incoming_uop_0_fu_code_6; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_7; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_7 = mem_incoming_uop_0_fu_code_7; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_8; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_8 = mem_incoming_uop_0_fu_code_8; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_9; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_9 = mem_incoming_uop_0_fu_code_9; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_issued; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_issued = mem_incoming_uop_0_iw_issued; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_issued_partial_agen; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_issued_partial_agen = mem_incoming_uop_0_iw_issued_partial_agen; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_issued_partial_dgen; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_issued_partial_dgen = mem_incoming_uop_0_iw_issued_partial_dgen; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_iw_p1_speculative_child; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_iw_p1_speculative_child = mem_incoming_uop_0_iw_p1_speculative_child; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_iw_p2_speculative_child; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_iw_p2_speculative_child = mem_incoming_uop_0_iw_p2_speculative_child; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_p1_bypass_hint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_p1_bypass_hint = mem_incoming_uop_0_iw_p1_bypass_hint; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_p2_bypass_hint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_p2_bypass_hint = mem_incoming_uop_0_iw_p2_bypass_hint; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_p3_bypass_hint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_p3_bypass_hint = mem_incoming_uop_0_iw_p3_bypass_hint; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_dis_col_sel; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_dis_col_sel = mem_incoming_uop_0_dis_col_sel; // @[util.scala:109:23] reg [11:0] mem_incoming_uop_0_br_mask; // @[lsu.scala:1053:37] reg [3:0] mem_incoming_uop_0_br_tag; // @[lsu.scala:1053:37] wire [3:0] w1_bits_out_uop_br_tag = mem_incoming_uop_0_br_tag; // @[util.scala:109:23] reg [3:0] mem_incoming_uop_0_br_type; // @[lsu.scala:1053:37] wire [3:0] w1_bits_out_uop_br_type = mem_incoming_uop_0_br_type; // @[util.scala:109:23] reg mem_incoming_uop_0_is_sfb; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_sfb = mem_incoming_uop_0_is_sfb; // @[util.scala:109:23] reg mem_incoming_uop_0_is_fence; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_fence = mem_incoming_uop_0_is_fence; // @[util.scala:109:23] reg mem_incoming_uop_0_is_fencei; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_fencei = mem_incoming_uop_0_is_fencei; // @[util.scala:109:23] reg mem_incoming_uop_0_is_sfence; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_sfence = mem_incoming_uop_0_is_sfence; // @[util.scala:109:23] reg mem_incoming_uop_0_is_amo; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_amo = mem_incoming_uop_0_is_amo; // @[util.scala:109:23] reg mem_incoming_uop_0_is_eret; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_eret = mem_incoming_uop_0_is_eret; // @[util.scala:109:23] reg mem_incoming_uop_0_is_sys_pc2epc; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_sys_pc2epc = mem_incoming_uop_0_is_sys_pc2epc; // @[util.scala:109:23] reg mem_incoming_uop_0_is_rocc; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_rocc = mem_incoming_uop_0_is_rocc; // @[util.scala:109:23] reg mem_incoming_uop_0_is_mov; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_mov = mem_incoming_uop_0_is_mov; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_ftq_idx; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_ftq_idx = mem_incoming_uop_0_ftq_idx; // @[util.scala:109:23] reg mem_incoming_uop_0_edge_inst; // @[lsu.scala:1053:37] wire w1_bits_out_uop_edge_inst = mem_incoming_uop_0_edge_inst; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_pc_lob; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_pc_lob = mem_incoming_uop_0_pc_lob; // @[util.scala:109:23] reg mem_incoming_uop_0_taken; // @[lsu.scala:1053:37] wire w1_bits_out_uop_taken = mem_incoming_uop_0_taken; // @[util.scala:109:23] reg mem_incoming_uop_0_imm_rename; // @[lsu.scala:1053:37] wire w1_bits_out_uop_imm_rename = mem_incoming_uop_0_imm_rename; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_imm_sel; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_imm_sel = mem_incoming_uop_0_imm_sel; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_pimm; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_pimm = mem_incoming_uop_0_pimm; // @[util.scala:109:23] reg [19:0] mem_incoming_uop_0_imm_packed; // @[lsu.scala:1053:37] wire [19:0] w1_bits_out_uop_imm_packed = mem_incoming_uop_0_imm_packed; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_op1_sel; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_op1_sel = mem_incoming_uop_0_op1_sel; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_op2_sel; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_op2_sel = mem_incoming_uop_0_op2_sel; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ldst; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ldst = mem_incoming_uop_0_fp_ctrl_ldst; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_wen; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_wen = mem_incoming_uop_0_fp_ctrl_wen; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ren1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ren1 = mem_incoming_uop_0_fp_ctrl_ren1; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ren2; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ren2 = mem_incoming_uop_0_fp_ctrl_ren2; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ren3; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ren3 = mem_incoming_uop_0_fp_ctrl_ren3; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_swap12; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_swap12 = mem_incoming_uop_0_fp_ctrl_swap12; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_swap23; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_swap23 = mem_incoming_uop_0_fp_ctrl_swap23; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_fp_ctrl_typeTagIn = mem_incoming_uop_0_fp_ctrl_typeTagIn; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_fp_ctrl_typeTagOut = mem_incoming_uop_0_fp_ctrl_typeTagOut; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_fromint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_fromint = mem_incoming_uop_0_fp_ctrl_fromint; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_toint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_toint = mem_incoming_uop_0_fp_ctrl_toint; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_fastpipe = mem_incoming_uop_0_fp_ctrl_fastpipe; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_fma; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_fma = mem_incoming_uop_0_fp_ctrl_fma; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_div; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_div = mem_incoming_uop_0_fp_ctrl_div; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_sqrt; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_sqrt = mem_incoming_uop_0_fp_ctrl_sqrt; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_wflags; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_wflags = mem_incoming_uop_0_fp_ctrl_wflags; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_vec; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_vec = mem_incoming_uop_0_fp_ctrl_vec; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_rob_idx; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_rob_idx = mem_incoming_uop_0_rob_idx; // @[util.scala:109:23] reg [3:0] mem_incoming_uop_0_ldq_idx; // @[lsu.scala:1053:37] wire [3:0] w1_bits_out_uop_ldq_idx = mem_incoming_uop_0_ldq_idx; // @[util.scala:109:23] reg [3:0] mem_incoming_uop_0_stq_idx; // @[lsu.scala:1053:37] wire [3:0] w1_bits_out_uop_stq_idx = mem_incoming_uop_0_stq_idx; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_rxq_idx; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_rxq_idx = mem_incoming_uop_0_rxq_idx; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_pdst; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_pdst = mem_incoming_uop_0_pdst; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_prs1; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_prs1 = mem_incoming_uop_0_prs1; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_prs2; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_prs2 = mem_incoming_uop_0_prs2; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_prs3; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_prs3 = mem_incoming_uop_0_prs3; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_ppred; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_ppred = mem_incoming_uop_0_ppred; // @[util.scala:109:23] reg mem_incoming_uop_0_prs1_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_prs1_busy = mem_incoming_uop_0_prs1_busy; // @[util.scala:109:23] reg mem_incoming_uop_0_prs2_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_prs2_busy = mem_incoming_uop_0_prs2_busy; // @[util.scala:109:23] reg mem_incoming_uop_0_prs3_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_prs3_busy = mem_incoming_uop_0_prs3_busy; // @[util.scala:109:23] reg mem_incoming_uop_0_ppred_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_ppred_busy = mem_incoming_uop_0_ppred_busy; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_stale_pdst; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_stale_pdst = mem_incoming_uop_0_stale_pdst; // @[util.scala:109:23] reg mem_incoming_uop_0_exception; // @[lsu.scala:1053:37] wire w1_bits_out_uop_exception = mem_incoming_uop_0_exception; // @[util.scala:109:23] reg [63:0] mem_incoming_uop_0_exc_cause; // @[lsu.scala:1053:37] wire [63:0] w1_bits_out_uop_exc_cause = mem_incoming_uop_0_exc_cause; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_mem_cmd; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_mem_cmd = mem_incoming_uop_0_mem_cmd; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_mem_size; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_mem_size = mem_incoming_uop_0_mem_size; // @[util.scala:109:23] reg mem_incoming_uop_0_mem_signed; // @[lsu.scala:1053:37] wire w1_bits_out_uop_mem_signed = mem_incoming_uop_0_mem_signed; // @[util.scala:109:23] reg mem_incoming_uop_0_uses_ldq; // @[lsu.scala:1053:37] wire w1_bits_out_uop_uses_ldq = mem_incoming_uop_0_uses_ldq; // @[util.scala:109:23] reg mem_incoming_uop_0_uses_stq; // @[lsu.scala:1053:37] wire w1_bits_out_uop_uses_stq = mem_incoming_uop_0_uses_stq; // @[util.scala:109:23] reg mem_incoming_uop_0_is_unique; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_unique = mem_incoming_uop_0_is_unique; // @[util.scala:109:23] reg mem_incoming_uop_0_flush_on_commit; // @[lsu.scala:1053:37] wire w1_bits_out_uop_flush_on_commit = mem_incoming_uop_0_flush_on_commit; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_csr_cmd; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_csr_cmd = mem_incoming_uop_0_csr_cmd; // @[util.scala:109:23] reg mem_incoming_uop_0_ldst_is_rs1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_ldst_is_rs1 = mem_incoming_uop_0_ldst_is_rs1; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_ldst; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_ldst = mem_incoming_uop_0_ldst; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_lrs1; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_lrs1 = mem_incoming_uop_0_lrs1; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_lrs2; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_lrs2 = mem_incoming_uop_0_lrs2; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_lrs3; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_lrs3 = mem_incoming_uop_0_lrs3; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_dst_rtype; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_dst_rtype = mem_incoming_uop_0_dst_rtype; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_lrs1_rtype; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_lrs1_rtype = mem_incoming_uop_0_lrs1_rtype; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_lrs2_rtype; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_lrs2_rtype = mem_incoming_uop_0_lrs2_rtype; // @[util.scala:109:23] reg mem_incoming_uop_0_frs3_en; // @[lsu.scala:1053:37] wire w1_bits_out_uop_frs3_en = mem_incoming_uop_0_frs3_en; // @[util.scala:109:23] reg mem_incoming_uop_0_fcn_dw; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fcn_dw = mem_incoming_uop_0_fcn_dw; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_fcn_op; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_fcn_op = mem_incoming_uop_0_fcn_op; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_val; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_val = mem_incoming_uop_0_fp_val; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_fp_rm; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_fp_rm = mem_incoming_uop_0_fp_rm; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_fp_typ; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_fp_typ = mem_incoming_uop_0_fp_typ; // @[util.scala:109:23] reg mem_incoming_uop_0_xcpt_pf_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_xcpt_pf_if = mem_incoming_uop_0_xcpt_pf_if; // @[util.scala:109:23] reg mem_incoming_uop_0_xcpt_ae_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_xcpt_ae_if = mem_incoming_uop_0_xcpt_ae_if; // @[util.scala:109:23] reg mem_incoming_uop_0_xcpt_ma_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_xcpt_ma_if = mem_incoming_uop_0_xcpt_ma_if; // @[util.scala:109:23] reg mem_incoming_uop_0_bp_debug_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_bp_debug_if = mem_incoming_uop_0_bp_debug_if; // @[util.scala:109:23] reg mem_incoming_uop_0_bp_xcpt_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_bp_xcpt_if = mem_incoming_uop_0_bp_xcpt_if; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_debug_fsrc; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_debug_fsrc = mem_incoming_uop_0_debug_fsrc; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_debug_tsrc; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_debug_tsrc = mem_incoming_uop_0_debug_tsrc; // @[util.scala:109:23] wire _mem_ldq_incoming_e_out_valid_T_4; // @[util.scala:116:31] wire _mem_ldq_incoming_e_WIRE_0_valid = mem_ldq_incoming_e_out_valid; // @[util.scala:114:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_inst = mem_ldq_incoming_e_out_bits_uop_inst; // @[util.scala:114:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_ldq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_ldq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_ldq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_0 = mem_ldq_incoming_e_out_bits_uop_iq_type_0; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_1 = mem_ldq_incoming_e_out_bits_uop_iq_type_1; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_2 = mem_ldq_incoming_e_out_bits_uop_iq_type_2; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_3 = mem_ldq_incoming_e_out_bits_uop_iq_type_3; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_0 = mem_ldq_incoming_e_out_bits_uop_fu_code_0; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_1 = mem_ldq_incoming_e_out_bits_uop_fu_code_1; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_2 = mem_ldq_incoming_e_out_bits_uop_fu_code_2; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_3 = mem_ldq_incoming_e_out_bits_uop_fu_code_3; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_4 = mem_ldq_incoming_e_out_bits_uop_fu_code_4; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_5 = mem_ldq_incoming_e_out_bits_uop_fu_code_5; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_6 = mem_ldq_incoming_e_out_bits_uop_fu_code_6; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_7 = mem_ldq_incoming_e_out_bits_uop_fu_code_7; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_8 = mem_ldq_incoming_e_out_bits_uop_fu_code_8; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_9 = mem_ldq_incoming_e_out_bits_uop_fu_code_9; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_issued = mem_ldq_incoming_e_out_bits_uop_iw_issued; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_agen = mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_dgen = mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p1_speculative_child = mem_ldq_incoming_e_out_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p2_speculative_child = mem_ldq_incoming_e_out_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p1_bypass_hint = mem_ldq_incoming_e_out_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p2_bypass_hint = mem_ldq_incoming_e_out_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p3_bypass_hint = mem_ldq_incoming_e_out_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [11:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_dis_col_sel = mem_ldq_incoming_e_out_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [11:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_mask = mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_tag = mem_ldq_incoming_e_out_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_type = mem_ldq_incoming_e_out_bits_uop_br_type; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_ldq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fence = mem_ldq_incoming_e_out_bits_uop_is_fence; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_ldq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sfence = mem_ldq_incoming_e_out_bits_uop_is_sfence; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_amo = mem_ldq_incoming_e_out_bits_uop_is_amo; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_eret = mem_ldq_incoming_e_out_bits_uop_is_eret; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_rocc = mem_ldq_incoming_e_out_bits_uop_is_rocc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_mov = mem_ldq_incoming_e_out_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_ldq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_ldq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_ldq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_taken = mem_ldq_incoming_e_out_bits_uop_taken; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_rename = mem_ldq_incoming_e_out_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_sel = mem_ldq_incoming_e_out_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pimm = mem_ldq_incoming_e_out_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_ldq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_op1_sel = mem_ldq_incoming_e_out_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_op2_sel = mem_ldq_incoming_e_out_bits_uop_op2_sel; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ldst = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wen = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren1 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren2 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren3 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap12 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap23 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagIn = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagOut = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fromint = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_toint = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fastpipe = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fma = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_div = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_sqrt = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wflags = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_vec = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_ldq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_ldq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_ldq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_ldq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pdst = mem_ldq_incoming_e_out_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1 = mem_ldq_incoming_e_out_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2 = mem_ldq_incoming_e_out_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3 = mem_ldq_incoming_e_out_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred = mem_ldq_incoming_e_out_bits_uop_ppred; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_ldq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_ldq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_ldq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_ldq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_ldq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_exception = mem_ldq_incoming_e_out_bits_uop_exception; // @[util.scala:114:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_ldq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_ldq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_size = mem_ldq_incoming_e_out_bits_uop_mem_size; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_ldq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_ldq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_ldq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_unique = mem_ldq_incoming_e_out_bits_uop_is_unique; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_ldq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_csr_cmd = mem_ldq_incoming_e_out_bits_uop_csr_cmd; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst = mem_ldq_incoming_e_out_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_ldq_incoming_e_out_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_ldq_incoming_e_out_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_ldq_incoming_e_out_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_ldq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_ldq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_ldq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_ldq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fcn_dw = mem_ldq_incoming_e_out_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fcn_op = mem_ldq_incoming_e_out_bits_uop_fcn_op; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_val = mem_ldq_incoming_e_out_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_rm = mem_ldq_incoming_e_out_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_typ = mem_ldq_incoming_e_out_bits_uop_fp_typ; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_ldq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_ldq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_ldq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_valid = mem_ldq_incoming_e_out_bits_addr_valid; // @[util.scala:114:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_addr_bits = mem_ldq_incoming_e_out_bits_addr_bits; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_ldq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_uncacheable = mem_ldq_incoming_e_out_bits_addr_is_uncacheable; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_executed = mem_ldq_incoming_e_out_bits_executed; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_succeeded = mem_ldq_incoming_e_out_bits_succeeded; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_order_fail = mem_ldq_incoming_e_out_bits_order_fail; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_observed = mem_ldq_incoming_e_out_bits_observed; // @[util.scala:114:23] wire [15:0] _mem_ldq_incoming_e_WIRE_0_bits_st_dep_mask = mem_ldq_incoming_e_out_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] _mem_ldq_incoming_e_WIRE_0_bits_ld_byte_mask = mem_ldq_incoming_e_out_bits_ld_byte_mask; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_forward_std_val = mem_ldq_incoming_e_out_bits_forward_std_val; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_forward_stq_idx = mem_ldq_incoming_e_out_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_debug_wb_data = mem_ldq_incoming_e_out_bits_debug_wb_data; // @[util.scala:114:23] wire [11:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1 = ldq_incoming_e_0_bits_uop_br_mask & _mem_ldq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_ldq_incoming_e_out_bits_uop_br_mask = _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [11:0] _mem_ldq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & ldq_incoming_e_0_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_ldq_incoming_e_out_valid_T_1 = \|_mem_ldq_incoming_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_ldq_incoming_e_out_valid_T_2 = _mem_ldq_incoming_e_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_ldq_incoming_e_out_valid_T_3 = ~_mem_ldq_incoming_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_ldq_incoming_e_out_valid_T_4 = ldq_incoming_e_0_valid & _mem_ldq_incoming_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_ldq_incoming_e_out_valid = _mem_ldq_incoming_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_ldq_incoming_e_0_valid; // @[lsu.scala:1054:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_inst; // @[lsu.scala:1054:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:1054:37] reg [39:0] mem_ldq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_0; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_1; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_2; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_3; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_0; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_1; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_2; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_3; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_4; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_5; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_6; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_7; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_8; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_9; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_issued; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_dis_col_sel; // @[lsu.scala:1054:37] reg [11:0] mem_ldq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_br_type; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_sfence; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_eret; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_rocc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_mov; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_taken; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_imm_rename; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_imm_sel; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_pimm; // @[lsu.scala:1054:37] reg [19:0] mem_ldq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_op1_sel; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_op2_sel; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_exception; // @[lsu.scala:1054:37] reg [63:0] mem_ldq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_csr_cmd; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fcn_dw; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_fcn_op; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_fp_rm; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_fp_typ; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_addr_valid; // @[lsu.scala:1054:37] reg [39:0] mem_ldq_incoming_e_0_bits_addr_bits; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_addr_is_uncacheable; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_executed; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_succeeded; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_order_fail; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_observed; // @[lsu.scala:1054:37] reg [15:0] mem_ldq_incoming_e_0_bits_st_dep_mask; // @[lsu.scala:1054:37] reg [7:0] mem_ldq_incoming_e_0_bits_ld_byte_mask; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_forward_std_val; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_forward_stq_idx; // @[lsu.scala:1054:37] reg [63:0] mem_ldq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:1054:37] wire _mem_stq_incoming_e_out_valid_T_4; // @[util.scala:116:31] wire _mem_stq_incoming_e_WIRE_0_valid = mem_stq_incoming_e_out_valid; // @[util.scala:114:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_inst = mem_stq_incoming_e_out_bits_uop_inst; // @[util.scala:114:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_stq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_stq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_stq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_0 = mem_stq_incoming_e_out_bits_uop_iq_type_0; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_1 = mem_stq_incoming_e_out_bits_uop_iq_type_1; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_2 = mem_stq_incoming_e_out_bits_uop_iq_type_2; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_3 = mem_stq_incoming_e_out_bits_uop_iq_type_3; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_0 = mem_stq_incoming_e_out_bits_uop_fu_code_0; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_1 = mem_stq_incoming_e_out_bits_uop_fu_code_1; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_2 = mem_stq_incoming_e_out_bits_uop_fu_code_2; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_3 = mem_stq_incoming_e_out_bits_uop_fu_code_3; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_4 = mem_stq_incoming_e_out_bits_uop_fu_code_4; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_5 = mem_stq_incoming_e_out_bits_uop_fu_code_5; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_6 = mem_stq_incoming_e_out_bits_uop_fu_code_6; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_7 = mem_stq_incoming_e_out_bits_uop_fu_code_7; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_8 = mem_stq_incoming_e_out_bits_uop_fu_code_8; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_9 = mem_stq_incoming_e_out_bits_uop_fu_code_9; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_issued = mem_stq_incoming_e_out_bits_uop_iw_issued; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_agen = mem_stq_incoming_e_out_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_dgen = mem_stq_incoming_e_out_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p1_speculative_child = mem_stq_incoming_e_out_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p2_speculative_child = mem_stq_incoming_e_out_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p1_bypass_hint = mem_stq_incoming_e_out_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p2_bypass_hint = mem_stq_incoming_e_out_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p3_bypass_hint = mem_stq_incoming_e_out_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [11:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_dis_col_sel = mem_stq_incoming_e_out_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [11:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_mask = mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_tag = mem_stq_incoming_e_out_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_type = mem_stq_incoming_e_out_bits_uop_br_type; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_stq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fence = mem_stq_incoming_e_out_bits_uop_is_fence; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_stq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sfence = mem_stq_incoming_e_out_bits_uop_is_sfence; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_amo = mem_stq_incoming_e_out_bits_uop_is_amo; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_eret = mem_stq_incoming_e_out_bits_uop_is_eret; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_rocc = mem_stq_incoming_e_out_bits_uop_is_rocc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_mov = mem_stq_incoming_e_out_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_stq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_stq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_stq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_taken = mem_stq_incoming_e_out_bits_uop_taken; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_imm_rename = mem_stq_incoming_e_out_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_imm_sel = mem_stq_incoming_e_out_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pimm = mem_stq_incoming_e_out_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] _mem_stq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_stq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_op1_sel = mem_stq_incoming_e_out_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_op2_sel = mem_stq_incoming_e_out_bits_uop_op2_sel; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ldst = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wen = mem_stq_incoming_e_out_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren1 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren2 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren3 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap12 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap23 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagIn = mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagOut = mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fromint = mem_stq_incoming_e_out_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_toint = mem_stq_incoming_e_out_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fastpipe = mem_stq_incoming_e_out_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fma = mem_stq_incoming_e_out_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_div = mem_stq_incoming_e_out_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_sqrt = mem_stq_incoming_e_out_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wflags = mem_stq_incoming_e_out_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_vec = mem_stq_incoming_e_out_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_stq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_stq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_stq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_stq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pdst = mem_stq_incoming_e_out_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs1 = mem_stq_incoming_e_out_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs2 = mem_stq_incoming_e_out_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs3 = mem_stq_incoming_e_out_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ppred = mem_stq_incoming_e_out_bits_uop_ppred; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_stq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_stq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_stq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_stq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_stq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_exception = mem_stq_incoming_e_out_bits_uop_exception; // @[util.scala:114:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_stq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_stq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_size = mem_stq_incoming_e_out_bits_uop_mem_size; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_stq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_stq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_stq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_unique = mem_stq_incoming_e_out_bits_uop_is_unique; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_stq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_csr_cmd = mem_stq_incoming_e_out_bits_uop_csr_cmd; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_stq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldst = mem_stq_incoming_e_out_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_stq_incoming_e_out_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_stq_incoming_e_out_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_stq_incoming_e_out_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_stq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_stq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_stq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_stq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fcn_dw = mem_stq_incoming_e_out_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fcn_op = mem_stq_incoming_e_out_bits_uop_fcn_op; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_val = mem_stq_incoming_e_out_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_rm = mem_stq_incoming_e_out_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_typ = mem_stq_incoming_e_out_bits_uop_fp_typ; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_stq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_stq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_stq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_stq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_stq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_stq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_stq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_valid = mem_stq_incoming_e_out_bits_addr_valid; // @[util.scala:114:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_addr_bits = mem_stq_incoming_e_out_bits_addr_bits; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_stq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_data_valid = mem_stq_incoming_e_out_bits_data_valid; // @[util.scala:114:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_data_bits = mem_stq_incoming_e_out_bits_data_bits; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_committed = mem_stq_incoming_e_out_bits_committed; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_succeeded = mem_stq_incoming_e_out_bits_succeeded; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_can_execute = mem_stq_incoming_e_out_bits_can_execute; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_cleared = mem_stq_incoming_e_out_bits_cleared; // @[util.scala:114:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_debug_wb_data = mem_stq_incoming_e_out_bits_debug_wb_data; // @[util.scala:114:23] wire [11:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_stq_incoming_e_out_bits_uop_br_mask_T_1 = stq_incoming_e_0_bits_uop_br_mask & _mem_stq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_stq_incoming_e_out_bits_uop_br_mask = _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [11:0] _mem_stq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & stq_incoming_e_0_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_stq_incoming_e_out_valid_T_1 = \|_mem_stq_incoming_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_stq_incoming_e_out_valid_T_2 = _mem_stq_incoming_e_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_stq_incoming_e_out_valid_T_3 = ~_mem_stq_incoming_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_stq_incoming_e_out_valid_T_4 = stq_incoming_e_0_valid & _mem_stq_incoming_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_stq_incoming_e_out_valid = _mem_stq_incoming_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_stq_incoming_e_0_valid; // @[lsu.scala:1055:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_inst; // @[lsu.scala:1055:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:1055:37] reg [39:0] mem_stq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_0; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_1; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_2; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_3; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_0; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_1; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_2; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_3; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_4; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_5; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_6; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_7; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_8; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_9; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_issued; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_dis_col_sel; // @[lsu.scala:1055:37] reg [11:0] mem_stq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:1055:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:1055:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_br_type; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_sfence; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_eret; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_rocc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_mov; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_taken; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_imm_rename; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_imm_sel; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_pimm; // @[lsu.scala:1055:37] reg [19:0] mem_stq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_op1_sel; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_op2_sel; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:1055:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:1055:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_exception; // @[lsu.scala:1055:37] reg [63:0] mem_stq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_csr_cmd; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fcn_dw; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_fcn_op; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_fp_rm; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_fp_typ; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:1055:37] reg [39:0] mem_stq_incoming_e_0_bits_addr_bits; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_data_valid; // @[lsu.scala:1055:37] reg [63:0] mem_stq_incoming_e_0_bits_data_bits; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_committed; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_succeeded; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_can_execute; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_cleared; // @[lsu.scala:1055:37] reg [63:0] mem_stq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:1055:37] wire _mem_ldq_wakeup_e_out_valid_T_4; // @[util.scala:116:31] wire [11:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] mem_ldq_wakeup_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_valid; // @[util.scala:114:23] wire [11:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1 = ldq_wakeup_e_bits_uop_br_mask & _mem_ldq_wakeup_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_ldq_wakeup_e_out_bits_uop_br_mask = _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire _mem_ldq_wakeup_e_out_valid_T_1 = \|_mem_ldq_wakeup_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_ldq_wakeup_e_out_valid_T_2 = _mem_ldq_wakeup_e_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_ldq_wakeup_e_out_valid_T_3 = ~_mem_ldq_wakeup_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_ldq_wakeup_e_out_valid_T_4 = ldq_wakeup_e_valid & _mem_ldq_wakeup_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_ldq_wakeup_e_out_valid = _mem_ldq_wakeup_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_ldq_wakeup_e_valid; // @[lsu.scala:1056:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_inst; // @[lsu.scala:1056:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_debug_inst; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:1056:37] reg [39:0] mem_ldq_wakeup_e_bits_uop_debug_pc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_0; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_1; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_2; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_3; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_0; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_1; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_2; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_3; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_4; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_5; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_6; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_7; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_8; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_9; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_issued; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_dis_col_sel; // @[lsu.scala:1056:37] reg [11:0] mem_ldq_wakeup_e_bits_uop_br_mask; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_br_tag; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_br_type; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_sfence; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_eret; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_rocc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_mov; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ftq_idx; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_pc_lob; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_imm_rename; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_imm_sel; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_pimm; // @[lsu.scala:1056:37] reg [19:0] mem_ldq_wakeup_e_bits_uop_imm_packed; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_op1_sel; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_op2_sel; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_rob_idx; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_ldq_idx; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_stq_idx; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_rxq_idx; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_pdst; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs1; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs2; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs3; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ppred; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_stale_pdst; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:1056:37] reg [63:0] mem_ldq_wakeup_e_bits_uop_exc_cause; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_mem_cmd; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_mem_size; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_csr_cmd; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_ldst; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs1; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs2; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs3; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_dst_rtype; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs1_rtype; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs2_rtype; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fcn_dw; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_fcn_op; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_fp_rm; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_fp_typ; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_debug_fsrc; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_debug_tsrc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:1056:37] reg [39:0] mem_ldq_wakeup_e_bits_addr_bits; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:1056:37] reg [15:0] mem_ldq_wakeup_e_bits_st_dep_mask; // @[lsu.scala:1056:37] reg [7:0] mem_ldq_wakeup_e_bits_ld_byte_mask; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_forward_stq_idx; // @[lsu.scala:1056:37] reg [63:0] mem_ldq_wakeup_e_bits_debug_wb_data; // @[lsu.scala:1056:37] wire [31:0] mem_ldq_retry_e_out_bits_uop_inst = mem_ldq_retry_e_e_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_ldq_retry_e_out_bits_uop_debug_inst = mem_ldq_retry_e_e_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_rvc = mem_ldq_retry_e_e_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_ldq_retry_e_out_bits_uop_debug_pc = mem_ldq_retry_e_e_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_0 = mem_ldq_retry_e_e_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_1 = mem_ldq_retry_e_e_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_2 = mem_ldq_retry_e_e_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_3 = mem_ldq_retry_e_e_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_0 = mem_ldq_retry_e_e_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_1 = mem_ldq_retry_e_e_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_2 = mem_ldq_retry_e_e_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_3 = mem_ldq_retry_e_e_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_4 = mem_ldq_retry_e_e_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_5 = mem_ldq_retry_e_e_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_6 = mem_ldq_retry_e_e_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_7 = mem_ldq_retry_e_e_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_8 = mem_ldq_retry_e_e_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_9 = mem_ldq_retry_e_e_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_issued = mem_ldq_retry_e_e_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_issued_partial_agen = mem_ldq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_issued_partial_dgen = mem_ldq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_iw_p1_speculative_child = mem_ldq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_iw_p2_speculative_child = mem_ldq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_p1_bypass_hint = mem_ldq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_p2_bypass_hint = mem_ldq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_p3_bypass_hint = mem_ldq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_dis_col_sel = mem_ldq_retry_e_e_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_br_tag = mem_ldq_retry_e_e_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_br_type = mem_ldq_retry_e_e_bits_uop_br_type; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_sfb = mem_ldq_retry_e_e_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_fence = mem_ldq_retry_e_e_bits_uop_is_fence; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_fencei = mem_ldq_retry_e_e_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_sfence = mem_ldq_retry_e_e_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_amo = mem_ldq_retry_e_e_bits_uop_is_amo; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_eret = mem_ldq_retry_e_e_bits_uop_is_eret; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_sys_pc2epc = mem_ldq_retry_e_e_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_rocc = mem_ldq_retry_e_e_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_mov = mem_ldq_retry_e_e_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ftq_idx = mem_ldq_retry_e_e_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_edge_inst = mem_ldq_retry_e_e_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_pc_lob = mem_ldq_retry_e_e_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_taken = mem_ldq_retry_e_e_bits_uop_taken; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_imm_rename = mem_ldq_retry_e_e_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_imm_sel = mem_ldq_retry_e_e_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_pimm = mem_ldq_retry_e_e_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_ldq_retry_e_out_bits_uop_imm_packed = mem_ldq_retry_e_e_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_op1_sel = mem_ldq_retry_e_e_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_op2_sel = mem_ldq_retry_e_e_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ldst = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_wen = mem_ldq_retry_e_e_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ren1 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ren2 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ren3 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_swap12 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_swap23 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_fp_ctrl_typeTagIn = mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_fp_ctrl_typeTagOut = mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_fromint = mem_ldq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_toint = mem_ldq_retry_e_e_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_fastpipe = mem_ldq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_fma = mem_ldq_retry_e_e_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_div = mem_ldq_retry_e_e_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_sqrt = mem_ldq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_wflags = mem_ldq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_vec = mem_ldq_retry_e_e_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_rob_idx = mem_ldq_retry_e_e_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_ldq_idx = mem_ldq_retry_e_e_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_stq_idx = mem_ldq_retry_e_e_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_rxq_idx = mem_ldq_retry_e_e_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_pdst = mem_ldq_retry_e_e_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs1 = mem_ldq_retry_e_e_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs2 = mem_ldq_retry_e_e_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs3 = mem_ldq_retry_e_e_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ppred = mem_ldq_retry_e_e_bits_uop_ppred; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_prs1_busy = mem_ldq_retry_e_e_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_prs2_busy = mem_ldq_retry_e_e_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_prs3_busy = mem_ldq_retry_e_e_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_ppred_busy = mem_ldq_retry_e_e_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_stale_pdst = mem_ldq_retry_e_e_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_exception = mem_ldq_retry_e_e_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_ldq_retry_e_out_bits_uop_exc_cause = mem_ldq_retry_e_e_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_mem_cmd = mem_ldq_retry_e_e_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_mem_size = mem_ldq_retry_e_e_bits_uop_mem_size; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_mem_signed = mem_ldq_retry_e_e_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_uses_ldq = mem_ldq_retry_e_e_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_uses_stq = mem_ldq_retry_e_e_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_unique = mem_ldq_retry_e_e_bits_uop_is_unique; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_flush_on_commit = mem_ldq_retry_e_e_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_csr_cmd = mem_ldq_retry_e_e_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_ldst_is_rs1 = mem_ldq_retry_e_e_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_ldst = mem_ldq_retry_e_e_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs1 = mem_ldq_retry_e_e_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs2 = mem_ldq_retry_e_e_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs3 = mem_ldq_retry_e_e_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_dst_rtype = mem_ldq_retry_e_e_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs1_rtype = mem_ldq_retry_e_e_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs2_rtype = mem_ldq_retry_e_e_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_frs3_en = mem_ldq_retry_e_e_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fcn_dw = mem_ldq_retry_e_e_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_fcn_op = mem_ldq_retry_e_e_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_val = mem_ldq_retry_e_e_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_fp_rm = mem_ldq_retry_e_e_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_fp_typ = mem_ldq_retry_e_e_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_pf_if = mem_ldq_retry_e_e_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ae_if = mem_ldq_retry_e_e_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ma_if = mem_ldq_retry_e_e_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_bp_debug_if = mem_ldq_retry_e_e_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_bp_xcpt_if = mem_ldq_retry_e_e_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_debug_fsrc = mem_ldq_retry_e_e_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_debug_tsrc = mem_ldq_retry_e_e_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_addr_valid = mem_ldq_retry_e_e_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_ldq_retry_e_out_bits_addr_bits = mem_ldq_retry_e_e_bits_addr_bits; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_addr_is_virtual = mem_ldq_retry_e_e_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_addr_is_uncacheable = mem_ldq_retry_e_e_bits_addr_is_uncacheable; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_executed = mem_ldq_retry_e_e_bits_executed; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_succeeded = mem_ldq_retry_e_e_bits_succeeded; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_order_fail = mem_ldq_retry_e_e_bits_order_fail; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_observed = mem_ldq_retry_e_e_bits_observed; // @[util.scala:114:23] wire [15:0] mem_ldq_retry_e_out_bits_st_dep_mask = mem_ldq_retry_e_e_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] mem_ldq_retry_e_out_bits_ld_byte_mask = mem_ldq_retry_e_e_bits_ld_byte_mask; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_forward_std_val = mem_ldq_retry_e_e_bits_forward_std_val; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_forward_stq_idx = mem_ldq_retry_e_e_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] mem_ldq_retry_e_out_bits_debug_wb_data = mem_ldq_retry_e_e_bits_debug_wb_data; // @[util.scala:114:23] wire [11:0] mem_ldq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_valid; // @[lsu.scala:233:17] assign mem_ldq_retry_e_e_valid = _GEN_25[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :234:32, :387:15, :533:27] assign mem_ldq_retry_e_e_bits_uop_inst = _GEN_76[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_inst = _GEN_77[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_rvc = _GEN_78[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_pc = _GEN_79[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_0 = _GEN_80[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_1 = _GEN_81[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_2 = _GEN_82[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_3 = _GEN_83[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_0 = _GEN_84[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_1 = _GEN_85[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_2 = _GEN_86[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_3 = _GEN_87[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_4 = _GEN_88[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_5 = _GEN_89[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_6 = _GEN_90[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_7 = _GEN_91[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_8 = _GEN_92[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_9 = _GEN_93[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_issued = _GEN_94[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_95[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_96[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_97[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_98[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_99[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_100[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_101[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_dis_col_sel = _GEN_102[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_br_mask = _GEN_103[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_br_tag = _GEN_104[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_br_type = _GEN_105[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_sfb = _GEN_106[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_fence = _GEN_107[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_fencei = _GEN_108[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_sfence = _GEN_109[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_amo = _GEN_110[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_eret = _GEN_111[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_112[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_rocc = _GEN_113[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_mov = _GEN_114[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ftq_idx = _GEN_115[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_edge_inst = _GEN_116[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_pc_lob = _GEN_117[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_taken = _GEN_118[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_imm_rename = _GEN_119[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_imm_sel = _GEN_120[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_pimm = _GEN_121[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_imm_packed = _GEN_122[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_op1_sel = _GEN_123[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_op2_sel = _GEN_124[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_125[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_126[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_127[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_128[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_129[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_130[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_131[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_132[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_133[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_134[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_135[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_136[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_137[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_138[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_139[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_140[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_141[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_rob_idx = _GEN_142[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ldq_idx = _GEN_143[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_stq_idx = _GEN_144[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_rxq_idx = _GEN_145[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_pdst = _GEN_146[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs1 = _GEN_147[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs2 = _GEN_148[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs3 = _GEN_149[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ppred = _GEN_150[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs1_busy = _GEN_151[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs2_busy = _GEN_152[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs3_busy = _GEN_153[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ppred_busy = _GEN_154[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_stale_pdst = _GEN_155[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_exception = _GEN_156[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_exc_cause = _GEN_157[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_mem_cmd = _GEN_158[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_mem_size = _GEN_159[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_mem_signed = _GEN_160[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_uses_ldq = _GEN_161[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_uses_stq = _GEN_162[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_unique = _GEN_163[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_flush_on_commit = _GEN_164[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_csr_cmd = _GEN_165[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_166[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ldst = _GEN_167[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs1 = _GEN_168[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs2 = _GEN_169[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs3 = _GEN_170[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_dst_rtype = _GEN_171[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs1_rtype = _GEN_172[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs2_rtype = _GEN_173[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_frs3_en = _GEN_174[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fcn_dw = _GEN_175[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fcn_op = _GEN_176[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_val = _GEN_177[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_rm = _GEN_178[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_typ = _GEN_179[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_180[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_181[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_182[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_bp_debug_if = _GEN_183[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_184[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_fsrc = _GEN_185[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_tsrc = _GEN_186[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_valid = _GEN_187[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :236:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_bits = _GEN_188[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :236:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_is_virtual = _GEN_189[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :237:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_is_uncacheable = _GEN_190[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :238:32, :533:27] assign mem_ldq_retry_e_e_bits_executed = _GEN_191[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :239:32, :533:27] assign mem_ldq_retry_e_e_bits_succeeded = _GEN_192[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :240:32, :533:27] assign mem_ldq_retry_e_e_bits_order_fail = _GEN_193[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :241:32, :533:27] assign mem_ldq_retry_e_e_bits_observed = _GEN_194[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :242:32, :533:27] assign mem_ldq_retry_e_e_bits_st_dep_mask = _GEN_195[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :243:32, :533:27] assign mem_ldq_retry_e_e_bits_ld_byte_mask = _GEN_196[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :244:32, :533:27] assign mem_ldq_retry_e_e_bits_forward_std_val = _GEN_197[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :245:32, :533:27] assign mem_ldq_retry_e_e_bits_forward_stq_idx = _GEN_198[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :246:32, :533:27] assign mem_ldq_retry_e_e_bits_debug_wb_data = _GEN_199[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :247:32, :533:27] wire _mem_ldq_retry_e_out_valid_T_4; // @[util.scala:116:31] wire [11:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] mem_ldq_retry_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_ldq_retry_e_out_valid; // @[util.scala:114:23] wire [11:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_ldq_retry_e_out_bits_uop_br_mask_T_1 = mem_ldq_retry_e_e_bits_uop_br_mask & _mem_ldq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_ldq_retry_e_out_bits_uop_br_mask = _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [11:0] _mem_ldq_retry_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & mem_ldq_retry_e_e_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_ldq_retry_e_out_valid_T_1 = \|_mem_ldq_retry_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_ldq_retry_e_out_valid_T_2 = _mem_ldq_retry_e_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_ldq_retry_e_out_valid_T_3 = ~_mem_ldq_retry_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_ldq_retry_e_out_valid_T_4 = mem_ldq_retry_e_e_valid & _mem_ldq_retry_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_ldq_retry_e_out_valid = _mem_ldq_retry_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_ldq_retry_e_valid; // @[lsu.scala:1057:37] reg [31:0] mem_ldq_retry_e_bits_uop_inst; // @[lsu.scala:1057:37] reg [31:0] mem_ldq_retry_e_bits_uop_debug_inst; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_rvc; // @[lsu.scala:1057:37] reg [39:0] mem_ldq_retry_e_bits_uop_debug_pc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_issued; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_dis_col_sel; // @[lsu.scala:1057:37] reg [11:0] mem_ldq_retry_e_bits_uop_br_mask; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_uop_br_tag; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_uop_br_type; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_sfb; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_fence; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_fencei; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_sfence; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_amo; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_eret; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_rocc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_mov; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_edge_inst; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_pc_lob; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_taken; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_imm_rename; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_imm_sel; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_pimm; // @[lsu.scala:1057:37] reg [19:0] mem_ldq_retry_e_bits_uop_imm_packed; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_op1_sel; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_op2_sel; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_rob_idx; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_uop_stq_idx; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_pdst; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs1; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs2; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs3; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_ppred; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_exception; // @[lsu.scala:1057:37] reg [63:0] mem_ldq_retry_e_bits_uop_exc_cause; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_mem_size; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_mem_signed; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_uses_stq; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_unique; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_csr_cmd; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_ldst; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs1; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs2; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs3; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_frs3_en; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_fcn_op; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_val; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_fp_rm; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_fp_typ; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_addr_valid; // @[lsu.scala:1057:37] reg [39:0] mem_ldq_retry_e_bits_addr_bits; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_addr_is_virtual; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_addr_is_uncacheable; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_executed; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_succeeded; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_order_fail; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_observed; // @[lsu.scala:1057:37] reg [15:0] mem_ldq_retry_e_bits_st_dep_mask; // @[lsu.scala:1057:37] reg [7:0] mem_ldq_retry_e_bits_ld_byte_mask; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_forward_std_val; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_forward_stq_idx; // @[lsu.scala:1057:37] reg [63:0] mem_ldq_retry_e_bits_debug_wb_data; // @[lsu.scala:1057:37] wire [31:0] mem_stq_retry_e_out_bits_uop_inst = mem_stq_retry_e_e_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_stq_retry_e_out_bits_uop_debug_inst = mem_stq_retry_e_e_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_rvc = mem_stq_retry_e_e_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_stq_retry_e_out_bits_uop_debug_pc = mem_stq_retry_e_e_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_0 = mem_stq_retry_e_e_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_1 = mem_stq_retry_e_e_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_2 = mem_stq_retry_e_e_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_3 = mem_stq_retry_e_e_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_0 = mem_stq_retry_e_e_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_1 = mem_stq_retry_e_e_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_2 = mem_stq_retry_e_e_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_3 = mem_stq_retry_e_e_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_4 = mem_stq_retry_e_e_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_5 = mem_stq_retry_e_e_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_6 = mem_stq_retry_e_e_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_7 = mem_stq_retry_e_e_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_8 = mem_stq_retry_e_e_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_9 = mem_stq_retry_e_e_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_issued = mem_stq_retry_e_e_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_issued_partial_agen = mem_stq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_issued_partial_dgen = mem_stq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_iw_p1_speculative_child = mem_stq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_iw_p2_speculative_child = mem_stq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_p1_bypass_hint = mem_stq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_p2_bypass_hint = mem_stq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_p3_bypass_hint = mem_stq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_dis_col_sel = mem_stq_retry_e_e_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_stq_retry_e_out_bits_uop_br_tag = mem_stq_retry_e_e_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_stq_retry_e_out_bits_uop_br_type = mem_stq_retry_e_e_bits_uop_br_type; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_sfb = mem_stq_retry_e_e_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_fence = mem_stq_retry_e_e_bits_uop_is_fence; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_fencei = mem_stq_retry_e_e_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_sfence = mem_stq_retry_e_e_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_amo = mem_stq_retry_e_e_bits_uop_is_amo; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_eret = mem_stq_retry_e_e_bits_uop_is_eret; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_sys_pc2epc = mem_stq_retry_e_e_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_rocc = mem_stq_retry_e_e_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_mov = mem_stq_retry_e_e_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ftq_idx = mem_stq_retry_e_e_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_edge_inst = mem_stq_retry_e_e_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_pc_lob = mem_stq_retry_e_e_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_taken = mem_stq_retry_e_e_bits_uop_taken; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_imm_rename = mem_stq_retry_e_e_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_imm_sel = mem_stq_retry_e_e_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_pimm = mem_stq_retry_e_e_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_stq_retry_e_out_bits_uop_imm_packed = mem_stq_retry_e_e_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_op1_sel = mem_stq_retry_e_e_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_op2_sel = mem_stq_retry_e_e_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ldst = mem_stq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_wen = mem_stq_retry_e_e_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ren1 = mem_stq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ren2 = mem_stq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ren3 = mem_stq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_swap12 = mem_stq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_swap23 = mem_stq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_fp_ctrl_typeTagIn = mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_fp_ctrl_typeTagOut = mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_fromint = mem_stq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_toint = mem_stq_retry_e_e_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_fastpipe = mem_stq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_fma = mem_stq_retry_e_e_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_div = mem_stq_retry_e_e_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_sqrt = mem_stq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_wflags = mem_stq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_vec = mem_stq_retry_e_e_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_rob_idx = mem_stq_retry_e_e_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] mem_stq_retry_e_out_bits_uop_ldq_idx = mem_stq_retry_e_e_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] mem_stq_retry_e_out_bits_uop_stq_idx = mem_stq_retry_e_e_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_rxq_idx = mem_stq_retry_e_e_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_pdst = mem_stq_retry_e_e_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs1 = mem_stq_retry_e_e_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs2 = mem_stq_retry_e_e_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs3 = mem_stq_retry_e_e_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ppred = mem_stq_retry_e_e_bits_uop_ppred; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_prs1_busy = mem_stq_retry_e_e_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_prs2_busy = mem_stq_retry_e_e_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_prs3_busy = mem_stq_retry_e_e_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_ppred_busy = mem_stq_retry_e_e_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_stale_pdst = mem_stq_retry_e_e_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_exception = mem_stq_retry_e_e_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_stq_retry_e_out_bits_uop_exc_cause = mem_stq_retry_e_e_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_mem_cmd = mem_stq_retry_e_e_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_mem_size = mem_stq_retry_e_e_bits_uop_mem_size; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_mem_signed = mem_stq_retry_e_e_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_uses_ldq = mem_stq_retry_e_e_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_uses_stq = mem_stq_retry_e_e_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_unique = mem_stq_retry_e_e_bits_uop_is_unique; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_flush_on_commit = mem_stq_retry_e_e_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_csr_cmd = mem_stq_retry_e_e_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_ldst_is_rs1 = mem_stq_retry_e_e_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_ldst = mem_stq_retry_e_e_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs1 = mem_stq_retry_e_e_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs2 = mem_stq_retry_e_e_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs3 = mem_stq_retry_e_e_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_dst_rtype = mem_stq_retry_e_e_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs1_rtype = mem_stq_retry_e_e_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs2_rtype = mem_stq_retry_e_e_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_frs3_en = mem_stq_retry_e_e_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fcn_dw = mem_stq_retry_e_e_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_fcn_op = mem_stq_retry_e_e_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_val = mem_stq_retry_e_e_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_fp_rm = mem_stq_retry_e_e_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_fp_typ = mem_stq_retry_e_e_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_xcpt_pf_if = mem_stq_retry_e_e_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ae_if = mem_stq_retry_e_e_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ma_if = mem_stq_retry_e_e_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_bp_debug_if = mem_stq_retry_e_e_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_bp_xcpt_if = mem_stq_retry_e_e_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_debug_fsrc = mem_stq_retry_e_e_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_debug_tsrc = mem_stq_retry_e_e_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_addr_valid = mem_stq_retry_e_e_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_stq_retry_e_out_bits_addr_bits = mem_stq_retry_e_e_bits_addr_bits; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_addr_is_virtual = mem_stq_retry_e_e_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_data_valid = mem_stq_retry_e_e_bits_data_valid; // @[util.scala:114:23] wire [63:0] mem_stq_retry_e_out_bits_data_bits = mem_stq_retry_e_e_bits_data_bits; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_committed = mem_stq_retry_e_e_bits_committed; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_succeeded = mem_stq_retry_e_e_bits_succeeded; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_can_execute = mem_stq_retry_e_e_bits_can_execute; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_cleared = mem_stq_retry_e_e_bits_cleared; // @[util.scala:114:23] wire [63:0] mem_stq_retry_e_out_bits_debug_wb_data = mem_stq_retry_e_e_bits_debug_wb_data; // @[util.scala:114:23] wire [11:0] mem_stq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_valid; // @[lsu.scala:262:17] assign mem_stq_retry_e_e_valid = _GEN_26[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :263:32, :392:15, :533:27] assign mem_stq_retry_e_e_bits_uop_inst = _GEN_200[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_inst = _GEN_201[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_rvc = _GEN_202[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_pc = _GEN_203[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_0 = _GEN_204[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_1 = _GEN_205[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_2 = _GEN_206[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_3 = _GEN_207[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_0 = _GEN_208[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_1 = _GEN_209[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_2 = _GEN_210[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_3 = _GEN_211[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_4 = _GEN_212[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_5 = _GEN_213[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_6 = _GEN_214[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_7 = _GEN_215[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_8 = _GEN_216[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_9 = _GEN_217[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_issued = _GEN_218[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_219[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_220[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_221[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_222[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_223[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_224[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_225[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_dis_col_sel = _GEN_226[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_br_mask = _GEN_227[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_br_tag = _GEN_228[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_br_type = _GEN_229[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_sfb = _GEN_230[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_fence = _GEN_231[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_fencei = _GEN_232[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_sfence = _GEN_233[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_amo = _GEN_234[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_eret = _GEN_235[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_236[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_rocc = _GEN_237[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_mov = _GEN_238[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ftq_idx = _GEN_239[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_edge_inst = _GEN_240[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_pc_lob = _GEN_241[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_taken = _GEN_242[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_imm_rename = _GEN_243[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_imm_sel = _GEN_244[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_pimm = _GEN_245[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_imm_packed = _GEN_246[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_op1_sel = _GEN_247[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_op2_sel = _GEN_248[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_249[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_250[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_251[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_252[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_253[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_254[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_255[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_256[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_257[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_258[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_259[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_260[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_261[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_262[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_263[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_264[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_265[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_rob_idx = _GEN_266[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ldq_idx = _GEN_267[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_stq_idx = _GEN_268[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_rxq_idx = _GEN_269[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_pdst = _GEN_270[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs1 = _GEN_271[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs2 = _GEN_272[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs3 = _GEN_273[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ppred = _GEN_274[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs1_busy = _GEN_275[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs2_busy = _GEN_276[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs3_busy = _GEN_277[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ppred_busy = _GEN_278[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_stale_pdst = _GEN_279[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_exception = _GEN_280[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_exc_cause = _GEN_281[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_mem_cmd = _GEN_282[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_mem_size = _GEN_283[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_mem_signed = _GEN_284[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_uses_ldq = _GEN_285[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_uses_stq = _GEN_286[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_unique = _GEN_287[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_flush_on_commit = _GEN_288[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_csr_cmd = _GEN_289[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_290[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ldst = _GEN_291[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs1 = _GEN_292[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs2 = _GEN_293[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs3 = _GEN_294[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_dst_rtype = _GEN_295[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs1_rtype = _GEN_296[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs2_rtype = _GEN_297[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_frs3_en = _GEN_298[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fcn_dw = _GEN_299[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fcn_op = _GEN_300[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_val = _GEN_301[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_rm = _GEN_302[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_typ = _GEN_303[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_304[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_305[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_306[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_bp_debug_if = _GEN_307[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_308[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_fsrc = _GEN_309[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_tsrc = _GEN_310[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_addr_valid = _GEN_311[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :265:32, :533:27] assign mem_stq_retry_e_e_bits_addr_bits = _GEN_312[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :265:32, :533:27] assign mem_stq_retry_e_e_bits_addr_is_virtual = _GEN_313[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :266:32, :533:27] assign mem_stq_retry_e_e_bits_data_valid = _GEN_314[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :267:32, :533:27] assign mem_stq_retry_e_e_bits_data_bits = _GEN_315[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :267:32, :533:27] assign mem_stq_retry_e_e_bits_committed = _GEN_316[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :268:32, :533:27] assign mem_stq_retry_e_e_bits_succeeded = _GEN_317[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :269:32, :533:27] assign mem_stq_retry_e_e_bits_can_execute = _GEN_318[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :270:32, :533:27] assign mem_stq_retry_e_e_bits_cleared = _GEN_319[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :271:32, :533:27] assign mem_stq_retry_e_e_bits_debug_wb_data = _GEN_320[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :272:32, :533:27] wire _mem_stq_retry_e_out_valid_T_4; // @[util.scala:116:31] wire [11:0] _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] mem_stq_retry_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_stq_retry_e_out_valid; // @[util.scala:114:23] wire [11:0] _mem_stq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_stq_retry_e_out_bits_uop_br_mask_T_1 = mem_stq_retry_e_e_bits_uop_br_mask & _mem_stq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_stq_retry_e_out_bits_uop_br_mask = _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [11:0] _mem_stq_retry_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & mem_stq_retry_e_e_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_stq_retry_e_out_valid_T_1 = \|_mem_stq_retry_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_stq_retry_e_out_valid_T_2 = _mem_stq_retry_e_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_stq_retry_e_out_valid_T_3 = ~_mem_stq_retry_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_stq_retry_e_out_valid_T_4 = mem_stq_retry_e_e_valid & _mem_stq_retry_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_stq_retry_e_out_valid = _mem_stq_retry_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_stq_retry_e_valid; // @[lsu.scala:1058:37] reg [31:0] mem_stq_retry_e_bits_uop_inst; // @[lsu.scala:1058:37] reg [31:0] mem_stq_retry_e_bits_uop_debug_inst; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:1058:37] reg [39:0] mem_stq_retry_e_bits_uop_debug_pc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_issued; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_dis_col_sel; // @[lsu.scala:1058:37] reg [11:0] mem_stq_retry_e_bits_uop_br_mask; // @[lsu.scala:1058:37] reg [3:0] mem_stq_retry_e_bits_uop_br_tag; // @[lsu.scala:1058:37] reg [3:0] mem_stq_retry_e_bits_uop_br_type; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_sfence; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_eret; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_rocc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_mov; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_pc_lob; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_imm_rename; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_imm_sel; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_pimm; // @[lsu.scala:1058:37] reg [19:0] mem_stq_retry_e_bits_uop_imm_packed; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_op1_sel; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_op2_sel; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_rob_idx; // @[lsu.scala:1058:37] reg [3:0] mem_stq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:1058:37] reg [3:0] mem_stq_retry_e_bits_uop_stq_idx; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_pdst; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_prs1; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_prs2; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_prs3; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_ppred; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:1058:37] reg [63:0] mem_stq_retry_e_bits_uop_exc_cause; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_mem_size; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_csr_cmd; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_ldst; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs1; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs2; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs3; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_fcn_op; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_fp_rm; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_fp_typ; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:1058:37] reg [39:0] mem_stq_retry_e_bits_addr_bits; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_data_valid; // @[lsu.scala:1058:37] reg [63:0] mem_stq_retry_e_bits_data_bits; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_committed; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_succeeded; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_can_execute; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_cleared; // @[lsu.scala:1058:37] reg [63:0] mem_stq_retry_e_bits_debug_wb_data; // @[lsu.scala:1058:37] wire _GEN_390 = fired_load_agen_0 \| fired_load_agen_exec_0; // @[lsu.scala:321:49, :1060:58] wire _mem_ldq_e_T; // @[lsu.scala:1060:58] assign _mem_ldq_e_T = _GEN_390; // @[lsu.scala:1060:58] wire _do_ld_search_T; // @[lsu.scala:1124:57] assign _do_ld_search_T = _GEN_390; // @[lsu.scala:1060:58, :1124:57] wire _lcam_ldq_idx_T; // @[lsu.scala:1144:51] assign _lcam_ldq_idx_T = _GEN_390; // @[lsu.scala:1060:58, :1144:51] wire _can_forward_T; // @[lsu.scala:1154:58] assign _can_forward_T = _GEN_390; // @[lsu.scala:1060:58, :1154:58] wire _mem_ldq_e_T_1_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_valid; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_debug_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_rvc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [39:0] _mem_ldq_e_T_1_bits_uop_debug_pc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_0 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_2 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_3 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_0 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_2 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_3 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_4 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_5 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_6 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_7 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_8 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_9 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_issued = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_issued; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_issued_partial_agen = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_issued_partial_dgen = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_iw_p1_speculative_child = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iw_p1_speculative_child : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_iw_p2_speculative_child = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iw_p2_speculative_child : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_p1_bypass_hint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_p2_bypass_hint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_p3_bypass_hint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_dis_col_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_dis_col_sel : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [11:0] _mem_ldq_e_T_1_bits_uop_br_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_mask : 12'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_br_tag = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_br_type = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_sfb = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_fence = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_fencei = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_sfence = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sfence; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_amo = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_eret = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_eret; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_rocc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_rocc; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_mov = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_mov; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ftq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_edge_inst = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_pc_lob = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_taken = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_imm_rename = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_imm_rename; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_imm_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_pimm = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [19:0] _mem_ldq_e_T_1_bits_uop_imm_packed = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_op1_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_op2_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ldst = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_wen = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren2 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren3 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap12 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap23 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagIn = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagOut = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_fromint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_toint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_fastpipe = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_fma = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_div = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_sqrt = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_wflags = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_vec = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_rob_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rob_idx : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_ldq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldq_idx : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stq_idx : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_rxq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ppred = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_prs1_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_prs2_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_prs3_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_ppred_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_stale_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_exception = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [63:0] _mem_ldq_e_T_1_bits_uop_exc_cause = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_mem_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_mem_size = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_mem_signed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_uses_ldq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_uses_stq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_unique = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_flush_on_commit = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_csr_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_ldst_is_rs1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_ldst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_dst_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs1_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs2_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_frs3_en = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fcn_dw = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_fcn_op = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_fp_rm = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_fp_typ = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_pf_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ae_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ma_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_bp_debug_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_bp_xcpt_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_debug_fsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_debug_tsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_addr_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [39:0] _mem_ldq_e_T_1_bits_addr_bits = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_addr_bits : 40'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_addr_is_virtual = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_addr_is_uncacheable = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_executed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_succeeded = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_order_fail = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_observed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [15:0] _mem_ldq_e_T_1_bits_st_dep_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_st_dep_mask : 16'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [7:0] _mem_ldq_e_T_1_bits_ld_byte_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_ld_byte_mask : 8'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_forward_std_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_forward_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_forward_stq_idx : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [63:0] _mem_ldq_e_T_1_bits_debug_wb_data = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_2_valid = fired_load_retry_0 ? mem_ldq_retry_e_valid : _mem_ldq_e_T_1_valid; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_inst : _mem_ldq_e_T_1_bits_uop_inst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_debug_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_inst : _mem_ldq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_rvc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_rvc : _mem_ldq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [39:0] _mem_ldq_e_T_2_bits_uop_debug_pc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_pc : _mem_ldq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_0 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_0 : _mem_ldq_e_T_1_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_1 : _mem_ldq_e_T_1_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_2 : _mem_ldq_e_T_1_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_3 : _mem_ldq_e_T_1_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_0 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_0 : _mem_ldq_e_T_1_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_1 : _mem_ldq_e_T_1_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_2 : _mem_ldq_e_T_1_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_3 : _mem_ldq_e_T_1_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_4 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_4 : _mem_ldq_e_T_1_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_5 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_5 : _mem_ldq_e_T_1_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_6 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_6 : _mem_ldq_e_T_1_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_7 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_7 : _mem_ldq_e_T_1_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_8 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_8 : _mem_ldq_e_T_1_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_9 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_9 : _mem_ldq_e_T_1_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_issued = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_issued : _mem_ldq_e_T_1_bits_uop_iw_issued; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_issued_partial_agen = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_issued_partial_agen : _mem_ldq_e_T_1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_issued_partial_dgen = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_issued_partial_dgen : _mem_ldq_e_T_1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_iw_p1_speculative_child = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p1_speculative_child : _mem_ldq_e_T_1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_iw_p2_speculative_child = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p2_speculative_child : _mem_ldq_e_T_1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_p1_bypass_hint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p1_bypass_hint : _mem_ldq_e_T_1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_p2_bypass_hint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p2_bypass_hint : _mem_ldq_e_T_1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_p3_bypass_hint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p3_bypass_hint : _mem_ldq_e_T_1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_dis_col_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_dis_col_sel : _mem_ldq_e_T_1_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [11:0] _mem_ldq_e_T_2_bits_uop_br_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_mask : _mem_ldq_e_T_1_bits_uop_br_mask; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_br_tag = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_tag : _mem_ldq_e_T_1_bits_uop_br_tag; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_br_type = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_type : _mem_ldq_e_T_1_bits_uop_br_type; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_sfb = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sfb : _mem_ldq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_fence = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fence : _mem_ldq_e_T_1_bits_uop_is_fence; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_fencei = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fencei : _mem_ldq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_sfence = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sfence : _mem_ldq_e_T_1_bits_uop_is_sfence; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_amo = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_amo : _mem_ldq_e_T_1_bits_uop_is_amo; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_eret = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_eret : _mem_ldq_e_T_1_bits_uop_is_eret; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_rocc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_rocc : _mem_ldq_e_T_1_bits_uop_is_rocc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_mov = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_mov : _mem_ldq_e_T_1_bits_uop_is_mov; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ftq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ftq_idx : _mem_ldq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_edge_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_edge_inst : _mem_ldq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_pc_lob = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pc_lob : _mem_ldq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_taken = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_taken : _mem_ldq_e_T_1_bits_uop_taken; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_imm_rename = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_rename : _mem_ldq_e_T_1_bits_uop_imm_rename; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_imm_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_sel : _mem_ldq_e_T_1_bits_uop_imm_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_pimm = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pimm : _mem_ldq_e_T_1_bits_uop_pimm; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [19:0] _mem_ldq_e_T_2_bits_uop_imm_packed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_packed : _mem_ldq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_op1_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_op1_sel : _mem_ldq_e_T_1_bits_uop_op1_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_op2_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_op2_sel : _mem_ldq_e_T_1_bits_uop_op2_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ldst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ldst : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_wen = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_wen : _mem_ldq_e_T_1_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ren1 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ren2 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ren3 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap12 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_swap12 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap23 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_swap23 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagIn = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagIn : _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagOut = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagOut : _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_fromint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_fromint : _mem_ldq_e_T_1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_toint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_toint : _mem_ldq_e_T_1_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_fastpipe = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_fastpipe : _mem_ldq_e_T_1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_fma = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_fma : _mem_ldq_e_T_1_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_div = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_div : _mem_ldq_e_T_1_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_sqrt = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_sqrt : _mem_ldq_e_T_1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_wflags = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_wflags : _mem_ldq_e_T_1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_vec = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_vec : _mem_ldq_e_T_1_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_rob_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rob_idx : _mem_ldq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_ldq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldq_idx : _mem_ldq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stq_idx : _mem_ldq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_rxq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rxq_idx : _mem_ldq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pdst : _mem_ldq_e_T_1_bits_uop_pdst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1 : _mem_ldq_e_T_1_bits_uop_prs1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2 : _mem_ldq_e_T_1_bits_uop_prs2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3 : _mem_ldq_e_T_1_bits_uop_prs3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ppred = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred : _mem_ldq_e_T_1_bits_uop_ppred; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_prs1_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1_busy : _mem_ldq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_prs2_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2_busy : _mem_ldq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_prs3_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3_busy : _mem_ldq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_ppred_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred_busy : _mem_ldq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_stale_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stale_pdst : _mem_ldq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_exception = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exception : _mem_ldq_e_T_1_bits_uop_exception; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [63:0] _mem_ldq_e_T_2_bits_uop_exc_cause = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exc_cause : _mem_ldq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_mem_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_cmd : _mem_ldq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_mem_size = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_size : _mem_ldq_e_T_1_bits_uop_mem_size; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_mem_signed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_signed : _mem_ldq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_uses_ldq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_ldq : _mem_ldq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_uses_stq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_stq : _mem_ldq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_unique = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_unique : _mem_ldq_e_T_1_bits_uop_is_unique; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_flush_on_commit = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_flush_on_commit : _mem_ldq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_csr_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_csr_cmd : _mem_ldq_e_T_1_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_ldst_is_rs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_ldst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst : _mem_ldq_e_T_1_bits_uop_ldst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1 : _mem_ldq_e_T_1_bits_uop_lrs1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2 : _mem_ldq_e_T_1_bits_uop_lrs2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs3 : _mem_ldq_e_T_1_bits_uop_lrs3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_dst_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_dst_rtype : _mem_ldq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs1_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1_rtype : _mem_ldq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs2_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2_rtype : _mem_ldq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_frs3_en = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_frs3_en : _mem_ldq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fcn_dw = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fcn_dw : _mem_ldq_e_T_1_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_fcn_op = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fcn_op : _mem_ldq_e_T_1_bits_uop_fcn_op; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_val : _mem_ldq_e_T_1_bits_uop_fp_val; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_fp_rm = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_rm : _mem_ldq_e_T_1_bits_uop_fp_rm; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_fp_typ = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_typ : _mem_ldq_e_T_1_bits_uop_fp_typ; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_pf_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_pf_if : _mem_ldq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ae_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ae_if : _mem_ldq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ma_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ma_if : _mem_ldq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_bp_debug_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_debug_if : _mem_ldq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_bp_xcpt_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_xcpt_if : _mem_ldq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_debug_fsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_fsrc : _mem_ldq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_debug_tsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_tsrc : _mem_ldq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_addr_valid = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_valid : _mem_ldq_e_T_1_bits_addr_valid; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [39:0] _mem_ldq_e_T_2_bits_addr_bits = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_bits : _mem_ldq_e_T_1_bits_addr_bits; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_addr_is_virtual = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_virtual : _mem_ldq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_addr_is_uncacheable = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_uncacheable : _mem_ldq_e_T_1_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_executed = fired_load_retry_0 ? mem_ldq_retry_e_bits_executed : _mem_ldq_e_T_1_bits_executed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_succeeded = fired_load_retry_0 ? mem_ldq_retry_e_bits_succeeded : _mem_ldq_e_T_1_bits_succeeded; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_order_fail = fired_load_retry_0 ? mem_ldq_retry_e_bits_order_fail : _mem_ldq_e_T_1_bits_order_fail; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_observed = fired_load_retry_0 ? mem_ldq_retry_e_bits_observed : _mem_ldq_e_T_1_bits_observed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [15:0] _mem_ldq_e_T_2_bits_st_dep_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_st_dep_mask : _mem_ldq_e_T_1_bits_st_dep_mask; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [7:0] _mem_ldq_e_T_2_bits_ld_byte_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_ld_byte_mask : _mem_ldq_e_T_1_bits_ld_byte_mask; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_forward_std_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_std_val : _mem_ldq_e_T_1_bits_forward_std_val; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_forward_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_stq_idx : _mem_ldq_e_T_1_bits_forward_stq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [63:0] _mem_ldq_e_T_2_bits_debug_wb_data = fired_load_retry_0 ? mem_ldq_retry_e_bits_debug_wb_data : _mem_ldq_e_T_1_bits_debug_wb_data; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_3_valid = _mem_ldq_e_T ? mem_ldq_incoming_e_0_valid : _mem_ldq_e_T_2_valid; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [31:0] _mem_ldq_e_T_3_bits_uop_inst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_inst : _mem_ldq_e_T_2_bits_uop_inst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [31:0] _mem_ldq_e_T_3_bits_uop_debug_inst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_inst : _mem_ldq_e_T_2_bits_uop_debug_inst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_rvc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_rvc : _mem_ldq_e_T_2_bits_uop_is_rvc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [39:0] _mem_ldq_e_T_3_bits_uop_debug_pc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_pc : _mem_ldq_e_T_2_bits_uop_debug_pc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_0 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_0 : _mem_ldq_e_T_2_bits_uop_iq_type_0; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_1 : _mem_ldq_e_T_2_bits_uop_iq_type_1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_2 : _mem_ldq_e_T_2_bits_uop_iq_type_2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_3 : _mem_ldq_e_T_2_bits_uop_iq_type_3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_0 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_0 : _mem_ldq_e_T_2_bits_uop_fu_code_0; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_1 : _mem_ldq_e_T_2_bits_uop_fu_code_1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_2 : _mem_ldq_e_T_2_bits_uop_fu_code_2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_3 : _mem_ldq_e_T_2_bits_uop_fu_code_3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_4 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_4 : _mem_ldq_e_T_2_bits_uop_fu_code_4; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_5 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_5 : _mem_ldq_e_T_2_bits_uop_fu_code_5; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_6 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_6 : _mem_ldq_e_T_2_bits_uop_fu_code_6; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_7 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_7 : _mem_ldq_e_T_2_bits_uop_fu_code_7; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_8 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_8 : _mem_ldq_e_T_2_bits_uop_fu_code_8; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_9 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_9 : _mem_ldq_e_T_2_bits_uop_fu_code_9; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_issued = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_issued : _mem_ldq_e_T_2_bits_uop_iw_issued; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_issued_partial_agen = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_agen : _mem_ldq_e_T_2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_issued_partial_dgen = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _mem_ldq_e_T_2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_iw_p1_speculative_child = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p1_speculative_child : _mem_ldq_e_T_2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_iw_p2_speculative_child = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p2_speculative_child : _mem_ldq_e_T_2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_p1_bypass_hint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _mem_ldq_e_T_2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_p2_bypass_hint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _mem_ldq_e_T_2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_p3_bypass_hint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _mem_ldq_e_T_2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_dis_col_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_dis_col_sel : _mem_ldq_e_T_2_bits_uop_dis_col_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [11:0] _mem_ldq_e_T_3_bits_uop_br_mask = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_br_mask : _mem_ldq_e_T_2_bits_uop_br_mask; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_uop_br_tag = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_br_tag : _mem_ldq_e_T_2_bits_uop_br_tag; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_uop_br_type = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_br_type : _mem_ldq_e_T_2_bits_uop_br_type; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_sfb = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_sfb : _mem_ldq_e_T_2_bits_uop_is_sfb; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_fence = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_fence : _mem_ldq_e_T_2_bits_uop_is_fence; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_fencei = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_fencei : _mem_ldq_e_T_2_bits_uop_is_fencei; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_sfence = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_sfence : _mem_ldq_e_T_2_bits_uop_is_sfence; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_amo = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_amo : _mem_ldq_e_T_2_bits_uop_is_amo; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_eret = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_eret : _mem_ldq_e_T_2_bits_uop_is_eret; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_sys_pc2epc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_rocc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_rocc : _mem_ldq_e_T_2_bits_uop_is_rocc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_mov = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_mov : _mem_ldq_e_T_2_bits_uop_is_mov; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_ftq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ftq_idx : _mem_ldq_e_T_2_bits_uop_ftq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_edge_inst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_edge_inst : _mem_ldq_e_T_2_bits_uop_edge_inst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_pc_lob = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_pc_lob : _mem_ldq_e_T_2_bits_uop_pc_lob; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_taken = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_taken : _mem_ldq_e_T_2_bits_uop_taken; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_imm_rename = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_imm_rename : _mem_ldq_e_T_2_bits_uop_imm_rename; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_imm_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_imm_sel : _mem_ldq_e_T_2_bits_uop_imm_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_pimm = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_pimm : _mem_ldq_e_T_2_bits_uop_pimm; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [19:0] _mem_ldq_e_T_3_bits_uop_imm_packed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_imm_packed : _mem_ldq_e_T_2_bits_uop_imm_packed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_op1_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_op1_sel : _mem_ldq_e_T_2_bits_uop_op1_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_op2_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_op2_sel : _mem_ldq_e_T_2_bits_uop_op2_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ldst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ldst : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_wen = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wen : _mem_ldq_e_T_2_bits_uop_fp_ctrl_wen; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap12 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap23 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagIn = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagOut = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_fromint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fromint : _mem_ldq_e_T_2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_toint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_toint : _mem_ldq_e_T_2_bits_uop_fp_ctrl_toint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_fastpipe = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _mem_ldq_e_T_2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_fma = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fma : _mem_ldq_e_T_2_bits_uop_fp_ctrl_fma; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_div = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_div : _mem_ldq_e_T_2_bits_uop_fp_ctrl_div; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_sqrt = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _mem_ldq_e_T_2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_wflags = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wflags : _mem_ldq_e_T_2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_vec = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_vec : _mem_ldq_e_T_2_bits_uop_fp_ctrl_vec; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_rob_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_rob_idx : _mem_ldq_e_T_2_bits_uop_rob_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_uop_ldq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ldq_idx : _mem_ldq_e_T_2_bits_uop_ldq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_uop_stq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_stq_idx : _mem_ldq_e_T_2_bits_uop_stq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_rxq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_rxq_idx : _mem_ldq_e_T_2_bits_uop_rxq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_pdst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_pdst : _mem_ldq_e_T_2_bits_uop_pdst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_prs1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs1 : _mem_ldq_e_T_2_bits_uop_prs1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_prs2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs2 : _mem_ldq_e_T_2_bits_uop_prs2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_prs3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs3 : _mem_ldq_e_T_2_bits_uop_prs3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_ppred = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ppred : _mem_ldq_e_T_2_bits_uop_ppred; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_prs1_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs1_busy : _mem_ldq_e_T_2_bits_uop_prs1_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_prs2_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs2_busy : _mem_ldq_e_T_2_bits_uop_prs2_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_prs3_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs3_busy : _mem_ldq_e_T_2_bits_uop_prs3_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_ppred_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ppred_busy : _mem_ldq_e_T_2_bits_uop_ppred_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_stale_pdst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_stale_pdst : _mem_ldq_e_T_2_bits_uop_stale_pdst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_exception = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_exception : _mem_ldq_e_T_2_bits_uop_exception; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [63:0] _mem_ldq_e_T_3_bits_uop_exc_cause = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_exc_cause : _mem_ldq_e_T_2_bits_uop_exc_cause; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_mem_cmd = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_mem_cmd : _mem_ldq_e_T_2_bits_uop_mem_cmd; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_mem_size = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_mem_size : _mem_ldq_e_T_2_bits_uop_mem_size; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_mem_signed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_mem_signed : _mem_ldq_e_T_2_bits_uop_mem_signed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_uses_ldq = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_uses_ldq : _mem_ldq_e_T_2_bits_uop_uses_ldq; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_uses_stq = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_uses_stq : _mem_ldq_e_T_2_bits_uop_uses_stq; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_unique = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_unique : _mem_ldq_e_T_2_bits_uop_is_unique; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_flush_on_commit = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_flush_on_commit : _mem_ldq_e_T_2_bits_uop_flush_on_commit; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_csr_cmd = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_csr_cmd : _mem_ldq_e_T_2_bits_uop_csr_cmd; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_ldst_is_rs1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_2_bits_uop_ldst_is_rs1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_ldst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ldst : _mem_ldq_e_T_2_bits_uop_ldst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_lrs1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs1 : _mem_ldq_e_T_2_bits_uop_lrs1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_lrs2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs2 : _mem_ldq_e_T_2_bits_uop_lrs2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_lrs3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs3 : _mem_ldq_e_T_2_bits_uop_lrs3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_dst_rtype = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_dst_rtype : _mem_ldq_e_T_2_bits_uop_dst_rtype; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_lrs1_rtype = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs1_rtype : _mem_ldq_e_T_2_bits_uop_lrs1_rtype; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_lrs2_rtype = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs2_rtype : _mem_ldq_e_T_2_bits_uop_lrs2_rtype; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_frs3_en = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_frs3_en : _mem_ldq_e_T_2_bits_uop_frs3_en; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fcn_dw = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fcn_dw : _mem_ldq_e_T_2_bits_uop_fcn_dw; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_fcn_op = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fcn_op : _mem_ldq_e_T_2_bits_uop_fcn_op; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_val = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_val : _mem_ldq_e_T_2_bits_uop_fp_val; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_fp_rm = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_rm : _mem_ldq_e_T_2_bits_uop_fp_rm; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_fp_typ = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_typ : _mem_ldq_e_T_2_bits_uop_fp_typ; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_xcpt_pf_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_ldq_e_T_2_bits_uop_xcpt_pf_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_xcpt_ae_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_ldq_e_T_2_bits_uop_xcpt_ae_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_xcpt_ma_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_ldq_e_T_2_bits_uop_xcpt_ma_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_bp_debug_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_bp_debug_if : _mem_ldq_e_T_2_bits_uop_bp_debug_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_bp_xcpt_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_ldq_e_T_2_bits_uop_bp_xcpt_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_debug_fsrc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_fsrc : _mem_ldq_e_T_2_bits_uop_debug_fsrc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_debug_tsrc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_tsrc : _mem_ldq_e_T_2_bits_uop_debug_tsrc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_addr_valid = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_valid : _mem_ldq_e_T_2_bits_addr_valid; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [39:0] _mem_ldq_e_T_3_bits_addr_bits = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_bits : _mem_ldq_e_T_2_bits_addr_bits; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_addr_is_virtual = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_is_virtual : _mem_ldq_e_T_2_bits_addr_is_virtual; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_addr_is_uncacheable = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_is_uncacheable : _mem_ldq_e_T_2_bits_addr_is_uncacheable; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_executed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_executed : _mem_ldq_e_T_2_bits_executed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_succeeded = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_succeeded : _mem_ldq_e_T_2_bits_succeeded; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_order_fail = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_order_fail : _mem_ldq_e_T_2_bits_order_fail; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_observed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_observed : _mem_ldq_e_T_2_bits_observed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [15:0] _mem_ldq_e_T_3_bits_st_dep_mask = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_st_dep_mask : _mem_ldq_e_T_2_bits_st_dep_mask; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [7:0] _mem_ldq_e_T_3_bits_ld_byte_mask = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_ld_byte_mask : _mem_ldq_e_T_2_bits_ld_byte_mask; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_forward_std_val = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_forward_std_val : _mem_ldq_e_T_2_bits_forward_std_val; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_forward_stq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_forward_stq_idx : _mem_ldq_e_T_2_bits_forward_stq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [63:0] _mem_ldq_e_T_3_bits_debug_wb_data = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_debug_wb_data : _mem_ldq_e_T_2_bits_debug_wb_data; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire mem_ldq_e_0_valid = _mem_ldq_e_T_3_valid; // @[lsu.scala:321:49, :1060:33] wire [31:0] mem_ldq_e_0_bits_uop_inst = _mem_ldq_e_T_3_bits_uop_inst; // @[lsu.scala:321:49, :1060:33] wire [31:0] mem_ldq_e_0_bits_uop_debug_inst = _mem_ldq_e_T_3_bits_uop_debug_inst; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_rvc = _mem_ldq_e_T_3_bits_uop_is_rvc; // @[lsu.scala:321:49, :1060:33] wire [39:0] mem_ldq_e_0_bits_uop_debug_pc = _mem_ldq_e_T_3_bits_uop_debug_pc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_0 = _mem_ldq_e_T_3_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_1 = _mem_ldq_e_T_3_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_2 = _mem_ldq_e_T_3_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_3 = _mem_ldq_e_T_3_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_0 = _mem_ldq_e_T_3_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_1 = _mem_ldq_e_T_3_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_2 = _mem_ldq_e_T_3_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_3 = _mem_ldq_e_T_3_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_4 = _mem_ldq_e_T_3_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_5 = _mem_ldq_e_T_3_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_6 = _mem_ldq_e_T_3_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_7 = _mem_ldq_e_T_3_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_8 = _mem_ldq_e_T_3_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_9 = _mem_ldq_e_T_3_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_issued = _mem_ldq_e_T_3_bits_uop_iw_issued; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_issued_partial_agen = _mem_ldq_e_T_3_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_issued_partial_dgen = _mem_ldq_e_T_3_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_iw_p1_speculative_child = _mem_ldq_e_T_3_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_iw_p2_speculative_child = _mem_ldq_e_T_3_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_p1_bypass_hint = _mem_ldq_e_T_3_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_p2_bypass_hint = _mem_ldq_e_T_3_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_p3_bypass_hint = _mem_ldq_e_T_3_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_dis_col_sel = _mem_ldq_e_T_3_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1060:33] wire [11:0] mem_ldq_e_0_bits_uop_br_mask = _mem_ldq_e_T_3_bits_uop_br_mask; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_uop_br_tag = _mem_ldq_e_T_3_bits_uop_br_tag; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_uop_br_type = _mem_ldq_e_T_3_bits_uop_br_type; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_sfb = _mem_ldq_e_T_3_bits_uop_is_sfb; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_fence = _mem_ldq_e_T_3_bits_uop_is_fence; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_fencei = _mem_ldq_e_T_3_bits_uop_is_fencei; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_sfence = _mem_ldq_e_T_3_bits_uop_is_sfence; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_amo = _mem_ldq_e_T_3_bits_uop_is_amo; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_eret = _mem_ldq_e_T_3_bits_uop_is_eret; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_sys_pc2epc = _mem_ldq_e_T_3_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_rocc = _mem_ldq_e_T_3_bits_uop_is_rocc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_mov = _mem_ldq_e_T_3_bits_uop_is_mov; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_ftq_idx = _mem_ldq_e_T_3_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_edge_inst = _mem_ldq_e_T_3_bits_uop_edge_inst; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_pc_lob = _mem_ldq_e_T_3_bits_uop_pc_lob; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_taken = _mem_ldq_e_T_3_bits_uop_taken; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_imm_rename = _mem_ldq_e_T_3_bits_uop_imm_rename; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_imm_sel = _mem_ldq_e_T_3_bits_uop_imm_sel; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_pimm = _mem_ldq_e_T_3_bits_uop_pimm; // @[lsu.scala:321:49, :1060:33] wire [19:0] mem_ldq_e_0_bits_uop_imm_packed = _mem_ldq_e_T_3_bits_uop_imm_packed; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_op1_sel = _mem_ldq_e_T_3_bits_uop_op1_sel; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_op2_sel = _mem_ldq_e_T_3_bits_uop_op2_sel; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ldst = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_wen = _mem_ldq_e_T_3_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ren1 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ren2 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ren3 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_swap12 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_swap23 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_fp_ctrl_typeTagIn = _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_fp_ctrl_typeTagOut = _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_fromint = _mem_ldq_e_T_3_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_toint = _mem_ldq_e_T_3_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_fastpipe = _mem_ldq_e_T_3_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_fma = _mem_ldq_e_T_3_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_div = _mem_ldq_e_T_3_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_sqrt = _mem_ldq_e_T_3_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_wflags = _mem_ldq_e_T_3_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_vec = _mem_ldq_e_T_3_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_rob_idx = _mem_ldq_e_T_3_bits_uop_rob_idx; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_uop_ldq_idx = _mem_ldq_e_T_3_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_uop_stq_idx = _mem_ldq_e_T_3_bits_uop_stq_idx; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_rxq_idx = _mem_ldq_e_T_3_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_pdst = _mem_ldq_e_T_3_bits_uop_pdst; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_prs1 = _mem_ldq_e_T_3_bits_uop_prs1; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_prs2 = _mem_ldq_e_T_3_bits_uop_prs2; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_prs3 = _mem_ldq_e_T_3_bits_uop_prs3; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_ppred = _mem_ldq_e_T_3_bits_uop_ppred; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_prs1_busy = _mem_ldq_e_T_3_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_prs2_busy = _mem_ldq_e_T_3_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_prs3_busy = _mem_ldq_e_T_3_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_ppred_busy = _mem_ldq_e_T_3_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_stale_pdst = _mem_ldq_e_T_3_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_exception = _mem_ldq_e_T_3_bits_uop_exception; // @[lsu.scala:321:49, :1060:33] wire [63:0] mem_ldq_e_0_bits_uop_exc_cause = _mem_ldq_e_T_3_bits_uop_exc_cause; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_mem_cmd = _mem_ldq_e_T_3_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_mem_size = _mem_ldq_e_T_3_bits_uop_mem_size; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_mem_signed = _mem_ldq_e_T_3_bits_uop_mem_signed; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_uses_ldq = _mem_ldq_e_T_3_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_uses_stq = _mem_ldq_e_T_3_bits_uop_uses_stq; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_unique = _mem_ldq_e_T_3_bits_uop_is_unique; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_flush_on_commit = _mem_ldq_e_T_3_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_csr_cmd = _mem_ldq_e_T_3_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_ldst_is_rs1 = _mem_ldq_e_T_3_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_ldst = _mem_ldq_e_T_3_bits_uop_ldst; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs1 = _mem_ldq_e_T_3_bits_uop_lrs1; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs2 = _mem_ldq_e_T_3_bits_uop_lrs2; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs3 = _mem_ldq_e_T_3_bits_uop_lrs3; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_dst_rtype = _mem_ldq_e_T_3_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs1_rtype = _mem_ldq_e_T_3_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs2_rtype = _mem_ldq_e_T_3_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_frs3_en = _mem_ldq_e_T_3_bits_uop_frs3_en; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fcn_dw = _mem_ldq_e_T_3_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_fcn_op = _mem_ldq_e_T_3_bits_uop_fcn_op; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_val = _mem_ldq_e_T_3_bits_uop_fp_val; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_fp_rm = _mem_ldq_e_T_3_bits_uop_fp_rm; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_fp_typ = _mem_ldq_e_T_3_bits_uop_fp_typ; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_xcpt_pf_if = _mem_ldq_e_T_3_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_xcpt_ae_if = _mem_ldq_e_T_3_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_xcpt_ma_if = _mem_ldq_e_T_3_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_bp_debug_if = _mem_ldq_e_T_3_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_bp_xcpt_if = _mem_ldq_e_T_3_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_debug_fsrc = _mem_ldq_e_T_3_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_debug_tsrc = _mem_ldq_e_T_3_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_addr_valid = _mem_ldq_e_T_3_bits_addr_valid; // @[lsu.scala:321:49, :1060:33] wire [39:0] mem_ldq_e_0_bits_addr_bits = _mem_ldq_e_T_3_bits_addr_bits; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_addr_is_virtual = _mem_ldq_e_T_3_bits_addr_is_virtual; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_addr_is_uncacheable = _mem_ldq_e_T_3_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_executed = _mem_ldq_e_T_3_bits_executed; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_succeeded = _mem_ldq_e_T_3_bits_succeeded; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_order_fail = _mem_ldq_e_T_3_bits_order_fail; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_observed = _mem_ldq_e_T_3_bits_observed; // @[lsu.scala:321:49, :1060:33] wire [15:0] mem_ldq_e_0_bits_st_dep_mask = _mem_ldq_e_T_3_bits_st_dep_mask; // @[lsu.scala:321:49, :1060:33] wire [7:0] mem_ldq_e_0_bits_ld_byte_mask = _mem_ldq_e_T_3_bits_ld_byte_mask; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_forward_std_val = _mem_ldq_e_T_3_bits_forward_std_val; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_forward_stq_idx = _mem_ldq_e_T_3_bits_forward_stq_idx; // @[lsu.scala:321:49, :1060:33] wire [63:0] mem_ldq_e_0_bits_debug_wb_data = _mem_ldq_e_T_3_bits_debug_wb_data; // @[lsu.scala:321:49, :1060:33] wire [15:0] lcam_st_dep_mask_0 = mem_ldq_e_0_bits_st_dep_mask; // @[lsu.scala:321:49] wire _mem_stq_e_T_valid = fired_store_retry_0 & mem_stq_retry_e_valid; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [31:0] _mem_stq_e_T_bits_uop_inst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [31:0] _mem_stq_e_T_bits_uop_debug_inst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_rvc = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [39:0] _mem_stq_e_T_bits_uop_debug_pc = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_0 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_2 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_3 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_0 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_2 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_3 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_4 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_5 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_6 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_7 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_8 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_9 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_issued = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_issued; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_issued_partial_agen = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_issued_partial_dgen = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_iw_p1_speculative_child = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_iw_p1_speculative_child : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_iw_p2_speculative_child = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_iw_p2_speculative_child : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_p1_bypass_hint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_p2_bypass_hint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_p3_bypass_hint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_dis_col_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_dis_col_sel : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [11:0] _mem_stq_e_T_bits_uop_br_mask = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_br_mask : 12'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [3:0] _mem_stq_e_T_bits_uop_br_tag = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [3:0] _mem_stq_e_T_bits_uop_br_type = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_sfb = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_fence = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_fencei = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_sfence = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_sfence; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_amo = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_eret = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_eret; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_sys_pc2epc = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_rocc = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_rocc; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_mov = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_mov; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_ftq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_edge_inst = fired_store_retry_0 & mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_pc_lob = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_taken = fired_store_retry_0 & mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_imm_rename = fired_store_retry_0 & mem_stq_retry_e_bits_uop_imm_rename; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_imm_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_pimm = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [19:0] _mem_stq_e_T_bits_uop_imm_packed = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_op1_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_op2_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ldst = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_wen = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ren1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ren2 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ren3 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_swap12 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_swap23 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_fp_ctrl_typeTagIn = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_fp_ctrl_typeTagOut = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_fromint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_toint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_fastpipe = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_fma = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_div = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_sqrt = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_wflags = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_vec = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_rob_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_rob_idx : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [3:0] _mem_stq_e_T_bits_uop_ldq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ldq_idx : 4'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [3:0] _mem_stq_e_T_bits_uop_stq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_stq_idx : 4'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_rxq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_pdst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_prs1 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_prs2 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_prs3 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_ppred = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_prs1_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_prs2_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_prs3_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_ppred_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_stale_pdst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_exception = fired_store_retry_0 & mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [63:0] _mem_stq_e_T_bits_uop_exc_cause = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_mem_cmd = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_mem_size = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_mem_signed = fired_store_retry_0 & mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_uses_ldq = fired_store_retry_0 & mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_uses_stq = fired_store_retry_0 & mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_unique = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_flush_on_commit = fired_store_retry_0 & mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_csr_cmd = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_ldst_is_rs1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_ldst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_lrs1 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_lrs2 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_lrs3 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_dst_rtype = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_lrs1_rtype = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_lrs2_rtype = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_frs3_en = fired_store_retry_0 & mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fcn_dw = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_fcn_op = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_val = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_fp_rm = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_fp_typ = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_xcpt_pf_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_xcpt_ae_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_xcpt_ma_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_bp_debug_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_bp_xcpt_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_debug_fsrc = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_debug_tsrc = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_addr_valid = fired_store_retry_0 & mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [39:0] _mem_stq_e_T_bits_addr_bits = fired_store_retry_0 ? mem_stq_retry_e_bits_addr_bits : 40'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_addr_is_virtual = fired_store_retry_0 & mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_data_valid = fired_store_retry_0 & mem_stq_retry_e_bits_data_valid; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [63:0] _mem_stq_e_T_bits_data_bits = fired_store_retry_0 ? mem_stq_retry_e_bits_data_bits : 64'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_committed = fired_store_retry_0 & mem_stq_retry_e_bits_committed; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_succeeded = fired_store_retry_0 & mem_stq_retry_e_bits_succeeded; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_can_execute = fired_store_retry_0 & mem_stq_retry_e_bits_can_execute; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_cleared = fired_store_retry_0 & mem_stq_retry_e_bits_cleared; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [63:0] _mem_stq_e_T_bits_debug_wb_data = fired_store_retry_0 ? mem_stq_retry_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_1_valid = fired_store_agen_0 ? mem_stq_incoming_e_0_valid : _mem_stq_e_T_valid; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [31:0] _mem_stq_e_T_1_bits_uop_inst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_inst : _mem_stq_e_T_bits_uop_inst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [31:0] _mem_stq_e_T_1_bits_uop_debug_inst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_inst : _mem_stq_e_T_bits_uop_debug_inst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_rvc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_rvc : _mem_stq_e_T_bits_uop_is_rvc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [39:0] _mem_stq_e_T_1_bits_uop_debug_pc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_pc : _mem_stq_e_T_bits_uop_debug_pc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_0 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_0 : _mem_stq_e_T_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_1 : _mem_stq_e_T_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_2 : _mem_stq_e_T_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_3 : _mem_stq_e_T_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_0 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_0 : _mem_stq_e_T_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_1 : _mem_stq_e_T_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_2 : _mem_stq_e_T_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_3 : _mem_stq_e_T_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_4 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_4 : _mem_stq_e_T_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_5 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_5 : _mem_stq_e_T_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_6 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_6 : _mem_stq_e_T_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_7 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_7 : _mem_stq_e_T_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_8 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_8 : _mem_stq_e_T_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_9 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_9 : _mem_stq_e_T_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_issued = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_issued : _mem_stq_e_T_bits_uop_iw_issued; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_issued_partial_agen = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_issued_partial_agen : _mem_stq_e_T_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_issued_partial_dgen = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _mem_stq_e_T_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_iw_p1_speculative_child = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p1_speculative_child : _mem_stq_e_T_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_iw_p2_speculative_child = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p2_speculative_child : _mem_stq_e_T_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_p1_bypass_hint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _mem_stq_e_T_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_p2_bypass_hint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _mem_stq_e_T_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_p3_bypass_hint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _mem_stq_e_T_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_dis_col_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_dis_col_sel : _mem_stq_e_T_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [11:0] _mem_stq_e_T_1_bits_uop_br_mask = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_br_mask : _mem_stq_e_T_bits_uop_br_mask; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [3:0] _mem_stq_e_T_1_bits_uop_br_tag = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_br_tag : _mem_stq_e_T_bits_uop_br_tag; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [3:0] _mem_stq_e_T_1_bits_uop_br_type = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_br_type : _mem_stq_e_T_bits_uop_br_type; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_sfb = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_sfb : _mem_stq_e_T_bits_uop_is_sfb; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_fence = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_fence : _mem_stq_e_T_bits_uop_is_fence; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_fencei = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_fencei : _mem_stq_e_T_bits_uop_is_fencei; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_sfence = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_sfence : _mem_stq_e_T_bits_uop_is_sfence; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_amo = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_amo : _mem_stq_e_T_bits_uop_is_amo; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_eret = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_eret : _mem_stq_e_T_bits_uop_is_eret; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_sys_pc2epc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_stq_e_T_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_rocc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_rocc : _mem_stq_e_T_bits_uop_is_rocc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_mov = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_mov : _mem_stq_e_T_bits_uop_is_mov; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ftq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ftq_idx : _mem_stq_e_T_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_edge_inst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_edge_inst : _mem_stq_e_T_bits_uop_edge_inst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_pc_lob = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_pc_lob : _mem_stq_e_T_bits_uop_pc_lob; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_taken = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_taken : _mem_stq_e_T_bits_uop_taken; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_imm_rename = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_imm_rename : _mem_stq_e_T_bits_uop_imm_rename; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_imm_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_imm_sel : _mem_stq_e_T_bits_uop_imm_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_pimm = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_pimm : _mem_stq_e_T_bits_uop_pimm; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [19:0] _mem_stq_e_T_1_bits_uop_imm_packed = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_imm_packed : _mem_stq_e_T_bits_uop_imm_packed; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_op1_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_op1_sel : _mem_stq_e_T_bits_uop_op1_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_op2_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_op2_sel : _mem_stq_e_T_bits_uop_op2_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ldst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ldst : _mem_stq_e_T_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_wen = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_wen : _mem_stq_e_T_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ren1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _mem_stq_e_T_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ren2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _mem_stq_e_T_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ren3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _mem_stq_e_T_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_swap12 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _mem_stq_e_T_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_swap23 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _mem_stq_e_T_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagIn = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _mem_stq_e_T_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagOut = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _mem_stq_e_T_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_fromint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_fromint : _mem_stq_e_T_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_toint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_toint : _mem_stq_e_T_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_fastpipe = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _mem_stq_e_T_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_fma = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_fma : _mem_stq_e_T_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_div = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_div : _mem_stq_e_T_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_sqrt = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _mem_stq_e_T_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_wflags = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_wflags : _mem_stq_e_T_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_vec = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_vec : _mem_stq_e_T_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_rob_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_rob_idx : _mem_stq_e_T_bits_uop_rob_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [3:0] _mem_stq_e_T_1_bits_uop_ldq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ldq_idx : _mem_stq_e_T_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [3:0] _mem_stq_e_T_1_bits_uop_stq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_stq_idx : _mem_stq_e_T_bits_uop_stq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_rxq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_rxq_idx : _mem_stq_e_T_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_pdst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_pdst : _mem_stq_e_T_bits_uop_pdst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs1 : _mem_stq_e_T_bits_uop_prs1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs2 : _mem_stq_e_T_bits_uop_prs2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs3 : _mem_stq_e_T_bits_uop_prs3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ppred = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ppred : _mem_stq_e_T_bits_uop_ppred; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_prs1_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs1_busy : _mem_stq_e_T_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_prs2_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs2_busy : _mem_stq_e_T_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_prs3_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs3_busy : _mem_stq_e_T_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_ppred_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ppred_busy : _mem_stq_e_T_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_stale_pdst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_stale_pdst : _mem_stq_e_T_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_exception = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_exception : _mem_stq_e_T_bits_uop_exception; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [63:0] _mem_stq_e_T_1_bits_uop_exc_cause = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_exc_cause : _mem_stq_e_T_bits_uop_exc_cause; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_mem_cmd = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_mem_cmd : _mem_stq_e_T_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_mem_size = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_mem_size : _mem_stq_e_T_bits_uop_mem_size; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_mem_signed = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_mem_signed : _mem_stq_e_T_bits_uop_mem_signed; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_uses_ldq = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_uses_ldq : _mem_stq_e_T_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_uses_stq = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_uses_stq : _mem_stq_e_T_bits_uop_uses_stq; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_unique = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_unique : _mem_stq_e_T_bits_uop_is_unique; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_flush_on_commit = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_flush_on_commit : _mem_stq_e_T_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_csr_cmd = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_csr_cmd : _mem_stq_e_T_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_ldst_is_rs1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_stq_e_T_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_ldst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ldst : _mem_stq_e_T_bits_uop_ldst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs1 : _mem_stq_e_T_bits_uop_lrs1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs2 : _mem_stq_e_T_bits_uop_lrs2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs3 : _mem_stq_e_T_bits_uop_lrs3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_dst_rtype = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_dst_rtype : _mem_stq_e_T_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs1_rtype = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs1_rtype : _mem_stq_e_T_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs2_rtype = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs2_rtype : _mem_stq_e_T_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_frs3_en = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_frs3_en : _mem_stq_e_T_bits_uop_frs3_en; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fcn_dw = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fcn_dw : _mem_stq_e_T_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_fcn_op = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fcn_op : _mem_stq_e_T_bits_uop_fcn_op; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_val = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_val : _mem_stq_e_T_bits_uop_fp_val; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_fp_rm = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_rm : _mem_stq_e_T_bits_uop_fp_rm; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_fp_typ = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_typ : _mem_stq_e_T_bits_uop_fp_typ; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_xcpt_pf_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_stq_e_T_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ae_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_stq_e_T_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ma_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_stq_e_T_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_bp_debug_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_bp_debug_if : _mem_stq_e_T_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_bp_xcpt_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_stq_e_T_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_debug_fsrc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_fsrc : _mem_stq_e_T_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_debug_tsrc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_tsrc : _mem_stq_e_T_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_addr_valid = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_addr_valid : _mem_stq_e_T_bits_addr_valid; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [39:0] _mem_stq_e_T_1_bits_addr_bits = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_addr_bits : _mem_stq_e_T_bits_addr_bits; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_addr_is_virtual = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_addr_is_virtual : _mem_stq_e_T_bits_addr_is_virtual; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_data_valid = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_data_valid : _mem_stq_e_T_bits_data_valid; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [63:0] _mem_stq_e_T_1_bits_data_bits = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_data_bits : _mem_stq_e_T_bits_data_bits; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_committed = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_committed : _mem_stq_e_T_bits_committed; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_succeeded = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_succeeded : _mem_stq_e_T_bits_succeeded; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_can_execute = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_can_execute : _mem_stq_e_T_bits_can_execute; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_cleared = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_cleared : _mem_stq_e_T_bits_cleared; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [63:0] _mem_stq_e_T_1_bits_debug_wb_data = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_debug_wb_data : _mem_stq_e_T_bits_debug_wb_data; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire mem_stq_e_0_valid = _mem_stq_e_T_1_valid; // @[lsu.scala:321:49, :1066:33] wire [31:0] mem_stq_e_0_bits_uop_inst = _mem_stq_e_T_1_bits_uop_inst; // @[lsu.scala:321:49, :1066:33] wire [31:0] mem_stq_e_0_bits_uop_debug_inst = _mem_stq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_rvc = _mem_stq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:321:49, :1066:33] wire [39:0] mem_stq_e_0_bits_uop_debug_pc = _mem_stq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_0 = _mem_stq_e_T_1_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_1 = _mem_stq_e_T_1_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_2 = _mem_stq_e_T_1_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_3 = _mem_stq_e_T_1_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_0 = _mem_stq_e_T_1_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_1 = _mem_stq_e_T_1_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_2 = _mem_stq_e_T_1_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_3 = _mem_stq_e_T_1_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_4 = _mem_stq_e_T_1_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_5 = _mem_stq_e_T_1_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_6 = _mem_stq_e_T_1_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_7 = _mem_stq_e_T_1_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_8 = _mem_stq_e_T_1_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_9 = _mem_stq_e_T_1_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_issued = _mem_stq_e_T_1_bits_uop_iw_issued; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_issued_partial_agen = _mem_stq_e_T_1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_issued_partial_dgen = _mem_stq_e_T_1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_iw_p1_speculative_child = _mem_stq_e_T_1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_iw_p2_speculative_child = _mem_stq_e_T_1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_p1_bypass_hint = _mem_stq_e_T_1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_p2_bypass_hint = _mem_stq_e_T_1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_p3_bypass_hint = _mem_stq_e_T_1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_dis_col_sel = _mem_stq_e_T_1_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1066:33] wire [11:0] mem_stq_e_0_bits_uop_br_mask = _mem_stq_e_T_1_bits_uop_br_mask; // @[lsu.scala:321:49, :1066:33] wire [3:0] mem_stq_e_0_bits_uop_br_tag = _mem_stq_e_T_1_bits_uop_br_tag; // @[lsu.scala:321:49, :1066:33] wire [3:0] mem_stq_e_0_bits_uop_br_type = _mem_stq_e_T_1_bits_uop_br_type; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_sfb = _mem_stq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_fence = _mem_stq_e_T_1_bits_uop_is_fence; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_fencei = _mem_stq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_sfence = _mem_stq_e_T_1_bits_uop_is_sfence; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_amo = _mem_stq_e_T_1_bits_uop_is_amo; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_eret = _mem_stq_e_T_1_bits_uop_is_eret; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_sys_pc2epc = _mem_stq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_rocc = _mem_stq_e_T_1_bits_uop_is_rocc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_mov = _mem_stq_e_T_1_bits_uop_is_mov; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_ftq_idx = _mem_stq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_edge_inst = _mem_stq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_pc_lob = _mem_stq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_taken = _mem_stq_e_T_1_bits_uop_taken; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_imm_rename = _mem_stq_e_T_1_bits_uop_imm_rename; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_imm_sel = _mem_stq_e_T_1_bits_uop_imm_sel; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_pimm = _mem_stq_e_T_1_bits_uop_pimm; // @[lsu.scala:321:49, :1066:33] wire [19:0] mem_stq_e_0_bits_uop_imm_packed = _mem_stq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_op1_sel = _mem_stq_e_T_1_bits_uop_op1_sel; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_op2_sel = _mem_stq_e_T_1_bits_uop_op2_sel; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ldst = _mem_stq_e_T_1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_wen = _mem_stq_e_T_1_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ren1 = _mem_stq_e_T_1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ren2 = _mem_stq_e_T_1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ren3 = _mem_stq_e_T_1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_swap12 = _mem_stq_e_T_1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_swap23 = _mem_stq_e_T_1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_fp_ctrl_typeTagIn = _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_fp_ctrl_typeTagOut = _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_fromint = _mem_stq_e_T_1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_toint = _mem_stq_e_T_1_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_fastpipe = _mem_stq_e_T_1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_fma = _mem_stq_e_T_1_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_div = _mem_stq_e_T_1_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_sqrt = _mem_stq_e_T_1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_wflags = _mem_stq_e_T_1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_vec = _mem_stq_e_T_1_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_rob_idx = _mem_stq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:321:49, :1066:33] wire [3:0] mem_stq_e_0_bits_uop_ldq_idx = _mem_stq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1066:33] wire [3:0] mem_stq_e_0_bits_uop_stq_idx = _mem_stq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_rxq_idx = _mem_stq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_pdst = _mem_stq_e_T_1_bits_uop_pdst; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_prs1 = _mem_stq_e_T_1_bits_uop_prs1; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_prs2 = _mem_stq_e_T_1_bits_uop_prs2; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_prs3 = _mem_stq_e_T_1_bits_uop_prs3; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_ppred = _mem_stq_e_T_1_bits_uop_ppred; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_prs1_busy = _mem_stq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_prs2_busy = _mem_stq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_prs3_busy = _mem_stq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_ppred_busy = _mem_stq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_stale_pdst = _mem_stq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_exception = _mem_stq_e_T_1_bits_uop_exception; // @[lsu.scala:321:49, :1066:33] wire [63:0] mem_stq_e_0_bits_uop_exc_cause = _mem_stq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_mem_cmd = _mem_stq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_mem_size = _mem_stq_e_T_1_bits_uop_mem_size; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_mem_signed = _mem_stq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_uses_ldq = _mem_stq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_uses_stq = _mem_stq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_unique = _mem_stq_e_T_1_bits_uop_is_unique; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_flush_on_commit = _mem_stq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_csr_cmd = _mem_stq_e_T_1_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_ldst_is_rs1 = _mem_stq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_ldst = _mem_stq_e_T_1_bits_uop_ldst; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_lrs1 = _mem_stq_e_T_1_bits_uop_lrs1; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_lrs2 = _mem_stq_e_T_1_bits_uop_lrs2; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_lrs3 = _mem_stq_e_T_1_bits_uop_lrs3; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_dst_rtype = _mem_stq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_lrs1_rtype = _mem_stq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_lrs2_rtype = _mem_stq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_frs3_en = _mem_stq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fcn_dw = _mem_stq_e_T_1_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_fcn_op = _mem_stq_e_T_1_bits_uop_fcn_op; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_val = _mem_stq_e_T_1_bits_uop_fp_val; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_fp_rm = _mem_stq_e_T_1_bits_uop_fp_rm; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_fp_typ = _mem_stq_e_T_1_bits_uop_fp_typ; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_xcpt_pf_if = _mem_stq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_xcpt_ae_if = _mem_stq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_xcpt_ma_if = _mem_stq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_bp_debug_if = _mem_stq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_bp_xcpt_if = _mem_stq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_debug_fsrc = _mem_stq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_debug_tsrc = _mem_stq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_addr_valid = _mem_stq_e_T_1_bits_addr_valid; // @[lsu.scala:321:49, :1066:33] wire [39:0] mem_stq_e_0_bits_addr_bits = _mem_stq_e_T_1_bits_addr_bits; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_addr_is_virtual = _mem_stq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_data_valid = _mem_stq_e_T_1_bits_data_valid; // @[lsu.scala:321:49, :1066:33] wire [63:0] mem_stq_e_0_bits_data_bits = _mem_stq_e_T_1_bits_data_bits; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_committed = _mem_stq_e_T_1_bits_committed; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_succeeded = _mem_stq_e_T_1_bits_succeeded; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_can_execute = _mem_stq_e_T_1_bits_can_execute; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_cleared = _mem_stq_e_T_1_bits_cleared; // @[lsu.scala:321:49, :1066:33] wire [63:0] mem_stq_e_0_bits_debug_wb_data = _mem_stq_e_T_1_bits_debug_wb_data; // @[lsu.scala:321:49, :1066:33] reg mem_tlb_miss_0; // @[lsu.scala:1070:41] reg mem_tlb_uncacheable_0; // @[lsu.scala:1071:41] reg [39:0] mem_paddr_0; // @[lsu.scala:1072:41] wire _stq_clr_head_idx_T = ~stq_cleared_0; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_1 = stq_valid_0 & _stq_clr_head_idx_T; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_2 = ~stq_cleared_1; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_3 = stq_valid_1 & _stq_clr_head_idx_T_2; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_4 = ~stq_cleared_2; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_5 = stq_valid_2 & _stq_clr_head_idx_T_4; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_6 = ~stq_cleared_3; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_7 = stq_valid_3 & _stq_clr_head_idx_T_6; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_8 = ~stq_cleared_4; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_9 = stq_valid_4 & _stq_clr_head_idx_T_8; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_10 = ~stq_cleared_5; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_11 = stq_valid_5 & _stq_clr_head_idx_T_10; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_12 = ~stq_cleared_6; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_13 = stq_valid_6 & _stq_clr_head_idx_T_12; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_14 = ~stq_cleared_7; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_15 = stq_valid_7 & _stq_clr_head_idx_T_14; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_16 = ~stq_cleared_8; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_17 = stq_valid_8 & _stq_clr_head_idx_T_16; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_18 = ~stq_cleared_9; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_19 = stq_valid_9 & _stq_clr_head_idx_T_18; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_20 = ~stq_cleared_10; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_21 = stq_valid_10 & _stq_clr_head_idx_T_20; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_22 = ~stq_cleared_11; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_23 = stq_valid_11 & _stq_clr_head_idx_T_22; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_24 = ~stq_cleared_12; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_25 = stq_valid_12 & _stq_clr_head_idx_T_24; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_26 = ~stq_cleared_13; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_27 = stq_valid_13 & _stq_clr_head_idx_T_26; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_28 = ~stq_cleared_14; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_29 = stq_valid_14 & _stq_clr_head_idx_T_28; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_30 = ~stq_cleared_15; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_31 = stq_valid_15 & _stq_clr_head_idx_T_30; // @[lsu.scala:251:32, :1077:{18,21}] wire stq_clr_head_idx_temp_vec_15 = _stq_clr_head_idx_T_31; // @[util.scala:352:65] wire stq_clr_head_idx_temp_vec_0 = _stq_clr_head_idx_T_1 & _stq_clr_head_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_1 = _stq_clr_head_idx_T_3 & _stq_clr_head_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_2 = _stq_clr_head_idx_T_5 & _stq_clr_head_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_3 = _stq_clr_head_idx_T_7 & _stq_clr_head_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_4 = _stq_clr_head_idx_T_9 & _stq_clr_head_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_5 = _stq_clr_head_idx_T_11 & _stq_clr_head_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_6 = _stq_clr_head_idx_T_13 & _stq_clr_head_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _stq_clr_head_idx_temp_vec_T_7 = ~(stq_commit_head[3]); // @[util.scala:352:72] wire stq_clr_head_idx_temp_vec_7 = _stq_clr_head_idx_T_15 & _stq_clr_head_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_8 = _stq_clr_head_idx_T_17 & _stq_clr_head_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_9 = _stq_clr_head_idx_T_19 & _stq_clr_head_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_10 = _stq_clr_head_idx_T_21 & _stq_clr_head_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_11 = _stq_clr_head_idx_T_23 & _stq_clr_head_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_12 = _stq_clr_head_idx_T_25 & _stq_clr_head_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_13 = _stq_clr_head_idx_T_27 & _stq_clr_head_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_14 = _stq_clr_head_idx_T_29 & _stq_clr_head_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire [4:0] _stq_clr_head_idx_idx_T = {4'hF, ~_stq_clr_head_idx_T_29}; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_1 = _stq_clr_head_idx_T_27 ? 5'h1D : _stq_clr_head_idx_idx_T; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_2 = _stq_clr_head_idx_T_25 ? 5'h1C : _stq_clr_head_idx_idx_T_1; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_3 = _stq_clr_head_idx_T_23 ? 5'h1B : _stq_clr_head_idx_idx_T_2; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_4 = _stq_clr_head_idx_T_21 ? 5'h1A : _stq_clr_head_idx_idx_T_3; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_5 = _stq_clr_head_idx_T_19 ? 5'h19 : _stq_clr_head_idx_idx_T_4; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_6 = _stq_clr_head_idx_T_17 ? 5'h18 : _stq_clr_head_idx_idx_T_5; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_7 = _stq_clr_head_idx_T_15 ? 5'h17 : _stq_clr_head_idx_idx_T_6; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_8 = _stq_clr_head_idx_T_13 ? 5'h16 : _stq_clr_head_idx_idx_T_7; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_9 = _stq_clr_head_idx_T_11 ? 5'h15 : _stq_clr_head_idx_idx_T_8; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_10 = _stq_clr_head_idx_T_9 ? 5'h14 : _stq_clr_head_idx_idx_T_9; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_11 = _stq_clr_head_idx_T_7 ? 5'h13 : _stq_clr_head_idx_idx_T_10; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_12 = _stq_clr_head_idx_T_5 ? 5'h12 : _stq_clr_head_idx_idx_T_11; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_13 = _stq_clr_head_idx_T_3 ? 5'h11 : _stq_clr_head_idx_idx_T_12; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_14 = _stq_clr_head_idx_T_1 ? 5'h10 : _stq_clr_head_idx_idx_T_13; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_15 = stq_clr_head_idx_temp_vec_15 ? 5'hF : _stq_clr_head_idx_idx_T_14; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_16 = stq_clr_head_idx_temp_vec_14 ? 5'hE : _stq_clr_head_idx_idx_T_15; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_17 = stq_clr_head_idx_temp_vec_13 ? 5'hD : _stq_clr_head_idx_idx_T_16; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_18 = stq_clr_head_idx_temp_vec_12 ? 5'hC : _stq_clr_head_idx_idx_T_17; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_19 = stq_clr_head_idx_temp_vec_11 ? 5'hB : _stq_clr_head_idx_idx_T_18; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_20 = stq_clr_head_idx_temp_vec_10 ? 5'hA : _stq_clr_head_idx_idx_T_19; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_21 = stq_clr_head_idx_temp_vec_9 ? 5'h9 : _stq_clr_head_idx_idx_T_20; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_22 = stq_clr_head_idx_temp_vec_8 ? 5'h8 : _stq_clr_head_idx_idx_T_21; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_23 = stq_clr_head_idx_temp_vec_7 ? 5'h7 : _stq_clr_head_idx_idx_T_22; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_24 = stq_clr_head_idx_temp_vec_6 ? 5'h6 : _stq_clr_head_idx_idx_T_23; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_25 = stq_clr_head_idx_temp_vec_5 ? 5'h5 : _stq_clr_head_idx_idx_T_24; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_26 = stq_clr_head_idx_temp_vec_4 ? 5'h4 : _stq_clr_head_idx_idx_T_25; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_27 = stq_clr_head_idx_temp_vec_3 ? 5'h3 : _stq_clr_head_idx_idx_T_26; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_28 = stq_clr_head_idx_temp_vec_2 ? 5'h2 : _stq_clr_head_idx_idx_T_27; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_29 = stq_clr_head_idx_temp_vec_1 ? 5'h1 : _stq_clr_head_idx_idx_T_28; // @[Mux.scala:50:70] wire [4:0] stq_clr_head_idx_idx = stq_clr_head_idx_temp_vec_0 ? 5'h0 : _stq_clr_head_idx_idx_T_29; // @[Mux.scala:50:70] wire [3:0] _stq_clr_head_idx_T_32 = stq_clr_head_idx_idx[3:0]; // @[Mux.scala:50:70] reg [3:0] stq_clr_head_idx; // @[lsu.scala:1076:33] wire [3:0] _s_uop_T = stq_clr_head_idx; // @[lsu.scala:1076:33] reg clr_valid; // @[lsu.scala:1084:24] reg [31:0] clr_uop_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_inst = clr_uop_inst; // @[util.scala:104:23] reg [31:0] clr_uop_debug_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_debug_inst = clr_uop_debug_inst; // @[util.scala:104:23] reg clr_uop_is_rvc; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_rvc = clr_uop_is_rvc; // @[util.scala:104:23] reg [39:0] clr_uop_debug_pc; // @[lsu.scala:1086:24] wire [39:0] clr_uop_1_out_debug_pc = clr_uop_debug_pc; // @[util.scala:104:23] reg clr_uop_iq_type_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_0 = clr_uop_iq_type_0; // @[util.scala:104:23] reg clr_uop_iq_type_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_1 = clr_uop_iq_type_1; // @[util.scala:104:23] reg clr_uop_iq_type_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_2 = clr_uop_iq_type_2; // @[util.scala:104:23] reg clr_uop_iq_type_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_3 = clr_uop_iq_type_3; // @[util.scala:104:23] reg clr_uop_fu_code_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_0 = clr_uop_fu_code_0; // @[util.scala:104:23] reg clr_uop_fu_code_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_1 = clr_uop_fu_code_1; // @[util.scala:104:23] reg clr_uop_fu_code_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_2 = clr_uop_fu_code_2; // @[util.scala:104:23] reg clr_uop_fu_code_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_3 = clr_uop_fu_code_3; // @[util.scala:104:23] reg clr_uop_fu_code_4; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_4 = clr_uop_fu_code_4; // @[util.scala:104:23] reg clr_uop_fu_code_5; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_5 = clr_uop_fu_code_5; // @[util.scala:104:23] reg clr_uop_fu_code_6; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_6 = clr_uop_fu_code_6; // @[util.scala:104:23] reg clr_uop_fu_code_7; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_7 = clr_uop_fu_code_7; // @[util.scala:104:23] reg clr_uop_fu_code_8; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_8 = clr_uop_fu_code_8; // @[util.scala:104:23] reg clr_uop_fu_code_9; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_9 = clr_uop_fu_code_9; // @[util.scala:104:23] reg clr_uop_iw_issued; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_issued = clr_uop_iw_issued; // @[util.scala:104:23] reg clr_uop_iw_issued_partial_agen; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_issued_partial_agen = clr_uop_iw_issued_partial_agen; // @[util.scala:104:23] reg clr_uop_iw_issued_partial_dgen; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_issued_partial_dgen = clr_uop_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] clr_uop_iw_p1_speculative_child; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_iw_p1_speculative_child = clr_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] clr_uop_iw_p2_speculative_child; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_iw_p2_speculative_child = clr_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg clr_uop_iw_p1_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_p1_bypass_hint = clr_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg clr_uop_iw_p2_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_p2_bypass_hint = clr_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg clr_uop_iw_p3_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_p3_bypass_hint = clr_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] clr_uop_dis_col_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_dis_col_sel = clr_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] clr_uop_br_mask; // @[lsu.scala:1086:24] reg [3:0] clr_uop_br_tag; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_br_tag = clr_uop_br_tag; // @[util.scala:104:23] reg [3:0] clr_uop_br_type; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_br_type = clr_uop_br_type; // @[util.scala:104:23] reg clr_uop_is_sfb; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_sfb = clr_uop_is_sfb; // @[util.scala:104:23] reg clr_uop_is_fence; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_fence = clr_uop_is_fence; // @[util.scala:104:23] reg clr_uop_is_fencei; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_fencei = clr_uop_is_fencei; // @[util.scala:104:23] reg clr_uop_is_sfence; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_sfence = clr_uop_is_sfence; // @[util.scala:104:23] reg clr_uop_is_amo; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_amo = clr_uop_is_amo; // @[util.scala:104:23] reg clr_uop_is_eret; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_eret = clr_uop_is_eret; // @[util.scala:104:23] reg clr_uop_is_sys_pc2epc; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_sys_pc2epc = clr_uop_is_sys_pc2epc; // @[util.scala:104:23] reg clr_uop_is_rocc; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_rocc = clr_uop_is_rocc; // @[util.scala:104:23] reg clr_uop_is_mov; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_mov = clr_uop_is_mov; // @[util.scala:104:23] reg [4:0] clr_uop_ftq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_ftq_idx = clr_uop_ftq_idx; // @[util.scala:104:23] reg clr_uop_edge_inst; // @[lsu.scala:1086:24] wire clr_uop_1_out_edge_inst = clr_uop_edge_inst; // @[util.scala:104:23] reg [5:0] clr_uop_pc_lob; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_pc_lob = clr_uop_pc_lob; // @[util.scala:104:23] reg clr_uop_taken; // @[lsu.scala:1086:24] wire clr_uop_1_out_taken = clr_uop_taken; // @[util.scala:104:23] reg clr_uop_imm_rename; // @[lsu.scala:1086:24] wire clr_uop_1_out_imm_rename = clr_uop_imm_rename; // @[util.scala:104:23] reg [2:0] clr_uop_imm_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_imm_sel = clr_uop_imm_sel; // @[util.scala:104:23] reg [4:0] clr_uop_pimm; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_pimm = clr_uop_pimm; // @[util.scala:104:23] reg [19:0] clr_uop_imm_packed; // @[lsu.scala:1086:24] wire [19:0] clr_uop_1_out_imm_packed = clr_uop_imm_packed; // @[util.scala:104:23] reg [1:0] clr_uop_op1_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_op1_sel = clr_uop_op1_sel; // @[util.scala:104:23] reg [2:0] clr_uop_op2_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_op2_sel = clr_uop_op2_sel; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ldst; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ldst = clr_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg clr_uop_fp_ctrl_wen; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_wen = clr_uop_fp_ctrl_wen; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ren1; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ren1 = clr_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ren2; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ren2 = clr_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ren3; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ren3 = clr_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg clr_uop_fp_ctrl_swap12; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_swap12 = clr_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg clr_uop_fp_ctrl_swap23; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_swap23 = clr_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] clr_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_fp_ctrl_typeTagIn = clr_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] clr_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_fp_ctrl_typeTagOut = clr_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg clr_uop_fp_ctrl_fromint; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_fromint = clr_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg clr_uop_fp_ctrl_toint; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_toint = clr_uop_fp_ctrl_toint; // @[util.scala:104:23] reg clr_uop_fp_ctrl_fastpipe; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_fastpipe = clr_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg clr_uop_fp_ctrl_fma; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_fma = clr_uop_fp_ctrl_fma; // @[util.scala:104:23] reg clr_uop_fp_ctrl_div; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_div = clr_uop_fp_ctrl_div; // @[util.scala:104:23] reg clr_uop_fp_ctrl_sqrt; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_sqrt = clr_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg clr_uop_fp_ctrl_wflags; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_wflags = clr_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg clr_uop_fp_ctrl_vec; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_vec = clr_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] clr_uop_rob_idx; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_rob_idx = clr_uop_rob_idx; // @[util.scala:104:23] reg [3:0] clr_uop_ldq_idx; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_ldq_idx = clr_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] clr_uop_stq_idx; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_stq_idx = clr_uop_stq_idx; // @[util.scala:104:23] reg [1:0] clr_uop_rxq_idx; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_rxq_idx = clr_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] clr_uop_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_pdst = clr_uop_pdst; // @[util.scala:104:23] reg [6:0] clr_uop_prs1; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_prs1 = clr_uop_prs1; // @[util.scala:104:23] reg [6:0] clr_uop_prs2; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_prs2 = clr_uop_prs2; // @[util.scala:104:23] reg [6:0] clr_uop_prs3; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_prs3 = clr_uop_prs3; // @[util.scala:104:23] reg [4:0] clr_uop_ppred; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_ppred = clr_uop_ppred; // @[util.scala:104:23] reg clr_uop_prs1_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_prs1_busy = clr_uop_prs1_busy; // @[util.scala:104:23] reg clr_uop_prs2_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_prs2_busy = clr_uop_prs2_busy; // @[util.scala:104:23] reg clr_uop_prs3_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_prs3_busy = clr_uop_prs3_busy; // @[util.scala:104:23] reg clr_uop_ppred_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_ppred_busy = clr_uop_ppred_busy; // @[util.scala:104:23] reg [6:0] clr_uop_stale_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_stale_pdst = clr_uop_stale_pdst; // @[util.scala:104:23] reg clr_uop_exception; // @[lsu.scala:1086:24] wire clr_uop_1_out_exception = clr_uop_exception; // @[util.scala:104:23] reg [63:0] clr_uop_exc_cause; // @[lsu.scala:1086:24] wire [63:0] clr_uop_1_out_exc_cause = clr_uop_exc_cause; // @[util.scala:104:23] reg [4:0] clr_uop_mem_cmd; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_mem_cmd = clr_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] clr_uop_mem_size; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_mem_size = clr_uop_mem_size; // @[util.scala:104:23] reg clr_uop_mem_signed; // @[lsu.scala:1086:24] wire clr_uop_1_out_mem_signed = clr_uop_mem_signed; // @[util.scala:104:23] reg clr_uop_uses_ldq; // @[lsu.scala:1086:24] wire clr_uop_1_out_uses_ldq = clr_uop_uses_ldq; // @[util.scala:104:23] reg clr_uop_uses_stq; // @[lsu.scala:1086:24] wire clr_uop_1_out_uses_stq = clr_uop_uses_stq; // @[util.scala:104:23] reg clr_uop_is_unique; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_unique = clr_uop_is_unique; // @[util.scala:104:23] reg clr_uop_flush_on_commit; // @[lsu.scala:1086:24] wire clr_uop_1_out_flush_on_commit = clr_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] clr_uop_csr_cmd; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_csr_cmd = clr_uop_csr_cmd; // @[util.scala:104:23] reg clr_uop_ldst_is_rs1; // @[lsu.scala:1086:24] wire clr_uop_1_out_ldst_is_rs1 = clr_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] clr_uop_ldst; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_ldst = clr_uop_ldst; // @[util.scala:104:23] reg [5:0] clr_uop_lrs1; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_lrs1 = clr_uop_lrs1; // @[util.scala:104:23] reg [5:0] clr_uop_lrs2; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_lrs2 = clr_uop_lrs2; // @[util.scala:104:23] reg [5:0] clr_uop_lrs3; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_lrs3 = clr_uop_lrs3; // @[util.scala:104:23] reg [1:0] clr_uop_dst_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_dst_rtype = clr_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_lrs1_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_lrs1_rtype = clr_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_lrs2_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_lrs2_rtype = clr_uop_lrs2_rtype; // @[util.scala:104:23] reg clr_uop_frs3_en; // @[lsu.scala:1086:24] wire clr_uop_1_out_frs3_en = clr_uop_frs3_en; // @[util.scala:104:23] reg clr_uop_fcn_dw; // @[lsu.scala:1086:24] wire clr_uop_1_out_fcn_dw = clr_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] clr_uop_fcn_op; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_fcn_op = clr_uop_fcn_op; // @[util.scala:104:23] reg clr_uop_fp_val; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_val = clr_uop_fp_val; // @[util.scala:104:23] reg [2:0] clr_uop_fp_rm; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_fp_rm = clr_uop_fp_rm; // @[util.scala:104:23] reg [1:0] clr_uop_fp_typ; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_fp_typ = clr_uop_fp_typ; // @[util.scala:104:23] reg clr_uop_xcpt_pf_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_xcpt_pf_if = clr_uop_xcpt_pf_if; // @[util.scala:104:23] reg clr_uop_xcpt_ae_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_xcpt_ae_if = clr_uop_xcpt_ae_if; // @[util.scala:104:23] reg clr_uop_xcpt_ma_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_xcpt_ma_if = clr_uop_xcpt_ma_if; // @[util.scala:104:23] reg clr_uop_bp_debug_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_bp_debug_if = clr_uop_bp_debug_if; // @[util.scala:104:23] reg clr_uop_bp_xcpt_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_bp_xcpt_if = clr_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] clr_uop_debug_fsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_debug_fsrc = clr_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] clr_uop_debug_tsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_debug_tsrc = clr_uop_debug_tsrc; // @[util.scala:104:23] wire [11:0] _clr_valid_1_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_br_mask; // @[util.scala:126:51] wire _clr_valid_1_T_1 = \|_clr_valid_1_T; // @[util.scala:126:{51,59}] wire _clr_valid_1_T_2 = _clr_valid_1_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _clr_valid_1_T_3 = ~_clr_valid_1_T_2; // @[util.scala:61:61] wire _clr_valid_1_T_4 = clr_valid & _clr_valid_1_T_3; // @[lsu.scala:1084:24, :1088:{41,44}] reg clr_valid_1; // @[lsu.scala:1088:30] wire [11:0] _clr_uop_1_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] clr_uop_1_out_br_mask; // @[util.scala:104:23] wire [11:0] _clr_uop_1_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_1_out_br_mask_T_1 = clr_uop_br_mask & _clr_uop_1_out_br_mask_T; // @[util.scala:93:{25,27}] assign clr_uop_1_out_br_mask = _clr_uop_1_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg [31:0] clr_uop_1_inst; // @[lsu.scala:1089:30] reg [31:0] clr_uop_1_debug_inst; // @[lsu.scala:1089:30] reg clr_uop_1_is_rvc; // @[lsu.scala:1089:30] reg [39:0] clr_uop_1_debug_pc; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_0; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_1; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_2; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_3; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_0; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_1; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_2; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_3; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_4; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_5; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_6; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_7; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_8; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_9; // @[lsu.scala:1089:30] reg clr_uop_1_iw_issued; // @[lsu.scala:1089:30] reg clr_uop_1_iw_issued_partial_agen; // @[lsu.scala:1089:30] reg clr_uop_1_iw_issued_partial_dgen; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_iw_p1_speculative_child; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_iw_p2_speculative_child; // @[lsu.scala:1089:30] reg clr_uop_1_iw_p1_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_iw_p2_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_iw_p3_bypass_hint; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_dis_col_sel; // @[lsu.scala:1089:30] reg [11:0] clr_uop_1_br_mask; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_br_tag; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_br_type; // @[lsu.scala:1089:30] reg clr_uop_1_is_sfb; // @[lsu.scala:1089:30] reg clr_uop_1_is_fence; // @[lsu.scala:1089:30] reg clr_uop_1_is_fencei; // @[lsu.scala:1089:30] reg clr_uop_1_is_sfence; // @[lsu.scala:1089:30] reg clr_uop_1_is_amo; // @[lsu.scala:1089:30] reg clr_uop_1_is_eret; // @[lsu.scala:1089:30] reg clr_uop_1_is_sys_pc2epc; // @[lsu.scala:1089:30] reg clr_uop_1_is_rocc; // @[lsu.scala:1089:30] reg clr_uop_1_is_mov; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_ftq_idx; // @[lsu.scala:1089:30] reg clr_uop_1_edge_inst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_pc_lob; // @[lsu.scala:1089:30] reg clr_uop_1_taken; // @[lsu.scala:1089:30] reg clr_uop_1_imm_rename; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_imm_sel; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_pimm; // @[lsu.scala:1089:30] reg [19:0] clr_uop_1_imm_packed; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_op1_sel; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_op2_sel; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ldst; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_wen; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ren1; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ren2; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ren3; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_swap12; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_swap23; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_fromint; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_toint; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_fma; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_div; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_sqrt; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_wflags; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_vec; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_rob_idx; // @[lsu.scala:1089:30] assign io_core_clr_bsy_0_bits_0 = clr_uop_1_rob_idx; // @[lsu.scala:211:7, :1089:30] reg [3:0] clr_uop_1_ldq_idx; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_stq_idx; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_rxq_idx; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_pdst; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_prs1; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_prs2; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_prs3; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_ppred; // @[lsu.scala:1089:30] reg clr_uop_1_prs1_busy; // @[lsu.scala:1089:30] reg clr_uop_1_prs2_busy; // @[lsu.scala:1089:30] reg clr_uop_1_prs3_busy; // @[lsu.scala:1089:30] reg clr_uop_1_ppred_busy; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_stale_pdst; // @[lsu.scala:1089:30] reg clr_uop_1_exception; // @[lsu.scala:1089:30] reg [63:0] clr_uop_1_exc_cause; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_mem_cmd; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_mem_size; // @[lsu.scala:1089:30] reg clr_uop_1_mem_signed; // @[lsu.scala:1089:30] reg clr_uop_1_uses_ldq; // @[lsu.scala:1089:30] reg clr_uop_1_uses_stq; // @[lsu.scala:1089:30] reg clr_uop_1_is_unique; // @[lsu.scala:1089:30] reg clr_uop_1_flush_on_commit; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_csr_cmd; // @[lsu.scala:1089:30] reg clr_uop_1_ldst_is_rs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_ldst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_lrs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_lrs2; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_lrs3; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_dst_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_lrs1_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_lrs2_rtype; // @[lsu.scala:1089:30] reg clr_uop_1_frs3_en; // @[lsu.scala:1089:30] reg clr_uop_1_fcn_dw; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_fcn_op; // @[lsu.scala:1089:30] reg clr_uop_1_fp_val; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_fp_rm; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_fp_typ; // @[lsu.scala:1089:30] reg clr_uop_1_xcpt_pf_if; // @[lsu.scala:1089:30] reg clr_uop_1_xcpt_ae_if; // @[lsu.scala:1089:30] reg clr_uop_1_xcpt_ma_if; // @[lsu.scala:1089:30] reg clr_uop_1_bp_debug_if; // @[lsu.scala:1089:30] reg clr_uop_1_bp_xcpt_if; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_debug_fsrc; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_debug_tsrc; // @[lsu.scala:1089:30] wire [3:0] _s_uop_T_1 = _s_uop_T; wire [31:0] clr_uop_out_inst = s_uop_inst; // @[util.scala:104:23] wire [31:0] clr_uop_out_debug_inst = s_uop_debug_inst; // @[util.scala:104:23] wire clr_uop_out_is_rvc = s_uop_is_rvc; // @[util.scala:104:23] wire [39:0] clr_uop_out_debug_pc = s_uop_debug_pc; // @[util.scala:104:23] wire clr_uop_out_iq_type_0 = s_uop_iq_type_0; // @[util.scala:104:23] wire clr_uop_out_iq_type_1 = s_uop_iq_type_1; // @[util.scala:104:23] wire clr_uop_out_iq_type_2 = s_uop_iq_type_2; // @[util.scala:104:23] wire clr_uop_out_iq_type_3 = s_uop_iq_type_3; // @[util.scala:104:23] wire clr_uop_out_fu_code_0 = s_uop_fu_code_0; // @[util.scala:104:23] wire clr_uop_out_fu_code_1 = s_uop_fu_code_1; // @[util.scala:104:23] wire clr_uop_out_fu_code_2 = s_uop_fu_code_2; // @[util.scala:104:23] wire clr_uop_out_fu_code_3 = s_uop_fu_code_3; // @[util.scala:104:23] wire clr_uop_out_fu_code_4 = s_uop_fu_code_4; // @[util.scala:104:23] wire clr_uop_out_fu_code_5 = s_uop_fu_code_5; // @[util.scala:104:23] wire clr_uop_out_fu_code_6 = s_uop_fu_code_6; // @[util.scala:104:23] wire clr_uop_out_fu_code_7 = s_uop_fu_code_7; // @[util.scala:104:23] wire clr_uop_out_fu_code_8 = s_uop_fu_code_8; // @[util.scala:104:23] wire clr_uop_out_fu_code_9 = s_uop_fu_code_9; // @[util.scala:104:23] wire clr_uop_out_iw_issued = s_uop_iw_issued; // @[util.scala:104:23] wire clr_uop_out_iw_issued_partial_agen = s_uop_iw_issued_partial_agen; // @[util.scala:104:23] wire clr_uop_out_iw_issued_partial_dgen = s_uop_iw_issued_partial_dgen; // @[util.scala:104:23] wire [1:0] clr_uop_out_iw_p1_speculative_child = s_uop_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] clr_uop_out_iw_p2_speculative_child = s_uop_iw_p2_speculative_child; // @[util.scala:104:23] wire clr_uop_out_iw_p1_bypass_hint = s_uop_iw_p1_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_iw_p2_bypass_hint = s_uop_iw_p2_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_iw_p3_bypass_hint = s_uop_iw_p3_bypass_hint; // @[util.scala:104:23] wire [1:0] clr_uop_out_dis_col_sel = s_uop_dis_col_sel; // @[util.scala:104:23] wire [3:0] clr_uop_out_br_tag = s_uop_br_tag; // @[util.scala:104:23] wire [3:0] clr_uop_out_br_type = s_uop_br_type; // @[util.scala:104:23] wire clr_uop_out_is_sfb = s_uop_is_sfb; // @[util.scala:104:23] wire clr_uop_out_is_fence = s_uop_is_fence; // @[util.scala:104:23] wire clr_uop_out_is_fencei = s_uop_is_fencei; // @[util.scala:104:23] wire clr_uop_out_is_sfence = s_uop_is_sfence; // @[util.scala:104:23] wire clr_uop_out_is_amo = s_uop_is_amo; // @[util.scala:104:23] wire clr_uop_out_is_eret = s_uop_is_eret; // @[util.scala:104:23] wire clr_uop_out_is_sys_pc2epc = s_uop_is_sys_pc2epc; // @[util.scala:104:23] wire clr_uop_out_is_rocc = s_uop_is_rocc; // @[util.scala:104:23] wire clr_uop_out_is_mov = s_uop_is_mov; // @[util.scala:104:23] wire [4:0] clr_uop_out_ftq_idx = s_uop_ftq_idx; // @[util.scala:104:23] wire clr_uop_out_edge_inst = s_uop_edge_inst; // @[util.scala:104:23] wire [5:0] clr_uop_out_pc_lob = s_uop_pc_lob; // @[util.scala:104:23] wire clr_uop_out_taken = s_uop_taken; // @[util.scala:104:23] wire clr_uop_out_imm_rename = s_uop_imm_rename; // @[util.scala:104:23] wire [2:0] clr_uop_out_imm_sel = s_uop_imm_sel; // @[util.scala:104:23] wire [4:0] clr_uop_out_pimm = s_uop_pimm; // @[util.scala:104:23] wire [19:0] clr_uop_out_imm_packed = s_uop_imm_packed; // @[util.scala:104:23] wire [1:0] clr_uop_out_op1_sel = s_uop_op1_sel; // @[util.scala:104:23] wire [2:0] clr_uop_out_op2_sel = s_uop_op2_sel; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ldst = s_uop_fp_ctrl_ldst; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_wen = s_uop_fp_ctrl_wen; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ren1 = s_uop_fp_ctrl_ren1; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ren2 = s_uop_fp_ctrl_ren2; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ren3 = s_uop_fp_ctrl_ren3; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_swap12 = s_uop_fp_ctrl_swap12; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_swap23 = s_uop_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] clr_uop_out_fp_ctrl_typeTagIn = s_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] clr_uop_out_fp_ctrl_typeTagOut = s_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_fromint = s_uop_fp_ctrl_fromint; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_toint = s_uop_fp_ctrl_toint; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_fastpipe = s_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_fma = s_uop_fp_ctrl_fma; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_div = s_uop_fp_ctrl_div; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_sqrt = s_uop_fp_ctrl_sqrt; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_wflags = s_uop_fp_ctrl_wflags; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_vec = s_uop_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] clr_uop_out_rob_idx = s_uop_rob_idx; // @[util.scala:104:23] wire [3:0] clr_uop_out_ldq_idx = s_uop_ldq_idx; // @[util.scala:104:23] wire [3:0] clr_uop_out_stq_idx = s_uop_stq_idx; // @[util.scala:104:23] wire [1:0] clr_uop_out_rxq_idx = s_uop_rxq_idx; // @[util.scala:104:23] wire [6:0] clr_uop_out_pdst = s_uop_pdst; // @[util.scala:104:23] wire [6:0] clr_uop_out_prs1 = s_uop_prs1; // @[util.scala:104:23] wire [6:0] clr_uop_out_prs2 = s_uop_prs2; // @[util.scala:104:23] wire [6:0] clr_uop_out_prs3 = s_uop_prs3; // @[util.scala:104:23] wire [4:0] clr_uop_out_ppred = s_uop_ppred; // @[util.scala:104:23] wire clr_uop_out_prs1_busy = s_uop_prs1_busy; // @[util.scala:104:23] wire clr_uop_out_prs2_busy = s_uop_prs2_busy; // @[util.scala:104:23] wire clr_uop_out_prs3_busy = s_uop_prs3_busy; // @[util.scala:104:23] wire clr_uop_out_ppred_busy = s_uop_ppred_busy; // @[util.scala:104:23] wire [6:0] clr_uop_out_stale_pdst = s_uop_stale_pdst; // @[util.scala:104:23] wire clr_uop_out_exception = s_uop_exception; // @[util.scala:104:23] wire [63:0] clr_uop_out_exc_cause = s_uop_exc_cause; // @[util.scala:104:23] wire [4:0] clr_uop_out_mem_cmd = s_uop_mem_cmd; // @[util.scala:104:23] wire [1:0] clr_uop_out_mem_size = s_uop_mem_size; // @[util.scala:104:23] wire clr_uop_out_mem_signed = s_uop_mem_signed; // @[util.scala:104:23] wire clr_uop_out_uses_ldq = s_uop_uses_ldq; // @[util.scala:104:23] wire clr_uop_out_uses_stq = s_uop_uses_stq; // @[util.scala:104:23] wire clr_uop_out_is_unique = s_uop_is_unique; // @[util.scala:104:23] wire clr_uop_out_flush_on_commit = s_uop_flush_on_commit; // @[util.scala:104:23] wire [2:0] clr_uop_out_csr_cmd = s_uop_csr_cmd; // @[util.scala:104:23] wire clr_uop_out_ldst_is_rs1 = s_uop_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_ldst = s_uop_ldst; // @[util.scala:104:23] wire [5:0] clr_uop_out_lrs1 = s_uop_lrs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_lrs2 = s_uop_lrs2; // @[util.scala:104:23] wire [5:0] clr_uop_out_lrs3 = s_uop_lrs3; // @[util.scala:104:23] wire [1:0] clr_uop_out_dst_rtype = s_uop_dst_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_lrs1_rtype = s_uop_lrs1_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_lrs2_rtype = s_uop_lrs2_rtype; // @[util.scala:104:23] wire clr_uop_out_frs3_en = s_uop_frs3_en; // @[util.scala:104:23] wire clr_uop_out_fcn_dw = s_uop_fcn_dw; // @[util.scala:104:23] wire [4:0] clr_uop_out_fcn_op = s_uop_fcn_op; // @[util.scala:104:23] wire clr_uop_out_fp_val = s_uop_fp_val; // @[util.scala:104:23] wire [2:0] clr_uop_out_fp_rm = s_uop_fp_rm; // @[util.scala:104:23] wire [1:0] clr_uop_out_fp_typ = s_uop_fp_typ; // @[util.scala:104:23] wire clr_uop_out_xcpt_pf_if = s_uop_xcpt_pf_if; // @[util.scala:104:23] wire clr_uop_out_xcpt_ae_if = s_uop_xcpt_ae_if; // @[util.scala:104:23] wire clr_uop_out_xcpt_ma_if = s_uop_xcpt_ma_if; // @[util.scala:104:23] wire clr_uop_out_bp_debug_if = s_uop_bp_debug_if; // @[util.scala:104:23] wire clr_uop_out_bp_xcpt_if = s_uop_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] clr_uop_out_debug_fsrc = s_uop_debug_fsrc; // @[util.scala:104:23] wire [2:0] clr_uop_out_debug_tsrc = s_uop_debug_tsrc; // @[util.scala:104:23] wire [11:0] s_uop_br_mask; // @[lsu.scala:1093:25] assign s_uop_inst = _GEN_200[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_inst = _GEN_201[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_rvc = _GEN_202[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_pc = _GEN_203[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_0 = _GEN_204[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_1 = _GEN_205[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_2 = _GEN_206[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_3 = _GEN_207[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_0 = _GEN_208[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_1 = _GEN_209[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_2 = _GEN_210[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_3 = _GEN_211[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_4 = _GEN_212[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_5 = _GEN_213[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_6 = _GEN_214[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_7 = _GEN_215[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_8 = _GEN_216[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_9 = _GEN_217[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_issued = _GEN_218[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_issued_partial_agen = _GEN_219[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_issued_partial_dgen = _GEN_220[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p1_speculative_child = _GEN_221[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p2_speculative_child = _GEN_222[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p1_bypass_hint = _GEN_223[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p2_bypass_hint = _GEN_224[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p3_bypass_hint = _GEN_225[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_dis_col_sel = _GEN_226[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_br_mask = _GEN_227[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_br_tag = _GEN_228[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_br_type = _GEN_229[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_sfb = _GEN_230[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_fence = _GEN_231[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_fencei = _GEN_232[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_sfence = _GEN_233[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_amo = _GEN_234[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_eret = _GEN_235[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_sys_pc2epc = _GEN_236[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_rocc = _GEN_237[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_mov = _GEN_238[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ftq_idx = _GEN_239[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_edge_inst = _GEN_240[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_pc_lob = _GEN_241[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_taken = _GEN_242[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_imm_rename = _GEN_243[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_imm_sel = _GEN_244[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_pimm = _GEN_245[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_imm_packed = _GEN_246[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_op1_sel = _GEN_247[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_op2_sel = _GEN_248[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ldst = _GEN_249[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_wen = _GEN_250[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ren1 = _GEN_251[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ren2 = _GEN_252[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ren3 = _GEN_253[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_swap12 = _GEN_254[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_swap23 = _GEN_255[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_typeTagIn = _GEN_256[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_typeTagOut = _GEN_257[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_fromint = _GEN_258[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_toint = _GEN_259[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_fastpipe = _GEN_260[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_fma = _GEN_261[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_div = _GEN_262[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_sqrt = _GEN_263[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_wflags = _GEN_264[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_vec = _GEN_265[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_rob_idx = _GEN_266[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ldq_idx = _GEN_267[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_stq_idx = _GEN_268[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_rxq_idx = _GEN_269[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_pdst = _GEN_270[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs1 = _GEN_271[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs2 = _GEN_272[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs3 = _GEN_273[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ppred = _GEN_274[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs1_busy = _GEN_275[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs2_busy = _GEN_276[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs3_busy = _GEN_277[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ppred_busy = _GEN_278[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_stale_pdst = _GEN_279[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_exception = _GEN_280[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_exc_cause = _GEN_281[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_mem_cmd = _GEN_282[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_mem_size = _GEN_283[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_mem_signed = _GEN_284[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_uses_ldq = _GEN_285[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_uses_stq = _GEN_286[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_unique = _GEN_287[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_flush_on_commit = _GEN_288[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_csr_cmd = _GEN_289[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ldst_is_rs1 = _GEN_290[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ldst = _GEN_291[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs1 = _GEN_292[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs2 = _GEN_293[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs3 = _GEN_294[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_dst_rtype = _GEN_295[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs1_rtype = _GEN_296[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs2_rtype = _GEN_297[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_frs3_en = _GEN_298[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fcn_dw = _GEN_299[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fcn_op = _GEN_300[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_val = _GEN_301[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_rm = _GEN_302[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_typ = _GEN_303[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_xcpt_pf_if = _GEN_304[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_xcpt_ae_if = _GEN_305[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_xcpt_ma_if = _GEN_306[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_bp_debug_if = _GEN_307[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_bp_xcpt_if = _GEN_308[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_fsrc = _GEN_309[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_tsrc = _GEN_310[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] wire [11:0] _clr_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] clr_uop_out_br_mask; // @[util.scala:104:23] wire [11:0] _clr_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_out_br_mask_T_1 = s_uop_br_mask & _clr_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign clr_uop_out_br_mask = _clr_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire [11:0] _io_core_clr_bsy_0_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_1_br_mask; // @[util.scala:126:51] wire _io_core_clr_bsy_0_valid_T_1 = \|_io_core_clr_bsy_0_valid_T; // @[util.scala:126:{51,59}] wire _io_core_clr_bsy_0_valid_T_2 = _io_core_clr_bsy_0_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_clr_bsy_0_valid_T_3 = ~_io_core_clr_bsy_0_valid_T_2; // @[util.scala:61:61] assign _io_core_clr_bsy_0_valid_T_4 = clr_valid_1 & _io_core_clr_bsy_0_valid_T_3; // @[lsu.scala:1088:30, :1107:{45,48}] assign io_core_clr_bsy_0_valid_0 = _io_core_clr_bsy_0_valid_T_4; // @[lsu.scala:211:7, :1107:45] wire [3:0] _T_236 = stq_clr_head_idx + 4'h1; // @[util.scala:211:14] reg clr_valid_2; // @[lsu.scala:1084:24] reg [31:0] clr_uop_2_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_1_inst = clr_uop_2_inst; // @[util.scala:104:23] reg [31:0] clr_uop_2_debug_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_1_debug_inst = clr_uop_2_debug_inst; // @[util.scala:104:23] reg clr_uop_2_is_rvc; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_rvc = clr_uop_2_is_rvc; // @[util.scala:104:23] reg [39:0] clr_uop_2_debug_pc; // @[lsu.scala:1086:24] wire [39:0] clr_uop_1_out_1_debug_pc = clr_uop_2_debug_pc; // @[util.scala:104:23] reg clr_uop_2_iq_type_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_0 = clr_uop_2_iq_type_0; // @[util.scala:104:23] reg clr_uop_2_iq_type_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_1 = clr_uop_2_iq_type_1; // @[util.scala:104:23] reg clr_uop_2_iq_type_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_2 = clr_uop_2_iq_type_2; // @[util.scala:104:23] reg clr_uop_2_iq_type_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_3 = clr_uop_2_iq_type_3; // @[util.scala:104:23] reg clr_uop_2_fu_code_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_0 = clr_uop_2_fu_code_0; // @[util.scala:104:23] reg clr_uop_2_fu_code_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_1 = clr_uop_2_fu_code_1; // @[util.scala:104:23] reg clr_uop_2_fu_code_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_2 = clr_uop_2_fu_code_2; // @[util.scala:104:23] reg clr_uop_2_fu_code_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_3 = clr_uop_2_fu_code_3; // @[util.scala:104:23] reg clr_uop_2_fu_code_4; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_4 = clr_uop_2_fu_code_4; // @[util.scala:104:23] reg clr_uop_2_fu_code_5; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_5 = clr_uop_2_fu_code_5; // @[util.scala:104:23] reg clr_uop_2_fu_code_6; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_6 = clr_uop_2_fu_code_6; // @[util.scala:104:23] reg clr_uop_2_fu_code_7; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_7 = clr_uop_2_fu_code_7; // @[util.scala:104:23] reg clr_uop_2_fu_code_8; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_8 = clr_uop_2_fu_code_8; // @[util.scala:104:23] reg clr_uop_2_fu_code_9; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_9 = clr_uop_2_fu_code_9; // @[util.scala:104:23] reg clr_uop_2_iw_issued; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_issued = clr_uop_2_iw_issued; // @[util.scala:104:23] reg clr_uop_2_iw_issued_partial_agen; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_issued_partial_agen = clr_uop_2_iw_issued_partial_agen; // @[util.scala:104:23] reg clr_uop_2_iw_issued_partial_dgen; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_issued_partial_dgen = clr_uop_2_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] clr_uop_2_iw_p1_speculative_child; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_iw_p1_speculative_child = clr_uop_2_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] clr_uop_2_iw_p2_speculative_child; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_iw_p2_speculative_child = clr_uop_2_iw_p2_speculative_child; // @[util.scala:104:23] reg clr_uop_2_iw_p1_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_p1_bypass_hint = clr_uop_2_iw_p1_bypass_hint; // @[util.scala:104:23] reg clr_uop_2_iw_p2_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_p2_bypass_hint = clr_uop_2_iw_p2_bypass_hint; // @[util.scala:104:23] reg clr_uop_2_iw_p3_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_p3_bypass_hint = clr_uop_2_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] clr_uop_2_dis_col_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_dis_col_sel = clr_uop_2_dis_col_sel; // @[util.scala:104:23] reg [11:0] clr_uop_2_br_mask; // @[lsu.scala:1086:24] reg [3:0] clr_uop_2_br_tag; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_1_br_tag = clr_uop_2_br_tag; // @[util.scala:104:23] reg [3:0] clr_uop_2_br_type; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_1_br_type = clr_uop_2_br_type; // @[util.scala:104:23] reg clr_uop_2_is_sfb; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_sfb = clr_uop_2_is_sfb; // @[util.scala:104:23] reg clr_uop_2_is_fence; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_fence = clr_uop_2_is_fence; // @[util.scala:104:23] reg clr_uop_2_is_fencei; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_fencei = clr_uop_2_is_fencei; // @[util.scala:104:23] reg clr_uop_2_is_sfence; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_sfence = clr_uop_2_is_sfence; // @[util.scala:104:23] reg clr_uop_2_is_amo; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_amo = clr_uop_2_is_amo; // @[util.scala:104:23] reg clr_uop_2_is_eret; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_eret = clr_uop_2_is_eret; // @[util.scala:104:23] reg clr_uop_2_is_sys_pc2epc; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_sys_pc2epc = clr_uop_2_is_sys_pc2epc; // @[util.scala:104:23] reg clr_uop_2_is_rocc; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_rocc = clr_uop_2_is_rocc; // @[util.scala:104:23] reg clr_uop_2_is_mov; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_mov = clr_uop_2_is_mov; // @[util.scala:104:23] reg [4:0] clr_uop_2_ftq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_ftq_idx = clr_uop_2_ftq_idx; // @[util.scala:104:23] reg clr_uop_2_edge_inst; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_edge_inst = clr_uop_2_edge_inst; // @[util.scala:104:23] reg [5:0] clr_uop_2_pc_lob; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_pc_lob = clr_uop_2_pc_lob; // @[util.scala:104:23] reg clr_uop_2_taken; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_taken = clr_uop_2_taken; // @[util.scala:104:23] reg clr_uop_2_imm_rename; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_imm_rename = clr_uop_2_imm_rename; // @[util.scala:104:23] reg [2:0] clr_uop_2_imm_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_imm_sel = clr_uop_2_imm_sel; // @[util.scala:104:23] reg [4:0] clr_uop_2_pimm; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_pimm = clr_uop_2_pimm; // @[util.scala:104:23] reg [19:0] clr_uop_2_imm_packed; // @[lsu.scala:1086:24] wire [19:0] clr_uop_1_out_1_imm_packed = clr_uop_2_imm_packed; // @[util.scala:104:23] reg [1:0] clr_uop_2_op1_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_op1_sel = clr_uop_2_op1_sel; // @[util.scala:104:23] reg [2:0] clr_uop_2_op2_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_op2_sel = clr_uop_2_op2_sel; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ldst; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ldst = clr_uop_2_fp_ctrl_ldst; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_wen; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_wen = clr_uop_2_fp_ctrl_wen; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ren1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ren1 = clr_uop_2_fp_ctrl_ren1; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ren2; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ren2 = clr_uop_2_fp_ctrl_ren2; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ren3; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ren3 = clr_uop_2_fp_ctrl_ren3; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_swap12; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_swap12 = clr_uop_2_fp_ctrl_swap12; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_swap23; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_swap23 = clr_uop_2_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] clr_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_fp_ctrl_typeTagIn = clr_uop_2_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] clr_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_fp_ctrl_typeTagOut = clr_uop_2_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_fromint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_fromint = clr_uop_2_fp_ctrl_fromint; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_toint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_toint = clr_uop_2_fp_ctrl_toint; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_fastpipe = clr_uop_2_fp_ctrl_fastpipe; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_fma; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_fma = clr_uop_2_fp_ctrl_fma; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_div; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_div = clr_uop_2_fp_ctrl_div; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_sqrt; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_sqrt = clr_uop_2_fp_ctrl_sqrt; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_wflags; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_wflags = clr_uop_2_fp_ctrl_wflags; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_vec; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_vec = clr_uop_2_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] clr_uop_2_rob_idx; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_rob_idx = clr_uop_2_rob_idx; // @[util.scala:104:23] reg [3:0] clr_uop_2_ldq_idx; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_1_ldq_idx = clr_uop_2_ldq_idx; // @[util.scala:104:23] reg [3:0] clr_uop_2_stq_idx; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_1_stq_idx = clr_uop_2_stq_idx; // @[util.scala:104:23] reg [1:0] clr_uop_2_rxq_idx; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_rxq_idx = clr_uop_2_rxq_idx; // @[util.scala:104:23] reg [6:0] clr_uop_2_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_pdst = clr_uop_2_pdst; // @[util.scala:104:23] reg [6:0] clr_uop_2_prs1; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_prs1 = clr_uop_2_prs1; // @[util.scala:104:23] reg [6:0] clr_uop_2_prs2; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_prs2 = clr_uop_2_prs2; // @[util.scala:104:23] reg [6:0] clr_uop_2_prs3; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_prs3 = clr_uop_2_prs3; // @[util.scala:104:23] reg [4:0] clr_uop_2_ppred; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_ppred = clr_uop_2_ppred; // @[util.scala:104:23] reg clr_uop_2_prs1_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_prs1_busy = clr_uop_2_prs1_busy; // @[util.scala:104:23] reg clr_uop_2_prs2_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_prs2_busy = clr_uop_2_prs2_busy; // @[util.scala:104:23] reg clr_uop_2_prs3_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_prs3_busy = clr_uop_2_prs3_busy; // @[util.scala:104:23] reg clr_uop_2_ppred_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_ppred_busy = clr_uop_2_ppred_busy; // @[util.scala:104:23] reg [6:0] clr_uop_2_stale_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_stale_pdst = clr_uop_2_stale_pdst; // @[util.scala:104:23] reg clr_uop_2_exception; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_exception = clr_uop_2_exception; // @[util.scala:104:23] reg [63:0] clr_uop_2_exc_cause; // @[lsu.scala:1086:24] wire [63:0] clr_uop_1_out_1_exc_cause = clr_uop_2_exc_cause; // @[util.scala:104:23] reg [4:0] clr_uop_2_mem_cmd; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_mem_cmd = clr_uop_2_mem_cmd; // @[util.scala:104:23] reg [1:0] clr_uop_2_mem_size; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_mem_size = clr_uop_2_mem_size; // @[util.scala:104:23] reg clr_uop_2_mem_signed; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_mem_signed = clr_uop_2_mem_signed; // @[util.scala:104:23] reg clr_uop_2_uses_ldq; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_uses_ldq = clr_uop_2_uses_ldq; // @[util.scala:104:23] reg clr_uop_2_uses_stq; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_uses_stq = clr_uop_2_uses_stq; // @[util.scala:104:23] reg clr_uop_2_is_unique; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_unique = clr_uop_2_is_unique; // @[util.scala:104:23] reg clr_uop_2_flush_on_commit; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_flush_on_commit = clr_uop_2_flush_on_commit; // @[util.scala:104:23] reg [2:0] clr_uop_2_csr_cmd; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_csr_cmd = clr_uop_2_csr_cmd; // @[util.scala:104:23] reg clr_uop_2_ldst_is_rs1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_ldst_is_rs1 = clr_uop_2_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] clr_uop_2_ldst; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_ldst = clr_uop_2_ldst; // @[util.scala:104:23] reg [5:0] clr_uop_2_lrs1; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_lrs1 = clr_uop_2_lrs1; // @[util.scala:104:23] reg [5:0] clr_uop_2_lrs2; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_lrs2 = clr_uop_2_lrs2; // @[util.scala:104:23] reg [5:0] clr_uop_2_lrs3; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_lrs3 = clr_uop_2_lrs3; // @[util.scala:104:23] reg [1:0] clr_uop_2_dst_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_dst_rtype = clr_uop_2_dst_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_2_lrs1_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_lrs1_rtype = clr_uop_2_lrs1_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_2_lrs2_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_lrs2_rtype = clr_uop_2_lrs2_rtype; // @[util.scala:104:23] reg clr_uop_2_frs3_en; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_frs3_en = clr_uop_2_frs3_en; // @[util.scala:104:23] reg clr_uop_2_fcn_dw; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fcn_dw = clr_uop_2_fcn_dw; // @[util.scala:104:23] reg [4:0] clr_uop_2_fcn_op; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_fcn_op = clr_uop_2_fcn_op; // @[util.scala:104:23] reg clr_uop_2_fp_val; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_val = clr_uop_2_fp_val; // @[util.scala:104:23] reg [2:0] clr_uop_2_fp_rm; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_fp_rm = clr_uop_2_fp_rm; // @[util.scala:104:23] reg [1:0] clr_uop_2_fp_typ; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_fp_typ = clr_uop_2_fp_typ; // @[util.scala:104:23] reg clr_uop_2_xcpt_pf_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_xcpt_pf_if = clr_uop_2_xcpt_pf_if; // @[util.scala:104:23] reg clr_uop_2_xcpt_ae_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_xcpt_ae_if = clr_uop_2_xcpt_ae_if; // @[util.scala:104:23] reg clr_uop_2_xcpt_ma_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_xcpt_ma_if = clr_uop_2_xcpt_ma_if; // @[util.scala:104:23] reg clr_uop_2_bp_debug_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_bp_debug_if = clr_uop_2_bp_debug_if; // @[util.scala:104:23] reg clr_uop_2_bp_xcpt_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_bp_xcpt_if = clr_uop_2_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] clr_uop_2_debug_fsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_debug_fsrc = clr_uop_2_debug_fsrc; // @[util.scala:104:23] reg [2:0] clr_uop_2_debug_tsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_debug_tsrc = clr_uop_2_debug_tsrc; // @[util.scala:104:23] wire [11:0] _clr_valid_1_T_5 = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_2_br_mask; // @[util.scala:126:51] wire _clr_valid_1_T_6 = \|_clr_valid_1_T_5; // @[util.scala:126:{51,59}] wire _clr_valid_1_T_7 = _clr_valid_1_T_6 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _clr_valid_1_T_8 = ~_clr_valid_1_T_7; // @[util.scala:61:61] wire _clr_valid_1_T_9 = clr_valid_2 & _clr_valid_1_T_8; // @[lsu.scala:1084:24, :1088:{41,44}] reg clr_valid_1_1; // @[lsu.scala:1088:30] wire [11:0] _clr_uop_1_out_br_mask_T_3; // @[util.scala:93:25] wire [11:0] clr_uop_1_out_1_br_mask; // @[util.scala:104:23] wire [11:0] _clr_uop_1_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_1_out_br_mask_T_3 = clr_uop_2_br_mask & _clr_uop_1_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign clr_uop_1_out_1_br_mask = _clr_uop_1_out_br_mask_T_3; // @[util.scala:93:25, :104:23] reg [31:0] clr_uop_1_1_inst; // @[lsu.scala:1089:30] reg [31:0] clr_uop_1_1_debug_inst; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_rvc; // @[lsu.scala:1089:30] reg [39:0] clr_uop_1_1_debug_pc; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_0; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_1; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_2; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_3; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_0; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_1; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_2; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_3; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_4; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_5; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_6; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_7; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_8; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_9; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_issued; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_issued_partial_agen; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_issued_partial_dgen; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_iw_p1_speculative_child; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_iw_p2_speculative_child; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_p1_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_p2_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_p3_bypass_hint; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_dis_col_sel; // @[lsu.scala:1089:30] reg [11:0] clr_uop_1_1_br_mask; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_1_br_tag; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_1_br_type; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_sfb; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_fence; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_fencei; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_sfence; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_amo; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_eret; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_sys_pc2epc; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_rocc; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_mov; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_ftq_idx; // @[lsu.scala:1089:30] reg clr_uop_1_1_edge_inst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_pc_lob; // @[lsu.scala:1089:30] reg clr_uop_1_1_taken; // @[lsu.scala:1089:30] reg clr_uop_1_1_imm_rename; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_imm_sel; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_pimm; // @[lsu.scala:1089:30] reg [19:0] clr_uop_1_1_imm_packed; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_op1_sel; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_op2_sel; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ldst; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_wen; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ren1; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ren2; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ren3; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_swap12; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_swap23; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_fp_ctrl_typeTagIn; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_fp_ctrl_typeTagOut; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_fromint; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_toint; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_fastpipe; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_fma; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_div; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_sqrt; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_wflags; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_vec; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_rob_idx; // @[lsu.scala:1089:30] assign io_core_clr_bsy_1_bits_0 = clr_uop_1_1_rob_idx; // @[lsu.scala:211:7, :1089:30] reg [3:0] clr_uop_1_1_ldq_idx; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_1_stq_idx; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_rxq_idx; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_pdst; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_prs1; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_prs2; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_prs3; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_ppred; // @[lsu.scala:1089:30] reg clr_uop_1_1_prs1_busy; // @[lsu.scala:1089:30] reg clr_uop_1_1_prs2_busy; // @[lsu.scala:1089:30] reg clr_uop_1_1_prs3_busy; // @[lsu.scala:1089:30] reg clr_uop_1_1_ppred_busy; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_stale_pdst; // @[lsu.scala:1089:30] reg clr_uop_1_1_exception; // @[lsu.scala:1089:30] reg [63:0] clr_uop_1_1_exc_cause; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_mem_cmd; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_mem_size; // @[lsu.scala:1089:30] reg clr_uop_1_1_mem_signed; // @[lsu.scala:1089:30] reg clr_uop_1_1_uses_ldq; // @[lsu.scala:1089:30] reg clr_uop_1_1_uses_stq; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_unique; // @[lsu.scala:1089:30] reg clr_uop_1_1_flush_on_commit; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_csr_cmd; // @[lsu.scala:1089:30] reg clr_uop_1_1_ldst_is_rs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_ldst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_lrs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_lrs2; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_lrs3; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_dst_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_lrs1_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_lrs2_rtype; // @[lsu.scala:1089:30] reg clr_uop_1_1_frs3_en; // @[lsu.scala:1089:30] reg clr_uop_1_1_fcn_dw; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_fcn_op; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_val; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_fp_rm; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_fp_typ; // @[lsu.scala:1089:30] reg clr_uop_1_1_xcpt_pf_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_xcpt_ae_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_xcpt_ma_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_bp_debug_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_bp_xcpt_if; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_debug_fsrc; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_debug_tsrc; // @[lsu.scala:1089:30] wire [31:0] clr_uop_out_1_inst = s_uop_1_inst; // @[util.scala:104:23] wire [31:0] clr_uop_out_1_debug_inst = s_uop_1_debug_inst; // @[util.scala:104:23] wire clr_uop_out_1_is_rvc = s_uop_1_is_rvc; // @[util.scala:104:23] wire [39:0] clr_uop_out_1_debug_pc = s_uop_1_debug_pc; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_0 = s_uop_1_iq_type_0; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_1 = s_uop_1_iq_type_1; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_2 = s_uop_1_iq_type_2; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_3 = s_uop_1_iq_type_3; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_0 = s_uop_1_fu_code_0; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_1 = s_uop_1_fu_code_1; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_2 = s_uop_1_fu_code_2; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_3 = s_uop_1_fu_code_3; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_4 = s_uop_1_fu_code_4; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_5 = s_uop_1_fu_code_5; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_6 = s_uop_1_fu_code_6; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_7 = s_uop_1_fu_code_7; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_8 = s_uop_1_fu_code_8; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_9 = s_uop_1_fu_code_9; // @[util.scala:104:23] wire clr_uop_out_1_iw_issued = s_uop_1_iw_issued; // @[util.scala:104:23] wire clr_uop_out_1_iw_issued_partial_agen = s_uop_1_iw_issued_partial_agen; // @[util.scala:104:23] wire clr_uop_out_1_iw_issued_partial_dgen = s_uop_1_iw_issued_partial_dgen; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_iw_p1_speculative_child = s_uop_1_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_iw_p2_speculative_child = s_uop_1_iw_p2_speculative_child; // @[util.scala:104:23] wire clr_uop_out_1_iw_p1_bypass_hint = s_uop_1_iw_p1_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_1_iw_p2_bypass_hint = s_uop_1_iw_p2_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_1_iw_p3_bypass_hint = s_uop_1_iw_p3_bypass_hint; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_dis_col_sel = s_uop_1_dis_col_sel; // @[util.scala:104:23] wire [3:0] clr_uop_out_1_br_tag = s_uop_1_br_tag; // @[util.scala:104:23] wire [3:0] clr_uop_out_1_br_type = s_uop_1_br_type; // @[util.scala:104:23] wire clr_uop_out_1_is_sfb = s_uop_1_is_sfb; // @[util.scala:104:23] wire clr_uop_out_1_is_fence = s_uop_1_is_fence; // @[util.scala:104:23] wire clr_uop_out_1_is_fencei = s_uop_1_is_fencei; // @[util.scala:104:23] wire clr_uop_out_1_is_sfence = s_uop_1_is_sfence; // @[util.scala:104:23] wire clr_uop_out_1_is_amo = s_uop_1_is_amo; // @[util.scala:104:23] wire clr_uop_out_1_is_eret = s_uop_1_is_eret; // @[util.scala:104:23] wire clr_uop_out_1_is_sys_pc2epc = s_uop_1_is_sys_pc2epc; // @[util.scala:104:23] wire clr_uop_out_1_is_rocc = s_uop_1_is_rocc; // @[util.scala:104:23] wire clr_uop_out_1_is_mov = s_uop_1_is_mov; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_ftq_idx = s_uop_1_ftq_idx; // @[util.scala:104:23] wire clr_uop_out_1_edge_inst = s_uop_1_edge_inst; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_pc_lob = s_uop_1_pc_lob; // @[util.scala:104:23] wire clr_uop_out_1_taken = s_uop_1_taken; // @[util.scala:104:23] wire clr_uop_out_1_imm_rename = s_uop_1_imm_rename; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_imm_sel = s_uop_1_imm_sel; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_pimm = s_uop_1_pimm; // @[util.scala:104:23] wire [19:0] clr_uop_out_1_imm_packed = s_uop_1_imm_packed; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_op1_sel = s_uop_1_op1_sel; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_op2_sel = s_uop_1_op2_sel; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ldst = s_uop_1_fp_ctrl_ldst; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_wen = s_uop_1_fp_ctrl_wen; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ren1 = s_uop_1_fp_ctrl_ren1; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ren2 = s_uop_1_fp_ctrl_ren2; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ren3 = s_uop_1_fp_ctrl_ren3; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_swap12 = s_uop_1_fp_ctrl_swap12; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_swap23 = s_uop_1_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_fp_ctrl_typeTagIn = s_uop_1_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_fp_ctrl_typeTagOut = s_uop_1_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_fromint = s_uop_1_fp_ctrl_fromint; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_toint = s_uop_1_fp_ctrl_toint; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_fastpipe = s_uop_1_fp_ctrl_fastpipe; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_fma = s_uop_1_fp_ctrl_fma; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_div = s_uop_1_fp_ctrl_div; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_sqrt = s_uop_1_fp_ctrl_sqrt; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_wflags = s_uop_1_fp_ctrl_wflags; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_vec = s_uop_1_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_rob_idx = s_uop_1_rob_idx; // @[util.scala:104:23] wire [3:0] clr_uop_out_1_ldq_idx = s_uop_1_ldq_idx; // @[util.scala:104:23] wire [3:0] clr_uop_out_1_stq_idx = s_uop_1_stq_idx; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_rxq_idx = s_uop_1_rxq_idx; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_pdst = s_uop_1_pdst; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_prs1 = s_uop_1_prs1; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_prs2 = s_uop_1_prs2; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_prs3 = s_uop_1_prs3; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_ppred = s_uop_1_ppred; // @[util.scala:104:23] wire clr_uop_out_1_prs1_busy = s_uop_1_prs1_busy; // @[util.scala:104:23] wire clr_uop_out_1_prs2_busy = s_uop_1_prs2_busy; // @[util.scala:104:23] wire clr_uop_out_1_prs3_busy = s_uop_1_prs3_busy; // @[util.scala:104:23] wire clr_uop_out_1_ppred_busy = s_uop_1_ppred_busy; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_stale_pdst = s_uop_1_stale_pdst; // @[util.scala:104:23] wire clr_uop_out_1_exception = s_uop_1_exception; // @[util.scala:104:23] wire [63:0] clr_uop_out_1_exc_cause = s_uop_1_exc_cause; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_mem_cmd = s_uop_1_mem_cmd; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_mem_size = s_uop_1_mem_size; // @[util.scala:104:23] wire clr_uop_out_1_mem_signed = s_uop_1_mem_signed; // @[util.scala:104:23] wire clr_uop_out_1_uses_ldq = s_uop_1_uses_ldq; // @[util.scala:104:23] wire clr_uop_out_1_uses_stq = s_uop_1_uses_stq; // @[util.scala:104:23] wire clr_uop_out_1_is_unique = s_uop_1_is_unique; // @[util.scala:104:23] wire clr_uop_out_1_flush_on_commit = s_uop_1_flush_on_commit; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_csr_cmd = s_uop_1_csr_cmd; // @[util.scala:104:23] wire clr_uop_out_1_ldst_is_rs1 = s_uop_1_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_ldst = s_uop_1_ldst; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_lrs1 = s_uop_1_lrs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_lrs2 = s_uop_1_lrs2; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_lrs3 = s_uop_1_lrs3; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_dst_rtype = s_uop_1_dst_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_lrs1_rtype = s_uop_1_lrs1_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_lrs2_rtype = s_uop_1_lrs2_rtype; // @[util.scala:104:23] wire clr_uop_out_1_frs3_en = s_uop_1_frs3_en; // @[util.scala:104:23] wire clr_uop_out_1_fcn_dw = s_uop_1_fcn_dw; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_fcn_op = s_uop_1_fcn_op; // @[util.scala:104:23] wire clr_uop_out_1_fp_val = s_uop_1_fp_val; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_fp_rm = s_uop_1_fp_rm; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_fp_typ = s_uop_1_fp_typ; // @[util.scala:104:23] wire clr_uop_out_1_xcpt_pf_if = s_uop_1_xcpt_pf_if; // @[util.scala:104:23] wire clr_uop_out_1_xcpt_ae_if = s_uop_1_xcpt_ae_if; // @[util.scala:104:23] wire clr_uop_out_1_xcpt_ma_if = s_uop_1_xcpt_ma_if; // @[util.scala:104:23] wire clr_uop_out_1_bp_debug_if = s_uop_1_bp_debug_if; // @[util.scala:104:23] wire clr_uop_out_1_bp_xcpt_if = s_uop_1_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_debug_fsrc = s_uop_1_debug_fsrc; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_debug_tsrc = s_uop_1_debug_tsrc; // @[util.scala:104:23] wire [11:0] s_uop_1_br_mask; // @[lsu.scala:1093:25] assign s_uop_1_inst = _GEN_200[_T_236]; // @[util.scala:211:14] assign s_uop_1_debug_inst = _GEN_201[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_rvc = _GEN_202[_T_236]; // @[util.scala:211:14] assign s_uop_1_debug_pc = _GEN_203[_T_236]; // @[util.scala:211:14] assign s_uop_1_iq_type_0 = _GEN_204[_T_236]; // @[util.scala:211:14] assign s_uop_1_iq_type_1 = _GEN_205[_T_236]; // @[util.scala:211:14] assign s_uop_1_iq_type_2 = _GEN_206[_T_236]; // @[util.scala:211:14] assign s_uop_1_iq_type_3 = _GEN_207[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_0 = _GEN_208[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_1 = _GEN_209[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_2 = _GEN_210[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_3 = _GEN_211[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_4 = _GEN_212[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_5 = _GEN_213[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_6 = _GEN_214[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_7 = _GEN_215[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_8 = _GEN_216[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_9 = _GEN_217[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_issued = _GEN_218[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_issued_partial_agen = _GEN_219[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_issued_partial_dgen = _GEN_220[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_p1_speculative_child = _GEN_221[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_p2_speculative_child = _GEN_222[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_p1_bypass_hint = _GEN_223[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_p2_bypass_hint = _GEN_224[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_p3_bypass_hint = _GEN_225[_T_236]; // @[util.scala:211:14] assign s_uop_1_dis_col_sel = _GEN_226[_T_236]; // @[util.scala:211:14] assign s_uop_1_br_mask = _GEN_227[_T_236]; // @[util.scala:211:14] assign s_uop_1_br_tag = _GEN_228[_T_236]; // @[util.scala:211:14] assign s_uop_1_br_type = _GEN_229[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_sfb = _GEN_230[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_fence = _GEN_231[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_fencei = _GEN_232[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_sfence = _GEN_233[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_amo = _GEN_234[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_eret = _GEN_235[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_sys_pc2epc = _GEN_236[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_rocc = _GEN_237[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_mov = _GEN_238[_T_236]; // @[util.scala:211:14] assign s_uop_1_ftq_idx = _GEN_239[_T_236]; // @[util.scala:211:14] assign s_uop_1_edge_inst = _GEN_240[_T_236]; // @[util.scala:211:14] assign s_uop_1_pc_lob = _GEN_241[_T_236]; // @[util.scala:211:14] assign s_uop_1_taken = _GEN_242[_T_236]; // @[util.scala:211:14] assign s_uop_1_imm_rename = _GEN_243[_T_236]; // @[util.scala:211:14] assign s_uop_1_imm_sel = _GEN_244[_T_236]; // @[util.scala:211:14] assign s_uop_1_pimm = _GEN_245[_T_236]; // @[util.scala:211:14] assign s_uop_1_imm_packed = _GEN_246[_T_236]; // @[util.scala:211:14] assign s_uop_1_op1_sel = _GEN_247[_T_236]; // @[util.scala:211:14] assign s_uop_1_op2_sel = _GEN_248[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_ldst = _GEN_249[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_wen = _GEN_250[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_ren1 = _GEN_251[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_ren2 = _GEN_252[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_ren3 = _GEN_253[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_swap12 = _GEN_254[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_swap23 = _GEN_255[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_typeTagIn = _GEN_256[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_typeTagOut = _GEN_257[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_fromint = _GEN_258[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_toint = _GEN_259[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_fastpipe = _GEN_260[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_fma = _GEN_261[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_div = _GEN_262[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_sqrt = _GEN_263[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_wflags = _GEN_264[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_vec = _GEN_265[_T_236]; // @[util.scala:211:14] assign s_uop_1_rob_idx = _GEN_266[_T_236]; // @[util.scala:211:14] assign s_uop_1_ldq_idx = _GEN_267[_T_236]; // @[util.scala:211:14] assign s_uop_1_stq_idx = _GEN_268[_T_236]; // @[util.scala:211:14] assign s_uop_1_rxq_idx = _GEN_269[_T_236]; // @[util.scala:211:14] assign s_uop_1_pdst = _GEN_270[_T_236]; // @[util.scala:211:14] assign s_uop_1_prs1 = _GEN_271[_T_236]; // @[util.scala:211:14] assign s_uop_1_prs2 = _GEN_272[_T_236]; // @[util.scala:211:14] assign s_uop_1_prs3 = _GEN_273[_T_236]; // @[util.scala:211:14] assign s_uop_1_ppred = _GEN_274[_T_236]; // @[util.scala:211:14] assign s_uop_1_prs1_busy = _GEN_275[_T_236]; // @[util.scala:211:14] assign s_uop_1_prs2_busy = _GEN_276[_T_236]; // @[util.scala:211:14] assign s_uop_1_prs3_busy = _GEN_277[_T_236]; // @[util.scala:211:14] assign s_uop_1_ppred_busy = _GEN_278[_T_236]; // @[util.scala:211:14] assign s_uop_1_stale_pdst = _GEN_279[_T_236]; // @[util.scala:211:14] assign s_uop_1_exception = _GEN_280[_T_236]; // @[util.scala:211:14] assign s_uop_1_exc_cause = _GEN_281[_T_236]; // @[util.scala:211:14] assign s_uop_1_mem_cmd = _GEN_282[_T_236]; // @[util.scala:211:14] assign s_uop_1_mem_size = _GEN_283[_T_236]; // @[util.scala:211:14] assign s_uop_1_mem_signed = _GEN_284[_T_236]; // @[util.scala:211:14] assign s_uop_1_uses_ldq = _GEN_285[_T_236]; // @[util.scala:211:14] assign s_uop_1_uses_stq = _GEN_286[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_unique = _GEN_287[_T_236]; // @[util.scala:211:14] assign s_uop_1_flush_on_commit = _GEN_288[_T_236]; // @[util.scala:211:14] assign s_uop_1_csr_cmd = _GEN_289[_T_236]; // @[util.scala:211:14] assign s_uop_1_ldst_is_rs1 = _GEN_290[_T_236]; // @[util.scala:211:14] assign s_uop_1_ldst = _GEN_291[_T_236]; // @[util.scala:211:14] assign s_uop_1_lrs1 = _GEN_292[_T_236]; // @[util.scala:211:14] assign s_uop_1_lrs2 = _GEN_293[_T_236]; // @[util.scala:211:14] assign s_uop_1_lrs3 = _GEN_294[_T_236]; // @[util.scala:211:14] assign s_uop_1_dst_rtype = _GEN_295[_T_236]; // @[util.scala:211:14] assign s_uop_1_lrs1_rtype = _GEN_296[_T_236]; // @[util.scala:211:14] assign s_uop_1_lrs2_rtype = _GEN_297[_T_236]; // @[util.scala:211:14] assign s_uop_1_frs3_en = _GEN_298[_T_236]; // @[util.scala:211:14] assign s_uop_1_fcn_dw = _GEN_299[_T_236]; // @[util.scala:211:14] assign s_uop_1_fcn_op = _GEN_300[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_val = _GEN_301[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_rm = _GEN_302[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_typ = _GEN_303[_T_236]; // @[util.scala:211:14] assign s_uop_1_xcpt_pf_if = _GEN_304[_T_236]; // @[util.scala:211:14] assign s_uop_1_xcpt_ae_if = _GEN_305[_T_236]; // @[util.scala:211:14] assign s_uop_1_xcpt_ma_if = _GEN_306[_T_236]; // @[util.scala:211:14] assign s_uop_1_bp_debug_if = _GEN_307[_T_236]; // @[util.scala:211:14] assign s_uop_1_bp_xcpt_if = _GEN_308[_T_236]; // @[util.scala:211:14] assign s_uop_1_debug_fsrc = _GEN_309[_T_236]; // @[util.scala:211:14] assign s_uop_1_debug_tsrc = _GEN_310[_T_236]; // @[util.scala:211:14] wire [11:0] _clr_uop_out_br_mask_T_3; // @[util.scala:93:25] wire [11:0] clr_uop_out_1_br_mask; // @[util.scala:104:23] wire [11:0] _clr_uop_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_out_br_mask_T_3 = s_uop_1_br_mask & _clr_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign clr_uop_out_1_br_mask = _clr_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire [11:0] _io_core_clr_bsy_1_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_1_1_br_mask; // @[util.scala:126:51] wire _io_core_clr_bsy_1_valid_T_1 = \|_io_core_clr_bsy_1_valid_T; // @[util.scala:126:{51,59}] wire _io_core_clr_bsy_1_valid_T_2 = _io_core_clr_bsy_1_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_clr_bsy_1_valid_T_3 = ~_io_core_clr_bsy_1_valid_T_2; // @[util.scala:61:61] assign _io_core_clr_bsy_1_valid_T_4 = clr_valid_1_1 & _io_core_clr_bsy_1_valid_T_3; // @[lsu.scala:1088:30, :1107:{45,48}] assign io_core_clr_bsy_1_valid_0 = _io_core_clr_bsy_1_valid_T_4; // @[lsu.scala:211:7, :1107:45] wire _GEN_391 = fired_store_agen_0 \| fired_store_retry_0; // @[lsu.scala:321:49, :1122:57] wire _do_st_search_T; // @[lsu.scala:1122:57] assign _do_st_search_T = _GEN_391; // @[lsu.scala:1122:57] wire _lcam_addr_T; // @[lsu.scala:1133:58] assign _lcam_addr_T = _GEN_391; // @[lsu.scala:1122:57, :1133:58] wire _do_st_search_T_1 = ~mem_tlb_miss_0; // @[lsu.scala:1070:41, :1122:85] wire _do_st_search_T_2 = _do_st_search_T & _do_st_search_T_1; // @[lsu.scala:1122:{57,82,85}] wire do_st_search_0 = _do_st_search_T_2; // @[lsu.scala:321:49, :1122:82] wire _do_ld_search_T_1 = _do_ld_search_T \| fired_load_retry_0; // @[lsu.scala:321:49, :1124:{57,84}] wire _do_ld_search_T_2 = ~mem_tlb_miss_0; // @[lsu.scala:1070:41, :1122:85, :1124:111] wire _do_ld_search_T_3 = _do_ld_search_T_1 & _do_ld_search_T_2; // @[lsu.scala:1124:{84,108,111}] wire _do_ld_search_T_4 = _do_ld_search_T_3 \| fired_load_wakeup_0; // @[lsu.scala:321:49, :1124:{108,129}] wire do_ld_search_0 = _do_ld_search_T_4; // @[lsu.scala:321:49, :1124:129] wire _lcam_addr_T_1 = _lcam_addr_T \| fired_load_agen_0; // @[lsu.scala:321:49, :1133:{58,82}] wire _lcam_addr_T_2 = _lcam_addr_T_1 \| fired_load_agen_exec_0; // @[lsu.scala:321:49, :1133:{82,104}] reg [31:0] lcam_addr_REG; // @[lsu.scala:1134:45] reg [31:0] lcam_addr_REG_1; // @[lsu.scala:1135:67] wire [39:0] _lcam_addr_T_3 = fired_release_0 ? {8'h0, lcam_addr_REG_1} : mem_paddr_0; // @[lsu.scala:1045:37, :1072:41, :1135:{41,67}] wire [39:0] _lcam_addr_T_4 = _lcam_addr_T_2 ? {8'h0, lcam_addr_REG} : _lcam_addr_T_3; // @[lsu.scala:1133:{37,104}, :1134:45, :1135:41] wire [39:0] lcam_addr_0 = _lcam_addr_T_4; // @[lsu.scala:321:49, :1133:37] wire [31:0] _lcam_uop_T_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :1138:37] wire [31:0] _lcam_uop_T_debug_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_rvc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_rvc; // @[lsu.scala:321:49, :1138:37] wire [39:0] _lcam_uop_T_debug_pc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_0 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_2 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_3 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_0 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_2 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_3 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_4 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_5 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_6 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_7 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_8 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_9 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_issued = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_issued; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_issued_partial_agen = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_issued_partial_dgen = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_iw_p1_speculative_child = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iw_p1_speculative_child : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_iw_p2_speculative_child = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iw_p2_speculative_child : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_p1_bypass_hint = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_p2_bypass_hint = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_p3_bypass_hint = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_dis_col_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_dis_col_sel : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [11:0] _lcam_uop_T_br_mask = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_mask : 12'h0; // @[lsu.scala:321:49, :1138:37] wire [3:0] _lcam_uop_T_br_tag = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :1138:37] wire [3:0] _lcam_uop_T_br_type = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_sfb = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sfb; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_fence = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fence; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_fencei = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fencei; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_sfence = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sfence; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_amo = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_amo; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_eret = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_eret; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_sys_pc2epc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_rocc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_rocc; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_mov = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_mov; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_ftq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_edge_inst = do_ld_search_0 & mem_ldq_e_0_bits_uop_edge_inst; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_pc_lob = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_taken = do_ld_search_0 & mem_ldq_e_0_bits_uop_taken; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_imm_rename = do_ld_search_0 & mem_ldq_e_0_bits_uop_imm_rename; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_imm_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_pimm = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :1138:37] wire [19:0] _lcam_uop_T_imm_packed = do_ld_search_0 ? mem_ldq_e_0_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_op1_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_op2_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ldst = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_wen = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ren1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ren2 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ren3 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_swap12 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_swap23 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_fp_ctrl_typeTagIn = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_fp_ctrl_typeTagOut = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_fromint = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_toint = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_fastpipe = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_fma = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_div = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_sqrt = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_wflags = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_vec = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_rob_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rob_idx : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [3:0] _lcam_uop_T_ldq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldq_idx : 4'h0; // @[lsu.scala:321:49, :1138:37] wire [3:0] _lcam_uop_T_stq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stq_idx : 4'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_rxq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_prs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_prs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_prs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_ppred = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_prs1_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_prs2_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_prs3_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_ppred_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_stale_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_exception = do_ld_search_0 & mem_ldq_e_0_bits_uop_exception; // @[lsu.scala:321:49, :1138:37] wire [63:0] _lcam_uop_T_exc_cause = do_ld_search_0 ? mem_ldq_e_0_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_mem_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_mem_size = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_size : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_mem_signed = do_ld_search_0 & mem_ldq_e_0_bits_uop_mem_signed; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_uses_ldq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_uses_stq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_stq; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_unique = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_unique; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_flush_on_commit = do_ld_search_0 & mem_ldq_e_0_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_csr_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_ldst_is_rs1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_ldst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_lrs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_lrs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_lrs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_dst_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_lrs1_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_lrs2_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_frs3_en = do_ld_search_0 & mem_ldq_e_0_bits_uop_frs3_en; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fcn_dw = do_ld_search_0 & mem_ldq_e_0_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_fcn_op = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_val = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_val; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_fp_rm = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_fp_typ = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_xcpt_pf_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_xcpt_ae_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_xcpt_ma_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_bp_debug_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_bp_xcpt_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_debug_fsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_debug_tsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [31:0] _lcam_uop_T_1_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_inst : _lcam_uop_T_inst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [31:0] _lcam_uop_T_1_debug_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_inst : _lcam_uop_T_debug_inst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_rvc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_rvc : _lcam_uop_T_is_rvc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [39:0] _lcam_uop_T_1_debug_pc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_pc : _lcam_uop_T_debug_pc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_0 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_0 : _lcam_uop_T_iq_type_0; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_1 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_1 : _lcam_uop_T_iq_type_1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_2 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_2 : _lcam_uop_T_iq_type_2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_3 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_3 : _lcam_uop_T_iq_type_3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_0 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_0 : _lcam_uop_T_fu_code_0; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_1 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_1 : _lcam_uop_T_fu_code_1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_2 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_2 : _lcam_uop_T_fu_code_2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_3 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_3 : _lcam_uop_T_fu_code_3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_4 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_4 : _lcam_uop_T_fu_code_4; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_5 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_5 : _lcam_uop_T_fu_code_5; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_6 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_6 : _lcam_uop_T_fu_code_6; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_7 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_7 : _lcam_uop_T_fu_code_7; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_8 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_8 : _lcam_uop_T_fu_code_8; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_9 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_9 : _lcam_uop_T_fu_code_9; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_issued = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_issued : _lcam_uop_T_iw_issued; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_issued_partial_agen = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_issued_partial_agen : _lcam_uop_T_iw_issued_partial_agen; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_issued_partial_dgen = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_issued_partial_dgen : _lcam_uop_T_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_iw_p1_speculative_child = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p1_speculative_child : _lcam_uop_T_iw_p1_speculative_child; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_iw_p2_speculative_child = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p2_speculative_child : _lcam_uop_T_iw_p2_speculative_child; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_p1_bypass_hint = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p1_bypass_hint : _lcam_uop_T_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_p2_bypass_hint = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p2_bypass_hint : _lcam_uop_T_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_p3_bypass_hint = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p3_bypass_hint : _lcam_uop_T_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_dis_col_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_dis_col_sel : _lcam_uop_T_dis_col_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [11:0] _lcam_uop_T_1_br_mask = do_st_search_0 ? mem_stq_e_0_bits_uop_br_mask : _lcam_uop_T_br_mask; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [3:0] _lcam_uop_T_1_br_tag = do_st_search_0 ? mem_stq_e_0_bits_uop_br_tag : _lcam_uop_T_br_tag; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [3:0] _lcam_uop_T_1_br_type = do_st_search_0 ? mem_stq_e_0_bits_uop_br_type : _lcam_uop_T_br_type; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_sfb = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sfb : _lcam_uop_T_is_sfb; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_fence = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fence : _lcam_uop_T_is_fence; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_fencei = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fencei : _lcam_uop_T_is_fencei; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_sfence = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sfence : _lcam_uop_T_is_sfence; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_amo = do_st_search_0 ? mem_stq_e_0_bits_uop_is_amo : _lcam_uop_T_is_amo; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_eret = do_st_search_0 ? mem_stq_e_0_bits_uop_is_eret : _lcam_uop_T_is_eret; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_sys_pc2epc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sys_pc2epc : _lcam_uop_T_is_sys_pc2epc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_rocc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_rocc : _lcam_uop_T_is_rocc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_mov = do_st_search_0 ? mem_stq_e_0_bits_uop_is_mov : _lcam_uop_T_is_mov; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_ftq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ftq_idx : _lcam_uop_T_ftq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_edge_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_edge_inst : _lcam_uop_T_edge_inst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_pc_lob = do_st_search_0 ? mem_stq_e_0_bits_uop_pc_lob : _lcam_uop_T_pc_lob; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_taken = do_st_search_0 ? mem_stq_e_0_bits_uop_taken : _lcam_uop_T_taken; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_imm_rename = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_rename : _lcam_uop_T_imm_rename; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_imm_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_sel : _lcam_uop_T_imm_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_pimm = do_st_search_0 ? mem_stq_e_0_bits_uop_pimm : _lcam_uop_T_pimm; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [19:0] _lcam_uop_T_1_imm_packed = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_packed : _lcam_uop_T_imm_packed; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_op1_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_op1_sel : _lcam_uop_T_op1_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_op2_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_op2_sel : _lcam_uop_T_op2_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ldst = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ldst : _lcam_uop_T_fp_ctrl_ldst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_wen = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_wen : _lcam_uop_T_fp_ctrl_wen; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ren1 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ren1 : _lcam_uop_T_fp_ctrl_ren1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ren2 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ren2 : _lcam_uop_T_fp_ctrl_ren2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ren3 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ren3 : _lcam_uop_T_fp_ctrl_ren3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_swap12 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_swap12 : _lcam_uop_T_fp_ctrl_swap12; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_swap23 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_swap23 : _lcam_uop_T_fp_ctrl_swap23; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_fp_ctrl_typeTagIn = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_typeTagIn : _lcam_uop_T_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_fp_ctrl_typeTagOut = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_typeTagOut : _lcam_uop_T_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_fromint = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_fromint : _lcam_uop_T_fp_ctrl_fromint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_toint = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_toint : _lcam_uop_T_fp_ctrl_toint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_fastpipe = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_fastpipe : _lcam_uop_T_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_fma = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_fma : _lcam_uop_T_fp_ctrl_fma; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_div = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_div : _lcam_uop_T_fp_ctrl_div; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_sqrt = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_sqrt : _lcam_uop_T_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_wflags = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_wflags : _lcam_uop_T_fp_ctrl_wflags; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_vec = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_vec : _lcam_uop_T_fp_ctrl_vec; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_rob_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rob_idx : _lcam_uop_T_rob_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [3:0] _lcam_uop_T_1_ldq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ldq_idx : _lcam_uop_T_ldq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [3:0] _lcam_uop_T_1_stq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_stq_idx : _lcam_uop_T_stq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_rxq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rxq_idx : _lcam_uop_T_rxq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_pdst : _lcam_uop_T_pdst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_prs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1 : _lcam_uop_T_prs1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_prs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2 : _lcam_uop_T_prs2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_prs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3 : _lcam_uop_T_prs3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_ppred = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred : _lcam_uop_T_ppred; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_prs1_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1_busy : _lcam_uop_T_prs1_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_prs2_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2_busy : _lcam_uop_T_prs2_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_prs3_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3_busy : _lcam_uop_T_prs3_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_ppred_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred_busy : _lcam_uop_T_ppred_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_stale_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_stale_pdst : _lcam_uop_T_stale_pdst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_exception = do_st_search_0 ? mem_stq_e_0_bits_uop_exception : _lcam_uop_T_exception; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [63:0] _lcam_uop_T_1_exc_cause = do_st_search_0 ? mem_stq_e_0_bits_uop_exc_cause : _lcam_uop_T_exc_cause; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_mem_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_cmd : _lcam_uop_T_mem_cmd; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_mem_size = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_size : _lcam_uop_T_mem_size; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_mem_signed = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_signed : _lcam_uop_T_mem_signed; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_uses_ldq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_ldq : _lcam_uop_T_uses_ldq; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_uses_stq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_stq : _lcam_uop_T_uses_stq; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_unique = do_st_search_0 ? mem_stq_e_0_bits_uop_is_unique : _lcam_uop_T_is_unique; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_flush_on_commit = do_st_search_0 ? mem_stq_e_0_bits_uop_flush_on_commit : _lcam_uop_T_flush_on_commit; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_csr_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_csr_cmd : _lcam_uop_T_csr_cmd; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_ldst_is_rs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst_is_rs1 : _lcam_uop_T_ldst_is_rs1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_ldst = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst : _lcam_uop_T_ldst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_lrs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1 : _lcam_uop_T_lrs1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_lrs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2 : _lcam_uop_T_lrs2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_lrs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs3 : _lcam_uop_T_lrs3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_dst_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_dst_rtype : _lcam_uop_T_dst_rtype; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_lrs1_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1_rtype : _lcam_uop_T_lrs1_rtype; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_lrs2_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2_rtype : _lcam_uop_T_lrs2_rtype; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_frs3_en = do_st_search_0 ? mem_stq_e_0_bits_uop_frs3_en : _lcam_uop_T_frs3_en; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fcn_dw = do_st_search_0 ? mem_stq_e_0_bits_uop_fcn_dw : _lcam_uop_T_fcn_dw; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_fcn_op = do_st_search_0 ? mem_stq_e_0_bits_uop_fcn_op : _lcam_uop_T_fcn_op; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_val = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_val : _lcam_uop_T_fp_val; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_fp_rm = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_rm : _lcam_uop_T_fp_rm; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_fp_typ = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_typ : _lcam_uop_T_fp_typ; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_xcpt_pf_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_pf_if : _lcam_uop_T_xcpt_pf_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_xcpt_ae_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ae_if : _lcam_uop_T_xcpt_ae_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_xcpt_ma_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ma_if : _lcam_uop_T_xcpt_ma_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_bp_debug_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_debug_if : _lcam_uop_T_bp_debug_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_bp_xcpt_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_xcpt_if : _lcam_uop_T_bp_xcpt_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_debug_fsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_fsrc : _lcam_uop_T_debug_fsrc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_debug_tsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_tsrc : _lcam_uop_T_debug_tsrc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [31:0] lcam_uop_0_inst = _lcam_uop_T_1_inst; // @[lsu.scala:321:49, :1137:37] wire [31:0] lcam_uop_0_debug_inst = _lcam_uop_T_1_debug_inst; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_rvc = _lcam_uop_T_1_is_rvc; // @[lsu.scala:321:49, :1137:37] wire [39:0] lcam_uop_0_debug_pc = _lcam_uop_T_1_debug_pc; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_0 = _lcam_uop_T_1_iq_type_0; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_1 = _lcam_uop_T_1_iq_type_1; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_2 = _lcam_uop_T_1_iq_type_2; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_3 = _lcam_uop_T_1_iq_type_3; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_0 = _lcam_uop_T_1_fu_code_0; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_1 = _lcam_uop_T_1_fu_code_1; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_2 = _lcam_uop_T_1_fu_code_2; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_3 = _lcam_uop_T_1_fu_code_3; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_4 = _lcam_uop_T_1_fu_code_4; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_5 = _lcam_uop_T_1_fu_code_5; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_6 = _lcam_uop_T_1_fu_code_6; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_7 = _lcam_uop_T_1_fu_code_7; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_8 = _lcam_uop_T_1_fu_code_8; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_9 = _lcam_uop_T_1_fu_code_9; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_issued = _lcam_uop_T_1_iw_issued; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_issued_partial_agen = _lcam_uop_T_1_iw_issued_partial_agen; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_issued_partial_dgen = _lcam_uop_T_1_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_iw_p1_speculative_child = _lcam_uop_T_1_iw_p1_speculative_child; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_iw_p2_speculative_child = _lcam_uop_T_1_iw_p2_speculative_child; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_p1_bypass_hint = _lcam_uop_T_1_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_p2_bypass_hint = _lcam_uop_T_1_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_p3_bypass_hint = _lcam_uop_T_1_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_dis_col_sel = _lcam_uop_T_1_dis_col_sel; // @[lsu.scala:321:49, :1137:37] wire [11:0] lcam_uop_0_br_mask = _lcam_uop_T_1_br_mask; // @[lsu.scala:321:49, :1137:37] wire [3:0] lcam_uop_0_br_tag = _lcam_uop_T_1_br_tag; // @[lsu.scala:321:49, :1137:37] wire [3:0] lcam_uop_0_br_type = _lcam_uop_T_1_br_type; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_sfb = _lcam_uop_T_1_is_sfb; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_fence = _lcam_uop_T_1_is_fence; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_fencei = _lcam_uop_T_1_is_fencei; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_sfence = _lcam_uop_T_1_is_sfence; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_amo = _lcam_uop_T_1_is_amo; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_eret = _lcam_uop_T_1_is_eret; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_sys_pc2epc = _lcam_uop_T_1_is_sys_pc2epc; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_rocc = _lcam_uop_T_1_is_rocc; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_mov = _lcam_uop_T_1_is_mov; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_ftq_idx = _lcam_uop_T_1_ftq_idx; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_edge_inst = _lcam_uop_T_1_edge_inst; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_pc_lob = _lcam_uop_T_1_pc_lob; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_taken = _lcam_uop_T_1_taken; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_imm_rename = _lcam_uop_T_1_imm_rename; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_imm_sel = _lcam_uop_T_1_imm_sel; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_pimm = _lcam_uop_T_1_pimm; // @[lsu.scala:321:49, :1137:37] wire [19:0] lcam_uop_0_imm_packed = _lcam_uop_T_1_imm_packed; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_op1_sel = _lcam_uop_T_1_op1_sel; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_op2_sel = _lcam_uop_T_1_op2_sel; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ldst = _lcam_uop_T_1_fp_ctrl_ldst; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_wen = _lcam_uop_T_1_fp_ctrl_wen; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ren1 = _lcam_uop_T_1_fp_ctrl_ren1; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ren2 = _lcam_uop_T_1_fp_ctrl_ren2; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ren3 = _lcam_uop_T_1_fp_ctrl_ren3; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_swap12 = _lcam_uop_T_1_fp_ctrl_swap12; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_swap23 = _lcam_uop_T_1_fp_ctrl_swap23; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_fp_ctrl_typeTagIn = _lcam_uop_T_1_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_fp_ctrl_typeTagOut = _lcam_uop_T_1_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_fromint = _lcam_uop_T_1_fp_ctrl_fromint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_toint = _lcam_uop_T_1_fp_ctrl_toint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_fastpipe = _lcam_uop_T_1_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_fma = _lcam_uop_T_1_fp_ctrl_fma; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_div = _lcam_uop_T_1_fp_ctrl_div; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_sqrt = _lcam_uop_T_1_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_wflags = _lcam_uop_T_1_fp_ctrl_wflags; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_vec = _lcam_uop_T_1_fp_ctrl_vec; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_rob_idx = _lcam_uop_T_1_rob_idx; // @[lsu.scala:321:49, :1137:37] wire [3:0] lcam_uop_0_ldq_idx = _lcam_uop_T_1_ldq_idx; // @[lsu.scala:321:49, :1137:37] wire [3:0] lcam_uop_0_stq_idx = _lcam_uop_T_1_stq_idx; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_rxq_idx = _lcam_uop_T_1_rxq_idx; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_pdst = _lcam_uop_T_1_pdst; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_prs1 = _lcam_uop_T_1_prs1; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_prs2 = _lcam_uop_T_1_prs2; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_prs3 = _lcam_uop_T_1_prs3; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_ppred = _lcam_uop_T_1_ppred; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_prs1_busy = _lcam_uop_T_1_prs1_busy; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_prs2_busy = _lcam_uop_T_1_prs2_busy; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_prs3_busy = _lcam_uop_T_1_prs3_busy; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_ppred_busy = _lcam_uop_T_1_ppred_busy; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_stale_pdst = _lcam_uop_T_1_stale_pdst; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_exception = _lcam_uop_T_1_exception; // @[lsu.scala:321:49, :1137:37] wire [63:0] lcam_uop_0_exc_cause = _lcam_uop_T_1_exc_cause; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_mem_cmd = _lcam_uop_T_1_mem_cmd; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_mem_size = _lcam_uop_T_1_mem_size; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_mem_signed = _lcam_uop_T_1_mem_signed; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_uses_ldq = _lcam_uop_T_1_uses_ldq; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_uses_stq = _lcam_uop_T_1_uses_stq; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_unique = _lcam_uop_T_1_is_unique; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_flush_on_commit = _lcam_uop_T_1_flush_on_commit; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_csr_cmd = _lcam_uop_T_1_csr_cmd; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_ldst_is_rs1 = _lcam_uop_T_1_ldst_is_rs1; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_ldst = _lcam_uop_T_1_ldst; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_lrs1 = _lcam_uop_T_1_lrs1; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_lrs2 = _lcam_uop_T_1_lrs2; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_lrs3 = _lcam_uop_T_1_lrs3; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_dst_rtype = _lcam_uop_T_1_dst_rtype; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_lrs1_rtype = _lcam_uop_T_1_lrs1_rtype; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_lrs2_rtype = _lcam_uop_T_1_lrs2_rtype; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_frs3_en = _lcam_uop_T_1_frs3_en; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fcn_dw = _lcam_uop_T_1_fcn_dw; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_fcn_op = _lcam_uop_T_1_fcn_op; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_val = _lcam_uop_T_1_fp_val; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_fp_rm = _lcam_uop_T_1_fp_rm; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_fp_typ = _lcam_uop_T_1_fp_typ; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_xcpt_pf_if = _lcam_uop_T_1_xcpt_pf_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_xcpt_ae_if = _lcam_uop_T_1_xcpt_ae_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_xcpt_ma_if = _lcam_uop_T_1_xcpt_ma_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_bp_debug_if = _lcam_uop_T_1_bp_debug_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_bp_xcpt_if = _lcam_uop_T_1_bp_xcpt_if; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_debug_fsrc = _lcam_uop_T_1_debug_fsrc; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_debug_tsrc = _lcam_uop_T_1_debug_tsrc; // @[lsu.scala:321:49, :1137:37] wire [7:0] lcam_mask_mask; // @[lsu.scala:1951:22] wire [7:0] lcam_mask_0 = lcam_mask_mask; // @[lsu.scala:321:49, :1951:22] wire _lcam_mask_mask_T = lcam_uop_0_mem_size == 2'h0; // @[lsu.scala:321:49, :1953:26] wire [2:0] _lcam_mask_mask_T_1 = lcam_addr_0[2:0]; // @[lsu.scala:321:49, :1953:55] wire [14:0] _lcam_mask_mask_T_2 = 15'h1 << _lcam_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _lcam_mask_mask_T_3 = lcam_uop_0_mem_size == 2'h1; // @[lsu.scala:321:49, :1954:26] wire [1:0] _lcam_mask_mask_T_4 = lcam_addr_0[2:1]; // @[lsu.scala:321:49, :1954:56] wire [2:0] _lcam_mask_mask_T_5 = {_lcam_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _lcam_mask_mask_T_6 = 15'h3 << _lcam_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _lcam_mask_mask_T_7 = lcam_uop_0_mem_size == 2'h2; // @[lsu.scala:321:49, :1955:26] wire _lcam_mask_mask_T_8 = lcam_addr_0[2]; // @[lsu.scala:321:49, :1955:46] wire [7:0] _lcam_mask_mask_T_9 = _lcam_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _lcam_mask_mask_T_10 = &lcam_uop_0_mem_size; // @[lsu.scala:321:49, :1956:26] wire [7:0] _lcam_mask_mask_T_12 = _lcam_mask_mask_T_7 ? _lcam_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_13 = _lcam_mask_mask_T_3 ? _lcam_mask_mask_T_6 : {7'h0, _lcam_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_14 = _lcam_mask_mask_T ? _lcam_mask_mask_T_2 : _lcam_mask_mask_T_13; // @[Mux.scala:126:16] assign lcam_mask_mask = _lcam_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] reg [3:0] lcam_ldq_idx_REG; // @[lsu.scala:1146:58] reg [3:0] lcam_ldq_idx_REG_1; // @[lsu.scala:1147:58] wire [3:0] _lcam_ldq_idx_T_1 = fired_load_retry_0 ? lcam_ldq_idx_REG_1 : 4'h0; // @[lsu.scala:321:49, :1147:{26,58}] wire [3:0] _lcam_ldq_idx_T_2 = fired_load_wakeup_0 ? lcam_ldq_idx_REG : _lcam_ldq_idx_T_1; // @[lsu.scala:321:49, :1146:{26,58}, :1147:26] wire [3:0] _lcam_ldq_idx_T_3 = _lcam_ldq_idx_T ? mem_incoming_uop_0_ldq_idx : _lcam_ldq_idx_T_2; // @[lsu.scala:1053:37, :1144:{26,51}, :1146:26] wire [3:0] lcam_ldq_idx_0 = _lcam_ldq_idx_T_3; // @[lsu.scala:321:49, :1144:26] wire [3:0] _wb_ldst_forward_e_e_valid_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_uop_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_addr_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_addr_is_virtual_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_executed_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_succeeded_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_order_fail_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_observed_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_st_dep_mask_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_ld_byte_mask_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_forward_std_val_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_forward_stq_idx_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_debug_wb_data_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] reg [3:0] lcam_stq_idx_REG; // @[lsu.scala:1150:56] wire [3:0] _lcam_stq_idx_T = fired_store_retry_0 ? lcam_stq_idx_REG : 4'h0; // @[lsu.scala:321:49, :1150:{26,56}] wire [3:0] _lcam_stq_idx_T_1 = fired_store_agen_0 ? mem_incoming_uop_0_stq_idx : _lcam_stq_idx_T; // @[lsu.scala:321:49, :1053:37, :1149:26, :1150:26] wire [3:0] lcam_stq_idx_0 = _lcam_stq_idx_T_1; // @[lsu.scala:321:49, :1149:26] wire [15:0] _lcam_younger_load_mask_hi_mask_T = 16'h1 << lcam_ldq_idx_0; // @[OneHot.scala:58:35] wire [15:0] _lcam_younger_load_mask_hi_mask_T_1 = _lcam_younger_load_mask_hi_mask_T; // @[OneHot.scala:58:35] wire [15:0] _lcam_younger_load_mask_hi_mask_T_2 = _lcam_younger_load_mask_hi_mask_T_1; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_3 = {1'h0, _lcam_younger_load_mask_hi_mask_T_1[15:1]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_4 = {2'h0, _lcam_younger_load_mask_hi_mask_T_1[15:2]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_5 = {3'h0, _lcam_younger_load_mask_hi_mask_T_1[15:3]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_6 = {4'h0, _lcam_younger_load_mask_hi_mask_T_1[15:4]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_7 = {5'h0, _lcam_younger_load_mask_hi_mask_T_1[15:5]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_8 = {6'h0, _lcam_younger_load_mask_hi_mask_T_1[15:6]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_9 = {7'h0, _lcam_younger_load_mask_hi_mask_T_1[15:7]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_10 = {8'h0, _lcam_younger_load_mask_hi_mask_T_1[15:8]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_11 = {9'h0, _lcam_younger_load_mask_hi_mask_T_1[15:9]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_12 = {10'h0, _lcam_younger_load_mask_hi_mask_T_1[15:10]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_13 = {11'h0, _lcam_younger_load_mask_hi_mask_T_1[15:11]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_14 = {12'h0, _lcam_younger_load_mask_hi_mask_T_1[15:12]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_15 = {13'h0, _lcam_younger_load_mask_hi_mask_T_1[15:13]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_16 = {14'h0, _lcam_younger_load_mask_hi_mask_T_1[15:14]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_17 = {15'h0, _lcam_younger_load_mask_hi_mask_T_1[15]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_18 = _lcam_younger_load_mask_hi_mask_T_2 \| _lcam_younger_load_mask_hi_mask_T_3; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_19 = _lcam_younger_load_mask_hi_mask_T_18 \| _lcam_younger_load_mask_hi_mask_T_4; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_20 = _lcam_younger_load_mask_hi_mask_T_19 \| _lcam_younger_load_mask_hi_mask_T_5; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_21 = _lcam_younger_load_mask_hi_mask_T_20 \| _lcam_younger_load_mask_hi_mask_T_6; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_22 = _lcam_younger_load_mask_hi_mask_T_21 \| _lcam_younger_load_mask_hi_mask_T_7; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_23 = _lcam_younger_load_mask_hi_mask_T_22 \| _lcam_younger_load_mask_hi_mask_T_8; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_24 = _lcam_younger_load_mask_hi_mask_T_23 \| _lcam_younger_load_mask_hi_mask_T_9; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_25 = _lcam_younger_load_mask_hi_mask_T_24 \| _lcam_younger_load_mask_hi_mask_T_10; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_26 = _lcam_younger_load_mask_hi_mask_T_25 \| _lcam_younger_load_mask_hi_mask_T_11; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_27 = _lcam_younger_load_mask_hi_mask_T_26 \| _lcam_younger_load_mask_hi_mask_T_12; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_28 = _lcam_younger_load_mask_hi_mask_T_27 \| _lcam_younger_load_mask_hi_mask_T_13; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_29 = _lcam_younger_load_mask_hi_mask_T_28 \| _lcam_younger_load_mask_hi_mask_T_14; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_30 = _lcam_younger_load_mask_hi_mask_T_29 \| _lcam_younger_load_mask_hi_mask_T_15; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_31 = _lcam_younger_load_mask_hi_mask_T_30 \| _lcam_younger_load_mask_hi_mask_T_16; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_32 = _lcam_younger_load_mask_hi_mask_T_31 \| _lcam_younger_load_mask_hi_mask_T_17; // @[util.scala:383:{29,45}] wire [15:0] lcam_younger_load_mask_hi_mask = ~_lcam_younger_load_mask_hi_mask_T_32; // @[util.scala:370:19, :383:45] wire [15:0] _lcam_younger_load_mask_lo_mask_T = 16'h1 << ldq_head; // @[OneHot.scala:58:35] wire [15:0] _lcam_younger_load_mask_lo_mask_T_1 = _lcam_younger_load_mask_lo_mask_T; // @[OneHot.scala:58:35] wire [16:0] _lcam_younger_load_mask_lo_mask_T_2 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_3 = _lcam_younger_load_mask_lo_mask_T_2[15:0]; // @[util.scala:394:{30,37}] wire [16:0] _lcam_younger_load_mask_lo_mask_T_4 = {_lcam_younger_load_mask_lo_mask_T_1, 1'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_5 = _lcam_younger_load_mask_lo_mask_T_4[15:0]; // @[util.scala:394:{30,37}] wire [18:0] _lcam_younger_load_mask_lo_mask_T_6 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1, 2'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_7 = _lcam_younger_load_mask_lo_mask_T_6[15:0]; // @[util.scala:394:{30,37}] wire [18:0] _lcam_younger_load_mask_lo_mask_T_8 = {_lcam_younger_load_mask_lo_mask_T_1, 3'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_9 = _lcam_younger_load_mask_lo_mask_T_8[15:0]; // @[util.scala:394:{30,37}] wire [22:0] _lcam_younger_load_mask_lo_mask_T_10 = {3'h0, _lcam_younger_load_mask_lo_mask_T_1, 4'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_11 = _lcam_younger_load_mask_lo_mask_T_10[15:0]; // @[util.scala:394:{30,37}] wire [22:0] _lcam_younger_load_mask_lo_mask_T_12 = {2'h0, _lcam_younger_load_mask_lo_mask_T_1, 5'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_13 = _lcam_younger_load_mask_lo_mask_T_12[15:0]; // @[util.scala:394:{30,37}] wire [22:0] _lcam_younger_load_mask_lo_mask_T_14 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1, 6'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_15 = _lcam_younger_load_mask_lo_mask_T_14[15:0]; // @[util.scala:394:{30,37}] wire [22:0] _lcam_younger_load_mask_lo_mask_T_16 = {_lcam_younger_load_mask_lo_mask_T_1, 7'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_17 = _lcam_younger_load_mask_lo_mask_T_16[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_18 = {7'h0, _lcam_younger_load_mask_lo_mask_T_1, 8'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_19 = _lcam_younger_load_mask_lo_mask_T_18[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_20 = {6'h0, _lcam_younger_load_mask_lo_mask_T_1, 9'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_21 = _lcam_younger_load_mask_lo_mask_T_20[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_22 = {5'h0, _lcam_younger_load_mask_lo_mask_T_1, 10'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_23 = _lcam_younger_load_mask_lo_mask_T_22[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_24 = {4'h0, _lcam_younger_load_mask_lo_mask_T_1, 11'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_25 = _lcam_younger_load_mask_lo_mask_T_24[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_26 = {3'h0, _lcam_younger_load_mask_lo_mask_T_1, 12'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_27 = _lcam_younger_load_mask_lo_mask_T_26[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_28 = {2'h0, _lcam_younger_load_mask_lo_mask_T_1, 13'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_29 = _lcam_younger_load_mask_lo_mask_T_28[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_30 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1, 14'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_31 = _lcam_younger_load_mask_lo_mask_T_30[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_32 = {_lcam_younger_load_mask_lo_mask_T_1, 15'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_33 = _lcam_younger_load_mask_lo_mask_T_32[15:0]; // @[util.scala:394:{30,37}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_34 = _lcam_younger_load_mask_lo_mask_T_3 \| _lcam_younger_load_mask_lo_mask_T_5; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_35 = _lcam_younger_load_mask_lo_mask_T_34 \| _lcam_younger_load_mask_lo_mask_T_7; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_36 = _lcam_younger_load_mask_lo_mask_T_35 \| _lcam_younger_load_mask_lo_mask_T_9; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_37 = _lcam_younger_load_mask_lo_mask_T_36 \| _lcam_younger_load_mask_lo_mask_T_11; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_38 = _lcam_younger_load_mask_lo_mask_T_37 \| _lcam_younger_load_mask_lo_mask_T_13; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_39 = _lcam_younger_load_mask_lo_mask_T_38 \| _lcam_younger_load_mask_lo_mask_T_15; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_40 = _lcam_younger_load_mask_lo_mask_T_39 \| _lcam_younger_load_mask_lo_mask_T_17; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_41 = _lcam_younger_load_mask_lo_mask_T_40 \| _lcam_younger_load_mask_lo_mask_T_19; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_42 = _lcam_younger_load_mask_lo_mask_T_41 \| _lcam_younger_load_mask_lo_mask_T_21; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_43 = _lcam_younger_load_mask_lo_mask_T_42 \| _lcam_younger_load_mask_lo_mask_T_23; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_44 = _lcam_younger_load_mask_lo_mask_T_43 \| _lcam_younger_load_mask_lo_mask_T_25; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_45 = _lcam_younger_load_mask_lo_mask_T_44 \| _lcam_younger_load_mask_lo_mask_T_27; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_46 = _lcam_younger_load_mask_lo_mask_T_45 \| _lcam_younger_load_mask_lo_mask_T_29; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_47 = _lcam_younger_load_mask_lo_mask_T_46 \| _lcam_younger_load_mask_lo_mask_T_31; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_48 = _lcam_younger_load_mask_lo_mask_T_47 \| _lcam_younger_load_mask_lo_mask_T_33; // @[util.scala:394:{37,54}] wire [15:0] lcam_younger_load_mask_lo_mask = ~_lcam_younger_load_mask_lo_mask_T_48; // @[util.scala:371:19, :394:54] wire _lcam_younger_load_mask_T = lcam_ldq_idx_0 < ldq_head; // @[util.scala:372:11] wire [15:0] _lcam_younger_load_mask_T_1 = lcam_younger_load_mask_hi_mask & lcam_younger_load_mask_lo_mask; // @[util.scala:370:19, :371:19, :372:27] wire [15:0] _lcam_younger_load_mask_T_2 = lcam_younger_load_mask_hi_mask \| lcam_younger_load_mask_lo_mask; // @[util.scala:370:19, :371:19, :372:46] wire [15:0] _lcam_younger_load_mask_T_3 = _lcam_younger_load_mask_T ? _lcam_younger_load_mask_T_1 : _lcam_younger_load_mask_T_2; // @[util.scala:372:{8,11,27,46}] wire [15:0] _lcam_younger_load_mask_T_4 = _lcam_younger_load_mask_T_3; // @[util.scala:372:{8,56}] wire [15:0] lcam_younger_load_mask_0 = _lcam_younger_load_mask_T_4; // @[util.scala:372:56] wire _can_forward_T_1 = _can_forward_T \| fired_load_retry_0; // @[lsu.scala:321:49, :1154:{58,85}] wire _can_forward_T_2 = ~mem_tlb_uncacheable_0; // @[lsu.scala:1071:41, :1155:5] wire _can_forward_T_3 = ~mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:1056:37, :1156:5] wire _can_forward_T_4 = _can_forward_T_1 ? _can_forward_T_2 : _can_forward_T_3; // @[lsu.scala:1154:{38,85}, :1155:5, :1156:5] wire can_forward_0 = _can_forward_T_4; // @[lsu.scala:321:49, :1154:38] wire kill_forward_0; // @[lsu.scala:1159:30] wire [15:0] _ldst_addr_matches_0_T_2; // @[lsu.scala:1344:79] wire [15:0] ldst_addr_matches_0; // @[lsu.scala:1162:34] wire [15:0] _ldst_forward_matches_0_T_2; // @[lsu.scala:1345:82] wire [15:0] ldst_forward_matches_0; // @[lsu.scala:1164:34] wire [15:0] _stld_prs2_matches_0_T_3; // @[lsu.scala:1346:80] wire [15:0] stld_prs2_matches_0; // @[lsu.scala:1166:34] reg s1_executing_loads_0; // @[lsu.scala:1168:35] reg s1_executing_loads_1; // @[lsu.scala:1168:35] reg s1_executing_loads_2; // @[lsu.scala:1168:35] reg s1_executing_loads_3; // @[lsu.scala:1168:35] reg s1_executing_loads_4; // @[lsu.scala:1168:35] reg s1_executing_loads_5; // @[lsu.scala:1168:35] reg s1_executing_loads_6; // @[lsu.scala:1168:35] reg s1_executing_loads_7; // @[lsu.scala:1168:35] reg s1_executing_loads_8; // @[lsu.scala:1168:35] reg s1_executing_loads_9; // @[lsu.scala:1168:35] reg s1_executing_loads_10; // @[lsu.scala:1168:35] reg s1_executing_loads_11; // @[lsu.scala:1168:35] reg s1_executing_loads_12; // @[lsu.scala:1168:35] reg s1_executing_loads_13; // @[lsu.scala:1168:35] reg s1_executing_loads_14; // @[lsu.scala:1168:35] reg s1_executing_loads_15; // @[lsu.scala:1168:35] wire s1_set_execute_0; // @[lsu.scala:1169:36] wire s1_set_execute_1; // @[lsu.scala:1169:36] wire s1_set_execute_2; // @[lsu.scala:1169:36] wire s1_set_execute_3; // @[lsu.scala:1169:36] wire s1_set_execute_4; // @[lsu.scala:1169:36] wire s1_set_execute_5; // @[lsu.scala:1169:36] wire s1_set_execute_6; // @[lsu.scala:1169:36] wire s1_set_execute_7; // @[lsu.scala:1169:36] wire s1_set_execute_8; // @[lsu.scala:1169:36] wire s1_set_execute_9; // @[lsu.scala:1169:36] wire s1_set_execute_10; // @[lsu.scala:1169:36] wire s1_set_execute_11; // @[lsu.scala:1169:36] wire s1_set_execute_12; // @[lsu.scala:1169:36] wire s1_set_execute_13; // @[lsu.scala:1169:36] wire s1_set_execute_14; // @[lsu.scala:1169:36] wire s1_set_execute_15; // @[lsu.scala:1169:36] reg [15:0] wb_ldst_forward_matches_0; // @[lsu.scala:1171:41] wire _wb_ldst_forward_valid_0_T_11; // @[lsu.scala:1380:100] wire wb_ldst_forward_valid_0; // @[lsu.scala:1172:38] wire [31:0] wb_ldst_forward_e_out_uop_inst = wb_ldst_forward_e_e_bits_uop_inst; // @[util.scala:109:23] wire [31:0] wb_ldst_forward_e_out_uop_debug_inst = wb_ldst_forward_e_e_bits_uop_debug_inst; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_rvc = wb_ldst_forward_e_e_bits_uop_is_rvc; // @[util.scala:109:23] wire [39:0] wb_ldst_forward_e_out_uop_debug_pc = wb_ldst_forward_e_e_bits_uop_debug_pc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_0 = wb_ldst_forward_e_e_bits_uop_iq_type_0; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_1 = wb_ldst_forward_e_e_bits_uop_iq_type_1; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_2 = wb_ldst_forward_e_e_bits_uop_iq_type_2; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_3 = wb_ldst_forward_e_e_bits_uop_iq_type_3; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_0 = wb_ldst_forward_e_e_bits_uop_fu_code_0; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_1 = wb_ldst_forward_e_e_bits_uop_fu_code_1; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_2 = wb_ldst_forward_e_e_bits_uop_fu_code_2; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_3 = wb_ldst_forward_e_e_bits_uop_fu_code_3; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_4 = wb_ldst_forward_e_e_bits_uop_fu_code_4; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_5 = wb_ldst_forward_e_e_bits_uop_fu_code_5; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_6 = wb_ldst_forward_e_e_bits_uop_fu_code_6; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_7 = wb_ldst_forward_e_e_bits_uop_fu_code_7; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_8 = wb_ldst_forward_e_e_bits_uop_fu_code_8; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_9 = wb_ldst_forward_e_e_bits_uop_fu_code_9; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_issued = wb_ldst_forward_e_e_bits_uop_iw_issued; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_issued_partial_agen = wb_ldst_forward_e_e_bits_uop_iw_issued_partial_agen; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_issued_partial_dgen = wb_ldst_forward_e_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_iw_p1_speculative_child = wb_ldst_forward_e_e_bits_uop_iw_p1_speculative_child; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_iw_p2_speculative_child = wb_ldst_forward_e_e_bits_uop_iw_p2_speculative_child; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_p1_bypass_hint = wb_ldst_forward_e_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_p2_bypass_hint = wb_ldst_forward_e_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_p3_bypass_hint = wb_ldst_forward_e_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_dis_col_sel = wb_ldst_forward_e_e_bits_uop_dis_col_sel; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_uop_br_tag = wb_ldst_forward_e_e_bits_uop_br_tag; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_uop_br_type = wb_ldst_forward_e_e_bits_uop_br_type; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_sfb = wb_ldst_forward_e_e_bits_uop_is_sfb; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_fence = wb_ldst_forward_e_e_bits_uop_is_fence; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_fencei = wb_ldst_forward_e_e_bits_uop_is_fencei; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_sfence = wb_ldst_forward_e_e_bits_uop_is_sfence; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_amo = wb_ldst_forward_e_e_bits_uop_is_amo; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_eret = wb_ldst_forward_e_e_bits_uop_is_eret; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_sys_pc2epc = wb_ldst_forward_e_e_bits_uop_is_sys_pc2epc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_rocc = wb_ldst_forward_e_e_bits_uop_is_rocc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_mov = wb_ldst_forward_e_e_bits_uop_is_mov; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_ftq_idx = wb_ldst_forward_e_e_bits_uop_ftq_idx; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_edge_inst = wb_ldst_forward_e_e_bits_uop_edge_inst; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_pc_lob = wb_ldst_forward_e_e_bits_uop_pc_lob; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_taken = wb_ldst_forward_e_e_bits_uop_taken; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_imm_rename = wb_ldst_forward_e_e_bits_uop_imm_rename; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_imm_sel = wb_ldst_forward_e_e_bits_uop_imm_sel; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_pimm = wb_ldst_forward_e_e_bits_uop_pimm; // @[util.scala:109:23] wire [19:0] wb_ldst_forward_e_out_uop_imm_packed = wb_ldst_forward_e_e_bits_uop_imm_packed; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_op1_sel = wb_ldst_forward_e_e_bits_uop_op1_sel; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_op2_sel = wb_ldst_forward_e_e_bits_uop_op2_sel; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ldst = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ldst; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_wen = wb_ldst_forward_e_e_bits_uop_fp_ctrl_wen; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ren1 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren1; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ren2 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren2; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ren3 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren3; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_swap12 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap12; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_swap23 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap23; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_fp_ctrl_typeTagIn = wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_fp_ctrl_typeTagOut = wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_fromint = wb_ldst_forward_e_e_bits_uop_fp_ctrl_fromint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_toint = wb_ldst_forward_e_e_bits_uop_fp_ctrl_toint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_fastpipe = wb_ldst_forward_e_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_fma = wb_ldst_forward_e_e_bits_uop_fp_ctrl_fma; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_div = wb_ldst_forward_e_e_bits_uop_fp_ctrl_div; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_sqrt = wb_ldst_forward_e_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_wflags = wb_ldst_forward_e_e_bits_uop_fp_ctrl_wflags; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_vec = wb_ldst_forward_e_e_bits_uop_fp_ctrl_vec; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_rob_idx = wb_ldst_forward_e_e_bits_uop_rob_idx; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_uop_ldq_idx = wb_ldst_forward_e_e_bits_uop_ldq_idx; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_uop_stq_idx = wb_ldst_forward_e_e_bits_uop_stq_idx; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_rxq_idx = wb_ldst_forward_e_e_bits_uop_rxq_idx; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_pdst = wb_ldst_forward_e_e_bits_uop_pdst; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_prs1 = wb_ldst_forward_e_e_bits_uop_prs1; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_prs2 = wb_ldst_forward_e_e_bits_uop_prs2; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_prs3 = wb_ldst_forward_e_e_bits_uop_prs3; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_ppred = wb_ldst_forward_e_e_bits_uop_ppred; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_prs1_busy = wb_ldst_forward_e_e_bits_uop_prs1_busy; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_prs2_busy = wb_ldst_forward_e_e_bits_uop_prs2_busy; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_prs3_busy = wb_ldst_forward_e_e_bits_uop_prs3_busy; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_ppred_busy = wb_ldst_forward_e_e_bits_uop_ppred_busy; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_stale_pdst = wb_ldst_forward_e_e_bits_uop_stale_pdst; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_exception = wb_ldst_forward_e_e_bits_uop_exception; // @[util.scala:109:23] wire [63:0] wb_ldst_forward_e_out_uop_exc_cause = wb_ldst_forward_e_e_bits_uop_exc_cause; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_mem_cmd = wb_ldst_forward_e_e_bits_uop_mem_cmd; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_mem_size = wb_ldst_forward_e_e_bits_uop_mem_size; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_mem_signed = wb_ldst_forward_e_e_bits_uop_mem_signed; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_uses_ldq = wb_ldst_forward_e_e_bits_uop_uses_ldq; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_uses_stq = wb_ldst_forward_e_e_bits_uop_uses_stq; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_unique = wb_ldst_forward_e_e_bits_uop_is_unique; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_flush_on_commit = wb_ldst_forward_e_e_bits_uop_flush_on_commit; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_csr_cmd = wb_ldst_forward_e_e_bits_uop_csr_cmd; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_ldst_is_rs1 = wb_ldst_forward_e_e_bits_uop_ldst_is_rs1; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_ldst = wb_ldst_forward_e_e_bits_uop_ldst; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_lrs1 = wb_ldst_forward_e_e_bits_uop_lrs1; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_lrs2 = wb_ldst_forward_e_e_bits_uop_lrs2; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_lrs3 = wb_ldst_forward_e_e_bits_uop_lrs3; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_dst_rtype = wb_ldst_forward_e_e_bits_uop_dst_rtype; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_lrs1_rtype = wb_ldst_forward_e_e_bits_uop_lrs1_rtype; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_lrs2_rtype = wb_ldst_forward_e_e_bits_uop_lrs2_rtype; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_frs3_en = wb_ldst_forward_e_e_bits_uop_frs3_en; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fcn_dw = wb_ldst_forward_e_e_bits_uop_fcn_dw; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_fcn_op = wb_ldst_forward_e_e_bits_uop_fcn_op; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_val = wb_ldst_forward_e_e_bits_uop_fp_val; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_fp_rm = wb_ldst_forward_e_e_bits_uop_fp_rm; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_fp_typ = wb_ldst_forward_e_e_bits_uop_fp_typ; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_xcpt_pf_if = wb_ldst_forward_e_e_bits_uop_xcpt_pf_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_xcpt_ae_if = wb_ldst_forward_e_e_bits_uop_xcpt_ae_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_xcpt_ma_if = wb_ldst_forward_e_e_bits_uop_xcpt_ma_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_bp_debug_if = wb_ldst_forward_e_e_bits_uop_bp_debug_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_bp_xcpt_if = wb_ldst_forward_e_e_bits_uop_bp_xcpt_if; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_debug_fsrc = wb_ldst_forward_e_e_bits_uop_debug_fsrc; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_debug_tsrc = wb_ldst_forward_e_e_bits_uop_debug_tsrc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_addr_valid = wb_ldst_forward_e_e_bits_addr_valid; // @[util.scala:109:23] wire [39:0] wb_ldst_forward_e_out_addr_bits = wb_ldst_forward_e_e_bits_addr_bits; // @[util.scala:109:23] wire wb_ldst_forward_e_out_addr_is_virtual = wb_ldst_forward_e_e_bits_addr_is_virtual; // @[util.scala:109:23] wire wb_ldst_forward_e_out_addr_is_uncacheable = wb_ldst_forward_e_e_bits_addr_is_uncacheable; // @[util.scala:109:23] wire wb_ldst_forward_e_out_executed = wb_ldst_forward_e_e_bits_executed; // @[util.scala:109:23] wire wb_ldst_forward_e_out_succeeded = wb_ldst_forward_e_e_bits_succeeded; // @[util.scala:109:23] wire wb_ldst_forward_e_out_order_fail = wb_ldst_forward_e_e_bits_order_fail; // @[util.scala:109:23] wire wb_ldst_forward_e_out_observed = wb_ldst_forward_e_e_bits_observed; // @[util.scala:109:23] wire [15:0] wb_ldst_forward_e_out_st_dep_mask = wb_ldst_forward_e_e_bits_st_dep_mask; // @[util.scala:109:23] wire [7:0] wb_ldst_forward_e_out_ld_byte_mask = wb_ldst_forward_e_e_bits_ld_byte_mask; // @[util.scala:109:23] wire wb_ldst_forward_e_out_forward_std_val = wb_ldst_forward_e_e_bits_forward_std_val; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_forward_stq_idx = wb_ldst_forward_e_e_bits_forward_stq_idx; // @[util.scala:109:23] wire [63:0] wb_ldst_forward_e_out_debug_wb_data = wb_ldst_forward_e_e_bits_debug_wb_data; // @[util.scala:109:23] wire [11:0] wb_ldst_forward_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_valid; // @[lsu.scala:233:17] wire [3:0] _wb_ldst_forward_e_e_valid_T_1 = _wb_ldst_forward_e_e_valid_T; assign wb_ldst_forward_e_e_valid = _GEN_25[_wb_ldst_forward_e_e_valid_T_1]; // @[lsu.scala:233:17, :234:32, :387:15] wire [3:0] _wb_ldst_forward_e_e_bits_uop_T_1 = _wb_ldst_forward_e_e_bits_uop_T; assign wb_ldst_forward_e_e_bits_uop_inst = _GEN_76[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_inst = _GEN_77[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_rvc = _GEN_78[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_pc = _GEN_79[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_0 = _GEN_80[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_1 = _GEN_81[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_2 = _GEN_82[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_3 = _GEN_83[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_0 = _GEN_84[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_1 = _GEN_85[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_2 = _GEN_86[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_3 = _GEN_87[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_4 = _GEN_88[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_5 = _GEN_89[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_6 = _GEN_90[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_7 = _GEN_91[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_8 = _GEN_92[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_9 = _GEN_93[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_issued = _GEN_94[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_issued_partial_agen = _GEN_95[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_issued_partial_dgen = _GEN_96[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p1_speculative_child = _GEN_97[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p2_speculative_child = _GEN_98[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p1_bypass_hint = _GEN_99[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p2_bypass_hint = _GEN_100[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p3_bypass_hint = _GEN_101[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_dis_col_sel = _GEN_102[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_br_mask = _GEN_103[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_br_tag = _GEN_104[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_br_type = _GEN_105[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_sfb = _GEN_106[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_fence = _GEN_107[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_fencei = _GEN_108[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_sfence = _GEN_109[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_amo = _GEN_110[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_eret = _GEN_111[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_sys_pc2epc = _GEN_112[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_rocc = _GEN_113[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_mov = _GEN_114[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ftq_idx = _GEN_115[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_edge_inst = _GEN_116[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_pc_lob = _GEN_117[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_taken = _GEN_118[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_imm_rename = _GEN_119[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_imm_sel = _GEN_120[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_pimm = _GEN_121[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_imm_packed = _GEN_122[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_op1_sel = _GEN_123[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_op2_sel = _GEN_124[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ldst = _GEN_125[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_wen = _GEN_126[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren1 = _GEN_127[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren2 = _GEN_128[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren3 = _GEN_129[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap12 = _GEN_130[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap23 = _GEN_131[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_132[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_133[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_fromint = _GEN_134[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_toint = _GEN_135[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_136[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_fma = _GEN_137[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_div = _GEN_138[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_sqrt = _GEN_139[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_wflags = _GEN_140[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_vec = _GEN_141[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_rob_idx = _GEN_142[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ldq_idx = _GEN_143[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_stq_idx = _GEN_144[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_rxq_idx = _GEN_145[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_pdst = _GEN_146[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs1 = _GEN_147[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs2 = _GEN_148[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs3 = _GEN_149[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ppred = _GEN_150[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs1_busy = _GEN_151[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs2_busy = _GEN_152[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs3_busy = _GEN_153[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ppred_busy = _GEN_154[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_stale_pdst = _GEN_155[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_exception = _GEN_156[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_exc_cause = _GEN_157[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_mem_cmd = _GEN_158[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_mem_size = _GEN_159[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_mem_signed = _GEN_160[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_uses_ldq = _GEN_161[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_uses_stq = _GEN_162[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_unique = _GEN_163[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_flush_on_commit = _GEN_164[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_csr_cmd = _GEN_165[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ldst_is_rs1 = _GEN_166[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ldst = _GEN_167[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs1 = _GEN_168[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs2 = _GEN_169[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs3 = _GEN_170[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_dst_rtype = _GEN_171[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs1_rtype = _GEN_172[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs2_rtype = _GEN_173[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_frs3_en = _GEN_174[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fcn_dw = _GEN_175[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fcn_op = _GEN_176[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_val = _GEN_177[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_rm = _GEN_178[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_typ = _GEN_179[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_xcpt_pf_if = _GEN_180[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_xcpt_ae_if = _GEN_181[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_xcpt_ma_if = _GEN_182[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_bp_debug_if = _GEN_183[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_bp_xcpt_if = _GEN_184[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_fsrc = _GEN_185[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_tsrc = _GEN_186[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] wire [3:0] _wb_ldst_forward_e_e_bits_addr_T_1 = _wb_ldst_forward_e_e_bits_addr_T; assign wb_ldst_forward_e_e_bits_addr_valid = _GEN_187[_wb_ldst_forward_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] assign wb_ldst_forward_e_e_bits_addr_bits = _GEN_188[_wb_ldst_forward_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] wire [3:0] _wb_ldst_forward_e_e_bits_addr_is_virtual_T_1 = _wb_ldst_forward_e_e_bits_addr_is_virtual_T; assign wb_ldst_forward_e_e_bits_addr_is_virtual = _GEN_189[_wb_ldst_forward_e_e_bits_addr_is_virtual_T_1]; // @[lsu.scala:233:17, :237:32] wire [3:0] _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T_1 = _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T; assign wb_ldst_forward_e_e_bits_addr_is_uncacheable = _GEN_190[_wb_ldst_forward_e_e_bits_addr_is_uncacheable_T_1]; // @[lsu.scala:233:17, :238:32] wire [3:0] _wb_ldst_forward_e_e_bits_executed_T_1 = _wb_ldst_forward_e_e_bits_executed_T; assign wb_ldst_forward_e_e_bits_executed = _GEN_191[_wb_ldst_forward_e_e_bits_executed_T_1]; // @[lsu.scala:233:17, :239:32] wire [3:0] _wb_ldst_forward_e_e_bits_succeeded_T_1 = _wb_ldst_forward_e_e_bits_succeeded_T; assign wb_ldst_forward_e_e_bits_succeeded = _GEN_192[_wb_ldst_forward_e_e_bits_succeeded_T_1]; // @[lsu.scala:233:17, :240:32] wire [3:0] _wb_ldst_forward_e_e_bits_order_fail_T_1 = _wb_ldst_forward_e_e_bits_order_fail_T; assign wb_ldst_forward_e_e_bits_order_fail = _GEN_193[_wb_ldst_forward_e_e_bits_order_fail_T_1]; // @[lsu.scala:233:17, :241:32] wire [3:0] _wb_ldst_forward_e_e_bits_observed_T_1 = _wb_ldst_forward_e_e_bits_observed_T; assign wb_ldst_forward_e_e_bits_observed = _GEN_194[_wb_ldst_forward_e_e_bits_observed_T_1]; // @[lsu.scala:233:17, :242:32] wire [3:0] _wb_ldst_forward_e_e_bits_st_dep_mask_T_1 = _wb_ldst_forward_e_e_bits_st_dep_mask_T; assign wb_ldst_forward_e_e_bits_st_dep_mask = _GEN_195[_wb_ldst_forward_e_e_bits_st_dep_mask_T_1]; // @[lsu.scala:233:17, :243:32] wire [3:0] _wb_ldst_forward_e_e_bits_ld_byte_mask_T_1 = _wb_ldst_forward_e_e_bits_ld_byte_mask_T; assign wb_ldst_forward_e_e_bits_ld_byte_mask = _GEN_196[_wb_ldst_forward_e_e_bits_ld_byte_mask_T_1]; // @[lsu.scala:233:17, :244:32] wire [3:0] _wb_ldst_forward_e_e_bits_forward_std_val_T_1 = _wb_ldst_forward_e_e_bits_forward_std_val_T; assign wb_ldst_forward_e_e_bits_forward_std_val = _GEN_197[_wb_ldst_forward_e_e_bits_forward_std_val_T_1]; // @[lsu.scala:233:17, :245:32] wire [3:0] _wb_ldst_forward_e_e_bits_forward_stq_idx_T_1 = _wb_ldst_forward_e_e_bits_forward_stq_idx_T; assign wb_ldst_forward_e_e_bits_forward_stq_idx = _GEN_198[_wb_ldst_forward_e_e_bits_forward_stq_idx_T_1]; // @[lsu.scala:233:17, :246:32] wire [3:0] _wb_ldst_forward_e_e_bits_debug_wb_data_T_1 = _wb_ldst_forward_e_e_bits_debug_wb_data_T; assign wb_ldst_forward_e_e_bits_debug_wb_data = _GEN_199[_wb_ldst_forward_e_e_bits_debug_wb_data_T_1]; // @[lsu.scala:233:17, :247:32] wire [11:0] _wb_ldst_forward_e_out_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] wb_ldst_forward_e_out_uop_br_mask; // @[util.scala:109:23] wire [11:0] _wb_ldst_forward_e_out_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _wb_ldst_forward_e_out_uop_br_mask_T_1 = wb_ldst_forward_e_e_bits_uop_br_mask & _wb_ldst_forward_e_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign wb_ldst_forward_e_out_uop_br_mask = _wb_ldst_forward_e_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] reg [31:0] wb_ldst_forward_e_REG_uop_inst; // @[lsu.scala:1173:55] wire [31:0] wb_ldst_forward_e_0_uop_inst = wb_ldst_forward_e_REG_uop_inst; // @[lsu.scala:321:49, :1173:55] reg [31:0] wb_ldst_forward_e_REG_uop_debug_inst; // @[lsu.scala:1173:55] wire [31:0] wb_ldst_forward_e_0_uop_debug_inst = wb_ldst_forward_e_REG_uop_debug_inst; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_rvc; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_rvc = wb_ldst_forward_e_REG_uop_is_rvc; // @[lsu.scala:321:49, :1173:55] reg [39:0] wb_ldst_forward_e_REG_uop_debug_pc; // @[lsu.scala:1173:55] wire [39:0] wb_ldst_forward_e_0_uop_debug_pc = wb_ldst_forward_e_REG_uop_debug_pc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_0; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_0 = wb_ldst_forward_e_REG_uop_iq_type_0; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_1 = wb_ldst_forward_e_REG_uop_iq_type_1; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_2; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_2 = wb_ldst_forward_e_REG_uop_iq_type_2; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_3; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_3 = wb_ldst_forward_e_REG_uop_iq_type_3; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_0; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_0 = wb_ldst_forward_e_REG_uop_fu_code_0; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_1 = wb_ldst_forward_e_REG_uop_fu_code_1; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_2; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_2 = wb_ldst_forward_e_REG_uop_fu_code_2; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_3; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_3 = wb_ldst_forward_e_REG_uop_fu_code_3; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_4; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_4 = wb_ldst_forward_e_REG_uop_fu_code_4; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_5; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_5 = wb_ldst_forward_e_REG_uop_fu_code_5; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_6; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_6 = wb_ldst_forward_e_REG_uop_fu_code_6; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_7; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_7 = wb_ldst_forward_e_REG_uop_fu_code_7; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_8; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_8 = wb_ldst_forward_e_REG_uop_fu_code_8; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_9; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_9 = wb_ldst_forward_e_REG_uop_fu_code_9; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_issued; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_issued = wb_ldst_forward_e_REG_uop_iw_issued; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_issued_partial_agen; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_issued_partial_agen = wb_ldst_forward_e_REG_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_issued_partial_dgen; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_issued_partial_dgen = wb_ldst_forward_e_REG_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_iw_p1_speculative_child; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_iw_p1_speculative_child = wb_ldst_forward_e_REG_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_iw_p2_speculative_child; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_iw_p2_speculative_child = wb_ldst_forward_e_REG_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_p1_bypass_hint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_p1_bypass_hint = wb_ldst_forward_e_REG_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_p2_bypass_hint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_p2_bypass_hint = wb_ldst_forward_e_REG_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_p3_bypass_hint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_p3_bypass_hint = wb_ldst_forward_e_REG_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_dis_col_sel; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_dis_col_sel = wb_ldst_forward_e_REG_uop_dis_col_sel; // @[lsu.scala:321:49, :1173:55] reg [11:0] wb_ldst_forward_e_REG_uop_br_mask; // @[lsu.scala:1173:55] wire [11:0] wb_ldst_forward_e_0_uop_br_mask = wb_ldst_forward_e_REG_uop_br_mask; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_uop_br_tag; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_uop_br_tag = wb_ldst_forward_e_REG_uop_br_tag; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_uop_br_type; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_uop_br_type = wb_ldst_forward_e_REG_uop_br_type; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_sfb; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_sfb = wb_ldst_forward_e_REG_uop_is_sfb; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_fence; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_fence = wb_ldst_forward_e_REG_uop_is_fence; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_fencei; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_fencei = wb_ldst_forward_e_REG_uop_is_fencei; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_sfence; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_sfence = wb_ldst_forward_e_REG_uop_is_sfence; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_amo; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_amo = wb_ldst_forward_e_REG_uop_is_amo; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_eret; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_eret = wb_ldst_forward_e_REG_uop_is_eret; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_sys_pc2epc; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_sys_pc2epc = wb_ldst_forward_e_REG_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_rocc; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_rocc = wb_ldst_forward_e_REG_uop_is_rocc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_mov; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_mov = wb_ldst_forward_e_REG_uop_is_mov; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_ftq_idx; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_ftq_idx = wb_ldst_forward_e_REG_uop_ftq_idx; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_edge_inst; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_edge_inst = wb_ldst_forward_e_REG_uop_edge_inst; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_pc_lob; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_pc_lob = wb_ldst_forward_e_REG_uop_pc_lob; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_taken; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_taken = wb_ldst_forward_e_REG_uop_taken; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_imm_rename; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_imm_rename = wb_ldst_forward_e_REG_uop_imm_rename; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_imm_sel; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_imm_sel = wb_ldst_forward_e_REG_uop_imm_sel; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_pimm; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_pimm = wb_ldst_forward_e_REG_uop_pimm; // @[lsu.scala:321:49, :1173:55] reg [19:0] wb_ldst_forward_e_REG_uop_imm_packed; // @[lsu.scala:1173:55] wire [19:0] wb_ldst_forward_e_0_uop_imm_packed = wb_ldst_forward_e_REG_uop_imm_packed; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_op1_sel; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_op1_sel = wb_ldst_forward_e_REG_uop_op1_sel; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_op2_sel; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_op2_sel = wb_ldst_forward_e_REG_uop_op2_sel; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ldst; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ldst = wb_ldst_forward_e_REG_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_wen; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_wen = wb_ldst_forward_e_REG_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ren1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ren1 = wb_ldst_forward_e_REG_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ren2; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ren2 = wb_ldst_forward_e_REG_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ren3; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ren3 = wb_ldst_forward_e_REG_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_swap12; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_swap12 = wb_ldst_forward_e_REG_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_swap23; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_swap23 = wb_ldst_forward_e_REG_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_fp_ctrl_typeTagIn = wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_fp_ctrl_typeTagOut = wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_fromint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_fromint = wb_ldst_forward_e_REG_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_toint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_toint = wb_ldst_forward_e_REG_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_fastpipe; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_fastpipe = wb_ldst_forward_e_REG_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_fma; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_fma = wb_ldst_forward_e_REG_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_div; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_div = wb_ldst_forward_e_REG_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_sqrt; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_sqrt = wb_ldst_forward_e_REG_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_wflags; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_wflags = wb_ldst_forward_e_REG_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_vec; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_vec = wb_ldst_forward_e_REG_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_rob_idx; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_rob_idx = wb_ldst_forward_e_REG_uop_rob_idx; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_uop_ldq_idx; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_uop_ldq_idx = wb_ldst_forward_e_REG_uop_ldq_idx; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_uop_stq_idx; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_uop_stq_idx = wb_ldst_forward_e_REG_uop_stq_idx; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_rxq_idx; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_rxq_idx = wb_ldst_forward_e_REG_uop_rxq_idx; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_pdst; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_pdst = wb_ldst_forward_e_REG_uop_pdst; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_prs1; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_prs1 = wb_ldst_forward_e_REG_uop_prs1; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_prs2; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_prs2 = wb_ldst_forward_e_REG_uop_prs2; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_prs3; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_prs3 = wb_ldst_forward_e_REG_uop_prs3; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_ppred; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_ppred = wb_ldst_forward_e_REG_uop_ppred; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_prs1_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_prs1_busy = wb_ldst_forward_e_REG_uop_prs1_busy; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_prs2_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_prs2_busy = wb_ldst_forward_e_REG_uop_prs2_busy; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_prs3_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_prs3_busy = wb_ldst_forward_e_REG_uop_prs3_busy; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_ppred_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_ppred_busy = wb_ldst_forward_e_REG_uop_ppred_busy; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_stale_pdst; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_stale_pdst = wb_ldst_forward_e_REG_uop_stale_pdst; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_exception; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_exception = wb_ldst_forward_e_REG_uop_exception; // @[lsu.scala:321:49, :1173:55] reg [63:0] wb_ldst_forward_e_REG_uop_exc_cause; // @[lsu.scala:1173:55] wire [63:0] wb_ldst_forward_e_0_uop_exc_cause = wb_ldst_forward_e_REG_uop_exc_cause; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_mem_cmd; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_mem_cmd = wb_ldst_forward_e_REG_uop_mem_cmd; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_mem_size; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_mem_size = wb_ldst_forward_e_REG_uop_mem_size; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_mem_signed; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_mem_signed = wb_ldst_forward_e_REG_uop_mem_signed; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_uses_ldq; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_uses_ldq = wb_ldst_forward_e_REG_uop_uses_ldq; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_uses_stq; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_uses_stq = wb_ldst_forward_e_REG_uop_uses_stq; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_unique; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_unique = wb_ldst_forward_e_REG_uop_is_unique; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_flush_on_commit; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_flush_on_commit = wb_ldst_forward_e_REG_uop_flush_on_commit; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_csr_cmd; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_csr_cmd = wb_ldst_forward_e_REG_uop_csr_cmd; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_ldst_is_rs1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_ldst_is_rs1 = wb_ldst_forward_e_REG_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_ldst; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_ldst = wb_ldst_forward_e_REG_uop_ldst; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_lrs1; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_lrs1 = wb_ldst_forward_e_REG_uop_lrs1; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_lrs2; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_lrs2 = wb_ldst_forward_e_REG_uop_lrs2; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_lrs3; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_lrs3 = wb_ldst_forward_e_REG_uop_lrs3; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_dst_rtype; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_dst_rtype = wb_ldst_forward_e_REG_uop_dst_rtype; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_lrs1_rtype; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_lrs1_rtype = wb_ldst_forward_e_REG_uop_lrs1_rtype; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_lrs2_rtype; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_lrs2_rtype = wb_ldst_forward_e_REG_uop_lrs2_rtype; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_frs3_en; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_frs3_en = wb_ldst_forward_e_REG_uop_frs3_en; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fcn_dw; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fcn_dw = wb_ldst_forward_e_REG_uop_fcn_dw; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_fcn_op; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_fcn_op = wb_ldst_forward_e_REG_uop_fcn_op; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_val; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_val = wb_ldst_forward_e_REG_uop_fp_val; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_fp_rm; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_fp_rm = wb_ldst_forward_e_REG_uop_fp_rm; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_fp_typ; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_fp_typ = wb_ldst_forward_e_REG_uop_fp_typ; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_xcpt_pf_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_xcpt_pf_if = wb_ldst_forward_e_REG_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_xcpt_ae_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_xcpt_ae_if = wb_ldst_forward_e_REG_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_xcpt_ma_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_xcpt_ma_if = wb_ldst_forward_e_REG_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_bp_debug_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_bp_debug_if = wb_ldst_forward_e_REG_uop_bp_debug_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_bp_xcpt_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_bp_xcpt_if = wb_ldst_forward_e_REG_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_debug_fsrc; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_debug_fsrc = wb_ldst_forward_e_REG_uop_debug_fsrc; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_debug_tsrc; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_debug_tsrc = wb_ldst_forward_e_REG_uop_debug_tsrc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_addr_valid; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_addr_valid = wb_ldst_forward_e_REG_addr_valid; // @[lsu.scala:321:49, :1173:55] reg [39:0] wb_ldst_forward_e_REG_addr_bits; // @[lsu.scala:1173:55] wire [39:0] wb_ldst_forward_e_0_addr_bits = wb_ldst_forward_e_REG_addr_bits; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_addr_is_virtual; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_addr_is_virtual = wb_ldst_forward_e_REG_addr_is_virtual; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_addr_is_uncacheable; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_addr_is_uncacheable = wb_ldst_forward_e_REG_addr_is_uncacheable; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_executed; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_executed = wb_ldst_forward_e_REG_executed; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_succeeded; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_succeeded = wb_ldst_forward_e_REG_succeeded; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_order_fail; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_order_fail = wb_ldst_forward_e_REG_order_fail; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_observed; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_observed = wb_ldst_forward_e_REG_observed; // @[lsu.scala:321:49, :1173:55] reg [15:0] wb_ldst_forward_e_REG_st_dep_mask; // @[lsu.scala:1173:55] wire [15:0] wb_ldst_forward_e_0_st_dep_mask = wb_ldst_forward_e_REG_st_dep_mask; // @[lsu.scala:321:49, :1173:55] reg [7:0] wb_ldst_forward_e_REG_ld_byte_mask; // @[lsu.scala:1173:55] wire [7:0] wb_ldst_forward_e_0_ld_byte_mask = wb_ldst_forward_e_REG_ld_byte_mask; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_forward_std_val; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_forward_std_val = wb_ldst_forward_e_REG_forward_std_val; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_forward_stq_idx; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_forward_stq_idx = wb_ldst_forward_e_REG_forward_stq_idx; // @[lsu.scala:321:49, :1173:55] reg [63:0] wb_ldst_forward_e_REG_debug_wb_data; // @[lsu.scala:1173:55] wire [63:0] wb_ldst_forward_e_0_debug_wb_data = wb_ldst_forward_e_REG_debug_wb_data; // @[lsu.scala:321:49, :1173:55] wire [1:0] size_1 = wb_ldst_forward_e_0_uop_mem_size; // @[AMOALU.scala:11:18] reg [3:0] wb_ldst_forward_ldq_idx_0; // @[lsu.scala:1174:41] reg [39:0] wb_ldst_forward_ld_addr_0; // @[lsu.scala:1175:41] wire [3:0] wb_ldst_forward_stq_idx_0; // @[lsu.scala:1176:38] wire failed_load; // @[lsu.scala:1178:29] wire [33:0] _block_addr_matches_T = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_3 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_6 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_9 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_12 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_15 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_18 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_21 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_24 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_27 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_30 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_33 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_36 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_39 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_42 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_45 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_1 = ldq_addr_0_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_2 = _block_addr_matches_T == _block_addr_matches_T_1; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_0 = _block_addr_matches_T_2; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_4 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_8 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_12 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_16 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_20 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_24 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_28 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_32 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_36 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_40 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_44 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_48 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_52 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_56 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_60 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_1 = ldq_addr_0_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_2 = _dword_addr_matches_T == _dword_addr_matches_T_1; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_3 = block_addr_matches_0 & _dword_addr_matches_T_2; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_0 = _dword_addr_matches_T_3; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_392 = ldq_ld_byte_mask_0 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T; // @[lsu.scala:1197:46] assign _mask_match_T = _GEN_392; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T; // @[lsu.scala:1198:46] assign _mask_overlap_T = _GEN_392; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_1 = _mask_match_T == ldq_ld_byte_mask_0; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_0 = _mask_match_T_1; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_1 = \|_mask_overlap_T; // @[lsu.scala:1198:{46,62}] wire mask_overlap_0 = _mask_overlap_T_1; // @[lsu.scala:321:49, :1198:62] wire _T_290 = ldq_executed_0 \| ldq_succeeded_0; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _GEN_393 = {12'h0, lcam_stq_idx_0}; // @[lsu.scala:321:49, :1218:33] wire [15:0] _T_266 = ldq_st_dep_mask_0 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_270 = do_st_search_0 & ldq_valid_0 & ldq_addr_0_valid & _T_290 & ~ldq_addr_is_virtual_0 & _T_266[0] & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T = ldq_forward_stq_idx_0 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_1 = ldq_forward_stq_idx_0 < l_uop_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_2 = _forwarded_is_older_T ^ _forwarded_is_older_T_1; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_3 = lcam_stq_idx_0 < l_uop_stq_idx; // @[util.scala:364:78] wire forwarded_is_older = _forwarded_is_older_T_2 ^ _forwarded_is_older_T_3; // @[util.scala:364:{58,72,78}] wire _T_274 = ~ldq_forward_std_val_0 \| ldq_forward_stq_idx_0 != lcam_stq_idx_0 & forwarded_is_older; // @[util.scala:364:72] wire _GEN_394 = _T_270 & _T_274; // @[lsu.scala:1178:29, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76] wire _T_280 = do_ld_search_0 & ldq_valid_0 & ldq_addr_0_valid & ~ldq_addr_is_virtual_0 & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older = lcam_younger_load_mask_0[0]; // @[lsu.scala:321:49, :1237:58] wire _T_299 = ldq_executed_0 & (ldq_succeeded_0 \| ldq_will_succeed_0); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_395 = lcam_ldq_idx_0 == 4'h0; // @[lsu.scala:321:49, :1254:48] wire _GEN_396 = lcam_ldq_idx_0 == 4'h1; // @[lsu.scala:321:49, :1254:48] wire _GEN_397 = lcam_ldq_idx_0 == 4'h2; // @[lsu.scala:321:49, :1254:48] wire _GEN_398 = lcam_ldq_idx_0 == 4'h3; // @[lsu.scala:321:49, :1254:48] wire _GEN_399 = lcam_ldq_idx_0 == 4'h4; // @[lsu.scala:321:49, :1254:48] wire _GEN_400 = lcam_ldq_idx_0 == 4'h5; // @[lsu.scala:321:49, :1254:48] wire _GEN_401 = lcam_ldq_idx_0 == 4'h6; // @[lsu.scala:321:49, :1254:48] wire _GEN_402 = lcam_ldq_idx_0 == 4'h7; // @[lsu.scala:321:49, :1254:48] wire _GEN_403 = lcam_ldq_idx_0 == 4'h8; // @[lsu.scala:321:49, :1254:48] wire _GEN_404 = lcam_ldq_idx_0 == 4'h9; // @[lsu.scala:321:49, :1254:48] wire _GEN_405 = lcam_ldq_idx_0 == 4'hA; // @[lsu.scala:321:49, :1254:48] wire _GEN_406 = lcam_ldq_idx_0 == 4'hB; // @[lsu.scala:321:49, :1254:48] wire _GEN_407 = lcam_ldq_idx_0 == 4'hC; // @[lsu.scala:321:49, :1254:48] wire _GEN_408 = lcam_ldq_idx_0 == 4'hD; // @[lsu.scala:321:49, :1254:48] wire _GEN_409 = lcam_ldq_idx_0 == 4'hE; // @[lsu.scala:321:49, :1254:48] reg REG_1; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_4 = ldq_addr_1_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_5 = _block_addr_matches_T_3 == _block_addr_matches_T_4; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_1_0 = _block_addr_matches_T_5; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_5 = ldq_addr_1_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_6 = _dword_addr_matches_T_4 == _dword_addr_matches_T_5; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_7 = block_addr_matches_1_0 & _dword_addr_matches_T_6; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_1_0 = _dword_addr_matches_T_7; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_410 = ldq_ld_byte_mask_1 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_2; // @[lsu.scala:1197:46] assign _mask_match_T_2 = _GEN_410; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_2; // @[lsu.scala:1198:46] assign _mask_overlap_T_2 = _GEN_410; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_3 = _mask_match_T_2 == ldq_ld_byte_mask_1; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_1_0 = _mask_match_T_3; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_3 = \|_mask_overlap_T_2; // @[lsu.scala:1198:{46,62}] wire mask_overlap_1_0 = _mask_overlap_T_3; // @[lsu.scala:321:49, :1198:62] wire _T_342 = ldq_executed_1 \| ldq_succeeded_1; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_318 = ldq_st_dep_mask_1 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_4 = ldq_forward_stq_idx_1 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_5 = ldq_forward_stq_idx_1 < l_uop_1_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_6 = _forwarded_is_older_T_4 ^ _forwarded_is_older_T_5; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_7 = lcam_stq_idx_0 < l_uop_1_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_1 = _forwarded_is_older_T_6 ^ _forwarded_is_older_T_7; // @[util.scala:364:{58,72,78}] wire _GEN_411 = do_st_search_0 & ldq_valid_1 & ldq_addr_1_valid & _T_342 & ~ldq_addr_is_virtual_1 & _T_318[0] & dword_addr_matches_1_0 & mask_overlap_1_0 & (~ldq_forward_std_val_1 \| ldq_forward_stq_idx_1 != lcam_stq_idx_0 & forwarded_is_older_1); // @[util.scala:364:72] wire _T_332 = do_ld_search_0 & ldq_valid_1 & ldq_addr_1_valid & ~ldq_addr_is_virtual_1 & dword_addr_matches_1_0 & mask_overlap_1_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_1 = lcam_younger_load_mask_0[1]; // @[lsu.scala:321:49, :1237:58] wire _T_351 = ldq_executed_1 & (ldq_succeeded_1 \| ldq_will_succeed_1); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_412 = searcher_is_older_1 \| _GEN_396; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_2; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_7 = ldq_addr_2_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_8 = _block_addr_matches_T_6 == _block_addr_matches_T_7; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_2_0 = _block_addr_matches_T_8; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_9 = ldq_addr_2_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_10 = _dword_addr_matches_T_8 == _dword_addr_matches_T_9; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_11 = block_addr_matches_2_0 & _dword_addr_matches_T_10; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_2_0 = _dword_addr_matches_T_11; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_413 = ldq_ld_byte_mask_2 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_4; // @[lsu.scala:1197:46] assign _mask_match_T_4 = _GEN_413; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_4; // @[lsu.scala:1198:46] assign _mask_overlap_T_4 = _GEN_413; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_5 = _mask_match_T_4 == ldq_ld_byte_mask_2; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_2_0 = _mask_match_T_5; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_5 = \|_mask_overlap_T_4; // @[lsu.scala:1198:{46,62}] wire mask_overlap_2_0 = _mask_overlap_T_5; // @[lsu.scala:321:49, :1198:62] wire _T_394 = ldq_executed_2 \| ldq_succeeded_2; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_370 = ldq_st_dep_mask_2 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_374 = do_st_search_0 & ldq_valid_2 & ldq_addr_2_valid & _T_394 & ~ldq_addr_is_virtual_2 & _T_370[0] & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_8 = ldq_forward_stq_idx_2 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_9 = ldq_forward_stq_idx_2 < l_uop_2_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_10 = _forwarded_is_older_T_8 ^ _forwarded_is_older_T_9; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_11 = lcam_stq_idx_0 < l_uop_2_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_2 = _forwarded_is_older_T_10 ^ _forwarded_is_older_T_11; // @[util.scala:364:{58,72,78}] wire _T_378 = ~ldq_forward_std_val_2 \| ldq_forward_stq_idx_2 != lcam_stq_idx_0 & forwarded_is_older_2; // @[util.scala:364:72] wire _GEN_414 = _T_374 ? _T_378 \| _GEN_411 \| _GEN_394 : _GEN_411 \| _GEN_394; // @[lsu.scala:394:59, :1178:29, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_384 = do_ld_search_0 & ldq_valid_2 & ldq_addr_2_valid & ~ldq_addr_is_virtual_2 & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_2 = lcam_younger_load_mask_0[2]; // @[lsu.scala:321:49, :1237:58] wire _T_403 = ldq_executed_2 & (ldq_succeeded_2 \| ldq_will_succeed_2); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_415 = searcher_is_older_2 \| _GEN_397; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_3; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_10 = ldq_addr_3_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_11 = _block_addr_matches_T_9 == _block_addr_matches_T_10; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_3_0 = _block_addr_matches_T_11; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_13 = ldq_addr_3_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_14 = _dword_addr_matches_T_12 == _dword_addr_matches_T_13; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_15 = block_addr_matches_3_0 & _dword_addr_matches_T_14; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_3_0 = _dword_addr_matches_T_15; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_416 = ldq_ld_byte_mask_3 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_6; // @[lsu.scala:1197:46] assign _mask_match_T_6 = _GEN_416; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_6; // @[lsu.scala:1198:46] assign _mask_overlap_T_6 = _GEN_416; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_7 = _mask_match_T_6 == ldq_ld_byte_mask_3; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_3_0 = _mask_match_T_7; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_7 = \|_mask_overlap_T_6; // @[lsu.scala:1198:{46,62}] wire mask_overlap_3_0 = _mask_overlap_T_7; // @[lsu.scala:321:49, :1198:62] wire _T_446 = ldq_executed_3 \| ldq_succeeded_3; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_422 = ldq_st_dep_mask_3 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_12 = ldq_forward_stq_idx_3 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_13 = ldq_forward_stq_idx_3 < l_uop_3_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_14 = _forwarded_is_older_T_12 ^ _forwarded_is_older_T_13; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_15 = lcam_stq_idx_0 < l_uop_3_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_3 = _forwarded_is_older_T_14 ^ _forwarded_is_older_T_15; // @[util.scala:364:{58,72,78}] wire _GEN_417 = do_st_search_0 & ldq_valid_3 & ldq_addr_3_valid & _T_446 & ~ldq_addr_is_virtual_3 & _T_422[0] & dword_addr_matches_3_0 & mask_overlap_3_0 & (~ldq_forward_std_val_3 \| ldq_forward_stq_idx_3 != lcam_stq_idx_0 & forwarded_is_older_3); // @[util.scala:364:72] wire _T_436 = do_ld_search_0 & ldq_valid_3 & ldq_addr_3_valid & ~ldq_addr_is_virtual_3 & dword_addr_matches_3_0 & mask_overlap_3_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_3 = lcam_younger_load_mask_0[3]; // @[lsu.scala:321:49, :1237:58] wire _T_455 = ldq_executed_3 & (ldq_succeeded_3 \| ldq_will_succeed_3); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_418 = searcher_is_older_3 \| _GEN_398; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_4; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_13 = ldq_addr_4_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_14 = _block_addr_matches_T_12 == _block_addr_matches_T_13; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_4_0 = _block_addr_matches_T_14; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_17 = ldq_addr_4_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_18 = _dword_addr_matches_T_16 == _dword_addr_matches_T_17; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_19 = block_addr_matches_4_0 & _dword_addr_matches_T_18; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_4_0 = _dword_addr_matches_T_19; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_419 = ldq_ld_byte_mask_4 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_8; // @[lsu.scala:1197:46] assign _mask_match_T_8 = _GEN_419; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_8; // @[lsu.scala:1198:46] assign _mask_overlap_T_8 = _GEN_419; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_9 = _mask_match_T_8 == ldq_ld_byte_mask_4; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_4_0 = _mask_match_T_9; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_9 = \|_mask_overlap_T_8; // @[lsu.scala:1198:{46,62}] wire mask_overlap_4_0 = _mask_overlap_T_9; // @[lsu.scala:321:49, :1198:62] wire _T_498 = ldq_executed_4 \| ldq_succeeded_4; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_474 = ldq_st_dep_mask_4 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_478 = do_st_search_0 & ldq_valid_4 & ldq_addr_4_valid & _T_498 & ~ldq_addr_is_virtual_4 & _T_474[0] & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_16 = ldq_forward_stq_idx_4 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_17 = ldq_forward_stq_idx_4 < l_uop_4_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_18 = _forwarded_is_older_T_16 ^ _forwarded_is_older_T_17; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_19 = lcam_stq_idx_0 < l_uop_4_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_4 = _forwarded_is_older_T_18 ^ _forwarded_is_older_T_19; // @[util.scala:364:{58,72,78}] wire _T_482 = ~ldq_forward_std_val_4 \| ldq_forward_stq_idx_4 != lcam_stq_idx_0 & forwarded_is_older_4; // @[util.scala:364:72] wire _GEN_420 = _T_478 ? _T_482 \| _GEN_417 \| _GEN_414 : _GEN_417 \| _GEN_414; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_488 = do_ld_search_0 & ldq_valid_4 & ldq_addr_4_valid & ~ldq_addr_is_virtual_4 & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_4 = lcam_younger_load_mask_0[4]; // @[lsu.scala:321:49, :1237:58] wire _T_507 = ldq_executed_4 & (ldq_succeeded_4 \| ldq_will_succeed_4); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_421 = searcher_is_older_4 \| _GEN_399; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_5; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_16 = ldq_addr_5_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_17 = _block_addr_matches_T_15 == _block_addr_matches_T_16; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_5_0 = _block_addr_matches_T_17; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_21 = ldq_addr_5_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_22 = _dword_addr_matches_T_20 == _dword_addr_matches_T_21; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_23 = block_addr_matches_5_0 & _dword_addr_matches_T_22; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_5_0 = _dword_addr_matches_T_23; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_422 = ldq_ld_byte_mask_5 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_10; // @[lsu.scala:1197:46] assign _mask_match_T_10 = _GEN_422; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_10; // @[lsu.scala:1198:46] assign _mask_overlap_T_10 = _GEN_422; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_11 = _mask_match_T_10 == ldq_ld_byte_mask_5; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_5_0 = _mask_match_T_11; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_11 = \|_mask_overlap_T_10; // @[lsu.scala:1198:{46,62}] wire mask_overlap_5_0 = _mask_overlap_T_11; // @[lsu.scala:321:49, :1198:62] wire _T_550 = ldq_executed_5 \| ldq_succeeded_5; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_526 = ldq_st_dep_mask_5 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_20 = ldq_forward_stq_idx_5 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_21 = ldq_forward_stq_idx_5 < l_uop_5_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_22 = _forwarded_is_older_T_20 ^ _forwarded_is_older_T_21; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_23 = lcam_stq_idx_0 < l_uop_5_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_5 = _forwarded_is_older_T_22 ^ _forwarded_is_older_T_23; // @[util.scala:364:{58,72,78}] wire _GEN_423 = do_st_search_0 & ldq_valid_5 & ldq_addr_5_valid & _T_550 & ~ldq_addr_is_virtual_5 & _T_526[0] & dword_addr_matches_5_0 & mask_overlap_5_0 & (~ldq_forward_std_val_5 \| ldq_forward_stq_idx_5 != lcam_stq_idx_0 & forwarded_is_older_5); // @[util.scala:364:72] wire _T_540 = do_ld_search_0 & ldq_valid_5 & ldq_addr_5_valid & ~ldq_addr_is_virtual_5 & dword_addr_matches_5_0 & mask_overlap_5_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_5 = lcam_younger_load_mask_0[5]; // @[lsu.scala:321:49, :1237:58] wire _T_559 = ldq_executed_5 & (ldq_succeeded_5 \| ldq_will_succeed_5); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_424 = searcher_is_older_5 \| _GEN_400; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_6; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_19 = ldq_addr_6_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_20 = _block_addr_matches_T_18 == _block_addr_matches_T_19; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_6_0 = _block_addr_matches_T_20; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_25 = ldq_addr_6_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_26 = _dword_addr_matches_T_24 == _dword_addr_matches_T_25; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_27 = block_addr_matches_6_0 & _dword_addr_matches_T_26; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_6_0 = _dword_addr_matches_T_27; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_425 = ldq_ld_byte_mask_6 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_12; // @[lsu.scala:1197:46] assign _mask_match_T_12 = _GEN_425; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_12; // @[lsu.scala:1198:46] assign _mask_overlap_T_12 = _GEN_425; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_13 = _mask_match_T_12 == ldq_ld_byte_mask_6; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_6_0 = _mask_match_T_13; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_13 = \|_mask_overlap_T_12; // @[lsu.scala:1198:{46,62}] wire mask_overlap_6_0 = _mask_overlap_T_13; // @[lsu.scala:321:49, :1198:62] wire _T_602 = ldq_executed_6 \| ldq_succeeded_6; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_578 = ldq_st_dep_mask_6 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_582 = do_st_search_0 & ldq_valid_6 & ldq_addr_6_valid & _T_602 & ~ldq_addr_is_virtual_6 & _T_578[0] & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_24 = ldq_forward_stq_idx_6 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_25 = ldq_forward_stq_idx_6 < l_uop_6_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_26 = _forwarded_is_older_T_24 ^ _forwarded_is_older_T_25; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_27 = lcam_stq_idx_0 < l_uop_6_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_6 = _forwarded_is_older_T_26 ^ _forwarded_is_older_T_27; // @[util.scala:364:{58,72,78}] wire _T_586 = ~ldq_forward_std_val_6 \| ldq_forward_stq_idx_6 != lcam_stq_idx_0 & forwarded_is_older_6; // @[util.scala:364:72] wire _GEN_426 = _T_582 ? _T_586 \| _GEN_423 \| _GEN_420 : _GEN_423 \| _GEN_420; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_592 = do_ld_search_0 & ldq_valid_6 & ldq_addr_6_valid & ~ldq_addr_is_virtual_6 & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_6 = lcam_younger_load_mask_0[6]; // @[lsu.scala:321:49, :1237:58] wire _T_611 = ldq_executed_6 & (ldq_succeeded_6 \| ldq_will_succeed_6); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_427 = searcher_is_older_6 \| _GEN_401; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_7; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_22 = ldq_addr_7_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_23 = _block_addr_matches_T_21 == _block_addr_matches_T_22; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_7_0 = _block_addr_matches_T_23; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_29 = ldq_addr_7_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_30 = _dword_addr_matches_T_28 == _dword_addr_matches_T_29; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_31 = block_addr_matches_7_0 & _dword_addr_matches_T_30; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_7_0 = _dword_addr_matches_T_31; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_428 = ldq_ld_byte_mask_7 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_14; // @[lsu.scala:1197:46] assign _mask_match_T_14 = _GEN_428; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_14; // @[lsu.scala:1198:46] assign _mask_overlap_T_14 = _GEN_428; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_15 = _mask_match_T_14 == ldq_ld_byte_mask_7; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_7_0 = _mask_match_T_15; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_15 = \|_mask_overlap_T_14; // @[lsu.scala:1198:{46,62}] wire mask_overlap_7_0 = _mask_overlap_T_15; // @[lsu.scala:321:49, :1198:62] wire _T_654 = ldq_executed_7 \| ldq_succeeded_7; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_630 = ldq_st_dep_mask_7 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_28 = ldq_forward_stq_idx_7 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_29 = ldq_forward_stq_idx_7 < l_uop_7_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_30 = _forwarded_is_older_T_28 ^ _forwarded_is_older_T_29; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_31 = lcam_stq_idx_0 < l_uop_7_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_7 = _forwarded_is_older_T_30 ^ _forwarded_is_older_T_31; // @[util.scala:364:{58,72,78}] wire _GEN_429 = do_st_search_0 & ldq_valid_7 & ldq_addr_7_valid & _T_654 & ~ldq_addr_is_virtual_7 & _T_630[0] & dword_addr_matches_7_0 & mask_overlap_7_0 & (~ldq_forward_std_val_7 \| ldq_forward_stq_idx_7 != lcam_stq_idx_0 & forwarded_is_older_7); // @[util.scala:364:72] wire _T_644 = do_ld_search_0 & ldq_valid_7 & ldq_addr_7_valid & ~ldq_addr_is_virtual_7 & dword_addr_matches_7_0 & mask_overlap_7_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_7 = lcam_younger_load_mask_0[7]; // @[lsu.scala:321:49, :1237:58] wire _T_663 = ldq_executed_7 & (ldq_succeeded_7 \| ldq_will_succeed_7); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_430 = searcher_is_older_7 \| _GEN_402; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_8; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_25 = ldq_addr_8_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_26 = _block_addr_matches_T_24 == _block_addr_matches_T_25; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_8_0 = _block_addr_matches_T_26; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_33 = ldq_addr_8_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_34 = _dword_addr_matches_T_32 == _dword_addr_matches_T_33; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_35 = block_addr_matches_8_0 & _dword_addr_matches_T_34; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_8_0 = _dword_addr_matches_T_35; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_431 = ldq_ld_byte_mask_8 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_16; // @[lsu.scala:1197:46] assign _mask_match_T_16 = _GEN_431; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_16; // @[lsu.scala:1198:46] assign _mask_overlap_T_16 = _GEN_431; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_17 = _mask_match_T_16 == ldq_ld_byte_mask_8; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_8_0 = _mask_match_T_17; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_17 = \|_mask_overlap_T_16; // @[lsu.scala:1198:{46,62}] wire mask_overlap_8_0 = _mask_overlap_T_17; // @[lsu.scala:321:49, :1198:62] wire _T_706 = ldq_executed_8 \| ldq_succeeded_8; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_682 = ldq_st_dep_mask_8 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_686 = do_st_search_0 & ldq_valid_8 & ldq_addr_8_valid & _T_706 & ~ldq_addr_is_virtual_8 & _T_682[0] & dword_addr_matches_8_0 & mask_overlap_8_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_32 = ldq_forward_stq_idx_8 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_33 = ldq_forward_stq_idx_8 < l_uop_8_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_34 = _forwarded_is_older_T_32 ^ _forwarded_is_older_T_33; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_35 = lcam_stq_idx_0 < l_uop_8_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_8 = _forwarded_is_older_T_34 ^ _forwarded_is_older_T_35; // @[util.scala:364:{58,72,78}] wire _T_690 = ~ldq_forward_std_val_8 \| ldq_forward_stq_idx_8 != lcam_stq_idx_0 & forwarded_is_older_8; // @[util.scala:364:72] wire _GEN_432 = _T_686 ? _T_690 \| _GEN_429 \| _GEN_426 : _GEN_429 \| _GEN_426; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_696 = do_ld_search_0 & ldq_valid_8 & ldq_addr_8_valid & ~ldq_addr_is_virtual_8 & dword_addr_matches_8_0 & mask_overlap_8_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_8 = lcam_younger_load_mask_0[8]; // @[lsu.scala:321:49, :1237:58] wire _T_715 = ldq_executed_8 & (ldq_succeeded_8 \| ldq_will_succeed_8); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_433 = searcher_is_older_8 \| _GEN_403; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_9; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_28 = ldq_addr_9_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_29 = _block_addr_matches_T_27 == _block_addr_matches_T_28; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_9_0 = _block_addr_matches_T_29; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_37 = ldq_addr_9_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_38 = _dword_addr_matches_T_36 == _dword_addr_matches_T_37; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_39 = block_addr_matches_9_0 & _dword_addr_matches_T_38; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_9_0 = _dword_addr_matches_T_39; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_434 = ldq_ld_byte_mask_9 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_18; // @[lsu.scala:1197:46] assign _mask_match_T_18 = _GEN_434; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_18; // @[lsu.scala:1198:46] assign _mask_overlap_T_18 = _GEN_434; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_19 = _mask_match_T_18 == ldq_ld_byte_mask_9; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_9_0 = _mask_match_T_19; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_19 = \|_mask_overlap_T_18; // @[lsu.scala:1198:{46,62}] wire mask_overlap_9_0 = _mask_overlap_T_19; // @[lsu.scala:321:49, :1198:62] wire _T_758 = ldq_executed_9 \| ldq_succeeded_9; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_734 = ldq_st_dep_mask_9 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_36 = ldq_forward_stq_idx_9 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_37 = ldq_forward_stq_idx_9 < l_uop_9_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_38 = _forwarded_is_older_T_36 ^ _forwarded_is_older_T_37; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_39 = lcam_stq_idx_0 < l_uop_9_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_9 = _forwarded_is_older_T_38 ^ _forwarded_is_older_T_39; // @[util.scala:364:{58,72,78}] wire _GEN_435 = do_st_search_0 & ldq_valid_9 & ldq_addr_9_valid & _T_758 & ~ldq_addr_is_virtual_9 & _T_734[0] & dword_addr_matches_9_0 & mask_overlap_9_0 & (~ldq_forward_std_val_9 \| ldq_forward_stq_idx_9 != lcam_stq_idx_0 & forwarded_is_older_9); // @[util.scala:364:72] wire _T_748 = do_ld_search_0 & ldq_valid_9 & ldq_addr_9_valid & ~ldq_addr_is_virtual_9 & dword_addr_matches_9_0 & mask_overlap_9_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_9 = lcam_younger_load_mask_0[9]; // @[lsu.scala:321:49, :1237:58] wire _T_767 = ldq_executed_9 & (ldq_succeeded_9 \| ldq_will_succeed_9); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_436 = searcher_is_older_9 \| _GEN_404; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_10; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_31 = ldq_addr_10_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_32 = _block_addr_matches_T_30 == _block_addr_matches_T_31; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_10_0 = _block_addr_matches_T_32; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_41 = ldq_addr_10_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_42 = _dword_addr_matches_T_40 == _dword_addr_matches_T_41; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_43 = block_addr_matches_10_0 & _dword_addr_matches_T_42; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_10_0 = _dword_addr_matches_T_43; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_437 = ldq_ld_byte_mask_10 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_20; // @[lsu.scala:1197:46] assign _mask_match_T_20 = _GEN_437; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_20; // @[lsu.scala:1198:46] assign _mask_overlap_T_20 = _GEN_437; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_21 = _mask_match_T_20 == ldq_ld_byte_mask_10; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_10_0 = _mask_match_T_21; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_21 = \|_mask_overlap_T_20; // @[lsu.scala:1198:{46,62}] wire mask_overlap_10_0 = _mask_overlap_T_21; // @[lsu.scala:321:49, :1198:62] wire _T_810 = ldq_executed_10 \| ldq_succeeded_10; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_786 = ldq_st_dep_mask_10 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_790 = do_st_search_0 & ldq_valid_10 & ldq_addr_10_valid & _T_810 & ~ldq_addr_is_virtual_10 & _T_786[0] & dword_addr_matches_10_0 & mask_overlap_10_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_40 = ldq_forward_stq_idx_10 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_41 = ldq_forward_stq_idx_10 < l_uop_10_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_42 = _forwarded_is_older_T_40 ^ _forwarded_is_older_T_41; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_43 = lcam_stq_idx_0 < l_uop_10_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_10 = _forwarded_is_older_T_42 ^ _forwarded_is_older_T_43; // @[util.scala:364:{58,72,78}] wire _T_794 = ~ldq_forward_std_val_10 \| ldq_forward_stq_idx_10 != lcam_stq_idx_0 & forwarded_is_older_10; // @[util.scala:364:72] wire _GEN_438 = _T_790 ? _T_794 \| _GEN_435 \| _GEN_432 : _GEN_435 \| _GEN_432; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_800 = do_ld_search_0 & ldq_valid_10 & ldq_addr_10_valid & ~ldq_addr_is_virtual_10 & dword_addr_matches_10_0 & mask_overlap_10_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_10 = lcam_younger_load_mask_0[10]; // @[lsu.scala:321:49, :1237:58] wire _T_819 = ldq_executed_10 & (ldq_succeeded_10 \| ldq_will_succeed_10); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_439 = searcher_is_older_10 \| _GEN_405; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_11; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_34 = ldq_addr_11_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_35 = _block_addr_matches_T_33 == _block_addr_matches_T_34; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_11_0 = _block_addr_matches_T_35; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_45 = ldq_addr_11_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_46 = _dword_addr_matches_T_44 == _dword_addr_matches_T_45; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_47 = block_addr_matches_11_0 & _dword_addr_matches_T_46; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_11_0 = _dword_addr_matches_T_47; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_440 = ldq_ld_byte_mask_11 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_22; // @[lsu.scala:1197:46] assign _mask_match_T_22 = _GEN_440; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_22; // @[lsu.scala:1198:46] assign _mask_overlap_T_22 = _GEN_440; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_23 = _mask_match_T_22 == ldq_ld_byte_mask_11; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_11_0 = _mask_match_T_23; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_23 = \|_mask_overlap_T_22; // @[lsu.scala:1198:{46,62}] wire mask_overlap_11_0 = _mask_overlap_T_23; // @[lsu.scala:321:49, :1198:62] wire _T_862 = ldq_executed_11 \| ldq_succeeded_11; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_838 = ldq_st_dep_mask_11 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_44 = ldq_forward_stq_idx_11 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_45 = ldq_forward_stq_idx_11 < l_uop_11_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_46 = _forwarded_is_older_T_44 ^ _forwarded_is_older_T_45; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_47 = lcam_stq_idx_0 < l_uop_11_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_11 = _forwarded_is_older_T_46 ^ _forwarded_is_older_T_47; // @[util.scala:364:{58,72,78}] wire _GEN_441 = do_st_search_0 & ldq_valid_11 & ldq_addr_11_valid & _T_862 & ~ldq_addr_is_virtual_11 & _T_838[0] & dword_addr_matches_11_0 & mask_overlap_11_0 & (~ldq_forward_std_val_11 \| ldq_forward_stq_idx_11 != lcam_stq_idx_0 & forwarded_is_older_11); // @[util.scala:364:72] wire _T_852 = do_ld_search_0 & ldq_valid_11 & ldq_addr_11_valid & ~ldq_addr_is_virtual_11 & dword_addr_matches_11_0 & mask_overlap_11_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_11 = lcam_younger_load_mask_0[11]; // @[lsu.scala:321:49, :1237:58] wire _T_871 = ldq_executed_11 & (ldq_succeeded_11 \| ldq_will_succeed_11); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_442 = searcher_is_older_11 \| _GEN_406; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_12; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_37 = ldq_addr_12_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_38 = _block_addr_matches_T_36 == _block_addr_matches_T_37; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_12_0 = _block_addr_matches_T_38; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_49 = ldq_addr_12_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_50 = _dword_addr_matches_T_48 == _dword_addr_matches_T_49; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_51 = block_addr_matches_12_0 & _dword_addr_matches_T_50; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_12_0 = _dword_addr_matches_T_51; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_443 = ldq_ld_byte_mask_12 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_24; // @[lsu.scala:1197:46] assign _mask_match_T_24 = _GEN_443; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_24; // @[lsu.scala:1198:46] assign _mask_overlap_T_24 = _GEN_443; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_25 = _mask_match_T_24 == ldq_ld_byte_mask_12; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_12_0 = _mask_match_T_25; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_25 = \|_mask_overlap_T_24; // @[lsu.scala:1198:{46,62}] wire mask_overlap_12_0 = _mask_overlap_T_25; // @[lsu.scala:321:49, :1198:62] wire _T_914 = ldq_executed_12 \| ldq_succeeded_12; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_890 = ldq_st_dep_mask_12 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_894 = do_st_search_0 & ldq_valid_12 & ldq_addr_12_valid & _T_914 & ~ldq_addr_is_virtual_12 & _T_890[0] & dword_addr_matches_12_0 & mask_overlap_12_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_48 = ldq_forward_stq_idx_12 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_49 = ldq_forward_stq_idx_12 < l_uop_12_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_50 = _forwarded_is_older_T_48 ^ _forwarded_is_older_T_49; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_51 = lcam_stq_idx_0 < l_uop_12_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_12 = _forwarded_is_older_T_50 ^ _forwarded_is_older_T_51; // @[util.scala:364:{58,72,78}] wire _T_898 = ~ldq_forward_std_val_12 \| ldq_forward_stq_idx_12 != lcam_stq_idx_0 & forwarded_is_older_12; // @[util.scala:364:72] wire _GEN_444 = _T_894 ? _T_898 \| _GEN_441 \| _GEN_438 : _GEN_441 \| _GEN_438; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_904 = do_ld_search_0 & ldq_valid_12 & ldq_addr_12_valid & ~ldq_addr_is_virtual_12 & dword_addr_matches_12_0 & mask_overlap_12_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_12 = lcam_younger_load_mask_0[12]; // @[lsu.scala:321:49, :1237:58] wire _T_923 = ldq_executed_12 & (ldq_succeeded_12 \| ldq_will_succeed_12); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_445 = searcher_is_older_12 \| _GEN_407; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_13; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_40 = ldq_addr_13_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_41 = _block_addr_matches_T_39 == _block_addr_matches_T_40; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_13_0 = _block_addr_matches_T_41; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_53 = ldq_addr_13_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_54 = _dword_addr_matches_T_52 == _dword_addr_matches_T_53; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_55 = block_addr_matches_13_0 & _dword_addr_matches_T_54; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_13_0 = _dword_addr_matches_T_55; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_446 = ldq_ld_byte_mask_13 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_26; // @[lsu.scala:1197:46] assign _mask_match_T_26 = _GEN_446; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_26; // @[lsu.scala:1198:46] assign _mask_overlap_T_26 = _GEN_446; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_27 = _mask_match_T_26 == ldq_ld_byte_mask_13; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_13_0 = _mask_match_T_27; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_27 = \|_mask_overlap_T_26; // @[lsu.scala:1198:{46,62}] wire mask_overlap_13_0 = _mask_overlap_T_27; // @[lsu.scala:321:49, :1198:62] wire _T_966 = ldq_executed_13 \| ldq_succeeded_13; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_942 = ldq_st_dep_mask_13 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_52 = ldq_forward_stq_idx_13 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_53 = ldq_forward_stq_idx_13 < l_uop_13_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_54 = _forwarded_is_older_T_52 ^ _forwarded_is_older_T_53; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_55 = lcam_stq_idx_0 < l_uop_13_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_13 = _forwarded_is_older_T_54 ^ _forwarded_is_older_T_55; // @[util.scala:364:{58,72,78}] wire _GEN_447 = do_st_search_0 & ldq_valid_13 & ldq_addr_13_valid & _T_966 & ~ldq_addr_is_virtual_13 & _T_942[0] & dword_addr_matches_13_0 & mask_overlap_13_0 & (~ldq_forward_std_val_13 \| ldq_forward_stq_idx_13 != lcam_stq_idx_0 & forwarded_is_older_13); // @[util.scala:364:72] wire _T_956 = do_ld_search_0 & ldq_valid_13 & ldq_addr_13_valid & ~ldq_addr_is_virtual_13 & dword_addr_matches_13_0 & mask_overlap_13_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_13 = lcam_younger_load_mask_0[13]; // @[lsu.scala:321:49, :1237:58] wire _T_975 = ldq_executed_13 & (ldq_succeeded_13 \| ldq_will_succeed_13); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_448 = searcher_is_older_13 \| _GEN_408; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_14; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_43 = ldq_addr_14_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_44 = _block_addr_matches_T_42 == _block_addr_matches_T_43; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_14_0 = _block_addr_matches_T_44; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_57 = ldq_addr_14_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_58 = _dword_addr_matches_T_56 == _dword_addr_matches_T_57; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_59 = block_addr_matches_14_0 & _dword_addr_matches_T_58; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_14_0 = _dword_addr_matches_T_59; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_449 = ldq_ld_byte_mask_14 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_28; // @[lsu.scala:1197:46] assign _mask_match_T_28 = _GEN_449; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_28; // @[lsu.scala:1198:46] assign _mask_overlap_T_28 = _GEN_449; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_29 = _mask_match_T_28 == ldq_ld_byte_mask_14; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_14_0 = _mask_match_T_29; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_29 = \|_mask_overlap_T_28; // @[lsu.scala:1198:{46,62}] wire mask_overlap_14_0 = _mask_overlap_T_29; // @[lsu.scala:321:49, :1198:62] wire _T_1018 = ldq_executed_14 \| ldq_succeeded_14; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_994 = ldq_st_dep_mask_14 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_998 = do_st_search_0 & ldq_valid_14 & ldq_addr_14_valid & _T_1018 & ~ldq_addr_is_virtual_14 & _T_994[0] & dword_addr_matches_14_0 & mask_overlap_14_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_56 = ldq_forward_stq_idx_14 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_57 = ldq_forward_stq_idx_14 < l_uop_14_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_58 = _forwarded_is_older_T_56 ^ _forwarded_is_older_T_57; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_59 = lcam_stq_idx_0 < l_uop_14_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_14 = _forwarded_is_older_T_58 ^ _forwarded_is_older_T_59; // @[util.scala:364:{58,72,78}] wire _T_1002 = ~ldq_forward_std_val_14 \| ldq_forward_stq_idx_14 != lcam_stq_idx_0 & forwarded_is_older_14; // @[util.scala:364:72] wire _T_1008 = do_ld_search_0 & ldq_valid_14 & ldq_addr_14_valid & ~ldq_addr_is_virtual_14 & dword_addr_matches_14_0 & mask_overlap_14_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_14 = lcam_younger_load_mask_0[14]; // @[lsu.scala:321:49, :1237:58] wire _T_1027 = ldq_executed_14 & (ldq_succeeded_14 \| ldq_will_succeed_14); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_450 = searcher_is_older_14 \| _GEN_409; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] wire _GEN_451 = (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & (&lcam_ldq_idx_0))) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & (&lcam_ldq_idx_0))) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & (&lcam_ldq_idx_0))) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & (&lcam_ldq_idx_0))) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & (&lcam_ldq_idx_0))) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & (&lcam_ldq_idx_0))) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & (&lcam_ldq_idx_0))) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & (&lcam_ldq_idx_0))) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & (&lcam_ldq_idx_0))) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & (&lcam_ldq_idx_0))) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & (&lcam_ldq_idx_0))) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & (&lcam_ldq_idx_0))) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & (&lcam_ldq_idx_0))) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & (&lcam_ldq_idx_0))) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & (&lcam_ldq_idx_0))) & s1_executing_loads_15; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] reg REG_15; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_46 = ldq_addr_15_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_47 = _block_addr_matches_T_45 == _block_addr_matches_T_46; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_15_0 = _block_addr_matches_T_47; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_61 = ldq_addr_15_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_62 = _dword_addr_matches_T_60 == _dword_addr_matches_T_61; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_63 = block_addr_matches_15_0 & _dword_addr_matches_T_62; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_15_0 = _dword_addr_matches_T_63; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_452 = ldq_ld_byte_mask_15 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_30; // @[lsu.scala:1197:46] assign _mask_match_T_30 = _GEN_452; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_30; // @[lsu.scala:1198:46] assign _mask_overlap_T_30 = _GEN_452; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_31 = _mask_match_T_30 == ldq_ld_byte_mask_15; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_15_0 = _mask_match_T_31; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_31 = \|_mask_overlap_T_30; // @[lsu.scala:1198:{46,62}] wire mask_overlap_15_0 = _mask_overlap_T_31; // @[lsu.scala:321:49, :1198:62] wire _T_1070 = ldq_executed_15 \| ldq_succeeded_15; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_1046 = ldq_st_dep_mask_15 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_60 = ldq_forward_stq_idx_15 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_61 = ldq_forward_stq_idx_15 < l_uop_15_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_62 = _forwarded_is_older_T_60 ^ _forwarded_is_older_T_61; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_63 = lcam_stq_idx_0 < l_uop_15_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_15 = _forwarded_is_older_T_62 ^ _forwarded_is_older_T_63; // @[util.scala:364:{58,72,78}] wire _GEN_453 = do_st_search_0 & ldq_valid_15 & ldq_addr_15_valid & _T_1070 & ~ldq_addr_is_virtual_15 & _T_1046[0] & dword_addr_matches_15_0 & mask_overlap_15_0 & (~ldq_forward_std_val_15 \| ldq_forward_stq_idx_15 != lcam_stq_idx_0 & forwarded_is_older_15); // @[util.scala:364:72] wire _T_1060 = do_ld_search_0 & ldq_valid_15 & ldq_addr_15_valid & ~ldq_addr_is_virtual_15 & dword_addr_matches_15_0 & mask_overlap_15_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_15 = lcam_younger_load_mask_0[15]; // @[lsu.scala:321:49, :1237:58] wire _T_1079 = ldq_executed_15 & (ldq_succeeded_15 \| ldq_will_succeed_15); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_454 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_395)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_395)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_395)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_395)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_395)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_395)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_395)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_395)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_395)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_395)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_395)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_395)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_395)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_395)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_395)) & s1_executing_loads_0; // @[lsu.scala:321:49, :1168:35, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_455 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_396)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_396)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_396)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_396)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_396)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_396)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_396)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_396)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_396)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_396)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_396)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_396)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_396)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_396)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_396)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_396)) & s1_executing_loads_1; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_456 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_397)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_397)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_397)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_397)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_397)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_397)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_397)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_397)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_397)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_397)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_397)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_397)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_397)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_397)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_397)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_397)) & s1_executing_loads_2; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_457 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_398)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_398)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_398)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_398)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_398)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_398)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_398)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_398)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_398)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_398)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_398)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_398)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_398)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_398)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_398)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_398)) & s1_executing_loads_3; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_458 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_399)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_399)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_399)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_399)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_399)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_399)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_399)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_399)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_399)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_399)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_399)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_399)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_399)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_399)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_399)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_399)) & s1_executing_loads_4; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_459 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_400)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_400)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_400)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_400)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_400)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_400)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_400)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_400)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_400)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_400)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_400)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_400)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_400)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_400)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_400)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_400)) & s1_executing_loads_5; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_460 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_401)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_401)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_401)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_401)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_401)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_401)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_401)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_401)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_401)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_401)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_401)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_401)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_401)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_401)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_401)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_401)) & s1_executing_loads_6; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_461 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_402)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_402)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_402)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_402)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_402)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_402)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_402)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_402)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_402)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_402)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_402)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_402)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_402)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_402)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_402)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_402)) & s1_executing_loads_7; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_462 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_403)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_403)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_403)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_403)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_403)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_403)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_403)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_403)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_403)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_403)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_403)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_403)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_403)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_403)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_403)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_403)) & s1_executing_loads_8; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_463 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_404)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_404)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_404)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_404)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_404)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_404)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_404)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_404)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_404)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_404)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_404)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_404)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_404)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_404)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_404)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_404)) & s1_executing_loads_9; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_464 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_405)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_405)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_405)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_405)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_405)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_405)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_405)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_405)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_405)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_405)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_405)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_405)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_405)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_405)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_405)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_405)) & s1_executing_loads_10; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_465 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_406)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_406)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_406)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_406)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_406)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_406)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_406)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_406)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_406)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_406)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_406)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_406)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_406)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_406)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_406)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_406)) & s1_executing_loads_11; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_466 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_407)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_407)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_407)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_407)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_407)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_407)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_407)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_407)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_407)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_407)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_407)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_407)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_407)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_407)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_407)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_407)) & s1_executing_loads_12; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_467 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_408)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_408)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_408)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_408)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_408)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_408)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_408)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_408)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_408)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_408)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_408)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_408)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_408)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_408)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_408)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_408)) & s1_executing_loads_13; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_468 = (~_T_1060 \| searcher_is_older_15 \| ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_409)) & (~_T_1008 \| _GEN_450 \| ~(~_T_1027 & _GEN_409)) & (~_T_956 \| _GEN_448 \| ~(~_T_975 & _GEN_409)) & (~_T_904 \| _GEN_445 \| ~(~_T_923 & _GEN_409)) & (~_T_852 \| _GEN_442 \| ~(~_T_871 & _GEN_409)) & (~_T_800 \| _GEN_439 \| ~(~_T_819 & _GEN_409)) & (~_T_748 \| _GEN_436 \| ~(~_T_767 & _GEN_409)) & (~_T_696 \| _GEN_433 \| ~(~_T_715 & _GEN_409)) & (~_T_644 \| _GEN_430 \| ~(~_T_663 & _GEN_409)) & (~_T_592 \| _GEN_427 \| ~(~_T_611 & _GEN_409)) & (~_T_540 \| _GEN_424 \| ~(~_T_559 & _GEN_409)) & (~_T_488 \| _GEN_421 \| ~(~_T_507 & _GEN_409)) & (~_T_436 \| _GEN_418 \| ~(~_T_455 & _GEN_409)) & (~_T_384 \| _GEN_415 \| ~(~_T_403 & _GEN_409)) & (~_T_332 \| _GEN_412 \| ~(~_T_351 & _GEN_409)) & (~_T_280 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_299 & _GEN_409)) & s1_executing_loads_14; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] reg REG_16; // @[lsu.scala:1255:26] wire _GEN_469 = _T_1060 & ~searcher_is_older_15 & ~(&lcam_ldq_idx_0) & ~_T_1079 & REG_16 & ~fired_load_agen_0 \| _T_1008 & ~_GEN_450 & ~_T_1027 & REG_15 & ~fired_load_agen_0 \| _T_956 & ~_GEN_448 & ~_T_975 & REG_14 & ~fired_load_agen_0 \| _T_904 & ~_GEN_445 & ~_T_923 & REG_13 & ~fired_load_agen_0 \| _T_852 & ~_GEN_442 & ~_T_871 & REG_12 & ~fired_load_agen_0 \| _T_800 & ~_GEN_439 & ~_T_819 & REG_11 & ~fired_load_agen_0 \| _T_748 & ~_GEN_436 & ~_T_767 & REG_10 & ~fired_load_agen_0 \| _T_696 & ~_GEN_433 & ~_T_715 & REG_9 & ~fired_load_agen_0 \| _T_644 & ~_GEN_430 & ~_T_663 & REG_8 & ~fired_load_agen_0 \| _T_592 & ~_GEN_427 & ~_T_611 & REG_7 & ~fired_load_agen_0 \| _T_540 & ~_GEN_424 & ~_T_559 & REG_6 & ~fired_load_agen_0 \| _T_488 & ~_GEN_421 & ~_T_507 & REG_5 & ~fired_load_agen_0 \| _T_436 & ~_GEN_418 & ~_T_455 & REG_4 & ~fired_load_agen_0 \| _T_384 & ~_GEN_415 & ~_T_403 & REG_3 & ~fired_load_agen_0 \| _T_332 & ~_GEN_412 & ~_T_351 & REG_2 & ~fired_load_agen_0 \| _T_280 & ~searcher_is_older & (\|lcam_ldq_idx_0) & ~_T_299 & REG_1 & ~fired_load_agen_0 \| io_dmem_s1_kill_0_REG; // @[lsu.scala:321:49, :893:{24,34}, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48, :1255:{26,61,64,85}, :1256:48] wire _GEN_470 = _T_1060 & ~searcher_is_older_15 & ~(&lcam_ldq_idx_0) & ~_T_1079 \| _T_1008 & ~_GEN_450 & ~_T_1027 \| _T_956 & ~_GEN_448 & ~_T_975 \| _T_904 & ~_GEN_445 & ~_T_923 \| _T_852 & ~_GEN_442 & ~_T_871 \| _T_800 & ~_GEN_439 & ~_T_819 \| _T_748 & ~_GEN_436 & ~_T_767 \| _T_696 & ~_GEN_433 & ~_T_715 \| _T_644 & ~_GEN_430 & ~_T_663 \| _T_592 & ~_GEN_427 & ~_T_611 \| _T_540 & ~_GEN_424 & ~_T_559 \| _T_488 & ~_GEN_421 & ~_T_507 \| _T_436 & ~_GEN_418 & ~_T_455 \| _T_384 & ~_GEN_415 & ~_T_403 \| _T_332 & ~_GEN_412 & ~_T_351 \| _T_280 & ~searcher_is_older & (\|lcam_ldq_idx_0) & ~_T_299; // @[lsu.scala:321:49, :893:24, :1159:30, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48, :1258:48] wire [36:0] _nack_dword_addr_matches_T = lcam_addr_0[39:3]; // @[lsu.scala:321:49, :1270:51] wire [36:0] _forward_dword_addr_matches_T = lcam_addr_0[39:3]; // @[lsu.scala:321:49, :1270:51, :1289:54] wire [36:0] _nack_dword_addr_matches_T_1 = io_dmem_nack_0_bits_addr_0[39:3]; // @[lsu.scala:211:7, :1270:89] wire nack_dword_addr_matches = _nack_dword_addr_matches_T == _nack_dword_addr_matches_T_1; // @[lsu.scala:1270:{51,57,89}] wire [7:0] nack_mask; // @[lsu.scala:1951:22] wire _nack_mask_mask_T = io_dmem_nack_0_bits_uop_mem_size_0 == 2'h0; // @[lsu.scala:211:7, :1953:26] wire [2:0] _nack_mask_mask_T_1 = io_dmem_nack_0_bits_addr_0[2:0]; // @[lsu.scala:211:7, :1953:55] wire [14:0] _nack_mask_mask_T_2 = 15'h1 << _nack_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _nack_mask_mask_T_3 = io_dmem_nack_0_bits_uop_mem_size_0 == 2'h1; // @[lsu.scala:211:7, :1954:26] wire [1:0] _nack_mask_mask_T_4 = io_dmem_nack_0_bits_addr_0[2:1]; // @[lsu.scala:211:7, :1954:56] wire [2:0] _nack_mask_mask_T_5 = {_nack_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _nack_mask_mask_T_6 = 15'h3 << _nack_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _nack_mask_mask_T_7 = io_dmem_nack_0_bits_uop_mem_size_0 == 2'h2; // @[lsu.scala:211:7, :1955:26] wire _nack_mask_mask_T_8 = io_dmem_nack_0_bits_addr_0[2]; // @[lsu.scala:211:7, :1955:46] wire [7:0] _nack_mask_mask_T_9 = _nack_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _nack_mask_mask_T_10 = &io_dmem_nack_0_bits_uop_mem_size_0; // @[lsu.scala:211:7, :1956:26] wire [7:0] _nack_mask_mask_T_12 = _nack_mask_mask_T_7 ? _nack_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _nack_mask_mask_T_13 = _nack_mask_mask_T_3 ? _nack_mask_mask_T_6 : {7'h0, _nack_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _nack_mask_mask_T_14 = _nack_mask_mask_T ? _nack_mask_mask_T_2 : _nack_mask_mask_T_13; // @[Mux.scala:126:16] assign nack_mask = _nack_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire [7:0] _nack_mask_overlap_T = nack_mask & lcam_mask_0; // @[lsu.scala:321:49, :1272:42, :1951:22] wire nack_mask_overlap = \|_nack_mask_overlap_T; // @[lsu.scala:1272:{42,58}] wire _T_1096 = do_ld_search_0 & io_dmem_nack_0_valid_0 & io_dmem_nack_0_bits_uop_uses_ldq_0 & nack_dword_addr_matches & nack_mask_overlap & (io_dmem_nack_0_bits_uop_ldq_idx_0 < lcam_ldq_idx_0 ^ io_dmem_nack_0_bits_uop_ldq_idx_0 < ldq_head ^ _lcam_younger_load_mask_T); // @[util.scala:364:{52,58,64,72}, :372:11] wire _GEN_471 = _T_1096 & _GEN_395; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_472 = _T_1096 & _GEN_396; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_473 = _T_1096 & _GEN_397; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_474 = _T_1096 & _GEN_398; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_475 = _T_1096 & _GEN_399; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_476 = _T_1096 & _GEN_400; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_477 = _T_1096 & _GEN_401; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_478 = _T_1096 & _GEN_402; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_479 = _T_1096 & _GEN_403; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_480 = _T_1096 & _GEN_404; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_481 = _T_1096 & _GEN_405; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_482 = _T_1096 & _GEN_406; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_483 = _T_1096 & _GEN_407; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_484 = _T_1096 & _GEN_408; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_485 = _T_1096 & _GEN_409; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_486 = _T_1096 & (&lcam_ldq_idx_0); // @[lsu.scala:321:49, :1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] reg REG_17; // @[lsu.scala:1280:22] wire _GEN_487 = _T_1096 & REG_17 & ~fired_load_agen_0; // @[lsu.scala:321:49, :1235:37, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1280:{22,57,60,81}, :1281:30] wire [36:0] _forward_dword_addr_matches_T_1 = wb_ldst_forward_ld_addr_0[39:3]; // @[lsu.scala:1175:41, :1289:91] wire forward_dword_addr_matches = _forward_dword_addr_matches_T == _forward_dword_addr_matches_T_1; // @[lsu.scala:1289:{54,59,91}] wire [7:0] forward_mask; // @[lsu.scala:1951:22] wire _forward_mask_mask_T = wb_ldst_forward_e_0_uop_mem_size == 2'h0; // @[lsu.scala:321:49, :1953:26] wire [2:0] _forward_mask_mask_T_1 = wb_ldst_forward_ld_addr_0[2:0]; // @[lsu.scala:1175:41, :1953:55] wire [14:0] _forward_mask_mask_T_2 = 15'h1 << _forward_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _forward_mask_mask_T_3 = wb_ldst_forward_e_0_uop_mem_size == 2'h1; // @[lsu.scala:321:49, :1954:26] wire [1:0] _forward_mask_mask_T_4 = wb_ldst_forward_ld_addr_0[2:1]; // @[lsu.scala:1175:41, :1954:56] wire [2:0] _forward_mask_mask_T_5 = {_forward_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _forward_mask_mask_T_6 = 15'h3 << _forward_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _forward_mask_mask_T_7 = wb_ldst_forward_e_0_uop_mem_size == 2'h2; // @[lsu.scala:321:49, :1955:26] wire _forward_mask_mask_T_8 = wb_ldst_forward_ld_addr_0[2]; // @[lsu.scala:1175:41, :1955:46] wire _iresp_0_bits_data_shifted_T = wb_ldst_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _fresp_0_bits_data_shifted_T = wb_ldst_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _ldq_debug_wb_data_shifted_T = wb_ldst_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire [7:0] _forward_mask_mask_T_9 = _forward_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _forward_mask_mask_T_10 = &wb_ldst_forward_e_0_uop_mem_size; // @[lsu.scala:321:49, :1956:26] wire [7:0] _forward_mask_mask_T_12 = _forward_mask_mask_T_7 ? _forward_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _forward_mask_mask_T_13 = _forward_mask_mask_T_3 ? _forward_mask_mask_T_6 : {7'h0, _forward_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _forward_mask_mask_T_14 = _forward_mask_mask_T ? _forward_mask_mask_T_2 : _forward_mask_mask_T_13; // @[Mux.scala:126:16] assign forward_mask = _forward_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire [7:0] _forward_mask_overlap_T = forward_mask & lcam_mask_0; // @[lsu.scala:321:49, :1291:48, :1951:22] wire forward_mask_overlap = \|_forward_mask_overlap_T; // @[lsu.scala:1291:{48,64}] wire _T_1112 = do_ld_search_0 & wb_ldst_forward_valid_0 & forward_dword_addr_matches & forward_mask_overlap & wb_ldst_forward_e_0_observed & (lcam_ldq_idx_0 < wb_ldst_forward_ldq_idx_0 ^ _lcam_younger_load_mask_T ^ wb_ldst_forward_ldq_idx_0 < ldq_head); // @[util.scala:364:{52,58,72,78}, :372:11] wire _GEN_488 = wb_ldst_forward_ldq_idx_0 == 4'h0; // @[lsu.scala:1174:41, :1298:53] wire _GEN_489 = wb_ldst_forward_ldq_idx_0 == 4'h1; // @[lsu.scala:1174:41, :1298:53] wire _GEN_490 = wb_ldst_forward_ldq_idx_0 == 4'h2; // @[lsu.scala:1174:41, :1298:53] wire _GEN_491 = wb_ldst_forward_ldq_idx_0 == 4'h3; // @[lsu.scala:1174:41, :1298:53] wire _GEN_492 = wb_ldst_forward_ldq_idx_0 == 4'h4; // @[lsu.scala:1174:41, :1298:53] wire _GEN_493 = wb_ldst_forward_ldq_idx_0 == 4'h5; // @[lsu.scala:1174:41, :1298:53] wire _GEN_494 = wb_ldst_forward_ldq_idx_0 == 4'h6; // @[lsu.scala:1174:41, :1298:53] wire _GEN_495 = wb_ldst_forward_ldq_idx_0 == 4'h7; // @[lsu.scala:1174:41, :1298:53] wire _GEN_496 = wb_ldst_forward_ldq_idx_0 == 4'h8; // @[lsu.scala:1174:41, :1298:53] wire _GEN_497 = wb_ldst_forward_ldq_idx_0 == 4'h9; // @[lsu.scala:1174:41, :1298:53] wire _GEN_498 = wb_ldst_forward_ldq_idx_0 == 4'hA; // @[lsu.scala:1174:41, :1298:53] wire _GEN_499 = wb_ldst_forward_ldq_idx_0 == 4'hB; // @[lsu.scala:1174:41, :1298:53] wire _GEN_500 = wb_ldst_forward_ldq_idx_0 == 4'hC; // @[lsu.scala:1174:41, :1298:53] wire _GEN_501 = wb_ldst_forward_ldq_idx_0 == 4'hD; // @[lsu.scala:1174:41, :1298:53] wire _GEN_502 = wb_ldst_forward_ldq_idx_0 == 4'hE; // @[lsu.scala:1174:41, :1298:53] wire _forwarded_is_older_T_64 = wb_ldst_forward_stq_idx_0 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_65 = wb_ldst_forward_stq_idx_0 < wb_ldst_forward_e_0_uop_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_66 = _forwarded_is_older_T_64 ^ _forwarded_is_older_T_65; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_67 = lcam_stq_idx_0 < wb_ldst_forward_e_0_uop_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_16 = _forwarded_is_older_T_66 ^ _forwarded_is_older_T_67; // @[util.scala:364:{58,72,78}] wire [15:0] _T_1118 = wb_ldst_forward_e_0_st_dep_mask >> _GEN_393; // @[lsu.scala:321:49, :1218:33, :1308:46] wire _T_1121 = do_st_search_0 & wb_ldst_forward_valid_0 & forward_dword_addr_matches & forward_mask_overlap & _T_1118[0] & forwarded_is_older_16; // @[util.scala:364:72] assign failed_load = _T_1121 \| _T_1112 \| _GEN_453 \| (_T_998 ? _T_1002 \| _GEN_447 \| _GEN_444 : _GEN_447 \| _GEN_444); // @[lsu.scala:394:59, :1178:29, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23, :1292:47, :1293:47, :1294:47, :1295:47, :1296:47, :1297:78, :1299:21, :1304:64, :1305:64, :1306:64, :1307:64, :1308:64, :1309:33, :1311:21] wire _addr_matches_0_0_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_1_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_2_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_3_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_4_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_5_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_6_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_7_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_8_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_9_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_10_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_11_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_12_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_13_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_14_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_15_T_1; // @[lsu.scala:1334:53] wire addr_matches_0_0; // @[lsu.scala:1316:29] wire addr_matches_0_1; // @[lsu.scala:1316:29] wire addr_matches_0_2; // @[lsu.scala:1316:29] wire addr_matches_0_3; // @[lsu.scala:1316:29] wire addr_matches_0_4; // @[lsu.scala:1316:29] wire addr_matches_0_5; // @[lsu.scala:1316:29] wire addr_matches_0_6; // @[lsu.scala:1316:29] wire addr_matches_0_7; // @[lsu.scala:1316:29] wire addr_matches_0_8; // @[lsu.scala:1316:29] wire addr_matches_0_9; // @[lsu.scala:1316:29] wire addr_matches_0_10; // @[lsu.scala:1316:29] wire addr_matches_0_11; // @[lsu.scala:1316:29] wire addr_matches_0_12; // @[lsu.scala:1316:29] wire addr_matches_0_13; // @[lsu.scala:1316:29] wire addr_matches_0_14; // @[lsu.scala:1316:29] wire addr_matches_0_15; // @[lsu.scala:1316:29] wire _forward_matches_0_0_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_1_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_2_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_3_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_4_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_5_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_6_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_7_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_8_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_9_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_10_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_11_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_12_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_13_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_14_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_15_T_2; // @[lsu.scala:1335:67] wire forward_matches_0_0; // @[lsu.scala:1317:29] wire forward_matches_0_1; // @[lsu.scala:1317:29] wire forward_matches_0_2; // @[lsu.scala:1317:29] wire forward_matches_0_3; // @[lsu.scala:1317:29] wire forward_matches_0_4; // @[lsu.scala:1317:29] wire forward_matches_0_5; // @[lsu.scala:1317:29] wire forward_matches_0_6; // @[lsu.scala:1317:29] wire forward_matches_0_7; // @[lsu.scala:1317:29] wire forward_matches_0_8; // @[lsu.scala:1317:29] wire forward_matches_0_9; // @[lsu.scala:1317:29] wire forward_matches_0_10; // @[lsu.scala:1317:29] wire forward_matches_0_11; // @[lsu.scala:1317:29] wire forward_matches_0_12; // @[lsu.scala:1317:29] wire forward_matches_0_13; // @[lsu.scala:1317:29] wire forward_matches_0_14; // @[lsu.scala:1317:29] wire forward_matches_0_15; // @[lsu.scala:1317:29] wire _prs2_matches_0_0_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_1_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_2_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_3_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_4_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_5_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_6_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_7_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_8_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_9_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_10_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_11_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_12_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_13_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_14_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_15_T_3; // @[lsu.scala:1338:58] wire prs2_matches_0_0; // @[lsu.scala:1318:29] wire prs2_matches_0_1; // @[lsu.scala:1318:29] wire prs2_matches_0_2; // @[lsu.scala:1318:29] wire prs2_matches_0_3; // @[lsu.scala:1318:29] wire prs2_matches_0_4; // @[lsu.scala:1318:29] wire prs2_matches_0_5; // @[lsu.scala:1318:29] wire prs2_matches_0_6; // @[lsu.scala:1318:29] wire prs2_matches_0_7; // @[lsu.scala:1318:29] wire prs2_matches_0_8; // @[lsu.scala:1318:29] wire prs2_matches_0_9; // @[lsu.scala:1318:29] wire prs2_matches_0_10; // @[lsu.scala:1318:29] wire prs2_matches_0_11; // @[lsu.scala:1318:29] wire prs2_matches_0_12; // @[lsu.scala:1318:29] wire prs2_matches_0_13; // @[lsu.scala:1318:29] wire prs2_matches_0_14; // @[lsu.scala:1318:29] wire prs2_matches_0_15; // @[lsu.scala:1318:29] wire [7:0] write_mask; // @[lsu.scala:1951:22] wire _write_mask_mask_T = s_uop_2_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_1 = stq_addr_0_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_2 = 15'h1 << _write_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_3 = s_uop_2_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_4 = stq_addr_0_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_5 = {_write_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_6 = 15'h3 << _write_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_7 = s_uop_2_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_8 = stq_addr_0_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_9 = _write_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_10 = &s_uop_2_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_12 = _write_mask_mask_T_7 ? _write_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_13 = _write_mask_mask_T_3 ? _write_mask_mask_T_6 : {7'h0, _write_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_14 = _write_mask_mask_T ? _write_mask_mask_T_2 : _write_mask_mask_T_13; // @[Mux.scala:126:16] assign write_mask = _write_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_64 = ~s_uop_2_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_65 = stq_addr_0_valid & _dword_addr_matches_T_64; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_66 = ~stq_addr_is_virtual_0; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_67 = _dword_addr_matches_T_65 & _dword_addr_matches_T_66; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_68 = stq_addr_0_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire [28:0] _dword_addr_matches_T_69 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_76 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_83 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_90 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_97 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_104 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_111 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_118 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_125 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_132 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_139 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_146 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_153 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_160 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_167 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_174 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire _dword_addr_matches_T_70 = _dword_addr_matches_T_68 == _dword_addr_matches_T_69; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_16 = _dword_addr_matches_T_67 & _dword_addr_matches_T_70; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union = lcam_mask_0 & write_mask; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_0_T = \|mask_union; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_0_T_1 = _addr_matches_0_0_T & dword_addr_matches_16; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_0 = _addr_matches_0_0_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_0_T = addr_matches_0_0 & stq_data_0_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_0_T_1 = mask_union == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_0_T_2 = _forward_matches_0_0_T & _forward_matches_0_0_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_0 = _forward_matches_0_0_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_0_T = s_uop_2_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_0_T_1 = s_uop_2_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_0_T_2 = _prs2_matches_0_0_T & _prs2_matches_0_0_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_0_T_3 = _prs2_matches_0_0_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_0 = _prs2_matches_0_0_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_1; // @[lsu.scala:1951:22] wire _write_mask_mask_T_15 = s_uop_3_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_16 = stq_addr_1_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_17 = 15'h1 << _write_mask_mask_T_16; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_18 = s_uop_3_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_19 = stq_addr_1_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_20 = {_write_mask_mask_T_19, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_21 = 15'h3 << _write_mask_mask_T_20; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_22 = s_uop_3_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_23 = stq_addr_1_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_24 = _write_mask_mask_T_23 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_25 = &s_uop_3_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_27 = _write_mask_mask_T_22 ? _write_mask_mask_T_24 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_28 = _write_mask_mask_T_18 ? _write_mask_mask_T_21 : {7'h0, _write_mask_mask_T_27}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_29 = _write_mask_mask_T_15 ? _write_mask_mask_T_17 : _write_mask_mask_T_28; // @[Mux.scala:126:16] assign write_mask_1 = _write_mask_mask_T_29[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_71 = ~s_uop_3_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_72 = stq_addr_1_valid & _dword_addr_matches_T_71; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_73 = ~stq_addr_is_virtual_1; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_74 = _dword_addr_matches_T_72 & _dword_addr_matches_T_73; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_75 = stq_addr_1_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_77 = _dword_addr_matches_T_75 == _dword_addr_matches_T_76; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_17 = _dword_addr_matches_T_74 & _dword_addr_matches_T_77; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_1 = lcam_mask_0 & write_mask_1; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_1_T = \|mask_union_1; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_1_T_1 = _addr_matches_0_1_T & dword_addr_matches_17; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_1 = _addr_matches_0_1_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_1_T = addr_matches_0_1 & stq_data_1_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_1_T_1 = mask_union_1 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_1_T_2 = _forward_matches_0_1_T & _forward_matches_0_1_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_1 = _forward_matches_0_1_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_1_T = s_uop_3_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_1_T_1 = s_uop_3_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_1_T_2 = _prs2_matches_0_1_T & _prs2_matches_0_1_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_1_T_3 = _prs2_matches_0_1_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_1 = _prs2_matches_0_1_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_2; // @[lsu.scala:1951:22] wire _write_mask_mask_T_30 = s_uop_4_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_31 = stq_addr_2_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_32 = 15'h1 << _write_mask_mask_T_31; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_33 = s_uop_4_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_34 = stq_addr_2_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_35 = {_write_mask_mask_T_34, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_36 = 15'h3 << _write_mask_mask_T_35; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_37 = s_uop_4_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_38 = stq_addr_2_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_39 = _write_mask_mask_T_38 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_40 = &s_uop_4_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_42 = _write_mask_mask_T_37 ? _write_mask_mask_T_39 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_43 = _write_mask_mask_T_33 ? _write_mask_mask_T_36 : {7'h0, _write_mask_mask_T_42}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_44 = _write_mask_mask_T_30 ? _write_mask_mask_T_32 : _write_mask_mask_T_43; // @[Mux.scala:126:16] assign write_mask_2 = _write_mask_mask_T_44[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_78 = ~s_uop_4_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_79 = stq_addr_2_valid & _dword_addr_matches_T_78; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_80 = ~stq_addr_is_virtual_2; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_81 = _dword_addr_matches_T_79 & _dword_addr_matches_T_80; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_82 = stq_addr_2_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_84 = _dword_addr_matches_T_82 == _dword_addr_matches_T_83; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_18 = _dword_addr_matches_T_81 & _dword_addr_matches_T_84; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_2 = lcam_mask_0 & write_mask_2; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_2_T = \|mask_union_2; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_2_T_1 = _addr_matches_0_2_T & dword_addr_matches_18; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_2 = _addr_matches_0_2_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_2_T = addr_matches_0_2 & stq_data_2_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_2_T_1 = mask_union_2 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_2_T_2 = _forward_matches_0_2_T & _forward_matches_0_2_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_2 = _forward_matches_0_2_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_2_T = s_uop_4_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_2_T_1 = s_uop_4_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_2_T_2 = _prs2_matches_0_2_T & _prs2_matches_0_2_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_2_T_3 = _prs2_matches_0_2_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_2 = _prs2_matches_0_2_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_3; // @[lsu.scala:1951:22] wire _write_mask_mask_T_45 = s_uop_5_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_46 = stq_addr_3_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_47 = 15'h1 << _write_mask_mask_T_46; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_48 = s_uop_5_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_49 = stq_addr_3_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_50 = {_write_mask_mask_T_49, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_51 = 15'h3 << _write_mask_mask_T_50; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_52 = s_uop_5_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_53 = stq_addr_3_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_54 = _write_mask_mask_T_53 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_55 = &s_uop_5_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_57 = _write_mask_mask_T_52 ? _write_mask_mask_T_54 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_58 = _write_mask_mask_T_48 ? _write_mask_mask_T_51 : {7'h0, _write_mask_mask_T_57}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_59 = _write_mask_mask_T_45 ? _write_mask_mask_T_47 : _write_mask_mask_T_58; // @[Mux.scala:126:16] assign write_mask_3 = _write_mask_mask_T_59[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_85 = ~s_uop_5_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_86 = stq_addr_3_valid & _dword_addr_matches_T_85; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_87 = ~stq_addr_is_virtual_3; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_88 = _dword_addr_matches_T_86 & _dword_addr_matches_T_87; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_89 = stq_addr_3_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_91 = _dword_addr_matches_T_89 == _dword_addr_matches_T_90; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_19 = _dword_addr_matches_T_88 & _dword_addr_matches_T_91; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_3 = lcam_mask_0 & write_mask_3; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_3_T = \|mask_union_3; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_3_T_1 = _addr_matches_0_3_T & dword_addr_matches_19; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_3 = _addr_matches_0_3_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_3_T = addr_matches_0_3 & stq_data_3_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_3_T_1 = mask_union_3 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_3_T_2 = _forward_matches_0_3_T & _forward_matches_0_3_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_3 = _forward_matches_0_3_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_3_T = s_uop_5_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_3_T_1 = s_uop_5_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_3_T_2 = _prs2_matches_0_3_T & _prs2_matches_0_3_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_3_T_3 = _prs2_matches_0_3_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_3 = _prs2_matches_0_3_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_4; // @[lsu.scala:1951:22] wire _write_mask_mask_T_60 = s_uop_6_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_61 = stq_addr_4_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_62 = 15'h1 << _write_mask_mask_T_61; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_63 = s_uop_6_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_64 = stq_addr_4_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_65 = {_write_mask_mask_T_64, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_66 = 15'h3 << _write_mask_mask_T_65; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_67 = s_uop_6_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_68 = stq_addr_4_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_69 = _write_mask_mask_T_68 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_70 = &s_uop_6_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_72 = _write_mask_mask_T_67 ? _write_mask_mask_T_69 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_73 = _write_mask_mask_T_63 ? _write_mask_mask_T_66 : {7'h0, _write_mask_mask_T_72}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_74 = _write_mask_mask_T_60 ? _write_mask_mask_T_62 : _write_mask_mask_T_73; // @[Mux.scala:126:16] assign write_mask_4 = _write_mask_mask_T_74[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_92 = ~s_uop_6_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_93 = stq_addr_4_valid & _dword_addr_matches_T_92; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_94 = ~stq_addr_is_virtual_4; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_95 = _dword_addr_matches_T_93 & _dword_addr_matches_T_94; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_96 = stq_addr_4_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_98 = _dword_addr_matches_T_96 == _dword_addr_matches_T_97; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_20 = _dword_addr_matches_T_95 & _dword_addr_matches_T_98; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_4 = lcam_mask_0 & write_mask_4; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_4_T = \|mask_union_4; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_4_T_1 = _addr_matches_0_4_T & dword_addr_matches_20; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_4 = _addr_matches_0_4_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_4_T = addr_matches_0_4 & stq_data_4_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_4_T_1 = mask_union_4 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_4_T_2 = _forward_matches_0_4_T & _forward_matches_0_4_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_4 = _forward_matches_0_4_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_4_T = s_uop_6_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_4_T_1 = s_uop_6_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_4_T_2 = _prs2_matches_0_4_T & _prs2_matches_0_4_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_4_T_3 = _prs2_matches_0_4_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_4 = _prs2_matches_0_4_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_5; // @[lsu.scala:1951:22] wire _write_mask_mask_T_75 = s_uop_7_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_76 = stq_addr_5_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_77 = 15'h1 << _write_mask_mask_T_76; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_78 = s_uop_7_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_79 = stq_addr_5_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_80 = {_write_mask_mask_T_79, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_81 = 15'h3 << _write_mask_mask_T_80; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_82 = s_uop_7_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_83 = stq_addr_5_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_84 = _write_mask_mask_T_83 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_85 = &s_uop_7_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_87 = _write_mask_mask_T_82 ? _write_mask_mask_T_84 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_88 = _write_mask_mask_T_78 ? _write_mask_mask_T_81 : {7'h0, _write_mask_mask_T_87}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_89 = _write_mask_mask_T_75 ? _write_mask_mask_T_77 : _write_mask_mask_T_88; // @[Mux.scala:126:16] assign write_mask_5 = _write_mask_mask_T_89[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_99 = ~s_uop_7_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_100 = stq_addr_5_valid & _dword_addr_matches_T_99; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_101 = ~stq_addr_is_virtual_5; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_102 = _dword_addr_matches_T_100 & _dword_addr_matches_T_101; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_103 = stq_addr_5_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_105 = _dword_addr_matches_T_103 == _dword_addr_matches_T_104; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_21 = _dword_addr_matches_T_102 & _dword_addr_matches_T_105; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_5 = lcam_mask_0 & write_mask_5; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_5_T = \|mask_union_5; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_5_T_1 = _addr_matches_0_5_T & dword_addr_matches_21; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_5 = _addr_matches_0_5_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_5_T = addr_matches_0_5 & stq_data_5_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_5_T_1 = mask_union_5 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_5_T_2 = _forward_matches_0_5_T & _forward_matches_0_5_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_5 = _forward_matches_0_5_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_5_T = s_uop_7_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_5_T_1 = s_uop_7_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_5_T_2 = _prs2_matches_0_5_T & _prs2_matches_0_5_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_5_T_3 = _prs2_matches_0_5_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_5 = _prs2_matches_0_5_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_6; // @[lsu.scala:1951:22] wire _write_mask_mask_T_90 = s_uop_8_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_91 = stq_addr_6_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_92 = 15'h1 << _write_mask_mask_T_91; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_93 = s_uop_8_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_94 = stq_addr_6_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_95 = {_write_mask_mask_T_94, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_96 = 15'h3 << _write_mask_mask_T_95; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_97 = s_uop_8_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_98 = stq_addr_6_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_99 = _write_mask_mask_T_98 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_100 = &s_uop_8_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_102 = _write_mask_mask_T_97 ? _write_mask_mask_T_99 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_103 = _write_mask_mask_T_93 ? _write_mask_mask_T_96 : {7'h0, _write_mask_mask_T_102}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_104 = _write_mask_mask_T_90 ? _write_mask_mask_T_92 : _write_mask_mask_T_103; // @[Mux.scala:126:16] assign write_mask_6 = _write_mask_mask_T_104[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_106 = ~s_uop_8_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_107 = stq_addr_6_valid & _dword_addr_matches_T_106; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_108 = ~stq_addr_is_virtual_6; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_109 = _dword_addr_matches_T_107 & _dword_addr_matches_T_108; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_110 = stq_addr_6_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_112 = _dword_addr_matches_T_110 == _dword_addr_matches_T_111; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_22 = _dword_addr_matches_T_109 & _dword_addr_matches_T_112; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_6 = lcam_mask_0 & write_mask_6; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_6_T = \|mask_union_6; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_6_T_1 = _addr_matches_0_6_T & dword_addr_matches_22; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_6 = _addr_matches_0_6_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_6_T = addr_matches_0_6 & stq_data_6_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_6_T_1 = mask_union_6 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_6_T_2 = _forward_matches_0_6_T & _forward_matches_0_6_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_6 = _forward_matches_0_6_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_6_T = s_uop_8_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_6_T_1 = s_uop_8_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_6_T_2 = _prs2_matches_0_6_T & _prs2_matches_0_6_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_6_T_3 = _prs2_matches_0_6_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_6 = _prs2_matches_0_6_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_7; // @[lsu.scala:1951:22] wire _write_mask_mask_T_105 = s_uop_9_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_106 = stq_addr_7_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_107 = 15'h1 << _write_mask_mask_T_106; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_108 = s_uop_9_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_109 = stq_addr_7_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_110 = {_write_mask_mask_T_109, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_111 = 15'h3 << _write_mask_mask_T_110; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_112 = s_uop_9_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_113 = stq_addr_7_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_114 = _write_mask_mask_T_113 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_115 = &s_uop_9_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_117 = _write_mask_mask_T_112 ? _write_mask_mask_T_114 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_118 = _write_mask_mask_T_108 ? _write_mask_mask_T_111 : {7'h0, _write_mask_mask_T_117}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_119 = _write_mask_mask_T_105 ? _write_mask_mask_T_107 : _write_mask_mask_T_118; // @[Mux.scala:126:16] assign write_mask_7 = _write_mask_mask_T_119[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_113 = ~s_uop_9_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_114 = stq_addr_7_valid & _dword_addr_matches_T_113; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_115 = ~stq_addr_is_virtual_7; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_116 = _dword_addr_matches_T_114 & _dword_addr_matches_T_115; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_117 = stq_addr_7_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_119 = _dword_addr_matches_T_117 == _dword_addr_matches_T_118; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_23 = _dword_addr_matches_T_116 & _dword_addr_matches_T_119; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_7 = lcam_mask_0 & write_mask_7; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_7_T = \|mask_union_7; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_7_T_1 = _addr_matches_0_7_T & dword_addr_matches_23; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_7 = _addr_matches_0_7_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_7_T = addr_matches_0_7 & stq_data_7_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_7_T_1 = mask_union_7 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_7_T_2 = _forward_matches_0_7_T & _forward_matches_0_7_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_7 = _forward_matches_0_7_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_7_T = s_uop_9_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_7_T_1 = s_uop_9_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_7_T_2 = _prs2_matches_0_7_T & _prs2_matches_0_7_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_7_T_3 = _prs2_matches_0_7_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_7 = _prs2_matches_0_7_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_8; // @[lsu.scala:1951:22] wire _write_mask_mask_T_120 = s_uop_10_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_121 = stq_addr_8_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_122 = 15'h1 << _write_mask_mask_T_121; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_123 = s_uop_10_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_124 = stq_addr_8_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_125 = {_write_mask_mask_T_124, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_126 = 15'h3 << _write_mask_mask_T_125; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_127 = s_uop_10_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_128 = stq_addr_8_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_129 = _write_mask_mask_T_128 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_130 = &s_uop_10_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_132 = _write_mask_mask_T_127 ? _write_mask_mask_T_129 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_133 = _write_mask_mask_T_123 ? _write_mask_mask_T_126 : {7'h0, _write_mask_mask_T_132}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_134 = _write_mask_mask_T_120 ? _write_mask_mask_T_122 : _write_mask_mask_T_133; // @[Mux.scala:126:16] assign write_mask_8 = _write_mask_mask_T_134[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_120 = ~s_uop_10_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_121 = stq_addr_8_valid & _dword_addr_matches_T_120; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_122 = ~stq_addr_is_virtual_8; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_123 = _dword_addr_matches_T_121 & _dword_addr_matches_T_122; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_124 = stq_addr_8_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_126 = _dword_addr_matches_T_124 == _dword_addr_matches_T_125; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_24 = _dword_addr_matches_T_123 & _dword_addr_matches_T_126; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_8 = lcam_mask_0 & write_mask_8; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_8_T = \|mask_union_8; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_8_T_1 = _addr_matches_0_8_T & dword_addr_matches_24; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_8 = _addr_matches_0_8_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_8_T = addr_matches_0_8 & stq_data_8_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_8_T_1 = mask_union_8 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_8_T_2 = _forward_matches_0_8_T & _forward_matches_0_8_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_8 = _forward_matches_0_8_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_8_T = s_uop_10_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_8_T_1 = s_uop_10_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_8_T_2 = _prs2_matches_0_8_T & _prs2_matches_0_8_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_8_T_3 = _prs2_matches_0_8_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_8 = _prs2_matches_0_8_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_9; // @[lsu.scala:1951:22] wire _write_mask_mask_T_135 = s_uop_11_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_136 = stq_addr_9_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_137 = 15'h1 << _write_mask_mask_T_136; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_138 = s_uop_11_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_139 = stq_addr_9_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_140 = {_write_mask_mask_T_139, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_141 = 15'h3 << _write_mask_mask_T_140; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_142 = s_uop_11_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_143 = stq_addr_9_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_144 = _write_mask_mask_T_143 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_145 = &s_uop_11_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_147 = _write_mask_mask_T_142 ? _write_mask_mask_T_144 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_148 = _write_mask_mask_T_138 ? _write_mask_mask_T_141 : {7'h0, _write_mask_mask_T_147}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_149 = _write_mask_mask_T_135 ? _write_mask_mask_T_137 : _write_mask_mask_T_148; // @[Mux.scala:126:16] assign write_mask_9 = _write_mask_mask_T_149[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_127 = ~s_uop_11_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_128 = stq_addr_9_valid & _dword_addr_matches_T_127; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_129 = ~stq_addr_is_virtual_9; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_130 = _dword_addr_matches_T_128 & _dword_addr_matches_T_129; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_131 = stq_addr_9_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_133 = _dword_addr_matches_T_131 == _dword_addr_matches_T_132; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_25 = _dword_addr_matches_T_130 & _dword_addr_matches_T_133; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_9 = lcam_mask_0 & write_mask_9; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_9_T = \|mask_union_9; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_9_T_1 = _addr_matches_0_9_T & dword_addr_matches_25; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_9 = _addr_matches_0_9_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_9_T = addr_matches_0_9 & stq_data_9_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_9_T_1 = mask_union_9 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_9_T_2 = _forward_matches_0_9_T & _forward_matches_0_9_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_9 = _forward_matches_0_9_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_9_T = s_uop_11_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_9_T_1 = s_uop_11_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_9_T_2 = _prs2_matches_0_9_T & _prs2_matches_0_9_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_9_T_3 = _prs2_matches_0_9_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_9 = _prs2_matches_0_9_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_10; // @[lsu.scala:1951:22] wire _write_mask_mask_T_150 = s_uop_12_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_151 = stq_addr_10_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_152 = 15'h1 << _write_mask_mask_T_151; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_153 = s_uop_12_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_154 = stq_addr_10_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_155 = {_write_mask_mask_T_154, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_156 = 15'h3 << _write_mask_mask_T_155; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_157 = s_uop_12_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_158 = stq_addr_10_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_159 = _write_mask_mask_T_158 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_160 = &s_uop_12_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_162 = _write_mask_mask_T_157 ? _write_mask_mask_T_159 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_163 = _write_mask_mask_T_153 ? _write_mask_mask_T_156 : {7'h0, _write_mask_mask_T_162}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_164 = _write_mask_mask_T_150 ? _write_mask_mask_T_152 : _write_mask_mask_T_163; // @[Mux.scala:126:16] assign write_mask_10 = _write_mask_mask_T_164[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_134 = ~s_uop_12_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_135 = stq_addr_10_valid & _dword_addr_matches_T_134; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_136 = ~stq_addr_is_virtual_10; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_137 = _dword_addr_matches_T_135 & _dword_addr_matches_T_136; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_138 = stq_addr_10_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_140 = _dword_addr_matches_T_138 == _dword_addr_matches_T_139; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_26 = _dword_addr_matches_T_137 & _dword_addr_matches_T_140; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_10 = lcam_mask_0 & write_mask_10; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_10_T = \|mask_union_10; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_10_T_1 = _addr_matches_0_10_T & dword_addr_matches_26; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_10 = _addr_matches_0_10_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_10_T = addr_matches_0_10 & stq_data_10_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_10_T_1 = mask_union_10 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_10_T_2 = _forward_matches_0_10_T & _forward_matches_0_10_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_10 = _forward_matches_0_10_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_10_T = s_uop_12_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_10_T_1 = s_uop_12_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_10_T_2 = _prs2_matches_0_10_T & _prs2_matches_0_10_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_10_T_3 = _prs2_matches_0_10_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_10 = _prs2_matches_0_10_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_11; // @[lsu.scala:1951:22] wire _write_mask_mask_T_165 = s_uop_13_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_166 = stq_addr_11_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_167 = 15'h1 << _write_mask_mask_T_166; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_168 = s_uop_13_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_169 = stq_addr_11_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_170 = {_write_mask_mask_T_169, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_171 = 15'h3 << _write_mask_mask_T_170; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_172 = s_uop_13_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_173 = stq_addr_11_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_174 = _write_mask_mask_T_173 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_175 = &s_uop_13_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_177 = _write_mask_mask_T_172 ? _write_mask_mask_T_174 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_178 = _write_mask_mask_T_168 ? _write_mask_mask_T_171 : {7'h0, _write_mask_mask_T_177}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_179 = _write_mask_mask_T_165 ? _write_mask_mask_T_167 : _write_mask_mask_T_178; // @[Mux.scala:126:16] assign write_mask_11 = _write_mask_mask_T_179[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_141 = ~s_uop_13_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_142 = stq_addr_11_valid & _dword_addr_matches_T_141; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_143 = ~stq_addr_is_virtual_11; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_144 = _dword_addr_matches_T_142 & _dword_addr_matches_T_143; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_145 = stq_addr_11_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_147 = _dword_addr_matches_T_145 == _dword_addr_matches_T_146; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_27 = _dword_addr_matches_T_144 & _dword_addr_matches_T_147; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_11 = lcam_mask_0 & write_mask_11; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_11_T = \|mask_union_11; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_11_T_1 = _addr_matches_0_11_T & dword_addr_matches_27; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_11 = _addr_matches_0_11_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_11_T = addr_matches_0_11 & stq_data_11_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_11_T_1 = mask_union_11 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_11_T_2 = _forward_matches_0_11_T & _forward_matches_0_11_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_11 = _forward_matches_0_11_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_11_T = s_uop_13_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_11_T_1 = s_uop_13_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_11_T_2 = _prs2_matches_0_11_T & _prs2_matches_0_11_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_11_T_3 = _prs2_matches_0_11_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_11 = _prs2_matches_0_11_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_12; // @[lsu.scala:1951:22] wire _write_mask_mask_T_180 = s_uop_14_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_181 = stq_addr_12_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_182 = 15'h1 << _write_mask_mask_T_181; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_183 = s_uop_14_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_184 = stq_addr_12_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_185 = {_write_mask_mask_T_184, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_186 = 15'h3 << _write_mask_mask_T_185; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_187 = s_uop_14_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_188 = stq_addr_12_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_189 = _write_mask_mask_T_188 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_190 = &s_uop_14_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_192 = _write_mask_mask_T_187 ? _write_mask_mask_T_189 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_193 = _write_mask_mask_T_183 ? _write_mask_mask_T_186 : {7'h0, _write_mask_mask_T_192}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_194 = _write_mask_mask_T_180 ? _write_mask_mask_T_182 : _write_mask_mask_T_193; // @[Mux.scala:126:16] assign write_mask_12 = _write_mask_mask_T_194[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_148 = ~s_uop_14_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_149 = stq_addr_12_valid & _dword_addr_matches_T_148; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_150 = ~stq_addr_is_virtual_12; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_151 = _dword_addr_matches_T_149 & _dword_addr_matches_T_150; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_152 = stq_addr_12_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_154 = _dword_addr_matches_T_152 == _dword_addr_matches_T_153; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_28 = _dword_addr_matches_T_151 & _dword_addr_matches_T_154; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_12 = lcam_mask_0 & write_mask_12; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_12_T = \|mask_union_12; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_12_T_1 = _addr_matches_0_12_T & dword_addr_matches_28; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_12 = _addr_matches_0_12_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_12_T = addr_matches_0_12 & stq_data_12_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_12_T_1 = mask_union_12 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_12_T_2 = _forward_matches_0_12_T & _forward_matches_0_12_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_12 = _forward_matches_0_12_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_12_T = s_uop_14_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_12_T_1 = s_uop_14_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_12_T_2 = _prs2_matches_0_12_T & _prs2_matches_0_12_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_12_T_3 = _prs2_matches_0_12_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_12 = _prs2_matches_0_12_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_13; // @[lsu.scala:1951:22] wire _write_mask_mask_T_195 = s_uop_15_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_196 = stq_addr_13_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_197 = 15'h1 << _write_mask_mask_T_196; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_198 = s_uop_15_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_199 = stq_addr_13_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_200 = {_write_mask_mask_T_199, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_201 = 15'h3 << _write_mask_mask_T_200; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_202 = s_uop_15_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_203 = stq_addr_13_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_204 = _write_mask_mask_T_203 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_205 = &s_uop_15_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_207 = _write_mask_mask_T_202 ? _write_mask_mask_T_204 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_208 = _write_mask_mask_T_198 ? _write_mask_mask_T_201 : {7'h0, _write_mask_mask_T_207}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_209 = _write_mask_mask_T_195 ? _write_mask_mask_T_197 : _write_mask_mask_T_208; // @[Mux.scala:126:16] assign write_mask_13 = _write_mask_mask_T_209[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_155 = ~s_uop_15_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_156 = stq_addr_13_valid & _dword_addr_matches_T_155; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_157 = ~stq_addr_is_virtual_13; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_158 = _dword_addr_matches_T_156 & _dword_addr_matches_T_157; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_159 = stq_addr_13_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_161 = _dword_addr_matches_T_159 == _dword_addr_matches_T_160; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_29 = _dword_addr_matches_T_158 & _dword_addr_matches_T_161; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_13 = lcam_mask_0 & write_mask_13; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_13_T = \|mask_union_13; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_13_T_1 = _addr_matches_0_13_T & dword_addr_matches_29; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_13 = _addr_matches_0_13_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_13_T = addr_matches_0_13 & stq_data_13_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_13_T_1 = mask_union_13 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_13_T_2 = _forward_matches_0_13_T & _forward_matches_0_13_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_13 = _forward_matches_0_13_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_13_T = s_uop_15_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_13_T_1 = s_uop_15_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_13_T_2 = _prs2_matches_0_13_T & _prs2_matches_0_13_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_13_T_3 = _prs2_matches_0_13_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_13 = _prs2_matches_0_13_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_14; // @[lsu.scala:1951:22] wire _write_mask_mask_T_210 = s_uop_16_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_211 = stq_addr_14_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_212 = 15'h1 << _write_mask_mask_T_211; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_213 = s_uop_16_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_214 = stq_addr_14_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_215 = {_write_mask_mask_T_214, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_216 = 15'h3 << _write_mask_mask_T_215; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_217 = s_uop_16_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_218 = stq_addr_14_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_219 = _write_mask_mask_T_218 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_220 = &s_uop_16_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_222 = _write_mask_mask_T_217 ? _write_mask_mask_T_219 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_223 = _write_mask_mask_T_213 ? _write_mask_mask_T_216 : {7'h0, _write_mask_mask_T_222}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_224 = _write_mask_mask_T_210 ? _write_mask_mask_T_212 : _write_mask_mask_T_223; // @[Mux.scala:126:16] assign write_mask_14 = _write_mask_mask_T_224[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_162 = ~s_uop_16_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_163 = stq_addr_14_valid & _dword_addr_matches_T_162; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_164 = ~stq_addr_is_virtual_14; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_165 = _dword_addr_matches_T_163 & _dword_addr_matches_T_164; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_166 = stq_addr_14_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_168 = _dword_addr_matches_T_166 == _dword_addr_matches_T_167; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_30 = _dword_addr_matches_T_165 & _dword_addr_matches_T_168; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_14 = lcam_mask_0 & write_mask_14; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_14_T = \|mask_union_14; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_14_T_1 = _addr_matches_0_14_T & dword_addr_matches_30; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_14 = _addr_matches_0_14_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_14_T = addr_matches_0_14 & stq_data_14_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_14_T_1 = mask_union_14 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_14_T_2 = _forward_matches_0_14_T & _forward_matches_0_14_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_14 = _forward_matches_0_14_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_14_T = s_uop_16_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_14_T_1 = s_uop_16_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_14_T_2 = _prs2_matches_0_14_T & _prs2_matches_0_14_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_14_T_3 = _prs2_matches_0_14_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_14 = _prs2_matches_0_14_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_15; // @[lsu.scala:1951:22] wire _write_mask_mask_T_225 = s_uop_17_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_226 = stq_addr_15_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_227 = 15'h1 << _write_mask_mask_T_226; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_228 = s_uop_17_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_229 = stq_addr_15_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_230 = {_write_mask_mask_T_229, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_231 = 15'h3 << _write_mask_mask_T_230; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_232 = s_uop_17_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_233 = stq_addr_15_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_234 = _write_mask_mask_T_233 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_235 = &s_uop_17_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_237 = _write_mask_mask_T_232 ? _write_mask_mask_T_234 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_238 = _write_mask_mask_T_228 ? _write_mask_mask_T_231 : {7'h0, _write_mask_mask_T_237}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_239 = _write_mask_mask_T_225 ? _write_mask_mask_T_227 : _write_mask_mask_T_238; // @[Mux.scala:126:16] assign write_mask_15 = _write_mask_mask_T_239[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_169 = ~s_uop_17_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_170 = stq_addr_15_valid & _dword_addr_matches_T_169; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_171 = ~stq_addr_is_virtual_15; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_172 = _dword_addr_matches_T_170 & _dword_addr_matches_T_171; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_173 = stq_addr_15_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_175 = _dword_addr_matches_T_173 == _dword_addr_matches_T_174; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_31 = _dword_addr_matches_T_172 & _dword_addr_matches_T_175; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_15 = lcam_mask_0 & write_mask_15; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_15_T = \|mask_union_15; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_15_T_1 = _addr_matches_0_15_T & dword_addr_matches_31; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_15 = _addr_matches_0_15_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_15_T = addr_matches_0_15 & stq_data_15_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_15_T_1 = mask_union_15 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_15_T_2 = _forward_matches_0_15_T & _forward_matches_0_15_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_15 = _forward_matches_0_15_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_15_T = s_uop_17_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_15_T_1 = s_uop_17_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_15_T_2 = _prs2_matches_0_15_T & _prs2_matches_0_15_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_15_T_3 = _prs2_matches_0_15_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_15 = _prs2_matches_0_15_T_3; // @[lsu.scala:1318:29, :1338:58] wire [3:0] fast_stq_valids_lo_lo = {fast_stq_valids_lo_lo_hi, fast_stq_valids_lo_lo_lo}; // @[lsu.scala:1342:35] wire [3:0] fast_stq_valids_lo_hi = {fast_stq_valids_lo_hi_hi, fast_stq_valids_lo_hi_lo}; // @[lsu.scala:1342:35] wire [7:0] fast_stq_valids_lo = {fast_stq_valids_lo_hi, fast_stq_valids_lo_lo}; // @[lsu.scala:1342:35] wire [3:0] fast_stq_valids_hi_lo = {fast_stq_valids_hi_lo_hi, fast_stq_valids_hi_lo_lo}; // @[lsu.scala:1342:35] wire [3:0] fast_stq_valids_hi_hi = {fast_stq_valids_hi_hi_hi, fast_stq_valids_hi_hi_lo}; // @[lsu.scala:1342:35] wire [7:0] fast_stq_valids_hi = {fast_stq_valids_hi_hi, fast_stq_valids_hi_lo}; // @[lsu.scala:1342:35] wire [15:0] fast_stq_valids = {fast_stq_valids_hi, fast_stq_valids_lo}; // @[lsu.scala:1342:35] wire [1:0] ldst_addr_matches_0_lo_lo_lo = {addr_matches_0_1, addr_matches_0_0}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_lo_lo_hi = {addr_matches_0_3, addr_matches_0_2}; // @[lsu.scala:1316:29, :1344:49] wire [3:0] ldst_addr_matches_0_lo_lo = {ldst_addr_matches_0_lo_lo_hi, ldst_addr_matches_0_lo_lo_lo}; // @[lsu.scala:1344:49] wire [1:0] ldst_addr_matches_0_lo_hi_lo = {addr_matches_0_5, addr_matches_0_4}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_lo_hi_hi = {addr_matches_0_7, addr_matches_0_6}; // @[lsu.scala:1316:29, :1344:49] wire [3:0] ldst_addr_matches_0_lo_hi = {ldst_addr_matches_0_lo_hi_hi, ldst_addr_matches_0_lo_hi_lo}; // @[lsu.scala:1344:49] wire [7:0] ldst_addr_matches_0_lo = {ldst_addr_matches_0_lo_hi, ldst_addr_matches_0_lo_lo}; // @[lsu.scala:1344:49] wire [1:0] ldst_addr_matches_0_hi_lo_lo = {addr_matches_0_9, addr_matches_0_8}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_hi_lo_hi = {addr_matches_0_11, addr_matches_0_10}; // @[lsu.scala:1316:29, :1344:49] wire [3:0] ldst_addr_matches_0_hi_lo = {ldst_addr_matches_0_hi_lo_hi, ldst_addr_matches_0_hi_lo_lo}; // @[lsu.scala:1344:49] wire [1:0] ldst_addr_matches_0_hi_hi_lo = {addr_matches_0_13, addr_matches_0_12}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_hi_hi_hi = {addr_matches_0_15, addr_matches_0_14}; // @[lsu.scala:1316:29, :1344:49] wire [3:0] ldst_addr_matches_0_hi_hi = {ldst_addr_matches_0_hi_hi_hi, ldst_addr_matches_0_hi_hi_lo}; // @[lsu.scala:1344:49] wire [7:0] ldst_addr_matches_0_hi = {ldst_addr_matches_0_hi_hi, ldst_addr_matches_0_hi_lo}; // @[lsu.scala:1344:49] wire [15:0] _ldst_addr_matches_0_T = {ldst_addr_matches_0_hi, ldst_addr_matches_0_lo}; // @[lsu.scala:1344:49] wire [15:0] _ldst_addr_matches_0_T_1 = _ldst_addr_matches_0_T & lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1344:{49,56}] assign _ldst_addr_matches_0_T_2 = _ldst_addr_matches_0_T_1 & fast_stq_valids; // @[lsu.scala:1342:35, :1344:{56,79}] assign ldst_addr_matches_0 = _ldst_addr_matches_0_T_2; // @[lsu.scala:1162:34, :1344:79] wire [1:0] ldst_forward_matches_0_lo_lo_lo = {forward_matches_0_1, forward_matches_0_0}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_lo_lo_hi = {forward_matches_0_3, forward_matches_0_2}; // @[lsu.scala:1317:29, :1345:52] wire [3:0] ldst_forward_matches_0_lo_lo = {ldst_forward_matches_0_lo_lo_hi, ldst_forward_matches_0_lo_lo_lo}; // @[lsu.scala:1345:52] wire [1:0] ldst_forward_matches_0_lo_hi_lo = {forward_matches_0_5, forward_matches_0_4}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_lo_hi_hi = {forward_matches_0_7, forward_matches_0_6}; // @[lsu.scala:1317:29, :1345:52] wire [3:0] ldst_forward_matches_0_lo_hi = {ldst_forward_matches_0_lo_hi_hi, ldst_forward_matches_0_lo_hi_lo}; // @[lsu.scala:1345:52] wire [7:0] ldst_forward_matches_0_lo = {ldst_forward_matches_0_lo_hi, ldst_forward_matches_0_lo_lo}; // @[lsu.scala:1345:52] wire [1:0] ldst_forward_matches_0_hi_lo_lo = {forward_matches_0_9, forward_matches_0_8}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_hi_lo_hi = {forward_matches_0_11, forward_matches_0_10}; // @[lsu.scala:1317:29, :1345:52] wire [3:0] ldst_forward_matches_0_hi_lo = {ldst_forward_matches_0_hi_lo_hi, ldst_forward_matches_0_hi_lo_lo}; // @[lsu.scala:1345:52] wire [1:0] ldst_forward_matches_0_hi_hi_lo = {forward_matches_0_13, forward_matches_0_12}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_hi_hi_hi = {forward_matches_0_15, forward_matches_0_14}; // @[lsu.scala:1317:29, :1345:52] wire [3:0] ldst_forward_matches_0_hi_hi = {ldst_forward_matches_0_hi_hi_hi, ldst_forward_matches_0_hi_hi_lo}; // @[lsu.scala:1345:52] wire [7:0] ldst_forward_matches_0_hi = {ldst_forward_matches_0_hi_hi, ldst_forward_matches_0_hi_lo}; // @[lsu.scala:1345:52] wire [15:0] _ldst_forward_matches_0_T = {ldst_forward_matches_0_hi, ldst_forward_matches_0_lo}; // @[lsu.scala:1345:52] wire [15:0] _ldst_forward_matches_0_T_1 = _ldst_forward_matches_0_T & lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1345:{52,59}] assign _ldst_forward_matches_0_T_2 = _ldst_forward_matches_0_T_1 & fast_stq_valids; // @[lsu.scala:1342:35, :1345:{59,82}] assign ldst_forward_matches_0 = _ldst_forward_matches_0_T_2; // @[lsu.scala:1164:34, :1345:82] wire [1:0] stld_prs2_matches_0_lo_lo_lo = {prs2_matches_0_1, prs2_matches_0_0}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_lo_lo_hi = {prs2_matches_0_3, prs2_matches_0_2}; // @[lsu.scala:1318:29, :1346:49] wire [3:0] stld_prs2_matches_0_lo_lo = {stld_prs2_matches_0_lo_lo_hi, stld_prs2_matches_0_lo_lo_lo}; // @[lsu.scala:1346:49] wire [1:0] stld_prs2_matches_0_lo_hi_lo = {prs2_matches_0_5, prs2_matches_0_4}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_lo_hi_hi = {prs2_matches_0_7, prs2_matches_0_6}; // @[lsu.scala:1318:29, :1346:49] wire [3:0] stld_prs2_matches_0_lo_hi = {stld_prs2_matches_0_lo_hi_hi, stld_prs2_matches_0_lo_hi_lo}; // @[lsu.scala:1346:49] wire [7:0] stld_prs2_matches_0_lo = {stld_prs2_matches_0_lo_hi, stld_prs2_matches_0_lo_lo}; // @[lsu.scala:1346:49] wire [1:0] stld_prs2_matches_0_hi_lo_lo = {prs2_matches_0_9, prs2_matches_0_8}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_hi_lo_hi = {prs2_matches_0_11, prs2_matches_0_10}; // @[lsu.scala:1318:29, :1346:49] wire [3:0] stld_prs2_matches_0_hi_lo = {stld_prs2_matches_0_hi_lo_hi, stld_prs2_matches_0_hi_lo_lo}; // @[lsu.scala:1346:49] wire [1:0] stld_prs2_matches_0_hi_hi_lo = {prs2_matches_0_13, prs2_matches_0_12}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_hi_hi_hi = {prs2_matches_0_15, prs2_matches_0_14}; // @[lsu.scala:1318:29, :1346:49] wire [3:0] stld_prs2_matches_0_hi_hi = {stld_prs2_matches_0_hi_hi_hi, stld_prs2_matches_0_hi_hi_lo}; // @[lsu.scala:1346:49] wire [7:0] stld_prs2_matches_0_hi = {stld_prs2_matches_0_hi_hi, stld_prs2_matches_0_hi_lo}; // @[lsu.scala:1346:49] wire [15:0] _stld_prs2_matches_0_T = {stld_prs2_matches_0_hi, stld_prs2_matches_0_lo}; // @[lsu.scala:1346:49] wire [15:0] _stld_prs2_matches_0_T_1 = ~lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1346:58] wire [15:0] _stld_prs2_matches_0_T_2 = _stld_prs2_matches_0_T & _stld_prs2_matches_0_T_1; // @[lsu.scala:1346:{49,56,58}] assign _stld_prs2_matches_0_T_3 = _stld_prs2_matches_0_T_2 & fast_stq_valids; // @[lsu.scala:1342:35, :1346:{56,80}] assign stld_prs2_matches_0 = _stld_prs2_matches_0_T_3; // @[lsu.scala:1166:34, :1346:80] wire _stq_amos_T = stq_uop_0_is_fence \| stq_uop_0_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_0 = _stq_amos_T; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_1 = stq_uop_1_is_fence \| stq_uop_1_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_1 = _stq_amos_T_1; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_2 = stq_uop_2_is_fence \| stq_uop_2_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_2 = _stq_amos_T_2; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_3 = stq_uop_3_is_fence \| stq_uop_3_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_3 = _stq_amos_T_3; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_4 = stq_uop_4_is_fence \| stq_uop_4_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_4 = _stq_amos_T_4; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_5 = stq_uop_5_is_fence \| stq_uop_5_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_5 = _stq_amos_T_5; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_6 = stq_uop_6_is_fence \| stq_uop_6_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_6 = _stq_amos_T_6; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_7 = stq_uop_7_is_fence \| stq_uop_7_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_7 = _stq_amos_T_7; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_8 = stq_uop_8_is_fence \| stq_uop_8_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_8 = _stq_amos_T_8; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_9 = stq_uop_9_is_fence \| stq_uop_9_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_9 = _stq_amos_T_9; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_10 = stq_uop_10_is_fence \| stq_uop_10_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_10 = _stq_amos_T_10; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_11 = stq_uop_11_is_fence \| stq_uop_11_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_11 = _stq_amos_T_11; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_12 = stq_uop_12_is_fence \| stq_uop_12_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_12 = _stq_amos_T_12; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_13 = stq_uop_13_is_fence \| stq_uop_13_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_13 = _stq_amos_T_13; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_14 = stq_uop_14_is_fence \| stq_uop_14_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_14 = _stq_amos_T_14; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_15 = stq_uop_15_is_fence \| stq_uop_15_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_15 = _stq_amos_T_15; // @[lsu.scala:1349:{25,54}] wire [1:0] has_older_amo_lo_lo_lo = {stq_amos_1, stq_amos_0}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_lo_lo_hi = {stq_amos_3, stq_amos_2}; // @[lsu.scala:1349:25, :1351:35] wire [3:0] has_older_amo_lo_lo = {has_older_amo_lo_lo_hi, has_older_amo_lo_lo_lo}; // @[lsu.scala:1351:35] wire [1:0] has_older_amo_lo_hi_lo = {stq_amos_5, stq_amos_4}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_lo_hi_hi = {stq_amos_7, stq_amos_6}; // @[lsu.scala:1349:25, :1351:35] wire [3:0] has_older_amo_lo_hi = {has_older_amo_lo_hi_hi, has_older_amo_lo_hi_lo}; // @[lsu.scala:1351:35] wire [7:0] has_older_amo_lo = {has_older_amo_lo_hi, has_older_amo_lo_lo}; // @[lsu.scala:1351:35] wire [1:0] has_older_amo_hi_lo_lo = {stq_amos_9, stq_amos_8}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_hi_lo_hi = {stq_amos_11, stq_amos_10}; // @[lsu.scala:1349:25, :1351:35] wire [3:0] has_older_amo_hi_lo = {has_older_amo_hi_lo_hi, has_older_amo_hi_lo_lo}; // @[lsu.scala:1351:35] wire [1:0] has_older_amo_hi_hi_lo = {stq_amos_13, stq_amos_12}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_hi_hi_hi = {stq_amos_15, stq_amos_14}; // @[lsu.scala:1349:25, :1351:35] wire [3:0] has_older_amo_hi_hi = {has_older_amo_hi_hi_hi, has_older_amo_hi_hi_lo}; // @[lsu.scala:1351:35] wire [7:0] has_older_amo_hi = {has_older_amo_hi_hi, has_older_amo_hi_lo}; // @[lsu.scala:1351:35] wire [15:0] _has_older_amo_T = {has_older_amo_hi, has_older_amo_lo}; // @[lsu.scala:1351:35] wire [15:0] _has_older_amo_T_1 = _has_older_amo_T & lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1351:{35,42}] wire has_older_amo = \|_has_older_amo_T_1; // @[lsu.scala:1351:{42,65}] wire _T_1126 = do_ld_search_0 & (\|{has_older_amo, ldst_addr_matches_0}); // @[lsu.scala:321:49, :1162:34, :1351:65, :1352:{27,45,70}] reg REG_18; // @[lsu.scala:1353:20] assign io_dmem_s1_kill_0_0 = _T_1126 ? REG_18 & ~fired_load_agen_0 \| _GEN_487 \| _GEN_469 : _GEN_487 \| _GEN_469; // @[lsu.scala:211:7, :321:49, :893:24, :1235:37, :1239:34, :1278:84, :1280:{57,81}, :1281:30, :1352:{27,81}, :1353:{20,55,58,79}, :1354:42] assign s1_set_execute_0 = _T_1126 ? ~(_GEN_395 \| _GEN_471) & _GEN_454 : ~_GEN_471 & _GEN_454; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_1 = _T_1126 ? ~(_GEN_396 \| _GEN_472) & _GEN_455 : ~_GEN_472 & _GEN_455; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_2 = _T_1126 ? ~(_GEN_397 \| _GEN_473) & _GEN_456 : ~_GEN_473 & _GEN_456; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_3 = _T_1126 ? ~(_GEN_398 \| _GEN_474) & _GEN_457 : ~_GEN_474 & _GEN_457; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_4 = _T_1126 ? ~(_GEN_399 \| _GEN_475) & _GEN_458 : ~_GEN_475 & _GEN_458; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_5 = _T_1126 ? ~(_GEN_400 \| _GEN_476) & _GEN_459 : ~_GEN_476 & _GEN_459; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_6 = _T_1126 ? ~(_GEN_401 \| _GEN_477) & _GEN_460 : ~_GEN_477 & _GEN_460; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_7 = _T_1126 ? ~(_GEN_402 \| _GEN_478) & _GEN_461 : ~_GEN_478 & _GEN_461; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_8 = _T_1126 ? ~(_GEN_403 \| _GEN_479) & _GEN_462 : ~_GEN_479 & _GEN_462; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_9 = _T_1126 ? ~(_GEN_404 \| _GEN_480) & _GEN_463 : ~_GEN_480 & _GEN_463; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_10 = _T_1126 ? ~(_GEN_405 \| _GEN_481) & _GEN_464 : ~_GEN_481 & _GEN_464; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_11 = _T_1126 ? ~(_GEN_406 \| _GEN_482) & _GEN_465 : ~_GEN_482 & _GEN_465; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_12 = _T_1126 ? ~(_GEN_407 \| _GEN_483) & _GEN_466 : ~_GEN_483 & _GEN_466; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_13 = _T_1126 ? ~(_GEN_408 \| _GEN_484) & _GEN_467 : ~_GEN_484 & _GEN_467; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_14 = _T_1126 ? ~(_GEN_409 \| _GEN_485) & _GEN_468 : ~_GEN_485 & _GEN_468; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_15 = _T_1126 ? ~((&lcam_ldq_idx_0) \| _GEN_486) & _GEN_451 : ~_GEN_486 & _GEN_451; // @[lsu.scala:321:49, :1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign kill_forward_0 = _T_1126 ? has_older_amo \| _T_1096 \| _GEN_470 : _T_1096 \| _GEN_470; // @[lsu.scala:1159:30, :1235:37, :1239:34, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1283:25, :1351:65, :1352:{27,81}, :1357:28, :1358:25] wire _wb_ldst_forward_valid_0_T = _logic_io_found_idx == _logic_1_io_found_idx; // @[lsu.scala:1377:55, :1965:23] wire _wb_ldst_forward_valid_0_T_1 = _wb_ldst_forward_valid_0_T & _logic_io_found; // @[lsu.scala:1377:{55,100}, :1965:23] wire _wb_ldst_forward_valid_0_T_2 = _wb_ldst_forward_valid_0_T_1 & _logic_1_io_found; // @[lsu.scala:1377:100, :1378:100, :1965:23] wire _wb_ldst_forward_valid_0_T_3 = ~kill_forward_0; // @[lsu.scala:1159:30, :1380:63] wire _wb_ldst_forward_valid_0_T_4 = can_forward_0 & _wb_ldst_forward_valid_0_T_3; // @[lsu.scala:321:49, :1380:{60,63}] wire _wb_ldst_forward_valid_0_T_5 = _wb_ldst_forward_valid_0_T_4 & do_ld_search_0; // @[lsu.scala:321:49, :1380:{60,80}] reg wb_ldst_forward_valid_0_REG; // @[lsu.scala:1380:44] wire _wb_ldst_forward_valid_0_T_6 = _wb_ldst_forward_valid_0_T_2 & wb_ldst_forward_valid_0_REG; // @[lsu.scala:1378:100, :1379:100, :1380:44] wire [11:0] _wb_ldst_forward_valid_0_T_7 = io_core_brupdate_b1_mispredict_mask_0 & lcam_uop_0_br_mask; // @[util.scala:126:51] wire _wb_ldst_forward_valid_0_T_8 = \|_wb_ldst_forward_valid_0_T_7; // @[util.scala:126:{51,59}] wire _wb_ldst_forward_valid_0_T_9 = _wb_ldst_forward_valid_0_T_8 \| io_core_exception_0; // @[util.scala:61:61, :126:59] reg wb_ldst_forward_valid_0_REG_1; // @[lsu.scala:1381:45] wire _wb_ldst_forward_valid_0_T_10 = ~wb_ldst_forward_valid_0_REG_1; // @[lsu.scala:1381:{37,45}] assign _wb_ldst_forward_valid_0_T_11 = _wb_ldst_forward_valid_0_T_6 & _wb_ldst_forward_valid_0_T_10; // @[lsu.scala:1379:100, :1380:100, :1381:37] assign wb_ldst_forward_valid_0 = _wb_ldst_forward_valid_0_T_11; // @[lsu.scala:1172:38, :1380:100] reg REG_19; // @[lsu.scala:1394:18] reg [3:0] store_blocked_counter; // @[lsu.scala:1399:36] wire _store_blocked_counter_T = &store_blocked_counter; // @[lsu.scala:1399:36, :1403:58] wire [4:0] _store_blocked_counter_T_1 = {1'h0, store_blocked_counter} + 5'h1; // @[lsu.scala:1399:36, :1403:96] wire [3:0] _store_blocked_counter_T_2 = _store_blocked_counter_T_1[3:0]; // @[lsu.scala:1403:96] wire [3:0] _store_blocked_counter_T_3 = _store_blocked_counter_T ? 4'hF : _store_blocked_counter_T_2; // @[lsu.scala:1403:{35,58,96}] assign block_load_wakeup = (&store_blocked_counter) \| REG_19 & ~wb_ldst_forward_valid_0; // @[lsu.scala:623:35, :1172:38, :1394:{18,49,52,79}, :1399:36, :1405:{33,43}, :1406:25] wire _mem_stld_forward_stq_idx_T = stld_prs2_matches_0[0]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_1 = stld_prs2_matches_0[1]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_2 = stld_prs2_matches_0[2]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_3 = stld_prs2_matches_0[3]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_4 = stld_prs2_matches_0[4]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_5 = stld_prs2_matches_0[5]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_6 = stld_prs2_matches_0[6]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_7 = stld_prs2_matches_0[7]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_8 = stld_prs2_matches_0[8]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_9 = stld_prs2_matches_0[9]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_10 = stld_prs2_matches_0[10]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_11 = stld_prs2_matches_0[11]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_12 = stld_prs2_matches_0[12]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_13 = stld_prs2_matches_0[13]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_14 = stld_prs2_matches_0[14]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_15 = stld_prs2_matches_0[15]; // @[lsu.scala:1166:34, :1412:88] wire mem_stld_forward_stq_idx_temp_vec_15 = _mem_stld_forward_stq_idx_T_15; // @[util.scala:352:65] wire _mem_stld_forward_stq_idx_temp_vec_T = lcam_uop_0_stq_idx == 4'h0; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_0 = _mem_stld_forward_stq_idx_T & _mem_stld_forward_stq_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_1 = lcam_uop_0_stq_idx < 4'h2; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_1 = _mem_stld_forward_stq_idx_T_1 & _mem_stld_forward_stq_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_2 = lcam_uop_0_stq_idx < 4'h3; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_2 = _mem_stld_forward_stq_idx_T_2 & _mem_stld_forward_stq_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_3 = lcam_uop_0_stq_idx < 4'h4; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_3 = _mem_stld_forward_stq_idx_T_3 & _mem_stld_forward_stq_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_4 = lcam_uop_0_stq_idx < 4'h5; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_4 = _mem_stld_forward_stq_idx_T_4 & _mem_stld_forward_stq_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_5 = lcam_uop_0_stq_idx < 4'h6; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_5 = _mem_stld_forward_stq_idx_T_5 & _mem_stld_forward_stq_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_6 = lcam_uop_0_stq_idx < 4'h7; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_6 = _mem_stld_forward_stq_idx_T_6 & _mem_stld_forward_stq_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_7 = ~(lcam_uop_0_stq_idx[3]); // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_7 = _mem_stld_forward_stq_idx_T_7 & _mem_stld_forward_stq_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_8 = lcam_uop_0_stq_idx < 4'h9; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_8 = _mem_stld_forward_stq_idx_T_8 & _mem_stld_forward_stq_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_9 = lcam_uop_0_stq_idx < 4'hA; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_9 = _mem_stld_forward_stq_idx_T_9 & _mem_stld_forward_stq_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_10 = lcam_uop_0_stq_idx < 4'hB; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_10 = _mem_stld_forward_stq_idx_T_10 & _mem_stld_forward_stq_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_11 = lcam_uop_0_stq_idx[3:2] != 2'h3; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_11 = _mem_stld_forward_stq_idx_T_11 & _mem_stld_forward_stq_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_12 = lcam_uop_0_stq_idx < 4'hD; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_12 = _mem_stld_forward_stq_idx_T_12 & _mem_stld_forward_stq_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_13 = lcam_uop_0_stq_idx[3:1] != 3'h7; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_13 = _mem_stld_forward_stq_idx_T_13 & _mem_stld_forward_stq_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_14 = lcam_uop_0_stq_idx != 4'hF; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_14 = _mem_stld_forward_stq_idx_T_14 & _mem_stld_forward_stq_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire [4:0] _mem_stld_forward_stq_idx_idx_T = {4'hF, ~_mem_stld_forward_stq_idx_T_14}; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_1 = _mem_stld_forward_stq_idx_T_13 ? 5'h1D : _mem_stld_forward_stq_idx_idx_T; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_2 = _mem_stld_forward_stq_idx_T_12 ? 5'h1C : _mem_stld_forward_stq_idx_idx_T_1; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_3 = _mem_stld_forward_stq_idx_T_11 ? 5'h1B : _mem_stld_forward_stq_idx_idx_T_2; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_4 = _mem_stld_forward_stq_idx_T_10 ? 5'h1A : _mem_stld_forward_stq_idx_idx_T_3; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_5 = _mem_stld_forward_stq_idx_T_9 ? 5'h19 : _mem_stld_forward_stq_idx_idx_T_4; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_6 = _mem_stld_forward_stq_idx_T_8 ? 5'h18 : _mem_stld_forward_stq_idx_idx_T_5; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_7 = _mem_stld_forward_stq_idx_T_7 ? 5'h17 : _mem_stld_forward_stq_idx_idx_T_6; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_8 = _mem_stld_forward_stq_idx_T_6 ? 5'h16 : _mem_stld_forward_stq_idx_idx_T_7; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_9 = _mem_stld_forward_stq_idx_T_5 ? 5'h15 : _mem_stld_forward_stq_idx_idx_T_8; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_10 = _mem_stld_forward_stq_idx_T_4 ? 5'h14 : _mem_stld_forward_stq_idx_idx_T_9; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_11 = _mem_stld_forward_stq_idx_T_3 ? 5'h13 : _mem_stld_forward_stq_idx_idx_T_10; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_12 = _mem_stld_forward_stq_idx_T_2 ? 5'h12 : _mem_stld_forward_stq_idx_idx_T_11; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_13 = _mem_stld_forward_stq_idx_T_1 ? 5'h11 : _mem_stld_forward_stq_idx_idx_T_12; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_14 = _mem_stld_forward_stq_idx_T ? 5'h10 : _mem_stld_forward_stq_idx_idx_T_13; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_15 = mem_stld_forward_stq_idx_temp_vec_15 ? 5'hF : _mem_stld_forward_stq_idx_idx_T_14; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_16 = mem_stld_forward_stq_idx_temp_vec_14 ? 5'hE : _mem_stld_forward_stq_idx_idx_T_15; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_17 = mem_stld_forward_stq_idx_temp_vec_13 ? 5'hD : _mem_stld_forward_stq_idx_idx_T_16; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_18 = mem_stld_forward_stq_idx_temp_vec_12 ? 5'hC : _mem_stld_forward_stq_idx_idx_T_17; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_19 = mem_stld_forward_stq_idx_temp_vec_11 ? 5'hB : _mem_stld_forward_stq_idx_idx_T_18; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_20 = mem_stld_forward_stq_idx_temp_vec_10 ? 5'hA : _mem_stld_forward_stq_idx_idx_T_19; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_21 = mem_stld_forward_stq_idx_temp_vec_9 ? 5'h9 : _mem_stld_forward_stq_idx_idx_T_20; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_22 = mem_stld_forward_stq_idx_temp_vec_8 ? 5'h8 : _mem_stld_forward_stq_idx_idx_T_21; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_23 = mem_stld_forward_stq_idx_temp_vec_7 ? 5'h7 : _mem_stld_forward_stq_idx_idx_T_22; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_24 = mem_stld_forward_stq_idx_temp_vec_6 ? 5'h6 : _mem_stld_forward_stq_idx_idx_T_23; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_25 = mem_stld_forward_stq_idx_temp_vec_5 ? 5'h5 : _mem_stld_forward_stq_idx_idx_T_24; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_26 = mem_stld_forward_stq_idx_temp_vec_4 ? 5'h4 : _mem_stld_forward_stq_idx_idx_T_25; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_27 = mem_stld_forward_stq_idx_temp_vec_3 ? 5'h3 : _mem_stld_forward_stq_idx_idx_T_26; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_28 = mem_stld_forward_stq_idx_temp_vec_2 ? 5'h2 : _mem_stld_forward_stq_idx_idx_T_27; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_29 = mem_stld_forward_stq_idx_temp_vec_1 ? 5'h1 : _mem_stld_forward_stq_idx_idx_T_28; // @[Mux.scala:50:70] wire [4:0] mem_stld_forward_stq_idx_idx = mem_stld_forward_stq_idx_temp_vec_0 ? 5'h0 : _mem_stld_forward_stq_idx_idx_T_29; // @[Mux.scala:50:70] wire [3:0] _mem_stld_forward_stq_idx_T_16 = mem_stld_forward_stq_idx_idx[3:0]; // @[Mux.scala:50:70] wire [3:0] mem_stld_forward_stq_idx_0 = _mem_stld_forward_stq_idx_T_16; // @[util.scala:354:8] wire [15:0] _mem_stld_forward_valid_T = stld_prs2_matches_0 >> mem_stld_forward_stq_idx_0; // @[lsu.scala:321:49, :1166:34, :1413:87] wire _mem_stld_forward_valid_T_1 = _mem_stld_forward_valid_T[0]; // @[lsu.scala:1413:87] wire _mem_stld_forward_valid_T_2 = do_ld_search_0 & _mem_stld_forward_valid_T_1; // @[lsu.scala:321:49, :1413:{64,87}] wire mem_stld_forward_valid_0 = _mem_stld_forward_valid_T_2; // @[lsu.scala:321:49, :1413:64] reg io_core_clr_unsafe_0_valid_REG; // @[lsu.scala:1421:14] wire _io_core_clr_unsafe_0_valid_T = ~io_dmem_nack_0_valid_0; // @[lsu.scala:211:7, :1422:8] wire _io_core_clr_unsafe_0_valid_T_1 = ~fired_load_agen_0; // @[lsu.scala:321:49, :1422:61] wire _io_core_clr_unsafe_0_valid_T_2 = do_ld_search_0 & _io_core_clr_unsafe_0_valid_T_1; // @[lsu.scala:321:49, :1422:{58,61}] wire _io_core_clr_unsafe_0_valid_T_3 = ~io_dmem_s1_kill_0_0; // @[lsu.scala:211:7, :1422:84] wire _io_core_clr_unsafe_0_valid_T_4 = _io_core_clr_unsafe_0_valid_T_2 & _io_core_clr_unsafe_0_valid_T_3; // @[lsu.scala:1422:{58,81,84}] reg io_core_clr_unsafe_0_valid_REG_1; // @[lsu.scala:1422:114] wire _io_core_clr_unsafe_0_valid_T_5 = _io_core_clr_unsafe_0_valid_T_4 & io_core_clr_unsafe_0_valid_REG_1; // @[lsu.scala:1422:{81,104,114}] reg io_core_clr_unsafe_0_valid_REG_2; // @[lsu.scala:1422:41] wire _io_core_clr_unsafe_0_valid_T_6 = _io_core_clr_unsafe_0_valid_T & io_core_clr_unsafe_0_valid_REG_2; // @[lsu.scala:1422:{8,31,41}] wire _io_core_clr_unsafe_0_valid_T_7 = io_core_clr_unsafe_0_valid_REG \| _io_core_clr_unsafe_0_valid_T_6; // @[lsu.scala:1421:{14,32}, :1422:31] reg io_core_clr_unsafe_0_valid_REG_3; // @[lsu.scala:1423:18] wire _io_core_clr_unsafe_0_valid_T_8 = ~io_core_clr_unsafe_0_valid_REG_3; // @[lsu.scala:1423:{10,18}] assign _io_core_clr_unsafe_0_valid_T_9 = _io_core_clr_unsafe_0_valid_T_7 & _io_core_clr_unsafe_0_valid_T_8; // @[lsu.scala:1421:32, :1423:{7,10}] assign io_core_clr_unsafe_0_valid_0 = _io_core_clr_unsafe_0_valid_T_9; // @[lsu.scala:211:7, :1423:7] reg [5:0] io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:1424:43] assign io_core_clr_unsafe_0_bits_0 = io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:211:7, :1424:43] wire _l_idx_T = ldq_valid_0 & ldq_order_fail_0; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_1 = ldq_valid_1 & ldq_order_fail_1; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_2 = ldq_valid_2 & ldq_order_fail_2; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_3 = ldq_valid_3 & ldq_order_fail_3; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_4 = ldq_valid_4 & ldq_order_fail_4; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_5 = ldq_valid_5 & ldq_order_fail_5; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_6 = ldq_valid_6 & ldq_order_fail_6; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_7 = ldq_valid_7 & ldq_order_fail_7; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_8 = ldq_valid_8 & ldq_order_fail_8; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_9 = ldq_valid_9 & ldq_order_fail_9; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_10 = ldq_valid_10 & ldq_order_fail_10; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_11 = ldq_valid_11 & ldq_order_fail_11; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_12 = ldq_valid_12 & ldq_order_fail_12; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_13 = ldq_valid_13 & ldq_order_fail_13; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_14 = ldq_valid_14 & ldq_order_fail_14; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_15 = ldq_valid_15 & ldq_order_fail_15; // @[lsu.scala:218:36, :225:36, :1429:82] wire l_idx_temp_vec_15 = _l_idx_T_15; // @[util.scala:352:65] wire l_idx_temp_vec_0 = _l_idx_T & _l_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_1 = _l_idx_T_1 & _l_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_2 = _l_idx_T_2 & _l_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_3 = _l_idx_T_3 & _l_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_4 = _l_idx_T_4 & _l_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_5 = _l_idx_T_5 & _l_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_6 = _l_idx_T_6 & _l_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _l_idx_temp_vec_T_7 = ~(ldq_head[3]); // @[util.scala:352:72] wire l_idx_temp_vec_7 = _l_idx_T_7 & _l_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_8 = _l_idx_T_8 & _l_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_9 = _l_idx_T_9 & _l_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_10 = _l_idx_T_10 & _l_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_11 = _l_idx_T_11 & _l_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_12 = _l_idx_T_12 & _l_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_13 = _l_idx_T_13 & _l_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_14 = _l_idx_T_14 & _l_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire [4:0] _l_idx_idx_T = {4'hF, ~_l_idx_T_14}; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_1 = _l_idx_T_13 ? 5'h1D : _l_idx_idx_T; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_2 = _l_idx_T_12 ? 5'h1C : _l_idx_idx_T_1; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_3 = _l_idx_T_11 ? 5'h1B : _l_idx_idx_T_2; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_4 = _l_idx_T_10 ? 5'h1A : _l_idx_idx_T_3; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_5 = _l_idx_T_9 ? 5'h19 : _l_idx_idx_T_4; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_6 = _l_idx_T_8 ? 5'h18 : _l_idx_idx_T_5; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_7 = _l_idx_T_7 ? 5'h17 : _l_idx_idx_T_6; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_8 = _l_idx_T_6 ? 5'h16 : _l_idx_idx_T_7; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_9 = _l_idx_T_5 ? 5'h15 : _l_idx_idx_T_8; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_10 = _l_idx_T_4 ? 5'h14 : _l_idx_idx_T_9; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_11 = _l_idx_T_3 ? 5'h13 : _l_idx_idx_T_10; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_12 = _l_idx_T_2 ? 5'h12 : _l_idx_idx_T_11; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_13 = _l_idx_T_1 ? 5'h11 : _l_idx_idx_T_12; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_14 = _l_idx_T ? 5'h10 : _l_idx_idx_T_13; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_15 = l_idx_temp_vec_15 ? 5'hF : _l_idx_idx_T_14; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_16 = l_idx_temp_vec_14 ? 5'hE : _l_idx_idx_T_15; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_17 = l_idx_temp_vec_13 ? 5'hD : _l_idx_idx_T_16; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_18 = l_idx_temp_vec_12 ? 5'hC : _l_idx_idx_T_17; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_19 = l_idx_temp_vec_11 ? 5'hB : _l_idx_idx_T_18; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_20 = l_idx_temp_vec_10 ? 5'hA : _l_idx_idx_T_19; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_21 = l_idx_temp_vec_9 ? 5'h9 : _l_idx_idx_T_20; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_22 = l_idx_temp_vec_8 ? 5'h8 : _l_idx_idx_T_21; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_23 = l_idx_temp_vec_7 ? 5'h7 : _l_idx_idx_T_22; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_24 = l_idx_temp_vec_6 ? 5'h6 : _l_idx_idx_T_23; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_25 = l_idx_temp_vec_5 ? 5'h5 : _l_idx_idx_T_24; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_26 = l_idx_temp_vec_4 ? 5'h4 : _l_idx_idx_T_25; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_27 = l_idx_temp_vec_3 ? 5'h3 : _l_idx_idx_T_26; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_28 = l_idx_temp_vec_2 ? 5'h2 : _l_idx_idx_T_27; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_29 = l_idx_temp_vec_1 ? 5'h1 : _l_idx_idx_T_28; // @[Mux.scala:50:70] wire [4:0] l_idx_idx = l_idx_temp_vec_0 ? 5'h0 : _l_idx_idx_T_29; // @[Mux.scala:50:70] wire [3:0] l_idx = l_idx_idx[3:0]; // @[Mux.scala:50:70] reg r_xcpt_valid; // @[lsu.scala:1434:29] reg [31:0] r_xcpt_uop_inst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_inst_0 = r_xcpt_uop_inst; // @[lsu.scala:211:7, :1435:25] reg [31:0] r_xcpt_uop_debug_inst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_inst_0 = r_xcpt_uop_debug_inst; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_rvc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_rvc_0 = r_xcpt_uop_is_rvc; // @[lsu.scala:211:7, :1435:25] reg [39:0] r_xcpt_uop_debug_pc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_pc_0 = r_xcpt_uop_debug_pc; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_0; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_0_0 = r_xcpt_uop_iq_type_0; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_1_0 = r_xcpt_uop_iq_type_1; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_2_0 = r_xcpt_uop_iq_type_2; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_3_0 = r_xcpt_uop_iq_type_3; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_0; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_0_0 = r_xcpt_uop_fu_code_0; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_1_0 = r_xcpt_uop_fu_code_1; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_2_0 = r_xcpt_uop_fu_code_2; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_3_0 = r_xcpt_uop_fu_code_3; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_4; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_4_0 = r_xcpt_uop_fu_code_4; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_5; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_5_0 = r_xcpt_uop_fu_code_5; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_6; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_6_0 = r_xcpt_uop_fu_code_6; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_7; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_7_0 = r_xcpt_uop_fu_code_7; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_8; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_8_0 = r_xcpt_uop_fu_code_8; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_9; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_9_0 = r_xcpt_uop_fu_code_9; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_issued; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_issued_0 = r_xcpt_uop_iw_issued; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_issued_partial_agen_0 = r_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_issued_partial_dgen_0 = r_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p1_speculative_child_0 = r_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p2_speculative_child_0 = r_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p1_bypass_hint_0 = r_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p2_bypass_hint_0 = r_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p3_bypass_hint_0 = r_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_dis_col_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_dis_col_sel_0 = r_xcpt_uop_dis_col_sel; // @[lsu.scala:211:7, :1435:25] reg [11:0] r_xcpt_uop_br_mask; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_br_mask_0 = r_xcpt_uop_br_mask; // @[lsu.scala:211:7, :1435:25] reg [3:0] r_xcpt_uop_br_tag; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_br_tag_0 = r_xcpt_uop_br_tag; // @[lsu.scala:211:7, :1435:25] reg [3:0] r_xcpt_uop_br_type; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_br_type_0 = r_xcpt_uop_br_type; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_sfb; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_sfb_0 = r_xcpt_uop_is_sfb; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_fence; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_fence_0 = r_xcpt_uop_is_fence; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_fencei; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_fencei_0 = r_xcpt_uop_is_fencei; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_sfence; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_sfence_0 = r_xcpt_uop_is_sfence; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_amo; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_amo_0 = r_xcpt_uop_is_amo; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_eret; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_eret_0 = r_xcpt_uop_is_eret; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_sys_pc2epc_0 = r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_rocc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_rocc_0 = r_xcpt_uop_is_rocc; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_mov; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_mov_0 = r_xcpt_uop_is_mov; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_ftq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ftq_idx_0 = r_xcpt_uop_ftq_idx; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_edge_inst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_edge_inst_0 = r_xcpt_uop_edge_inst; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_pc_lob; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_pc_lob_0 = r_xcpt_uop_pc_lob; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_taken; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_taken_0 = r_xcpt_uop_taken; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_imm_rename; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_imm_rename_0 = r_xcpt_uop_imm_rename; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_imm_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_imm_sel_0 = r_xcpt_uop_imm_sel; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_pimm; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_pimm_0 = r_xcpt_uop_pimm; // @[lsu.scala:211:7, :1435:25] reg [19:0] r_xcpt_uop_imm_packed; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_imm_packed_0 = r_xcpt_uop_imm_packed; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_op1_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_op1_sel_0 = r_xcpt_uop_op1_sel; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_op2_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_op2_sel_0 = r_xcpt_uop_op2_sel; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ldst_0 = r_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_wen_0 = r_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ren1_0 = r_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ren2_0 = r_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ren3_0 = r_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_swap12_0 = r_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_swap23_0 = r_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn_0 = r_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut_0 = r_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_fromint_0 = r_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_toint_0 = r_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_fastpipe_0 = r_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_fma_0 = r_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_div; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_div_0 = r_xcpt_uop_fp_ctrl_div; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_sqrt_0 = r_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_wflags_0 = r_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_vec_0 = r_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_rob_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_rob_idx_0 = r_xcpt_uop_rob_idx; // @[lsu.scala:211:7, :1435:25] reg [3:0] r_xcpt_uop_ldq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ldq_idx_0 = r_xcpt_uop_ldq_idx; // @[lsu.scala:211:7, :1435:25] reg [3:0] r_xcpt_uop_stq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_stq_idx_0 = r_xcpt_uop_stq_idx; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_rxq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_rxq_idx_0 = r_xcpt_uop_rxq_idx; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_pdst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_pdst_0 = r_xcpt_uop_pdst; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_prs1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs1_0 = r_xcpt_uop_prs1; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_prs2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs2_0 = r_xcpt_uop_prs2; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_prs3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs3_0 = r_xcpt_uop_prs3; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_ppred; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ppred_0 = r_xcpt_uop_ppred; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_prs1_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs1_busy_0 = r_xcpt_uop_prs1_busy; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_prs2_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs2_busy_0 = r_xcpt_uop_prs2_busy; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_prs3_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs3_busy_0 = r_xcpt_uop_prs3_busy; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_ppred_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ppred_busy_0 = r_xcpt_uop_ppred_busy; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_stale_pdst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_stale_pdst_0 = r_xcpt_uop_stale_pdst; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_exception; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_exception_0 = r_xcpt_uop_exception; // @[lsu.scala:211:7, :1435:25] reg [63:0] r_xcpt_uop_exc_cause; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_exc_cause_0 = r_xcpt_uop_exc_cause; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_mem_cmd; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_mem_cmd_0 = r_xcpt_uop_mem_cmd; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_mem_size; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_mem_size_0 = r_xcpt_uop_mem_size; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_mem_signed; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_mem_signed_0 = r_xcpt_uop_mem_signed; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_uses_ldq; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_uses_ldq_0 = r_xcpt_uop_uses_ldq; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_uses_stq; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_uses_stq_0 = r_xcpt_uop_uses_stq; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_unique; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_unique_0 = r_xcpt_uop_is_unique; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_flush_on_commit; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_flush_on_commit_0 = r_xcpt_uop_flush_on_commit; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_csr_cmd; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_csr_cmd_0 = r_xcpt_uop_csr_cmd; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ldst_is_rs1_0 = r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_ldst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ldst_0 = r_xcpt_uop_ldst; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_lrs1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs1_0 = r_xcpt_uop_lrs1; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_lrs2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs2_0 = r_xcpt_uop_lrs2; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_lrs3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs3_0 = r_xcpt_uop_lrs3; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_dst_rtype; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_dst_rtype_0 = r_xcpt_uop_dst_rtype; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_lrs1_rtype; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs1_rtype_0 = r_xcpt_uop_lrs1_rtype; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_lrs2_rtype; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs2_rtype_0 = r_xcpt_uop_lrs2_rtype; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_frs3_en; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_frs3_en_0 = r_xcpt_uop_frs3_en; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fcn_dw; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fcn_dw_0 = r_xcpt_uop_fcn_dw; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_fcn_op; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fcn_op_0 = r_xcpt_uop_fcn_op; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_val; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_val_0 = r_xcpt_uop_fp_val; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_fp_rm; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_rm_0 = r_xcpt_uop_fp_rm; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_fp_typ; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_typ_0 = r_xcpt_uop_fp_typ; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_xcpt_pf_if_0 = r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_xcpt_ae_if_0 = r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_xcpt_ma_if_0 = r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_bp_debug_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_bp_debug_if_0 = r_xcpt_uop_bp_debug_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_bp_xcpt_if_0 = r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_debug_fsrc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_fsrc_0 = r_xcpt_uop_debug_fsrc; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_debug_tsrc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_tsrc_0 = r_xcpt_uop_debug_tsrc; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_cause; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_cause_0 = r_xcpt_cause; // @[lsu.scala:211:7, :1435:25] reg [39:0] r_xcpt_badvaddr; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_badvaddr_0 = r_xcpt_badvaddr; // @[lsu.scala:211:7, :1435:25] wire [1:0] ld_xcpt_valid_lo_lo_lo = {ldq_order_fail_1, ldq_order_fail_0}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_lo_lo_hi = {ldq_order_fail_3, ldq_order_fail_2}; // @[lsu.scala:225:36, :1437:39] wire [3:0] ld_xcpt_valid_lo_lo = {ld_xcpt_valid_lo_lo_hi, ld_xcpt_valid_lo_lo_lo}; // @[lsu.scala:1437:39] wire [1:0] ld_xcpt_valid_lo_hi_lo = {ldq_order_fail_5, ldq_order_fail_4}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_lo_hi_hi = {ldq_order_fail_7, ldq_order_fail_6}; // @[lsu.scala:225:36, :1437:39] wire [3:0] ld_xcpt_valid_lo_hi = {ld_xcpt_valid_lo_hi_hi, ld_xcpt_valid_lo_hi_lo}; // @[lsu.scala:1437:39] wire [7:0] ld_xcpt_valid_lo = {ld_xcpt_valid_lo_hi, ld_xcpt_valid_lo_lo}; // @[lsu.scala:1437:39] wire [1:0] ld_xcpt_valid_hi_lo_lo = {ldq_order_fail_9, ldq_order_fail_8}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_hi_lo_hi = {ldq_order_fail_11, ldq_order_fail_10}; // @[lsu.scala:225:36, :1437:39] wire [3:0] ld_xcpt_valid_hi_lo = {ld_xcpt_valid_hi_lo_hi, ld_xcpt_valid_hi_lo_lo}; // @[lsu.scala:1437:39] wire [1:0] ld_xcpt_valid_hi_hi_lo = {ldq_order_fail_13, ldq_order_fail_12}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_hi_hi_hi = {ldq_order_fail_15, ldq_order_fail_14}; // @[lsu.scala:225:36, :1437:39] wire [3:0] ld_xcpt_valid_hi_hi = {ld_xcpt_valid_hi_hi_hi, ld_xcpt_valid_hi_hi_lo}; // @[lsu.scala:1437:39] wire [7:0] ld_xcpt_valid_hi = {ld_xcpt_valid_hi_hi, ld_xcpt_valid_hi_lo}; // @[lsu.scala:1437:39] wire [15:0] _ld_xcpt_valid_T = {ld_xcpt_valid_hi, ld_xcpt_valid_lo}; // @[lsu.scala:1437:39] wire [3:0] ld_xcpt_valid_lo_lo_1 = {ld_xcpt_valid_lo_lo_hi_1, ld_xcpt_valid_lo_lo_lo_1}; // @[lsu.scala:1437:58] wire [3:0] ld_xcpt_valid_lo_hi_1 = {ld_xcpt_valid_lo_hi_hi_1, ld_xcpt_valid_lo_hi_lo_1}; // @[lsu.scala:1437:58] wire [7:0] ld_xcpt_valid_lo_1 = {ld_xcpt_valid_lo_hi_1, ld_xcpt_valid_lo_lo_1}; // @[lsu.scala:1437:58] wire [3:0] ld_xcpt_valid_hi_lo_1 = {ld_xcpt_valid_hi_lo_hi_1, ld_xcpt_valid_hi_lo_lo_1}; // @[lsu.scala:1437:58] wire [3:0] ld_xcpt_valid_hi_hi_1 = {ld_xcpt_valid_hi_hi_hi_1, ld_xcpt_valid_hi_hi_lo_1}; // @[lsu.scala:1437:58] wire [7:0] ld_xcpt_valid_hi_1 = {ld_xcpt_valid_hi_hi_1, ld_xcpt_valid_hi_lo_1}; // @[lsu.scala:1437:58] wire [15:0] _ld_xcpt_valid_T_1 = {ld_xcpt_valid_hi_1, ld_xcpt_valid_lo_1}; // @[lsu.scala:1437:58] wire [15:0] _ld_xcpt_valid_T_2 = _ld_xcpt_valid_T & _ld_xcpt_valid_T_1; // @[lsu.scala:1437:{39,46,58}] wire ld_xcpt_valid = \|_ld_xcpt_valid_T_2; // @[lsu.scala:1437:{46,66}] wire [5:0] _ld_xcpt_uop_T_1 = {2'h0, l_idx} - 6'h10; // @[util.scala:354:8] wire [4:0] _ld_xcpt_uop_T_2 = _ld_xcpt_uop_T_1[4:0]; // @[lsu.scala:1438:76] wire [4:0] _ld_xcpt_uop_T_3 = {1'h0, l_idx}; // @[util.scala:354:8] wire [3:0] _ld_xcpt_uop_T_4 = _ld_xcpt_uop_T_3[3:0]; // @[lsu.scala:1438:43] wire ld_xcpt_uop_iq_type_0; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iq_type_1; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iq_type_2; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iq_type_3; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_0; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_1; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_2; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_3; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_4; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_5; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_6; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_7; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_8; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_9; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_div; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:1438:31] wire [31:0] ld_xcpt_uop_inst; // @[lsu.scala:1438:31] wire [31:0] ld_xcpt_uop_debug_inst; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_rvc; // @[lsu.scala:1438:31] wire [39:0] ld_xcpt_uop_debug_pc; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_issued; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_dis_col_sel; // @[lsu.scala:1438:31] wire [11:0] ld_xcpt_uop_br_mask; // @[lsu.scala:1438:31] wire [3:0] ld_xcpt_uop_br_tag; // @[lsu.scala:1438:31] wire [3:0] ld_xcpt_uop_br_type; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_sfb; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_fence; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_fencei; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_sfence; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_amo; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_eret; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_rocc; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_mov; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_ftq_idx; // @[lsu.scala:1438:31] wire ld_xcpt_uop_edge_inst; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_pc_lob; // @[lsu.scala:1438:31] wire ld_xcpt_uop_taken; // @[lsu.scala:1438:31] wire ld_xcpt_uop_imm_rename; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_imm_sel; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_pimm; // @[lsu.scala:1438:31] wire [19:0] ld_xcpt_uop_imm_packed; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_op1_sel; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_op2_sel; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_rob_idx; // @[lsu.scala:1438:31] wire [3:0] ld_xcpt_uop_ldq_idx; // @[lsu.scala:1438:31] wire [3:0] ld_xcpt_uop_stq_idx; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_rxq_idx; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_pdst; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_prs1; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_prs2; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_prs3; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_ppred; // @[lsu.scala:1438:31] wire ld_xcpt_uop_prs1_busy; // @[lsu.scala:1438:31] wire ld_xcpt_uop_prs2_busy; // @[lsu.scala:1438:31] wire ld_xcpt_uop_prs3_busy; // @[lsu.scala:1438:31] wire ld_xcpt_uop_ppred_busy; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_stale_pdst; // @[lsu.scala:1438:31] wire ld_xcpt_uop_exception; // @[lsu.scala:1438:31] wire [63:0] ld_xcpt_uop_exc_cause; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_mem_cmd; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_mem_size; // @[lsu.scala:1438:31] wire ld_xcpt_uop_mem_signed; // @[lsu.scala:1438:31] wire ld_xcpt_uop_uses_ldq; // @[lsu.scala:1438:31] wire ld_xcpt_uop_uses_stq; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_unique; // @[lsu.scala:1438:31] wire ld_xcpt_uop_flush_on_commit; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_csr_cmd; // @[lsu.scala:1438:31] wire ld_xcpt_uop_ldst_is_rs1; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_ldst; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_lrs1; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_lrs2; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_lrs3; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_dst_rtype; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_lrs1_rtype; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_lrs2_rtype; // @[lsu.scala:1438:31] wire ld_xcpt_uop_frs3_en; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fcn_dw; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_fcn_op; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_val; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_fp_rm; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_fp_typ; // @[lsu.scala:1438:31] wire ld_xcpt_uop_xcpt_pf_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_xcpt_ae_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_xcpt_ma_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_bp_debug_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_bp_xcpt_if; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_debug_fsrc; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_debug_tsrc; // @[lsu.scala:1438:31] assign ld_xcpt_uop_inst = _GEN_76[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_debug_inst = _GEN_77[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_rvc = _GEN_78[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_debug_pc = _GEN_79[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iq_type_0 = _GEN_80[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iq_type_1 = _GEN_81[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iq_type_2 = _GEN_82[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iq_type_3 = _GEN_83[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_0 = _GEN_84[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_1 = _GEN_85[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_2 = _GEN_86[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_3 = _GEN_87[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_4 = _GEN_88[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_5 = _GEN_89[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_6 = _GEN_90[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_7 = _GEN_91[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_8 = _GEN_92[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_9 = _GEN_93[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_issued = _GEN_94[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_issued_partial_agen = _GEN_95[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_issued_partial_dgen = _GEN_96[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_p1_speculative_child = _GEN_97[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_p2_speculative_child = _GEN_98[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_p1_bypass_hint = _GEN_99[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_p2_bypass_hint = _GEN_100[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_p3_bypass_hint = _GEN_101[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_dis_col_sel = _GEN_102[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_br_mask = _GEN_103[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_br_tag = _GEN_104[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_br_type = _GEN_105[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_sfb = _GEN_106[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_fence = _GEN_107[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_fencei = _GEN_108[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_sfence = _GEN_109[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_amo = _GEN_110[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_eret = _GEN_111[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_sys_pc2epc = _GEN_112[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_rocc = _GEN_113[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_mov = _GEN_114[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_ftq_idx = _GEN_115[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_edge_inst = _GEN_116[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_pc_lob = _GEN_117[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_taken = _GEN_118[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_imm_rename = _GEN_119[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_imm_sel = _GEN_120[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_pimm = _GEN_121[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_imm_packed = _GEN_122[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_op1_sel = _GEN_123[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_op2_sel = _GEN_124[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_ldst = _GEN_125[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_wen = _GEN_126[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_ren1 = _GEN_127[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_ren2 = _GEN_128[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_ren3 = _GEN_129[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_swap12 = _GEN_130[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_swap23 = _GEN_131[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_typeTagIn = _GEN_132[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_typeTagOut = _GEN_133[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_fromint = _GEN_134[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_toint = _GEN_135[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_fastpipe = _GEN_136[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_fma = _GEN_137[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_div = _GEN_138[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_sqrt = _GEN_139[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_wflags = _GEN_140[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_vec = _GEN_141[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_rob_idx = _GEN_142[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_ldq_idx = _GEN_143[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_stq_idx = _GEN_144[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_rxq_idx = _GEN_145[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_pdst = _GEN_146[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_prs1 = _GEN_147[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_prs2 = _GEN_148[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_prs3 = _GEN_149[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_ppred = _GEN_150[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_prs1_busy = _GEN_151[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_prs2_busy = _GEN_152[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_prs3_busy = _GEN_153[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_ppred_busy = _GEN_154[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_stale_pdst = _GEN_155[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_exception = _GEN_156[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_exc_cause = _GEN_157[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_mem_cmd = _GEN_158[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_mem_size = _GEN_159[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_mem_signed = _GEN_160[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_uses_ldq = _GEN_161[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_uses_stq = _GEN_162[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_unique = _GEN_163[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_flush_on_commit = _GEN_164[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_csr_cmd = _GEN_165[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_ldst_is_rs1 = _GEN_166[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_ldst = _GEN_167[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_lrs1 = _GEN_168[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_lrs2 = _GEN_169[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_lrs3 = _GEN_170[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_dst_rtype = _GEN_171[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_lrs1_rtype = _GEN_172[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_lrs2_rtype = _GEN_173[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_frs3_en = _GEN_174[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fcn_dw = _GEN_175[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fcn_op = _GEN_176[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_val = _GEN_177[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_rm = _GEN_178[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_typ = _GEN_179[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_xcpt_pf_if = _GEN_180[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_xcpt_ae_if = _GEN_181[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_xcpt_ma_if = _GEN_182[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_bp_debug_if = _GEN_183[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_bp_xcpt_if = _GEN_184[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_debug_fsrc = _GEN_185[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_debug_tsrc = _GEN_186[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] wire _use_mem_xcpt_T = mem_xcpt_uop_rob_idx < ld_xcpt_uop_rob_idx; // @[util.scala:364:52] wire _use_mem_xcpt_T_1 = mem_xcpt_uop_rob_idx < io_core_rob_head_idx_0; // @[util.scala:364:64] wire _use_mem_xcpt_T_2 = _use_mem_xcpt_T ^ _use_mem_xcpt_T_1; // @[util.scala:364:{52,58,64}] wire _use_mem_xcpt_T_3 = ld_xcpt_uop_rob_idx < io_core_rob_head_idx_0; // @[util.scala:364:78] wire _use_mem_xcpt_T_4 = _use_mem_xcpt_T_2 ^ _use_mem_xcpt_T_3; // @[util.scala:364:{58,72,78}] wire _use_mem_xcpt_T_5 = mem_xcpt_valid & _use_mem_xcpt_T_4; // @[util.scala:364:72] wire _use_mem_xcpt_T_6 = ~ld_xcpt_valid; // @[lsu.scala:1437:66, :1440:118] wire use_mem_xcpt = _use_mem_xcpt_T_5 \| _use_mem_xcpt_T_6; // @[lsu.scala:1440:{38,115,118}] wire [31:0] xcpt_uop_inst = use_mem_xcpt ? mem_xcpt_uop_inst : ld_xcpt_uop_inst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [31:0] xcpt_uop_debug_inst = use_mem_xcpt ? mem_xcpt_uop_debug_inst : ld_xcpt_uop_debug_inst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_rvc = use_mem_xcpt ? mem_xcpt_uop_is_rvc : ld_xcpt_uop_is_rvc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [39:0] xcpt_uop_debug_pc = use_mem_xcpt ? mem_xcpt_uop_debug_pc : ld_xcpt_uop_debug_pc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_0 = use_mem_xcpt ? mem_xcpt_uop_iq_type_0 : ld_xcpt_uop_iq_type_0; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_1 = use_mem_xcpt ? mem_xcpt_uop_iq_type_1 : ld_xcpt_uop_iq_type_1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_2 = use_mem_xcpt ? mem_xcpt_uop_iq_type_2 : ld_xcpt_uop_iq_type_2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_3 = use_mem_xcpt ? mem_xcpt_uop_iq_type_3 : ld_xcpt_uop_iq_type_3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_0 = use_mem_xcpt ? mem_xcpt_uop_fu_code_0 : ld_xcpt_uop_fu_code_0; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_1 = use_mem_xcpt ? mem_xcpt_uop_fu_code_1 : ld_xcpt_uop_fu_code_1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_2 = use_mem_xcpt ? mem_xcpt_uop_fu_code_2 : ld_xcpt_uop_fu_code_2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_3 = use_mem_xcpt ? mem_xcpt_uop_fu_code_3 : ld_xcpt_uop_fu_code_3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_4 = use_mem_xcpt ? mem_xcpt_uop_fu_code_4 : ld_xcpt_uop_fu_code_4; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_5 = use_mem_xcpt ? mem_xcpt_uop_fu_code_5 : ld_xcpt_uop_fu_code_5; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_6 = use_mem_xcpt ? mem_xcpt_uop_fu_code_6 : ld_xcpt_uop_fu_code_6; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_7 = use_mem_xcpt ? mem_xcpt_uop_fu_code_7 : ld_xcpt_uop_fu_code_7; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_8 = use_mem_xcpt ? mem_xcpt_uop_fu_code_8 : ld_xcpt_uop_fu_code_8; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_9 = use_mem_xcpt ? mem_xcpt_uop_fu_code_9 : ld_xcpt_uop_fu_code_9; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_issued = use_mem_xcpt ? mem_xcpt_uop_iw_issued : ld_xcpt_uop_iw_issued; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_issued_partial_agen = use_mem_xcpt ? mem_xcpt_uop_iw_issued_partial_agen : ld_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_issued_partial_dgen = use_mem_xcpt ? mem_xcpt_uop_iw_issued_partial_dgen : ld_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_iw_p1_speculative_child = use_mem_xcpt ? mem_xcpt_uop_iw_p1_speculative_child : ld_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_iw_p2_speculative_child = use_mem_xcpt ? mem_xcpt_uop_iw_p2_speculative_child : ld_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_p1_bypass_hint = use_mem_xcpt ? mem_xcpt_uop_iw_p1_bypass_hint : ld_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_p2_bypass_hint = use_mem_xcpt ? mem_xcpt_uop_iw_p2_bypass_hint : ld_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_p3_bypass_hint = use_mem_xcpt ? mem_xcpt_uop_iw_p3_bypass_hint : ld_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_dis_col_sel = use_mem_xcpt ? mem_xcpt_uop_dis_col_sel : ld_xcpt_uop_dis_col_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [11:0] xcpt_uop_br_mask = use_mem_xcpt ? mem_xcpt_uop_br_mask : ld_xcpt_uop_br_mask; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [3:0] xcpt_uop_br_tag = use_mem_xcpt ? mem_xcpt_uop_br_tag : ld_xcpt_uop_br_tag; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [3:0] xcpt_uop_br_type = use_mem_xcpt ? mem_xcpt_uop_br_type : ld_xcpt_uop_br_type; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_sfb = use_mem_xcpt ? mem_xcpt_uop_is_sfb : ld_xcpt_uop_is_sfb; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_fence = use_mem_xcpt ? mem_xcpt_uop_is_fence : ld_xcpt_uop_is_fence; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_fencei = use_mem_xcpt ? mem_xcpt_uop_is_fencei : ld_xcpt_uop_is_fencei; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_sfence = use_mem_xcpt ? mem_xcpt_uop_is_sfence : ld_xcpt_uop_is_sfence; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_amo = use_mem_xcpt ? mem_xcpt_uop_is_amo : ld_xcpt_uop_is_amo; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_eret = use_mem_xcpt ? mem_xcpt_uop_is_eret : ld_xcpt_uop_is_eret; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_sys_pc2epc = use_mem_xcpt ? mem_xcpt_uop_is_sys_pc2epc : ld_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_rocc = use_mem_xcpt ? mem_xcpt_uop_is_rocc : ld_xcpt_uop_is_rocc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_mov = use_mem_xcpt ? mem_xcpt_uop_is_mov : ld_xcpt_uop_is_mov; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_ftq_idx = use_mem_xcpt ? mem_xcpt_uop_ftq_idx : ld_xcpt_uop_ftq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_edge_inst = use_mem_xcpt ? mem_xcpt_uop_edge_inst : ld_xcpt_uop_edge_inst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_pc_lob = use_mem_xcpt ? mem_xcpt_uop_pc_lob : ld_xcpt_uop_pc_lob; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_taken = use_mem_xcpt ? mem_xcpt_uop_taken : ld_xcpt_uop_taken; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_imm_rename = use_mem_xcpt ? mem_xcpt_uop_imm_rename : ld_xcpt_uop_imm_rename; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_imm_sel = use_mem_xcpt ? mem_xcpt_uop_imm_sel : ld_xcpt_uop_imm_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_pimm = use_mem_xcpt ? mem_xcpt_uop_pimm : ld_xcpt_uop_pimm; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [19:0] xcpt_uop_imm_packed = use_mem_xcpt ? mem_xcpt_uop_imm_packed : ld_xcpt_uop_imm_packed; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_op1_sel = use_mem_xcpt ? mem_xcpt_uop_op1_sel : ld_xcpt_uop_op1_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_op2_sel = use_mem_xcpt ? mem_xcpt_uop_op2_sel : ld_xcpt_uop_op2_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ldst = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ldst : ld_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_wen = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_wen : ld_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ren1 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ren1 : ld_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ren2 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ren2 : ld_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ren3 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ren3 : ld_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_swap12 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_swap12 : ld_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_swap23 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_swap23 : ld_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_fp_ctrl_typeTagIn = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_typeTagIn : ld_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_fp_ctrl_typeTagOut = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_typeTagOut : ld_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_fromint = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_fromint : ld_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_toint = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_toint : ld_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_fastpipe = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_fastpipe : ld_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_fma = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_fma : ld_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_div = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_div : ld_xcpt_uop_fp_ctrl_div; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_sqrt = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_sqrt : ld_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_wflags = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_wflags : ld_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_vec = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_vec : ld_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_rob_idx = use_mem_xcpt ? mem_xcpt_uop_rob_idx : ld_xcpt_uop_rob_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [3:0] xcpt_uop_ldq_idx = use_mem_xcpt ? mem_xcpt_uop_ldq_idx : ld_xcpt_uop_ldq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [3:0] xcpt_uop_stq_idx = use_mem_xcpt ? mem_xcpt_uop_stq_idx : ld_xcpt_uop_stq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_rxq_idx = use_mem_xcpt ? mem_xcpt_uop_rxq_idx : ld_xcpt_uop_rxq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_pdst = use_mem_xcpt ? mem_xcpt_uop_pdst : ld_xcpt_uop_pdst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_prs1 = use_mem_xcpt ? mem_xcpt_uop_prs1 : ld_xcpt_uop_prs1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_prs2 = use_mem_xcpt ? mem_xcpt_uop_prs2 : ld_xcpt_uop_prs2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_prs3 = use_mem_xcpt ? mem_xcpt_uop_prs3 : ld_xcpt_uop_prs3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_ppred = use_mem_xcpt ? mem_xcpt_uop_ppred : ld_xcpt_uop_ppred; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_prs1_busy = use_mem_xcpt ? mem_xcpt_uop_prs1_busy : ld_xcpt_uop_prs1_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_prs2_busy = use_mem_xcpt ? mem_xcpt_uop_prs2_busy : ld_xcpt_uop_prs2_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_prs3_busy = use_mem_xcpt ? mem_xcpt_uop_prs3_busy : ld_xcpt_uop_prs3_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_ppred_busy = use_mem_xcpt ? mem_xcpt_uop_ppred_busy : ld_xcpt_uop_ppred_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_stale_pdst = use_mem_xcpt ? mem_xcpt_uop_stale_pdst : ld_xcpt_uop_stale_pdst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_exception = use_mem_xcpt ? mem_xcpt_uop_exception : ld_xcpt_uop_exception; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [63:0] xcpt_uop_exc_cause = use_mem_xcpt ? mem_xcpt_uop_exc_cause : ld_xcpt_uop_exc_cause; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_mem_cmd = use_mem_xcpt ? mem_xcpt_uop_mem_cmd : ld_xcpt_uop_mem_cmd; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_mem_size = use_mem_xcpt ? mem_xcpt_uop_mem_size : ld_xcpt_uop_mem_size; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_mem_signed = use_mem_xcpt ? mem_xcpt_uop_mem_signed : ld_xcpt_uop_mem_signed; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_uses_ldq = use_mem_xcpt ? mem_xcpt_uop_uses_ldq : ld_xcpt_uop_uses_ldq; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_uses_stq = use_mem_xcpt ? mem_xcpt_uop_uses_stq : ld_xcpt_uop_uses_stq; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_unique = use_mem_xcpt ? mem_xcpt_uop_is_unique : ld_xcpt_uop_is_unique; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_flush_on_commit = use_mem_xcpt ? mem_xcpt_uop_flush_on_commit : ld_xcpt_uop_flush_on_commit; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_csr_cmd = use_mem_xcpt ? mem_xcpt_uop_csr_cmd : ld_xcpt_uop_csr_cmd; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_ldst_is_rs1 = use_mem_xcpt ? mem_xcpt_uop_ldst_is_rs1 : ld_xcpt_uop_ldst_is_rs1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_ldst = use_mem_xcpt ? mem_xcpt_uop_ldst : ld_xcpt_uop_ldst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_lrs1 = use_mem_xcpt ? mem_xcpt_uop_lrs1 : ld_xcpt_uop_lrs1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_lrs2 = use_mem_xcpt ? mem_xcpt_uop_lrs2 : ld_xcpt_uop_lrs2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_lrs3 = use_mem_xcpt ? mem_xcpt_uop_lrs3 : ld_xcpt_uop_lrs3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_dst_rtype = use_mem_xcpt ? mem_xcpt_uop_dst_rtype : ld_xcpt_uop_dst_rtype; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_lrs1_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs1_rtype : ld_xcpt_uop_lrs1_rtype; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_lrs2_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs2_rtype : ld_xcpt_uop_lrs2_rtype; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_frs3_en = use_mem_xcpt ? mem_xcpt_uop_frs3_en : ld_xcpt_uop_frs3_en; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fcn_dw = use_mem_xcpt ? mem_xcpt_uop_fcn_dw : ld_xcpt_uop_fcn_dw; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_fcn_op = use_mem_xcpt ? mem_xcpt_uop_fcn_op : ld_xcpt_uop_fcn_op; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_val = use_mem_xcpt ? mem_xcpt_uop_fp_val : ld_xcpt_uop_fp_val; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_fp_rm = use_mem_xcpt ? mem_xcpt_uop_fp_rm : ld_xcpt_uop_fp_rm; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_fp_typ = use_mem_xcpt ? mem_xcpt_uop_fp_typ : ld_xcpt_uop_fp_typ; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_xcpt_pf_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_pf_if : ld_xcpt_uop_xcpt_pf_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_xcpt_ae_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ae_if : ld_xcpt_uop_xcpt_ae_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_xcpt_ma_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ma_if : ld_xcpt_uop_xcpt_ma_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_bp_debug_if = use_mem_xcpt ? mem_xcpt_uop_bp_debug_if : ld_xcpt_uop_bp_debug_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_bp_xcpt_if = use_mem_xcpt ? mem_xcpt_uop_bp_xcpt_if : ld_xcpt_uop_bp_xcpt_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_debug_fsrc = use_mem_xcpt ? mem_xcpt_uop_debug_fsrc : ld_xcpt_uop_debug_fsrc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_debug_tsrc = use_mem_xcpt ? mem_xcpt_uop_debug_tsrc : ld_xcpt_uop_debug_tsrc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire _r_xcpt_valid_T = ld_xcpt_valid \| mem_xcpt_valid; // @[lsu.scala:457:29, :1437:66, :1444:34] wire [11:0] _r_xcpt_valid_T_1 = io_core_brupdate_b1_mispredict_mask_0 & xcpt_uop_br_mask; // @[util.scala:126:51] wire _r_xcpt_valid_T_2 = \|_r_xcpt_valid_T_1; // @[util.scala:126:{51,59}] wire _r_xcpt_valid_T_3 = _r_xcpt_valid_T_2 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _r_xcpt_valid_T_4 = ~_r_xcpt_valid_T_3; // @[util.scala:61:61] wire _r_xcpt_valid_T_5 = _r_xcpt_valid_T & _r_xcpt_valid_T_4; // @[lsu.scala:1444:{34,53,56}] wire [11:0] _r_xcpt_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] wire [11:0] _r_xcpt_uop_br_mask_T_1 = xcpt_uop_br_mask & _r_xcpt_uop_br_mask_T; // @[util.scala:93:{25,27}] wire [4:0] _r_xcpt_cause_T = use_mem_xcpt ? {1'h0, mem_xcpt_cause} : 5'h10; // @[lsu.scala:458:29, :1440:115, :1447:28] wire [11:0] _io_core_lxcpt_valid_T = io_core_brupdate_b1_mispredict_mask_0 & r_xcpt_uop_br_mask; // @[util.scala:126:51] wire _io_core_lxcpt_valid_T_1 = \|_io_core_lxcpt_valid_T; // @[util.scala:126:{51,59}] wire _io_core_lxcpt_valid_T_2 = _io_core_lxcpt_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_lxcpt_valid_T_3 = ~_io_core_lxcpt_valid_T_2; // @[util.scala:61:61] assign _io_core_lxcpt_valid_T_4 = r_xcpt_valid & _io_core_lxcpt_valid_T_3; // @[lsu.scala:1434:29, :1450:{39,42}] assign io_core_lxcpt_valid_0 = _io_core_lxcpt_valid_T_4; // @[lsu.scala:211:7, :1450:39] reg wakeupArbs_0_io_in_1_valid_REG; // @[lsu.scala:1458:47] wire _wakeupArbs_0_io_in_1_valid_T = fired_load_agen_exec_0 & wakeupArbs_0_io_in_1_valid_REG; // @[lsu.scala:321:49, :1457:69, :1458:47] wire _wakeupArbs_0_io_in_1_valid_T_2 = _wakeupArbs_0_io_in_1_valid_T; // @[lsu.scala:1457:69, :1458:69] wire _wakeupArbs_0_io_in_1_valid_T_3 = ~mem_incoming_uop_0_fp_val; // @[lsu.scala:1053:37, :1460:40] wire _wakeupArbs_0_io_in_1_valid_T_4 = _wakeupArbs_0_io_in_1_valid_T_2 & _wakeupArbs_0_io_in_1_valid_T_3; // @[lsu.scala:1458:69, :1459:69, :1460:40] wire [31:0] io_core_iresp_0_out_bits_uop_inst = iresp_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] io_core_iresp_0_out_bits_uop_debug_inst = iresp_0_bits_uop_debug_inst; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_rvc = iresp_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] io_core_iresp_0_out_bits_uop_debug_pc = iresp_0_bits_uop_debug_pc; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_0 = iresp_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_1 = iresp_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_2 = iresp_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_3 = iresp_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_0 = iresp_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_1 = iresp_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_2 = iresp_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_3 = iresp_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_4 = iresp_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_5 = iresp_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_6 = iresp_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_7 = iresp_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_8 = iresp_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_9 = iresp_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_issued = iresp_0_bits_uop_iw_issued; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_issued_partial_agen = iresp_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_issued_partial_dgen = iresp_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_iw_p1_speculative_child = iresp_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_iw_p2_speculative_child = iresp_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_p1_bypass_hint = iresp_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_p2_bypass_hint = iresp_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_p3_bypass_hint = iresp_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_dis_col_sel = iresp_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] io_core_iresp_0_out_bits_uop_br_tag = iresp_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] io_core_iresp_0_out_bits_uop_br_type = iresp_0_bits_uop_br_type; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_sfb = iresp_0_bits_uop_is_sfb; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_fence = iresp_0_bits_uop_is_fence; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_fencei = iresp_0_bits_uop_is_fencei; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_sfence = iresp_0_bits_uop_is_sfence; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_amo = iresp_0_bits_uop_is_amo; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_eret = iresp_0_bits_uop_is_eret; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_sys_pc2epc = iresp_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_rocc = iresp_0_bits_uop_is_rocc; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_mov = iresp_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_ftq_idx = iresp_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_edge_inst = iresp_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_pc_lob = iresp_0_bits_uop_pc_lob; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_taken = iresp_0_bits_uop_taken; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_imm_rename = iresp_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_imm_sel = iresp_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_pimm = iresp_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] io_core_iresp_0_out_bits_uop_imm_packed = iresp_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_op1_sel = iresp_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_op2_sel = iresp_0_bits_uop_op2_sel; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ldst = iresp_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_wen = iresp_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ren1 = iresp_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ren2 = iresp_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ren3 = iresp_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_swap12 = iresp_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_swap23 = iresp_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_fp_ctrl_typeTagIn = iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_fp_ctrl_typeTagOut = iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_fromint = iresp_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_toint = iresp_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_fastpipe = iresp_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_fma = iresp_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_div = iresp_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_sqrt = iresp_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_wflags = iresp_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_vec = iresp_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_rob_idx = iresp_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] io_core_iresp_0_out_bits_uop_ldq_idx = iresp_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] io_core_iresp_0_out_bits_uop_stq_idx = iresp_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_rxq_idx = iresp_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_pdst = iresp_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_prs1 = iresp_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_prs2 = iresp_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_prs3 = iresp_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_ppred = iresp_0_bits_uop_ppred; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_prs1_busy = iresp_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_prs2_busy = iresp_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_prs3_busy = iresp_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_ppred_busy = iresp_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_stale_pdst = iresp_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_exception = iresp_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] io_core_iresp_0_out_bits_uop_exc_cause = iresp_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_mem_cmd = iresp_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_mem_size = iresp_0_bits_uop_mem_size; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_mem_signed = iresp_0_bits_uop_mem_signed; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_uses_ldq = iresp_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_uses_stq = iresp_0_bits_uop_uses_stq; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_unique = iresp_0_bits_uop_is_unique; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_flush_on_commit = iresp_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_csr_cmd = iresp_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_ldst_is_rs1 = iresp_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_ldst = iresp_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_lrs1 = iresp_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_lrs2 = iresp_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_lrs3 = iresp_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_dst_rtype = iresp_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_lrs1_rtype = iresp_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_lrs2_rtype = iresp_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_frs3_en = iresp_0_bits_uop_frs3_en; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fcn_dw = iresp_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_fcn_op = iresp_0_bits_uop_fcn_op; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_val = iresp_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_fp_rm = iresp_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_fp_typ = iresp_0_bits_uop_fp_typ; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_xcpt_pf_if = iresp_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_xcpt_ae_if = iresp_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_xcpt_ma_if = iresp_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_bp_debug_if = iresp_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_bp_xcpt_if = iresp_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_debug_fsrc = iresp_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_debug_tsrc = iresp_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire [63:0] io_core_iresp_0_out_bits_data = iresp_0_bits_data; // @[util.scala:114:23] wire [11:0] iresp_0_bits_uop_br_mask; // @[lsu.scala:1477:19] wire iresp_0_valid; // @[lsu.scala:1477:19] assign io_core_fresp_0_valid_0 = fresp_0_valid; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_inst_0 = fresp_0_bits_uop_inst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_inst_0 = fresp_0_bits_uop_debug_inst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_rvc_0 = fresp_0_bits_uop_is_rvc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_pc_0 = fresp_0_bits_uop_debug_pc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_0_0 = fresp_0_bits_uop_iq_type_0; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_1_0 = fresp_0_bits_uop_iq_type_1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_2_0 = fresp_0_bits_uop_iq_type_2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_3_0 = fresp_0_bits_uop_iq_type_3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_0_0 = fresp_0_bits_uop_fu_code_0; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_1_0 = fresp_0_bits_uop_fu_code_1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_2_0 = fresp_0_bits_uop_fu_code_2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_3_0 = fresp_0_bits_uop_fu_code_3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_4_0 = fresp_0_bits_uop_fu_code_4; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_5_0 = fresp_0_bits_uop_fu_code_5; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_6_0 = fresp_0_bits_uop_fu_code_6; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_7_0 = fresp_0_bits_uop_fu_code_7; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_8_0 = fresp_0_bits_uop_fu_code_8; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_9_0 = fresp_0_bits_uop_fu_code_9; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_issued_0 = fresp_0_bits_uop_iw_issued; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_issued_partial_agen_0 = fresp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_issued_partial_dgen_0 = fresp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p1_speculative_child_0 = fresp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p2_speculative_child_0 = fresp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p1_bypass_hint_0 = fresp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p2_bypass_hint_0 = fresp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p3_bypass_hint_0 = fresp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_dis_col_sel_0 = fresp_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_br_mask_0 = fresp_0_bits_uop_br_mask; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_br_tag_0 = fresp_0_bits_uop_br_tag; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_br_type_0 = fresp_0_bits_uop_br_type; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_sfb_0 = fresp_0_bits_uop_is_sfb; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_fence_0 = fresp_0_bits_uop_is_fence; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_fencei_0 = fresp_0_bits_uop_is_fencei; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_sfence_0 = fresp_0_bits_uop_is_sfence; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_amo_0 = fresp_0_bits_uop_is_amo; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_eret_0 = fresp_0_bits_uop_is_eret; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_sys_pc2epc_0 = fresp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_rocc_0 = fresp_0_bits_uop_is_rocc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_mov_0 = fresp_0_bits_uop_is_mov; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ftq_idx_0 = fresp_0_bits_uop_ftq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_edge_inst_0 = fresp_0_bits_uop_edge_inst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_pc_lob_0 = fresp_0_bits_uop_pc_lob; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_taken_0 = fresp_0_bits_uop_taken; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_imm_rename_0 = fresp_0_bits_uop_imm_rename; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_imm_sel_0 = fresp_0_bits_uop_imm_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_pimm_0 = fresp_0_bits_uop_pimm; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_imm_packed_0 = fresp_0_bits_uop_imm_packed; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_op1_sel_0 = fresp_0_bits_uop_op1_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_op2_sel_0 = fresp_0_bits_uop_op2_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ldst_0 = fresp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_wen_0 = fresp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ren1_0 = fresp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ren2_0 = fresp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ren3_0 = fresp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_swap12_0 = fresp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_swap23_0 = fresp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn_0 = fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut_0 = fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_fromint_0 = fresp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_toint_0 = fresp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_fastpipe_0 = fresp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_fma_0 = fresp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_div_0 = fresp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_sqrt_0 = fresp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_wflags_0 = fresp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_vec_0 = fresp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_rob_idx_0 = fresp_0_bits_uop_rob_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ldq_idx_0 = fresp_0_bits_uop_ldq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_stq_idx_0 = fresp_0_bits_uop_stq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_rxq_idx_0 = fresp_0_bits_uop_rxq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_pdst_0 = fresp_0_bits_uop_pdst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs1_0 = fresp_0_bits_uop_prs1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs2_0 = fresp_0_bits_uop_prs2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs3_0 = fresp_0_bits_uop_prs3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ppred_0 = fresp_0_bits_uop_ppred; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs1_busy_0 = fresp_0_bits_uop_prs1_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs2_busy_0 = fresp_0_bits_uop_prs2_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs3_busy_0 = fresp_0_bits_uop_prs3_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ppred_busy_0 = fresp_0_bits_uop_ppred_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_stale_pdst_0 = fresp_0_bits_uop_stale_pdst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_exception_0 = fresp_0_bits_uop_exception; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_exc_cause_0 = fresp_0_bits_uop_exc_cause; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_mem_cmd_0 = fresp_0_bits_uop_mem_cmd; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_mem_size_0 = fresp_0_bits_uop_mem_size; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_mem_signed_0 = fresp_0_bits_uop_mem_signed; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_uses_ldq_0 = fresp_0_bits_uop_uses_ldq; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_uses_stq_0 = fresp_0_bits_uop_uses_stq; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_unique_0 = fresp_0_bits_uop_is_unique; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_flush_on_commit_0 = fresp_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_csr_cmd_0 = fresp_0_bits_uop_csr_cmd; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ldst_is_rs1_0 = fresp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ldst_0 = fresp_0_bits_uop_ldst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs1_0 = fresp_0_bits_uop_lrs1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs2_0 = fresp_0_bits_uop_lrs2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs3_0 = fresp_0_bits_uop_lrs3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_dst_rtype_0 = fresp_0_bits_uop_dst_rtype; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs1_rtype_0 = fresp_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs2_rtype_0 = fresp_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_frs3_en_0 = fresp_0_bits_uop_frs3_en; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fcn_dw_0 = fresp_0_bits_uop_fcn_dw; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fcn_op_0 = fresp_0_bits_uop_fcn_op; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_val_0 = fresp_0_bits_uop_fp_val; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_rm_0 = fresp_0_bits_uop_fp_rm; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_typ_0 = fresp_0_bits_uop_fp_typ; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_xcpt_pf_if_0 = fresp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_xcpt_ae_if_0 = fresp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_xcpt_ma_if_0 = fresp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_bp_debug_if_0 = fresp_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_bp_xcpt_if_0 = fresp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_fsrc_0 = fresp_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_tsrc_0 = fresp_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_data_0 = fresp_0_bits_data; // @[lsu.scala:211:7, :1478:19] wire _io_core_iresp_0_out_valid_T_4; // @[util.scala:116:31] wire [11:0] _io_core_iresp_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] io_core_iresp_0_out_bits_uop_br_mask; // @[util.scala:114:23] wire io_core_iresp_0_out_valid; // @[util.scala:114:23] wire [11:0] _io_core_iresp_0_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _io_core_iresp_0_out_bits_uop_br_mask_T_1 = iresp_0_bits_uop_br_mask & _io_core_iresp_0_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign io_core_iresp_0_out_bits_uop_br_mask = _io_core_iresp_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [11:0] _io_core_iresp_0_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & iresp_0_bits_uop_br_mask; // @[util.scala:126:51] wire _io_core_iresp_0_out_valid_T_1 = \|_io_core_iresp_0_out_valid_T; // @[util.scala:126:{51,59}] wire _io_core_iresp_0_out_valid_T_2 = _io_core_iresp_0_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_iresp_0_out_valid_T_3 = ~_io_core_iresp_0_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _io_core_iresp_0_out_valid_T_4 = iresp_0_valid & _io_core_iresp_0_out_valid_T_3; // @[util.scala:116:{31,34}] assign io_core_iresp_0_out_valid = _io_core_iresp_0_out_valid_T_4; // @[util.scala:114:23, :116:31] reg io_core_iresp_0_REG_valid; // @[lsu.scala:1485:70] assign io_core_iresp_0_valid_0 = io_core_iresp_0_REG_valid; // @[lsu.scala:211:7, :1485:70] reg [31:0] io_core_iresp_0_REG_bits_uop_inst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_inst_0 = io_core_iresp_0_REG_bits_uop_inst; // @[lsu.scala:211:7, :1485:70] reg [31:0] io_core_iresp_0_REG_bits_uop_debug_inst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_inst_0 = io_core_iresp_0_REG_bits_uop_debug_inst; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_rvc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_rvc_0 = io_core_iresp_0_REG_bits_uop_is_rvc; // @[lsu.scala:211:7, :1485:70] reg [39:0] io_core_iresp_0_REG_bits_uop_debug_pc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_pc_0 = io_core_iresp_0_REG_bits_uop_debug_pc; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_0; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_0_0 = io_core_iresp_0_REG_bits_uop_iq_type_0; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_1_0 = io_core_iresp_0_REG_bits_uop_iq_type_1; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_2_0 = io_core_iresp_0_REG_bits_uop_iq_type_2; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_3_0 = io_core_iresp_0_REG_bits_uop_iq_type_3; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_0; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_0_0 = io_core_iresp_0_REG_bits_uop_fu_code_0; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_1_0 = io_core_iresp_0_REG_bits_uop_fu_code_1; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_2_0 = io_core_iresp_0_REG_bits_uop_fu_code_2; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_3_0 = io_core_iresp_0_REG_bits_uop_fu_code_3; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_4; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_4_0 = io_core_iresp_0_REG_bits_uop_fu_code_4; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_5; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_5_0 = io_core_iresp_0_REG_bits_uop_fu_code_5; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_6; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_6_0 = io_core_iresp_0_REG_bits_uop_fu_code_6; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_7; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_7_0 = io_core_iresp_0_REG_bits_uop_fu_code_7; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_8; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_8_0 = io_core_iresp_0_REG_bits_uop_fu_code_8; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_9; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_9_0 = io_core_iresp_0_REG_bits_uop_fu_code_9; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_issued; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_issued_0 = io_core_iresp_0_REG_bits_uop_iw_issued; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_issued_partial_agen_0 = io_core_iresp_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_issued_partial_dgen_0 = io_core_iresp_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p1_speculative_child_0 = io_core_iresp_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p2_speculative_child_0 = io_core_iresp_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p1_bypass_hint_0 = io_core_iresp_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p2_bypass_hint_0 = io_core_iresp_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p3_bypass_hint_0 = io_core_iresp_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_dis_col_sel_0 = io_core_iresp_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:211:7, :1485:70] reg [11:0] io_core_iresp_0_REG_bits_uop_br_mask; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_br_mask_0 = io_core_iresp_0_REG_bits_uop_br_mask; // @[lsu.scala:211:7, :1485:70] reg [3:0] io_core_iresp_0_REG_bits_uop_br_tag; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_br_tag_0 = io_core_iresp_0_REG_bits_uop_br_tag; // @[lsu.scala:211:7, :1485:70] reg [3:0] io_core_iresp_0_REG_bits_uop_br_type; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_br_type_0 = io_core_iresp_0_REG_bits_uop_br_type; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_sfb; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_sfb_0 = io_core_iresp_0_REG_bits_uop_is_sfb; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_fence; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_fence_0 = io_core_iresp_0_REG_bits_uop_is_fence; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_fencei; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_fencei_0 = io_core_iresp_0_REG_bits_uop_is_fencei; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_sfence; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_sfence_0 = io_core_iresp_0_REG_bits_uop_is_sfence; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_amo; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_amo_0 = io_core_iresp_0_REG_bits_uop_is_amo; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_eret; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_eret_0 = io_core_iresp_0_REG_bits_uop_is_eret; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_sys_pc2epc_0 = io_core_iresp_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_rocc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_rocc_0 = io_core_iresp_0_REG_bits_uop_is_rocc; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_mov; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_mov_0 = io_core_iresp_0_REG_bits_uop_is_mov; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_ftq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ftq_idx_0 = io_core_iresp_0_REG_bits_uop_ftq_idx; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_edge_inst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_edge_inst_0 = io_core_iresp_0_REG_bits_uop_edge_inst; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_pc_lob; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_pc_lob_0 = io_core_iresp_0_REG_bits_uop_pc_lob; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_taken; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_taken_0 = io_core_iresp_0_REG_bits_uop_taken; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_imm_rename; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_imm_rename_0 = io_core_iresp_0_REG_bits_uop_imm_rename; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_imm_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_imm_sel_0 = io_core_iresp_0_REG_bits_uop_imm_sel; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_pimm; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_pimm_0 = io_core_iresp_0_REG_bits_uop_pimm; // @[lsu.scala:211:7, :1485:70] reg [19:0] io_core_iresp_0_REG_bits_uop_imm_packed; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_imm_packed_0 = io_core_iresp_0_REG_bits_uop_imm_packed; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_op1_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_op1_sel_0 = io_core_iresp_0_REG_bits_uop_op1_sel; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_op2_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_op2_sel_0 = io_core_iresp_0_REG_bits_uop_op2_sel; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ldst_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_wen_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ren1_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ren2_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ren3_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_swap12_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_swap23_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_fromint_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_toint_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_fastpipe_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_fma_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_div_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_sqrt_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_wflags_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_vec_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_rob_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_rob_idx_0 = io_core_iresp_0_REG_bits_uop_rob_idx; // @[lsu.scala:211:7, :1485:70] reg [3:0] io_core_iresp_0_REG_bits_uop_ldq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ldq_idx_0 = io_core_iresp_0_REG_bits_uop_ldq_idx; // @[lsu.scala:211:7, :1485:70] reg [3:0] io_core_iresp_0_REG_bits_uop_stq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_stq_idx_0 = io_core_iresp_0_REG_bits_uop_stq_idx; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_rxq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_rxq_idx_0 = io_core_iresp_0_REG_bits_uop_rxq_idx; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_pdst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_pdst_0 = io_core_iresp_0_REG_bits_uop_pdst; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_prs1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs1_0 = io_core_iresp_0_REG_bits_uop_prs1; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_prs2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs2_0 = io_core_iresp_0_REG_bits_uop_prs2; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_prs3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs3_0 = io_core_iresp_0_REG_bits_uop_prs3; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_ppred; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ppred_0 = io_core_iresp_0_REG_bits_uop_ppred; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_prs1_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs1_busy_0 = io_core_iresp_0_REG_bits_uop_prs1_busy; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_prs2_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs2_busy_0 = io_core_iresp_0_REG_bits_uop_prs2_busy; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_prs3_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs3_busy_0 = io_core_iresp_0_REG_bits_uop_prs3_busy; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_ppred_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ppred_busy_0 = io_core_iresp_0_REG_bits_uop_ppred_busy; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_stale_pdst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_stale_pdst_0 = io_core_iresp_0_REG_bits_uop_stale_pdst; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_exception; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_exception_0 = io_core_iresp_0_REG_bits_uop_exception; // @[lsu.scala:211:7, :1485:70] reg [63:0] io_core_iresp_0_REG_bits_uop_exc_cause; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_exc_cause_0 = io_core_iresp_0_REG_bits_uop_exc_cause; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_mem_cmd; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_mem_cmd_0 = io_core_iresp_0_REG_bits_uop_mem_cmd; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_mem_size; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_mem_size_0 = io_core_iresp_0_REG_bits_uop_mem_size; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_mem_signed; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_mem_signed_0 = io_core_iresp_0_REG_bits_uop_mem_signed; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_uses_ldq; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_uses_ldq_0 = io_core_iresp_0_REG_bits_uop_uses_ldq; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_uses_stq; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_uses_stq_0 = io_core_iresp_0_REG_bits_uop_uses_stq; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_unique; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_unique_0 = io_core_iresp_0_REG_bits_uop_is_unique; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_flush_on_commit_0 = io_core_iresp_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_csr_cmd; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_csr_cmd_0 = io_core_iresp_0_REG_bits_uop_csr_cmd; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ldst_is_rs1_0 = io_core_iresp_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_ldst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ldst_0 = io_core_iresp_0_REG_bits_uop_ldst; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_lrs1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs1_0 = io_core_iresp_0_REG_bits_uop_lrs1; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_lrs2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs2_0 = io_core_iresp_0_REG_bits_uop_lrs2; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_lrs3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs3_0 = io_core_iresp_0_REG_bits_uop_lrs3; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_dst_rtype; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_dst_rtype_0 = io_core_iresp_0_REG_bits_uop_dst_rtype; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs1_rtype_0 = io_core_iresp_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs2_rtype_0 = io_core_iresp_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_frs3_en; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_frs3_en_0 = io_core_iresp_0_REG_bits_uop_frs3_en; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fcn_dw; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fcn_dw_0 = io_core_iresp_0_REG_bits_uop_fcn_dw; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_fcn_op; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fcn_op_0 = io_core_iresp_0_REG_bits_uop_fcn_op; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_val; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_val_0 = io_core_iresp_0_REG_bits_uop_fp_val; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_fp_rm; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_rm_0 = io_core_iresp_0_REG_bits_uop_fp_rm; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_fp_typ; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_typ_0 = io_core_iresp_0_REG_bits_uop_fp_typ; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_xcpt_pf_if_0 = io_core_iresp_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_xcpt_ae_if_0 = io_core_iresp_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_xcpt_ma_if_0 = io_core_iresp_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_bp_debug_if_0 = io_core_iresp_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_bp_xcpt_if_0 = io_core_iresp_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_fsrc_0 = io_core_iresp_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_tsrc_0 = io_core_iresp_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:211:7, :1485:70] reg [63:0] io_core_iresp_0_REG_bits_data; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_data_0 = io_core_iresp_0_REG_bits_data; // @[lsu.scala:211:7, :1485:70] wire wb_spec_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1491:29] wire [31:0] wb_spec_wakeups_0_bits_uop_inst; // @[lsu.scala:1491:29] wire [31:0] wb_spec_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1491:29] wire [39:0] wb_spec_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1491:29] wire [11:0] wb_spec_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1491:29] wire [3:0] wb_spec_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1491:29] wire [3:0] wb_spec_wakeups_0_bits_uop_br_type; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_taken; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_pimm; // @[lsu.scala:1491:29] wire [19:0] wb_spec_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1491:29] wire [3:0] wb_spec_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1491:29] wire [3:0] wb_spec_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_pdst; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_prs1; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_prs2; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_prs3; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_ppred; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_exception; // @[lsu.scala:1491:29] wire [63:0] wb_spec_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_ldst; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_valid; // @[lsu.scala:1491:29] wire spec_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1492:26] wire [31:0] spec_wakeups_0_bits_uop_inst; // @[lsu.scala:1492:26] wire [31:0] spec_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1492:26] wire [39:0] spec_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1492:26] wire [11:0] spec_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1492:26] wire [3:0] spec_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1492:26] wire [3:0] spec_wakeups_0_bits_uop_br_type; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_taken; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_pimm; // @[lsu.scala:1492:26] wire [19:0] spec_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1492:26] wire [3:0] spec_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1492:26] wire [3:0] spec_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_pdst; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_prs1; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_prs2; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_prs3; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_ppred; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_exception; // @[lsu.scala:1492:26] wire [63:0] spec_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_ldst; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_bypassable; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_speculative_mask; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_rebusy; // @[lsu.scala:1492:26] wire spec_wakeups_0_valid; // @[lsu.scala:1492:26] wire [31:0] slow_wakeups_0_out_bits_uop_inst = wb_slow_wakeups_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] slow_wakeups_0_out_bits_uop_debug_inst = wb_slow_wakeups_0_bits_uop_debug_inst; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_rvc = wb_slow_wakeups_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] slow_wakeups_0_out_bits_uop_debug_pc = wb_slow_wakeups_0_bits_uop_debug_pc; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_0 = wb_slow_wakeups_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_1 = wb_slow_wakeups_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_2 = wb_slow_wakeups_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_3 = wb_slow_wakeups_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_0 = wb_slow_wakeups_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_1 = wb_slow_wakeups_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_2 = wb_slow_wakeups_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_3 = wb_slow_wakeups_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_4 = wb_slow_wakeups_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_5 = wb_slow_wakeups_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_6 = wb_slow_wakeups_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_7 = wb_slow_wakeups_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_8 = wb_slow_wakeups_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_9 = wb_slow_wakeups_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_issued = wb_slow_wakeups_0_bits_uop_iw_issued; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_issued_partial_agen = wb_slow_wakeups_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_issued_partial_dgen = wb_slow_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_iw_p1_speculative_child = wb_slow_wakeups_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_iw_p2_speculative_child = wb_slow_wakeups_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_p1_bypass_hint = wb_slow_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_p2_bypass_hint = wb_slow_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_p3_bypass_hint = wb_slow_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_dis_col_sel = wb_slow_wakeups_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] slow_wakeups_0_out_bits_uop_br_tag = wb_slow_wakeups_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] slow_wakeups_0_out_bits_uop_br_type = wb_slow_wakeups_0_bits_uop_br_type; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_sfb = wb_slow_wakeups_0_bits_uop_is_sfb; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_fence = wb_slow_wakeups_0_bits_uop_is_fence; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_fencei = wb_slow_wakeups_0_bits_uop_is_fencei; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_sfence = wb_slow_wakeups_0_bits_uop_is_sfence; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_amo = wb_slow_wakeups_0_bits_uop_is_amo; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_eret = wb_slow_wakeups_0_bits_uop_is_eret; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_sys_pc2epc = wb_slow_wakeups_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_rocc = wb_slow_wakeups_0_bits_uop_is_rocc; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_mov = wb_slow_wakeups_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_ftq_idx = wb_slow_wakeups_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_edge_inst = wb_slow_wakeups_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_pc_lob = wb_slow_wakeups_0_bits_uop_pc_lob; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_taken = wb_slow_wakeups_0_bits_uop_taken; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_imm_rename = wb_slow_wakeups_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_imm_sel = wb_slow_wakeups_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_pimm = wb_slow_wakeups_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] slow_wakeups_0_out_bits_uop_imm_packed = wb_slow_wakeups_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_op1_sel = wb_slow_wakeups_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_op2_sel = wb_slow_wakeups_0_bits_uop_op2_sel; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ldst = wb_slow_wakeups_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_wen = wb_slow_wakeups_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ren1 = wb_slow_wakeups_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ren2 = wb_slow_wakeups_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ren3 = wb_slow_wakeups_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_swap12 = wb_slow_wakeups_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_swap23 = wb_slow_wakeups_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_fp_ctrl_typeTagIn = wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_fp_ctrl_typeTagOut = wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_fromint = wb_slow_wakeups_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_toint = wb_slow_wakeups_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_fastpipe = wb_slow_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_fma = wb_slow_wakeups_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_div = wb_slow_wakeups_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_sqrt = wb_slow_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_wflags = wb_slow_wakeups_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_vec = wb_slow_wakeups_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_rob_idx = wb_slow_wakeups_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] slow_wakeups_0_out_bits_uop_ldq_idx = wb_slow_wakeups_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] slow_wakeups_0_out_bits_uop_stq_idx = wb_slow_wakeups_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_rxq_idx = wb_slow_wakeups_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_pdst = wb_slow_wakeups_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_prs1 = wb_slow_wakeups_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_prs2 = wb_slow_wakeups_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_prs3 = wb_slow_wakeups_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_ppred = wb_slow_wakeups_0_bits_uop_ppred; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_prs1_busy = wb_slow_wakeups_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_prs2_busy = wb_slow_wakeups_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_prs3_busy = wb_slow_wakeups_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_ppred_busy = wb_slow_wakeups_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_stale_pdst = wb_slow_wakeups_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_exception = wb_slow_wakeups_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] slow_wakeups_0_out_bits_uop_exc_cause = wb_slow_wakeups_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_mem_cmd = wb_slow_wakeups_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_mem_size = wb_slow_wakeups_0_bits_uop_mem_size; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_mem_signed = wb_slow_wakeups_0_bits_uop_mem_signed; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_uses_ldq = wb_slow_wakeups_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_uses_stq = wb_slow_wakeups_0_bits_uop_uses_stq; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_unique = wb_slow_wakeups_0_bits_uop_is_unique; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_flush_on_commit = wb_slow_wakeups_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_csr_cmd = wb_slow_wakeups_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_ldst_is_rs1 = wb_slow_wakeups_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_ldst = wb_slow_wakeups_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_lrs1 = wb_slow_wakeups_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_lrs2 = wb_slow_wakeups_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_lrs3 = wb_slow_wakeups_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_dst_rtype = wb_slow_wakeups_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_lrs1_rtype = wb_slow_wakeups_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_lrs2_rtype = wb_slow_wakeups_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_frs3_en = wb_slow_wakeups_0_bits_uop_frs3_en; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fcn_dw = wb_slow_wakeups_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_fcn_op = wb_slow_wakeups_0_bits_uop_fcn_op; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_val = wb_slow_wakeups_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_fp_rm = wb_slow_wakeups_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_fp_typ = wb_slow_wakeups_0_bits_uop_fp_typ; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_xcpt_pf_if = wb_slow_wakeups_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_xcpt_ae_if = wb_slow_wakeups_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_xcpt_ma_if = wb_slow_wakeups_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_bp_debug_if = wb_slow_wakeups_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_bp_xcpt_if = wb_slow_wakeups_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_debug_fsrc = wb_slow_wakeups_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_debug_tsrc = wb_slow_wakeups_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire [11:0] wb_slow_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_valid; // @[lsu.scala:1494:29] wire slow_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1495:26] wire [31:0] slow_wakeups_0_bits_uop_inst; // @[lsu.scala:1495:26] wire [31:0] slow_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1495:26] wire [39:0] slow_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1495:26] wire [11:0] slow_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1495:26] wire [3:0] slow_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1495:26] wire [3:0] slow_wakeups_0_bits_uop_br_type; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_taken; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_pimm; // @[lsu.scala:1495:26] wire [19:0] slow_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1495:26] wire [3:0] slow_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1495:26] wire [3:0] slow_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_pdst; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_prs1; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_prs2; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_prs3; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_ppred; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_exception; // @[lsu.scala:1495:26] wire [63:0] slow_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_ldst; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1495:26] wire dmem_resp_fired_0; // @[lsu.scala:1497:33] reg w1_valid; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_valid = w1_valid; // @[lsu.scala:1491:29, :1499:17] reg [31:0] w1_bits_uop_inst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_inst = w1_bits_uop_inst; // @[lsu.scala:1491:29, :1499:17] wire [31:0] w2_bits_out_uop_inst = w1_bits_uop_inst; // @[util.scala:109:23] reg [31:0] w1_bits_uop_debug_inst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_inst = w1_bits_uop_debug_inst; // @[lsu.scala:1491:29, :1499:17] wire [31:0] w2_bits_out_uop_debug_inst = w1_bits_uop_debug_inst; // @[util.scala:109:23] reg w1_bits_uop_is_rvc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_rvc = w1_bits_uop_is_rvc; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_rvc = w1_bits_uop_is_rvc; // @[util.scala:109:23] reg [39:0] w1_bits_uop_debug_pc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_pc = w1_bits_uop_debug_pc; // @[lsu.scala:1491:29, :1499:17] wire [39:0] w2_bits_out_uop_debug_pc = w1_bits_uop_debug_pc; // @[util.scala:109:23] reg w1_bits_uop_iq_type_0; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_0 = w1_bits_uop_iq_type_0; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_0 = w1_bits_uop_iq_type_0; // @[util.scala:109:23] reg w1_bits_uop_iq_type_1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_1 = w1_bits_uop_iq_type_1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_1 = w1_bits_uop_iq_type_1; // @[util.scala:109:23] reg w1_bits_uop_iq_type_2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_2 = w1_bits_uop_iq_type_2; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_2 = w1_bits_uop_iq_type_2; // @[util.scala:109:23] reg w1_bits_uop_iq_type_3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_3 = w1_bits_uop_iq_type_3; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_3 = w1_bits_uop_iq_type_3; // @[util.scala:109:23] reg w1_bits_uop_fu_code_0; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_0 = w1_bits_uop_fu_code_0; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_0 = w1_bits_uop_fu_code_0; // @[util.scala:109:23] reg w1_bits_uop_fu_code_1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_1 = w1_bits_uop_fu_code_1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_1 = w1_bits_uop_fu_code_1; // @[util.scala:109:23] reg w1_bits_uop_fu_code_2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_2 = w1_bits_uop_fu_code_2; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_2 = w1_bits_uop_fu_code_2; // @[util.scala:109:23] reg w1_bits_uop_fu_code_3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_3 = w1_bits_uop_fu_code_3; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_3 = w1_bits_uop_fu_code_3; // @[util.scala:109:23] reg w1_bits_uop_fu_code_4; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_4 = w1_bits_uop_fu_code_4; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_4 = w1_bits_uop_fu_code_4; // @[util.scala:109:23] reg w1_bits_uop_fu_code_5; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_5 = w1_bits_uop_fu_code_5; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_5 = w1_bits_uop_fu_code_5; // @[util.scala:109:23] reg w1_bits_uop_fu_code_6; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_6 = w1_bits_uop_fu_code_6; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_6 = w1_bits_uop_fu_code_6; // @[util.scala:109:23] reg w1_bits_uop_fu_code_7; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_7 = w1_bits_uop_fu_code_7; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_7 = w1_bits_uop_fu_code_7; // @[util.scala:109:23] reg w1_bits_uop_fu_code_8; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_8 = w1_bits_uop_fu_code_8; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_8 = w1_bits_uop_fu_code_8; // @[util.scala:109:23] reg w1_bits_uop_fu_code_9; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_9 = w1_bits_uop_fu_code_9; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_9 = w1_bits_uop_fu_code_9; // @[util.scala:109:23] reg w1_bits_uop_iw_issued; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_issued = w1_bits_uop_iw_issued; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_issued = w1_bits_uop_iw_issued; // @[util.scala:109:23] reg w1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_issued_partial_agen = w1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_issued_partial_agen = w1_bits_uop_iw_issued_partial_agen; // @[util.scala:109:23] reg w1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_issued_partial_dgen = w1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_issued_partial_dgen = w1_bits_uop_iw_issued_partial_dgen; // @[util.scala:109:23] reg [1:0] w1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p1_speculative_child = w1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_iw_p1_speculative_child = w1_bits_uop_iw_p1_speculative_child; // @[util.scala:109:23] reg [1:0] w1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p2_speculative_child = w1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_iw_p2_speculative_child = w1_bits_uop_iw_p2_speculative_child; // @[util.scala:109:23] reg w1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p1_bypass_hint = w1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_p1_bypass_hint = w1_bits_uop_iw_p1_bypass_hint; // @[util.scala:109:23] reg w1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p2_bypass_hint = w1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_p2_bypass_hint = w1_bits_uop_iw_p2_bypass_hint; // @[util.scala:109:23] reg w1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p3_bypass_hint = w1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_p3_bypass_hint = w1_bits_uop_iw_p3_bypass_hint; // @[util.scala:109:23] reg [1:0] w1_bits_uop_dis_col_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_dis_col_sel = w1_bits_uop_dis_col_sel; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_dis_col_sel = w1_bits_uop_dis_col_sel; // @[util.scala:109:23] reg [11:0] w1_bits_uop_br_mask; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_br_mask = w1_bits_uop_br_mask; // @[lsu.scala:1491:29, :1499:17] reg [3:0] w1_bits_uop_br_tag; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_br_tag = w1_bits_uop_br_tag; // @[lsu.scala:1491:29, :1499:17] wire [3:0] w2_bits_out_uop_br_tag = w1_bits_uop_br_tag; // @[util.scala:109:23] reg [3:0] w1_bits_uop_br_type; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_br_type = w1_bits_uop_br_type; // @[lsu.scala:1491:29, :1499:17] wire [3:0] w2_bits_out_uop_br_type = w1_bits_uop_br_type; // @[util.scala:109:23] reg w1_bits_uop_is_sfb; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_sfb = w1_bits_uop_is_sfb; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_sfb = w1_bits_uop_is_sfb; // @[util.scala:109:23] reg w1_bits_uop_is_fence; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_fence = w1_bits_uop_is_fence; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_fence = w1_bits_uop_is_fence; // @[util.scala:109:23] reg w1_bits_uop_is_fencei; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_fencei = w1_bits_uop_is_fencei; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_fencei = w1_bits_uop_is_fencei; // @[util.scala:109:23] reg w1_bits_uop_is_sfence; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_sfence = w1_bits_uop_is_sfence; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_sfence = w1_bits_uop_is_sfence; // @[util.scala:109:23] reg w1_bits_uop_is_amo; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_amo = w1_bits_uop_is_amo; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_amo = w1_bits_uop_is_amo; // @[util.scala:109:23] reg w1_bits_uop_is_eret; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_eret = w1_bits_uop_is_eret; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_eret = w1_bits_uop_is_eret; // @[util.scala:109:23] reg w1_bits_uop_is_sys_pc2epc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_sys_pc2epc = w1_bits_uop_is_sys_pc2epc; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_sys_pc2epc = w1_bits_uop_is_sys_pc2epc; // @[util.scala:109:23] reg w1_bits_uop_is_rocc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_rocc = w1_bits_uop_is_rocc; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_rocc = w1_bits_uop_is_rocc; // @[util.scala:109:23] reg w1_bits_uop_is_mov; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_mov = w1_bits_uop_is_mov; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_mov = w1_bits_uop_is_mov; // @[util.scala:109:23] reg [4:0] w1_bits_uop_ftq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ftq_idx = w1_bits_uop_ftq_idx; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_ftq_idx = w1_bits_uop_ftq_idx; // @[util.scala:109:23] reg w1_bits_uop_edge_inst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_edge_inst = w1_bits_uop_edge_inst; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_edge_inst = w1_bits_uop_edge_inst; // @[util.scala:109:23] reg [5:0] w1_bits_uop_pc_lob; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_pc_lob = w1_bits_uop_pc_lob; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_pc_lob = w1_bits_uop_pc_lob; // @[util.scala:109:23] reg w1_bits_uop_taken; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_taken = w1_bits_uop_taken; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_taken = w1_bits_uop_taken; // @[util.scala:109:23] reg w1_bits_uop_imm_rename; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_imm_rename = w1_bits_uop_imm_rename; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_imm_rename = w1_bits_uop_imm_rename; // @[util.scala:109:23] reg [2:0] w1_bits_uop_imm_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_imm_sel = w1_bits_uop_imm_sel; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_imm_sel = w1_bits_uop_imm_sel; // @[util.scala:109:23] reg [4:0] w1_bits_uop_pimm; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_pimm = w1_bits_uop_pimm; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_pimm = w1_bits_uop_pimm; // @[util.scala:109:23] reg [19:0] w1_bits_uop_imm_packed; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_imm_packed = w1_bits_uop_imm_packed; // @[lsu.scala:1491:29, :1499:17] wire [19:0] w2_bits_out_uop_imm_packed = w1_bits_uop_imm_packed; // @[util.scala:109:23] reg [1:0] w1_bits_uop_op1_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_op1_sel = w1_bits_uop_op1_sel; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_op1_sel = w1_bits_uop_op1_sel; // @[util.scala:109:23] reg [2:0] w1_bits_uop_op2_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_op2_sel = w1_bits_uop_op2_sel; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_op2_sel = w1_bits_uop_op2_sel; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ldst = w1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ldst = w1_bits_uop_fp_ctrl_ldst; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_wen; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_wen = w1_bits_uop_fp_ctrl_wen; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_wen = w1_bits_uop_fp_ctrl_wen; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ren1 = w1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ren1 = w1_bits_uop_fp_ctrl_ren1; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ren2 = w1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ren2 = w1_bits_uop_fp_ctrl_ren2; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ren3 = w1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ren3 = w1_bits_uop_fp_ctrl_ren3; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_swap12 = w1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_swap12 = w1_bits_uop_fp_ctrl_swap12; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_swap23 = w1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_swap23 = w1_bits_uop_fp_ctrl_swap23; // @[util.scala:109:23] reg [1:0] w1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn = w1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_fp_ctrl_typeTagIn = w1_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23] reg [1:0] w1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut = w1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_fp_ctrl_typeTagOut = w1_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_fromint = w1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_fromint = w1_bits_uop_fp_ctrl_fromint; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_toint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_toint = w1_bits_uop_fp_ctrl_toint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_toint = w1_bits_uop_fp_ctrl_toint; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_fastpipe = w1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_fastpipe = w1_bits_uop_fp_ctrl_fastpipe; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_fma; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_fma = w1_bits_uop_fp_ctrl_fma; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_fma = w1_bits_uop_fp_ctrl_fma; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_div; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_div = w1_bits_uop_fp_ctrl_div; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_div = w1_bits_uop_fp_ctrl_div; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_sqrt = w1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_sqrt = w1_bits_uop_fp_ctrl_sqrt; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_wflags = w1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_wflags = w1_bits_uop_fp_ctrl_wflags; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_vec; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_vec = w1_bits_uop_fp_ctrl_vec; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_vec = w1_bits_uop_fp_ctrl_vec; // @[util.scala:109:23] reg [5:0] w1_bits_uop_rob_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_rob_idx = w1_bits_uop_rob_idx; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_rob_idx = w1_bits_uop_rob_idx; // @[util.scala:109:23] reg [3:0] w1_bits_uop_ldq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ldq_idx = w1_bits_uop_ldq_idx; // @[lsu.scala:1491:29, :1499:17] wire [3:0] w2_bits_out_uop_ldq_idx = w1_bits_uop_ldq_idx; // @[util.scala:109:23] reg [3:0] w1_bits_uop_stq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_stq_idx = w1_bits_uop_stq_idx; // @[lsu.scala:1491:29, :1499:17] wire [3:0] w2_bits_out_uop_stq_idx = w1_bits_uop_stq_idx; // @[util.scala:109:23] reg [1:0] w1_bits_uop_rxq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_rxq_idx = w1_bits_uop_rxq_idx; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_rxq_idx = w1_bits_uop_rxq_idx; // @[util.scala:109:23] reg [6:0] w1_bits_uop_pdst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_pdst = w1_bits_uop_pdst; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_pdst = w1_bits_uop_pdst; // @[util.scala:109:23] reg [6:0] w1_bits_uop_prs1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs1 = w1_bits_uop_prs1; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_prs1 = w1_bits_uop_prs1; // @[util.scala:109:23] reg [6:0] w1_bits_uop_prs2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs2 = w1_bits_uop_prs2; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_prs2 = w1_bits_uop_prs2; // @[util.scala:109:23] reg [6:0] w1_bits_uop_prs3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs3 = w1_bits_uop_prs3; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_prs3 = w1_bits_uop_prs3; // @[util.scala:109:23] reg [4:0] w1_bits_uop_ppred; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ppred = w1_bits_uop_ppred; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_ppred = w1_bits_uop_ppred; // @[util.scala:109:23] reg w1_bits_uop_prs1_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs1_busy = w1_bits_uop_prs1_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_prs1_busy = w1_bits_uop_prs1_busy; // @[util.scala:109:23] reg w1_bits_uop_prs2_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs2_busy = w1_bits_uop_prs2_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_prs2_busy = w1_bits_uop_prs2_busy; // @[util.scala:109:23] reg w1_bits_uop_prs3_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs3_busy = w1_bits_uop_prs3_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_prs3_busy = w1_bits_uop_prs3_busy; // @[util.scala:109:23] reg w1_bits_uop_ppred_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ppred_busy = w1_bits_uop_ppred_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_ppred_busy = w1_bits_uop_ppred_busy; // @[util.scala:109:23] reg [6:0] w1_bits_uop_stale_pdst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_stale_pdst = w1_bits_uop_stale_pdst; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_stale_pdst = w1_bits_uop_stale_pdst; // @[util.scala:109:23] reg w1_bits_uop_exception; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_exception = w1_bits_uop_exception; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_exception = w1_bits_uop_exception; // @[util.scala:109:23] reg [63:0] w1_bits_uop_exc_cause; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_exc_cause = w1_bits_uop_exc_cause; // @[lsu.scala:1491:29, :1499:17] wire [63:0] w2_bits_out_uop_exc_cause = w1_bits_uop_exc_cause; // @[util.scala:109:23] reg [4:0] w1_bits_uop_mem_cmd; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_mem_cmd = w1_bits_uop_mem_cmd; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_mem_cmd = w1_bits_uop_mem_cmd; // @[util.scala:109:23] reg [1:0] w1_bits_uop_mem_size; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_mem_size = w1_bits_uop_mem_size; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_mem_size = w1_bits_uop_mem_size; // @[util.scala:109:23] reg w1_bits_uop_mem_signed; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_mem_signed = w1_bits_uop_mem_signed; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_mem_signed = w1_bits_uop_mem_signed; // @[util.scala:109:23] reg w1_bits_uop_uses_ldq; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_uses_ldq = w1_bits_uop_uses_ldq; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_uses_ldq = w1_bits_uop_uses_ldq; // @[util.scala:109:23] reg w1_bits_uop_uses_stq; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_uses_stq = w1_bits_uop_uses_stq; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_uses_stq = w1_bits_uop_uses_stq; // @[util.scala:109:23] reg w1_bits_uop_is_unique; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_unique = w1_bits_uop_is_unique; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_unique = w1_bits_uop_is_unique; // @[util.scala:109:23] reg w1_bits_uop_flush_on_commit; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_flush_on_commit = w1_bits_uop_flush_on_commit; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_flush_on_commit = w1_bits_uop_flush_on_commit; // @[util.scala:109:23] reg [2:0] w1_bits_uop_csr_cmd; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_csr_cmd = w1_bits_uop_csr_cmd; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_csr_cmd = w1_bits_uop_csr_cmd; // @[util.scala:109:23] reg w1_bits_uop_ldst_is_rs1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ldst_is_rs1 = w1_bits_uop_ldst_is_rs1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_ldst_is_rs1 = w1_bits_uop_ldst_is_rs1; // @[util.scala:109:23] reg [5:0] w1_bits_uop_ldst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ldst = w1_bits_uop_ldst; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_ldst = w1_bits_uop_ldst; // @[util.scala:109:23] reg [5:0] w1_bits_uop_lrs1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs1 = w1_bits_uop_lrs1; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_lrs1 = w1_bits_uop_lrs1; // @[util.scala:109:23] reg [5:0] w1_bits_uop_lrs2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs2 = w1_bits_uop_lrs2; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_lrs2 = w1_bits_uop_lrs2; // @[util.scala:109:23] reg [5:0] w1_bits_uop_lrs3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs3 = w1_bits_uop_lrs3; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_lrs3 = w1_bits_uop_lrs3; // @[util.scala:109:23] reg [1:0] w1_bits_uop_dst_rtype; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_dst_rtype = w1_bits_uop_dst_rtype; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_dst_rtype = w1_bits_uop_dst_rtype; // @[util.scala:109:23] reg [1:0] w1_bits_uop_lrs1_rtype; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs1_rtype = w1_bits_uop_lrs1_rtype; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_lrs1_rtype = w1_bits_uop_lrs1_rtype; // @[util.scala:109:23] reg [1:0] w1_bits_uop_lrs2_rtype; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs2_rtype = w1_bits_uop_lrs2_rtype; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_lrs2_rtype = w1_bits_uop_lrs2_rtype; // @[util.scala:109:23] reg w1_bits_uop_frs3_en; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_frs3_en = w1_bits_uop_frs3_en; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_frs3_en = w1_bits_uop_frs3_en; // @[util.scala:109:23] reg w1_bits_uop_fcn_dw; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fcn_dw = w1_bits_uop_fcn_dw; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fcn_dw = w1_bits_uop_fcn_dw; // @[util.scala:109:23] reg [4:0] w1_bits_uop_fcn_op; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fcn_op = w1_bits_uop_fcn_op; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_fcn_op = w1_bits_uop_fcn_op; // @[util.scala:109:23] reg w1_bits_uop_fp_val; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_val = w1_bits_uop_fp_val; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_val = w1_bits_uop_fp_val; // @[util.scala:109:23] reg [2:0] w1_bits_uop_fp_rm; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_rm = w1_bits_uop_fp_rm; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_fp_rm = w1_bits_uop_fp_rm; // @[util.scala:109:23] reg [1:0] w1_bits_uop_fp_typ; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_typ = w1_bits_uop_fp_typ; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_fp_typ = w1_bits_uop_fp_typ; // @[util.scala:109:23] reg w1_bits_uop_xcpt_pf_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_xcpt_pf_if = w1_bits_uop_xcpt_pf_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_xcpt_pf_if = w1_bits_uop_xcpt_pf_if; // @[util.scala:109:23] reg w1_bits_uop_xcpt_ae_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_xcpt_ae_if = w1_bits_uop_xcpt_ae_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_xcpt_ae_if = w1_bits_uop_xcpt_ae_if; // @[util.scala:109:23] reg w1_bits_uop_xcpt_ma_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_xcpt_ma_if = w1_bits_uop_xcpt_ma_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_xcpt_ma_if = w1_bits_uop_xcpt_ma_if; // @[util.scala:109:23] reg w1_bits_uop_bp_debug_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_bp_debug_if = w1_bits_uop_bp_debug_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_bp_debug_if = w1_bits_uop_bp_debug_if; // @[util.scala:109:23] reg w1_bits_uop_bp_xcpt_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_bp_xcpt_if = w1_bits_uop_bp_xcpt_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_bp_xcpt_if = w1_bits_uop_bp_xcpt_if; // @[util.scala:109:23] reg [2:0] w1_bits_uop_debug_fsrc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_fsrc = w1_bits_uop_debug_fsrc; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_debug_fsrc = w1_bits_uop_debug_fsrc; // @[util.scala:109:23] reg [2:0] w1_bits_uop_debug_tsrc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_tsrc = w1_bits_uop_debug_tsrc; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_debug_tsrc = w1_bits_uop_debug_tsrc; // @[util.scala:109:23] wire _w1_valid_T = _wakeupArbs_0_io_in_1_ready & _wakeupArbs_0_io_in_1_valid_T_4; // @[Decoupled.scala:51:35] wire [11:0] _w1_valid_T_1 = io_core_brupdate_b1_mispredict_mask_0 & mem_incoming_uop_0_br_mask; // @[util.scala:126:51] wire _w1_valid_T_2 = \|_w1_valid_T_1; // @[util.scala:126:{51,59}] wire _w1_valid_T_3 = _w1_valid_T_2 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _w1_valid_T_4 = ~_w1_valid_T_3; // @[util.scala:61:61] wire _w1_valid_T_5 = _w1_valid_T & _w1_valid_T_4; // @[Decoupled.scala:51:35] wire [11:0] _w1_bits_out_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] w1_bits_out_uop_br_mask; // @[util.scala:109:23] wire [11:0] _w1_bits_out_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _w1_bits_out_uop_br_mask_T_1 = mem_incoming_uop_0_br_mask & _w1_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign w1_bits_out_uop_br_mask = _w1_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] reg w2_valid; // @[lsu.scala:1503:17] assign spec_wakeups_0_valid = w2_valid; // @[lsu.scala:1492:26, :1503:17] reg [31:0] w2_bits_uop_inst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_inst = w2_bits_uop_inst; // @[lsu.scala:1492:26, :1503:17] reg [31:0] w2_bits_uop_debug_inst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_inst = w2_bits_uop_debug_inst; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_rvc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_rvc = w2_bits_uop_is_rvc; // @[lsu.scala:1492:26, :1503:17] reg [39:0] w2_bits_uop_debug_pc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_pc = w2_bits_uop_debug_pc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_0; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_0 = w2_bits_uop_iq_type_0; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_1 = w2_bits_uop_iq_type_1; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_2 = w2_bits_uop_iq_type_2; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_3 = w2_bits_uop_iq_type_3; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_0; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_0 = w2_bits_uop_fu_code_0; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_1 = w2_bits_uop_fu_code_1; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_2 = w2_bits_uop_fu_code_2; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_3 = w2_bits_uop_fu_code_3; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_4; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_4 = w2_bits_uop_fu_code_4; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_5; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_5 = w2_bits_uop_fu_code_5; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_6; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_6 = w2_bits_uop_fu_code_6; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_7; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_7 = w2_bits_uop_fu_code_7; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_8; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_8 = w2_bits_uop_fu_code_8; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_9; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_9 = w2_bits_uop_fu_code_9; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_issued; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_issued = w2_bits_uop_iw_issued; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_issued_partial_agen = w2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_issued_partial_dgen = w2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p1_speculative_child = w2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p2_speculative_child = w2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p1_bypass_hint = w2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p2_bypass_hint = w2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p3_bypass_hint = w2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_dis_col_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_dis_col_sel = w2_bits_uop_dis_col_sel; // @[lsu.scala:1492:26, :1503:17] reg [11:0] w2_bits_uop_br_mask; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_br_mask = w2_bits_uop_br_mask; // @[lsu.scala:1492:26, :1503:17] reg [3:0] w2_bits_uop_br_tag; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_br_tag = w2_bits_uop_br_tag; // @[lsu.scala:1492:26, :1503:17] reg [3:0] w2_bits_uop_br_type; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_br_type = w2_bits_uop_br_type; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_sfb; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_sfb = w2_bits_uop_is_sfb; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_fence; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_fence = w2_bits_uop_is_fence; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_fencei; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_fencei = w2_bits_uop_is_fencei; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_sfence; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_sfence = w2_bits_uop_is_sfence; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_amo; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_amo = w2_bits_uop_is_amo; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_eret; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_eret = w2_bits_uop_is_eret; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_sys_pc2epc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_sys_pc2epc = w2_bits_uop_is_sys_pc2epc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_rocc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_rocc = w2_bits_uop_is_rocc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_mov; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_mov = w2_bits_uop_is_mov; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_ftq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ftq_idx = w2_bits_uop_ftq_idx; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_edge_inst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_edge_inst = w2_bits_uop_edge_inst; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_pc_lob; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_pc_lob = w2_bits_uop_pc_lob; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_taken; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_taken = w2_bits_uop_taken; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_imm_rename; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_imm_rename = w2_bits_uop_imm_rename; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_imm_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_imm_sel = w2_bits_uop_imm_sel; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_pimm; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_pimm = w2_bits_uop_pimm; // @[lsu.scala:1492:26, :1503:17] reg [19:0] w2_bits_uop_imm_packed; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_imm_packed = w2_bits_uop_imm_packed; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_op1_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_op1_sel = w2_bits_uop_op1_sel; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_op2_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_op2_sel = w2_bits_uop_op2_sel; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ldst = w2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_wen; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_wen = w2_bits_uop_fp_ctrl_wen; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ren1 = w2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ren2 = w2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ren3 = w2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_swap12 = w2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_swap23 = w2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn = w2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut = w2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_fromint = w2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_toint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_toint = w2_bits_uop_fp_ctrl_toint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_fastpipe = w2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_fma; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_fma = w2_bits_uop_fp_ctrl_fma; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_div; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_div = w2_bits_uop_fp_ctrl_div; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_sqrt = w2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_wflags = w2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_vec; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_vec = w2_bits_uop_fp_ctrl_vec; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_rob_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_rob_idx = w2_bits_uop_rob_idx; // @[lsu.scala:1492:26, :1503:17] reg [3:0] w2_bits_uop_ldq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ldq_idx = w2_bits_uop_ldq_idx; // @[lsu.scala:1492:26, :1503:17] reg [3:0] w2_bits_uop_stq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_stq_idx = w2_bits_uop_stq_idx; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_rxq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_rxq_idx = w2_bits_uop_rxq_idx; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_pdst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_pdst = w2_bits_uop_pdst; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_prs1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs1 = w2_bits_uop_prs1; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_prs2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs2 = w2_bits_uop_prs2; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_prs3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs3 = w2_bits_uop_prs3; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_ppred; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ppred = w2_bits_uop_ppred; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_prs1_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs1_busy = w2_bits_uop_prs1_busy; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_prs2_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs2_busy = w2_bits_uop_prs2_busy; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_prs3_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs3_busy = w2_bits_uop_prs3_busy; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_ppred_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ppred_busy = w2_bits_uop_ppred_busy; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_stale_pdst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_stale_pdst = w2_bits_uop_stale_pdst; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_exception; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_exception = w2_bits_uop_exception; // @[lsu.scala:1492:26, :1503:17] reg [63:0] w2_bits_uop_exc_cause; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_exc_cause = w2_bits_uop_exc_cause; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_mem_cmd; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_mem_cmd = w2_bits_uop_mem_cmd; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_mem_size; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_mem_size = w2_bits_uop_mem_size; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_mem_signed; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_mem_signed = w2_bits_uop_mem_signed; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_uses_ldq; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_uses_ldq = w2_bits_uop_uses_ldq; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_uses_stq; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_uses_stq = w2_bits_uop_uses_stq; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_unique; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_unique = w2_bits_uop_is_unique; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_flush_on_commit; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_flush_on_commit = w2_bits_uop_flush_on_commit; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_csr_cmd; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_csr_cmd = w2_bits_uop_csr_cmd; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_ldst_is_rs1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ldst_is_rs1 = w2_bits_uop_ldst_is_rs1; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_ldst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ldst = w2_bits_uop_ldst; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_lrs1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs1 = w2_bits_uop_lrs1; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_lrs2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs2 = w2_bits_uop_lrs2; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_lrs3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs3 = w2_bits_uop_lrs3; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_dst_rtype; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_dst_rtype = w2_bits_uop_dst_rtype; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_lrs1_rtype; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs1_rtype = w2_bits_uop_lrs1_rtype; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_lrs2_rtype; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs2_rtype = w2_bits_uop_lrs2_rtype; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_frs3_en; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_frs3_en = w2_bits_uop_frs3_en; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fcn_dw; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fcn_dw = w2_bits_uop_fcn_dw; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_fcn_op; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fcn_op = w2_bits_uop_fcn_op; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_val; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_val = w2_bits_uop_fp_val; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_fp_rm; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_rm = w2_bits_uop_fp_rm; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_fp_typ; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_typ = w2_bits_uop_fp_typ; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_xcpt_pf_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_xcpt_pf_if = w2_bits_uop_xcpt_pf_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_xcpt_ae_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_xcpt_ae_if = w2_bits_uop_xcpt_ae_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_xcpt_ma_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_xcpt_ma_if = w2_bits_uop_xcpt_ma_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_bp_debug_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_bp_debug_if = w2_bits_uop_bp_debug_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_bp_xcpt_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_bp_xcpt_if = w2_bits_uop_bp_xcpt_if; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_debug_fsrc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_fsrc = w2_bits_uop_debug_fsrc; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_debug_tsrc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_tsrc = w2_bits_uop_debug_tsrc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_bypassable; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_bypassable = w2_bits_bypassable; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_speculative_mask; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_speculative_mask = w2_bits_speculative_mask; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_rebusy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_rebusy = w2_bits_rebusy; // @[lsu.scala:1492:26, :1503:17] wire [11:0] _w2_valid_T = io_core_brupdate_b1_mispredict_mask_0 & w1_bits_uop_br_mask; // @[util.scala:126:51] wire _w2_valid_T_1 = \|_w2_valid_T; // @[util.scala:126:{51,59}] wire _w2_valid_T_2 = _w2_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _w2_valid_T_3 = ~_w2_valid_T_2; // @[util.scala:61:61] wire _w2_valid_T_4 = w1_valid & _w2_valid_T_3; // @[lsu.scala:1499:17, :1504:{26,29}] wire [11:0] _w2_bits_out_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] w2_bits_out_uop_br_mask; // @[util.scala:109:23] wire [11:0] _w2_bits_out_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _w2_bits_out_uop_br_mask_T_1 = w1_bits_uop_br_mask & _w2_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign w2_bits_out_uop_br_mask = _w2_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] wire _GEN_503 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0; // @[lsu.scala:211:7, :1520:44] wire _GEN_504 = _GEN_503 & io_dmem_nack_0_bits_uop_uses_ldq_0 & ~reset; // @[lsu.scala:211:7, :1520:44, :1522:55, :1523:15] wire _T_1159 = io_dmem_nack_0_bits_uop_stq_idx_0 < stq_execute_head ^ io_dmem_nack_0_bits_uop_stq_idx_0 < stq_head ^ stq_execute_head < stq_head; // @[util.scala:364:{52,58,64,72,78}] wire _GEN_505 = io_dmem_nack_0_bits_is_hella_0 \| io_dmem_nack_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7, :895:40, :1520:44, :1522:55, :1527:86] assign stq_execute_queue_flush = io_dmem_nack_0_valid_0 & ~_GEN_505 & _T_1159 \| ~_GEN_385 & _T_1139 & ~dmem_req_fire_0; // @[util.scala:364:{58,72}] wire _resp_T = ~io_dmem_resp_0_valid_0; // @[lsu.scala:211:7, :1534:20] wire _resp_T_1 = _resp_T; // @[lsu.scala:1534:{20,43}] wire [31:0] resp_uop_inst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_inst_0 : io_dmem_resp_0_bits_uop_inst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [31:0] resp_uop_debug_inst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_inst_0 : io_dmem_resp_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_rvc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_rvc_0 : io_dmem_resp_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [39:0] resp_uop_debug_pc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_pc_0 : io_dmem_resp_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_0 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_0_0 : io_dmem_resp_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_1_0 : io_dmem_resp_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_2_0 : io_dmem_resp_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_3_0 : io_dmem_resp_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_0 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_0_0 : io_dmem_resp_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_1_0 : io_dmem_resp_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_2_0 : io_dmem_resp_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_3_0 : io_dmem_resp_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_4 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_4_0 : io_dmem_resp_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_5 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_5_0 : io_dmem_resp_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_6 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_6_0 : io_dmem_resp_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_7 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_7_0 : io_dmem_resp_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_8 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_8_0 : io_dmem_resp_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_9 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_9_0 : io_dmem_resp_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_issued = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_issued_0 : io_dmem_resp_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_issued_partial_agen = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_issued_partial_agen_0 : io_dmem_resp_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_issued_partial_dgen = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen_0 : io_dmem_resp_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_iw_p1_speculative_child = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p1_speculative_child_0 : io_dmem_resp_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_iw_p2_speculative_child = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p2_speculative_child_0 : io_dmem_resp_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_p1_bypass_hint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint_0 : io_dmem_resp_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_p2_bypass_hint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint_0 : io_dmem_resp_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_p3_bypass_hint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint_0 : io_dmem_resp_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_dis_col_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_dis_col_sel_0 : io_dmem_resp_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [11:0] resp_uop_br_mask = _resp_T_1 ? io_dmem_ll_resp_bits_uop_br_mask_0 : io_dmem_resp_0_bits_uop_br_mask_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [3:0] resp_uop_br_tag = _resp_T_1 ? io_dmem_ll_resp_bits_uop_br_tag_0 : io_dmem_resp_0_bits_uop_br_tag_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [3:0] resp_uop_br_type = _resp_T_1 ? io_dmem_ll_resp_bits_uop_br_type_0 : io_dmem_resp_0_bits_uop_br_type_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_sfb = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_sfb_0 : io_dmem_resp_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_fence = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_fence_0 : io_dmem_resp_0_bits_uop_is_fence_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_fencei = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_fencei_0 : io_dmem_resp_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_sfence = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_sfence_0 : io_dmem_resp_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_amo = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_amo_0 : io_dmem_resp_0_bits_uop_is_amo_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_eret = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_eret_0 : io_dmem_resp_0_bits_uop_is_eret_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_sys_pc2epc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_sys_pc2epc_0 : io_dmem_resp_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_rocc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_rocc_0 : io_dmem_resp_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_mov = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_mov_0 : io_dmem_resp_0_bits_uop_is_mov_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_ftq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ftq_idx_0 : io_dmem_resp_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_edge_inst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_edge_inst_0 : io_dmem_resp_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_pc_lob = _resp_T_1 ? io_dmem_ll_resp_bits_uop_pc_lob_0 : io_dmem_resp_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_taken = _resp_T_1 ? io_dmem_ll_resp_bits_uop_taken_0 : io_dmem_resp_0_bits_uop_taken_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_imm_rename = _resp_T_1 ? io_dmem_ll_resp_bits_uop_imm_rename_0 : io_dmem_resp_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_imm_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_imm_sel_0 : io_dmem_resp_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_pimm = _resp_T_1 ? io_dmem_ll_resp_bits_uop_pimm_0 : io_dmem_resp_0_bits_uop_pimm_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [19:0] resp_uop_imm_packed = _resp_T_1 ? io_dmem_ll_resp_bits_uop_imm_packed_0 : io_dmem_resp_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_op1_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_op1_sel_0 : io_dmem_resp_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_op2_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_op2_sel_0 : io_dmem_resp_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ldst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ldst_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_wen = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_wen_0 : io_dmem_resp_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ren1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ren1_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ren2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ren2_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ren3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ren3_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_swap12 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_swap12_0 : io_dmem_resp_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_swap23 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_swap23_0 : io_dmem_resp_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_fp_ctrl_typeTagIn = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn_0 : io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_fp_ctrl_typeTagOut = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut_0 : io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_fromint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_fromint_0 : io_dmem_resp_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_toint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_toint_0 : io_dmem_resp_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_fastpipe = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe_0 : io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_fma = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_fma_0 : io_dmem_resp_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_div = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_div_0 : io_dmem_resp_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_sqrt = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt_0 : io_dmem_resp_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_wflags = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_wflags_0 : io_dmem_resp_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_vec = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_vec_0 : io_dmem_resp_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_rob_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_rob_idx_0 : io_dmem_resp_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [3:0] resp_uop_ldq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ldq_idx_0 : io_dmem_resp_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [3:0] resp_uop_stq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_stq_idx_0 : io_dmem_resp_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_rxq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_rxq_idx_0 : io_dmem_resp_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_pdst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_pdst_0 : io_dmem_resp_0_bits_uop_pdst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_prs1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs1_0 : io_dmem_resp_0_bits_uop_prs1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_prs2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs2_0 : io_dmem_resp_0_bits_uop_prs2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_prs3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs3_0 : io_dmem_resp_0_bits_uop_prs3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_ppred = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ppred_0 : io_dmem_resp_0_bits_uop_ppred_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_prs1_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs1_busy_0 : io_dmem_resp_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_prs2_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs2_busy_0 : io_dmem_resp_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_prs3_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs3_busy_0 : io_dmem_resp_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_ppred_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ppred_busy_0 : io_dmem_resp_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_stale_pdst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_stale_pdst_0 : io_dmem_resp_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_exception = _resp_T_1 ? io_dmem_ll_resp_bits_uop_exception_0 : io_dmem_resp_0_bits_uop_exception_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [63:0] resp_uop_exc_cause = _resp_T_1 ? io_dmem_ll_resp_bits_uop_exc_cause_0 : io_dmem_resp_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_mem_cmd = _resp_T_1 ? io_dmem_ll_resp_bits_uop_mem_cmd_0 : io_dmem_resp_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_mem_size = _resp_T_1 ? io_dmem_ll_resp_bits_uop_mem_size_0 : io_dmem_resp_0_bits_uop_mem_size_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_mem_signed = _resp_T_1 ? io_dmem_ll_resp_bits_uop_mem_signed_0 : io_dmem_resp_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_uses_ldq = _resp_T_1 ? io_dmem_ll_resp_bits_uop_uses_ldq_0 : io_dmem_resp_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_uses_stq = _resp_T_1 ? io_dmem_ll_resp_bits_uop_uses_stq_0 : io_dmem_resp_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_unique = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_unique_0 : io_dmem_resp_0_bits_uop_is_unique_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_flush_on_commit = _resp_T_1 ? io_dmem_ll_resp_bits_uop_flush_on_commit_0 : io_dmem_resp_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_csr_cmd = _resp_T_1 ? io_dmem_ll_resp_bits_uop_csr_cmd_0 : io_dmem_resp_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_ldst_is_rs1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ldst_is_rs1_0 : io_dmem_resp_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_ldst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ldst_0 : io_dmem_resp_0_bits_uop_ldst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_lrs1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs1_0 : io_dmem_resp_0_bits_uop_lrs1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_lrs2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs2_0 : io_dmem_resp_0_bits_uop_lrs2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_lrs3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs3_0 : io_dmem_resp_0_bits_uop_lrs3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_dst_rtype = _resp_T_1 ? io_dmem_ll_resp_bits_uop_dst_rtype_0 : io_dmem_resp_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_lrs1_rtype = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs1_rtype_0 : io_dmem_resp_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_lrs2_rtype = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs2_rtype_0 : io_dmem_resp_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_frs3_en = _resp_T_1 ? io_dmem_ll_resp_bits_uop_frs3_en_0 : io_dmem_resp_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fcn_dw = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fcn_dw_0 : io_dmem_resp_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_fcn_op = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fcn_op_0 : io_dmem_resp_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_val = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_val_0 : io_dmem_resp_0_bits_uop_fp_val_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_fp_rm = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_rm_0 : io_dmem_resp_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_fp_typ = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_typ_0 : io_dmem_resp_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_xcpt_pf_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_xcpt_pf_if_0 : io_dmem_resp_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_xcpt_ae_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_xcpt_ae_if_0 : io_dmem_resp_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_xcpt_ma_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_xcpt_ma_if_0 : io_dmem_resp_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_bp_debug_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_bp_debug_if_0 : io_dmem_resp_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_bp_xcpt_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_bp_xcpt_if_0 : io_dmem_resp_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_debug_fsrc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_fsrc_0 : io_dmem_resp_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_debug_tsrc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_tsrc_0 : io_dmem_resp_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [63:0] resp_data = _resp_T_1 ? io_dmem_ll_resp_bits_data_0 : io_dmem_resp_0_bits_data_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_is_hella = _resp_T_1 ? io_dmem_ll_resp_bits_is_hella_0 : io_dmem_resp_0_bits_is_hella_0; // @[lsu.scala:211:7, :1534:{19,43}] wire _io_dmem_ll_resp_ready_T = ~io_dmem_resp_0_valid_0; // @[lsu.scala:211:7, :1534:20, :1537:32] wire _io_dmem_ll_resp_ready_T_1 = ~wb_spec_wakeups_0_valid; // @[lsu.scala:1491:29, :1537:58] assign _io_dmem_ll_resp_ready_T_2 = _io_dmem_ll_resp_ready_T & _io_dmem_ll_resp_ready_T_1; // @[lsu.scala:1537:{32,55,58}] assign io_dmem_ll_resp_ready_0 = _io_dmem_ll_resp_ready_T_2; // @[lsu.scala:211:7, :1537:55] wire _T_1507 = io_dmem_ll_resp_ready_0 & io_dmem_ll_resp_valid_0; // @[Decoupled.scala:51:35] wire _T_1162 = io_dmem_resp_0_valid_0 \| _T_1507; // @[Decoupled.scala:51:35] wire _GEN_506 = _T_1162 & resp_uop_uses_ldq; // @[lsu.scala:1534:19, :1539:33, :1540:32] wire uop_iq_type_0; // @[lsu.scala:1543:27] wire uop_iq_type_1; // @[lsu.scala:1543:27] wire uop_iq_type_2; // @[lsu.scala:1543:27] wire uop_iq_type_3; // @[lsu.scala:1543:27] wire uop_fu_code_0; // @[lsu.scala:1543:27] wire uop_fu_code_1; // @[lsu.scala:1543:27] wire uop_fu_code_2; // @[lsu.scala:1543:27] wire uop_fu_code_3; // @[lsu.scala:1543:27] wire uop_fu_code_4; // @[lsu.scala:1543:27] wire uop_fu_code_5; // @[lsu.scala:1543:27] wire uop_fu_code_6; // @[lsu.scala:1543:27] wire uop_fu_code_7; // @[lsu.scala:1543:27] wire uop_fu_code_8; // @[lsu.scala:1543:27] wire uop_fu_code_9; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ldst; // @[lsu.scala:1543:27] wire uop_fp_ctrl_wen; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ren1; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ren2; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ren3; // @[lsu.scala:1543:27] wire uop_fp_ctrl_swap12; // @[lsu.scala:1543:27] wire uop_fp_ctrl_swap23; // @[lsu.scala:1543:27] wire [1:0] uop_fp_ctrl_typeTagIn; // @[lsu.scala:1543:27] wire [1:0] uop_fp_ctrl_typeTagOut; // @[lsu.scala:1543:27] wire uop_fp_ctrl_fromint; // @[lsu.scala:1543:27] wire uop_fp_ctrl_toint; // @[lsu.scala:1543:27] wire uop_fp_ctrl_fastpipe; // @[lsu.scala:1543:27] wire uop_fp_ctrl_fma; // @[lsu.scala:1543:27] wire uop_fp_ctrl_div; // @[lsu.scala:1543:27] wire uop_fp_ctrl_sqrt; // @[lsu.scala:1543:27] wire uop_fp_ctrl_wflags; // @[lsu.scala:1543:27] wire uop_fp_ctrl_vec; // @[lsu.scala:1543:27] wire [31:0] uop_inst; // @[lsu.scala:1543:27] wire [31:0] uop_debug_inst; // @[lsu.scala:1543:27] wire uop_is_rvc; // @[lsu.scala:1543:27] wire [39:0] uop_debug_pc; // @[lsu.scala:1543:27] wire uop_iw_issued; // @[lsu.scala:1543:27] wire uop_iw_issued_partial_agen; // @[lsu.scala:1543:27] wire uop_iw_issued_partial_dgen; // @[lsu.scala:1543:27] wire [1:0] uop_iw_p1_speculative_child; // @[lsu.scala:1543:27] wire [1:0] uop_iw_p2_speculative_child; // @[lsu.scala:1543:27] wire uop_iw_p1_bypass_hint; // @[lsu.scala:1543:27] wire uop_iw_p2_bypass_hint; // @[lsu.scala:1543:27] wire uop_iw_p3_bypass_hint; // @[lsu.scala:1543:27] wire [1:0] uop_dis_col_sel; // @[lsu.scala:1543:27] wire [11:0] uop_br_mask; // @[lsu.scala:1543:27] wire [3:0] uop_br_tag; // @[lsu.scala:1543:27] wire [3:0] uop_br_type; // @[lsu.scala:1543:27] wire uop_is_sfb; // @[lsu.scala:1543:27] wire uop_is_fence; // @[lsu.scala:1543:27] wire uop_is_fencei; // @[lsu.scala:1543:27] wire uop_is_sfence; // @[lsu.scala:1543:27] wire uop_is_amo; // @[lsu.scala:1543:27] wire uop_is_eret; // @[lsu.scala:1543:27] wire uop_is_sys_pc2epc; // @[lsu.scala:1543:27] wire uop_is_rocc; // @[lsu.scala:1543:27] wire uop_is_mov; // @[lsu.scala:1543:27] wire [4:0] uop_ftq_idx; // @[lsu.scala:1543:27] wire uop_edge_inst; // @[lsu.scala:1543:27] wire [5:0] uop_pc_lob; // @[lsu.scala:1543:27] wire uop_taken; // @[lsu.scala:1543:27] wire uop_imm_rename; // @[lsu.scala:1543:27] wire [2:0] uop_imm_sel; // @[lsu.scala:1543:27] wire [4:0] uop_pimm; // @[lsu.scala:1543:27] wire [19:0] uop_imm_packed; // @[lsu.scala:1543:27] wire [1:0] uop_op1_sel; // @[lsu.scala:1543:27] wire [2:0] uop_op2_sel; // @[lsu.scala:1543:27] wire [5:0] uop_rob_idx; // @[lsu.scala:1543:27] wire [3:0] uop_ldq_idx; // @[lsu.scala:1543:27] wire [3:0] uop_stq_idx; // @[lsu.scala:1543:27] wire [1:0] uop_rxq_idx; // @[lsu.scala:1543:27] wire [6:0] uop_pdst; // @[lsu.scala:1543:27] wire [6:0] uop_prs1; // @[lsu.scala:1543:27] wire [6:0] uop_prs2; // @[lsu.scala:1543:27] wire [6:0] uop_prs3; // @[lsu.scala:1543:27] wire [4:0] uop_ppred; // @[lsu.scala:1543:27] wire uop_prs1_busy; // @[lsu.scala:1543:27] wire uop_prs2_busy; // @[lsu.scala:1543:27] wire uop_prs3_busy; // @[lsu.scala:1543:27] wire uop_ppred_busy; // @[lsu.scala:1543:27] wire [6:0] uop_stale_pdst; // @[lsu.scala:1543:27] wire uop_exception; // @[lsu.scala:1543:27] wire [63:0] uop_exc_cause; // @[lsu.scala:1543:27] wire [4:0] uop_mem_cmd; // @[lsu.scala:1543:27] wire [1:0] uop_mem_size; // @[lsu.scala:1543:27] wire uop_mem_signed; // @[lsu.scala:1543:27] wire uop_uses_ldq; // @[lsu.scala:1543:27] wire uop_uses_stq; // @[lsu.scala:1543:27] wire uop_is_unique; // @[lsu.scala:1543:27] wire uop_flush_on_commit; // @[lsu.scala:1543:27] wire [2:0] uop_csr_cmd; // @[lsu.scala:1543:27] wire uop_ldst_is_rs1; // @[lsu.scala:1543:27] wire [5:0] uop_ldst; // @[lsu.scala:1543:27] wire [5:0] uop_lrs1; // @[lsu.scala:1543:27] wire [5:0] uop_lrs2; // @[lsu.scala:1543:27] wire [5:0] uop_lrs3; // @[lsu.scala:1543:27] wire [1:0] uop_dst_rtype; // @[lsu.scala:1543:27] wire [1:0] uop_lrs1_rtype; // @[lsu.scala:1543:27] wire [1:0] uop_lrs2_rtype; // @[lsu.scala:1543:27] wire uop_frs3_en; // @[lsu.scala:1543:27] wire uop_fcn_dw; // @[lsu.scala:1543:27] wire [4:0] uop_fcn_op; // @[lsu.scala:1543:27] wire uop_fp_val; // @[lsu.scala:1543:27] wire [2:0] uop_fp_rm; // @[lsu.scala:1543:27] wire [1:0] uop_fp_typ; // @[lsu.scala:1543:27] wire uop_xcpt_pf_if; // @[lsu.scala:1543:27] wire uop_xcpt_ae_if; // @[lsu.scala:1543:27] wire uop_xcpt_ma_if; // @[lsu.scala:1543:27] wire uop_bp_debug_if; // @[lsu.scala:1543:27] wire uop_bp_xcpt_if; // @[lsu.scala:1543:27] wire [2:0] uop_debug_fsrc; // @[lsu.scala:1543:27] wire [2:0] uop_debug_tsrc; // @[lsu.scala:1543:27] assign uop_inst = _GEN_76[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_inst = _GEN_77[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_rvc = _GEN_78[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_pc = _GEN_79[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_0 = _GEN_80[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_1 = _GEN_81[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_2 = _GEN_82[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_3 = _GEN_83[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_0 = _GEN_84[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_1 = _GEN_85[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_2 = _GEN_86[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_3 = _GEN_87[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_4 = _GEN_88[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_5 = _GEN_89[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_6 = _GEN_90[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_7 = _GEN_91[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_8 = _GEN_92[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_9 = _GEN_93[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_issued = _GEN_94[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_issued_partial_agen = _GEN_95[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_issued_partial_dgen = _GEN_96[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p1_speculative_child = _GEN_97[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p2_speculative_child = _GEN_98[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p1_bypass_hint = _GEN_99[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p2_bypass_hint = _GEN_100[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p3_bypass_hint = _GEN_101[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_dis_col_sel = _GEN_102[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_br_mask = _GEN_103[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_br_tag = _GEN_104[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_br_type = _GEN_105[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_sfb = _GEN_106[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_fence = _GEN_107[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_fencei = _GEN_108[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_sfence = _GEN_109[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_amo = _GEN_110[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_eret = _GEN_111[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_sys_pc2epc = _GEN_112[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_rocc = _GEN_113[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_mov = _GEN_114[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ftq_idx = _GEN_115[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_edge_inst = _GEN_116[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_pc_lob = _GEN_117[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_taken = _GEN_118[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_imm_rename = _GEN_119[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_imm_sel = _GEN_120[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_pimm = _GEN_121[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_imm_packed = _GEN_122[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_op1_sel = _GEN_123[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_op2_sel = _GEN_124[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ldst = _GEN_125[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_wen = _GEN_126[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ren1 = _GEN_127[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ren2 = _GEN_128[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ren3 = _GEN_129[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_swap12 = _GEN_130[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_swap23 = _GEN_131[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_typeTagIn = _GEN_132[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_typeTagOut = _GEN_133[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_fromint = _GEN_134[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_toint = _GEN_135[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_fastpipe = _GEN_136[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_fma = _GEN_137[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_div = _GEN_138[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_sqrt = _GEN_139[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_wflags = _GEN_140[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_vec = _GEN_141[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_rob_idx = _GEN_142[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ldq_idx = _GEN_143[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_stq_idx = _GEN_144[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_rxq_idx = _GEN_145[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_pdst = _GEN_146[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs1 = _GEN_147[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs2 = _GEN_148[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs3 = _GEN_149[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ppred = _GEN_150[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs1_busy = _GEN_151[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs2_busy = _GEN_152[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs3_busy = _GEN_153[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ppred_busy = _GEN_154[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_stale_pdst = _GEN_155[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_exception = _GEN_156[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_exc_cause = _GEN_157[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_mem_cmd = _GEN_158[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_mem_size = _GEN_159[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_mem_signed = _GEN_160[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_uses_ldq = _GEN_161[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_uses_stq = _GEN_162[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_unique = _GEN_163[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_flush_on_commit = _GEN_164[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_csr_cmd = _GEN_165[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ldst_is_rs1 = _GEN_166[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ldst = _GEN_167[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs1 = _GEN_168[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs2 = _GEN_169[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs3 = _GEN_170[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_dst_rtype = _GEN_171[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs1_rtype = _GEN_172[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs2_rtype = _GEN_173[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_frs3_en = _GEN_174[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fcn_dw = _GEN_175[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fcn_op = _GEN_176[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_val = _GEN_177[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_rm = _GEN_178[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_typ = _GEN_179[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_xcpt_pf_if = _GEN_180[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_xcpt_ae_if = _GEN_181[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_xcpt_ma_if = _GEN_182[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_bp_debug_if = _GEN_183[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_bp_xcpt_if = _GEN_184[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_fsrc = _GEN_185[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_tsrc = _GEN_186[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] wire send_iresp = uop_dst_rtype == 2'h0; // @[lsu.scala:1543:27, :1544:40] wire send_fresp = uop_dst_rtype == 2'h1; // @[lsu.scala:1543:27, :1545:40] wire _ldq_will_succeed_T = iresp_0_valid \| fresp_0_valid; // @[lsu.scala:1477:19, :1478:19, :1560:54] wire _GEN_507 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h0; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_508 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h1; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_509 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h2; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_510 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h3; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_511 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h4; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_512 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h5; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_513 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h6; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_514 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h7; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_515 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h8; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_516 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h9; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_517 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'hA; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_518 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'hB; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_519 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'hC; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_520 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'hD; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_521 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'hE; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_522 = _T_1162 & resp_uop_uses_ldq & (&resp_uop_ldq_idx); // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] assign dmem_resp_fired_0 = _T_1162 & (resp_uop_uses_stq \| resp_uop_uses_ldq); // @[lsu.scala:1497:33, :1534:19, :1539:{33,83}, :1540:32, :1558:28, :1571:7, :1574:28] wire _GEN_523 = _T_1162 & (resp_uop_uses_stq \| resp_uop_uses_ldq & send_iresp); // @[lsu.scala:1481:20, :1534:19, :1539:{33,83}, :1540:32, :1544:40, :1549:28, :1571:7, :1575:28] wire _T_1176 = dmem_resp_fired_0 & wb_ldst_forward_valid_0; // @[lsu.scala:1172:38, :1497:33, :1594:30] wire _T_1178 = ~dmem_resp_fired_0 & wb_ldst_forward_valid_0; // @[lsu.scala:1172:38, :1497:33, :1598:{18,38}] wire [1:0] size; // @[AMOALU.scala:11:18] assign size = _GEN_283[wb_ldst_forward_stq_idx_0]; // @[AMOALU.scala:11:18, :12:8] wire [3:0][63:0] _GEN_524 = {{_GEN_315[wb_ldst_forward_stq_idx_0]}, {{2{_GEN_315[wb_ldst_forward_stq_idx_0][31:0]}}}, {{2{{2{_GEN_315[wb_ldst_forward_stq_idx_0][15:0]}}}}}, {{2{{2{{2{_GEN_315[wb_ldst_forward_stq_idx_0][7:0]}}}}}}}}; // @[AMOALU.scala:29:{13,19,32,69}] wire _GEN_525 = wb_ldst_forward_e_0_uop_dst_rtype == 2'h0; // @[lsu.scala:321:49, :1612:60] wire _wb_slow_wakeups_0_valid_T; // @[lsu.scala:1612:60] assign _wb_slow_wakeups_0_valid_T = _GEN_525; // @[lsu.scala:1612:60] wire _iresp_0_valid_T; // @[lsu.scala:1618:48] assign _iresp_0_valid_T = _GEN_525; // @[lsu.scala:1612:60, :1618:48] wire _GEN_526 = _T_1176 \| ~_T_1178; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1598:38, :1599:5] assign wb_slow_wakeups_0_valid = _GEN_526 ? _GEN_523 : _wb_slow_wakeups_0_valid_T; // @[lsu.scala:1481:20, :1494:29, :1539:83, :1571:7, :1595:5, :1599:5, :1612:60] wire [31:0] _GEN_527 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_200[resp_uop_stq_idx] : uop_inst) : wb_ldst_forward_e_0_uop_inst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_inst = _GEN_527; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_inst = _GEN_527; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [31:0] _GEN_528 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_201[resp_uop_stq_idx] : uop_debug_inst) : wb_ldst_forward_e_0_uop_debug_inst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_inst = _GEN_528; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_inst = _GEN_528; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_529 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_202[resp_uop_stq_idx] : uop_is_rvc) : wb_ldst_forward_e_0_uop_is_rvc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_rvc = _GEN_529; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_rvc = _GEN_529; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [39:0] _GEN_530 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_203[resp_uop_stq_idx] : uop_debug_pc) : wb_ldst_forward_e_0_uop_debug_pc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_pc = _GEN_530; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_pc = _GEN_530; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_531 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_204[resp_uop_stq_idx] : uop_iq_type_0) : wb_ldst_forward_e_0_uop_iq_type_0; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_0 = _GEN_531; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_0 = _GEN_531; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_532 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_205[resp_uop_stq_idx] : uop_iq_type_1) : wb_ldst_forward_e_0_uop_iq_type_1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_1 = _GEN_532; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_1 = _GEN_532; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_533 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_206[resp_uop_stq_idx] : uop_iq_type_2) : wb_ldst_forward_e_0_uop_iq_type_2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_2 = _GEN_533; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_2 = _GEN_533; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_534 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_207[resp_uop_stq_idx] : uop_iq_type_3) : wb_ldst_forward_e_0_uop_iq_type_3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_3 = _GEN_534; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_3 = _GEN_534; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_535 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_208[resp_uop_stq_idx] : uop_fu_code_0) : wb_ldst_forward_e_0_uop_fu_code_0; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_0 = _GEN_535; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_0 = _GEN_535; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_536 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_209[resp_uop_stq_idx] : uop_fu_code_1) : wb_ldst_forward_e_0_uop_fu_code_1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_1 = _GEN_536; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_1 = _GEN_536; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_537 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_210[resp_uop_stq_idx] : uop_fu_code_2) : wb_ldst_forward_e_0_uop_fu_code_2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_2 = _GEN_537; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_2 = _GEN_537; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_538 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_211[resp_uop_stq_idx] : uop_fu_code_3) : wb_ldst_forward_e_0_uop_fu_code_3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_3 = _GEN_538; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_3 = _GEN_538; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_539 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_212[resp_uop_stq_idx] : uop_fu_code_4) : wb_ldst_forward_e_0_uop_fu_code_4; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_4 = _GEN_539; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_4 = _GEN_539; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_540 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_213[resp_uop_stq_idx] : uop_fu_code_5) : wb_ldst_forward_e_0_uop_fu_code_5; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_5 = _GEN_540; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_5 = _GEN_540; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_541 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_214[resp_uop_stq_idx] : uop_fu_code_6) : wb_ldst_forward_e_0_uop_fu_code_6; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_6 = _GEN_541; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_6 = _GEN_541; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_542 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_215[resp_uop_stq_idx] : uop_fu_code_7) : wb_ldst_forward_e_0_uop_fu_code_7; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_7 = _GEN_542; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_7 = _GEN_542; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_543 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_216[resp_uop_stq_idx] : uop_fu_code_8) : wb_ldst_forward_e_0_uop_fu_code_8; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_8 = _GEN_543; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_8 = _GEN_543; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_544 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_217[resp_uop_stq_idx] : uop_fu_code_9) : wb_ldst_forward_e_0_uop_fu_code_9; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_9 = _GEN_544; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_9 = _GEN_544; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_545 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_218[resp_uop_stq_idx] : uop_iw_issued) : wb_ldst_forward_e_0_uop_iw_issued; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_issued = _GEN_545; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_issued = _GEN_545; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_546 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_219[resp_uop_stq_idx] : uop_iw_issued_partial_agen) : wb_ldst_forward_e_0_uop_iw_issued_partial_agen; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_issued_partial_agen = _GEN_546; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_issued_partial_agen = _GEN_546; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_547 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_220[resp_uop_stq_idx] : uop_iw_issued_partial_dgen) : wb_ldst_forward_e_0_uop_iw_issued_partial_dgen; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_issued_partial_dgen = _GEN_547; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_issued_partial_dgen = _GEN_547; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_548 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_221[resp_uop_stq_idx] : uop_iw_p1_speculative_child) : wb_ldst_forward_e_0_uop_iw_p1_speculative_child; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p1_speculative_child = _GEN_548; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p1_speculative_child = _GEN_548; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_549 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_222[resp_uop_stq_idx] : uop_iw_p2_speculative_child) : wb_ldst_forward_e_0_uop_iw_p2_speculative_child; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p2_speculative_child = _GEN_549; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p2_speculative_child = _GEN_549; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_550 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_223[resp_uop_stq_idx] : uop_iw_p1_bypass_hint) : wb_ldst_forward_e_0_uop_iw_p1_bypass_hint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p1_bypass_hint = _GEN_550; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p1_bypass_hint = _GEN_550; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_551 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_224[resp_uop_stq_idx] : uop_iw_p2_bypass_hint) : wb_ldst_forward_e_0_uop_iw_p2_bypass_hint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p2_bypass_hint = _GEN_551; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p2_bypass_hint = _GEN_551; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_552 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_225[resp_uop_stq_idx] : uop_iw_p3_bypass_hint) : wb_ldst_forward_e_0_uop_iw_p3_bypass_hint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p3_bypass_hint = _GEN_552; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p3_bypass_hint = _GEN_552; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_553 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_226[resp_uop_stq_idx] : uop_dis_col_sel) : wb_ldst_forward_e_0_uop_dis_col_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_dis_col_sel = _GEN_553; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_dis_col_sel = _GEN_553; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [11:0] _GEN_554 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_227[resp_uop_stq_idx] : uop_br_mask) : wb_ldst_forward_e_0_uop_br_mask; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_br_mask = _GEN_554; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_br_mask = _GEN_554; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [3:0] _GEN_555 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_228[resp_uop_stq_idx] : uop_br_tag) : wb_ldst_forward_e_0_uop_br_tag; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_br_tag = _GEN_555; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_br_tag = _GEN_555; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [3:0] _GEN_556 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_229[resp_uop_stq_idx] : uop_br_type) : wb_ldst_forward_e_0_uop_br_type; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_br_type = _GEN_556; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_br_type = _GEN_556; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_557 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_230[resp_uop_stq_idx] : uop_is_sfb) : wb_ldst_forward_e_0_uop_is_sfb; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_sfb = _GEN_557; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_sfb = _GEN_557; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_558 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_231[resp_uop_stq_idx] : uop_is_fence) : wb_ldst_forward_e_0_uop_is_fence; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_fence = _GEN_558; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_fence = _GEN_558; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_559 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_232[resp_uop_stq_idx] : uop_is_fencei) : wb_ldst_forward_e_0_uop_is_fencei; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_fencei = _GEN_559; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_fencei = _GEN_559; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_560 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_233[resp_uop_stq_idx] : uop_is_sfence) : wb_ldst_forward_e_0_uop_is_sfence; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_sfence = _GEN_560; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_sfence = _GEN_560; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_561 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_234[resp_uop_stq_idx] : uop_is_amo) : wb_ldst_forward_e_0_uop_is_amo; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_amo = _GEN_561; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_amo = _GEN_561; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_562 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_235[resp_uop_stq_idx] : uop_is_eret) : wb_ldst_forward_e_0_uop_is_eret; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_eret = _GEN_562; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_eret = _GEN_562; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_563 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_236[resp_uop_stq_idx] : uop_is_sys_pc2epc) : wb_ldst_forward_e_0_uop_is_sys_pc2epc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_sys_pc2epc = _GEN_563; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_sys_pc2epc = _GEN_563; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_564 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_237[resp_uop_stq_idx] : uop_is_rocc) : wb_ldst_forward_e_0_uop_is_rocc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_rocc = _GEN_564; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_rocc = _GEN_564; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_565 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_238[resp_uop_stq_idx] : uop_is_mov) : wb_ldst_forward_e_0_uop_is_mov; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_mov = _GEN_565; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_mov = _GEN_565; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_566 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_239[resp_uop_stq_idx] : uop_ftq_idx) : wb_ldst_forward_e_0_uop_ftq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ftq_idx = _GEN_566; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ftq_idx = _GEN_566; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_567 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_240[resp_uop_stq_idx] : uop_edge_inst) : wb_ldst_forward_e_0_uop_edge_inst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_edge_inst = _GEN_567; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_edge_inst = _GEN_567; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_568 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_241[resp_uop_stq_idx] : uop_pc_lob) : wb_ldst_forward_e_0_uop_pc_lob; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_pc_lob = _GEN_568; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_pc_lob = _GEN_568; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_569 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_242[resp_uop_stq_idx] : uop_taken) : wb_ldst_forward_e_0_uop_taken; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_taken = _GEN_569; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_taken = _GEN_569; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_570 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_243[resp_uop_stq_idx] : uop_imm_rename) : wb_ldst_forward_e_0_uop_imm_rename; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_imm_rename = _GEN_570; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_imm_rename = _GEN_570; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_571 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_244[resp_uop_stq_idx] : uop_imm_sel) : wb_ldst_forward_e_0_uop_imm_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_imm_sel = _GEN_571; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_imm_sel = _GEN_571; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_572 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_245[resp_uop_stq_idx] : uop_pimm) : wb_ldst_forward_e_0_uop_pimm; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_pimm = _GEN_572; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_pimm = _GEN_572; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [19:0] _GEN_573 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_246[resp_uop_stq_idx] : uop_imm_packed) : wb_ldst_forward_e_0_uop_imm_packed; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_imm_packed = _GEN_573; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_imm_packed = _GEN_573; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_574 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_247[resp_uop_stq_idx] : uop_op1_sel) : wb_ldst_forward_e_0_uop_op1_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_op1_sel = _GEN_574; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_op1_sel = _GEN_574; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_575 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_248[resp_uop_stq_idx] : uop_op2_sel) : wb_ldst_forward_e_0_uop_op2_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_op2_sel = _GEN_575; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_op2_sel = _GEN_575; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_576 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_249[resp_uop_stq_idx] : uop_fp_ctrl_ldst) : wb_ldst_forward_e_0_uop_fp_ctrl_ldst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ldst = _GEN_576; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ldst = _GEN_576; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_577 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_250[resp_uop_stq_idx] : uop_fp_ctrl_wen) : wb_ldst_forward_e_0_uop_fp_ctrl_wen; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_wen = _GEN_577; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_wen = _GEN_577; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_578 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_251[resp_uop_stq_idx] : uop_fp_ctrl_ren1) : wb_ldst_forward_e_0_uop_fp_ctrl_ren1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ren1 = _GEN_578; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ren1 = _GEN_578; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_579 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_252[resp_uop_stq_idx] : uop_fp_ctrl_ren2) : wb_ldst_forward_e_0_uop_fp_ctrl_ren2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ren2 = _GEN_579; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ren2 = _GEN_579; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_580 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_253[resp_uop_stq_idx] : uop_fp_ctrl_ren3) : wb_ldst_forward_e_0_uop_fp_ctrl_ren3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ren3 = _GEN_580; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ren3 = _GEN_580; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_581 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_254[resp_uop_stq_idx] : uop_fp_ctrl_swap12) : wb_ldst_forward_e_0_uop_fp_ctrl_swap12; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_swap12 = _GEN_581; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_swap12 = _GEN_581; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_582 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_255[resp_uop_stq_idx] : uop_fp_ctrl_swap23) : wb_ldst_forward_e_0_uop_fp_ctrl_swap23; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_swap23 = _GEN_582; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_swap23 = _GEN_582; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_583 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_256[resp_uop_stq_idx] : uop_fp_ctrl_typeTagIn) : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagIn; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_typeTagIn = _GEN_583; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn = _GEN_583; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_584 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_257[resp_uop_stq_idx] : uop_fp_ctrl_typeTagOut) : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagOut; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_typeTagOut = _GEN_584; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut = _GEN_584; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_585 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_258[resp_uop_stq_idx] : uop_fp_ctrl_fromint) : wb_ldst_forward_e_0_uop_fp_ctrl_fromint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_fromint = _GEN_585; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_fromint = _GEN_585; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_586 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_259[resp_uop_stq_idx] : uop_fp_ctrl_toint) : wb_ldst_forward_e_0_uop_fp_ctrl_toint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_toint = _GEN_586; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_toint = _GEN_586; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_587 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_260[resp_uop_stq_idx] : uop_fp_ctrl_fastpipe) : wb_ldst_forward_e_0_uop_fp_ctrl_fastpipe; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_fastpipe = _GEN_587; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_fastpipe = _GEN_587; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_588 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_261[resp_uop_stq_idx] : uop_fp_ctrl_fma) : wb_ldst_forward_e_0_uop_fp_ctrl_fma; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_fma = _GEN_588; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_fma = _GEN_588; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_589 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_262[resp_uop_stq_idx] : uop_fp_ctrl_div) : wb_ldst_forward_e_0_uop_fp_ctrl_div; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_div = _GEN_589; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_div = _GEN_589; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_590 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_263[resp_uop_stq_idx] : uop_fp_ctrl_sqrt) : wb_ldst_forward_e_0_uop_fp_ctrl_sqrt; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_sqrt = _GEN_590; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_sqrt = _GEN_590; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_591 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_264[resp_uop_stq_idx] : uop_fp_ctrl_wflags) : wb_ldst_forward_e_0_uop_fp_ctrl_wflags; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_wflags = _GEN_591; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_wflags = _GEN_591; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_592 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_265[resp_uop_stq_idx] : uop_fp_ctrl_vec) : wb_ldst_forward_e_0_uop_fp_ctrl_vec; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_vec = _GEN_592; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_vec = _GEN_592; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_593 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_266[resp_uop_stq_idx] : uop_rob_idx) : wb_ldst_forward_e_0_uop_rob_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_rob_idx = _GEN_593; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_rob_idx = _GEN_593; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [3:0] _GEN_594 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_267[resp_uop_stq_idx] : uop_ldq_idx) : wb_ldst_forward_e_0_uop_ldq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ldq_idx = _GEN_594; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ldq_idx = _GEN_594; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [3:0] _GEN_595 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_268[resp_uop_stq_idx] : uop_stq_idx) : wb_ldst_forward_e_0_uop_stq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_stq_idx = _GEN_595; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_stq_idx = _GEN_595; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_596 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_269[resp_uop_stq_idx] : uop_rxq_idx) : wb_ldst_forward_e_0_uop_rxq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_rxq_idx = _GEN_596; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_rxq_idx = _GEN_596; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_597 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_270[resp_uop_stq_idx] : uop_pdst) : wb_ldst_forward_e_0_uop_pdst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_pdst = _GEN_597; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_pdst = _GEN_597; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_598 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_271[resp_uop_stq_idx] : uop_prs1) : wb_ldst_forward_e_0_uop_prs1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs1 = _GEN_598; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs1 = _GEN_598; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_599 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_272[resp_uop_stq_idx] : uop_prs2) : wb_ldst_forward_e_0_uop_prs2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs2 = _GEN_599; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs2 = _GEN_599; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_600 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_273[resp_uop_stq_idx] : uop_prs3) : wb_ldst_forward_e_0_uop_prs3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs3 = _GEN_600; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs3 = _GEN_600; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_601 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_274[resp_uop_stq_idx] : uop_ppred) : wb_ldst_forward_e_0_uop_ppred; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ppred = _GEN_601; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ppred = _GEN_601; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_602 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_275[resp_uop_stq_idx] : uop_prs1_busy) : wb_ldst_forward_e_0_uop_prs1_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs1_busy = _GEN_602; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs1_busy = _GEN_602; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_603 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_276[resp_uop_stq_idx] : uop_prs2_busy) : wb_ldst_forward_e_0_uop_prs2_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs2_busy = _GEN_603; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs2_busy = _GEN_603; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_604 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_277[resp_uop_stq_idx] : uop_prs3_busy) : wb_ldst_forward_e_0_uop_prs3_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs3_busy = _GEN_604; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs3_busy = _GEN_604; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_605 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_278[resp_uop_stq_idx] : uop_ppred_busy) : wb_ldst_forward_e_0_uop_ppred_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ppred_busy = _GEN_605; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ppred_busy = _GEN_605; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_606 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_279[resp_uop_stq_idx] : uop_stale_pdst) : wb_ldst_forward_e_0_uop_stale_pdst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_stale_pdst = _GEN_606; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_stale_pdst = _GEN_606; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_607 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_280[resp_uop_stq_idx] : uop_exception) : wb_ldst_forward_e_0_uop_exception; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_exception = _GEN_607; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_exception = _GEN_607; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [63:0] _GEN_608 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_281[resp_uop_stq_idx] : uop_exc_cause) : wb_ldst_forward_e_0_uop_exc_cause; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_exc_cause = _GEN_608; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_exc_cause = _GEN_608; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_609 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_282[resp_uop_stq_idx] : uop_mem_cmd) : wb_ldst_forward_e_0_uop_mem_cmd; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_mem_cmd = _GEN_609; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_mem_cmd = _GEN_609; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_610 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_283[resp_uop_stq_idx] : uop_mem_size) : wb_ldst_forward_e_0_uop_mem_size; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_mem_size = _GEN_610; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_mem_size = _GEN_610; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_611 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_284[resp_uop_stq_idx] : uop_mem_signed) : wb_ldst_forward_e_0_uop_mem_signed; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_mem_signed = _GEN_611; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_mem_signed = _GEN_611; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_612 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_285[resp_uop_stq_idx] : uop_uses_ldq) : wb_ldst_forward_e_0_uop_uses_ldq; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_uses_ldq = _GEN_612; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_uses_ldq = _GEN_612; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_613 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_286[resp_uop_stq_idx] : uop_uses_stq) : wb_ldst_forward_e_0_uop_uses_stq; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_uses_stq = _GEN_613; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_uses_stq = _GEN_613; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_614 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_287[resp_uop_stq_idx] : uop_is_unique) : wb_ldst_forward_e_0_uop_is_unique; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_unique = _GEN_614; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_unique = _GEN_614; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_615 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_288[resp_uop_stq_idx] : uop_flush_on_commit) : wb_ldst_forward_e_0_uop_flush_on_commit; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_flush_on_commit = _GEN_615; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_flush_on_commit = _GEN_615; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_616 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_289[resp_uop_stq_idx] : uop_csr_cmd) : wb_ldst_forward_e_0_uop_csr_cmd; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_csr_cmd = _GEN_616; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_csr_cmd = _GEN_616; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_617 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_290[resp_uop_stq_idx] : uop_ldst_is_rs1) : wb_ldst_forward_e_0_uop_ldst_is_rs1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ldst_is_rs1 = _GEN_617; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ldst_is_rs1 = _GEN_617; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_618 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_291[resp_uop_stq_idx] : uop_ldst) : wb_ldst_forward_e_0_uop_ldst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ldst = _GEN_618; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ldst = _GEN_618; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_619 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_292[resp_uop_stq_idx] : uop_lrs1) : wb_ldst_forward_e_0_uop_lrs1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs1 = _GEN_619; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs1 = _GEN_619; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_620 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_293[resp_uop_stq_idx] : uop_lrs2) : wb_ldst_forward_e_0_uop_lrs2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs2 = _GEN_620; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs2 = _GEN_620; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_621 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_294[resp_uop_stq_idx] : uop_lrs3) : wb_ldst_forward_e_0_uop_lrs3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs3 = _GEN_621; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs3 = _GEN_621; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_622 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_295[resp_uop_stq_idx] : uop_dst_rtype) : wb_ldst_forward_e_0_uop_dst_rtype; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_dst_rtype = _GEN_622; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_dst_rtype = _GEN_622; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_623 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_296[resp_uop_stq_idx] : uop_lrs1_rtype) : wb_ldst_forward_e_0_uop_lrs1_rtype; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs1_rtype = _GEN_623; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs1_rtype = _GEN_623; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_624 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_297[resp_uop_stq_idx] : uop_lrs2_rtype) : wb_ldst_forward_e_0_uop_lrs2_rtype; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs2_rtype = _GEN_624; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs2_rtype = _GEN_624; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_625 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_298[resp_uop_stq_idx] : uop_frs3_en) : wb_ldst_forward_e_0_uop_frs3_en; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_frs3_en = _GEN_625; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_frs3_en = _GEN_625; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_626 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_299[resp_uop_stq_idx] : uop_fcn_dw) : wb_ldst_forward_e_0_uop_fcn_dw; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fcn_dw = _GEN_626; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fcn_dw = _GEN_626; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_627 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_300[resp_uop_stq_idx] : uop_fcn_op) : wb_ldst_forward_e_0_uop_fcn_op; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fcn_op = _GEN_627; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fcn_op = _GEN_627; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_628 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_301[resp_uop_stq_idx] : uop_fp_val) : wb_ldst_forward_e_0_uop_fp_val; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_val = _GEN_628; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_val = _GEN_628; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_629 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_302[resp_uop_stq_idx] : uop_fp_rm) : wb_ldst_forward_e_0_uop_fp_rm; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_rm = _GEN_629; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_rm = _GEN_629; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_630 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_303[resp_uop_stq_idx] : uop_fp_typ) : wb_ldst_forward_e_0_uop_fp_typ; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_typ = _GEN_630; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_typ = _GEN_630; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_631 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_304[resp_uop_stq_idx] : uop_xcpt_pf_if) : wb_ldst_forward_e_0_uop_xcpt_pf_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_xcpt_pf_if = _GEN_631; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_xcpt_pf_if = _GEN_631; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_632 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_305[resp_uop_stq_idx] : uop_xcpt_ae_if) : wb_ldst_forward_e_0_uop_xcpt_ae_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_xcpt_ae_if = _GEN_632; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_xcpt_ae_if = _GEN_632; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_633 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_306[resp_uop_stq_idx] : uop_xcpt_ma_if) : wb_ldst_forward_e_0_uop_xcpt_ma_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_xcpt_ma_if = _GEN_633; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_xcpt_ma_if = _GEN_633; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_634 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_307[resp_uop_stq_idx] : uop_bp_debug_if) : wb_ldst_forward_e_0_uop_bp_debug_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_bp_debug_if = _GEN_634; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_bp_debug_if = _GEN_634; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_635 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_308[resp_uop_stq_idx] : uop_bp_xcpt_if) : wb_ldst_forward_e_0_uop_bp_xcpt_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_bp_xcpt_if = _GEN_635; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_bp_xcpt_if = _GEN_635; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_636 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_309[resp_uop_stq_idx] : uop_debug_fsrc) : wb_ldst_forward_e_0_uop_debug_fsrc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_fsrc = _GEN_636; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_fsrc = _GEN_636; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_637 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_310[resp_uop_stq_idx] : uop_debug_tsrc) : wb_ldst_forward_e_0_uop_debug_tsrc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_tsrc = _GEN_637; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_tsrc = _GEN_637; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] assign iresp_0_valid = _GEN_526 ? _GEN_523 : _iresp_0_valid_T; // @[lsu.scala:1477:19, :1481:20, :1539:83, :1571:7, :1595:5, :1599:5, :1618:48] wire _fresp_0_valid_T = wb_ldst_forward_e_0_uop_dst_rtype == 2'h1; // @[lsu.scala:321:49, :1619:48] assign fresp_0_valid = _GEN_526 ? _GEN_506 & send_fresp : _fresp_0_valid_T; // @[lsu.scala:1478:19, :1483:20, :1539:83, :1540:32, :1545:40, :1554:28, :1595:5, :1599:5, :1619:48] assign fresp_0_bits_uop_inst = _GEN_526 ? uop_inst : wb_ldst_forward_e_0_uop_inst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_inst = _GEN_526 ? uop_debug_inst : wb_ldst_forward_e_0_uop_debug_inst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_rvc = _GEN_526 ? uop_is_rvc : wb_ldst_forward_e_0_uop_is_rvc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_pc = _GEN_526 ? uop_debug_pc : wb_ldst_forward_e_0_uop_debug_pc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_0 = _GEN_526 ? uop_iq_type_0 : wb_ldst_forward_e_0_uop_iq_type_0; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_1 = _GEN_526 ? uop_iq_type_1 : wb_ldst_forward_e_0_uop_iq_type_1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_2 = _GEN_526 ? uop_iq_type_2 : wb_ldst_forward_e_0_uop_iq_type_2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_3 = _GEN_526 ? uop_iq_type_3 : wb_ldst_forward_e_0_uop_iq_type_3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_0 = _GEN_526 ? uop_fu_code_0 : wb_ldst_forward_e_0_uop_fu_code_0; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_1 = _GEN_526 ? uop_fu_code_1 : wb_ldst_forward_e_0_uop_fu_code_1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_2 = _GEN_526 ? uop_fu_code_2 : wb_ldst_forward_e_0_uop_fu_code_2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_3 = _GEN_526 ? uop_fu_code_3 : wb_ldst_forward_e_0_uop_fu_code_3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_4 = _GEN_526 ? uop_fu_code_4 : wb_ldst_forward_e_0_uop_fu_code_4; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_5 = _GEN_526 ? uop_fu_code_5 : wb_ldst_forward_e_0_uop_fu_code_5; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_6 = _GEN_526 ? uop_fu_code_6 : wb_ldst_forward_e_0_uop_fu_code_6; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_7 = _GEN_526 ? uop_fu_code_7 : wb_ldst_forward_e_0_uop_fu_code_7; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_8 = _GEN_526 ? uop_fu_code_8 : wb_ldst_forward_e_0_uop_fu_code_8; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_9 = _GEN_526 ? uop_fu_code_9 : wb_ldst_forward_e_0_uop_fu_code_9; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_issued = _GEN_526 ? uop_iw_issued : wb_ldst_forward_e_0_uop_iw_issued; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_issued_partial_agen = _GEN_526 ? uop_iw_issued_partial_agen : wb_ldst_forward_e_0_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_issued_partial_dgen = _GEN_526 ? uop_iw_issued_partial_dgen : wb_ldst_forward_e_0_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p1_speculative_child = _GEN_526 ? uop_iw_p1_speculative_child : wb_ldst_forward_e_0_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p2_speculative_child = _GEN_526 ? uop_iw_p2_speculative_child : wb_ldst_forward_e_0_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p1_bypass_hint = _GEN_526 ? uop_iw_p1_bypass_hint : wb_ldst_forward_e_0_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p2_bypass_hint = _GEN_526 ? uop_iw_p2_bypass_hint : wb_ldst_forward_e_0_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p3_bypass_hint = _GEN_526 ? uop_iw_p3_bypass_hint : wb_ldst_forward_e_0_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_dis_col_sel = _GEN_526 ? uop_dis_col_sel : wb_ldst_forward_e_0_uop_dis_col_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_br_mask = _GEN_526 ? uop_br_mask : wb_ldst_forward_e_0_uop_br_mask; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_br_tag = _GEN_526 ? uop_br_tag : wb_ldst_forward_e_0_uop_br_tag; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_br_type = _GEN_526 ? uop_br_type : wb_ldst_forward_e_0_uop_br_type; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_sfb = _GEN_526 ? uop_is_sfb : wb_ldst_forward_e_0_uop_is_sfb; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_fence = _GEN_526 ? uop_is_fence : wb_ldst_forward_e_0_uop_is_fence; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_fencei = _GEN_526 ? uop_is_fencei : wb_ldst_forward_e_0_uop_is_fencei; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_sfence = _GEN_526 ? uop_is_sfence : wb_ldst_forward_e_0_uop_is_sfence; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_amo = _GEN_526 ? uop_is_amo : wb_ldst_forward_e_0_uop_is_amo; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_eret = _GEN_526 ? uop_is_eret : wb_ldst_forward_e_0_uop_is_eret; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_sys_pc2epc = _GEN_526 ? uop_is_sys_pc2epc : wb_ldst_forward_e_0_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_rocc = _GEN_526 ? uop_is_rocc : wb_ldst_forward_e_0_uop_is_rocc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_mov = _GEN_526 ? uop_is_mov : wb_ldst_forward_e_0_uop_is_mov; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ftq_idx = _GEN_526 ? uop_ftq_idx : wb_ldst_forward_e_0_uop_ftq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_edge_inst = _GEN_526 ? uop_edge_inst : wb_ldst_forward_e_0_uop_edge_inst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_pc_lob = _GEN_526 ? uop_pc_lob : wb_ldst_forward_e_0_uop_pc_lob; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_taken = _GEN_526 ? uop_taken : wb_ldst_forward_e_0_uop_taken; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_imm_rename = _GEN_526 ? uop_imm_rename : wb_ldst_forward_e_0_uop_imm_rename; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_imm_sel = _GEN_526 ? uop_imm_sel : wb_ldst_forward_e_0_uop_imm_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_pimm = _GEN_526 ? uop_pimm : wb_ldst_forward_e_0_uop_pimm; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_imm_packed = _GEN_526 ? uop_imm_packed : wb_ldst_forward_e_0_uop_imm_packed; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_op1_sel = _GEN_526 ? uop_op1_sel : wb_ldst_forward_e_0_uop_op1_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_op2_sel = _GEN_526 ? uop_op2_sel : wb_ldst_forward_e_0_uop_op2_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ldst = _GEN_526 ? uop_fp_ctrl_ldst : wb_ldst_forward_e_0_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_wen = _GEN_526 ? uop_fp_ctrl_wen : wb_ldst_forward_e_0_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ren1 = _GEN_526 ? uop_fp_ctrl_ren1 : wb_ldst_forward_e_0_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ren2 = _GEN_526 ? uop_fp_ctrl_ren2 : wb_ldst_forward_e_0_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ren3 = _GEN_526 ? uop_fp_ctrl_ren3 : wb_ldst_forward_e_0_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_swap12 = _GEN_526 ? uop_fp_ctrl_swap12 : wb_ldst_forward_e_0_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_swap23 = _GEN_526 ? uop_fp_ctrl_swap23 : wb_ldst_forward_e_0_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_typeTagIn = _GEN_526 ? uop_fp_ctrl_typeTagIn : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_typeTagOut = _GEN_526 ? uop_fp_ctrl_typeTagOut : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_fromint = _GEN_526 ? uop_fp_ctrl_fromint : wb_ldst_forward_e_0_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_toint = _GEN_526 ? uop_fp_ctrl_toint : wb_ldst_forward_e_0_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_fastpipe = _GEN_526 ? uop_fp_ctrl_fastpipe : wb_ldst_forward_e_0_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_fma = _GEN_526 ? uop_fp_ctrl_fma : wb_ldst_forward_e_0_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_div = _GEN_526 ? uop_fp_ctrl_div : wb_ldst_forward_e_0_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_sqrt = _GEN_526 ? uop_fp_ctrl_sqrt : wb_ldst_forward_e_0_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_wflags = _GEN_526 ? uop_fp_ctrl_wflags : wb_ldst_forward_e_0_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_vec = _GEN_526 ? uop_fp_ctrl_vec : wb_ldst_forward_e_0_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_rob_idx = _GEN_526 ? uop_rob_idx : wb_ldst_forward_e_0_uop_rob_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ldq_idx = _GEN_526 ? uop_ldq_idx : wb_ldst_forward_e_0_uop_ldq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_stq_idx = _GEN_526 ? uop_stq_idx : wb_ldst_forward_e_0_uop_stq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_rxq_idx = _GEN_526 ? uop_rxq_idx : wb_ldst_forward_e_0_uop_rxq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_pdst = _GEN_526 ? uop_pdst : wb_ldst_forward_e_0_uop_pdst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs1 = _GEN_526 ? uop_prs1 : wb_ldst_forward_e_0_uop_prs1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs2 = _GEN_526 ? uop_prs2 : wb_ldst_forward_e_0_uop_prs2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs3 = _GEN_526 ? uop_prs3 : wb_ldst_forward_e_0_uop_prs3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ppred = _GEN_526 ? uop_ppred : wb_ldst_forward_e_0_uop_ppred; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs1_busy = _GEN_526 ? uop_prs1_busy : wb_ldst_forward_e_0_uop_prs1_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs2_busy = _GEN_526 ? uop_prs2_busy : wb_ldst_forward_e_0_uop_prs2_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs3_busy = _GEN_526 ? uop_prs3_busy : wb_ldst_forward_e_0_uop_prs3_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ppred_busy = _GEN_526 ? uop_ppred_busy : wb_ldst_forward_e_0_uop_ppred_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_stale_pdst = _GEN_526 ? uop_stale_pdst : wb_ldst_forward_e_0_uop_stale_pdst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_exception = _GEN_526 ? uop_exception : wb_ldst_forward_e_0_uop_exception; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_exc_cause = _GEN_526 ? uop_exc_cause : wb_ldst_forward_e_0_uop_exc_cause; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_mem_cmd = _GEN_526 ? uop_mem_cmd : wb_ldst_forward_e_0_uop_mem_cmd; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_mem_size = _GEN_526 ? uop_mem_size : wb_ldst_forward_e_0_uop_mem_size; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_mem_signed = _GEN_526 ? uop_mem_signed : wb_ldst_forward_e_0_uop_mem_signed; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_uses_ldq = _GEN_526 ? uop_uses_ldq : wb_ldst_forward_e_0_uop_uses_ldq; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_uses_stq = _GEN_526 ? uop_uses_stq : wb_ldst_forward_e_0_uop_uses_stq; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_unique = _GEN_526 ? uop_is_unique : wb_ldst_forward_e_0_uop_is_unique; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_flush_on_commit = _GEN_526 ? uop_flush_on_commit : wb_ldst_forward_e_0_uop_flush_on_commit; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_csr_cmd = _GEN_526 ? uop_csr_cmd : wb_ldst_forward_e_0_uop_csr_cmd; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ldst_is_rs1 = _GEN_526 ? uop_ldst_is_rs1 : wb_ldst_forward_e_0_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ldst = _GEN_526 ? uop_ldst : wb_ldst_forward_e_0_uop_ldst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs1 = _GEN_526 ? uop_lrs1 : wb_ldst_forward_e_0_uop_lrs1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs2 = _GEN_526 ? uop_lrs2 : wb_ldst_forward_e_0_uop_lrs2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs3 = _GEN_526 ? uop_lrs3 : wb_ldst_forward_e_0_uop_lrs3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_dst_rtype = _GEN_526 ? uop_dst_rtype : wb_ldst_forward_e_0_uop_dst_rtype; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs1_rtype = _GEN_526 ? uop_lrs1_rtype : wb_ldst_forward_e_0_uop_lrs1_rtype; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs2_rtype = _GEN_526 ? uop_lrs2_rtype : wb_ldst_forward_e_0_uop_lrs2_rtype; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_frs3_en = _GEN_526 ? uop_frs3_en : wb_ldst_forward_e_0_uop_frs3_en; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fcn_dw = _GEN_526 ? uop_fcn_dw : wb_ldst_forward_e_0_uop_fcn_dw; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fcn_op = _GEN_526 ? uop_fcn_op : wb_ldst_forward_e_0_uop_fcn_op; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_val = _GEN_526 ? uop_fp_val : wb_ldst_forward_e_0_uop_fp_val; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_rm = _GEN_526 ? uop_fp_rm : wb_ldst_forward_e_0_uop_fp_rm; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_typ = _GEN_526 ? uop_fp_typ : wb_ldst_forward_e_0_uop_fp_typ; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_xcpt_pf_if = _GEN_526 ? uop_xcpt_pf_if : wb_ldst_forward_e_0_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_xcpt_ae_if = _GEN_526 ? uop_xcpt_ae_if : wb_ldst_forward_e_0_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_xcpt_ma_if = _GEN_526 ? uop_xcpt_ma_if : wb_ldst_forward_e_0_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_bp_debug_if = _GEN_526 ? uop_bp_debug_if : wb_ldst_forward_e_0_uop_bp_debug_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_bp_xcpt_if = _GEN_526 ? uop_bp_xcpt_if : wb_ldst_forward_e_0_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_fsrc = _GEN_526 ? uop_debug_fsrc : wb_ldst_forward_e_0_uop_debug_fsrc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_tsrc = _GEN_526 ? uop_debug_tsrc : wb_ldst_forward_e_0_uop_debug_tsrc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] wire [31:0] _iresp_0_bits_data_shifted_T_1 = _GEN_524[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _iresp_0_bits_data_T_5 = _GEN_524[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _fresp_0_bits_data_shifted_T_1 = _GEN_524[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _fresp_0_bits_data_T_5 = _GEN_524[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _ldq_debug_wb_data_shifted_T_1 = _GEN_524[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _ldq_debug_wb_data_T_5 = _GEN_524[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _iresp_0_bits_data_shifted_T_2 = _GEN_524[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _fresp_0_bits_data_shifted_T_2 = _GEN_524[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _ldq_debug_wb_data_shifted_T_2 = _GEN_524[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] iresp_0_bits_data_shifted = _iresp_0_bits_data_shifted_T ? _iresp_0_bits_data_shifted_T_1 : _iresp_0_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] iresp_0_bits_data_zeroed = iresp_0_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _GEN_638 = size_1 == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _iresp_0_bits_data_T; // @[AMOALU.scala:45:26] assign _iresp_0_bits_data_T = _GEN_638; // @[AMOALU.scala:45:26] wire _fresp_0_bits_data_T; // @[AMOALU.scala:45:26] assign _fresp_0_bits_data_T = _GEN_638; // @[AMOALU.scala:45:26] wire _ldq_debug_wb_data_T; // @[AMOALU.scala:45:26] assign _ldq_debug_wb_data_T = _GEN_638; // @[AMOALU.scala:45:26] wire _iresp_0_bits_data_T_1 = _iresp_0_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _iresp_0_bits_data_T_2 = iresp_0_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _iresp_0_bits_data_T_3 = wb_ldst_forward_e_0_uop_mem_signed & _iresp_0_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _iresp_0_bits_data_T_4 = {32{_iresp_0_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _iresp_0_bits_data_T_6 = _iresp_0_bits_data_T_1 ? _iresp_0_bits_data_T_4 : _iresp_0_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _iresp_0_bits_data_T_7 = {_iresp_0_bits_data_T_6, iresp_0_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _iresp_0_bits_data_shifted_T_3 = wb_ldst_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _fresp_0_bits_data_shifted_T_3 = wb_ldst_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _ldq_debug_wb_data_shifted_T_3 = wb_ldst_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire [15:0] _iresp_0_bits_data_shifted_T_4 = _iresp_0_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _iresp_0_bits_data_shifted_T_5 = _iresp_0_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] iresp_0_bits_data_shifted_1 = _iresp_0_bits_data_shifted_T_3 ? _iresp_0_bits_data_shifted_T_4 : _iresp_0_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] iresp_0_bits_data_zeroed_1 = iresp_0_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _GEN_639 = size_1 == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _iresp_0_bits_data_T_8; // @[AMOALU.scala:45:26] assign _iresp_0_bits_data_T_8 = _GEN_639; // @[AMOALU.scala:45:26] wire _fresp_0_bits_data_T_8; // @[AMOALU.scala:45:26] assign _fresp_0_bits_data_T_8 = _GEN_639; // @[AMOALU.scala:45:26] wire _ldq_debug_wb_data_T_8; // @[AMOALU.scala:45:26] assign _ldq_debug_wb_data_T_8 = _GEN_639; // @[AMOALU.scala:45:26] wire _iresp_0_bits_data_T_9 = _iresp_0_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _iresp_0_bits_data_T_10 = iresp_0_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _iresp_0_bits_data_T_11 = wb_ldst_forward_e_0_uop_mem_signed & _iresp_0_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _iresp_0_bits_data_T_12 = {48{_iresp_0_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _iresp_0_bits_data_T_13 = _iresp_0_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _iresp_0_bits_data_T_14 = _iresp_0_bits_data_T_9 ? _iresp_0_bits_data_T_12 : _iresp_0_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _iresp_0_bits_data_T_15 = {_iresp_0_bits_data_T_14, iresp_0_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _iresp_0_bits_data_shifted_T_6 = wb_ldst_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _fresp_0_bits_data_shifted_T_6 = wb_ldst_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _ldq_debug_wb_data_shifted_T_6 = wb_ldst_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire [7:0] _iresp_0_bits_data_shifted_T_7 = _iresp_0_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _iresp_0_bits_data_shifted_T_8 = _iresp_0_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] iresp_0_bits_data_shifted_2 = _iresp_0_bits_data_shifted_T_6 ? _iresp_0_bits_data_shifted_T_7 : _iresp_0_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] iresp_0_bits_data_zeroed_2 = iresp_0_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _GEN_640 = size_1 == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _iresp_0_bits_data_T_16; // @[AMOALU.scala:45:26] assign _iresp_0_bits_data_T_16 = _GEN_640; // @[AMOALU.scala:45:26] wire _fresp_0_bits_data_T_16; // @[AMOALU.scala:45:26] assign _fresp_0_bits_data_T_16 = _GEN_640; // @[AMOALU.scala:45:26] wire _ldq_debug_wb_data_T_16; // @[AMOALU.scala:45:26] assign _ldq_debug_wb_data_T_16 = _GEN_640; // @[AMOALU.scala:45:26] wire _iresp_0_bits_data_T_17 = _iresp_0_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _iresp_0_bits_data_T_18 = iresp_0_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _iresp_0_bits_data_T_19 = wb_ldst_forward_e_0_uop_mem_signed & _iresp_0_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _iresp_0_bits_data_T_20 = {56{_iresp_0_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _iresp_0_bits_data_T_21 = _iresp_0_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _iresp_0_bits_data_T_22 = _iresp_0_bits_data_T_17 ? _iresp_0_bits_data_T_20 : _iresp_0_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _iresp_0_bits_data_T_23 = {_iresp_0_bits_data_T_22, iresp_0_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign iresp_0_bits_data = _GEN_526 ? resp_data : _iresp_0_bits_data_T_23; // @[AMOALU.scala:45:16] wire [31:0] fresp_0_bits_data_shifted = _fresp_0_bits_data_shifted_T ? _fresp_0_bits_data_shifted_T_1 : _fresp_0_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] fresp_0_bits_data_zeroed = fresp_0_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _fresp_0_bits_data_T_1 = _fresp_0_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _fresp_0_bits_data_T_2 = fresp_0_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _fresp_0_bits_data_T_3 = wb_ldst_forward_e_0_uop_mem_signed & _fresp_0_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _fresp_0_bits_data_T_4 = {32{_fresp_0_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _fresp_0_bits_data_T_6 = _fresp_0_bits_data_T_1 ? _fresp_0_bits_data_T_4 : _fresp_0_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _fresp_0_bits_data_T_7 = {_fresp_0_bits_data_T_6, fresp_0_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _fresp_0_bits_data_shifted_T_4 = _fresp_0_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _fresp_0_bits_data_shifted_T_5 = _fresp_0_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] fresp_0_bits_data_shifted_1 = _fresp_0_bits_data_shifted_T_3 ? _fresp_0_bits_data_shifted_T_4 : _fresp_0_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] fresp_0_bits_data_zeroed_1 = fresp_0_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _fresp_0_bits_data_T_9 = _fresp_0_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _fresp_0_bits_data_T_10 = fresp_0_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _fresp_0_bits_data_T_11 = wb_ldst_forward_e_0_uop_mem_signed & _fresp_0_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _fresp_0_bits_data_T_12 = {48{_fresp_0_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _fresp_0_bits_data_T_13 = _fresp_0_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _fresp_0_bits_data_T_14 = _fresp_0_bits_data_T_9 ? _fresp_0_bits_data_T_12 : _fresp_0_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _fresp_0_bits_data_T_15 = {_fresp_0_bits_data_T_14, fresp_0_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _fresp_0_bits_data_shifted_T_7 = _fresp_0_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _fresp_0_bits_data_shifted_T_8 = _fresp_0_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] fresp_0_bits_data_shifted_2 = _fresp_0_bits_data_shifted_T_6 ? _fresp_0_bits_data_shifted_T_7 : _fresp_0_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] fresp_0_bits_data_zeroed_2 = fresp_0_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _fresp_0_bits_data_T_17 = _fresp_0_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _fresp_0_bits_data_T_18 = fresp_0_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _fresp_0_bits_data_T_19 = wb_ldst_forward_e_0_uop_mem_signed & _fresp_0_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _fresp_0_bits_data_T_20 = {56{_fresp_0_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _fresp_0_bits_data_T_21 = _fresp_0_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _fresp_0_bits_data_T_22 = _fresp_0_bits_data_T_17 ? _fresp_0_bits_data_T_20 : _fresp_0_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _fresp_0_bits_data_T_23 = {_fresp_0_bits_data_T_22, fresp_0_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign fresp_0_bits_data = _GEN_526 ? resp_data : _fresp_0_bits_data_T_23; // @[AMOALU.scala:45:16] wire _GEN_641 = _T_1178 & _GEN_488; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_642 = ~_T_1176 & _GEN_641; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_0 = _GEN_642 \| (_GEN_507 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_60 & ldq_succeeded_0 : ~_GEN_28 & ldq_succeeded_0); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_643 = _T_1178 & _GEN_489; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_644 = ~_T_1176 & _GEN_643; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_1 = _GEN_644 \| (_GEN_508 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_61 & ldq_succeeded_1 : ~_GEN_29 & ldq_succeeded_1); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_645 = _T_1178 & _GEN_490; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_646 = ~_T_1176 & _GEN_645; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_2 = _GEN_646 \| (_GEN_509 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_62 & ldq_succeeded_2 : ~_GEN_30 & ldq_succeeded_2); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_647 = _T_1178 & _GEN_491; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_648 = ~_T_1176 & _GEN_647; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_3 = _GEN_648 \| (_GEN_510 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_63 & ldq_succeeded_3 : ~_GEN_31 & ldq_succeeded_3); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_649 = _T_1178 & _GEN_492; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_650 = ~_T_1176 & _GEN_649; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_4 = _GEN_650 \| (_GEN_511 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_64 & ldq_succeeded_4 : ~_GEN_32 & ldq_succeeded_4); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_651 = _T_1178 & _GEN_493; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_652 = ~_T_1176 & _GEN_651; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_5 = _GEN_652 \| (_GEN_512 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_65 & ldq_succeeded_5 : ~_GEN_33 & ldq_succeeded_5); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_653 = _T_1178 & _GEN_494; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_654 = ~_T_1176 & _GEN_653; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_6 = _GEN_654 \| (_GEN_513 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_66 & ldq_succeeded_6 : ~_GEN_34 & ldq_succeeded_6); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_655 = _T_1178 & _GEN_495; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_656 = ~_T_1176 & _GEN_655; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_7 = _GEN_656 \| (_GEN_514 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_67 & ldq_succeeded_7 : ~_GEN_35 & ldq_succeeded_7); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_657 = _T_1178 & _GEN_496; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_658 = ~_T_1176 & _GEN_657; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_8 = _GEN_658 \| (_GEN_515 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_68 & ldq_succeeded_8 : ~_GEN_36 & ldq_succeeded_8); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_659 = _T_1178 & _GEN_497; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_660 = ~_T_1176 & _GEN_659; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_9 = _GEN_660 \| (_GEN_516 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_69 & ldq_succeeded_9 : ~_GEN_37 & ldq_succeeded_9); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_661 = _T_1178 & _GEN_498; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_662 = ~_T_1176 & _GEN_661; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_10 = _GEN_662 \| (_GEN_517 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_70 & ldq_succeeded_10 : ~_GEN_38 & ldq_succeeded_10); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_663 = _T_1178 & _GEN_499; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_664 = ~_T_1176 & _GEN_663; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_11 = _GEN_664 \| (_GEN_518 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_71 & ldq_succeeded_11 : ~_GEN_39 & ldq_succeeded_11); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_665 = _T_1178 & _GEN_500; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_666 = ~_T_1176 & _GEN_665; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_12 = _GEN_666 \| (_GEN_519 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_72 & ldq_succeeded_12 : ~_GEN_40 & ldq_succeeded_12); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_667 = _T_1178 & _GEN_501; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_668 = ~_T_1176 & _GEN_667; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_13 = _GEN_668 \| (_GEN_520 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_73 & ldq_succeeded_13 : ~_GEN_41 & ldq_succeeded_13); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_669 = _T_1178 & _GEN_502; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_670 = ~_T_1176 & _GEN_669; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_14 = _GEN_670 \| (_GEN_521 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_74 & ldq_succeeded_14 : ~_GEN_42 & ldq_succeeded_14); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_671 = _T_1178 & (&wb_ldst_forward_ldq_idx_0); // @[lsu.scala:1174:41, :1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_672 = ~_T_1176 & _GEN_671; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_15 = _GEN_672 \| (_GEN_522 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_75 & ldq_succeeded_15 : ~_GEN_43 & ldq_succeeded_15); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire [31:0] ldq_debug_wb_data_shifted = _ldq_debug_wb_data_shifted_T ? _ldq_debug_wb_data_shifted_T_1 : _ldq_debug_wb_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] ldq_debug_wb_data_zeroed = ldq_debug_wb_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _ldq_debug_wb_data_T_1 = _ldq_debug_wb_data_T; // @[AMOALU.scala:45:{26,34}] wire _ldq_debug_wb_data_T_2 = ldq_debug_wb_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_debug_wb_data_T_3 = wb_ldst_forward_e_0_uop_mem_signed & _ldq_debug_wb_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _ldq_debug_wb_data_T_4 = {32{_ldq_debug_wb_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _ldq_debug_wb_data_T_6 = _ldq_debug_wb_data_T_1 ? _ldq_debug_wb_data_T_4 : _ldq_debug_wb_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_debug_wb_data_T_7 = {_ldq_debug_wb_data_T_6, ldq_debug_wb_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _ldq_debug_wb_data_shifted_T_4 = _ldq_debug_wb_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _ldq_debug_wb_data_shifted_T_5 = _ldq_debug_wb_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] ldq_debug_wb_data_shifted_1 = _ldq_debug_wb_data_shifted_T_3 ? _ldq_debug_wb_data_shifted_T_4 : _ldq_debug_wb_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] ldq_debug_wb_data_zeroed_1 = ldq_debug_wb_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _ldq_debug_wb_data_T_9 = _ldq_debug_wb_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _ldq_debug_wb_data_T_10 = ldq_debug_wb_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_debug_wb_data_T_11 = wb_ldst_forward_e_0_uop_mem_signed & _ldq_debug_wb_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _ldq_debug_wb_data_T_12 = {48{_ldq_debug_wb_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _ldq_debug_wb_data_T_13 = _ldq_debug_wb_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _ldq_debug_wb_data_T_14 = _ldq_debug_wb_data_T_9 ? _ldq_debug_wb_data_T_12 : _ldq_debug_wb_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_debug_wb_data_T_15 = {_ldq_debug_wb_data_T_14, ldq_debug_wb_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _ldq_debug_wb_data_shifted_T_7 = _ldq_debug_wb_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _ldq_debug_wb_data_shifted_T_8 = _ldq_debug_wb_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] ldq_debug_wb_data_shifted_2 = _ldq_debug_wb_data_shifted_T_6 ? _ldq_debug_wb_data_shifted_T_7 : _ldq_debug_wb_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] ldq_debug_wb_data_zeroed_2 = ldq_debug_wb_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _ldq_debug_wb_data_T_17 = _ldq_debug_wb_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _ldq_debug_wb_data_T_18 = ldq_debug_wb_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_debug_wb_data_T_19 = wb_ldst_forward_e_0_uop_mem_signed & _ldq_debug_wb_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _ldq_debug_wb_data_T_20 = {56{_ldq_debug_wb_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _ldq_debug_wb_data_T_21 = _ldq_debug_wb_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _ldq_debug_wb_data_T_22 = _ldq_debug_wb_data_T_17 ? _ldq_debug_wb_data_T_20 : _ldq_debug_wb_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_debug_wb_data_T_23 = {_ldq_debug_wb_data_T_22, ldq_debug_wb_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _slow_wakeups_0_out_valid_T_4; // @[util.scala:116:31] wire [11:0] _slow_wakeups_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] slow_wakeups_0_out_bits_uop_br_mask; // @[util.scala:114:23] wire slow_wakeups_0_out_valid; // @[util.scala:114:23] wire [11:0] _slow_wakeups_0_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _slow_wakeups_0_out_bits_uop_br_mask_T_1 = wb_slow_wakeups_0_bits_uop_br_mask & _slow_wakeups_0_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign slow_wakeups_0_out_bits_uop_br_mask = _slow_wakeups_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [11:0] _slow_wakeups_0_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & wb_slow_wakeups_0_bits_uop_br_mask; // @[util.scala:126:51] wire _slow_wakeups_0_out_valid_T_1 = \|_slow_wakeups_0_out_valid_T; // @[util.scala:126:{51,59}] wire _slow_wakeups_0_out_valid_T_2 = _slow_wakeups_0_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _slow_wakeups_0_out_valid_T_3 = ~_slow_wakeups_0_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _slow_wakeups_0_out_valid_T_4 = wb_slow_wakeups_0_valid & _slow_wakeups_0_out_valid_T_3; // @[util.scala:116:{31,34}] assign slow_wakeups_0_out_valid = _slow_wakeups_0_out_valid_T_4; // @[util.scala:114:23, :116:31] reg slow_wakeups_0_REG_valid; // @[lsu.scala:1647:79] assign slow_wakeups_0_valid = slow_wakeups_0_REG_valid; // @[lsu.scala:1495:26, :1647:79] reg [31:0] slow_wakeups_0_REG_bits_uop_inst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_inst = slow_wakeups_0_REG_bits_uop_inst; // @[lsu.scala:1495:26, :1647:79] reg [31:0] slow_wakeups_0_REG_bits_uop_debug_inst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_inst = slow_wakeups_0_REG_bits_uop_debug_inst; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_rvc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_rvc = slow_wakeups_0_REG_bits_uop_is_rvc; // @[lsu.scala:1495:26, :1647:79] reg [39:0] slow_wakeups_0_REG_bits_uop_debug_pc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_pc = slow_wakeups_0_REG_bits_uop_debug_pc; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_0; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_0 = slow_wakeups_0_REG_bits_uop_iq_type_0; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_1 = slow_wakeups_0_REG_bits_uop_iq_type_1; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_2 = slow_wakeups_0_REG_bits_uop_iq_type_2; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_3 = slow_wakeups_0_REG_bits_uop_iq_type_3; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_0; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_0 = slow_wakeups_0_REG_bits_uop_fu_code_0; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_1 = slow_wakeups_0_REG_bits_uop_fu_code_1; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_2 = slow_wakeups_0_REG_bits_uop_fu_code_2; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_3 = slow_wakeups_0_REG_bits_uop_fu_code_3; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_4; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_4 = slow_wakeups_0_REG_bits_uop_fu_code_4; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_5; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_5 = slow_wakeups_0_REG_bits_uop_fu_code_5; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_6; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_6 = slow_wakeups_0_REG_bits_uop_fu_code_6; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_7; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_7 = slow_wakeups_0_REG_bits_uop_fu_code_7; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_8; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_8 = slow_wakeups_0_REG_bits_uop_fu_code_8; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_9; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_9 = slow_wakeups_0_REG_bits_uop_fu_code_9; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_issued; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_issued = slow_wakeups_0_REG_bits_uop_iw_issued; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_issued_partial_agen = slow_wakeups_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_issued_partial_dgen = slow_wakeups_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p1_speculative_child = slow_wakeups_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p2_speculative_child = slow_wakeups_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p1_bypass_hint = slow_wakeups_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p2_bypass_hint = slow_wakeups_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p3_bypass_hint = slow_wakeups_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_dis_col_sel = slow_wakeups_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:1495:26, :1647:79] reg [11:0] slow_wakeups_0_REG_bits_uop_br_mask; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_br_mask = slow_wakeups_0_REG_bits_uop_br_mask; // @[lsu.scala:1495:26, :1647:79] reg [3:0] slow_wakeups_0_REG_bits_uop_br_tag; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_br_tag = slow_wakeups_0_REG_bits_uop_br_tag; // @[lsu.scala:1495:26, :1647:79] reg [3:0] slow_wakeups_0_REG_bits_uop_br_type; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_br_type = slow_wakeups_0_REG_bits_uop_br_type; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_sfb; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_sfb = slow_wakeups_0_REG_bits_uop_is_sfb; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_fence; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_fence = slow_wakeups_0_REG_bits_uop_is_fence; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_fencei; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_fencei = slow_wakeups_0_REG_bits_uop_is_fencei; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_sfence; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_sfence = slow_wakeups_0_REG_bits_uop_is_sfence; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_amo; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_amo = slow_wakeups_0_REG_bits_uop_is_amo; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_eret; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_eret = slow_wakeups_0_REG_bits_uop_is_eret; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_sys_pc2epc = slow_wakeups_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_rocc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_rocc = slow_wakeups_0_REG_bits_uop_is_rocc; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_mov; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_mov = slow_wakeups_0_REG_bits_uop_is_mov; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_ftq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ftq_idx = slow_wakeups_0_REG_bits_uop_ftq_idx; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_edge_inst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_edge_inst = slow_wakeups_0_REG_bits_uop_edge_inst; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_pc_lob; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_pc_lob = slow_wakeups_0_REG_bits_uop_pc_lob; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_taken; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_taken = slow_wakeups_0_REG_bits_uop_taken; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_imm_rename; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_imm_rename = slow_wakeups_0_REG_bits_uop_imm_rename; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_imm_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_imm_sel = slow_wakeups_0_REG_bits_uop_imm_sel; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_pimm; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_pimm = slow_wakeups_0_REG_bits_uop_pimm; // @[lsu.scala:1495:26, :1647:79] reg [19:0] slow_wakeups_0_REG_bits_uop_imm_packed; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_imm_packed = slow_wakeups_0_REG_bits_uop_imm_packed; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_op1_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_op1_sel = slow_wakeups_0_REG_bits_uop_op1_sel; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_op2_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_op2_sel = slow_wakeups_0_REG_bits_uop_op2_sel; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ldst = slow_wakeups_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_wen = slow_wakeups_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ren1 = slow_wakeups_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ren2 = slow_wakeups_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ren3 = slow_wakeups_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_swap12 = slow_wakeups_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_swap23 = slow_wakeups_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn = slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut = slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_fromint = slow_wakeups_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_toint = slow_wakeups_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_fastpipe = slow_wakeups_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_fma = slow_wakeups_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_div = slow_wakeups_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_sqrt = slow_wakeups_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_wflags = slow_wakeups_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_vec = slow_wakeups_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_rob_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_rob_idx = slow_wakeups_0_REG_bits_uop_rob_idx; // @[lsu.scala:1495:26, :1647:79] reg [3:0] slow_wakeups_0_REG_bits_uop_ldq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ldq_idx = slow_wakeups_0_REG_bits_uop_ldq_idx; // @[lsu.scala:1495:26, :1647:79] reg [3:0] slow_wakeups_0_REG_bits_uop_stq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_stq_idx = slow_wakeups_0_REG_bits_uop_stq_idx; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_rxq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_rxq_idx = slow_wakeups_0_REG_bits_uop_rxq_idx; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_pdst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_pdst = slow_wakeups_0_REG_bits_uop_pdst; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_prs1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs1 = slow_wakeups_0_REG_bits_uop_prs1; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_prs2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs2 = slow_wakeups_0_REG_bits_uop_prs2; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_prs3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs3 = slow_wakeups_0_REG_bits_uop_prs3; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_ppred; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ppred = slow_wakeups_0_REG_bits_uop_ppred; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_prs1_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs1_busy = slow_wakeups_0_REG_bits_uop_prs1_busy; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_prs2_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs2_busy = slow_wakeups_0_REG_bits_uop_prs2_busy; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_prs3_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs3_busy = slow_wakeups_0_REG_bits_uop_prs3_busy; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_ppred_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ppred_busy = slow_wakeups_0_REG_bits_uop_ppred_busy; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_stale_pdst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_stale_pdst = slow_wakeups_0_REG_bits_uop_stale_pdst; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_exception; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_exception = slow_wakeups_0_REG_bits_uop_exception; // @[lsu.scala:1495:26, :1647:79] reg [63:0] slow_wakeups_0_REG_bits_uop_exc_cause; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_exc_cause = slow_wakeups_0_REG_bits_uop_exc_cause; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_mem_cmd; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_mem_cmd = slow_wakeups_0_REG_bits_uop_mem_cmd; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_mem_size; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_mem_size = slow_wakeups_0_REG_bits_uop_mem_size; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_mem_signed; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_mem_signed = slow_wakeups_0_REG_bits_uop_mem_signed; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_uses_ldq; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_uses_ldq = slow_wakeups_0_REG_bits_uop_uses_ldq; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_uses_stq; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_uses_stq = slow_wakeups_0_REG_bits_uop_uses_stq; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_unique; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_unique = slow_wakeups_0_REG_bits_uop_is_unique; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_flush_on_commit = slow_wakeups_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_csr_cmd; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_csr_cmd = slow_wakeups_0_REG_bits_uop_csr_cmd; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ldst_is_rs1 = slow_wakeups_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_ldst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ldst = slow_wakeups_0_REG_bits_uop_ldst; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_lrs1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs1 = slow_wakeups_0_REG_bits_uop_lrs1; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_lrs2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs2 = slow_wakeups_0_REG_bits_uop_lrs2; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_lrs3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs3 = slow_wakeups_0_REG_bits_uop_lrs3; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_dst_rtype; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_dst_rtype = slow_wakeups_0_REG_bits_uop_dst_rtype; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs1_rtype = slow_wakeups_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs2_rtype = slow_wakeups_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_frs3_en; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_frs3_en = slow_wakeups_0_REG_bits_uop_frs3_en; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fcn_dw; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fcn_dw = slow_wakeups_0_REG_bits_uop_fcn_dw; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_fcn_op; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fcn_op = slow_wakeups_0_REG_bits_uop_fcn_op; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_val; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_val = slow_wakeups_0_REG_bits_uop_fp_val; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_fp_rm; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_rm = slow_wakeups_0_REG_bits_uop_fp_rm; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_fp_typ; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_typ = slow_wakeups_0_REG_bits_uop_fp_typ; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_xcpt_pf_if = slow_wakeups_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_xcpt_ae_if = slow_wakeups_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_xcpt_ma_if = slow_wakeups_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_bp_debug_if = slow_wakeups_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_bp_xcpt_if = slow_wakeups_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_fsrc = slow_wakeups_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_tsrc = slow_wakeups_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:1495:26, :1647:79] wire [11:0] _stq_uop_0_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_0_br_mask_T_1 = uop_1_br_mask & _stq_uop_0_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_1_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_1_br_mask_T_1 = uop_2_br_mask & _stq_uop_1_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_2_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_2_br_mask_T_1 = uop_3_br_mask & _stq_uop_2_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_3_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_3_br_mask_T_1 = uop_4_br_mask & _stq_uop_3_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_4_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_4_br_mask_T_1 = uop_5_br_mask & _stq_uop_4_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_5_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_5_br_mask_T_1 = uop_6_br_mask & _stq_uop_5_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_6_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_6_br_mask_T_1 = uop_7_br_mask & _stq_uop_6_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_7_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_7_br_mask_T_1 = uop_8_br_mask & _stq_uop_7_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_8_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_8_br_mask_T_1 = uop_9_br_mask & _stq_uop_8_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_9_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_9_br_mask_T_1 = uop_10_br_mask & _stq_uop_9_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_10_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_10_br_mask_T_1 = uop_11_br_mask & _stq_uop_10_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_11_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_11_br_mask_T_1 = uop_12_br_mask & _stq_uop_11_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_12_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_12_br_mask_T_1 = uop_13_br_mask & _stq_uop_12_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_13_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_13_br_mask_T_1 = uop_14_br_mask & _stq_uop_13_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_14_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_14_br_mask_T_1 = uop_15_br_mask & _stq_uop_14_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_15_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_15_br_mask_T_1 = uop_16_br_mask & _stq_uop_15_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_0_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_0_br_mask_T_1 = uop_17_br_mask & _ldq_uop_0_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_1_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_1_br_mask_T_1 = uop_18_br_mask & _ldq_uop_1_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_2_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_2_br_mask_T_1 = uop_19_br_mask & _ldq_uop_2_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_3_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_3_br_mask_T_1 = uop_20_br_mask & _ldq_uop_3_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_4_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_4_br_mask_T_1 = uop_21_br_mask & _ldq_uop_4_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_5_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_5_br_mask_T_1 = uop_22_br_mask & _ldq_uop_5_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_6_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_6_br_mask_T_1 = uop_23_br_mask & _ldq_uop_6_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_7_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_7_br_mask_T_1 = uop_24_br_mask & _ldq_uop_7_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_8_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_8_br_mask_T_1 = uop_25_br_mask & _ldq_uop_8_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_9_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_9_br_mask_T_1 = uop_26_br_mask & _ldq_uop_9_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_10_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_10_br_mask_T_1 = uop_27_br_mask & _ldq_uop_10_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_11_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_11_br_mask_T_1 = uop_28_br_mask & _ldq_uop_11_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_12_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_12_br_mask_T_1 = uop_29_br_mask & _ldq_uop_12_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_13_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_13_br_mask_T_1 = uop_30_br_mask & _ldq_uop_13_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_14_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_14_br_mask_T_1 = uop_31_br_mask & _ldq_uop_14_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_15_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_15_br_mask_T_1 = uop_32_br_mask & _ldq_uop_15_br_mask_T; // @[util.scala:97:{21,23}] wire commit_store = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_stq_0; // @[lsu.scala:211:7, :1724:49] wire commit_load = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_ldq_0; // @[lsu.scala:211:7, :1725:49] wire l_uop_16_iq_type_0; // @[lsu.scala:1728:25] wire l_uop_16_iq_type_1; // @[lsu.scala:1728:25] wire l_uop_16_iq_type_2; // @[lsu.scala:1728:25] wire l_uop_16_iq_type_3; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_0; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_1; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_2; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_3; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_4; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_5; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_6; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_7; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_8; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_9; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_ldst; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_wen; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_ren1; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_ren2; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_ren3; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_swap12; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_swap23; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_fromint; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_toint; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_fma; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_div; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_sqrt; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_wflags; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_vec; // @[lsu.scala:1728:25] wire [31:0] l_uop_16_inst; // @[lsu.scala:1728:25] wire [31:0] l_uop_16_debug_inst; // @[lsu.scala:1728:25] wire l_uop_16_is_rvc; // @[lsu.scala:1728:25] wire [39:0] l_uop_16_debug_pc; // @[lsu.scala:1728:25] wire l_uop_16_iw_issued; // @[lsu.scala:1728:25] wire l_uop_16_iw_issued_partial_agen; // @[lsu.scala:1728:25] wire l_uop_16_iw_issued_partial_dgen; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_iw_p1_speculative_child; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_iw_p2_speculative_child; // @[lsu.scala:1728:25] wire l_uop_16_iw_p1_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_16_iw_p2_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_16_iw_p3_bypass_hint; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_dis_col_sel; // @[lsu.scala:1728:25] wire [11:0] l_uop_16_br_mask; // @[lsu.scala:1728:25] wire [3:0] l_uop_16_br_tag; // @[lsu.scala:1728:25] wire [3:0] l_uop_16_br_type; // @[lsu.scala:1728:25] wire l_uop_16_is_sfb; // @[lsu.scala:1728:25] wire l_uop_16_is_fence; // @[lsu.scala:1728:25] wire l_uop_16_is_fencei; // @[lsu.scala:1728:25] wire l_uop_16_is_sfence; // @[lsu.scala:1728:25] wire l_uop_16_is_amo; // @[lsu.scala:1728:25] wire l_uop_16_is_eret; // @[lsu.scala:1728:25] wire l_uop_16_is_sys_pc2epc; // @[lsu.scala:1728:25] wire l_uop_16_is_rocc; // @[lsu.scala:1728:25] wire l_uop_16_is_mov; // @[lsu.scala:1728:25] wire [4:0] l_uop_16_ftq_idx; // @[lsu.scala:1728:25] wire l_uop_16_edge_inst; // @[lsu.scala:1728:25] wire [5:0] l_uop_16_pc_lob; // @[lsu.scala:1728:25] wire l_uop_16_taken; // @[lsu.scala:1728:25] wire l_uop_16_imm_rename; // @[lsu.scala:1728:25] wire [2:0] l_uop_16_imm_sel; // @[lsu.scala:1728:25] wire [4:0] l_uop_16_pimm; // @[lsu.scala:1728:25] wire [19:0] l_uop_16_imm_packed; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_op1_sel; // @[lsu.scala:1728:25] wire [2:0] l_uop_16_op2_sel; // @[lsu.scala:1728:25] wire [5:0] l_uop_16_rob_idx; // @[lsu.scala:1728:25] wire [3:0] l_uop_16_ldq_idx; // @[lsu.scala:1728:25] wire [3:0] l_uop_16_stq_idx; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_rxq_idx; // @[lsu.scala:1728:25] wire [6:0] l_uop_16_pdst; // @[lsu.scala:1728:25] wire [6:0] l_uop_16_prs1; // @[lsu.scala:1728:25] wire [6:0] l_uop_16_prs2; // @[lsu.scala:1728:25] wire [6:0] l_uop_16_prs3; // @[lsu.scala:1728:25] wire [4:0] l_uop_16_ppred; // @[lsu.scala:1728:25] wire l_uop_16_prs1_busy; // @[lsu.scala:1728:25] wire l_uop_16_prs2_busy; // @[lsu.scala:1728:25] wire l_uop_16_prs3_busy; // @[lsu.scala:1728:25] wire l_uop_16_ppred_busy; // @[lsu.scala:1728:25] wire [6:0] l_uop_16_stale_pdst; // @[lsu.scala:1728:25] wire l_uop_16_exception; // @[lsu.scala:1728:25] wire [63:0] l_uop_16_exc_cause; // @[lsu.scala:1728:25] wire [4:0] l_uop_16_mem_cmd; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_mem_size; // @[lsu.scala:1728:25] wire l_uop_16_mem_signed; // @[lsu.scala:1728:25] wire l_uop_16_uses_ldq; // @[lsu.scala:1728:25] wire l_uop_16_uses_stq; // @[lsu.scala:1728:25] wire l_uop_16_is_unique; // @[lsu.scala:1728:25] wire l_uop_16_flush_on_commit; // @[lsu.scala:1728:25] wire [2:0] l_uop_16_csr_cmd; // @[lsu.scala:1728:25] wire l_uop_16_ldst_is_rs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_16_ldst; // @[lsu.scala:1728:25] wire [5:0] l_uop_16_lrs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_16_lrs2; // @[lsu.scala:1728:25] wire [5:0] l_uop_16_lrs3; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_dst_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_lrs1_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_lrs2_rtype; // @[lsu.scala:1728:25] wire l_uop_16_frs3_en; // @[lsu.scala:1728:25] wire l_uop_16_fcn_dw; // @[lsu.scala:1728:25] wire [4:0] l_uop_16_fcn_op; // @[lsu.scala:1728:25] wire l_uop_16_fp_val; // @[lsu.scala:1728:25] wire [2:0] l_uop_16_fp_rm; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_fp_typ; // @[lsu.scala:1728:25] wire l_uop_16_xcpt_pf_if; // @[lsu.scala:1728:25] wire l_uop_16_xcpt_ae_if; // @[lsu.scala:1728:25] wire l_uop_16_xcpt_ma_if; // @[lsu.scala:1728:25] wire l_uop_16_bp_debug_if; // @[lsu.scala:1728:25] wire l_uop_16_bp_xcpt_if; // @[lsu.scala:1728:25] wire [2:0] l_uop_16_debug_fsrc; // @[lsu.scala:1728:25] wire [2:0] l_uop_16_debug_tsrc; // @[lsu.scala:1728:25] assign l_uop_16_inst = _GEN_76[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_debug_inst = _GEN_77[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_rvc = _GEN_78[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_debug_pc = _GEN_79[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iq_type_0 = _GEN_80[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iq_type_1 = _GEN_81[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iq_type_2 = _GEN_82[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iq_type_3 = _GEN_83[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_0 = _GEN_84[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_1 = _GEN_85[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_2 = _GEN_86[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_3 = _GEN_87[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_4 = _GEN_88[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_5 = _GEN_89[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_6 = _GEN_90[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_7 = _GEN_91[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_8 = _GEN_92[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_9 = _GEN_93[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_issued = _GEN_94[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_issued_partial_agen = _GEN_95[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_issued_partial_dgen = _GEN_96[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_p1_speculative_child = _GEN_97[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_p2_speculative_child = _GEN_98[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_p1_bypass_hint = _GEN_99[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_p2_bypass_hint = _GEN_100[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_p3_bypass_hint = _GEN_101[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_dis_col_sel = _GEN_102[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_br_mask = _GEN_103[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_br_tag = _GEN_104[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_br_type = _GEN_105[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_sfb = _GEN_106[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_fence = _GEN_107[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_fencei = _GEN_108[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_sfence = _GEN_109[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_amo = _GEN_110[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_eret = _GEN_111[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_sys_pc2epc = _GEN_112[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_rocc = _GEN_113[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_mov = _GEN_114[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_ftq_idx = _GEN_115[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_edge_inst = _GEN_116[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_pc_lob = _GEN_117[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_taken = _GEN_118[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_imm_rename = _GEN_119[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_imm_sel = _GEN_120[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_pimm = _GEN_121[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_imm_packed = _GEN_122[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_op1_sel = _GEN_123[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_op2_sel = _GEN_124[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_ldst = _GEN_125[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_wen = _GEN_126[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_ren1 = _GEN_127[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_ren2 = _GEN_128[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_ren3 = _GEN_129[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_swap12 = _GEN_130[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_swap23 = _GEN_131[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_typeTagIn = _GEN_132[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_typeTagOut = _GEN_133[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_fromint = _GEN_134[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_toint = _GEN_135[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_fastpipe = _GEN_136[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_fma = _GEN_137[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_div = _GEN_138[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_sqrt = _GEN_139[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_wflags = _GEN_140[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_vec = _GEN_141[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_rob_idx = _GEN_142[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_ldq_idx = _GEN_143[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_stq_idx = _GEN_144[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_rxq_idx = _GEN_145[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_pdst = _GEN_146[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_prs1 = _GEN_147[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_prs2 = _GEN_148[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_prs3 = _GEN_149[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_ppred = _GEN_150[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_prs1_busy = _GEN_151[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_prs2_busy = _GEN_152[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_prs3_busy = _GEN_153[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_ppred_busy = _GEN_154[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_stale_pdst = _GEN_155[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_exception = _GEN_156[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_exc_cause = _GEN_157[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_mem_cmd = _GEN_158[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_mem_size = _GEN_159[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_mem_signed = _GEN_160[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_uses_ldq = _GEN_161[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_uses_stq = _GEN_162[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_unique = _GEN_163[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_flush_on_commit = _GEN_164[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_csr_cmd = _GEN_165[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_ldst_is_rs1 = _GEN_166[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_ldst = _GEN_167[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_lrs1 = _GEN_168[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_lrs2 = _GEN_169[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_lrs3 = _GEN_170[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_dst_rtype = _GEN_171[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_lrs1_rtype = _GEN_172[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_lrs2_rtype = _GEN_173[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_frs3_en = _GEN_174[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fcn_dw = _GEN_175[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fcn_op = _GEN_176[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_val = _GEN_177[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_rm = _GEN_178[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_typ = _GEN_179[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_xcpt_pf_if = _GEN_180[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_xcpt_ae_if = _GEN_181[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_xcpt_ma_if = _GEN_182[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_bp_debug_if = _GEN_183[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_bp_xcpt_if = _GEN_184[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_debug_fsrc = _GEN_185[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_debug_tsrc = _GEN_186[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] wire s_uop_18_iq_type_0; // @[lsu.scala:1729:25] wire s_uop_18_iq_type_1; // @[lsu.scala:1729:25] wire s_uop_18_iq_type_2; // @[lsu.scala:1729:25] wire s_uop_18_iq_type_3; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_0; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_1; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_2; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_3; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_4; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_5; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_6; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_7; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_8; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_9; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_ldst; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_wen; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_ren1; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_ren2; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_ren3; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_swap12; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_swap23; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_fromint; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_toint; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_fma; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_div; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_sqrt; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_wflags; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_vec; // @[lsu.scala:1729:25] wire [31:0] s_uop_18_inst; // @[lsu.scala:1729:25] wire [31:0] s_uop_18_debug_inst; // @[lsu.scala:1729:25] wire s_uop_18_is_rvc; // @[lsu.scala:1729:25] wire [39:0] s_uop_18_debug_pc; // @[lsu.scala:1729:25] wire s_uop_18_iw_issued; // @[lsu.scala:1729:25] wire s_uop_18_iw_issued_partial_agen; // @[lsu.scala:1729:25] wire s_uop_18_iw_issued_partial_dgen; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_iw_p1_speculative_child; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_iw_p2_speculative_child; // @[lsu.scala:1729:25] wire s_uop_18_iw_p1_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_18_iw_p2_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_18_iw_p3_bypass_hint; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_dis_col_sel; // @[lsu.scala:1729:25] wire [11:0] s_uop_18_br_mask; // @[lsu.scala:1729:25] wire [3:0] s_uop_18_br_tag; // @[lsu.scala:1729:25] wire [3:0] s_uop_18_br_type; // @[lsu.scala:1729:25] wire s_uop_18_is_sfb; // @[lsu.scala:1729:25] wire s_uop_18_is_fence; // @[lsu.scala:1729:25] wire s_uop_18_is_fencei; // @[lsu.scala:1729:25] wire s_uop_18_is_sfence; // @[lsu.scala:1729:25] wire s_uop_18_is_amo; // @[lsu.scala:1729:25] wire s_uop_18_is_eret; // @[lsu.scala:1729:25] wire s_uop_18_is_sys_pc2epc; // @[lsu.scala:1729:25] wire s_uop_18_is_rocc; // @[lsu.scala:1729:25] wire s_uop_18_is_mov; // @[lsu.scala:1729:25] wire [4:0] s_uop_18_ftq_idx; // @[lsu.scala:1729:25] wire s_uop_18_edge_inst; // @[lsu.scala:1729:25] wire [5:0] s_uop_18_pc_lob; // @[lsu.scala:1729:25] wire s_uop_18_taken; // @[lsu.scala:1729:25] wire s_uop_18_imm_rename; // @[lsu.scala:1729:25] wire [2:0] s_uop_18_imm_sel; // @[lsu.scala:1729:25] wire [4:0] s_uop_18_pimm; // @[lsu.scala:1729:25] wire [19:0] s_uop_18_imm_packed; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_op1_sel; // @[lsu.scala:1729:25] wire [2:0] s_uop_18_op2_sel; // @[lsu.scala:1729:25] wire [5:0] s_uop_18_rob_idx; // @[lsu.scala:1729:25] wire [3:0] s_uop_18_ldq_idx; // @[lsu.scala:1729:25] wire [3:0] s_uop_18_stq_idx; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_rxq_idx; // @[lsu.scala:1729:25] wire [6:0] s_uop_18_pdst; // @[lsu.scala:1729:25] wire [6:0] s_uop_18_prs1; // @[lsu.scala:1729:25] wire [6:0] s_uop_18_prs2; // @[lsu.scala:1729:25] wire [6:0] s_uop_18_prs3; // @[lsu.scala:1729:25] wire [4:0] s_uop_18_ppred; // @[lsu.scala:1729:25] wire s_uop_18_prs1_busy; // @[lsu.scala:1729:25] wire s_uop_18_prs2_busy; // @[lsu.scala:1729:25] wire s_uop_18_prs3_busy; // @[lsu.scala:1729:25] wire s_uop_18_ppred_busy; // @[lsu.scala:1729:25] wire [6:0] s_uop_18_stale_pdst; // @[lsu.scala:1729:25] wire s_uop_18_exception; // @[lsu.scala:1729:25] wire [63:0] s_uop_18_exc_cause; // @[lsu.scala:1729:25] wire [4:0] s_uop_18_mem_cmd; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_mem_size; // @[lsu.scala:1729:25] wire s_uop_18_mem_signed; // @[lsu.scala:1729:25] wire s_uop_18_uses_ldq; // @[lsu.scala:1729:25] wire s_uop_18_uses_stq; // @[lsu.scala:1729:25] wire s_uop_18_is_unique; // @[lsu.scala:1729:25] wire s_uop_18_flush_on_commit; // @[lsu.scala:1729:25] wire [2:0] s_uop_18_csr_cmd; // @[lsu.scala:1729:25] wire s_uop_18_ldst_is_rs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_18_ldst; // @[lsu.scala:1729:25] wire [5:0] s_uop_18_lrs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_18_lrs2; // @[lsu.scala:1729:25] wire [5:0] s_uop_18_lrs3; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_dst_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_lrs1_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_lrs2_rtype; // @[lsu.scala:1729:25] wire s_uop_18_frs3_en; // @[lsu.scala:1729:25] wire s_uop_18_fcn_dw; // @[lsu.scala:1729:25] wire [4:0] s_uop_18_fcn_op; // @[lsu.scala:1729:25] wire s_uop_18_fp_val; // @[lsu.scala:1729:25] wire [2:0] s_uop_18_fp_rm; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_fp_typ; // @[lsu.scala:1729:25] wire s_uop_18_xcpt_pf_if; // @[lsu.scala:1729:25] wire s_uop_18_xcpt_ae_if; // @[lsu.scala:1729:25] wire s_uop_18_xcpt_ma_if; // @[lsu.scala:1729:25] wire s_uop_18_bp_debug_if; // @[lsu.scala:1729:25] wire s_uop_18_bp_xcpt_if; // @[lsu.scala:1729:25] wire [2:0] s_uop_18_debug_fsrc; // @[lsu.scala:1729:25] wire [2:0] s_uop_18_debug_tsrc; // @[lsu.scala:1729:25] assign s_uop_18_inst = _GEN_200[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_debug_inst = _GEN_201[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_rvc = _GEN_202[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_debug_pc = _GEN_203[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iq_type_0 = _GEN_204[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iq_type_1 = _GEN_205[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iq_type_2 = _GEN_206[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iq_type_3 = _GEN_207[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_0 = _GEN_208[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_1 = _GEN_209[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_2 = _GEN_210[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_3 = _GEN_211[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_4 = _GEN_212[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_5 = _GEN_213[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_6 = _GEN_214[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_7 = _GEN_215[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_8 = _GEN_216[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_9 = _GEN_217[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_issued = _GEN_218[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_issued_partial_agen = _GEN_219[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_issued_partial_dgen = _GEN_220[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_p1_speculative_child = _GEN_221[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_p2_speculative_child = _GEN_222[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_p1_bypass_hint = _GEN_223[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_p2_bypass_hint = _GEN_224[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_p3_bypass_hint = _GEN_225[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_dis_col_sel = _GEN_226[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_br_mask = _GEN_227[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_br_tag = _GEN_228[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_br_type = _GEN_229[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_sfb = _GEN_230[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_fence = _GEN_231[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_fencei = _GEN_232[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_sfence = _GEN_233[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_amo = _GEN_234[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_eret = _GEN_235[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_sys_pc2epc = _GEN_236[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_rocc = _GEN_237[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_mov = _GEN_238[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_ftq_idx = _GEN_239[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_edge_inst = _GEN_240[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_pc_lob = _GEN_241[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_taken = _GEN_242[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_imm_rename = _GEN_243[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_imm_sel = _GEN_244[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_pimm = _GEN_245[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_imm_packed = _GEN_246[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_op1_sel = _GEN_247[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_op2_sel = _GEN_248[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_ldst = _GEN_249[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_wen = _GEN_250[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_ren1 = _GEN_251[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_ren2 = _GEN_252[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_ren3 = _GEN_253[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_swap12 = _GEN_254[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_swap23 = _GEN_255[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_typeTagIn = _GEN_256[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_typeTagOut = _GEN_257[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_fromint = _GEN_258[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_toint = _GEN_259[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_fastpipe = _GEN_260[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_fma = _GEN_261[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_div = _GEN_262[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_sqrt = _GEN_263[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_wflags = _GEN_264[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_vec = _GEN_265[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_rob_idx = _GEN_266[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_ldq_idx = _GEN_267[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_stq_idx = _GEN_268[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_rxq_idx = _GEN_269[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_pdst = _GEN_270[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_prs1 = _GEN_271[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_prs2 = _GEN_272[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_prs3 = _GEN_273[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_ppred = _GEN_274[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_prs1_busy = _GEN_275[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_prs2_busy = _GEN_276[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_prs3_busy = _GEN_277[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_ppred_busy = _GEN_278[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_stale_pdst = _GEN_279[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_exception = _GEN_280[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_exc_cause = _GEN_281[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_mem_cmd = _GEN_282[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_mem_size = _GEN_283[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_mem_signed = _GEN_284[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_uses_ldq = _GEN_285[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_uses_stq = _GEN_286[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_unique = _GEN_287[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_flush_on_commit = _GEN_288[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_csr_cmd = _GEN_289[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_ldst_is_rs1 = _GEN_290[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_ldst = _GEN_291[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_lrs1 = _GEN_292[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_lrs2 = _GEN_293[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_lrs3 = _GEN_294[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_dst_rtype = _GEN_295[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_lrs1_rtype = _GEN_296[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_lrs2_rtype = _GEN_297[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_frs3_en = _GEN_298[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fcn_dw = _GEN_299[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fcn_op = _GEN_300[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_val = _GEN_301[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_rm = _GEN_302[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_typ = _GEN_303[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_xcpt_pf_if = _GEN_304[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_xcpt_ae_if = _GEN_305[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_xcpt_ma_if = _GEN_306[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_bp_debug_if = _GEN_307[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_bp_xcpt_if = _GEN_308[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_debug_fsrc = _GEN_309[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_debug_tsrc = _GEN_310[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] wire _GEN_673 = ~commit_store & commit_load; // @[lsu.scala:1724:49, :1725:49, :1731:5, :1735:31] wire _GEN_674 = _GEN_673 & ~reset; // @[lsu.scala:1735:31, :1736:14] wire _GEN_675 = _GEN_25[ldq_head]; // @[lsu.scala:278:29, :387:15, :1736:14] wire [3:0] _T_1456 = stq_commit_head + 4'h1; // @[util.scala:211:14] wire [3:0] _T_1459 = commit_store ? _T_1456 : stq_commit_head; // @[util.scala:211:14] wire [3:0] _T_1460 = ldq_head + 4'h1; // @[util.scala:211:14] wire [3:0] _T_1463 = commit_load ? _T_1460 : ldq_head; // @[util.scala:211:14] wire commit_store_1 = io_core_commit_valids_1_0 & io_core_commit_uops_1_uses_stq_0; // @[lsu.scala:211:7, :1724:49] wire commit_load_1 = io_core_commit_valids_1_0 & io_core_commit_uops_1_uses_ldq_0; // @[lsu.scala:211:7, :1725:49] wire l_uop_17_iq_type_0; // @[lsu.scala:1728:25] wire l_uop_17_iq_type_1; // @[lsu.scala:1728:25] wire l_uop_17_iq_type_2; // @[lsu.scala:1728:25] wire l_uop_17_iq_type_3; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_0; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_1; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_2; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_3; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_4; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_5; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_6; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_7; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_8; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_9; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_ldst; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_wen; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_ren1; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_ren2; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_ren3; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_swap12; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_swap23; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_fromint; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_toint; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_fma; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_div; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_sqrt; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_wflags; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_vec; // @[lsu.scala:1728:25] wire [31:0] l_uop_17_inst; // @[lsu.scala:1728:25] wire [31:0] l_uop_17_debug_inst; // @[lsu.scala:1728:25] wire l_uop_17_is_rvc; // @[lsu.scala:1728:25] wire [39:0] l_uop_17_debug_pc; // @[lsu.scala:1728:25] wire l_uop_17_iw_issued; // @[lsu.scala:1728:25] wire l_uop_17_iw_issued_partial_agen; // @[lsu.scala:1728:25] wire l_uop_17_iw_issued_partial_dgen; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_iw_p1_speculative_child; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_iw_p2_speculative_child; // @[lsu.scala:1728:25] wire l_uop_17_iw_p1_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_17_iw_p2_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_17_iw_p3_bypass_hint; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_dis_col_sel; // @[lsu.scala:1728:25] wire [11:0] l_uop_17_br_mask; // @[lsu.scala:1728:25] wire [3:0] l_uop_17_br_tag; // @[lsu.scala:1728:25] wire [3:0] l_uop_17_br_type; // @[lsu.scala:1728:25] wire l_uop_17_is_sfb; // @[lsu.scala:1728:25] wire l_uop_17_is_fence; // @[lsu.scala:1728:25] wire l_uop_17_is_fencei; // @[lsu.scala:1728:25] wire l_uop_17_is_sfence; // @[lsu.scala:1728:25] wire l_uop_17_is_amo; // @[lsu.scala:1728:25] wire l_uop_17_is_eret; // @[lsu.scala:1728:25] wire l_uop_17_is_sys_pc2epc; // @[lsu.scala:1728:25] wire l_uop_17_is_rocc; // @[lsu.scala:1728:25] wire l_uop_17_is_mov; // @[lsu.scala:1728:25] wire [4:0] l_uop_17_ftq_idx; // @[lsu.scala:1728:25] wire l_uop_17_edge_inst; // @[lsu.scala:1728:25] wire [5:0] l_uop_17_pc_lob; // @[lsu.scala:1728:25] wire l_uop_17_taken; // @[lsu.scala:1728:25] wire l_uop_17_imm_rename; // @[lsu.scala:1728:25] wire [2:0] l_uop_17_imm_sel; // @[lsu.scala:1728:25] wire [4:0] l_uop_17_pimm; // @[lsu.scala:1728:25] wire [19:0] l_uop_17_imm_packed; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_op1_sel; // @[lsu.scala:1728:25] wire [2:0] l_uop_17_op2_sel; // @[lsu.scala:1728:25] wire [5:0] l_uop_17_rob_idx; // @[lsu.scala:1728:25] wire [3:0] l_uop_17_ldq_idx; // @[lsu.scala:1728:25] wire [3:0] l_uop_17_stq_idx; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_rxq_idx; // @[lsu.scala:1728:25] wire [6:0] l_uop_17_pdst; // @[lsu.scala:1728:25] wire [6:0] l_uop_17_prs1; // @[lsu.scala:1728:25] wire [6:0] l_uop_17_prs2; // @[lsu.scala:1728:25] wire [6:0] l_uop_17_prs3; // @[lsu.scala:1728:25] wire [4:0] l_uop_17_ppred; // @[lsu.scala:1728:25] wire l_uop_17_prs1_busy; // @[lsu.scala:1728:25] wire l_uop_17_prs2_busy; // @[lsu.scala:1728:25] wire l_uop_17_prs3_busy; // @[lsu.scala:1728:25] wire l_uop_17_ppred_busy; // @[lsu.scala:1728:25] wire [6:0] l_uop_17_stale_pdst; // @[lsu.scala:1728:25] wire l_uop_17_exception; // @[lsu.scala:1728:25] wire [63:0] l_uop_17_exc_cause; // @[lsu.scala:1728:25] wire [4:0] l_uop_17_mem_cmd; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_mem_size; // @[lsu.scala:1728:25] wire l_uop_17_mem_signed; // @[lsu.scala:1728:25] wire l_uop_17_uses_ldq; // @[lsu.scala:1728:25] wire l_uop_17_uses_stq; // @[lsu.scala:1728:25] wire l_uop_17_is_unique; // @[lsu.scala:1728:25] wire l_uop_17_flush_on_commit; // @[lsu.scala:1728:25] wire [2:0] l_uop_17_csr_cmd; // @[lsu.scala:1728:25] wire l_uop_17_ldst_is_rs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_17_ldst; // @[lsu.scala:1728:25] wire [5:0] l_uop_17_lrs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_17_lrs2; // @[lsu.scala:1728:25] wire [5:0] l_uop_17_lrs3; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_dst_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_lrs1_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_lrs2_rtype; // @[lsu.scala:1728:25] wire l_uop_17_frs3_en; // @[lsu.scala:1728:25] wire l_uop_17_fcn_dw; // @[lsu.scala:1728:25] wire [4:0] l_uop_17_fcn_op; // @[lsu.scala:1728:25] wire l_uop_17_fp_val; // @[lsu.scala:1728:25] wire [2:0] l_uop_17_fp_rm; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_fp_typ; // @[lsu.scala:1728:25] wire l_uop_17_xcpt_pf_if; // @[lsu.scala:1728:25] wire l_uop_17_xcpt_ae_if; // @[lsu.scala:1728:25] wire l_uop_17_xcpt_ma_if; // @[lsu.scala:1728:25] wire l_uop_17_bp_debug_if; // @[lsu.scala:1728:25] wire l_uop_17_bp_xcpt_if; // @[lsu.scala:1728:25] wire [2:0] l_uop_17_debug_fsrc; // @[lsu.scala:1728:25] wire [2:0] l_uop_17_debug_tsrc; // @[lsu.scala:1728:25] assign l_uop_17_inst = _GEN_76[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_debug_inst = _GEN_77[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_rvc = _GEN_78[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_debug_pc = _GEN_79[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iq_type_0 = _GEN_80[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iq_type_1 = _GEN_81[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iq_type_2 = _GEN_82[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iq_type_3 = _GEN_83[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_0 = _GEN_84[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_1 = _GEN_85[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_2 = _GEN_86[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_3 = _GEN_87[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_4 = _GEN_88[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_5 = _GEN_89[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_6 = _GEN_90[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_7 = _GEN_91[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_8 = _GEN_92[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_9 = _GEN_93[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_issued = _GEN_94[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_issued_partial_agen = _GEN_95[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_issued_partial_dgen = _GEN_96[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_p1_speculative_child = _GEN_97[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_p2_speculative_child = _GEN_98[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_p1_bypass_hint = _GEN_99[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_p2_bypass_hint = _GEN_100[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_p3_bypass_hint = _GEN_101[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_dis_col_sel = _GEN_102[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_br_mask = _GEN_103[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_br_tag = _GEN_104[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_br_type = _GEN_105[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_sfb = _GEN_106[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_fence = _GEN_107[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_fencei = _GEN_108[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_sfence = _GEN_109[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_amo = _GEN_110[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_eret = _GEN_111[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_sys_pc2epc = _GEN_112[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_rocc = _GEN_113[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_mov = _GEN_114[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_ftq_idx = _GEN_115[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_edge_inst = _GEN_116[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_pc_lob = _GEN_117[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_taken = _GEN_118[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_imm_rename = _GEN_119[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_imm_sel = _GEN_120[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_pimm = _GEN_121[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_imm_packed = _GEN_122[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_op1_sel = _GEN_123[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_op2_sel = _GEN_124[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_ldst = _GEN_125[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_wen = _GEN_126[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_ren1 = _GEN_127[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_ren2 = _GEN_128[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_ren3 = _GEN_129[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_swap12 = _GEN_130[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_swap23 = _GEN_131[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_typeTagIn = _GEN_132[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_typeTagOut = _GEN_133[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_fromint = _GEN_134[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_toint = _GEN_135[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_fastpipe = _GEN_136[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_fma = _GEN_137[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_div = _GEN_138[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_sqrt = _GEN_139[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_wflags = _GEN_140[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_vec = _GEN_141[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_rob_idx = _GEN_142[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_ldq_idx = _GEN_143[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_stq_idx = _GEN_144[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_rxq_idx = _GEN_145[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_pdst = _GEN_146[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_prs1 = _GEN_147[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_prs2 = _GEN_148[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_prs3 = _GEN_149[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_ppred = _GEN_150[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_prs1_busy = _GEN_151[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_prs2_busy = _GEN_152[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_prs3_busy = _GEN_153[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_ppred_busy = _GEN_154[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_stale_pdst = _GEN_155[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_exception = _GEN_156[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_exc_cause = _GEN_157[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_mem_cmd = _GEN_158[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_mem_size = _GEN_159[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_mem_signed = _GEN_160[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_uses_ldq = _GEN_161[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_uses_stq = _GEN_162[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_unique = _GEN_163[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_flush_on_commit = _GEN_164[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_csr_cmd = _GEN_165[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_ldst_is_rs1 = _GEN_166[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_ldst = _GEN_167[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_lrs1 = _GEN_168[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_lrs2 = _GEN_169[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_lrs3 = _GEN_170[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_dst_rtype = _GEN_171[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_lrs1_rtype = _GEN_172[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_lrs2_rtype = _GEN_173[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_frs3_en = _GEN_174[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fcn_dw = _GEN_175[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fcn_op = _GEN_176[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_val = _GEN_177[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_rm = _GEN_178[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_typ = _GEN_179[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_xcpt_pf_if = _GEN_180[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_xcpt_ae_if = _GEN_181[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_xcpt_ma_if = _GEN_182[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_bp_debug_if = _GEN_183[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_bp_xcpt_if = _GEN_184[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_debug_fsrc = _GEN_185[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_debug_tsrc = _GEN_186[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] wire s_uop_19_iq_type_0; // @[lsu.scala:1729:25] wire s_uop_19_iq_type_1; // @[lsu.scala:1729:25] wire s_uop_19_iq_type_2; // @[lsu.scala:1729:25] wire s_uop_19_iq_type_3; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_0; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_1; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_2; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_3; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_4; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_5; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_6; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_7; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_8; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_9; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_ldst; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_wen; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_ren1; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_ren2; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_ren3; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_swap12; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_swap23; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_fromint; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_toint; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_fma; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_div; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_sqrt; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_wflags; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_vec; // @[lsu.scala:1729:25] wire [31:0] s_uop_19_inst; // @[lsu.scala:1729:25] wire [31:0] s_uop_19_debug_inst; // @[lsu.scala:1729:25] wire s_uop_19_is_rvc; // @[lsu.scala:1729:25] wire [39:0] s_uop_19_debug_pc; // @[lsu.scala:1729:25] wire s_uop_19_iw_issued; // @[lsu.scala:1729:25] wire s_uop_19_iw_issued_partial_agen; // @[lsu.scala:1729:25] wire s_uop_19_iw_issued_partial_dgen; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_iw_p1_speculative_child; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_iw_p2_speculative_child; // @[lsu.scala:1729:25] wire s_uop_19_iw_p1_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_19_iw_p2_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_19_iw_p3_bypass_hint; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_dis_col_sel; // @[lsu.scala:1729:25] wire [11:0] s_uop_19_br_mask; // @[lsu.scala:1729:25] wire [3:0] s_uop_19_br_tag; // @[lsu.scala:1729:25] wire [3:0] s_uop_19_br_type; // @[lsu.scala:1729:25] wire s_uop_19_is_sfb; // @[lsu.scala:1729:25] wire s_uop_19_is_fence; // @[lsu.scala:1729:25] wire s_uop_19_is_fencei; // @[lsu.scala:1729:25] wire s_uop_19_is_sfence; // @[lsu.scala:1729:25] wire s_uop_19_is_amo; // @[lsu.scala:1729:25] wire s_uop_19_is_eret; // @[lsu.scala:1729:25] wire s_uop_19_is_sys_pc2epc; // @[lsu.scala:1729:25] wire s_uop_19_is_rocc; // @[lsu.scala:1729:25] wire s_uop_19_is_mov; // @[lsu.scala:1729:25] wire [4:0] s_uop_19_ftq_idx; // @[lsu.scala:1729:25] wire s_uop_19_edge_inst; // @[lsu.scala:1729:25] wire [5:0] s_uop_19_pc_lob; // @[lsu.scala:1729:25] wire s_uop_19_taken; // @[lsu.scala:1729:25] wire s_uop_19_imm_rename; // @[lsu.scala:1729:25] wire [2:0] s_uop_19_imm_sel; // @[lsu.scala:1729:25] wire [4:0] s_uop_19_pimm; // @[lsu.scala:1729:25] wire [19:0] s_uop_19_imm_packed; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_op1_sel; // @[lsu.scala:1729:25] wire [2:0] s_uop_19_op2_sel; // @[lsu.scala:1729:25] wire [5:0] s_uop_19_rob_idx; // @[lsu.scala:1729:25] wire [3:0] s_uop_19_ldq_idx; // @[lsu.scala:1729:25] wire [3:0] s_uop_19_stq_idx; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_rxq_idx; // @[lsu.scala:1729:25] wire [6:0] s_uop_19_pdst; // @[lsu.scala:1729:25] wire [6:0] s_uop_19_prs1; // @[lsu.scala:1729:25] wire [6:0] s_uop_19_prs2; // @[lsu.scala:1729:25] wire [6:0] s_uop_19_prs3; // @[lsu.scala:1729:25] wire [4:0] s_uop_19_ppred; // @[lsu.scala:1729:25] wire s_uop_19_prs1_busy; // @[lsu.scala:1729:25] wire s_uop_19_prs2_busy; // @[lsu.scala:1729:25] wire s_uop_19_prs3_busy; // @[lsu.scala:1729:25] wire s_uop_19_ppred_busy; // @[lsu.scala:1729:25] wire [6:0] s_uop_19_stale_pdst; // @[lsu.scala:1729:25] wire s_uop_19_exception; // @[lsu.scala:1729:25] wire [63:0] s_uop_19_exc_cause; // @[lsu.scala:1729:25] wire [4:0] s_uop_19_mem_cmd; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_mem_size; // @[lsu.scala:1729:25] wire s_uop_19_mem_signed; // @[lsu.scala:1729:25] wire s_uop_19_uses_ldq; // @[lsu.scala:1729:25] wire s_uop_19_uses_stq; // @[lsu.scala:1729:25] wire s_uop_19_is_unique; // @[lsu.scala:1729:25] wire s_uop_19_flush_on_commit; // @[lsu.scala:1729:25] wire [2:0] s_uop_19_csr_cmd; // @[lsu.scala:1729:25] wire s_uop_19_ldst_is_rs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_19_ldst; // @[lsu.scala:1729:25] wire [5:0] s_uop_19_lrs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_19_lrs2; // @[lsu.scala:1729:25] wire [5:0] s_uop_19_lrs3; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_dst_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_lrs1_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_lrs2_rtype; // @[lsu.scala:1729:25] wire s_uop_19_frs3_en; // @[lsu.scala:1729:25] wire s_uop_19_fcn_dw; // @[lsu.scala:1729:25] wire [4:0] s_uop_19_fcn_op; // @[lsu.scala:1729:25] wire s_uop_19_fp_val; // @[lsu.scala:1729:25] wire [2:0] s_uop_19_fp_rm; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_fp_typ; // @[lsu.scala:1729:25] wire s_uop_19_xcpt_pf_if; // @[lsu.scala:1729:25] wire s_uop_19_xcpt_ae_if; // @[lsu.scala:1729:25] wire s_uop_19_xcpt_ma_if; // @[lsu.scala:1729:25] wire s_uop_19_bp_debug_if; // @[lsu.scala:1729:25] wire s_uop_19_bp_xcpt_if; // @[lsu.scala:1729:25] wire [2:0] s_uop_19_debug_fsrc; // @[lsu.scala:1729:25] wire [2:0] s_uop_19_debug_tsrc; // @[lsu.scala:1729:25] assign s_uop_19_inst = _GEN_200[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_debug_inst = _GEN_201[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_rvc = _GEN_202[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_debug_pc = _GEN_203[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iq_type_0 = _GEN_204[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iq_type_1 = _GEN_205[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iq_type_2 = _GEN_206[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iq_type_3 = _GEN_207[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_0 = _GEN_208[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_1 = _GEN_209[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_2 = _GEN_210[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_3 = _GEN_211[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_4 = _GEN_212[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_5 = _GEN_213[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_6 = _GEN_214[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_7 = _GEN_215[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_8 = _GEN_216[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_9 = _GEN_217[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_issued = _GEN_218[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_issued_partial_agen = _GEN_219[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_issued_partial_dgen = _GEN_220[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_p1_speculative_child = _GEN_221[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_p2_speculative_child = _GEN_222[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_p1_bypass_hint = _GEN_223[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_p2_bypass_hint = _GEN_224[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_p3_bypass_hint = _GEN_225[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_dis_col_sel = _GEN_226[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_br_mask = _GEN_227[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_br_tag = _GEN_228[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_br_type = _GEN_229[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_sfb = _GEN_230[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_fence = _GEN_231[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_fencei = _GEN_232[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_sfence = _GEN_233[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_amo = _GEN_234[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_eret = _GEN_235[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_sys_pc2epc = _GEN_236[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_rocc = _GEN_237[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_mov = _GEN_238[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_ftq_idx = _GEN_239[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_edge_inst = _GEN_240[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_pc_lob = _GEN_241[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_taken = _GEN_242[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_imm_rename = _GEN_243[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_imm_sel = _GEN_244[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_pimm = _GEN_245[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_imm_packed = _GEN_246[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_op1_sel = _GEN_247[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_op2_sel = _GEN_248[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_ldst = _GEN_249[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_wen = _GEN_250[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_ren1 = _GEN_251[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_ren2 = _GEN_252[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_ren3 = _GEN_253[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_swap12 = _GEN_254[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_swap23 = _GEN_255[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_typeTagIn = _GEN_256[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_typeTagOut = _GEN_257[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_fromint = _GEN_258[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_toint = _GEN_259[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_fastpipe = _GEN_260[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_fma = _GEN_261[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_div = _GEN_262[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_sqrt = _GEN_263[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_wflags = _GEN_264[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_vec = _GEN_265[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_rob_idx = _GEN_266[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_ldq_idx = _GEN_267[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_stq_idx = _GEN_268[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_rxq_idx = _GEN_269[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_pdst = _GEN_270[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_prs1 = _GEN_271[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_prs2 = _GEN_272[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_prs3 = _GEN_273[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_ppred = _GEN_274[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_prs1_busy = _GEN_275[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_prs2_busy = _GEN_276[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_prs3_busy = _GEN_277[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_ppred_busy = _GEN_278[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_stale_pdst = _GEN_279[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_exception = _GEN_280[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_exc_cause = _GEN_281[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_mem_cmd = _GEN_282[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_mem_size = _GEN_283[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_mem_signed = _GEN_284[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_uses_ldq = _GEN_285[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_uses_stq = _GEN_286[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_unique = _GEN_287[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_flush_on_commit = _GEN_288[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_csr_cmd = _GEN_289[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_ldst_is_rs1 = _GEN_290[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_ldst = _GEN_291[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_lrs1 = _GEN_292[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_lrs2 = _GEN_293[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_lrs3 = _GEN_294[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_dst_rtype = _GEN_295[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_lrs1_rtype = _GEN_296[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_lrs2_rtype = _GEN_297[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_frs3_en = _GEN_298[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fcn_dw = _GEN_299[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fcn_op = _GEN_300[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_val = _GEN_301[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_rm = _GEN_302[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_typ = _GEN_303[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_xcpt_pf_if = _GEN_304[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_xcpt_ae_if = _GEN_305[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_xcpt_ma_if = _GEN_306[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_bp_debug_if = _GEN_307[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_bp_xcpt_if = _GEN_308[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_debug_fsrc = _GEN_309[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_debug_tsrc = _GEN_310[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] wire _GEN_676 = ~commit_store_1 & commit_load_1; // @[lsu.scala:1724:49, :1725:49, :1731:5, :1735:31] wire _GEN_677 = _GEN_676 & ~reset; // @[lsu.scala:1735:31, :1736:14]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_14( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [4:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [4:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_26 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_32 = 1'h1; // @[Parameters.scala:56:32] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_3 = 3'h6; // @[Misc.scala:202:34] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_13 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1_decode = 3'h7; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _legal_source_uncommonBits_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_6 = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = ~_source_ok_T_6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_9 & _source_ok_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_9 = _uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_12 = _uncommonBits_T_12[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_13 = _uncommonBits_T_13[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_14 = _uncommonBits_T_14[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_15 = _uncommonBits_T_15[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_12 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_18 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_13 = _source_ok_T_12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_16 = source_ok_uncommonBits_2 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_17 = _source_ok_T_15 & _source_ok_T_16; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_22 = source_ok_uncommonBits_3 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_1 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :309:31] wire [3:0] uncommonBits_18 = _uncommonBits_T_18[3:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T = io_in_b_bits_source_0[4]; // @[Monitor.scala:36:7] wire _legal_source_T_6 = io_in_b_bits_source_0[4]; // @[Monitor.scala:36:7] wire [3:0] uncommonBits_19 = _uncommonBits_T_19[3:0]; // @[Parameters.scala:52:{29,56}] wire [31:0] _address_ok_T = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire [3:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_1 = _legal_source_T; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_3 = _legal_source_T_1; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_4 = legal_source_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_3 & _legal_source_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire [3:0] legal_source_uncommonBits_1 = _legal_source_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_7 = ~_legal_source_T_6; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_9 = _legal_source_T_7; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_10 = legal_source_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_11 = _legal_source_T_9 & _legal_source_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire _legal_source_WIRE_1 = _legal_source_T_11; // @[Parameters.scala:1138:31] wire [4:0] _legal_source_T_12 = {_legal_source_WIRE_0, 4'h0}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_14 = _legal_source_T_12; // @[Mux.scala:30:73] wire [4:0] _legal_source_WIRE_1_0 = _legal_source_T_14; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_24 = io_in_c_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = io_in_c_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_25 = _source_ok_T_24; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_27 = _source_ok_T_25; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_28 = source_ok_uncommonBits_4 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_29 = _source_ok_T_27 & _source_ok_T_28; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_31 = ~_source_ok_T_30; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_33 = _source_ok_T_31; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = source_ok_uncommonBits_5 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_35 = _source_ok_T_33 & _source_ok_T_34; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_1 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_0 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_0; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [31:0] _address_ok_T_5 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [3:0] uncommonBits_20 = _uncommonBits_T_20[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_21 = _uncommonBits_T_21[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_24 = _uncommonBits_T_24[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_25 = _uncommonBits_T_25[3:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :367:31] wire _T_1322 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1322; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1322; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1396 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1396; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1396; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1396; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_1396; // @[Decoupled.scala:51:35] wire [12:0] _GEN_1 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_1; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_1; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [2:0] b_first_counter; // @[Edges.scala:229:27] wire [3:0] _b_first_counter1_T = {1'h0, b_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] b_first_counter1 = _b_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _b_first_counter_T = b_first ? 3'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [4:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_1393 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_1393; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_1393; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [4:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [24:0] inflight; // @[Monitor.scala:614:27] reg [99:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [99:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [24:0] a_set; // @[Monitor.scala:626:34] wire [24:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [99:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [99:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_2 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_2; // @[Monitor.scala:637:69] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:637:69, :641:65] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_2; // @[Monitor.scala:637:69, :680:101] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:637:69, :681:99] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_2; // @[Monitor.scala:637:69, :749:69] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:637:69, :750:67] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_2; // @[Monitor.scala:637:69, :790:101] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:637:69, :791:99] wire [99:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [99:0] _a_opcode_lookup_T_6 = {96'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [99:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[99:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [99:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [99:0] _a_size_lookup_T_6 = {96'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [99:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[99:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[24:0] : 25'h0; // @[OneHot.scala:58:35] wire _T_1248 = _T_1322 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1248 ? _a_set_T[24:0] : 25'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1248 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1248 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _GEN_4 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_4; // @[Monitor.scala:659:79] wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_4; // @[Monitor.scala:659:79, :660:77] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1248 ? _a_opcodes_set_T_1[99:0] : 100'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1248 ? _a_sizes_set_T_1[99:0] : 100'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [24:0] d_clr; // @[Monitor.scala:664:34] wire [24:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [99:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [99:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1294 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_6; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1294 & ~d_release_ack ? _d_clr_wo_ready_T[24:0] : 25'h0; // @[OneHot.scala:58:35] wire _T_1263 = _T_1396 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1263 ? _d_clr_T[24:0] : 25'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1263 ? _d_opcodes_clr_T_5[99:0] : 100'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1263 ? _d_sizes_clr_T_5[99:0] : 100'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [24:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [24:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [24:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [99:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [99:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [99:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [99:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [99:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [99:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [24:0] inflight_1; // @[Monitor.scala:726:35] reg [99:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [99:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [24:0] c_set; // @[Monitor.scala:738:34] wire [24:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [99:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [99:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [99:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [99:0] _c_opcode_lookup_T_6 = {96'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [99:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[99:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [99:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [99:0] _c_size_lookup_T_6 = {96'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [99:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[99:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [31:0] _GEN_7 = 32'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_7; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[24:0] : 25'h0; // @[OneHot.scala:58:35] wire _T_1335 = _T_1393 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_1335 ? _c_set_T[24:0] : 25'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_1335 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_1335 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [7:0] _GEN_8 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [7:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_8; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_8; // @[Monitor.scala:767:79, :768:77] wire [258:0] _c_opcodes_set_T_1 = {255'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_1335 ? _c_opcodes_set_T_1[99:0] : 100'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [258:0] _c_sizes_set_T_1 = {255'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_1335 ? _c_sizes_set_T_1[99:0] : 100'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [24:0] d_clr_1; // @[Monitor.scala:774:34] wire [24:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [99:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [99:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1366 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1366 & d_release_ack_1 ? _d_clr_wo_ready_T_1[24:0] : 25'h0; // @[OneHot.scala:58:35] wire _T_1348 = _T_1396 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1348 ? _d_clr_T_1[24:0] : 25'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1348 ? _d_opcodes_clr_T_11[99:0] : 100'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1348 ? _d_sizes_clr_T_11[99:0] : 100'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [24:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [24:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [24:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [99:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [99:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [99:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [99:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [99:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [99:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [6:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [6:0] d_set; // @[Monitor.scala:833:25] wire _T_1402 = _T_1396 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_1402 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35] wire [6:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _e_clr_T = 8'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ class IntXbar()(implicit p: Parameters) extends LazyModule { val intnode = new IntNexusNode( sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, sourceFn = { seq => IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten) }) { override def circuitIdentity = outputs == 1 && inputs == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { override def desiredName = s"IntXbar_i${intnode.in.size}_o${intnode.out.size}" val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten intnode.out.foreach { case (o, _) => o := cat } } } class IntSyncXbar()(implicit p: Parameters) extends LazyModule { val intnode = new IntSyncNexusNode( sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, sourceFn = { seq => IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten) }) { override def circuitIdentity = outputs == 1 && inputs == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncXbar_i${intnode.in.size}_o${intnode.out.size}" val cat = intnode.in.map { case (i, e) => i.sync.take(e.source.num) }.flatten intnode.out.foreach { case (o, _) => o.sync := cat } } } object IntXbar { def apply()(implicit p: Parameters): IntNode = { val xbar = LazyModule(new IntXbar) xbar.intnode } } object IntSyncXbar { def apply()(implicit p: Parameters): IntSyncNode = { val xbar = LazyModule(new IntSyncXbar) xbar.intnode } }	module IntXbar_i1_o1_2(); // @[Xbar.scala:22:9] wire auto_anon_in_0 = 1'h0; // @[Xbar.scala:22:9] wire auto_anon_out_0 = 1'h0; // @[Xbar.scala:22:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire anonIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_0 = 1'h0; // @[MixedNode.scala:542:17] endmodule
Generate the Verilog code corresponding to the following Chisel files. File icache.scala: //**************************************************************************** // Copyright (c) 2017 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // ICache //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.ifu import chisel3._ import chisel3.util._ import chisel3.util.random._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property._ import freechips.rocketchip.rocket.{HasL1ICacheParameters, ICacheParams, ICacheErrors, ICacheReq} import boom.v4.common._ import boom.v4.util.{BoomCoreStringPrefix} / * ICache module * * @param icacheParams parameters for the icache * @param hartId the id of the hardware thread in the cache * @param enableBlackBox use a blackbox icache / class ICache( val icacheParams: ICacheParams, val tileId: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new ICacheModule(this) val masterNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( sourceId = IdRange(0, 1 + icacheParams.prefetch.toInt), // 0=refill, 1=hint name = s"Core ${tileId} ICache"))))) val size = icacheParams.nSets icacheParams.nWays * icacheParams.blockBytes private val wordBytes = icacheParams.fetchBytes } /** * IO Signals leaving the ICache * * @param outer top level ICache class / class ICacheResp(val outer: ICache) extends Bundle { val data = UInt((outer.icacheParams.fetchBytes8).W) val replay = Bool() val ae = Bool() } /** * IO Signals for interacting with the ICache * * @param outer top level ICache class / class ICacheBundle(val outer: ICache) extends BoomBundle()(outer.p) with HasBoomFrontendParameters { val req = Flipped(Decoupled(new ICacheReq)) val s1_paddr = Input(UInt(paddrBits.W)) // delayed one cycle w.r.t. req val s1_kill = Input(Bool()) // delayed one cycle w.r.t. req val s2_kill = Input(Bool()) // delayed two cycles; prevents I$ miss emission val s2_prefetch = Input(Bool()) // should I$ prefetch next line on a miss? val resp = Valid(new ICacheResp(outer)) val invalidate = Input(Bool()) val perf = Output(new Bundle { val acquire = Bool() }) } /* * Main ICache module * * @param outer top level ICache class / class ICacheModule(outer: ICache) extends LazyModuleImp(outer) with HasBoomFrontendParameters { override def tlBundleParams = outer.masterNode.out.head._2.bundle val enableICacheDelay = tileParams.core.asInstanceOf[BoomCoreParams].enableICacheDelay val icacheSinglePorted = tileParams.core.asInstanceOf[BoomCoreParams].icacheSinglePorted val io = IO(new ICacheBundle(outer)) val (tl_out, edge_out) = outer.masterNode.out(0) require(isPow2(nSets) && isPow2(nWays)) require(usingVM) require(pgIdxBits >= untagBits) // How many bits do we intend to fetch at most every cycle? val wordBits = outer.icacheParams.fetchBytes8 // Each of these cases require some special-case handling. require (tl_out.d.bits.data.getWidth == wordBits) val s0_valid = io.req.fire val s0_vaddr = io.req.bits.addr val s1_valid = RegNext(s0_valid, false.B) val s1_tag_hit = Wire(Vec(nWays, Bool())) val s1_hit = s1_tag_hit.reduce(_\|\|_) val s2_valid = RegNext(s1_valid && !io.s1_kill, false.B) val s2_hit = RegNext(s1_hit) val invalidated = Reg(Bool()) val refill_valid = RegInit(false.B) val refill_fire = tl_out.a.fire val s2_miss = s2_valid && !s2_hit && !RegNext(refill_valid) val refill_paddr = RegEnable(io.s1_paddr, s1_valid && !(refill_valid \|\| s2_miss)) val refill_tag = refill_paddr(tagBits+untagBits-1,untagBits) val refill_idx = refill_paddr(untagBits-1,blockOffBits) val refill_one_beat = tl_out.d.fire && edge_out.hasData(tl_out.d.bits) io.req.ready := !refill_one_beat val (_, _, d_done, refill_cnt) = edge_out.count(tl_out.d) val refill_done = refill_one_beat && d_done tl_out.d.ready := true.B require (edge_out.manager.minLatency > 0) val repl_way = if (isDM) 0.U else LFSR(16, refill_fire)(log2Ceil(nWays)-1,0) val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(tagBits.W))) val tag_rdata = if (icacheSinglePorted) { tag_array.read(s0_vaddr(untagBits-1, blockOffBits), !refill_done && s0_valid) } else { tag_array.read(s0_vaddr(untagBits-1, blockOffBits), io.req.valid) } when (refill_done) { tag_array.write(refill_idx, VecInit(Seq.fill(nWays)(refill_tag)), Seq.tabulate(nWays)(repl_way === _.U)) } val vb_array = RegInit(0.U((nSetsnWays).W)) when (refill_one_beat) { vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), refill_done && !invalidated) } when (io.invalidate) { vb_array := 0.U invalidated := true.B } val s2_dout = Wire(Vec(nWays, UInt(wordBits.W))) val s1_bankid = Wire(Bool()) for (i <- 0 until nWays) { val s1_idx = io.s1_paddr(untagBits-1,blockOffBits) val s1_tag = io.s1_paddr(tagBits+untagBits-1,untagBits) val s1_vb = vb_array(Cat(i.U, s1_idx)) val tag = tag_rdata(i) s1_tag_hit(i) := s1_vb && tag === s1_tag } assert(PopCount(s1_tag_hit) <= 1.U \|\| !s1_valid) val ramDepth = nSets refillCycles val dataArrays = Seq.tabulate(nBanks) { b => DescribedSRAM( name = s"dataArrayB${b}", desc = "ICache Data Array", size = ramDepth, data = Vec(nWays, UInt((wordBits/nBanks).W)) ) } if (nBanks == 1) { // Use unbanked icache for narrow accesses. s1_bankid := 0.U val array = dataArrays(0) def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) val s0_ren = s0_valid val wen = refill_one_beat && !invalidated val mem_idx = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) \| refill_cnt, row(s0_vaddr)) val wmask = UIntToOH(repl_way)(nWays-1,0).asBools when (wen) { array.write(mem_idx, VecInit(Seq.fill(nWays) { tl_out.d.bits.data }), wmask) } if (enableICacheDelay) { if (icacheSinglePorted) s2_dout := array.read(RegNext(mem_idx), RegNext(!wen && s0_ren)) else s2_dout := array.read(RegNext(mem_idx), RegNext(s0_ren)) } else { if (icacheSinglePorted) s2_dout := RegNext(array.read(mem_idx, !wen && s0_ren)) else s2_dout := RegNext(array.read(mem_idx, io.req.valid)) } } else { // Use two banks, interleaved. val array_0 = dataArrays(0) val array_1 = dataArrays(1) require (nBanks == 2) // Bank0 row's id wraps around if Bank1 is the starting bank. def b0Row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) + bank(addr) // Bank1 row's id stays the same regardless of which Bank has the fetch address. def b1Row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) s1_bankid := RegNext(bank(s0_vaddr)) val s0_ren = s0_valid val wen = (refill_one_beat && !invalidated) val wmask = UIntToOH(repl_way)(nWays-1,0).asBools var mem_idx0: UInt = null var mem_idx1: UInt = null // write a refill beat across both banks. mem_idx0 = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) \| refill_cnt, b0Row(s0_vaddr)) mem_idx1 = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) \| refill_cnt, b1Row(s0_vaddr)) when (wen) { val data = tl_out.d.bits.data val wdata_0 = VecInit(Seq.fill(nWays) { data(wordBits/2-1, 0) }) val wdata_1 = VecInit(Seq.fill(nWays) { data(wordBits-1, wordBits/2) }) array_0.write(mem_idx0, wdata_0, wmask) array_1.write(mem_idx1, wdata_1, wmask) } val rdata_0 = Wire(Vec(nWays, UInt((wordBits/nBanks).W))) val rdata_1 = Wire(Vec(nWays, UInt((wordBits/nBanks).W))) if (enableICacheDelay) { if (icacheSinglePorted) { rdata_0 := array_0.read(RegNext(mem_idx0), RegNext(!wen && s0_ren)) rdata_1 := array_1.read(RegNext(mem_idx1), RegNext(!wen && s0_ren)) } else { rdata_0 := array_0.read(RegNext(mem_idx0), RegNext(s0_ren)) rdata_1 := array_1.read(RegNext(mem_idx1), RegNext(s0_ren)) } } else { if (icacheSinglePorted) { rdata_0 := RegNext(array_0.read(mem_idx0, !wen && s0_ren)) rdata_1 := RegNext(array_1.read(mem_idx1, !wen && s0_ren)) } else { rdata_0 := RegNext(array_0.read(mem_idx0, io.req.valid)) rdata_1 := RegNext(array_1.read(mem_idx1, io.req.valid)) } } for (w <- 0 until nWays) { s2_dout(w) := Cat(rdata_1(w), rdata_0(w)) } } val s2_tag_hit = RegNext(s1_tag_hit) val s2_hit_way = OHToUInt(s2_tag_hit) val s2_bankid = RegNext(s1_bankid) val s2_way_mux = Mux1H(s2_tag_hit, s2_dout) val s2_unbanked_data = s2_way_mux val sz = s2_way_mux.getWidth val s2_bank0_data = s2_way_mux(sz/2-1,0) val s2_bank1_data = s2_way_mux(sz-1,sz/2) val s2_data = if (nBanks == 2) { Mux(s2_bankid, Cat(s2_bank0_data, s2_bank1_data), Cat(s2_bank1_data, s2_bank0_data)) } else { s2_unbanked_data } io.resp.bits.data := s2_data io.resp.bits.ae := DontCare io.resp.bits.replay := DontCare io.resp.valid := s2_valid && s2_hit tl_out.a.valid := s2_miss && !refill_valid && !io.s2_kill tl_out.a.bits := edge_out.Get( fromSource = 0.U, toAddress = (refill_paddr >> blockOffBits) << blockOffBits, lgSize = lgCacheBlockBytes.U)._2 tl_out.b.ready := true.B tl_out.c.valid := false.B tl_out.e.valid := false.B io.perf.acquire := tl_out.a.fire when (!refill_valid) { invalidated := false.B } when (refill_fire) { refill_valid := true.B } when (refill_done) { refill_valid := false.B } override def toString: String = BoomCoreStringPrefix( "==L1-ICache==", "Fetch bytes : " + cacheParams.fetchBytes, "Block bytes : " + (1 << blockOffBits), "Word bits : " + wordBits, "Sets : " + nSets, "Ways : " + nWays, "Refill cycles : " + refillCycles, "RAMs : (" + wordBits/nBanks + " x " + nSets*refillCycles + ") using " + nBanks + " banks", "" + (if (nBanks == 2) "Dual-banked" else "Single-banked"), "I-TLB ways : " + cacheParams.nTLBWays + "\n") }	module tag_array_0( // @[icache.scala:141:30] input [5:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [79:0] RW0_wdata, output [79:0] RW0_rdata, input [3:0] RW0_wmask ); tag_array_0_ext tag_array_0_ext ( // @[icache.scala:141:30] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[icache.scala:141:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_350( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_90( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File BankBinder.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} case class BankBinderNode(mask: BigInt)(implicit valName: ValName) extends TLCustomNode { private val bit = mask & -mask val maxXfer = TransferSizes(1, if (bit == 0 \|\| bit > 4096) 4096 else bit.toInt) val ids = AddressSet.enumerateMask(mask) def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { val ports = ids.size val oStar = if (oStars == 0) 0 else (ports - oKnown) / oStars val iStar = if (iStars == 0) 0 else (ports - iKnown) / iStars require (ports == iKnown + iStariStars, s"${name} must have ${ports} inputs, but has ${iKnown} + ${iStar}${iStars} (at ${lazyModule.line})") require (ports == oKnown + oStaroStars, s"${name} must have ${ports} outputs, but has ${oKnown} + ${oStar}${oStars} (at ${lazyModule.line})") (iStar, oStar) } def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = (p zip ids) map { case (cp, id) => cp.v1copy(clients = cp.clients.map { c => c.v1copy( visibility = c.visibility.flatMap { a => a.intersect(AddressSet(id, ~mask))}, supportsProbe = c.supports.probe intersect maxXfer, supportsArithmetic = c.supports.arithmetic intersect maxXfer, supportsLogical = c.supports.logical intersect maxXfer, supportsGet = c.supports.get intersect maxXfer, supportsPutFull = c.supports.putFull intersect maxXfer, supportsPutPartial = c.supports.putPartial intersect maxXfer, supportsHint = c.supports.hint intersect maxXfer)})} def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = (p zip ids) map { case (mp, id) => mp.v1copy(managers = mp.managers.flatMap { m => val addresses = m.address.flatMap(a => a.intersect(AddressSet(id, ~mask))) if (addresses.nonEmpty) Some(m.v1copy( address = addresses, supportsAcquireT = m.supportsAcquireT intersect maxXfer, supportsAcquireB = m.supportsAcquireB intersect maxXfer, supportsArithmetic = m.supportsArithmetic intersect maxXfer, supportsLogical = m.supportsLogical intersect maxXfer, supportsGet = m.supportsGet intersect maxXfer, supportsPutFull = m.supportsPutFull intersect maxXfer, supportsPutPartial = m.supportsPutPartial intersect maxXfer, supportsHint = m.supportsHint intersect maxXfer)) else None })} } /* A BankBinder is used to divide contiguous memory regions into banks, suitable for a cache / class BankBinder(mask: BigInt)(implicit p: Parameters) extends LazyModule { val node = BankBinderNode(mask) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out <> in } } } object BankBinder { def apply(mask: BigInt)(implicit p: Parameters): TLNode = { val binder = LazyModule(new BankBinder(mask)) binder.node } def apply(nBanks: Int, granularity: Int)(implicit p: Parameters): TLNode = { if (nBanks > 0) apply(granularity (nBanks-1)) else TLTempNode() } } File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Filter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes} class TLFilter( mfilter: TLFilter.ManagerFilter = TLFilter.mIdentity, cfilter: TLFilter.ClientFilter = TLFilter.cIdentity )(implicit p: Parameters) extends LazyModule { val node = new TLAdapterNode( clientFn = { cp => cp.v1copy(clients = cp.clients.flatMap { c => val out = cfilter(c) out.map { o => // Confirm the filter only REMOVES capability require (c.sourceId.contains(o.sourceId)) require (c.supports.probe.contains(o.supports.probe)) require (c.supports.arithmetic.contains(o.supports.arithmetic)) require (c.supports.logical.contains(o.supports.logical)) require (c.supports.get.contains(o.supports.get)) require (c.supports.putFull.contains(o.supports.putFull)) require (c.supports.putPartial.contains(o.supports.putPartial)) require (c.supports.hint.contains(o.supports.hint)) require (!c.requestFifo \|\| o.requestFifo) } out })}, managerFn = { mp => val managers = mp.managers.flatMap { m => val out = mfilter(m) out.map { o => // Confirm the filter only REMOVES capability o.address.foreach { a => require (m.address.map(_.contains(a)).reduce(_\|\|_)) } require (o.regionType <= m.regionType) // we allow executable to be changed both ways require (m.supportsAcquireT.contains(o.supportsAcquireT)) require (m.supportsAcquireB.contains(o.supportsAcquireB)) require (m.supportsArithmetic.contains(o.supportsArithmetic)) require (m.supportsLogical.contains(o.supportsLogical)) require (m.supportsGet.contains(o.supportsGet)) require (m.supportsPutFull.contains(o.supportsPutFull)) require (m.supportsPutPartial.contains(o.supportsPutPartial)) require (m.supportsHint.contains(o.supportsHint)) require (!o.fifoId.isDefined \|\| m.fifoId == o.fifoId) } out } mp.v1copy(managers = managers, endSinkId = if (managers.exists(_.supportsAcquireB)) mp.endSinkId else 0) } ) { override def circuitIdentity = true } lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out <> in // In case the inner interface removes Acquire, tie-off the channels if (!edgeIn.manager.anySupportAcquireB) { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFilter { type ManagerFilter = TLSlaveParameters => Option[TLSlaveParameters] type ClientFilter = TLMasterParameters => Option[TLMasterParameters] // preserve manager visibility def mIdentity: ManagerFilter = { m => Some(m) } // preserve client visibility def cIdentity: ClientFilter = { c => Some(c) } // make only the intersected address sets visible def mSelectIntersect(select: AddressSet): ManagerFilter = { m => val filtered = m.address.map(_.intersect(select)).flatten val alignment = select.alignment /* alignment 0 means 'select' selected everything / transferSizeHelper(m, filtered, alignment) } // make everything except the intersected address sets visible def mSubtract(excepts: Seq[AddressSet]): ManagerFilter = { m => val filtered = excepts.foldLeft(m.address) { (a,e) => a.flatMap(_.subtract(e)) } val alignment: BigInt = if (filtered.isEmpty) 0 else filtered.map(_.alignment).min transferSizeHelper(m, filtered, alignment) } def mSubtract(except: AddressSet): ManagerFilter = { m => mSubtract(Seq(except))(m) } // adjust supported transfer sizes based on filtered intersection private def transferSizeHelper(m: TLSlaveParameters, filtered: Seq[AddressSet], alignment: BigInt): Option[TLSlaveParameters] = { val maxTransfer = 1 << 30 val capTransfer = if (alignment == 0 \|\| alignment > maxTransfer) maxTransfer else alignment.toInt val cap = TransferSizes(1, capTransfer) if (filtered.isEmpty) { None } else { Some(m.v1copy( address = filtered, supportsAcquireT = m.supportsAcquireT .intersect(cap), supportsAcquireB = m.supportsAcquireB .intersect(cap), supportsArithmetic = m.supportsArithmetic.intersect(cap), supportsLogical = m.supportsLogical .intersect(cap), supportsGet = m.supportsGet .intersect(cap), supportsPutFull = m.supportsPutFull .intersect(cap), supportsPutPartial = m.supportsPutPartial.intersect(cap), supportsHint = m.supportsHint .intersect(cap))) } } // hide any fully contained address sets def mHideContained(containedBy: AddressSet): ManagerFilter = { m => val filtered = m.address.filterNot(containedBy.contains(_)) if (filtered.isEmpty) None else Some(m.v1copy(address = filtered)) } // hide all cacheable managers def mHideCacheable: ManagerFilter = { m => if (m.supportsAcquireB) None else Some(m) } // make visible only cacheable managers def mSelectCacheable: ManagerFilter = { m => if (m.supportsAcquireB) Some(m) else None } // cacheable managers cannot be acquired from def mMaskCacheable: ManagerFilter = { m => if (m.supportsAcquireB) { Some(m.v1copy( regionType = RegionType.UNCACHED, supportsAcquireB = TransferSizes.none, supportsAcquireT = TransferSizes.none, alwaysGrantsT = false)) } else { Some(m) } } // only cacheable managers are visible, but cannot be acquired from def mSelectAndMaskCacheable: ManagerFilter = { m => if (m.supportsAcquireB) { Some(m.v1copy( regionType = RegionType.UNCACHED, supportsAcquireB = TransferSizes.none, supportsAcquireT = TransferSizes.none, alwaysGrantsT = false)) } else { None } } // hide all caching clients def cHideCaching: ClientFilter = { c => if (c.supports.probe) None else Some(c) } // onyl caching clients are visible def cSelectCaching: ClientFilter = { c => if (c.supports.probe) Some(c) else None } // removes resources from managers def mResourceRemover: ManagerFilter = { m => Some(m.v2copy(resources=Nil)) } // default application applies neither type of filter unless overridden def apply( mfilter: ManagerFilter = TLFilter.mIdentity, cfilter: ClientFilter = TLFilter.cIdentity )(implicit p: Parameters): TLNode = { val filter = LazyModule(new TLFilter(mfilter, cfilter)) filter.node } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File Jbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet class TLJbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) extends LazyModule { val node: TLJunctionNode = new TLJunctionNode( clientFn = { seq => Seq.fill(node.dRatio)(seq(0).v1copy( minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } )) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() Seq.fill(node.uRatio)(seq(0).v1copy( minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } )) }) { override def circuitIdentity = uRatio == 1 && dRatio == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { node.inoutGrouped.foreach { case (in, out) => TLXbar.circuit(policy, in, out) } } } object TLJbar { def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) = { val jbar = LazyModule(new TLJbar(policy)) jbar.node } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLJbarTestImp(nClients: Int, nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val jbar = LazyModule(new TLJbar) val fuzzers = Seq.fill(nClients) { val fuzzer = LazyModule(new TLFuzzer(txns)) jbar.node := TLXbar() := TLDelayer(0.1) := fuzzer.node fuzzer } for (n <- 0 until nManagers) { TLRAM(AddressSet(0x0+0x400n, 0x3ff)) := TLFragmenter(4, 256) := TLDelayer(0.1) := jbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.map(_.module.io.finished).reduce(_ && _) } } class TLJbarTest(nClients: Int, nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLJbarTestImp(nClients, nManagers, txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in \|\| corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ \|\| !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready \|\| !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel \| count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)outByteswidth-1, ioutByteswidth) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes8-1, edgeOut.manager.beatBytes8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Configs.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tilelink._ import sifive.blocks.inclusivecache._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util._ import sifive.blocks.inclusivecache.InclusiveCacheParameters case class InclusiveCacheParams( ways: Int, sets: Int, writeBytes: Int, // backing store update granularity portFactor: Int, // numSubBanks = (widest TL port portFactor) / writeBytes memCycles: Int, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) physicalFilter: Option[PhysicalFilterParams] = None, hintsSkipProbe: Boolean = false, // do hints probe the same client bankedControl: Boolean = false, // bank the cache ctrl with the cache banks ctrlAddr: Option[Int] = Some(InclusiveCacheParameters.L2ControlAddress), // Interior/Exterior refer to placement either inside the Scheduler or outside it // Inner/Outer refer to buffers on the front (towards cores) or back (towards DDR) of the L2 bufInnerInterior: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, bufInnerExterior: InclusiveCachePortParameters = InclusiveCachePortParameters.flowAD, bufOuterInterior: InclusiveCachePortParameters = InclusiveCachePortParameters.full, bufOuterExterior: InclusiveCachePortParameters = InclusiveCachePortParameters.none) case object InclusiveCacheKey extends Field[InclusiveCacheParams] class WithInclusiveCache( nWays: Int = 8, capacityKB: Int = 512, outerLatencyCycles: Int = 40, subBankingFactor: Int = 4, hintsSkipProbe: Boolean = false, bankedControl: Boolean = false, ctrlAddr: Option[Int] = Some(InclusiveCacheParameters.L2ControlAddress), writeBytes: Int = 8 ) extends Config((site, here, up) => { case InclusiveCacheKey => InclusiveCacheParams( sets = (capacityKB * 1024)/(site(CacheBlockBytes) * nWays * up(SubsystemBankedCoherenceKey, site).nBanks), ways = nWays, memCycles = outerLatencyCycles, writeBytes = writeBytes, portFactor = subBankingFactor, hintsSkipProbe = hintsSkipProbe, bankedControl = bankedControl, ctrlAddr = ctrlAddr) case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(coherenceManager = { context => implicit val p = context.p val sbus = context.tlBusWrapperLocationMap(SBUS) val cbus = context.tlBusWrapperLocationMap.lift(CBUS).getOrElse(sbus) val InclusiveCacheParams( ways, sets, writeBytes, portFactor, memCycles, physicalFilter, hintsSkipProbe, bankedControl, ctrlAddr, bufInnerInterior, bufInnerExterior, bufOuterInterior, bufOuterExterior) = p(InclusiveCacheKey) val l2Ctrl = ctrlAddr.map { addr => InclusiveCacheControlParameters( address = addr, beatBytes = cbus.beatBytes, bankedControl = bankedControl) } val l2 = LazyModule(new InclusiveCache( CacheParameters( level = 2, ways = ways, sets = sets, blockBytes = sbus.blockBytes, beatBytes = sbus.beatBytes, hintsSkipProbe = hintsSkipProbe), InclusiveCacheMicroParameters( writeBytes = writeBytes, portFactor = portFactor, memCycles = memCycles, innerBuf = bufInnerInterior, outerBuf = bufOuterInterior), l2Ctrl)) def skipMMIO(x: TLClientParameters) = { val dcacheMMIO = x.requestFifo && x.sourceId.start % 2 == 1 && // 1 => dcache issues acquires from another master x.nodePath.last.name == "dcache.node" if (dcacheMMIO) None else Some(x) } val filter = LazyModule(new TLFilter(cfilter = skipMMIO)) val l2_inner_buffer = bufInnerExterior() val l2_outer_buffer = bufOuterExterior() val cork = LazyModule(new TLCacheCork) val lastLevelNode = cork.node l2_inner_buffer.suggestName("InclusiveCache_inner_TLBuffer") l2_outer_buffer.suggestName("InclusiveCache_outer_TLBuffer") l2_inner_buffer.node := filter.node l2.node := l2_inner_buffer.node l2_outer_buffer.node := l2.node / PhysicalFilters need to be on the TL-C side of a CacheCork to prevent Acquire.NtoB -> Grant.toT / physicalFilter match { case None => lastLevelNode := l2_outer_buffer.node case Some(fp) => { val physicalFilter = LazyModule(new PhysicalFilter(fp.copy(controlBeatBytes = cbus.beatBytes))) lastLevelNode := physicalFilter.node := l2_outer_buffer.node physicalFilter.controlNode := cbus.coupleTo("physical_filter") { TLBuffer(1) := TLFragmenter(cbus, Some("LLCPhysicalFilter")) := _ } } } l2.ctrls.foreach { _.ctrlnode := cbus.coupleTo("l2_ctrl") { TLBuffer(1) := TLFragmenter(cbus, Some("LLCCtrl")) := _ } } ElaborationArtefacts.add("l2.json", l2.module.json) (filter.node, lastLevelNode, None) }) }) File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module CoherenceManagerWrapper( // @[ClockDomain.scala:14:9] input auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coherent_jbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_coherent_jbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coherent_jbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coherent_jbar_anon_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coherent_jbar_anon_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coherent_jbar_anon_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coherent_jbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coherent_jbar_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coherent_jbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coherent_jbar_anon_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_l2_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_l2_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_l2_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_l2_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_l2_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_l2_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_l2_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_l2_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_l2_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_l2_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coh_clock_groups_in_member_coh_0_clock, // @[LazyModuleImp.scala:107:25] input auto_coh_clock_groups_in_member_coh_0_reset // @[LazyModuleImp.scala:107:25] ); wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [4:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [3:0] coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:216:19] wire [3:0] coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [6:0] coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire filter_auto_anon_out_d_valid; // @[Filter.scala:60:9] wire filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9] wire filter_auto_anon_out_c_ready; // @[Filter.scala:60:9] wire filter_auto_anon_out_b_valid; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9] wire filter_auto_anon_out_a_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_e_valid; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_in_d_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_bits_denied; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_in_d_bits_sink; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_in_d_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_d_bits_size; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_in_d_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_d_bits_opcode; // @[Filter.scala:60:9] wire filter_auto_anon_in_c_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_c_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9] wire filter_auto_anon_in_b_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_b_ready; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_in_b_bits_address; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_in_b_bits_param; // @[Filter.scala:60:9] wire filter_auto_anon_in_a_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_a_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9] wire [15:0] filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9] wire fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] wire fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:53:9] wire _binder_auto_in_a_ready; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_valid; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_d_bits_opcode; // @[BankBinder.scala:71:28] wire [1:0] _binder_auto_in_d_bits_param; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_d_bits_size; // @[BankBinder.scala:71:28] wire [4:0] _binder_auto_in_d_bits_source; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_bits_sink; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_bits_denied; // @[BankBinder.scala:71:28] wire [63:0] _binder_auto_in_d_bits_data; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_bits_corrupt; // @[BankBinder.scala:71:28] wire _cork_auto_out_a_valid; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_a_bits_opcode; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_a_bits_param; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_a_bits_size; // @[Configs.scala:120:26] wire [4:0] _cork_auto_out_a_bits_source; // @[Configs.scala:120:26] wire [31:0] _cork_auto_out_a_bits_address; // @[Configs.scala:120:26] wire [7:0] _cork_auto_out_a_bits_mask; // @[Configs.scala:120:26] wire [63:0] _cork_auto_out_a_bits_data; // @[Configs.scala:120:26] wire _cork_auto_out_a_bits_corrupt; // @[Configs.scala:120:26] wire _cork_auto_out_d_ready; // @[Configs.scala:120:26] wire _InclusiveCache_inner_TLBuffer_auto_out_a_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_size; // @[Parameters.scala:56:69] wire [6:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_address; // @[Parameters.scala:56:69] wire [15:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask; // @[Parameters.scala:56:69] wire [127:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_b_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_c_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_size; // @[Parameters.scala:56:69] wire [6:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_address; // @[Parameters.scala:56:69] wire [127:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_d_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_e_valid; // @[Parameters.scala:56:69] wire [3:0] _InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink; // @[Parameters.scala:56:69] wire _l2_auto_in_a_ready; // @[Configs.scala:93:24] wire _l2_auto_in_b_valid; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_b_bits_param; // @[Configs.scala:93:24] wire [31:0] _l2_auto_in_b_bits_address; // @[Configs.scala:93:24] wire _l2_auto_in_c_ready; // @[Configs.scala:93:24] wire _l2_auto_in_d_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_d_bits_opcode; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_d_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_d_bits_size; // @[Configs.scala:93:24] wire [6:0] _l2_auto_in_d_bits_source; // @[Configs.scala:93:24] wire [3:0] _l2_auto_in_d_bits_sink; // @[Configs.scala:93:24] wire _l2_auto_in_d_bits_denied; // @[Configs.scala:93:24] wire [127:0] _l2_auto_in_d_bits_data; // @[Configs.scala:93:24] wire _l2_auto_in_d_bits_corrupt; // @[Configs.scala:93:24] wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_a_valid_0 = auto_coherent_jbar_anon_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_a_bits_opcode_0 = auto_coherent_jbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_a_bits_param_0 = auto_coherent_jbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_a_bits_size_0 = auto_coherent_jbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_coherent_jbar_anon_in_a_bits_source_0 = auto_coherent_jbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coherent_jbar_anon_in_a_bits_address_0 = auto_coherent_jbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] auto_coherent_jbar_anon_in_a_bits_mask_0 = auto_coherent_jbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] auto_coherent_jbar_anon_in_a_bits_data_0 = auto_coherent_jbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_a_bits_corrupt_0 = auto_coherent_jbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_b_ready_0 = auto_coherent_jbar_anon_in_b_ready; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_c_valid_0 = auto_coherent_jbar_anon_in_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_c_bits_opcode_0 = auto_coherent_jbar_anon_in_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_c_bits_param_0 = auto_coherent_jbar_anon_in_c_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_c_bits_size_0 = auto_coherent_jbar_anon_in_c_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_coherent_jbar_anon_in_c_bits_source_0 = auto_coherent_jbar_anon_in_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coherent_jbar_anon_in_c_bits_address_0 = auto_coherent_jbar_anon_in_c_bits_address; // @[ClockDomain.scala:14:9] wire [127:0] auto_coherent_jbar_anon_in_c_bits_data_0 = auto_coherent_jbar_anon_in_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_c_bits_corrupt_0 = auto_coherent_jbar_anon_in_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_ready_0 = auto_coherent_jbar_anon_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_e_valid_0 = auto_coherent_jbar_anon_in_e_valid; // @[ClockDomain.scala:14:9] wire [3:0] auto_coherent_jbar_anon_in_e_bits_sink_0 = auto_coherent_jbar_anon_in_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_a_valid_0 = auto_l2_ctrls_ctrl_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode_0 = auto_l2_ctrls_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_param_0 = auto_l2_ctrls_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [1:0] auto_l2_ctrls_ctrl_in_a_bits_size_0 = auto_l2_ctrls_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [11:0] auto_l2_ctrls_ctrl_in_a_bits_source_0 = auto_l2_ctrls_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [25:0] auto_l2_ctrls_ctrl_in_a_bits_address_0 = auto_l2_ctrls_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask_0 = auto_l2_ctrls_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_l2_ctrls_ctrl_in_a_bits_data_0 = auto_l2_ctrls_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_a_bits_corrupt_0 = auto_l2_ctrls_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_ready_0 = auto_l2_ctrls_ctrl_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_coh_clock_groups_in_member_coh_0_clock_0 = auto_coh_clock_groups_in_member_coh_0_clock; // @[ClockDomain.scala:14:9] wire auto_coh_clock_groups_in_member_coh_0_reset_0 = auto_coh_clock_groups_in_member_coh_0_reset; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] filter_auto_anon_in_b_bits_opcode = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_b_bits_size = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_b_bits_opcode = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_b_bits_size = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] filter_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] filter_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_auto_anon_in_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_b_bits_size = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_out_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_out_b_bits_size = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coherent_jbar_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coherent_jbar_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_in_0_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_b_bits_size = 3'h6; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_out_0_b_bits_opcode = 3'h6; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_out_0_b_bits_size = 3'h6; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_size = 3'h6; // @[Xbar.scala:352:24] wire [6:0] auto_coherent_jbar_anon_in_b_bits_source = 7'h40; // @[ClockDomain.scala:14:9] wire [6:0] filter_auto_anon_in_b_bits_source = 7'h40; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_b_bits_source = 7'h40; // @[Filter.scala:60:9] wire [6:0] filter_anonOut_b_bits_source = 7'h40; // @[MixedNode.scala:542:17] wire [6:0] filter_anonIn_b_bits_source = 7'h40; // @[MixedNode.scala:551:17] wire [6:0] coherent_jbar_auto_anon_in_b_bits_source = 7'h40; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_out_b_bits_source = 7'h40; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_b_bits_source = 7'h40; // @[MixedNode.scala:542:17] wire [6:0] coherent_jbar_anonIn_b_bits_source = 7'h40; // @[MixedNode.scala:551:17] wire [6:0] coherent_jbar_in_0_b_bits_source = 7'h40; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar__anonIn_b_bits_source_T = 7'h40; // @[Xbar.scala:156:69] wire [6:0] coherent_jbar_out_0_b_bits_source = 7'h40; // @[Xbar.scala:216:19] wire [6:0] coherent_jbar__requestBOI_uncommonBits_T = 7'h40; // @[Parameters.scala:52:29] wire [6:0] coherent_jbar_requestBOI_uncommonBits = 7'h40; // @[Parameters.scala:52:56] wire [6:0] coherent_jbar_portsBIO_filtered_0_bits_source = 7'h40; // @[Xbar.scala:352:24] wire [15:0] auto_coherent_jbar_anon_in_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9] wire [15:0] filter_auto_anon_in_b_bits_mask = 16'hFFFF; // @[Filter.scala:60:9] wire [15:0] filter_auto_anon_out_b_bits_mask = 16'hFFFF; // @[Filter.scala:60:9] wire [15:0] filter_anonOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] filter_anonIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coherent_jbar_auto_anon_in_b_bits_mask = 16'hFFFF; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_auto_anon_out_b_bits_mask = 16'hFFFF; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_anonOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] coherent_jbar_anonIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coherent_jbar_in_0_b_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] coherent_jbar_out_0_b_bits_mask = 16'hFFFF; // @[Xbar.scala:216:19] wire [15:0] coherent_jbar_portsBIO_filtered_0_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [127:0] auto_coherent_jbar_anon_in_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9] wire [127:0] filter_auto_anon_in_b_bits_data = 128'h0; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_b_bits_data = 128'h0; // @[Filter.scala:60:9] wire [127:0] filter_anonOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] filter_anonIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coherent_jbar_auto_anon_in_b_bits_data = 128'h0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_out_b_bits_data = 128'h0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coherent_jbar_anonIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coherent_jbar_in_0_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_out_0_b_bits_data = 128'h0; // @[Xbar.scala:216:19] wire [127:0] coherent_jbar_portsBIO_filtered_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire auto_coherent_jbar_anon_in_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire coh_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire coh_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire coh_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixedClockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire fixedClockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire fixedClockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire filter_auto_anon_in_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9] wire filter_auto_anon_out_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9] wire filter_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire filter_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_auto_in_b_valid = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_b_valid = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_b_valid = 1'h0; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeIn_b_valid = 1'h0; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_in_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coherent_jbar_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coherent_jbar_in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire coherent_jbar_out_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire coherent_jbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire coherent_jbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire coherent_jbar__requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire coherent_jbar_beatsBO_opdata = 1'h0; // @[Edges.scala:97:28] wire coherent_jbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire auto_coherent_jbar_anon_in_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire filter_auto_anon_in_e_ready = 1'h1; // @[Filter.scala:60:9] wire filter_auto_anon_out_e_ready = 1'h1; // @[Filter.scala:60:9] wire filter_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire filter_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_auto_in_b_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_e_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_b_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_e_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_b_ready = 1'h1; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeIn_b_ready = 1'h1; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_in_e_ready = 1'h1; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_e_ready = 1'h1; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coherent_jbar_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coherent_jbar_in_0_e_ready = 1'h1; // @[Xbar.scala:159:18] wire coherent_jbar_out_0_e_ready = 1'h1; // @[Xbar.scala:216:19] wire coherent_jbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire coherent_jbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire coherent_jbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire coherent_jbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire coherent_jbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire coherent_jbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire coherent_jbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire coherent_jbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire coherent_jbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire coherent_jbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire coherent_jbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire coherent_jbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire coherent_jbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire coherent_jbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire coherent_jbar__requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire coherent_jbar__requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire coherent_jbar__requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire coherent_jbar__requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire coherent_jbar_requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48] wire coherent_jbar__beatsBO_opdata_T = 1'h1; // @[Edges.scala:97:37] wire coherent_jbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar_portsEOI_filtered_0_ready = 1'h1; // @[Xbar.scala:352:24] wire coherent_jbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] coherent_jbar_beatsBO_0 = 2'h0; // @[Edges.scala:221:14] wire [1:0] coherent_jbar_beatsBO_decode = 2'h3; // @[Edges.scala:220:59] wire [5:0] coherent_jbar__beatsBO_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] coherent_jbar__beatsBO_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] coherent_jbar__beatsBO_decode_T = 13'hFC0; // @[package.scala:243:71] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_size = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_size = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_size = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_size = 3'h0; // @[MixedNode.scala:551:17] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_source = 4'h0; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_source = 4'h0; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_source = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_source = 4'h0; // @[MixedNode.scala:551:17] wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_address = 32'h0; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_address = 32'h0; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_address = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_address = 32'h0; // @[MixedNode.scala:551:17] wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_mask = 8'h0; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_mask = 8'h0; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_mask = 8'h0; // @[MixedNode.scala:542:17] wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_data = 64'h0; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_data = 64'h0; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [32:0] coherent_jbar__requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] coherent_jbar__requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] coherent_jbar__requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] coherent_jbar__requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coherent_jbar_auto_anon_in_a_valid = auto_coherent_jbar_anon_in_a_valid_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_a_bits_opcode = auto_coherent_jbar_anon_in_a_bits_opcode_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_a_bits_param = auto_coherent_jbar_anon_in_a_bits_param_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_a_bits_size = auto_coherent_jbar_anon_in_a_bits_size_0; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_in_a_bits_source = auto_coherent_jbar_anon_in_a_bits_source_0; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_auto_anon_in_a_bits_address = auto_coherent_jbar_anon_in_a_bits_address_0; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_auto_anon_in_a_bits_mask = auto_coherent_jbar_anon_in_a_bits_mask_0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_in_a_bits_data = auto_coherent_jbar_anon_in_a_bits_data_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_a_bits_corrupt = auto_coherent_jbar_anon_in_a_bits_corrupt_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_b_ready = auto_coherent_jbar_anon_in_b_ready_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_c_valid = auto_coherent_jbar_anon_in_c_valid_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_c_bits_opcode = auto_coherent_jbar_anon_in_c_bits_opcode_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_c_bits_param = auto_coherent_jbar_anon_in_c_bits_param_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_c_bits_size = auto_coherent_jbar_anon_in_c_bits_size_0; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_in_c_bits_source = auto_coherent_jbar_anon_in_c_bits_source_0; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_auto_anon_in_c_bits_address = auto_coherent_jbar_anon_in_c_bits_address_0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_in_c_bits_data = auto_coherent_jbar_anon_in_c_bits_data_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_c_bits_corrupt = auto_coherent_jbar_anon_in_c_bits_corrupt_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_ready = auto_coherent_jbar_anon_in_d_ready_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_e_valid = auto_coherent_jbar_anon_in_e_valid_0; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_auto_anon_in_e_bits_sink = auto_coherent_jbar_anon_in_e_bits_sink_0; // @[Jbar.scala:44:9] wire coh_clock_groups_auto_in_member_coh_0_clock = auto_coh_clock_groups_in_member_coh_0_clock_0; // @[ClockGroup.scala:53:9] wire coh_clock_groups_auto_in_member_coh_0_reset = auto_coh_clock_groups_in_member_coh_0_reset_0; // @[ClockGroup.scala:53:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire coh_clock_groups_nodeIn_member_coh_0_clock = coh_clock_groups_auto_in_member_coh_0_clock; // @[ClockGroup.scala:53:9] wire coh_clock_groups_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17] wire coh_clock_groups_nodeIn_member_coh_0_reset = coh_clock_groups_auto_in_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire coh_clock_groups_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_coh_0_clock = coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_coh_0_reset = coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign coh_clock_groups_auto_out_member_coh_0_clock = coh_clock_groups_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9] assign coh_clock_groups_auto_out_member_coh_0_reset = coh_clock_groups_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9] assign coh_clock_groups_nodeOut_member_coh_0_clock = coh_clock_groups_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17] assign coh_clock_groups_nodeOut_member_coh_0_reset = coh_clock_groups_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_coh_0_clock = clockGroup_auto_in_member_coh_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_coh_0_reset = clockGroup_auto_in_member_coh_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire fixedClockNode_auto_anon_in_clock = clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9, :104:9] wire fixedClockNode_auto_anon_in_reset = clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9, :104:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixedClockNode_anonIn_clock = fixedClockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire fixedClockNode_anonOut_clock; // @[MixedNode.scala:542:17] wire fixedClockNode_anonIn_reset = fixedClockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] wire fixedClockNode_anonOut_reset; // @[MixedNode.scala:542:17] assign clockSinkNodeIn_clock = fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] assign clockSinkNodeIn_reset = fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] assign fixedClockNode_auto_anon_out_clock = fixedClockNode_anonOut_clock; // @[ClockGroup.scala:104:9] assign fixedClockNode_auto_anon_out_reset = fixedClockNode_anonOut_reset; // @[ClockGroup.scala:104:9] assign fixedClockNode_anonOut_clock = fixedClockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17] assign fixedClockNode_anonOut_reset = fixedClockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17] wire filter_anonIn_a_ready; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_a_ready = filter_auto_anon_in_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9] wire filter_anonIn_a_valid = filter_auto_anon_in_a_valid; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_a_bits_opcode = filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_a_bits_param = filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_a_bits_size = filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9] wire [6:0] coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9] wire [6:0] filter_anonIn_a_bits_source = filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9] wire [31:0] coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9] wire [31:0] filter_anonIn_a_bits_address = filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9] wire [15:0] coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9] wire [15:0] filter_anonIn_a_bits_mask = filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9] wire [127:0] coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9] wire [127:0] filter_anonIn_a_bits_data = filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9] wire filter_anonIn_a_bits_corrupt = filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9] wire filter_anonIn_b_ready = filter_auto_anon_in_b_ready; // @[Filter.scala:60:9] wire filter_anonIn_b_valid; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_b_valid = filter_auto_anon_in_b_valid; // @[Jbar.scala:44:9] wire [1:0] filter_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coherent_jbar_auto_anon_out_b_bits_param = filter_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] filter_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [31:0] coherent_jbar_auto_anon_out_b_bits_address = filter_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9] wire filter_anonIn_c_ready; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_c_ready = filter_auto_anon_in_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9] wire filter_anonIn_c_valid = filter_auto_anon_in_c_valid; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_c_bits_opcode = filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_c_bits_param = filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_c_bits_size = filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9] wire [6:0] coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9] wire [6:0] filter_anonIn_c_bits_source = filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9] wire [31:0] coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9] wire [31:0] filter_anonIn_c_bits_address = filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9] wire [127:0] coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9] wire [127:0] filter_anonIn_c_bits_data = filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9] wire filter_anonIn_c_bits_corrupt = filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9] wire filter_anonIn_d_ready = filter_auto_anon_in_d_ready; // @[Filter.scala:60:9] wire filter_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] filter_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_d_valid = filter_auto_anon_in_d_valid; // @[Jbar.scala:44:9] wire [1:0] filter_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_auto_anon_out_d_bits_opcode = filter_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coherent_jbar_auto_anon_out_d_bits_param = filter_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9] wire [6:0] filter_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_auto_anon_out_d_bits_size = filter_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9] wire [3:0] filter_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [6:0] coherent_jbar_auto_anon_out_d_bits_source = filter_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9] wire filter_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [3:0] coherent_jbar_auto_anon_out_d_bits_sink = filter_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9] wire [127:0] filter_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_d_bits_denied = filter_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9] wire filter_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [127:0] coherent_jbar_auto_anon_out_d_bits_data = filter_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_d_bits_corrupt = filter_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9] wire filter_anonIn_e_valid = filter_auto_anon_in_e_valid; // @[Filter.scala:60:9] wire [3:0] coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9] wire [3:0] filter_anonIn_e_bits_sink = filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9] wire filter_anonOut_a_ready = filter_auto_anon_out_a_ready; // @[Filter.scala:60:9] wire filter_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] filter_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] filter_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] filter_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] filter_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire filter_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire filter_anonOut_b_ready; // @[MixedNode.scala:542:17] wire filter_anonOut_b_valid = filter_auto_anon_out_b_valid; // @[Filter.scala:60:9] wire [1:0] filter_anonOut_b_bits_param = filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9] wire [31:0] filter_anonOut_b_bits_address = filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9] wire filter_anonOut_c_ready = filter_auto_anon_out_c_ready; // @[Filter.scala:60:9] wire filter_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [6:0] filter_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] filter_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] filter_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire filter_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire filter_anonOut_d_ready; // @[MixedNode.scala:542:17] wire filter_anonOut_d_valid = filter_auto_anon_out_d_valid; // @[Filter.scala:60:9] wire [2:0] filter_anonOut_d_bits_opcode = filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9] wire [1:0] filter_anonOut_d_bits_param = filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_anonOut_d_bits_size = filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9] wire [6:0] filter_anonOut_d_bits_source = filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9] wire [3:0] filter_anonOut_d_bits_sink = filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9] wire filter_anonOut_d_bits_denied = filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9] wire [127:0] filter_anonOut_d_bits_data = filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9] wire filter_anonOut_d_bits_corrupt = filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9] wire filter_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] filter_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] filter_auto_anon_out_a_bits_opcode; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_a_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_a_bits_size; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_a_bits_source; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_out_a_bits_address; // @[Filter.scala:60:9] wire [15:0] filter_auto_anon_out_a_bits_mask; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_a_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_out_a_bits_corrupt; // @[Filter.scala:60:9] wire filter_auto_anon_out_a_valid; // @[Filter.scala:60:9] wire filter_auto_anon_out_b_ready; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_c_bits_opcode; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_c_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_c_bits_size; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_c_bits_source; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_out_c_bits_address; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_c_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_out_c_bits_corrupt; // @[Filter.scala:60:9] wire filter_auto_anon_out_c_valid; // @[Filter.scala:60:9] wire filter_auto_anon_out_d_ready; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_out_e_bits_sink; // @[Filter.scala:60:9] wire filter_auto_anon_out_e_valid; // @[Filter.scala:60:9] assign filter_anonIn_a_ready = filter_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_out_a_valid = filter_anonOut_a_valid; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_opcode = filter_anonOut_a_bits_opcode; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_param = filter_anonOut_a_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_size = filter_anonOut_a_bits_size; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_source = filter_anonOut_a_bits_source; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_address = filter_anonOut_a_bits_address; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_mask = filter_anonOut_a_bits_mask; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_data = filter_anonOut_a_bits_data; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_corrupt = filter_anonOut_a_bits_corrupt; // @[Filter.scala:60:9] assign filter_auto_anon_out_b_ready = filter_anonOut_b_ready; // @[Filter.scala:60:9] assign filter_anonIn_b_valid = filter_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_b_bits_param = filter_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_b_bits_address = filter_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_c_ready = filter_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_out_c_valid = filter_anonOut_c_valid; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_opcode = filter_anonOut_c_bits_opcode; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_param = filter_anonOut_c_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_size = filter_anonOut_c_bits_size; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_source = filter_anonOut_c_bits_source; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_address = filter_anonOut_c_bits_address; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_data = filter_anonOut_c_bits_data; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_corrupt = filter_anonOut_c_bits_corrupt; // @[Filter.scala:60:9] assign filter_auto_anon_out_d_ready = filter_anonOut_d_ready; // @[Filter.scala:60:9] assign filter_anonIn_d_valid = filter_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_opcode = filter_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_param = filter_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_size = filter_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_source = filter_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_sink = filter_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_denied = filter_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_data = filter_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_corrupt = filter_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_out_e_valid = filter_anonOut_e_valid; // @[Filter.scala:60:9] assign filter_auto_anon_out_e_bits_sink = filter_anonOut_e_bits_sink; // @[Filter.scala:60:9] assign filter_auto_anon_in_a_ready = filter_anonIn_a_ready; // @[Filter.scala:60:9] assign filter_anonOut_a_valid = filter_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_opcode = filter_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_param = filter_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_size = filter_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_source = filter_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_address = filter_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_mask = filter_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_data = filter_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_corrupt = filter_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_b_ready = filter_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_in_b_valid = filter_anonIn_b_valid; // @[Filter.scala:60:9] assign filter_auto_anon_in_b_bits_param = filter_anonIn_b_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_in_b_bits_address = filter_anonIn_b_bits_address; // @[Filter.scala:60:9] assign filter_auto_anon_in_c_ready = filter_anonIn_c_ready; // @[Filter.scala:60:9] assign filter_anonOut_c_valid = filter_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_opcode = filter_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_param = filter_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_size = filter_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_source = filter_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_address = filter_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_data = filter_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_corrupt = filter_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_d_ready = filter_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_in_d_valid = filter_anonIn_d_valid; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_opcode = filter_anonIn_d_bits_opcode; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_param = filter_anonIn_d_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_size = filter_anonIn_d_bits_size; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_source = filter_anonIn_d_bits_source; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_sink = filter_anonIn_d_bits_sink; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_denied = filter_anonIn_d_bits_denied; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_data = filter_anonIn_d_bits_data; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_corrupt = filter_anonIn_d_bits_corrupt; // @[Filter.scala:60:9] assign filter_anonOut_e_valid = filter_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_e_bits_sink = filter_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_a_valid = InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param = InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size = InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source = InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address = InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask = InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data = InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_c_valid = InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param = InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size = InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source = InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address = InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data = InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_d_ready = InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_e_valid = InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink = InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_a_ready = InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_c_ready = InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_d_valid = InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode = InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param = InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size = InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source = InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink = InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied = InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data = InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_e_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeIn_a_ready = InclusiveCache_outer_TLBuffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_out_a_valid = InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeIn_c_ready = InclusiveCache_outer_TLBuffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_out_c_valid = InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_d_ready = InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeIn_d_valid = InclusiveCache_outer_TLBuffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_out_e_valid = InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_a_ready = InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeOut_a_valid = InclusiveCache_outer_TLBuffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_in_c_ready = InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeOut_c_valid = InclusiveCache_outer_TLBuffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_d_ready = InclusiveCache_outer_TLBuffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_in_d_valid = InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeOut_e_valid = InclusiveCache_outer_TLBuffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coherent_jbar_anonIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_a_ready_0 = coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_a_valid = coherent_jbar_auto_anon_in_a_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_a_bits_opcode = coherent_jbar_auto_anon_in_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_a_bits_param = coherent_jbar_auto_anon_in_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_a_bits_size = coherent_jbar_auto_anon_in_a_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonIn_a_bits_source = coherent_jbar_auto_anon_in_a_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonIn_a_bits_address = coherent_jbar_auto_anon_in_a_bits_address; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_anonIn_a_bits_mask = coherent_jbar_auto_anon_in_a_bits_mask; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonIn_a_bits_data = coherent_jbar_auto_anon_in_a_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_a_bits_corrupt = coherent_jbar_auto_anon_in_a_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_b_ready = coherent_jbar_auto_anon_in_b_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_b_valid_0 = coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_b_bits_param_0 = coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_b_bits_address_0 = coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_c_ready_0 = coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_c_valid = coherent_jbar_auto_anon_in_c_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_c_bits_opcode = coherent_jbar_auto_anon_in_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_c_bits_param = coherent_jbar_auto_anon_in_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_c_bits_size = coherent_jbar_auto_anon_in_c_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonIn_c_bits_source = coherent_jbar_auto_anon_in_c_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonIn_c_bits_address = coherent_jbar_auto_anon_in_c_bits_address; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonIn_c_bits_data = coherent_jbar_auto_anon_in_c_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_c_bits_corrupt = coherent_jbar_auto_anon_in_c_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_ready = coherent_jbar_auto_anon_in_d_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_valid_0 = coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_opcode_0 = coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_param_0 = coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_size_0 = coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_source_0 = coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_sink_0 = coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_denied_0 = coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_data_0 = coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_corrupt_0 = coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_e_valid = coherent_jbar_auto_anon_in_e_valid; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonIn_e_bits_sink = coherent_jbar_auto_anon_in_e_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_a_ready = coherent_jbar_auto_anon_out_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_a_valid; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_valid = coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_opcode = coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_param = coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_size = coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_source = coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_address = coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_mask = coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_data = coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_corrupt = coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_b_ready; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_b_ready = coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_b_valid = coherent_jbar_auto_anon_out_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonOut_b_bits_param = coherent_jbar_auto_anon_out_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonOut_b_bits_address = coherent_jbar_auto_anon_out_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_c_ready = coherent_jbar_auto_anon_out_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_c_valid; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_valid = coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_opcode = coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_c_bits_param; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_param = coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_c_bits_size; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_size = coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_c_bits_source; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_source = coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonOut_c_bits_address; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_address = coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_c_bits_data; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_data = coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_corrupt = coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_ready; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_d_ready = coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_valid = coherent_jbar_auto_anon_out_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_d_bits_opcode = coherent_jbar_auto_anon_out_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonOut_d_bits_param = coherent_jbar_auto_anon_out_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_d_bits_size = coherent_jbar_auto_anon_out_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_d_bits_source = coherent_jbar_auto_anon_out_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonOut_d_bits_sink = coherent_jbar_auto_anon_out_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_bits_denied = coherent_jbar_auto_anon_out_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_d_bits_data = coherent_jbar_auto_anon_out_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_bits_corrupt = coherent_jbar_auto_anon_out_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_e_valid; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_e_valid = coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_e_bits_sink = coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_a_ready = coherent_jbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_valid = coherent_jbar_anonOut_a_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_opcode = coherent_jbar_anonOut_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_param = coherent_jbar_anonOut_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_size = coherent_jbar_anonOut_a_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_source = coherent_jbar_anonOut_a_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_address = coherent_jbar_anonOut_a_bits_address; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_mask = coherent_jbar_anonOut_a_bits_mask; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_data = coherent_jbar_anonOut_a_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_corrupt = coherent_jbar_anonOut_a_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_b_ready = coherent_jbar_anonOut_b_ready; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_b_valid = coherent_jbar_anonOut_b_valid; // @[Xbar.scala:216:19] wire [1:0] coherent_jbar_out_0_b_bits_param = coherent_jbar_anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [31:0] coherent_jbar_out_0_b_bits_address = coherent_jbar_anonOut_b_bits_address; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_c_ready = coherent_jbar_anonOut_c_ready; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_valid = coherent_jbar_anonOut_c_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_opcode = coherent_jbar_anonOut_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_param = coherent_jbar_anonOut_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_size = coherent_jbar_anonOut_c_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_source = coherent_jbar_anonOut_c_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_address = coherent_jbar_anonOut_c_bits_address; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_data = coherent_jbar_anonOut_c_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_corrupt = coherent_jbar_anonOut_c_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_d_ready = coherent_jbar_anonOut_d_ready; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_d_valid = coherent_jbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_out_0_d_bits_opcode = coherent_jbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] coherent_jbar_out_0_d_bits_param = coherent_jbar_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_out_0_d_bits_size = coherent_jbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [6:0] coherent_jbar_out_0_d_bits_source = coherent_jbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [3:0] coherent_jbar__out_0_d_bits_sink_T = coherent_jbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire coherent_jbar_out_0_d_bits_denied = coherent_jbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [127:0] coherent_jbar_out_0_d_bits_data = coherent_jbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_d_bits_corrupt = coherent_jbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_e_valid = coherent_jbar_anonOut_e_valid; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign coherent_jbar_auto_anon_out_e_bits_sink = coherent_jbar_anonOut_e_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_a_ready = coherent_jbar_anonIn_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_a_valid = coherent_jbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_a_bits_opcode = coherent_jbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_a_bits_param = coherent_jbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_a_bits_size = coherent_jbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar__in_0_a_bits_source_T = coherent_jbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] coherent_jbar_in_0_a_bits_address = coherent_jbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] coherent_jbar_in_0_a_bits_mask = coherent_jbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_in_0_a_bits_data = coherent_jbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_a_bits_corrupt = coherent_jbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_b_ready = coherent_jbar_anonIn_b_ready; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_b_valid = coherent_jbar_anonIn_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_b_bits_param = coherent_jbar_anonIn_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_b_bits_address = coherent_jbar_anonIn_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_c_ready = coherent_jbar_anonIn_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_c_valid = coherent_jbar_anonIn_c_valid; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_c_bits_opcode = coherent_jbar_anonIn_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_c_bits_param = coherent_jbar_anonIn_c_bits_param; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_c_bits_size = coherent_jbar_anonIn_c_bits_size; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar__in_0_c_bits_source_T = coherent_jbar_anonIn_c_bits_source; // @[Xbar.scala:187:55] wire [31:0] coherent_jbar_in_0_c_bits_address = coherent_jbar_anonIn_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_in_0_c_bits_data = coherent_jbar_anonIn_c_bits_data; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_c_bits_corrupt = coherent_jbar_anonIn_c_bits_corrupt; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_d_ready = coherent_jbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_valid = coherent_jbar_anonIn_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_opcode = coherent_jbar_anonIn_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_param = coherent_jbar_anonIn_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_size = coherent_jbar_anonIn_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign coherent_jbar_auto_anon_in_d_bits_source = coherent_jbar_anonIn_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_sink = coherent_jbar_anonIn_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_denied = coherent_jbar_anonIn_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_data = coherent_jbar_anonIn_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_corrupt = coherent_jbar_anonIn_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_e_valid = coherent_jbar_anonIn_e_valid; // @[Xbar.scala:159:18] wire [3:0] coherent_jbar_in_0_e_bits_sink = coherent_jbar_anonIn_e_bits_sink; // @[Xbar.scala:159:18] wire coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_a_ready = coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18] wire coherent_jbar__portsAOI_filtered_0_valid_T_1 = coherent_jbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_opcode = coherent_jbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_param = coherent_jbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_size = coherent_jbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] coherent_jbar_portsAOI_filtered_0_bits_source = coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] coherent_jbar__requestAIO_T = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] coherent_jbar_portsAOI_filtered_0_bits_address = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] coherent_jbar_portsAOI_filtered_0_bits_mask = coherent_jbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] coherent_jbar_portsAOI_filtered_0_bits_data = coherent_jbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsAOI_filtered_0_bits_corrupt = coherent_jbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsBIO_filtered_0_ready = coherent_jbar_in_0_b_ready; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_b_valid = coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18] wire [1:0] coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_b_bits_param = coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18] wire [31:0] coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_b_bits_address = coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18] wire coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_c_ready = coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18] wire coherent_jbar__portsCOI_filtered_0_valid_T_1 = coherent_jbar_in_0_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_opcode = coherent_jbar_in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_param = coherent_jbar_in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_size = coherent_jbar_in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] coherent_jbar_portsCOI_filtered_0_bits_source = coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] coherent_jbar__requestCIO_T = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] coherent_jbar_portsCOI_filtered_0_bits_address = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] coherent_jbar_portsCOI_filtered_0_bits_data = coherent_jbar_in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsCOI_filtered_0_bits_corrupt = coherent_jbar_in_0_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsDIO_filtered_0_ready = coherent_jbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_valid = coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_opcode = coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_param = coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_size = coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign coherent_jbar__anonIn_d_bits_source_T = coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire [3:0] coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_sink = coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] wire coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_denied = coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_data = coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_corrupt = coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire coherent_jbar__portsEOI_filtered_0_valid_T_1 = coherent_jbar_in_0_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] coherent_jbar__requestEIO_uncommonBits_T = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18] wire [3:0] coherent_jbar_portsEOI_filtered_0_bits_sink = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_a_bits_source = coherent_jbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign coherent_jbar_in_0_c_bits_source = coherent_jbar__in_0_c_bits_source_T; // @[Xbar.scala:159:18, :187:55] assign coherent_jbar_anonIn_d_bits_source = coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign coherent_jbar_portsAOI_filtered_0_ready = coherent_jbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonOut_a_valid = coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_opcode = coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_param = coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_size = coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_source = coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_address = coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_mask = coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_data = coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_corrupt = coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_b_ready = coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19] wire coherent_jbar__portsBIO_filtered_0_valid_T_1 = coherent_jbar_out_0_b_valid; // @[Xbar.scala:216:19, :355:40] assign coherent_jbar_portsBIO_filtered_0_bits_param = coherent_jbar_out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsBIO_filtered_0_bits_address = coherent_jbar_out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsCOI_filtered_0_ready = coherent_jbar_out_0_c_ready; // @[Xbar.scala:216:19, :352:24] wire coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonOut_c_valid = coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_opcode = coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_param = coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_size = coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_source = coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_address = coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_data = coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_corrupt = coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_d_ready = coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19] wire coherent_jbar__portsDIO_filtered_0_valid_T_1 = coherent_jbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign coherent_jbar_portsDIO_filtered_0_bits_opcode = coherent_jbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_param = coherent_jbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_size = coherent_jbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] coherent_jbar__requestDOI_uncommonBits_T = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_portsDIO_filtered_0_bits_source = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_sink = coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_denied = coherent_jbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_data = coherent_jbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_corrupt = coherent_jbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonOut_e_valid = coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19] assign coherent_jbar__anonOut_e_bits_sink_T = coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19] assign coherent_jbar_out_0_d_bits_sink = coherent_jbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign coherent_jbar_anonOut_e_bits_sink = coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] coherent_jbar__requestAIO_T_1 = {1'h0, coherent_jbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] coherent_jbar__requestCIO_T_1 = {1'h0, coherent_jbar__requestCIO_T}; // @[Parameters.scala:137:{31,41}] wire [6:0] coherent_jbar_requestDOI_uncommonBits = coherent_jbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] coherent_jbar_requestEIO_uncommonBits = coherent_jbar__requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] coherent_jbar__beatsAI_decode_T = 13'h3F << coherent_jbar_in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] coherent_jbar__beatsAI_decode_T_1 = coherent_jbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] coherent_jbar__beatsAI_decode_T_2 = ~coherent_jbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] coherent_jbar_beatsAI_decode = coherent_jbar__beatsAI_decode_T_2[5:4]; // @[package.scala:243:46] wire coherent_jbar__beatsAI_opdata_T = coherent_jbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire coherent_jbar_beatsAI_opdata = ~coherent_jbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [1:0] coherent_jbar_beatsAI_0 = coherent_jbar_beatsAI_opdata ? coherent_jbar_beatsAI_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] coherent_jbar__beatsCI_decode_T = 13'h3F << coherent_jbar_in_0_c_bits_size; // @[package.scala:243:71] wire [5:0] coherent_jbar__beatsCI_decode_T_1 = coherent_jbar__beatsCI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] coherent_jbar__beatsCI_decode_T_2 = ~coherent_jbar__beatsCI_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] coherent_jbar_beatsCI_decode = coherent_jbar__beatsCI_decode_T_2[5:4]; // @[package.scala:243:46] wire coherent_jbar_beatsCI_opdata = coherent_jbar_in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [1:0] coherent_jbar_beatsCI_0 = coherent_jbar_beatsCI_opdata ? coherent_jbar_beatsCI_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [12:0] coherent_jbar__beatsDO_decode_T = 13'h3F << coherent_jbar_out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] coherent_jbar__beatsDO_decode_T_1 = coherent_jbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] coherent_jbar__beatsDO_decode_T_2 = ~coherent_jbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] coherent_jbar_beatsDO_decode = coherent_jbar__beatsDO_decode_T_2[5:4]; // @[package.scala:243:46] wire coherent_jbar_beatsDO_opdata = coherent_jbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [1:0] coherent_jbar_beatsDO_0 = coherent_jbar_beatsDO_opdata ? coherent_jbar_beatsDO_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign coherent_jbar_in_0_a_ready = coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_out_0_a_valid = coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_opcode = coherent_jbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_param = coherent_jbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_size = coherent_jbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_source = coherent_jbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_address = coherent_jbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_mask = coherent_jbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_data = coherent_jbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_corrupt = coherent_jbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsAOI_filtered_0_valid = coherent_jbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_out_0_b_ready = coherent_jbar_portsBIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_in_0_b_valid = coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_b_bits_param = coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_b_bits_address = coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_portsBIO_filtered_0_valid = coherent_jbar__portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_in_0_c_ready = coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_out_0_c_valid = coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_opcode = coherent_jbar_portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_param = coherent_jbar_portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_size = coherent_jbar_portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_source = coherent_jbar_portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_address = coherent_jbar_portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_data = coherent_jbar_portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_corrupt = coherent_jbar_portsCOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsCOI_filtered_0_valid = coherent_jbar__portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_out_0_d_ready = coherent_jbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_in_0_d_valid = coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_opcode = coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_param = coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_size = coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_source = coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_sink = coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_denied = coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_data = coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_corrupt = coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_portsDIO_filtered_0_valid = coherent_jbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_out_0_e_valid = coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_e_bits_sink = coherent_jbar_portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsEOI_filtered_0_valid = coherent_jbar__portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingOut_a_ready = coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_bus_xingOut_d_valid = coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_param = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_size = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17] wire [4:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_source = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_data = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [4:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [4:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_anonIn_a_ready = coupler_to_bus_named_mbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_anonIn_d_valid = coupler_to_bus_named_mbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_param = coupler_to_bus_named_mbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_size = coupler_to_bus_named_mbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_source = coupler_to_bus_named_mbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_data = coupler_to_bus_named_mbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_anonOut_a_valid = coupler_to_bus_named_mbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_param = coupler_to_bus_named_mbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_size = coupler_to_bus_named_mbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_source = coupler_to_bus_named_mbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_address = coupler_to_bus_named_mbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_data = coupler_to_bus_named_mbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_d_ready = coupler_to_bus_named_mbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_bus_xingIn_a_ready = coupler_to_bus_named_mbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_valid = coupler_to_bus_named_mbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_param = coupler_to_bus_named_mbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_size = coupler_to_bus_named_mbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_source = coupler_to_bus_named_mbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_data = coupler_to_bus_named_mbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_bus_xingOut_a_valid = coupler_to_bus_named_mbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_param = coupler_to_bus_named_mbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_size = coupler_to_bus_named_mbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_source = coupler_to_bus_named_mbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_address = coupler_to_bus_named_mbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_data = coupler_to_bus_named_mbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_d_ready = coupler_to_bus_named_mbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] InclusiveCache l2 ( // @[Configs.scala:93:24] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_ctrls_ctrl_in_a_ready (auto_l2_ctrls_ctrl_in_a_ready_0), .auto_ctrls_ctrl_in_a_valid (auto_l2_ctrls_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_opcode (auto_l2_ctrls_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_param (auto_l2_ctrls_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_size (auto_l2_ctrls_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_source (auto_l2_ctrls_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_address (auto_l2_ctrls_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_mask (auto_l2_ctrls_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_data (auto_l2_ctrls_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_corrupt (auto_l2_ctrls_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_d_ready (auto_l2_ctrls_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_d_valid (auto_l2_ctrls_ctrl_in_d_valid_0), .auto_ctrls_ctrl_in_d_bits_opcode (auto_l2_ctrls_ctrl_in_d_bits_opcode_0), .auto_ctrls_ctrl_in_d_bits_size (auto_l2_ctrls_ctrl_in_d_bits_size_0), .auto_ctrls_ctrl_in_d_bits_source (auto_l2_ctrls_ctrl_in_d_bits_source_0), .auto_ctrls_ctrl_in_d_bits_data (auto_l2_ctrls_ctrl_in_d_bits_data_0), .auto_in_a_ready (_l2_auto_in_a_ready), .auto_in_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid), // @[Parameters.scala:56:69] .auto_in_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode), // @[Parameters.scala:56:69] .auto_in_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param), // @[Parameters.scala:56:69] .auto_in_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size), // @[Parameters.scala:56:69] .auto_in_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source), // @[Parameters.scala:56:69] .auto_in_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address), // @[Parameters.scala:56:69] .auto_in_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask), // @[Parameters.scala:56:69] .auto_in_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data), // @[Parameters.scala:56:69] .auto_in_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready), // @[Parameters.scala:56:69] .auto_in_b_valid (_l2_auto_in_b_valid), .auto_in_b_bits_param (_l2_auto_in_b_bits_param), .auto_in_b_bits_address (_l2_auto_in_b_bits_address), .auto_in_c_ready (_l2_auto_in_c_ready), .auto_in_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid), // @[Parameters.scala:56:69] .auto_in_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode), // @[Parameters.scala:56:69] .auto_in_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param), // @[Parameters.scala:56:69] .auto_in_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size), // @[Parameters.scala:56:69] .auto_in_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source), // @[Parameters.scala:56:69] .auto_in_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address), // @[Parameters.scala:56:69] .auto_in_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data), // @[Parameters.scala:56:69] .auto_in_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready), // @[Parameters.scala:56:69] .auto_in_d_valid (_l2_auto_in_d_valid), .auto_in_d_bits_opcode (_l2_auto_in_d_bits_opcode), .auto_in_d_bits_param (_l2_auto_in_d_bits_param), .auto_in_d_bits_size (_l2_auto_in_d_bits_size), .auto_in_d_bits_source (_l2_auto_in_d_bits_source), .auto_in_d_bits_sink (_l2_auto_in_d_bits_sink), .auto_in_d_bits_denied (_l2_auto_in_d_bits_denied), .auto_in_d_bits_data (_l2_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_l2_auto_in_d_bits_corrupt), .auto_in_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid), // @[Parameters.scala:56:69] .auto_in_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink), // @[Parameters.scala:56:69] .auto_out_a_ready (InclusiveCache_outer_TLBuffer_auto_in_a_ready), // @[Buffer.scala:40:9] .auto_out_a_valid (InclusiveCache_outer_TLBuffer_auto_in_a_valid), .auto_out_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode), .auto_out_a_bits_param (InclusiveCache_outer_TLBuffer_auto_in_a_bits_param), .auto_out_a_bits_size (InclusiveCache_outer_TLBuffer_auto_in_a_bits_size), .auto_out_a_bits_source (InclusiveCache_outer_TLBuffer_auto_in_a_bits_source), .auto_out_a_bits_address (InclusiveCache_outer_TLBuffer_auto_in_a_bits_address), .auto_out_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask), .auto_out_a_bits_data (InclusiveCache_outer_TLBuffer_auto_in_a_bits_data), .auto_out_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt), .auto_out_c_ready (InclusiveCache_outer_TLBuffer_auto_in_c_ready), // @[Buffer.scala:40:9] .auto_out_c_valid (InclusiveCache_outer_TLBuffer_auto_in_c_valid), .auto_out_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode), .auto_out_c_bits_param (InclusiveCache_outer_TLBuffer_auto_in_c_bits_param), .auto_out_c_bits_size (InclusiveCache_outer_TLBuffer_auto_in_c_bits_size), .auto_out_c_bits_source (InclusiveCache_outer_TLBuffer_auto_in_c_bits_source), .auto_out_c_bits_address (InclusiveCache_outer_TLBuffer_auto_in_c_bits_address), .auto_out_c_bits_data (InclusiveCache_outer_TLBuffer_auto_in_c_bits_data), .auto_out_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt), .auto_out_d_ready (InclusiveCache_outer_TLBuffer_auto_in_d_ready), .auto_out_d_valid (InclusiveCache_outer_TLBuffer_auto_in_d_valid), // @[Buffer.scala:40:9] .auto_out_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode), // @[Buffer.scala:40:9] .auto_out_d_bits_param (InclusiveCache_outer_TLBuffer_auto_in_d_bits_param), // @[Buffer.scala:40:9] .auto_out_d_bits_size (InclusiveCache_outer_TLBuffer_auto_in_d_bits_size), // @[Buffer.scala:40:9] .auto_out_d_bits_source (InclusiveCache_outer_TLBuffer_auto_in_d_bits_source), // @[Buffer.scala:40:9] .auto_out_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink), // @[Buffer.scala:40:9] .auto_out_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied), // @[Buffer.scala:40:9] .auto_out_d_bits_data (InclusiveCache_outer_TLBuffer_auto_in_d_bits_data), // @[Buffer.scala:40:9] .auto_out_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt), // @[Buffer.scala:40:9] .auto_out_e_valid (InclusiveCache_outer_TLBuffer_auto_in_e_valid), .auto_out_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink) ); // @[Configs.scala:93:24] TLBuffer_a32d128s7k4z3c InclusiveCache_inner_TLBuffer ( // @[Parameters.scala:56:69] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (filter_auto_anon_out_a_ready), .auto_in_a_valid (filter_auto_anon_out_a_valid), // @[Filter.scala:60:9] .auto_in_a_bits_opcode (filter_auto_anon_out_a_bits_opcode), // @[Filter.scala:60:9] .auto_in_a_bits_param (filter_auto_anon_out_a_bits_param), // @[Filter.scala:60:9] .auto_in_a_bits_size (filter_auto_anon_out_a_bits_size), // @[Filter.scala:60:9] .auto_in_a_bits_source (filter_auto_anon_out_a_bits_source), // @[Filter.scala:60:9] .auto_in_a_bits_address (filter_auto_anon_out_a_bits_address), // @[Filter.scala:60:9] .auto_in_a_bits_mask (filter_auto_anon_out_a_bits_mask), // @[Filter.scala:60:9] .auto_in_a_bits_data (filter_auto_anon_out_a_bits_data), // @[Filter.scala:60:9] .auto_in_a_bits_corrupt (filter_auto_anon_out_a_bits_corrupt), // @[Filter.scala:60:9] .auto_in_b_ready (filter_auto_anon_out_b_ready), // @[Filter.scala:60:9] .auto_in_b_valid (filter_auto_anon_out_b_valid), .auto_in_b_bits_param (filter_auto_anon_out_b_bits_param), .auto_in_b_bits_address (filter_auto_anon_out_b_bits_address), .auto_in_c_ready (filter_auto_anon_out_c_ready), .auto_in_c_valid (filter_auto_anon_out_c_valid), // @[Filter.scala:60:9] .auto_in_c_bits_opcode (filter_auto_anon_out_c_bits_opcode), // @[Filter.scala:60:9] .auto_in_c_bits_param (filter_auto_anon_out_c_bits_param), // @[Filter.scala:60:9] .auto_in_c_bits_size (filter_auto_anon_out_c_bits_size), // @[Filter.scala:60:9] .auto_in_c_bits_source (filter_auto_anon_out_c_bits_source), // @[Filter.scala:60:9] .auto_in_c_bits_address (filter_auto_anon_out_c_bits_address), // @[Filter.scala:60:9] .auto_in_c_bits_data (filter_auto_anon_out_c_bits_data), // @[Filter.scala:60:9] .auto_in_c_bits_corrupt (filter_auto_anon_out_c_bits_corrupt), // @[Filter.scala:60:9] .auto_in_d_ready (filter_auto_anon_out_d_ready), // @[Filter.scala:60:9] .auto_in_d_valid (filter_auto_anon_out_d_valid), .auto_in_d_bits_opcode (filter_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (filter_auto_anon_out_d_bits_param), .auto_in_d_bits_size (filter_auto_anon_out_d_bits_size), .auto_in_d_bits_source (filter_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (filter_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (filter_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (filter_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (filter_auto_anon_out_d_bits_corrupt), .auto_in_e_valid (filter_auto_anon_out_e_valid), // @[Filter.scala:60:9] .auto_in_e_bits_sink (filter_auto_anon_out_e_bits_sink), // @[Filter.scala:60:9] .auto_out_a_ready (_l2_auto_in_a_ready), // @[Configs.scala:93:24] .auto_out_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid), .auto_out_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode), .auto_out_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param), .auto_out_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size), .auto_out_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source), .auto_out_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address), .auto_out_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask), .auto_out_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt), .auto_out_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready), .auto_out_b_valid (_l2_auto_in_b_valid), // @[Configs.scala:93:24] .auto_out_b_bits_param (_l2_auto_in_b_bits_param), // @[Configs.scala:93:24] .auto_out_b_bits_address (_l2_auto_in_b_bits_address), // @[Configs.scala:93:24] .auto_out_c_ready (_l2_auto_in_c_ready), // @[Configs.scala:93:24] .auto_out_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid), .auto_out_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode), .auto_out_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param), .auto_out_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size), .auto_out_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source), .auto_out_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address), .auto_out_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data), .auto_out_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt), .auto_out_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready), .auto_out_d_valid (_l2_auto_in_d_valid), // @[Configs.scala:93:24] .auto_out_d_bits_opcode (_l2_auto_in_d_bits_opcode), // @[Configs.scala:93:24] .auto_out_d_bits_param (_l2_auto_in_d_bits_param), // @[Configs.scala:93:24] .auto_out_d_bits_size (_l2_auto_in_d_bits_size), // @[Configs.scala:93:24] .auto_out_d_bits_source (_l2_auto_in_d_bits_source), // @[Configs.scala:93:24] .auto_out_d_bits_sink (_l2_auto_in_d_bits_sink), // @[Configs.scala:93:24] .auto_out_d_bits_denied (_l2_auto_in_d_bits_denied), // @[Configs.scala:93:24] .auto_out_d_bits_data (_l2_auto_in_d_bits_data), // @[Configs.scala:93:24] .auto_out_d_bits_corrupt (_l2_auto_in_d_bits_corrupt), // @[Configs.scala:93:24] .auto_out_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid), .auto_out_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink) ); // @[Parameters.scala:56:69] TLCacheCork cork ( // @[Configs.scala:120:26] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (InclusiveCache_outer_TLBuffer_auto_out_a_ready), .auto_in_a_valid (InclusiveCache_outer_TLBuffer_auto_out_a_valid), // @[Buffer.scala:40:9] .auto_in_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode), // @[Buffer.scala:40:9] .auto_in_a_bits_param (InclusiveCache_outer_TLBuffer_auto_out_a_bits_param), // @[Buffer.scala:40:9] .auto_in_a_bits_size (InclusiveCache_outer_TLBuffer_auto_out_a_bits_size), // @[Buffer.scala:40:9] .auto_in_a_bits_source (InclusiveCache_outer_TLBuffer_auto_out_a_bits_source), // @[Buffer.scala:40:9] .auto_in_a_bits_address (InclusiveCache_outer_TLBuffer_auto_out_a_bits_address), // @[Buffer.scala:40:9] .auto_in_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask), // @[Buffer.scala:40:9] .auto_in_a_bits_data (InclusiveCache_outer_TLBuffer_auto_out_a_bits_data), // @[Buffer.scala:40:9] .auto_in_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9] .auto_in_c_ready (InclusiveCache_outer_TLBuffer_auto_out_c_ready), .auto_in_c_valid (InclusiveCache_outer_TLBuffer_auto_out_c_valid), // @[Buffer.scala:40:9] .auto_in_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode), // @[Buffer.scala:40:9] .auto_in_c_bits_param (InclusiveCache_outer_TLBuffer_auto_out_c_bits_param), // @[Buffer.scala:40:9] .auto_in_c_bits_size (InclusiveCache_outer_TLBuffer_auto_out_c_bits_size), // @[Buffer.scala:40:9] .auto_in_c_bits_source (InclusiveCache_outer_TLBuffer_auto_out_c_bits_source), // @[Buffer.scala:40:9] .auto_in_c_bits_address (InclusiveCache_outer_TLBuffer_auto_out_c_bits_address), // @[Buffer.scala:40:9] .auto_in_c_bits_data (InclusiveCache_outer_TLBuffer_auto_out_c_bits_data), // @[Buffer.scala:40:9] .auto_in_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt), // @[Buffer.scala:40:9] .auto_in_d_ready (InclusiveCache_outer_TLBuffer_auto_out_d_ready), // @[Buffer.scala:40:9] .auto_in_d_valid (InclusiveCache_outer_TLBuffer_auto_out_d_valid), .auto_in_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode), .auto_in_d_bits_param (InclusiveCache_outer_TLBuffer_auto_out_d_bits_param), .auto_in_d_bits_size (InclusiveCache_outer_TLBuffer_auto_out_d_bits_size), .auto_in_d_bits_source (InclusiveCache_outer_TLBuffer_auto_out_d_bits_source), .auto_in_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink), .auto_in_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied), .auto_in_d_bits_data (InclusiveCache_outer_TLBuffer_auto_out_d_bits_data), .auto_in_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt), .auto_in_e_valid (InclusiveCache_outer_TLBuffer_auto_out_e_valid), // @[Buffer.scala:40:9] .auto_in_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink), // @[Buffer.scala:40:9] .auto_out_a_ready (_binder_auto_in_a_ready), // @[BankBinder.scala:71:28] .auto_out_a_valid (_cork_auto_out_a_valid), .auto_out_a_bits_opcode (_cork_auto_out_a_bits_opcode), .auto_out_a_bits_param (_cork_auto_out_a_bits_param), .auto_out_a_bits_size (_cork_auto_out_a_bits_size), .auto_out_a_bits_source (_cork_auto_out_a_bits_source), .auto_out_a_bits_address (_cork_auto_out_a_bits_address), .auto_out_a_bits_mask (_cork_auto_out_a_bits_mask), .auto_out_a_bits_data (_cork_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_cork_auto_out_a_bits_corrupt), .auto_out_d_ready (_cork_auto_out_d_ready), .auto_out_d_valid (_binder_auto_in_d_valid), // @[BankBinder.scala:71:28] .auto_out_d_bits_opcode (_binder_auto_in_d_bits_opcode), // @[BankBinder.scala:71:28] .auto_out_d_bits_param (_binder_auto_in_d_bits_param), // @[BankBinder.scala:71:28] .auto_out_d_bits_size (_binder_auto_in_d_bits_size), // @[BankBinder.scala:71:28] .auto_out_d_bits_source (_binder_auto_in_d_bits_source), // @[BankBinder.scala:71:28] .auto_out_d_bits_sink (_binder_auto_in_d_bits_sink), // @[BankBinder.scala:71:28] .auto_out_d_bits_denied (_binder_auto_in_d_bits_denied), // @[BankBinder.scala:71:28] .auto_out_d_bits_data (_binder_auto_in_d_bits_data), // @[BankBinder.scala:71:28] .auto_out_d_bits_corrupt (_binder_auto_in_d_bits_corrupt) // @[BankBinder.scala:71:28] ); // @[Configs.scala:120:26] BankBinder binder ( // @[BankBinder.scala:71:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_binder_auto_in_a_ready), .auto_in_a_valid (_cork_auto_out_a_valid), // @[Configs.scala:120:26] .auto_in_a_bits_opcode (_cork_auto_out_a_bits_opcode), // @[Configs.scala:120:26] .auto_in_a_bits_param (_cork_auto_out_a_bits_param), // @[Configs.scala:120:26] .auto_in_a_bits_size (_cork_auto_out_a_bits_size), // @[Configs.scala:120:26] .auto_in_a_bits_source (_cork_auto_out_a_bits_source), // @[Configs.scala:120:26] .auto_in_a_bits_address (_cork_auto_out_a_bits_address), // @[Configs.scala:120:26] .auto_in_a_bits_mask (_cork_auto_out_a_bits_mask), // @[Configs.scala:120:26] .auto_in_a_bits_data (_cork_auto_out_a_bits_data), // @[Configs.scala:120:26] .auto_in_a_bits_corrupt (_cork_auto_out_a_bits_corrupt), // @[Configs.scala:120:26] .auto_in_d_ready (_cork_auto_out_d_ready), // @[Configs.scala:120:26] .auto_in_d_valid (_binder_auto_in_d_valid), .auto_in_d_bits_opcode (_binder_auto_in_d_bits_opcode), .auto_in_d_bits_param (_binder_auto_in_d_bits_param), .auto_in_d_bits_size (_binder_auto_in_d_bits_size), .auto_in_d_bits_source (_binder_auto_in_d_bits_source), .auto_in_d_bits_sink (_binder_auto_in_d_bits_sink), .auto_in_d_bits_denied (_binder_auto_in_d_bits_denied), .auto_in_d_bits_data (_binder_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_binder_auto_in_d_bits_corrupt), .auto_out_a_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7] .auto_out_a_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid), .auto_out_a_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode), .auto_out_a_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param), .auto_out_a_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size), .auto_out_a_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source), .auto_out_a_bits_address (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address), .auto_out_a_bits_mask (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask), .auto_out_a_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data), .auto_out_a_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt), .auto_out_d_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready), .auto_out_d_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_sink (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_denied (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyModuleImp.scala:138:7] ); // @[BankBinder.scala:71:28] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_a_ready = auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_b_valid = auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_b_bits_param = auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_b_bits_address = auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_c_ready = auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_valid = auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_opcode = auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_param = auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_size = auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_source = auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_sink = auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_denied = auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_data = auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_corrupt = auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_a_ready = auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_valid = auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_opcode = auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_size = auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_source = auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_data = auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_120( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_54( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_607; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module TLBuffer_a32d64s1k4z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_72 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s1k4z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s1k4z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSetsblockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined \|\| nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined \|\| nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBitsrowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /* Bundle definitions for HellaCache interfaces / trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /* Base classes for Diplomatic TL2 HellaCaches / abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB \|\| !m.executable \|\| m.regionType >= RegionType.TRACKED \|\| m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM \|\| cfg.blockBytes cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush \|\| cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated / case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /* Mix-ins for constructing tiles that have a HellaCache / trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /* Metadata array used for all HellaCaches */ class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst \|\| io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst }	module tag_array_0( // @[HellaCache.scala:339:30] input [3:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [47:0] RW0_wdata, output [47:0] RW0_rdata, input [1:0] RW0_wmask ); tag_array_ext tag_array_ext ( // @[HellaCache.scala:339:30] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[HellaCache.scala:339:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_175( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_151( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }	module MSHR_4( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [5:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] wire [5:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [1:0] meta_clients; // @[MSHR.scala:100:17] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [1:0] probes_done; // @[MSHR.scala:150:24] reg [1:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [1:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _req_clientBit_T = request_source[5:2]; // @[Parameters.scala:54:10] wire [3:0] _req_clientBit_T_6 = request_source[5:2]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_5 = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T_7 = _req_clientBit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_9 = _req_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_10 = req_clientBit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_11 = _req_clientBit_T_9 & _req_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit = {_req_clientBit_T_11, _req_clientBit_T_5}; // @[Parameters.scala:56:48] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [1:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [1:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _probe_bit_T = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire [3:0] _probe_bit_T_6 = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_5 = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T_7 = _probe_bit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_9 = _probe_bit_T_7; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_10 = probe_bit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_11 = _probe_bit_T_9 & _probe_bit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit = {_probe_bit_T_11, _probe_bit_T_5}; // @[Parameters.scala:56:48] wire [1:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [1:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [1:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [1:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [1:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire [5:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [1:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _new_clientBit_T = new_request_source[5:2]; // @[Parameters.scala:54:10] wire [3:0] _new_clientBit_T_6 = new_request_source[5:2]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_5 = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T_7 = _new_clientBit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_9 = _new_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_10 = new_clientBit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_11 = _new_clientBit_T_9 & _new_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit = {_new_clientBit_T_11, _new_clientBit_T_5}; // @[Parameters.scala:56:48] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_101( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_378( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_122 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module IntSyncSyncCrossingSink_n1x5( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] input auto_in_sync_1, // @[LazyModuleImp.scala:107:25] input auto_in_sync_2, // @[LazyModuleImp.scala:107:25] input auto_in_sync_3, // @[LazyModuleImp.scala:107:25] input auto_in_sync_4, // @[LazyModuleImp.scala:107:25] output auto_out_0, // @[LazyModuleImp.scala:107:25] output auto_out_1, // @[LazyModuleImp.scala:107:25] output auto_out_2, // @[LazyModuleImp.scala:107:25] output auto_out_3, // @[LazyModuleImp.scala:107:25] output auto_out_4 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire auto_in_sync_1_0 = auto_in_sync_1; // @[Crossing.scala:96:9] wire auto_in_sync_2_0 = auto_in_sync_2; // @[Crossing.scala:96:9] wire auto_in_sync_3_0 = auto_in_sync_3; // @[Crossing.scala:96:9] wire auto_in_sync_4_0 = auto_in_sync_4; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeIn_sync_1 = auto_in_sync_1_0; // @[Crossing.scala:96:9] wire nodeIn_sync_2 = auto_in_sync_2_0; // @[Crossing.scala:96:9] wire nodeIn_sync_3 = auto_in_sync_3_0; // @[Crossing.scala:96:9] wire nodeIn_sync_4 = auto_in_sync_4_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire nodeOut_1; // @[MixedNode.scala:542:17] wire nodeOut_2; // @[MixedNode.scala:542:17] wire nodeOut_3; // @[MixedNode.scala:542:17] wire nodeOut_4; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] wire auto_out_1_0; // @[Crossing.scala:96:9] wire auto_out_2_0; // @[Crossing.scala:96:9] wire auto_out_3_0; // @[Crossing.scala:96:9] wire auto_out_4_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_1 = nodeIn_sync_1; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_2 = nodeIn_sync_2; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_3 = nodeIn_sync_3; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_4 = nodeIn_sync_4; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_1_0 = nodeOut_1; // @[Crossing.scala:96:9] assign auto_out_2_0 = nodeOut_2; // @[Crossing.scala:96:9] assign auto_out_3_0 = nodeOut_3; // @[Crossing.scala:96:9] assign auto_out_4_0 = nodeOut_4; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] assign auto_out_1 = auto_out_1_0; // @[Crossing.scala:96:9] assign auto_out_2 = auto_out_2_0; // @[Crossing.scala:96:9] assign auto_out_3 = auto_out_3_0; // @[Crossing.scala:96:9] assign auto_out_4 = auto_out_4_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width2, width) >> 1) \| (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_\|\|_).init assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ \| _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_\|\|_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_) count := count + 1.U io.finished := count >= txns.U } /* This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. / class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /* This tests that the lowest index is always selected across random single cycle transactions. / class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /* This tests that the highest index is always selected across random single cycle transactions. / class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module TLXbar_mbus_i1_o2_a32d64s4k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _portsAOI_in_0_a_ready_T_2 = auto_anon_in_a_bits_address[31] & auto_anon_out_0_a_ready \| ~(auto_anon_in_a_bits_address[31]) & auto_anon_out_1_a_ready; // @[Mux.scala:30:73] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire [1:0] readys_valid = {auto_anon_out_1_d_valid, auto_anon_out_0_d_valid}; // @[Arbiter.scala:68:51] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [1:0] readys_readys = ~({readys_mask[1], _readys_filter_T_1[1] \| readys_mask[0]} & ({_readys_filter_T_1[0], auto_anon_out_1_d_valid} \| _readys_filter_T_1)); // @[package.scala:262:43] wire winner_0 = readys_readys[0] & auto_anon_out_0_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_1 = readys_readys[1] & auto_anon_out_1_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire _in_0_d_valid_T = auto_anon_out_0_d_valid \| auto_anon_out_1_d_valid; // @[Arbiter.scala:79:31]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_155( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File composer.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} class ComposedBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val (components, resp) = getBPDComponents(io.resp_in(0), p) io.resp := resp var metas = 0.U(1.W) var meta_sz = 0 for (c <- components) { c.io.f0_valid := io.f0_valid c.io.f0_pc := io.f0_pc c.io.f0_mask := io.f0_mask c.io.f1_ghist := io.f1_ghist c.io.f1_lhist := io.f1_lhist c.io.f3_fire := io.f3_fire if (c.metaSz > 0) { metas = (metas << c.metaSz) \| c.io.f3_meta(c.metaSz-1,0) } meta_sz = meta_sz + c.metaSz } require(meta_sz < bpdMaxMetaLength) io.f3_meta := metas var update_meta = io.update.bits.meta for (c <- components.reverse) { c.io.update := io.update c.io.update.bits.meta := update_meta update_meta = update_meta >> c.metaSz } val mems = components.map(_.mems).flatten } File predictor.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} // A branch prediction for a single instruction class BranchPrediction(implicit p: Parameters) extends BoomBundle()(p) { // If this is a branch, do we take it? val taken = Bool() // Is this a branch? val is_br = Bool() // Is this a JAL? val is_jal = Bool() // What is the target of his branch/jump? Do we know the target? val predicted_pc = Valid(UInt(vaddrBitsExtended.W)) } // A branch prediction for a entire fetch-width worth of instructions // This is typically merged from individual predictions from the banked // predictor class BranchPredictionBundle(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val pc = UInt(vaddrBitsExtended.W) val preds = Vec(fetchWidth, new BranchPrediction) val meta = Output(Vec(nBanks, UInt(bpdMaxMetaLength.W))) val lhist = Output(Vec(nBanks, UInt(localHistoryLength.W))) } // A branch update for a fetch-width worth of instructions class BranchPredictionUpdate(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { // Indicates that this update is due to a speculated misprediction // Local predictors typically update themselves with speculative info // Global predictors only care about non-speculative updates val is_mispredict_update = Bool() val is_repair_update = Bool() val btb_mispredicts = UInt(fetchWidth.W) def is_btb_mispredict_update = btb_mispredicts =/= 0.U def is_commit_update = !(is_mispredict_update \|\| is_repair_update \|\| is_btb_mispredict_update) val pc = UInt(vaddrBitsExtended.W) // Mask of instructions which are branches. // If these are not cfi_idx, then they were predicted not taken val br_mask = UInt(fetchWidth.W) // Which CFI was taken/mispredicted (if any) val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W)) // Was the cfi taken? val cfi_taken = Bool() // Was the cfi mispredicted from the original prediction? val cfi_mispredicted = Bool() // Was the cfi a br? val cfi_is_br = Bool() // Was the cfi a jal/jalr? val cfi_is_jal = Bool() // Was the cfi a jalr val cfi_is_jalr = Bool() //val cfi_is_ret = Bool() val ghist = new GlobalHistory val lhist = Vec(nBanks, UInt(localHistoryLength.W)) // What did this CFI jump to? val target = UInt(vaddrBitsExtended.W) val meta = Vec(nBanks, UInt(bpdMaxMetaLength.W)) } // A branch update to a single bank class BranchPredictionBankUpdate(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val is_mispredict_update = Bool() val is_repair_update = Bool() val btb_mispredicts = UInt(bankWidth.W) def is_btb_mispredict_update = btb_mispredicts =/= 0.U def is_commit_update = !(is_mispredict_update \|\| is_repair_update \|\| is_btb_mispredict_update) val pc = UInt(vaddrBitsExtended.W) val br_mask = UInt(bankWidth.W) val cfi_idx = Valid(UInt(log2Ceil(bankWidth).W)) val cfi_taken = Bool() val cfi_mispredicted = Bool() val cfi_is_br = Bool() val cfi_is_jal = Bool() val cfi_is_jalr = Bool() val ghist = UInt(globalHistoryLength.W) val lhist = UInt(localHistoryLength.W) val target = UInt(vaddrBitsExtended.W) val meta = UInt(bpdMaxMetaLength.W) } class BranchPredictionRequest(implicit p: Parameters) extends BoomBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val ghist = new GlobalHistory } class BranchPredictionBankResponse(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val f1 = Vec(bankWidth, new BranchPrediction) val f2 = Vec(bankWidth, new BranchPrediction) val f3 = Vec(bankWidth, new BranchPrediction) } abstract class BranchPredictorBank(implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { val metaSz = 0 def nInputs = 1 val mems: Seq[Tuple3[String, Int, Int]] val io = IO(new Bundle { val f0_valid = Input(Bool()) val f0_pc = Input(UInt(vaddrBitsExtended.W)) val f0_mask = Input(UInt(bankWidth.W)) // Local history not available until end of f1 val f1_ghist = Input(UInt(globalHistoryLength.W)) val f1_lhist = Input(UInt(localHistoryLength.W)) val resp_in = Input(Vec(nInputs, new BranchPredictionBankResponse)) val resp = Output(new BranchPredictionBankResponse) // Store the meta as a UInt, use width inference to figure out the shape val f3_meta = Output(UInt(bpdMaxMetaLength.W)) val f3_fire = Input(Bool()) val update = Input(Valid(new BranchPredictionBankUpdate)) }) io.resp := io.resp_in(0) io.f3_meta := 0.U val s0_idx = fetchIdx(io.f0_pc) val s1_idx = RegNext(s0_idx) val s2_idx = RegNext(s1_idx) val s3_idx = RegNext(s2_idx) val s0_valid = io.f0_valid val s1_valid = RegNext(s0_valid) val s2_valid = RegNext(s1_valid) val s3_valid = RegNext(s2_valid) val s0_mask = io.f0_mask val s1_mask = RegNext(s0_mask) val s2_mask = RegNext(s1_mask) val s3_mask = RegNext(s2_mask) val s0_pc = io.f0_pc val s1_pc = RegNext(s0_pc) val s0_update = io.update val s0_update_idx = fetchIdx(io.update.bits.pc) val s0_update_valid = io.update.valid val s1_update = RegNext(s0_update) val s1_update_idx = RegNext(s0_update_idx) val s1_update_valid = RegNext(s0_update_valid) } class BranchPredictor(implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { val io = IO(new Bundle { // Requests and responses val f0_req = Input(Valid(new BranchPredictionRequest)) val resp = Output(new Bundle { val f1 = new BranchPredictionBundle val f2 = new BranchPredictionBundle val f3 = new BranchPredictionBundle }) val f3_fire = Input(Bool()) // Update val update = Input(Valid(new BranchPredictionUpdate)) }) var total_memsize = 0 val bpdStr = new StringBuilder bpdStr.append(BoomCoreStringPrefix("==Branch Predictor Memory Sizes==\n")) val banked_predictors = (0 until nBanks) map ( b => { val m = Module(if (useBPD) new ComposedBranchPredictorBank else new NullBranchPredictorBank) for ((n, d, w) <- m.mems) { bpdStr.append(BoomCoreStringPrefix(f"bank$b $n: $d x $w = ${d * w / 8}")) total_memsize = total_memsize + d * w / 8 } m }) bpdStr.append(BoomCoreStringPrefix(f"Total bpd size: ${total_memsize / 1024} KB\n")) override def toString: String = bpdStr.toString val banked_lhist_providers = Seq.fill(nBanks) { Module(if (localHistoryNSets > 0) new LocalBranchPredictorBank else new NullLocalBranchPredictorBank) } if (nBanks == 1) { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc) banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) } else { require(nBanks == 2) banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) banked_predictors(1).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist banked_predictors(1).io.f1_lhist := banked_lhist_providers(1).io.f1_lhist when (bank(io.f0_req.bits.pc) === 0.U) { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_lhist_providers(1).io.f0_valid := io.f0_req.valid banked_lhist_providers(1).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc) banked_predictors(1).io.f0_valid := io.f0_req.valid banked_predictors(1).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(1).io.f0_mask := ~(0.U(bankWidth.W)) } .otherwise { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc) banked_lhist_providers(0).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_lhist_providers(1).io.f0_valid := io.f0_req.valid banked_lhist_providers(1).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc) banked_predictors(0).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := ~(0.U(bankWidth.W)) banked_predictors(1).io.f0_valid := io.f0_req.valid banked_predictors(1).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(1).io.f0_mask := fetchMask(io.f0_req.bits.pc) } when (RegNext(bank(io.f0_req.bits.pc) === 0.U)) { banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1)) } .otherwise { banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1)) banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) } } for (i <- 0 until nBanks) { banked_lhist_providers(i).io.f3_taken_br := banked_predictors(i).io.resp.f3.map ( p => p.is_br && p.predicted_pc.valid && p.taken ).reduce(_\|\|_) } if (nBanks == 1) { io.resp.f1.preds := banked_predictors(0).io.resp.f1 io.resp.f2.preds := banked_predictors(0).io.resp.f2 io.resp.f3.preds := banked_predictors(0).io.resp.f3 io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist banked_predictors(0).io.f3_fire := io.f3_fire banked_lhist_providers(0).io.f3_fire := io.f3_fire } else { require(nBanks == 2) val b0_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(0).io.f0_valid))) val b1_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(1).io.f0_valid))) banked_predictors(0).io.f3_fire := b0_fire banked_predictors(1).io.f3_fire := b1_fire banked_lhist_providers(0).io.f3_fire := b0_fire banked_lhist_providers(1).io.f3_fire := b1_fire // The branch prediction metadata is stored un-shuffled io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta io.resp.f3.meta(1) := banked_predictors(1).io.f3_meta io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist io.resp.f3.lhist(1) := banked_lhist_providers(1).io.f3_lhist when (bank(io.resp.f1.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f1.preds(i) := banked_predictors(0).io.resp.f1(i) io.resp.f1.preds(i+bankWidth) := banked_predictors(1).io.resp.f1(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f1.preds(i) := banked_predictors(1).io.resp.f1(i) io.resp.f1.preds(i+bankWidth) := banked_predictors(0).io.resp.f1(i) } } when (bank(io.resp.f2.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f2.preds(i) := banked_predictors(0).io.resp.f2(i) io.resp.f2.preds(i+bankWidth) := banked_predictors(1).io.resp.f2(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f2.preds(i) := banked_predictors(1).io.resp.f2(i) io.resp.f2.preds(i+bankWidth) := banked_predictors(0).io.resp.f2(i) } } when (bank(io.resp.f3.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f3.preds(i) := banked_predictors(0).io.resp.f3(i) io.resp.f3.preds(i+bankWidth) := banked_predictors(1).io.resp.f3(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f3.preds(i) := banked_predictors(1).io.resp.f3(i) io.resp.f3.preds(i+bankWidth) := banked_predictors(0).io.resp.f3(i) } } } io.resp.f1.pc := RegNext(io.f0_req.bits.pc) io.resp.f2.pc := RegNext(io.resp.f1.pc) io.resp.f3.pc := RegNext(io.resp.f2.pc) // We don't care about meta from the f1 and f2 resps // Use the meta from the latest resp io.resp.f1.meta := DontCare io.resp.f2.meta := DontCare io.resp.f1.lhist := DontCare io.resp.f2.lhist := DontCare for (i <- 0 until nBanks) { banked_predictors(i).io.update.bits.is_mispredict_update := io.update.bits.is_mispredict_update banked_predictors(i).io.update.bits.is_repair_update := io.update.bits.is_repair_update banked_predictors(i).io.update.bits.meta := io.update.bits.meta(i) banked_predictors(i).io.update.bits.lhist := io.update.bits.lhist(i) banked_predictors(i).io.update.bits.cfi_idx.bits := io.update.bits.cfi_idx.bits banked_predictors(i).io.update.bits.cfi_taken := io.update.bits.cfi_taken banked_predictors(i).io.update.bits.cfi_mispredicted := io.update.bits.cfi_mispredicted banked_predictors(i).io.update.bits.cfi_is_br := io.update.bits.cfi_is_br banked_predictors(i).io.update.bits.cfi_is_jal := io.update.bits.cfi_is_jal banked_predictors(i).io.update.bits.cfi_is_jalr := io.update.bits.cfi_is_jalr banked_predictors(i).io.update.bits.target := io.update.bits.target banked_lhist_providers(i).io.update.mispredict := io.update.bits.is_mispredict_update banked_lhist_providers(i).io.update.repair := io.update.bits.is_repair_update banked_lhist_providers(i).io.update.lhist := io.update.bits.lhist(i) } if (nBanks == 1) { banked_predictors(0).io.update.valid := io.update.valid banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask =/= 0.U banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc) } else { require(nBanks == 2) // Split the single update bundle for the fetchpacket into two updates // 1 for each bank. when (bank(io.update.bits.pc) === 0.U) { val b1_update_valid = io.update.valid && (!io.update.bits.cfi_idx.valid \|\| io.update.bits.cfi_idx.bits >= bankWidth.U) banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U banked_lhist_providers(1).io.update.valid := b1_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc) banked_lhist_providers(1).io.update.pc := nextBank(io.update.bits.pc) banked_predictors(0).io.update.valid := io.update.valid banked_predictors(1).io.update.valid := b1_update_valid banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(1).io.update.bits.pc := nextBank(io.update.bits.pc) banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(1) } .otherwise { val b0_update_valid = io.update.valid && !mayNotBeDualBanked(io.update.bits.pc) && (!io.update.bits.cfi_idx.valid \|\| io.update.bits.cfi_idx.bits >= bankWidth.U) banked_lhist_providers(1).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U banked_lhist_providers(0).io.update.valid := b0_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U banked_lhist_providers(1).io.update.pc := bankAlign(io.update.bits.pc) banked_lhist_providers(0).io.update.pc := nextBank(io.update.bits.pc) banked_predictors(1).io.update.valid := io.update.valid banked_predictors(0).io.update.valid := b0_update_valid banked_predictors(1).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(0).io.update.bits.pc := nextBank(io.update.bits.pc) banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(1) } } when (io.update.valid) { when (io.update.bits.cfi_is_br && io.update.bits.cfi_idx.valid) { assert(io.update.bits.br_mask(io.update.bits.cfi_idx.bits)) } } } class NullBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val mems = Nil } File config-mixins.scala: //**************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ package boom.v3.common import chisel3._ import chisel3.util.{log2Up} import org.chipsalliance.cde.config.{Parameters, Config, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.{BootROMParams} import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing} import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ import boom.v3.ifu._ import boom.v3.exu._ import boom.v3.lsu._ // --------------------- // BOOM Config Fragments // --------------------- class WithBoomCommitLogPrintf extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( enableCommitLogPrintf = true ))) case other => other } }) class WithBoomBranchPrintf extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( enableBranchPrintf = true ))) case other => other } }) class WithNBoomPerfCounters(n: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( nPerfCounters = n ))) case other => other } }) class WithSynchronousBoomTiles extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( crossingType = SynchronousCrossing() )) case other => other } }) class WithAsynchronousBoomTiles extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( crossingType = AsynchronousCrossing() )) case other => other } }) class WithRationalBoomTiles extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( crossingType = RationalCrossing() )) case other => other } }) / * 1-wide BOOM. / class WithNSmallBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 4, decodeWidth = 1, numRobEntries = 32, issueParams = Seq( IssueParams(issueWidth=1, numEntries=8, iqType=IQT_MEM.litValue, dispatchWidth=1), IssueParams(issueWidth=1, numEntries=8, iqType=IQT_INT.litValue, dispatchWidth=1), IssueParams(issueWidth=1, numEntries=8, iqType=IQT_FP.litValue , dispatchWidth=1)), numIntPhysRegisters = 52, numFpPhysRegisters = 48, numLdqEntries = 8, numStqEntries = 8, maxBrCount = 8, numFetchBufferEntries = 8, ftq = FtqParameters(nEntries=16), nPerfCounters = 2, fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true)) ), dcache = Some( DCacheParams(rowBits = 64, nSets=64, nWays=4, nMSHRs=2, nTLBWays=8) ), icache = Some( ICacheParams(rowBits = 64, nSets=64, nWays=4, fetchBytes=24) ), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) /** * 2-wide BOOM. / class WithNMediumBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 4, decodeWidth = 2, numRobEntries = 64, issueParams = Seq( IssueParams(issueWidth=1, numEntries=12, iqType=IQT_MEM.litValue, dispatchWidth=2), IssueParams(issueWidth=2, numEntries=20, iqType=IQT_INT.litValue, dispatchWidth=2), IssueParams(issueWidth=1, numEntries=16, iqType=IQT_FP.litValue , dispatchWidth=2)), numIntPhysRegisters = 80, numFpPhysRegisters = 64, numLdqEntries = 16, numStqEntries = 16, maxBrCount = 12, numFetchBufferEntries = 16, ftq = FtqParameters(nEntries=32), nPerfCounters = 6, fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true)) ), dcache = Some( DCacheParams(rowBits = 64, nSets=64, nWays=4, nMSHRs=2, nTLBWays=8) ), icache = Some( ICacheParams(rowBits = 64, nSets=64, nWays=4, fetchBytes=24) ), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) // DOC include start: LargeBoomConfig /** * 3-wide BOOM. Try to match the Cortex-A15. / class WithNLargeBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 8, decodeWidth = 3, numRobEntries = 96, issueParams = Seq( IssueParams(issueWidth=1, numEntries=16, iqType=IQT_MEM.litValue, dispatchWidth=3), IssueParams(issueWidth=3, numEntries=32, iqType=IQT_INT.litValue, dispatchWidth=3), IssueParams(issueWidth=1, numEntries=24, iqType=IQT_FP.litValue , dispatchWidth=3)), numIntPhysRegisters = 100, numFpPhysRegisters = 96, numLdqEntries = 24, numStqEntries = 24, maxBrCount = 16, numFetchBufferEntries = 24, ftq = FtqParameters(nEntries=32), fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true)) ), dcache = Some( DCacheParams(rowBits = 128, nSets=64, nWays=8, nMSHRs=4, nTLBWays=16) ), icache = Some( ICacheParams(rowBits = 128, nSets=64, nWays=8, fetchBytes=44) ), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) // DOC include end: LargeBoomConfig /** * 4-wide BOOM. / class WithNMegaBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 8, decodeWidth = 4, numRobEntries = 128, issueParams = Seq( IssueParams(issueWidth=2, numEntries=24, iqType=IQT_MEM.litValue, dispatchWidth=4), IssueParams(issueWidth=4, numEntries=40, iqType=IQT_INT.litValue, dispatchWidth=4), IssueParams(issueWidth=2, numEntries=32, iqType=IQT_FP.litValue , dispatchWidth=4)), numIntPhysRegisters = 128, numFpPhysRegisters = 128, numLdqEntries = 32, numStqEntries = 32, maxBrCount = 20, numFetchBufferEntries = 32, enablePrefetching = true, ftq = FtqParameters(nEntries=40), fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true)) ), dcache = Some( DCacheParams(rowBits = 128, nSets=64, nWays=8, nMSHRs=8, nTLBWays=32) ), icache = Some( ICacheParams(rowBits = 128, nSets=64, nWays=8, fetchBytes=44) ), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) /** * 5-wide BOOM. / class WithNGigaBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 8, decodeWidth = 5, numRobEntries = 130, issueParams = Seq( IssueParams(issueWidth=2, numEntries=24, iqType=IQT_MEM.litValue, dispatchWidth=5), IssueParams(issueWidth=5, numEntries=40, iqType=IQT_INT.litValue, dispatchWidth=5), IssueParams(issueWidth=2, numEntries=32, iqType=IQT_FP.litValue , dispatchWidth=5)), numIntPhysRegisters = 128, numFpPhysRegisters = 128, numLdqEntries = 32, numStqEntries = 32, maxBrCount = 20, numFetchBufferEntries = 35, enablePrefetching = true, numDCacheBanks = 1, ftq = FtqParameters(nEntries=40), fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true)) ), dcache = Some( DCacheParams(rowBits = 128, nSets=64, nWays=8, nMSHRs=8, nTLBWays=32) ), icache = Some( ICacheParams(rowBits = 128, nSets=64, nWays=8, fetchBytes=44) ), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) class WithCloneBoomTiles( n: Int = 1, cloneTileId: Int = 0, location: HierarchicalLocation = InSubsystem, cloneLocation: HierarchicalLocation = InSubsystem ) extends Config((site, here, up) => { case TilesLocated(`location`) => { val prev = up(TilesLocated(location), site) val idOffset = up(NumTiles) val tileAttachParams = up(TilesLocated(cloneLocation)).find(_.tileParams.tileId == cloneTileId) .get.asInstanceOf[BoomTileAttachParams] (0 until n).map { i => CloneTileAttachParams(cloneTileId, tileAttachParams.copy( tileParams = tileAttachParams.tileParams.copy(tileId = i + idOffset) )) } ++ prev } case NumTiles => up(NumTiles) + n }) /** * BOOM Configs for CS152 lab / class WithNCS152BaselineBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => val coreWidth = 1 // CS152: Change me (1 to 4) val memWidth = 1 // CS152: Change me (1 or 2) BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 4, // CS152: Change me (4 or 8) numRobEntries = 4, // CS152: Change me (2+) numIntPhysRegisters = 33, // CS152: Change me (33+) numLdqEntries = 8, // CS152: Change me (2+) numStqEntries = 8, // CS152: Change me (2+) maxBrCount = 8, // CS152: Change me (2+) enableBranchPrediction = false, // CS152: Change me numRasEntries = 0, // CS152: Change me // DO NOT CHANGE BELOW enableBranchPrintf = true, decodeWidth = coreWidth, numFetchBufferEntries = coreWidth 8, numDCacheBanks = memWidth, issueParams = Seq( IssueParams(issueWidth=memWidth, numEntries=8, iqType=IQT_MEM.litValue, dispatchWidth=coreWidth), IssueParams(issueWidth=coreWidth, numEntries=32, iqType=IQT_INT.litValue, dispatchWidth=coreWidth), IssueParams(issueWidth=1, numEntries=4, iqType=IQT_FP.litValue , dispatchWidth=coreWidth)) // DO NOT CHANGE ABOVE ), dcache = Some(DCacheParams( rowBits=64, nSets=64, // CS152: Change me (must be pow2, 2-64) nWays=4, // CS152: Change me (1-8) nMSHRs=2 // CS152: Change me (1+) )), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) class WithNCS152DefaultBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => val coreWidth = 3 // CS152: Change me (1 to 4) val memWidth = 1 // CS152: Change me (1 or 2) val nIssueSlots = 32 // CS152: Change me (2+) BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 4, // CS152: Change me (4 or 8) numRobEntries = 96, // CS152: Change me (2+) numIntPhysRegisters = 96, // CS152: Change me (33+) numLdqEntries = 16, // CS152: Change me (2+) numStqEntries = 16, // CS152: Change me (2+) maxBrCount = 12, // CS152: Change me (2+) enableBranchPrediction = true, // CS152: Change me numRasEntries = 16, // CS152: Change me // DO NOT CHANGE BELOW enableBranchPrintf = true, decodeWidth = coreWidth, numFetchBufferEntries = coreWidth * 8, numDCacheBanks = memWidth, issueParams = Seq( IssueParams(issueWidth=memWidth, numEntries=nIssueSlots, iqType=IQT_MEM.litValue, dispatchWidth=coreWidth), IssueParams(issueWidth=coreWidth, numEntries=nIssueSlots, iqType=IQT_INT.litValue, dispatchWidth=coreWidth), IssueParams(issueWidth=1, numEntries=nIssueSlots, iqType=IQT_FP.litValue , dispatchWidth=coreWidth)) // DO NOT CHANGE ABOVE ), dcache = Some(DCacheParams( rowBits=64, nSets=64, // CS152: Change me (must be pow2, 2-64) nWays=4, // CS152: Change me (1-8) nMSHRs=2 // CS152: Change me (1+) )), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) /** * Branch prediction configs below */ class WithTAGELBPD extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( bpdMaxMetaLength = 120, globalHistoryLength = 64, localHistoryLength = 1, localHistoryNSets = 0, branchPredictor = ((resp_in: BranchPredictionBankResponse, p: Parameters) => { val loop = Module(new LoopBranchPredictorBank()(p)) val tage = Module(new TageBranchPredictorBank()(p)) val btb = Module(new BTBBranchPredictorBank()(p)) val bim = Module(new BIMBranchPredictorBank()(p)) val ubtb = Module(new FAMicroBTBBranchPredictorBank()(p)) val preds = Seq(loop, tage, btb, ubtb, bim) preds.map(_.io := DontCare) ubtb.io.resp_in(0) := resp_in bim.io.resp_in(0) := ubtb.io.resp btb.io.resp_in(0) := bim.io.resp tage.io.resp_in(0) := btb.io.resp loop.io.resp_in(0) := tage.io.resp (preds, loop.io.resp) }) ))) case other => other } }) class WithBoom2BPD extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( bpdMaxMetaLength = 45, globalHistoryLength = 16, localHistoryLength = 1, localHistoryNSets = 0, branchPredictor = ((resp_in: BranchPredictionBankResponse, p: Parameters) => { // gshare is just variant of TAGE with 1 table val gshare = Module(new TageBranchPredictorBank( BoomTageParams(tableInfo = Seq((256, 16, 7))) )(p)) val btb = Module(new BTBBranchPredictorBank()(p)) val bim = Module(new BIMBranchPredictorBank()(p)) val preds = Seq(bim, btb, gshare) preds.map(_.io := DontCare) bim.io.resp_in(0) := resp_in btb.io.resp_in(0) := bim.io.resp gshare.io.resp_in(0) := btb.io.resp (preds, gshare.io.resp) }) ))) case other => other } }) class WithAlpha21264BPD extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( bpdMaxMetaLength = 64, globalHistoryLength = 32, localHistoryLength = 32, localHistoryNSets = 128, branchPredictor = ((resp_in: BranchPredictionBankResponse, p: Parameters) => { val btb = Module(new BTBBranchPredictorBank()(p)) val gbim = Module(new HBIMBranchPredictorBank()(p)) val lbim = Module(new HBIMBranchPredictorBank(BoomHBIMParams(useLocal=true))(p)) val tourney = Module(new TourneyBranchPredictorBank()(p)) val preds = Seq(lbim, btb, gbim, tourney) preds.map(_.io := DontCare) gbim.io.resp_in(0) := resp_in lbim.io.resp_in(0) := resp_in tourney.io.resp_in(0) := gbim.io.resp tourney.io.resp_in(1) := lbim.io.resp btb.io.resp_in(0) := tourney.io.resp (preds, btb.io.resp) }) ))) case other => other } }) class WithSWBPD extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( bpdMaxMetaLength = 1, globalHistoryLength = 32, localHistoryLength = 1, localHistoryNSets = 0, branchPredictor = ((resp_in: BranchPredictionBankResponse, p: Parameters) => { val sw = Module(new SwBranchPredictorBank()(p)) sw.io.resp_in(0) := resp_in (Seq(sw), sw.io.resp) }) ))) case other => other } })	module ComposedBranchPredictorBank_1( // @[composer.scala:14:7] input clock, // @[composer.scala:14:7] input reset, // @[composer.scala:14:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire _ubtb_io_resp_f1_0_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_0_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_0_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:449:26] wire [119:0] _ubtb_io_f3_meta; // @[config-mixins.scala:449:26] wire _bim_io_resp_f1_0_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_0_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_0_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:448:25] wire [119:0] _bim_io_f3_meta; // @[config-mixins.scala:448:25] wire _btb_io_resp_f1_0_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_0_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_0_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:447:25] wire [119:0] _btb_io_f3_meta; // @[config-mixins.scala:447:25] wire _tage_io_resp_f1_0_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_0_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_0_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:446:26] wire [119:0] _tage_io_f3_meta; // @[config-mixins.scala:446:26] wire [119:0] _loop_io_f3_meta; // @[config-mixins.scala:445:26] wire io_f0_valid_0 = io_f0_valid; // @[composer.scala:14:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[composer.scala:14:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[composer.scala:14:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[composer.scala:14:7] wire io_f3_fire_0 = io_f3_fire; // @[composer.scala:14:7] wire io_update_valid_0 = io_update_valid; // @[composer.scala:14:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[composer.scala:14:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[composer.scala:14:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[composer.scala:14:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[composer.scala:14:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[composer.scala:14:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[composer.scala:14:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[composer.scala:14:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[composer.scala:14:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[composer.scala:14:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[composer.scala:14:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[composer.scala:14:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[composer.scala:14:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[composer.scala:14:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[composer.scala:14:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[composer.scala:14:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[composer.scala:14:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire io_f1_lhist = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_0_taken_0; // @[composer.scala:14:7] wire io_resp_f1_0_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_0_is_jal_0; // @[composer.scala:14:7] wire io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_1_taken_0; // @[composer.scala:14:7] wire io_resp_f1_1_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_1_is_jal_0; // @[composer.scala:14:7] wire io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_2_taken_0; // @[composer.scala:14:7] wire io_resp_f1_2_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_2_is_jal_0; // @[composer.scala:14:7] wire io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_3_taken_0; // @[composer.scala:14:7] wire io_resp_f1_3_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_3_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_0_taken_0; // @[composer.scala:14:7] wire io_resp_f2_0_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_0_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_1_taken_0; // @[composer.scala:14:7] wire io_resp_f2_1_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_1_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_2_taken_0; // @[composer.scala:14:7] wire io_resp_f2_2_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_2_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_3_taken_0; // @[composer.scala:14:7] wire io_resp_f2_3_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_3_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_0_taken_0; // @[composer.scala:14:7] wire io_resp_f3_0_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_0_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_1_taken_0; // @[composer.scala:14:7] wire io_resp_f3_1_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_1_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_2_taken_0; // @[composer.scala:14:7] wire io_resp_f3_2_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_2_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_3_taken_0; // @[composer.scala:14:7] wire io_resp_f3_3_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_3_is_jal_0; // @[composer.scala:14:7] wire [119:0] io_f3_meta_0; // @[composer.scala:14:7] wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35] reg [35:0] s1_idx; // @[predictor.scala:163:29] reg [35:0] s2_idx; // @[predictor.scala:164:29] reg [35:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [35:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] assign io_f3_meta_0 = {7'h0, _loop_io_f3_meta[39:0], _tage_io_f3_meta[55:0], _btb_io_f3_meta[0], _ubtb_io_f3_meta[7:0], _bim_io_f3_meta[7:0]}; // @[composer.scala:14:7, :31:49, :36:14] always @(posedge clock) begin // @[composer.scala:14:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30] s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32] always @(posedge) LoopBranchPredictorBank_1 loop ( // @[config-mixins.scala:445:26] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_tage_io_resp_f1_0_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_is_br (_tage_io_resp_f1_0_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_is_jal (_tage_io_resp_f1_0_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_taken (_tage_io_resp_f1_1_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_is_br (_tage_io_resp_f1_1_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_is_jal (_tage_io_resp_f1_1_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_taken (_tage_io_resp_f1_2_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_is_br (_tage_io_resp_f1_2_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_is_jal (_tage_io_resp_f1_2_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_taken (_tage_io_resp_f1_3_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_is_br (_tage_io_resp_f1_3_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_is_jal (_tage_io_resp_f1_3_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_taken (_tage_io_resp_f2_0_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_is_br (_tage_io_resp_f2_0_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_is_jal (_tage_io_resp_f2_0_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_taken (_tage_io_resp_f2_1_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_is_br (_tage_io_resp_f2_1_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_is_jal (_tage_io_resp_f2_1_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_taken (_tage_io_resp_f2_2_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_is_br (_tage_io_resp_f2_2_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_is_jal (_tage_io_resp_f2_2_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_taken (_tage_io_resp_f2_3_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_is_br (_tage_io_resp_f2_3_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_is_jal (_tage_io_resp_f2_3_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_taken (_tage_io_resp_f3_0_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_is_br (_tage_io_resp_f3_0_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_is_jal (_tage_io_resp_f3_0_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_taken (_tage_io_resp_f3_1_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_is_br (_tage_io_resp_f3_1_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_is_jal (_tage_io_resp_f3_1_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_taken (_tage_io_resp_f3_2_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_is_br (_tage_io_resp_f3_2_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_is_jal (_tage_io_resp_f3_2_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_taken (_tage_io_resp_f3_3_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_is_br (_tage_io_resp_f3_3_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_is_jal (_tage_io_resp_f3_3_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_f1_0_taken (io_resp_f1_0_taken_0), .io_resp_f1_0_is_br (io_resp_f1_0_is_br_0), .io_resp_f1_0_is_jal (io_resp_f1_0_is_jal_0), .io_resp_f1_0_predicted_pc_valid (io_resp_f1_0_predicted_pc_valid_0), .io_resp_f1_0_predicted_pc_bits (io_resp_f1_0_predicted_pc_bits_0), .io_resp_f1_1_taken (io_resp_f1_1_taken_0), .io_resp_f1_1_is_br (io_resp_f1_1_is_br_0), .io_resp_f1_1_is_jal (io_resp_f1_1_is_jal_0), .io_resp_f1_1_predicted_pc_valid (io_resp_f1_1_predicted_pc_valid_0), .io_resp_f1_1_predicted_pc_bits (io_resp_f1_1_predicted_pc_bits_0), .io_resp_f1_2_taken (io_resp_f1_2_taken_0), .io_resp_f1_2_is_br (io_resp_f1_2_is_br_0), .io_resp_f1_2_is_jal (io_resp_f1_2_is_jal_0), .io_resp_f1_2_predicted_pc_valid (io_resp_f1_2_predicted_pc_valid_0), .io_resp_f1_2_predicted_pc_bits (io_resp_f1_2_predicted_pc_bits_0), .io_resp_f1_3_taken (io_resp_f1_3_taken_0), .io_resp_f1_3_is_br (io_resp_f1_3_is_br_0), .io_resp_f1_3_is_jal (io_resp_f1_3_is_jal_0), .io_resp_f1_3_predicted_pc_valid (io_resp_f1_3_predicted_pc_valid_0), .io_resp_f1_3_predicted_pc_bits (io_resp_f1_3_predicted_pc_bits_0), .io_resp_f2_0_taken (io_resp_f2_0_taken_0), .io_resp_f2_0_is_br (io_resp_f2_0_is_br_0), .io_resp_f2_0_is_jal (io_resp_f2_0_is_jal_0), .io_resp_f2_0_predicted_pc_valid (io_resp_f2_0_predicted_pc_valid_0), .io_resp_f2_0_predicted_pc_bits (io_resp_f2_0_predicted_pc_bits_0), .io_resp_f2_1_taken (io_resp_f2_1_taken_0), .io_resp_f2_1_is_br (io_resp_f2_1_is_br_0), .io_resp_f2_1_is_jal (io_resp_f2_1_is_jal_0), .io_resp_f2_1_predicted_pc_valid (io_resp_f2_1_predicted_pc_valid_0), .io_resp_f2_1_predicted_pc_bits (io_resp_f2_1_predicted_pc_bits_0), .io_resp_f2_2_taken (io_resp_f2_2_taken_0), .io_resp_f2_2_is_br (io_resp_f2_2_is_br_0), .io_resp_f2_2_is_jal (io_resp_f2_2_is_jal_0), .io_resp_f2_2_predicted_pc_valid (io_resp_f2_2_predicted_pc_valid_0), .io_resp_f2_2_predicted_pc_bits (io_resp_f2_2_predicted_pc_bits_0), .io_resp_f2_3_taken (io_resp_f2_3_taken_0), .io_resp_f2_3_is_br (io_resp_f2_3_is_br_0), .io_resp_f2_3_is_jal (io_resp_f2_3_is_jal_0), .io_resp_f2_3_predicted_pc_valid (io_resp_f2_3_predicted_pc_valid_0), .io_resp_f2_3_predicted_pc_bits (io_resp_f2_3_predicted_pc_bits_0), .io_resp_f3_0_taken (io_resp_f3_0_taken_0), .io_resp_f3_0_is_br (io_resp_f3_0_is_br_0), .io_resp_f3_0_is_jal (io_resp_f3_0_is_jal_0), .io_resp_f3_0_predicted_pc_valid (io_resp_f3_0_predicted_pc_valid_0), .io_resp_f3_0_predicted_pc_bits (io_resp_f3_0_predicted_pc_bits_0), .io_resp_f3_1_taken (io_resp_f3_1_taken_0), .io_resp_f3_1_is_br (io_resp_f3_1_is_br_0), .io_resp_f3_1_is_jal (io_resp_f3_1_is_jal_0), .io_resp_f3_1_predicted_pc_valid (io_resp_f3_1_predicted_pc_valid_0), .io_resp_f3_1_predicted_pc_bits (io_resp_f3_1_predicted_pc_bits_0), .io_resp_f3_2_taken (io_resp_f3_2_taken_0), .io_resp_f3_2_is_br (io_resp_f3_2_is_br_0), .io_resp_f3_2_is_jal (io_resp_f3_2_is_jal_0), .io_resp_f3_2_predicted_pc_valid (io_resp_f3_2_predicted_pc_valid_0), .io_resp_f3_2_predicted_pc_bits (io_resp_f3_2_predicted_pc_bits_0), .io_resp_f3_3_taken (io_resp_f3_3_taken_0), .io_resp_f3_3_is_br (io_resp_f3_3_is_br_0), .io_resp_f3_3_is_jal (io_resp_f3_3_is_jal_0), .io_resp_f3_3_predicted_pc_valid (io_resp_f3_3_predicted_pc_valid_0), .io_resp_f3_3_predicted_pc_bits (io_resp_f3_3_predicted_pc_bits_0), .io_f3_meta (_loop_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({73'h0, io_update_bits_meta_0[119:73]}) // @[composer.scala:14:7, :42:27, :43:31] ); // @[config-mixins.scala:445:26] TageBranchPredictorBank_1 tage ( // @[config-mixins.scala:446:26] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_btb_io_resp_f1_0_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_is_br (_btb_io_resp_f1_0_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_is_jal (_btb_io_resp_f1_0_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_taken (_btb_io_resp_f1_1_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_is_br (_btb_io_resp_f1_1_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_is_jal (_btb_io_resp_f1_1_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_taken (_btb_io_resp_f1_2_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_is_br (_btb_io_resp_f1_2_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_is_jal (_btb_io_resp_f1_2_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_taken (_btb_io_resp_f1_3_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_is_br (_btb_io_resp_f1_3_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_is_jal (_btb_io_resp_f1_3_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_taken (_btb_io_resp_f2_0_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_is_br (_btb_io_resp_f2_0_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_is_jal (_btb_io_resp_f2_0_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_taken (_btb_io_resp_f2_1_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_is_br (_btb_io_resp_f2_1_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_is_jal (_btb_io_resp_f2_1_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_taken (_btb_io_resp_f2_2_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_is_br (_btb_io_resp_f2_2_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_is_jal (_btb_io_resp_f2_2_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_taken (_btb_io_resp_f2_3_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_is_br (_btb_io_resp_f2_3_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_is_jal (_btb_io_resp_f2_3_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_taken (_btb_io_resp_f3_0_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_is_br (_btb_io_resp_f3_0_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_is_jal (_btb_io_resp_f3_0_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_taken (_btb_io_resp_f3_1_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_is_br (_btb_io_resp_f3_1_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_is_jal (_btb_io_resp_f3_1_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_taken (_btb_io_resp_f3_2_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_is_br (_btb_io_resp_f3_2_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_is_jal (_btb_io_resp_f3_2_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_taken (_btb_io_resp_f3_3_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_is_br (_btb_io_resp_f3_3_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_is_jal (_btb_io_resp_f3_3_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_f1_0_taken (_tage_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_tage_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_tage_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_tage_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_tage_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_tage_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_tage_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_tage_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_tage_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_tage_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_tage_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_tage_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_tage_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_tage_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_tage_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_tage_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_tage_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_tage_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_tage_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_tage_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_tage_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_tage_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_tage_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_tage_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_tage_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_tage_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_tage_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_tage_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_tage_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_tage_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_tage_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_tage_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_tage_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_tage_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_tage_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_tage_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_tage_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({17'h0, io_update_bits_meta_0[119:17]}) // @[composer.scala:14:7, :42:27, :43:31] ); // @[config-mixins.scala:446:26] BTBBranchPredictorBank_1 btb ( // @[config-mixins.scala:447:25] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_bim_io_resp_f1_0_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_is_br (_bim_io_resp_f1_0_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_is_jal (_bim_io_resp_f1_0_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_taken (_bim_io_resp_f1_1_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_is_br (_bim_io_resp_f1_1_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_is_jal (_bim_io_resp_f1_1_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_taken (_bim_io_resp_f1_2_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_is_br (_bim_io_resp_f1_2_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_is_jal (_bim_io_resp_f1_2_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_taken (_bim_io_resp_f1_3_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_is_br (_bim_io_resp_f1_3_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_is_jal (_bim_io_resp_f1_3_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_taken (_bim_io_resp_f2_0_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_is_br (_bim_io_resp_f2_0_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_is_jal (_bim_io_resp_f2_0_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_taken (_bim_io_resp_f2_1_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_is_br (_bim_io_resp_f2_1_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_is_jal (_bim_io_resp_f2_1_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_taken (_bim_io_resp_f2_2_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_is_br (_bim_io_resp_f2_2_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_is_jal (_bim_io_resp_f2_2_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_taken (_bim_io_resp_f2_3_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_is_br (_bim_io_resp_f2_3_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_is_jal (_bim_io_resp_f2_3_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_taken (_bim_io_resp_f3_0_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_is_br (_bim_io_resp_f3_0_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_is_jal (_bim_io_resp_f3_0_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_taken (_bim_io_resp_f3_1_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_is_br (_bim_io_resp_f3_1_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_is_jal (_bim_io_resp_f3_1_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_taken (_bim_io_resp_f3_2_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_is_br (_bim_io_resp_f3_2_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_is_jal (_bim_io_resp_f3_2_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_taken (_bim_io_resp_f3_3_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_is_br (_bim_io_resp_f3_3_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_is_jal (_bim_io_resp_f3_3_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_f1_0_taken (_btb_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_btb_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_btb_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_btb_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_btb_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_btb_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_btb_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_btb_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_btb_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_btb_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_btb_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_btb_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_btb_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_btb_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_btb_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_btb_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_btb_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_btb_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_btb_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_btb_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_btb_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_btb_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_btb_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_btb_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_btb_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_btb_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_btb_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_btb_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_btb_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_btb_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_btb_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_btb_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_btb_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_btb_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_btb_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_btb_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_btb_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({16'h0, io_update_bits_meta_0[119:16]}) // @[composer.scala:14:7, :42:27, :43:31] ); // @[config-mixins.scala:447:25] BIMBranchPredictorBank_1 bim ( // @[config-mixins.scala:448:25] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_ubtb_io_resp_f1_0_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_is_br (_ubtb_io_resp_f1_0_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_taken (_ubtb_io_resp_f1_1_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_is_br (_ubtb_io_resp_f1_1_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_taken (_ubtb_io_resp_f1_2_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_is_br (_ubtb_io_resp_f1_2_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_taken (_ubtb_io_resp_f1_3_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_is_br (_ubtb_io_resp_f1_3_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_taken (_ubtb_io_resp_f2_0_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_is_br (_ubtb_io_resp_f2_0_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_taken (_ubtb_io_resp_f2_1_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_is_br (_ubtb_io_resp_f2_1_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_taken (_ubtb_io_resp_f2_2_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_is_br (_ubtb_io_resp_f2_2_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_taken (_ubtb_io_resp_f2_3_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_is_br (_ubtb_io_resp_f2_3_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_taken (_ubtb_io_resp_f3_0_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_is_br (_ubtb_io_resp_f3_0_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_taken (_ubtb_io_resp_f3_1_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_is_br (_ubtb_io_resp_f3_1_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_taken (_ubtb_io_resp_f3_2_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_is_br (_ubtb_io_resp_f3_2_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_taken (_ubtb_io_resp_f3_3_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_is_br (_ubtb_io_resp_f3_3_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_f1_0_taken (_bim_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_bim_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_bim_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_bim_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_bim_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_bim_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_bim_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_bim_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_bim_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_bim_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_bim_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_bim_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_bim_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_bim_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_bim_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_bim_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_bim_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_bim_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_bim_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_bim_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_bim_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_bim_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_bim_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_bim_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_bim_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_bim_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_bim_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_bim_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_bim_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_bim_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_bim_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_bim_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_bim_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_bim_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_bim_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_bim_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_bim_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta (io_update_bits_meta_0) // @[composer.scala:14:7] ); // @[config-mixins.scala:448:25] FAMicroBTBBranchPredictorBank_1 ubtb ( // @[config-mixins.scala:449:26] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_f1_0_taken (_ubtb_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_ubtb_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_ubtb_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_ubtb_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_ubtb_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_ubtb_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_ubtb_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_ubtb_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_ubtb_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_ubtb_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_ubtb_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_ubtb_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_ubtb_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_ubtb_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_ubtb_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_ubtb_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_ubtb_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_ubtb_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_ubtb_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_ubtb_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_ubtb_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_ubtb_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_ubtb_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_ubtb_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_ubtb_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({8'h0, io_update_bits_meta_0[119:8]}) // @[composer.scala:14:7, :31:22, :42:27, :43:31] ); // @[config-mixins.scala:449:26] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[composer.scala:14:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[composer.scala:14:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[composer.scala:14:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[composer.scala:14:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[composer.scala:14:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[composer.scala:14:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[composer.scala:14:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[composer.scala:14:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[composer.scala:14:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[composer.scala:14:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[composer.scala:14:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[composer.scala:14:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_f3_meta = io_f3_meta_0; // @[composer.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid \|\| io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }	module PriorityQueueStage_122( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_EntryData_28( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn \|\| noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }	module TLNoC_router_1ClockSinkDomain( // @[ClockDomain.scala:14:9] output [3:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_1 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready), .auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload), .auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready), .auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail), .auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload), .auto_ingress_nodes_in_2_flit_ready (auto_routers_ingress_nodes_in_2_flit_ready), .auto_ingress_nodes_in_2_flit_valid (auto_routers_ingress_nodes_in_2_flit_valid), .auto_ingress_nodes_in_2_flit_bits_head (auto_routers_ingress_nodes_in_2_flit_bits_head), .auto_ingress_nodes_in_2_flit_bits_payload (auto_routers_ingress_nodes_in_2_flit_bits_payload), .auto_ingress_nodes_in_2_flit_bits_egress_id (auto_routers_ingress_nodes_in_2_flit_bits_egress_id), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) \| wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /* @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File BTB.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.HasCoreParameters import freechips.rocketchip.util._ case class BHTParams( nEntries: Int = 512, counterLength: Int = 1, historyLength: Int = 8, historyBits: Int = 3) case class BTBParams( nEntries: Int = 28, nMatchBits: Int = 14, nPages: Int = 6, nRAS: Int = 6, bhtParams: Option[BHTParams] = Some(BHTParams()), updatesOutOfOrder: Boolean = false) trait HasBtbParameters extends HasCoreParameters { this: InstanceId => val btbParams = tileParams.btb.getOrElse(BTBParams(nEntries = 0)) val matchBits = btbParams.nMatchBits max log2Ceil(p(CacheBlockBytes) tileParams.icache.get.nSets) val entries = btbParams.nEntries val updatesOutOfOrder = btbParams.updatesOutOfOrder val nPages = (btbParams.nPages + 1) / 2 * 2 // control logic assumes 2 divides pages } abstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters { Annotated.params(this, btbParams) } abstract class BtbBundle(implicit val p: Parameters) extends Bundle with HasBtbParameters class RAS(nras: Int) { def push(addr: UInt): Unit = { when (count < nras.U) { count := count + 1.U } val nextPos = Mux((isPow2(nras)).B \|\| pos < (nras-1).U, pos+1.U, 0.U) stack(nextPos) := addr pos := nextPos } def peek: UInt = stack(pos) def pop(): Unit = when (!isEmpty) { count := count - 1.U pos := Mux((isPow2(nras)).B \|\| pos > 0.U, pos-1.U, (nras-1).U) } def clear(): Unit = count := 0.U def isEmpty: Bool = count === 0.U private val count = RegInit(0.U(log2Up(nras+1).W)) private val pos = RegInit(0.U(log2Up(nras).W)) private val stack = Reg(Vec(nras, UInt())) } class BHTResp(implicit p: Parameters) extends BtbBundle()(p) { val history = UInt(btbParams.bhtParams.map(_.historyLength).getOrElse(1).W) val value = UInt(btbParams.bhtParams.map(_.counterLength).getOrElse(1).W) def taken = value(0) def strongly_taken = value === 1.U } // BHT contains table of 2-bit counters and a global history register. // The BHT only predicts and updates when there is a BTB hit. // The global history: // - updated speculatively in fetch (if there's a BTB hit). // - on a mispredict, the history register is reset (again, only if BTB hit). // The counter table: // - each counter corresponds with the address of the fetch packet ("fetch pc"). // - updated when a branch resolves (and BTB was a hit for that branch). // The updating branch must provide its "fetch pc". class BHT(params: BHTParams)(implicit val p: Parameters) extends HasCoreParameters { def index(addr: UInt, history: UInt) = { def hashHistory(hist: UInt) = if (params.historyLength == params.historyBits) hist else { val k = math.sqrt(3)/2 val i = BigDecimal(k * math.pow(2, params.historyLength)).toBigInt (i.U * hist)(params.historyLength-1, params.historyLength-params.historyBits) } def hashAddr(addr: UInt) = { val hi = addr >> log2Ceil(fetchBytes) hi(log2Ceil(params.nEntries)-1, 0) ^ (hi >> log2Ceil(params.nEntries))(1, 0) } hashAddr(addr) ^ (hashHistory(history) << (log2Up(params.nEntries) - params.historyBits)) } def get(addr: UInt): BHTResp = { val res = Wire(new BHTResp) res.value := Mux(resetting, 0.U, table(index(addr, history))) res.history := history res } def updateTable(addr: UInt, d: BHTResp, taken: Bool): Unit = { wen := true.B when (!resetting) { waddr := index(addr, d.history) wdata := (params.counterLength match { case 1 => taken case 2 => Cat(taken ^ d.value(0), d.value === 1.U \|\| d.value(1) && taken) }) } } def resetHistory(d: BHTResp): Unit = { history := d.history } def updateHistory(addr: UInt, d: BHTResp, taken: Bool): Unit = { history := Cat(taken, d.history >> 1) } def advanceHistory(taken: Bool): Unit = { history := Cat(taken, history >> 1) } private val table = Mem(params.nEntries, UInt(params.counterLength.W)) val history = RegInit(0.U(params.historyLength.W)) private val reset_waddr = RegInit(0.U((params.nEntries.log2+1).W)) private val resetting = !reset_waddr(params.nEntries.log2) private val wen = WireInit(resetting) private val waddr = WireInit(reset_waddr) private val wdata = WireInit(0.U) when (resetting) { reset_waddr := reset_waddr + 1.U } when (wen) { table(waddr) := wdata } } object CFIType { def SZ = 2 def apply() = UInt(SZ.W) def branch = 0.U def jump = 1.U def call = 2.U def ret = 3.U } // BTB update occurs during branch resolution (and only on a mispredict). // - "pc" is what future fetch PCs will tag match against. // - "br_pc" is the PC of the branch instruction. class BTBUpdate(implicit p: Parameters) extends BtbBundle()(p) { val prediction = new BTBResp val pc = UInt(vaddrBits.W) val target = UInt(vaddrBits.W) val taken = Bool() val isValid = Bool() val br_pc = UInt(vaddrBits.W) val cfiType = CFIType() } // BHT update occurs during branch resolution on all conditional branches. // - "pc" is what future fetch PCs will tag match against. class BHTUpdate(implicit p: Parameters) extends BtbBundle()(p) { val prediction = new BHTResp val pc = UInt(vaddrBits.W) val branch = Bool() val taken = Bool() val mispredict = Bool() } class RASUpdate(implicit p: Parameters) extends BtbBundle()(p) { val cfiType = CFIType() val returnAddr = UInt(vaddrBits.W) } // - "bridx" is the low-order PC bits of the predicted branch (after // shifting off the lowest log(inst_bytes) bits off). // - "mask" provides a mask of valid instructions (instructions are // masked off by the predicted taken branch from the BTB). class BTBResp(implicit p: Parameters) extends BtbBundle()(p) { val cfiType = CFIType() val taken = Bool() val mask = Bits(fetchWidth.W) val bridx = Bits(log2Up(fetchWidth).W) val target = UInt(vaddrBits.W) val entry = UInt(log2Up(entries + 1).W) val bht = new BHTResp } class BTBReq(implicit p: Parameters) extends BtbBundle()(p) { val addr = UInt(vaddrBits.W) } // fully-associative branch target buffer // Higher-performance processors may cause BTB updates to occur out-of-order, // which requires an extra CAM port for updates (to ensure no duplicates get // placed in BTB). class BTB(implicit p: Parameters) extends BtbModule { val io = IO(new Bundle { val req = Flipped(Valid(new BTBReq)) val resp = Valid(new BTBResp) val btb_update = Flipped(Valid(new BTBUpdate)) val bht_update = Flipped(Valid(new BHTUpdate)) val bht_advance = Flipped(Valid(new BTBResp)) val ras_update = Flipped(Valid(new RASUpdate)) val ras_head = Valid(UInt(vaddrBits.W)) val flush = Input(Bool()) }) val idxs = Reg(Vec(entries, UInt((matchBits - log2Up(coreInstBytes)).W))) val idxPages = Reg(Vec(entries, UInt(log2Up(nPages).W))) val tgts = Reg(Vec(entries, UInt((matchBits - log2Up(coreInstBytes)).W))) val tgtPages = Reg(Vec(entries, UInt(log2Up(nPages).W))) val pages = Reg(Vec(nPages, UInt((vaddrBits - matchBits).W))) val pageValid = RegInit(0.U(nPages.W)) val pagesMasked = (pageValid.asBools zip pages).map { case (v, p) => Mux(v, p, 0.U) } val isValid = RegInit(0.U(entries.W)) val cfiType = Reg(Vec(entries, CFIType())) val brIdx = Reg(Vec(entries, UInt(log2Up(fetchWidth).W))) private def page(addr: UInt) = addr >> matchBits private def pageMatch(addr: UInt) = { val p = page(addr) pageValid & pages.map(_ === p).asUInt } private def idxMatch(addr: UInt) = { val idx = addr(matchBits-1, log2Up(coreInstBytes)) idxs.map(_ === idx).asUInt & isValid } val r_btb_update = Pipe(io.btb_update) val update_target = io.req.bits.addr val pageHit = pageMatch(io.req.bits.addr) val idxHit = idxMatch(io.req.bits.addr) val updatePageHit = pageMatch(r_btb_update.bits.pc) val (updateHit, updateHitAddr) = if (updatesOutOfOrder) { val updateHits = (pageHit << 1)(Mux1H(idxMatch(r_btb_update.bits.pc), idxPages)) (updateHits.orR, OHToUInt(updateHits)) } else (r_btb_update.bits.prediction.entry < entries.U, r_btb_update.bits.prediction.entry) val useUpdatePageHit = updatePageHit.orR val usePageHit = pageHit.orR val doIdxPageRepl = !useUpdatePageHit val nextPageRepl = RegInit(0.U(log2Ceil(nPages).W)) val idxPageRepl = Cat(pageHit(nPages-2,0), pageHit(nPages-1)) \| Mux(usePageHit, 0.U, UIntToOH(nextPageRepl)) val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl) val idxPageUpdate = OHToUInt(idxPageUpdateOH) val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, 0.U) val samePage = page(r_btb_update.bits.pc) === page(update_target) val doTgtPageRepl = !samePage && !usePageHit val tgtPageRepl = Mux(samePage, idxPageUpdateOH, Cat(idxPageUpdateOH(nPages-2,0), idxPageUpdateOH(nPages-1))) val tgtPageUpdate = OHToUInt(pageHit \| Mux(usePageHit, 0.U, tgtPageRepl)) val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, 0.U) when (r_btb_update.valid && (doIdxPageRepl \|\| doTgtPageRepl)) { val both = doIdxPageRepl && doTgtPageRepl val next = nextPageRepl + Mux[UInt](both, 2.U, 1.U) nextPageRepl := Mux(next >= nPages.U, next(0), next) } val repl = new PseudoLRU(entries) val waddr = Mux(updateHit, updateHitAddr, repl.way) val r_resp = Pipe(io.resp) when (r_resp.valid && r_resp.bits.taken \|\| r_btb_update.valid) { repl.access(Mux(r_btb_update.valid, waddr, r_resp.bits.entry)) } when (r_btb_update.valid) { val mask = UIntToOH(waddr) idxs(waddr) := r_btb_update.bits.pc(matchBits-1, log2Up(coreInstBytes)) tgts(waddr) := update_target(matchBits-1, log2Up(coreInstBytes)) idxPages(waddr) := idxPageUpdate +& 1.U // the +1 corresponds to the <<1 on io.resp.valid tgtPages(waddr) := tgtPageUpdate cfiType(waddr) := r_btb_update.bits.cfiType isValid := Mux(r_btb_update.bits.isValid, isValid \| mask, isValid & ~mask) if (fetchWidth > 1) brIdx(waddr) := r_btb_update.bits.br_pc >> log2Up(coreInstBytes) require(nPages % 2 == 0) val idxWritesEven = !idxPageUpdate(0) def writeBank(i: Int, mod: Int, en: UInt, data: UInt) = for (i <- i until nPages by mod) when (en(i)) { pages(i) := data } writeBank(0, 2, Mux(idxWritesEven, idxPageReplEn, tgtPageReplEn), Mux(idxWritesEven, page(r_btb_update.bits.pc), page(update_target))) writeBank(1, 2, Mux(idxWritesEven, tgtPageReplEn, idxPageReplEn), Mux(idxWritesEven, page(update_target), page(r_btb_update.bits.pc))) pageValid := pageValid \| tgtPageReplEn \| idxPageReplEn } io.resp.valid := (pageHit << 1)(Mux1H(idxHit, idxPages)) io.resp.bits.taken := true.B io.resp.bits.target := Cat(pagesMasked(Mux1H(idxHit, tgtPages)), Mux1H(idxHit, tgts) << log2Up(coreInstBytes)) io.resp.bits.entry := OHToUInt(idxHit) io.resp.bits.bridx := (if (fetchWidth > 1) Mux1H(idxHit, brIdx) else 0.U) io.resp.bits.mask := Cat((1.U << ~Mux(io.resp.bits.taken, ~io.resp.bits.bridx, 0.U))-1.U, 1.U) io.resp.bits.cfiType := Mux1H(idxHit, cfiType) // if multiple entries for same PC land in BTB, zap them when (PopCountAtLeast(idxHit, 2)) { isValid := isValid & ~idxHit } when (io.flush) { isValid := 0.U } if (btbParams.bhtParams.nonEmpty) { val bht = new BHT(Annotated.params(this, btbParams.bhtParams.get)) val isBranch = (idxHit & cfiType.map(_ === CFIType.branch).asUInt).orR val res = bht.get(io.req.bits.addr) when (io.bht_advance.valid) { bht.advanceHistory(io.bht_advance.bits.bht.taken) } when (io.bht_update.valid) { when (io.bht_update.bits.branch) { bht.updateTable(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken) when (io.bht_update.bits.mispredict) { bht.updateHistory(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken) } }.elsewhen (io.bht_update.bits.mispredict) { bht.resetHistory(io.bht_update.bits.prediction) } } when (!res.taken && isBranch) { io.resp.bits.taken := false.B } io.resp.bits.bht := res } if (btbParams.nRAS > 0) { val ras = new RAS(btbParams.nRAS) val doPeek = (idxHit & cfiType.map(_ === CFIType.ret).asUInt).orR io.ras_head.valid := !ras.isEmpty io.ras_head.bits := ras.peek when (!ras.isEmpty && doPeek) { io.resp.bits.target := ras.peek } when (io.ras_update.valid) { when (io.ras_update.bits.cfiType === CFIType.call) { ras.push(io.ras_update.bits.returnAddr) }.elsewhen (io.ras_update.bits.cfiType === CFIType.ret) { ras.pop() } } } }	module BTB_4( // @[BTB.scala:187:7] input clock, // @[BTB.scala:187:7] input reset, // @[BTB.scala:187:7] input io_req_valid, // @[BTB.scala:188:14] input [38:0] io_req_bits_addr, // @[BTB.scala:188:14] output io_resp_valid, // @[BTB.scala:188:14] output [1:0] io_resp_bits_cfiType, // @[BTB.scala:188:14] output io_resp_bits_taken, // @[BTB.scala:188:14] output [1:0] io_resp_bits_mask, // @[BTB.scala:188:14] output io_resp_bits_bridx, // @[BTB.scala:188:14] output [38:0] io_resp_bits_target, // @[BTB.scala:188:14] output [4:0] io_resp_bits_entry, // @[BTB.scala:188:14] output [7:0] io_resp_bits_bht_history, // @[BTB.scala:188:14] output io_resp_bits_bht_value, // @[BTB.scala:188:14] input io_btb_update_valid, // @[BTB.scala:188:14] input [1:0] io_btb_update_bits_prediction_cfiType, // @[BTB.scala:188:14] input io_btb_update_bits_prediction_taken, // @[BTB.scala:188:14] input [1:0] io_btb_update_bits_prediction_mask, // @[BTB.scala:188:14] input io_btb_update_bits_prediction_bridx, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_prediction_target, // @[BTB.scala:188:14] input [4:0] io_btb_update_bits_prediction_entry, // @[BTB.scala:188:14] input [7:0] io_btb_update_bits_prediction_bht_history, // @[BTB.scala:188:14] input io_btb_update_bits_prediction_bht_value, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_pc, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_target, // @[BTB.scala:188:14] input io_btb_update_bits_isValid, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_br_pc, // @[BTB.scala:188:14] input [1:0] io_btb_update_bits_cfiType, // @[BTB.scala:188:14] input io_bht_update_valid, // @[BTB.scala:188:14] input [7:0] io_bht_update_bits_prediction_history, // @[BTB.scala:188:14] input io_bht_update_bits_prediction_value, // @[BTB.scala:188:14] input [38:0] io_bht_update_bits_pc, // @[BTB.scala:188:14] input io_bht_update_bits_branch, // @[BTB.scala:188:14] input io_bht_update_bits_taken, // @[BTB.scala:188:14] input io_bht_update_bits_mispredict, // @[BTB.scala:188:14] input io_bht_advance_valid, // @[BTB.scala:188:14] input [1:0] io_bht_advance_bits_cfiType, // @[BTB.scala:188:14] input io_bht_advance_bits_taken, // @[BTB.scala:188:14] input [1:0] io_bht_advance_bits_mask, // @[BTB.scala:188:14] input io_bht_advance_bits_bridx, // @[BTB.scala:188:14] input [38:0] io_bht_advance_bits_target, // @[BTB.scala:188:14] input [4:0] io_bht_advance_bits_entry, // @[BTB.scala:188:14] input [7:0] io_bht_advance_bits_bht_history, // @[BTB.scala:188:14] input io_bht_advance_bits_bht_value, // @[BTB.scala:188:14] input io_ras_update_valid, // @[BTB.scala:188:14] input [1:0] io_ras_update_bits_cfiType, // @[BTB.scala:188:14] input [38:0] io_ras_update_bits_returnAddr, // @[BTB.scala:188:14] output io_ras_head_valid, // @[BTB.scala:188:14] output [38:0] io_ras_head_bits, // @[BTB.scala:188:14] input io_flush // @[BTB.scala:188:14] ); wire _table_ext_R0_data; // @[BTB.scala:116:26] wire io_req_valid_0 = io_req_valid; // @[BTB.scala:187:7] wire [38:0] io_req_bits_addr_0 = io_req_bits_addr; // @[BTB.scala:187:7] wire io_btb_update_valid_0 = io_btb_update_valid; // @[BTB.scala:187:7] wire [1:0] io_btb_update_bits_prediction_cfiType_0 = io_btb_update_bits_prediction_cfiType; // @[BTB.scala:187:7] wire io_btb_update_bits_prediction_taken_0 = io_btb_update_bits_prediction_taken; // @[BTB.scala:187:7] wire [1:0] io_btb_update_bits_prediction_mask_0 = io_btb_update_bits_prediction_mask; // @[BTB.scala:187:7] wire io_btb_update_bits_prediction_bridx_0 = io_btb_update_bits_prediction_bridx; // @[BTB.scala:187:7] wire [38:0] io_btb_update_bits_prediction_target_0 = io_btb_update_bits_prediction_target; // @[BTB.scala:187:7] wire [4:0] io_btb_update_bits_prediction_entry_0 = io_btb_update_bits_prediction_entry; // @[BTB.scala:187:7] wire [7:0] io_btb_update_bits_prediction_bht_history_0 = io_btb_update_bits_prediction_bht_history; // @[BTB.scala:187:7] wire io_btb_update_bits_prediction_bht_value_0 = io_btb_update_bits_prediction_bht_value; // @[BTB.scala:187:7] wire [38:0] io_btb_update_bits_pc_0 = io_btb_update_bits_pc; // @[BTB.scala:187:7] wire [38:0] io_btb_update_bits_target_0 = io_btb_update_bits_target; // @[BTB.scala:187:7] wire io_btb_update_bits_isValid_0 = io_btb_update_bits_isValid; // @[BTB.scala:187:7] wire [38:0] io_btb_update_bits_br_pc_0 = io_btb_update_bits_br_pc; // @[BTB.scala:187:7] wire [1:0] io_btb_update_bits_cfiType_0 = io_btb_update_bits_cfiType; // @[BTB.scala:187:7] wire io_bht_update_valid_0 = io_bht_update_valid; // @[BTB.scala:187:7] wire [7:0] io_bht_update_bits_prediction_history_0 = io_bht_update_bits_prediction_history; // @[BTB.scala:187:7] wire io_bht_update_bits_prediction_value_0 = io_bht_update_bits_prediction_value; // @[BTB.scala:187:7] wire [38:0] io_bht_update_bits_pc_0 = io_bht_update_bits_pc; // @[BTB.scala:187:7] wire io_bht_update_bits_branch_0 = io_bht_update_bits_branch; // @[BTB.scala:187:7] wire io_bht_update_bits_taken_0 = io_bht_update_bits_taken; // @[BTB.scala:187:7] wire io_bht_update_bits_mispredict_0 = io_bht_update_bits_mispredict; // @[BTB.scala:187:7] wire io_bht_advance_valid_0 = io_bht_advance_valid; // @[BTB.scala:187:7] wire [1:0] io_bht_advance_bits_cfiType_0 = io_bht_advance_bits_cfiType; // @[BTB.scala:187:7] wire io_bht_advance_bits_taken_0 = io_bht_advance_bits_taken; // @[BTB.scala:187:7] wire [1:0] io_bht_advance_bits_mask_0 = io_bht_advance_bits_mask; // @[BTB.scala:187:7] wire io_bht_advance_bits_bridx_0 = io_bht_advance_bits_bridx; // @[BTB.scala:187:7] wire [38:0] io_bht_advance_bits_target_0 = io_bht_advance_bits_target; // @[BTB.scala:187:7] wire [4:0] io_bht_advance_bits_entry_0 = io_bht_advance_bits_entry; // @[BTB.scala:187:7] wire [7:0] io_bht_advance_bits_bht_history_0 = io_bht_advance_bits_bht_history; // @[BTB.scala:187:7] wire io_bht_advance_bits_bht_value_0 = io_bht_advance_bits_bht_value; // @[BTB.scala:187:7] wire io_ras_update_valid_0 = io_ras_update_valid; // @[BTB.scala:187:7] wire [1:0] io_ras_update_bits_cfiType_0 = io_ras_update_bits_cfiType; // @[BTB.scala:187:7] wire [38:0] io_ras_update_bits_returnAddr_0 = io_ras_update_bits_returnAddr; // @[BTB.scala:187:7] wire io_flush_0 = io_flush; // @[BTB.scala:187:7] wire io_btb_update_bits_taken = 1'h0; // @[BTB.scala:187:7] wire r_btb_update_bits_taken = 1'h0; // @[Valid.scala:135:21] wire _io_resp_valid_T_85; // @[BTB.scala:287:34] wire [1:0] _io_resp_bits_cfiType_WIRE; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_WIRE; // @[Mux.scala:30:73] wire [4:0] _io_resp_bits_entry_T_12; // @[OneHot.scala:32:10] wire [7:0] res_history; // @[BTB.scala:91:19] wire res_value; // @[BTB.scala:91:19] wire _io_ras_head_valid_T_1; // @[BTB.scala:327:26] wire [7:0] io_resp_bits_bht_history_0; // @[BTB.scala:187:7] wire io_resp_bits_bht_value_0; // @[BTB.scala:187:7] wire [1:0] io_resp_bits_cfiType_0; // @[BTB.scala:187:7] wire io_resp_bits_taken_0; // @[BTB.scala:187:7] wire [1:0] io_resp_bits_mask_0; // @[BTB.scala:187:7] wire io_resp_bits_bridx_0; // @[BTB.scala:187:7] wire [38:0] io_resp_bits_target_0; // @[BTB.scala:187:7] wire [4:0] io_resp_bits_entry_0; // @[BTB.scala:187:7] wire io_resp_valid_0; // @[BTB.scala:187:7] wire io_ras_head_valid_0; // @[BTB.scala:187:7] wire [38:0] io_ras_head_bits_0; // @[BTB.scala:187:7] reg [12:0] idxs_0; // @[BTB.scala:199:17] reg [12:0] idxs_1; // @[BTB.scala:199:17] reg [12:0] idxs_2; // @[BTB.scala:199:17] reg [12:0] idxs_3; // @[BTB.scala:199:17] reg [12:0] idxs_4; // @[BTB.scala:199:17] reg [12:0] idxs_5; // @[BTB.scala:199:17] reg [12:0] idxs_6; // @[BTB.scala:199:17] reg [12:0] idxs_7; // @[BTB.scala:199:17] reg [12:0] idxs_8; // @[BTB.scala:199:17] reg [12:0] idxs_9; // @[BTB.scala:199:17] reg [12:0] idxs_10; // @[BTB.scala:199:17] reg [12:0] idxs_11; // @[BTB.scala:199:17] reg [12:0] idxs_12; // @[BTB.scala:199:17] reg [12:0] idxs_13; // @[BTB.scala:199:17] reg [12:0] idxs_14; // @[BTB.scala:199:17] reg [12:0] idxs_15; // @[BTB.scala:199:17] reg [12:0] idxs_16; // @[BTB.scala:199:17] reg [12:0] idxs_17; // @[BTB.scala:199:17] reg [12:0] idxs_18; // @[BTB.scala:199:17] reg [12:0] idxs_19; // @[BTB.scala:199:17] reg [12:0] idxs_20; // @[BTB.scala:199:17] reg [12:0] idxs_21; // @[BTB.scala:199:17] reg [12:0] idxs_22; // @[BTB.scala:199:17] reg [12:0] idxs_23; // @[BTB.scala:199:17] reg [12:0] idxs_24; // @[BTB.scala:199:17] reg [12:0] idxs_25; // @[BTB.scala:199:17] reg [12:0] idxs_26; // @[BTB.scala:199:17] reg [12:0] idxs_27; // @[BTB.scala:199:17] reg [2:0] idxPages_0; // @[BTB.scala:200:21] reg [2:0] idxPages_1; // @[BTB.scala:200:21] reg [2:0] idxPages_2; // @[BTB.scala:200:21] reg [2:0] idxPages_3; // @[BTB.scala:200:21] reg [2:0] idxPages_4; // @[BTB.scala:200:21] reg [2:0] idxPages_5; // @[BTB.scala:200:21] reg [2:0] idxPages_6; // @[BTB.scala:200:21] reg [2:0] idxPages_7; // @[BTB.scala:200:21] reg [2:0] idxPages_8; // @[BTB.scala:200:21] reg [2:0] idxPages_9; // @[BTB.scala:200:21] reg [2:0] idxPages_10; // @[BTB.scala:200:21] reg [2:0] idxPages_11; // @[BTB.scala:200:21] reg [2:0] idxPages_12; // @[BTB.scala:200:21] reg [2:0] idxPages_13; // @[BTB.scala:200:21] reg [2:0] idxPages_14; // @[BTB.scala:200:21] reg [2:0] idxPages_15; // @[BTB.scala:200:21] reg [2:0] idxPages_16; // @[BTB.scala:200:21] reg [2:0] idxPages_17; // @[BTB.scala:200:21] reg [2:0] idxPages_18; // @[BTB.scala:200:21] reg [2:0] idxPages_19; // @[BTB.scala:200:21] reg [2:0] idxPages_20; // @[BTB.scala:200:21] reg [2:0] idxPages_21; // @[BTB.scala:200:21] reg [2:0] idxPages_22; // @[BTB.scala:200:21] reg [2:0] idxPages_23; // @[BTB.scala:200:21] reg [2:0] idxPages_24; // @[BTB.scala:200:21] reg [2:0] idxPages_25; // @[BTB.scala:200:21] reg [2:0] idxPages_26; // @[BTB.scala:200:21] reg [2:0] idxPages_27; // @[BTB.scala:200:21] reg [12:0] tgts_0; // @[BTB.scala:201:17] reg [12:0] tgts_1; // @[BTB.scala:201:17] reg [12:0] tgts_2; // @[BTB.scala:201:17] reg [12:0] tgts_3; // @[BTB.scala:201:17] reg [12:0] tgts_4; // @[BTB.scala:201:17] reg [12:0] tgts_5; // @[BTB.scala:201:17] reg [12:0] tgts_6; // @[BTB.scala:201:17] reg [12:0] tgts_7; // @[BTB.scala:201:17] reg [12:0] tgts_8; // @[BTB.scala:201:17] reg [12:0] tgts_9; // @[BTB.scala:201:17] reg [12:0] tgts_10; // @[BTB.scala:201:17] reg [12:0] tgts_11; // @[BTB.scala:201:17] reg [12:0] tgts_12; // @[BTB.scala:201:17] reg [12:0] tgts_13; // @[BTB.scala:201:17] reg [12:0] tgts_14; // @[BTB.scala:201:17] reg [12:0] tgts_15; // @[BTB.scala:201:17] reg [12:0] tgts_16; // @[BTB.scala:201:17] reg [12:0] tgts_17; // @[BTB.scala:201:17] reg [12:0] tgts_18; // @[BTB.scala:201:17] reg [12:0] tgts_19; // @[BTB.scala:201:17] reg [12:0] tgts_20; // @[BTB.scala:201:17] reg [12:0] tgts_21; // @[BTB.scala:201:17] reg [12:0] tgts_22; // @[BTB.scala:201:17] reg [12:0] tgts_23; // @[BTB.scala:201:17] reg [12:0] tgts_24; // @[BTB.scala:201:17] reg [12:0] tgts_25; // @[BTB.scala:201:17] reg [12:0] tgts_26; // @[BTB.scala:201:17] reg [12:0] tgts_27; // @[BTB.scala:201:17] reg [2:0] tgtPages_0; // @[BTB.scala:202:21] reg [2:0] tgtPages_1; // @[BTB.scala:202:21] reg [2:0] tgtPages_2; // @[BTB.scala:202:21] reg [2:0] tgtPages_3; // @[BTB.scala:202:21] reg [2:0] tgtPages_4; // @[BTB.scala:202:21] reg [2:0] tgtPages_5; // @[BTB.scala:202:21] reg [2:0] tgtPages_6; // @[BTB.scala:202:21] reg [2:0] tgtPages_7; // @[BTB.scala:202:21] reg [2:0] tgtPages_8; // @[BTB.scala:202:21] reg [2:0] tgtPages_9; // @[BTB.scala:202:21] reg [2:0] tgtPages_10; // @[BTB.scala:202:21] reg [2:0] tgtPages_11; // @[BTB.scala:202:21] reg [2:0] tgtPages_12; // @[BTB.scala:202:21] reg [2:0] tgtPages_13; // @[BTB.scala:202:21] reg [2:0] tgtPages_14; // @[BTB.scala:202:21] reg [2:0] tgtPages_15; // @[BTB.scala:202:21] reg [2:0] tgtPages_16; // @[BTB.scala:202:21] reg [2:0] tgtPages_17; // @[BTB.scala:202:21] reg [2:0] tgtPages_18; // @[BTB.scala:202:21] reg [2:0] tgtPages_19; // @[BTB.scala:202:21] reg [2:0] tgtPages_20; // @[BTB.scala:202:21] reg [2:0] tgtPages_21; // @[BTB.scala:202:21] reg [2:0] tgtPages_22; // @[BTB.scala:202:21] reg [2:0] tgtPages_23; // @[BTB.scala:202:21] reg [2:0] tgtPages_24; // @[BTB.scala:202:21] reg [2:0] tgtPages_25; // @[BTB.scala:202:21] reg [2:0] tgtPages_26; // @[BTB.scala:202:21] reg [2:0] tgtPages_27; // @[BTB.scala:202:21] reg [24:0] pages_0; // @[BTB.scala:203:18] reg [24:0] pages_1; // @[BTB.scala:203:18] reg [24:0] pages_2; // @[BTB.scala:203:18] reg [24:0] pages_3; // @[BTB.scala:203:18] reg [24:0] pages_4; // @[BTB.scala:203:18] reg [24:0] pages_5; // @[BTB.scala:203:18] reg [5:0] pageValid; // @[BTB.scala:204:26] wire _pagesMasked_T = pageValid[0]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_1 = pageValid[1]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_2 = pageValid[2]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_3 = pageValid[3]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_4 = pageValid[4]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_5 = pageValid[5]; // @[BTB.scala:204:26, :205:32] wire [24:0] pagesMasked_0 = _pagesMasked_T ? pages_0 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_1 = _pagesMasked_T_1 ? pages_1 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_2 = _pagesMasked_T_2 ? pages_2 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_3 = _pagesMasked_T_3 ? pages_3 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_4 = _pagesMasked_T_4 ? pages_4 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_5 = _pagesMasked_T_5 ? pages_5 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] reg [27:0] isValid; // @[BTB.scala:207:24] reg [1:0] cfiType_0; // @[BTB.scala:208:20] reg [1:0] cfiType_1; // @[BTB.scala:208:20] reg [1:0] cfiType_2; // @[BTB.scala:208:20] reg [1:0] cfiType_3; // @[BTB.scala:208:20] reg [1:0] cfiType_4; // @[BTB.scala:208:20] reg [1:0] cfiType_5; // @[BTB.scala:208:20] reg [1:0] cfiType_6; // @[BTB.scala:208:20] reg [1:0] cfiType_7; // @[BTB.scala:208:20] reg [1:0] cfiType_8; // @[BTB.scala:208:20] reg [1:0] cfiType_9; // @[BTB.scala:208:20] reg [1:0] cfiType_10; // @[BTB.scala:208:20] reg [1:0] cfiType_11; // @[BTB.scala:208:20] reg [1:0] cfiType_12; // @[BTB.scala:208:20] reg [1:0] cfiType_13; // @[BTB.scala:208:20] reg [1:0] cfiType_14; // @[BTB.scala:208:20] reg [1:0] cfiType_15; // @[BTB.scala:208:20] reg [1:0] cfiType_16; // @[BTB.scala:208:20] reg [1:0] cfiType_17; // @[BTB.scala:208:20] reg [1:0] cfiType_18; // @[BTB.scala:208:20] reg [1:0] cfiType_19; // @[BTB.scala:208:20] reg [1:0] cfiType_20; // @[BTB.scala:208:20] reg [1:0] cfiType_21; // @[BTB.scala:208:20] reg [1:0] cfiType_22; // @[BTB.scala:208:20] reg [1:0] cfiType_23; // @[BTB.scala:208:20] reg [1:0] cfiType_24; // @[BTB.scala:208:20] reg [1:0] cfiType_25; // @[BTB.scala:208:20] reg [1:0] cfiType_26; // @[BTB.scala:208:20] reg [1:0] cfiType_27; // @[BTB.scala:208:20] reg brIdx_0; // @[BTB.scala:209:18] reg brIdx_1; // @[BTB.scala:209:18] reg brIdx_2; // @[BTB.scala:209:18] reg brIdx_3; // @[BTB.scala:209:18] reg brIdx_4; // @[BTB.scala:209:18] reg brIdx_5; // @[BTB.scala:209:18] reg brIdx_6; // @[BTB.scala:209:18] reg brIdx_7; // @[BTB.scala:209:18] reg brIdx_8; // @[BTB.scala:209:18] reg brIdx_9; // @[BTB.scala:209:18] reg brIdx_10; // @[BTB.scala:209:18] reg brIdx_11; // @[BTB.scala:209:18] reg brIdx_12; // @[BTB.scala:209:18] reg brIdx_13; // @[BTB.scala:209:18] reg brIdx_14; // @[BTB.scala:209:18] reg brIdx_15; // @[BTB.scala:209:18] reg brIdx_16; // @[BTB.scala:209:18] reg brIdx_17; // @[BTB.scala:209:18] reg brIdx_18; // @[BTB.scala:209:18] reg brIdx_19; // @[BTB.scala:209:18] reg brIdx_20; // @[BTB.scala:209:18] reg brIdx_21; // @[BTB.scala:209:18] reg brIdx_22; // @[BTB.scala:209:18] reg brIdx_23; // @[BTB.scala:209:18] reg brIdx_24; // @[BTB.scala:209:18] reg brIdx_25; // @[BTB.scala:209:18] reg brIdx_26; // @[BTB.scala:209:18] reg brIdx_27; // @[BTB.scala:209:18] reg r_btb_update_pipe_v; // @[Valid.scala:141:24] wire r_btb_update_valid = r_btb_update_pipe_v; // @[Valid.scala:135:21, :141:24] reg [1:0] r_btb_update_pipe_b_prediction_cfiType; // @[Valid.scala:142:26] wire [1:0] r_btb_update_bits_prediction_cfiType = r_btb_update_pipe_b_prediction_cfiType; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_prediction_taken; // @[Valid.scala:142:26] wire r_btb_update_bits_prediction_taken = r_btb_update_pipe_b_prediction_taken; // @[Valid.scala:135:21, :142:26] reg [1:0] r_btb_update_pipe_b_prediction_mask; // @[Valid.scala:142:26] wire [1:0] r_btb_update_bits_prediction_mask = r_btb_update_pipe_b_prediction_mask; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_prediction_bridx; // @[Valid.scala:142:26] wire r_btb_update_bits_prediction_bridx = r_btb_update_pipe_b_prediction_bridx; // @[Valid.scala:135:21, :142:26] reg [38:0] r_btb_update_pipe_b_prediction_target; // @[Valid.scala:142:26] wire [38:0] r_btb_update_bits_prediction_target = r_btb_update_pipe_b_prediction_target; // @[Valid.scala:135:21, :142:26] reg [4:0] r_btb_update_pipe_b_prediction_entry; // @[Valid.scala:142:26] wire [4:0] r_btb_update_bits_prediction_entry = r_btb_update_pipe_b_prediction_entry; // @[Valid.scala:135:21, :142:26] reg [7:0] r_btb_update_pipe_b_prediction_bht_history; // @[Valid.scala:142:26] wire [7:0] r_btb_update_bits_prediction_bht_history = r_btb_update_pipe_b_prediction_bht_history; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_prediction_bht_value; // @[Valid.scala:142:26] wire r_btb_update_bits_prediction_bht_value = r_btb_update_pipe_b_prediction_bht_value; // @[Valid.scala:135:21, :142:26] reg [38:0] r_btb_update_pipe_b_pc; // @[Valid.scala:142:26] wire [38:0] r_btb_update_bits_pc = r_btb_update_pipe_b_pc; // @[Valid.scala:135:21, :142:26] reg [38:0] r_btb_update_pipe_b_target; // @[Valid.scala:142:26] wire [38:0] r_btb_update_bits_target = r_btb_update_pipe_b_target; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_isValid; // @[Valid.scala:142:26] wire r_btb_update_bits_isValid = r_btb_update_pipe_b_isValid; // @[Valid.scala:135:21, :142:26] reg [38:0] r_btb_update_pipe_b_br_pc; // @[Valid.scala:142:26] wire [38:0] r_btb_update_bits_br_pc = r_btb_update_pipe_b_br_pc; // @[Valid.scala:135:21, :142:26] reg [1:0] r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] wire [1:0] r_btb_update_bits_cfiType = r_btb_update_pipe_b_cfiType; // @[Valid.scala:135:21, :142:26] wire [24:0] pageHit_p = io_req_bits_addr_0[38:14]; // @[BTB.scala:187:7, :211:39] wire [24:0] _samePage_T_1 = io_req_bits_addr_0[38:14]; // @[BTB.scala:187:7, :211:39] wire _pageHit_T = pages_0 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_1 = pages_1 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_2 = pages_2 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_3 = pages_3 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_4 = pages_4 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_5 = pages_5 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire [1:0] pageHit_lo_hi = {_pageHit_T_2, _pageHit_T_1}; // @[package.scala:45:27] wire [2:0] pageHit_lo = {pageHit_lo_hi, _pageHit_T}; // @[package.scala:45:27] wire [1:0] pageHit_hi_hi = {_pageHit_T_5, _pageHit_T_4}; // @[package.scala:45:27] wire [2:0] pageHit_hi = {pageHit_hi_hi, _pageHit_T_3}; // @[package.scala:45:27] wire [5:0] _pageHit_T_6 = {pageHit_hi, pageHit_lo}; // @[package.scala:45:27] wire [5:0] pageHit = pageValid & _pageHit_T_6; // @[package.scala:45:27] wire [12:0] idxHit_idx = io_req_bits_addr_0[13:1]; // @[BTB.scala:187:7, :217:19] wire [12:0] _tgts_T = io_req_bits_addr_0[13:1]; // @[BTB.scala:187:7, :217:19, :265:33] wire _idxHit_T = idxs_0 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_1 = idxs_1 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_2 = idxs_2 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_3 = idxs_3 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_4 = idxs_4 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_5 = idxs_5 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_6 = idxs_6 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_7 = idxs_7 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_8 = idxs_8 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_9 = idxs_9 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_10 = idxs_10 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_11 = idxs_11 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_12 = idxs_12 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_13 = idxs_13 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_14 = idxs_14 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_15 = idxs_15 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_16 = idxs_16 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_17 = idxs_17 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_18 = idxs_18 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_19 = idxs_19 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_20 = idxs_20 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_21 = idxs_21 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_22 = idxs_22 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_23 = idxs_23 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_24 = idxs_24 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_25 = idxs_25 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_26 = idxs_26 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_27 = idxs_27 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire [1:0] idxHit_lo_lo_lo_hi = {_idxHit_T_2, _idxHit_T_1}; // @[package.scala:45:27] wire [2:0] idxHit_lo_lo_lo = {idxHit_lo_lo_lo_hi, _idxHit_T}; // @[package.scala:45:27] wire [1:0] idxHit_lo_lo_hi_lo = {_idxHit_T_4, _idxHit_T_3}; // @[package.scala:45:27] wire [1:0] idxHit_lo_lo_hi_hi = {_idxHit_T_6, _idxHit_T_5}; // @[package.scala:45:27] wire [3:0] idxHit_lo_lo_hi = {idxHit_lo_lo_hi_hi, idxHit_lo_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_lo_lo = {idxHit_lo_lo_hi, idxHit_lo_lo_lo}; // @[package.scala:45:27] wire [1:0] idxHit_lo_hi_lo_hi = {_idxHit_T_9, _idxHit_T_8}; // @[package.scala:45:27] wire [2:0] idxHit_lo_hi_lo = {idxHit_lo_hi_lo_hi, _idxHit_T_7}; // @[package.scala:45:27] wire [1:0] idxHit_lo_hi_hi_lo = {_idxHit_T_11, _idxHit_T_10}; // @[package.scala:45:27] wire [1:0] idxHit_lo_hi_hi_hi = {_idxHit_T_13, _idxHit_T_12}; // @[package.scala:45:27] wire [3:0] idxHit_lo_hi_hi = {idxHit_lo_hi_hi_hi, idxHit_lo_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_lo_hi = {idxHit_lo_hi_hi, idxHit_lo_hi_lo}; // @[package.scala:45:27] wire [13:0] idxHit_lo = {idxHit_lo_hi, idxHit_lo_lo}; // @[package.scala:45:27] wire [1:0] idxHit_hi_lo_lo_hi = {_idxHit_T_16, _idxHit_T_15}; // @[package.scala:45:27] wire [2:0] idxHit_hi_lo_lo = {idxHit_hi_lo_lo_hi, _idxHit_T_14}; // @[package.scala:45:27] wire [1:0] idxHit_hi_lo_hi_lo = {_idxHit_T_18, _idxHit_T_17}; // @[package.scala:45:27] wire [1:0] idxHit_hi_lo_hi_hi = {_idxHit_T_20, _idxHit_T_19}; // @[package.scala:45:27] wire [3:0] idxHit_hi_lo_hi = {idxHit_hi_lo_hi_hi, idxHit_hi_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_hi_lo = {idxHit_hi_lo_hi, idxHit_hi_lo_lo}; // @[package.scala:45:27] wire [1:0] idxHit_hi_hi_lo_hi = {_idxHit_T_23, _idxHit_T_22}; // @[package.scala:45:27] wire [2:0] idxHit_hi_hi_lo = {idxHit_hi_hi_lo_hi, _idxHit_T_21}; // @[package.scala:45:27] wire [1:0] idxHit_hi_hi_hi_lo = {_idxHit_T_25, _idxHit_T_24}; // @[package.scala:45:27] wire [1:0] idxHit_hi_hi_hi_hi = {_idxHit_T_27, _idxHit_T_26}; // @[package.scala:45:27] wire [3:0] idxHit_hi_hi_hi = {idxHit_hi_hi_hi_hi, idxHit_hi_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_hi_hi = {idxHit_hi_hi_hi, idxHit_hi_hi_lo}; // @[package.scala:45:27] wire [13:0] idxHit_hi = {idxHit_hi_hi, idxHit_hi_lo}; // @[package.scala:45:27] wire [27:0] _idxHit_T_28 = {idxHit_hi, idxHit_lo}; // @[package.scala:45:27] wire [27:0] idxHit = _idxHit_T_28 & isValid; // @[package.scala:45:27] wire [24:0] updatePageHit_p = r_btb_update_bits_pc[38:14]; // @[Valid.scala:135:21] wire [24:0] _samePage_T = r_btb_update_bits_pc[38:14]; // @[Valid.scala:135:21] wire _updatePageHit_T = pages_0 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_1 = pages_1 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_2 = pages_2 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_3 = pages_3 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_4 = pages_4 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_5 = pages_5 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire [1:0] updatePageHit_lo_hi = {_updatePageHit_T_2, _updatePageHit_T_1}; // @[package.scala:45:27] wire [2:0] updatePageHit_lo = {updatePageHit_lo_hi, _updatePageHit_T}; // @[package.scala:45:27] wire [1:0] updatePageHit_hi_hi = {_updatePageHit_T_5, _updatePageHit_T_4}; // @[package.scala:45:27] wire [2:0] updatePageHit_hi = {updatePageHit_hi_hi, _updatePageHit_T_3}; // @[package.scala:45:27] wire [5:0] _updatePageHit_T_6 = {updatePageHit_hi, updatePageHit_lo}; // @[package.scala:45:27] wire [5:0] updatePageHit = pageValid & _updatePageHit_T_6; // @[package.scala:45:27] wire updateHit = r_btb_update_bits_prediction_entry[4:2] != 3'h7; // @[Valid.scala:135:21] wire useUpdatePageHit = \|updatePageHit; // @[BTB.scala:214:15, :234:40] wire usePageHit = \|pageHit; // @[BTB.scala:214:15, :235:28] wire doIdxPageRepl = ~useUpdatePageHit; // @[BTB.scala:234:40, :236:23] reg [2:0] nextPageRepl; // @[BTB.scala:237:29] wire [4:0] _idxPageRepl_T = pageHit[4:0]; // @[BTB.scala:214:15, :238:32] wire _idxPageRepl_T_1 = pageHit[5]; // @[BTB.scala:214:15, :238:53] wire [5:0] _idxPageRepl_T_2 = {_idxPageRepl_T, _idxPageRepl_T_1}; // @[BTB.scala:238:{24,32,53}] wire [7:0] _idxPageRepl_T_3 = 8'h1 << nextPageRepl; // @[OneHot.scala:58:35] wire [7:0] _idxPageRepl_T_4 = usePageHit ? 8'h0 : _idxPageRepl_T_3; // @[OneHot.scala:58:35] wire [7:0] idxPageRepl = {2'h0, _idxPageRepl_T_2} \| _idxPageRepl_T_4; // @[BTB.scala:238:{24,65,70}] wire [7:0] idxPageUpdateOH = useUpdatePageHit ? {2'h0, updatePageHit} : idxPageRepl; // @[BTB.scala:214:15, :234:40, :238:65, :239:28] wire [3:0] idxPageUpdate_hi = idxPageUpdateOH[7:4]; // @[OneHot.scala:30:18] wire [3:0] idxPageUpdate_lo = idxPageUpdateOH[3:0]; // @[OneHot.scala:31:18] wire _idxPageUpdate_T = \|idxPageUpdate_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _idxPageUpdate_T_1 = idxPageUpdate_hi \| idxPageUpdate_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] idxPageUpdate_hi_1 = _idxPageUpdate_T_1[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] idxPageUpdate_lo_1 = _idxPageUpdate_T_1[1:0]; // @[OneHot.scala:31:18, :32:28] wire _idxPageUpdate_T_2 = \|idxPageUpdate_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _idxPageUpdate_T_3 = idxPageUpdate_hi_1 \| idxPageUpdate_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _idxPageUpdate_T_4 = _idxPageUpdate_T_3[1]; // @[OneHot.scala:32:28] wire [1:0] _idxPageUpdate_T_5 = {_idxPageUpdate_T_2, _idxPageUpdate_T_4}; // @[OneHot.scala:32:{10,14}] wire [2:0] idxPageUpdate = {_idxPageUpdate_T, _idxPageUpdate_T_5}; // @[OneHot.scala:32:{10,14}] wire [7:0] idxPageReplEn = doIdxPageRepl ? idxPageRepl : 8'h0; // @[BTB.scala:236:23, :238:65, :241:26] wire samePage = _samePage_T == _samePage_T_1; // @[BTB.scala:211:39, :243:45] wire _doTgtPageRepl_T = ~samePage; // @[BTB.scala:243:45, :244:23] wire _doTgtPageRepl_T_1 = ~usePageHit; // @[BTB.scala:235:28, :244:36] wire doTgtPageRepl = _doTgtPageRepl_T & _doTgtPageRepl_T_1; // @[BTB.scala:244:{23,33,36}] wire [4:0] _tgtPageRepl_T = idxPageUpdateOH[4:0]; // @[BTB.scala:239:28, :245:71] wire _tgtPageRepl_T_1 = idxPageUpdateOH[5]; // @[BTB.scala:239:28, :245:100] wire [5:0] _tgtPageRepl_T_2 = {_tgtPageRepl_T, _tgtPageRepl_T_1}; // @[BTB.scala:245:{55,71,100}] wire [7:0] tgtPageRepl = samePage ? idxPageUpdateOH : {2'h0, _tgtPageRepl_T_2}; // @[BTB.scala:239:28, :243:45, :245:{24,55}] wire [7:0] _tgtPageUpdate_T = usePageHit ? 8'h0 : tgtPageRepl; // @[BTB.scala:235:28, :245:24, :246:45] wire [7:0] _tgtPageUpdate_T_1 = {2'h0, pageHit} \| _tgtPageUpdate_T; // @[BTB.scala:214:15, :246:{40,45}] wire [3:0] tgtPageUpdate_hi = _tgtPageUpdate_T_1[7:4]; // @[OneHot.scala:30:18] wire [3:0] tgtPageUpdate_lo = _tgtPageUpdate_T_1[3:0]; // @[OneHot.scala:31:18] wire _tgtPageUpdate_T_2 = \|tgtPageUpdate_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _tgtPageUpdate_T_3 = tgtPageUpdate_hi \| tgtPageUpdate_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] tgtPageUpdate_hi_1 = _tgtPageUpdate_T_3[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] tgtPageUpdate_lo_1 = _tgtPageUpdate_T_3[1:0]; // @[OneHot.scala:31:18, :32:28] wire _tgtPageUpdate_T_4 = \|tgtPageUpdate_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _tgtPageUpdate_T_5 = tgtPageUpdate_hi_1 \| tgtPageUpdate_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _tgtPageUpdate_T_6 = _tgtPageUpdate_T_5[1]; // @[OneHot.scala:32:28] wire [1:0] _tgtPageUpdate_T_7 = {_tgtPageUpdate_T_4, _tgtPageUpdate_T_6}; // @[OneHot.scala:32:{10,14}] wire [2:0] tgtPageUpdate = {_tgtPageUpdate_T_2, _tgtPageUpdate_T_7}; // @[OneHot.scala:32:{10,14}] wire [7:0] tgtPageReplEn = doTgtPageRepl ? tgtPageRepl : 8'h0; // @[BTB.scala:244:33, :245:24, :247:26] wire both = doIdxPageRepl & doTgtPageRepl; // @[BTB.scala:236:23, :244:33, :250:30] wire [1:0] _next_T = both ? 2'h2 : 2'h1; // @[BTB.scala:250:30, :251:40, :292:33] wire [3:0] _next_T_1 = {1'h0, nextPageRepl} + {2'h0, _next_T}; // @[BTB.scala:237:29, :251:{29,40}] wire [2:0] next = _next_T_1[2:0]; // @[BTB.scala:251:29] wire _nextPageRepl_T = next > 3'h5; // @[BTB.scala:251:29, :252:30] wire _nextPageRepl_T_1 = next[0]; // @[BTB.scala:251:29, :252:47] wire [2:0] _nextPageRepl_T_2 = _nextPageRepl_T ? {2'h0, _nextPageRepl_T_1} : next; // @[BTB.scala:251:29, :252:{24,30,47}] reg [26:0] state_reg; // @[Replacement.scala:168:70] wire waddr_left_subtree_older = state_reg[26]; // @[Replacement.scala:168:70, :243:38] wire [10:0] waddr_left_subtree_state = state_reg[25:15]; // @[package.scala:163:13] wire [10:0] state_reg_left_subtree_state = state_reg[25:15]; // @[package.scala:163:13] wire [14:0] waddr_right_subtree_state = state_reg[14:0]; // @[Replacement.scala:168:70, :245:38] wire [14:0] state_reg_right_subtree_state = state_reg[14:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire waddr_left_subtree_older_1 = waddr_left_subtree_state[10]; // @[package.scala:163:13] wire [2:0] waddr_left_subtree_state_1 = waddr_left_subtree_state[9:7]; // @[package.scala:163:13] wire [6:0] waddr_right_subtree_state_1 = waddr_left_subtree_state[6:0]; // @[package.scala:163:13] wire waddr_left_subtree_older_2 = waddr_left_subtree_state_1[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_2 = waddr_left_subtree_state_1[1]; // @[package.scala:163:13] wire _waddr_T = waddr_left_subtree_state_2; // @[package.scala:163:13] wire waddr_right_subtree_state_2 = waddr_left_subtree_state_1[0]; // @[package.scala:163:13] wire _waddr_T_1 = waddr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_2 = waddr_left_subtree_older_2 ? _waddr_T : _waddr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_3 = {waddr_left_subtree_older_2, _waddr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_3 = waddr_right_subtree_state_1[6]; // @[Replacement.scala:243:38, :245:38] wire [2:0] waddr_left_subtree_state_3 = waddr_right_subtree_state_1[5:3]; // @[package.scala:163:13] wire [2:0] waddr_right_subtree_state_3 = waddr_right_subtree_state_1[2:0]; // @[Replacement.scala:245:38] wire waddr_left_subtree_older_4 = waddr_left_subtree_state_3[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_4 = waddr_left_subtree_state_3[1]; // @[package.scala:163:13] wire _waddr_T_4 = waddr_left_subtree_state_4; // @[package.scala:163:13] wire waddr_right_subtree_state_4 = waddr_left_subtree_state_3[0]; // @[package.scala:163:13] wire _waddr_T_5 = waddr_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_6 = waddr_left_subtree_older_4 ? _waddr_T_4 : _waddr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_7 = {waddr_left_subtree_older_4, _waddr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_5 = waddr_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38] wire waddr_left_subtree_state_5 = waddr_right_subtree_state_3[1]; // @[package.scala:163:13] wire _waddr_T_8 = waddr_left_subtree_state_5; // @[package.scala:163:13] wire waddr_right_subtree_state_5 = waddr_right_subtree_state_3[0]; // @[Replacement.scala:245:38] wire _waddr_T_9 = waddr_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_10 = waddr_left_subtree_older_5 ? _waddr_T_8 : _waddr_T_9; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_11 = {waddr_left_subtree_older_5, _waddr_T_10}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _waddr_T_12 = waddr_left_subtree_older_3 ? _waddr_T_7 : _waddr_T_11; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_13 = {waddr_left_subtree_older_3, _waddr_T_12}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_14 = waddr_left_subtree_older_1 ? {1'h0, _waddr_T_3} : _waddr_T_13; // @[Replacement.scala:243:38, :249:12, :250:16] wire [3:0] _waddr_T_15 = {waddr_left_subtree_older_1, _waddr_T_14}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_6 = waddr_right_subtree_state[14]; // @[Replacement.scala:243:38, :245:38] wire [6:0] waddr_left_subtree_state_6 = waddr_right_subtree_state[13:7]; // @[package.scala:163:13] wire [6:0] waddr_right_subtree_state_6 = waddr_right_subtree_state[6:0]; // @[Replacement.scala:245:38] wire waddr_left_subtree_older_7 = waddr_left_subtree_state_6[6]; // @[package.scala:163:13] wire [2:0] waddr_left_subtree_state_7 = waddr_left_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] waddr_right_subtree_state_7 = waddr_left_subtree_state_6[2:0]; // @[package.scala:163:13] wire waddr_left_subtree_older_8 = waddr_left_subtree_state_7[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_8 = waddr_left_subtree_state_7[1]; // @[package.scala:163:13] wire _waddr_T_16 = waddr_left_subtree_state_8; // @[package.scala:163:13] wire waddr_right_subtree_state_8 = waddr_left_subtree_state_7[0]; // @[package.scala:163:13] wire _waddr_T_17 = waddr_right_subtree_state_8; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_18 = waddr_left_subtree_older_8 ? _waddr_T_16 : _waddr_T_17; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_19 = {waddr_left_subtree_older_8, _waddr_T_18}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_9 = waddr_right_subtree_state_7[2]; // @[Replacement.scala:243:38, :245:38] wire waddr_left_subtree_state_9 = waddr_right_subtree_state_7[1]; // @[package.scala:163:13] wire _waddr_T_20 = waddr_left_subtree_state_9; // @[package.scala:163:13] wire waddr_right_subtree_state_9 = waddr_right_subtree_state_7[0]; // @[Replacement.scala:245:38] wire _waddr_T_21 = waddr_right_subtree_state_9; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_22 = waddr_left_subtree_older_9 ? _waddr_T_20 : _waddr_T_21; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_23 = {waddr_left_subtree_older_9, _waddr_T_22}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _waddr_T_24 = waddr_left_subtree_older_7 ? _waddr_T_19 : _waddr_T_23; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_25 = {waddr_left_subtree_older_7, _waddr_T_24}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_10 = waddr_right_subtree_state_6[6]; // @[Replacement.scala:243:38, :245:38] wire [2:0] waddr_left_subtree_state_10 = waddr_right_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] waddr_right_subtree_state_10 = waddr_right_subtree_state_6[2:0]; // @[Replacement.scala:245:38] wire waddr_left_subtree_older_11 = waddr_left_subtree_state_10[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_11 = waddr_left_subtree_state_10[1]; // @[package.scala:163:13] wire _waddr_T_26 = waddr_left_subtree_state_11; // @[package.scala:163:13] wire waddr_right_subtree_state_11 = waddr_left_subtree_state_10[0]; // @[package.scala:163:13] wire _waddr_T_27 = waddr_right_subtree_state_11; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_28 = waddr_left_subtree_older_11 ? _waddr_T_26 : _waddr_T_27; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_29 = {waddr_left_subtree_older_11, _waddr_T_28}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_12 = waddr_right_subtree_state_10[2]; // @[Replacement.scala:243:38, :245:38] wire waddr_left_subtree_state_12 = waddr_right_subtree_state_10[1]; // @[package.scala:163:13] wire _waddr_T_30 = waddr_left_subtree_state_12; // @[package.scala:163:13] wire waddr_right_subtree_state_12 = waddr_right_subtree_state_10[0]; // @[Replacement.scala:245:38] wire _waddr_T_31 = waddr_right_subtree_state_12; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_32 = waddr_left_subtree_older_12 ? _waddr_T_30 : _waddr_T_31; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_33 = {waddr_left_subtree_older_12, _waddr_T_32}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _waddr_T_34 = waddr_left_subtree_older_10 ? _waddr_T_29 : _waddr_T_33; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_35 = {waddr_left_subtree_older_10, _waddr_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_36 = waddr_left_subtree_older_6 ? _waddr_T_25 : _waddr_T_35; // @[Replacement.scala:243:38, :249:12, :250:16] wire [3:0] _waddr_T_37 = {waddr_left_subtree_older_6, _waddr_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [3:0] _waddr_T_38 = waddr_left_subtree_older ? _waddr_T_15 : _waddr_T_37; // @[Replacement.scala:243:38, :249:12, :250:16] wire [4:0] _waddr_T_39 = {waddr_left_subtree_older, _waddr_T_38}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [4:0] waddr = updateHit ? r_btb_update_bits_prediction_entry : _waddr_T_39; // @[Valid.scala:135:21] reg r_resp_pipe_v; // @[Valid.scala:141:24] wire r_resp_valid = r_resp_pipe_v; // @[Valid.scala:135:21, :141:24] reg [1:0] r_resp_pipe_b_cfiType; // @[Valid.scala:142:26] wire [1:0] r_resp_bits_cfiType = r_resp_pipe_b_cfiType; // @[Valid.scala:135:21, :142:26] reg r_resp_pipe_b_taken; // @[Valid.scala:142:26] wire r_resp_bits_taken = r_resp_pipe_b_taken; // @[Valid.scala:135:21, :142:26] reg [1:0] r_resp_pipe_b_mask; // @[Valid.scala:142:26] wire [1:0] r_resp_bits_mask = r_resp_pipe_b_mask; // @[Valid.scala:135:21, :142:26] reg r_resp_pipe_b_bridx; // @[Valid.scala:142:26] wire r_resp_bits_bridx = r_resp_pipe_b_bridx; // @[Valid.scala:135:21, :142:26] reg [38:0] r_resp_pipe_b_target; // @[Valid.scala:142:26] wire [38:0] r_resp_bits_target = r_resp_pipe_b_target; // @[Valid.scala:135:21, :142:26] reg [4:0] r_resp_pipe_b_entry; // @[Valid.scala:142:26] wire [4:0] r_resp_bits_entry = r_resp_pipe_b_entry; // @[Valid.scala:135:21, :142:26] reg [7:0] r_resp_pipe_b_bht_history; // @[Valid.scala:142:26] wire [7:0] r_resp_bits_bht_history = r_resp_pipe_b_bht_history; // @[Valid.scala:135:21, :142:26] reg r_resp_pipe_b_bht_value; // @[Valid.scala:142:26] wire r_resp_bits_bht_value = r_resp_pipe_b_bht_value; // @[Valid.scala:135:21, :142:26] wire [4:0] state_reg_touch_way_sized = r_btb_update_valid ? waddr : r_resp_bits_entry; // @[Valid.scala:135:21] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[4]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [3:0] _state_reg_T = state_reg_touch_way_sized[3:0]; // @[package.scala:163:13] wire [3:0] _state_reg_T_39 = state_reg_touch_way_sized[3:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_1 = _state_reg_T[3]; // @[package.scala:163:13] wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_1 = state_reg_left_subtree_state[9:7]; // @[package.scala:163:13] wire [6:0] state_reg_right_subtree_state_1 = state_reg_left_subtree_state[6:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_1 = _state_reg_T[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_2 = _state_reg_T_1[1]; // @[package.scala:163:13] wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_2 = state_reg_left_subtree_state_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_2 = state_reg_left_subtree_state_1[0]; // @[package.scala:163:13] wire _state_reg_T_2 = _state_reg_T_1[0]; // @[package.scala:163:13] wire _state_reg_T_6 = _state_reg_T_1[0]; // @[package.scala:163:13] wire _state_reg_T_3 = _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_4 = ~_state_reg_T_3; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_5 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_4; // @[package.scala:163:13] wire _state_reg_T_7 = _state_reg_T_6; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_8 = ~_state_reg_T_7; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_9 = state_reg_set_left_older_2 ? _state_reg_T_8 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older_2, _state_reg_T_5}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_10 = {state_reg_hi, _state_reg_T_9}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_11 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_10; // @[package.scala:163:13] wire [2:0] _state_reg_T_12 = _state_reg_T[2:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_3 = _state_reg_T_12[2]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_3 = state_reg_right_subtree_state_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state_3 = state_reg_right_subtree_state_1[2:0]; // @[Replacement.scala:198:38] wire [1:0] _state_reg_T_13 = _state_reg_T_12[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_24 = _state_reg_T_12[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_4 = _state_reg_T_13[1]; // @[package.scala:163:13] wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13] wire _state_reg_T_14 = _state_reg_T_13[0]; // @[package.scala:163:13] wire _state_reg_T_18 = _state_reg_T_13[0]; // @[package.scala:163:13] wire _state_reg_T_15 = _state_reg_T_14; // @[package.scala:163:13] wire _state_reg_T_16 = ~_state_reg_T_15; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_17 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_16; // @[package.scala:163:13] wire _state_reg_T_19 = _state_reg_T_18; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_20 = ~_state_reg_T_19; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_21 = state_reg_set_left_older_4 ? _state_reg_T_20 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_4, _state_reg_T_17}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_22 = {state_reg_hi_1, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_23 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_22; // @[package.scala:163:13] wire _state_reg_set_left_older_T_5 = _state_reg_T_24[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38] wire _state_reg_T_25 = _state_reg_T_24[0]; // @[package.scala:163:13] wire _state_reg_T_29 = _state_reg_T_24[0]; // @[package.scala:163:13] wire _state_reg_T_26 = _state_reg_T_25; // @[package.scala:163:13] wire _state_reg_T_27 = ~_state_reg_T_26; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_28 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_27; // @[package.scala:163:13] wire _state_reg_T_30 = _state_reg_T_29; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_31 = ~_state_reg_T_30; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_32 = state_reg_set_left_older_5 ? _state_reg_T_31 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_2 = {state_reg_set_left_older_5, _state_reg_T_28}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_33 = {state_reg_hi_2, _state_reg_T_32}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_34 = state_reg_set_left_older_3 ? _state_reg_T_33 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_3 = {state_reg_set_left_older_3, _state_reg_T_23}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_35 = {state_reg_hi_3, _state_reg_T_34}; // @[Replacement.scala:202:12, :206:16] wire [6:0] _state_reg_T_36 = state_reg_set_left_older_1 ? _state_reg_T_35 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_4 = {state_reg_set_left_older_1, _state_reg_T_11}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [10:0] _state_reg_T_37 = {state_reg_hi_4, _state_reg_T_36}; // @[Replacement.scala:202:12, :206:16] wire [10:0] _state_reg_T_38 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_37; // @[package.scala:163:13] wire _state_reg_set_left_older_T_6 = _state_reg_T_39[3]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}] wire [6:0] state_reg_left_subtree_state_6 = state_reg_right_subtree_state[13:7]; // @[package.scala:163:13] wire [6:0] state_reg_right_subtree_state_6 = state_reg_right_subtree_state[6:0]; // @[Replacement.scala:198:38] wire [2:0] _state_reg_T_40 = _state_reg_T_39[2:0]; // @[package.scala:163:13] wire [2:0] _state_reg_T_65 = _state_reg_T_39[2:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_7 = _state_reg_T_40[2]; // @[package.scala:163:13] wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[2:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_41 = _state_reg_T_40[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_52 = _state_reg_T_40[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_8 = _state_reg_T_41[1]; // @[package.scala:163:13] wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_8 = state_reg_left_subtree_state_7[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_8 = state_reg_left_subtree_state_7[0]; // @[package.scala:163:13] wire _state_reg_T_42 = _state_reg_T_41[0]; // @[package.scala:163:13] wire _state_reg_T_46 = _state_reg_T_41[0]; // @[package.scala:163:13] wire _state_reg_T_43 = _state_reg_T_42; // @[package.scala:163:13] wire _state_reg_T_44 = ~_state_reg_T_43; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_45 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_44; // @[package.scala:163:13] wire _state_reg_T_47 = _state_reg_T_46; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_48 = ~_state_reg_T_47; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_49 = state_reg_set_left_older_8 ? _state_reg_T_48 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_5 = {state_reg_set_left_older_8, _state_reg_T_45}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_50 = {state_reg_hi_5, _state_reg_T_49}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_51 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_50; // @[package.scala:163:13] wire _state_reg_set_left_older_T_9 = _state_reg_T_52[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_9 = ~_state_reg_set_left_older_T_9; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_9 = state_reg_right_subtree_state_7[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_9 = state_reg_right_subtree_state_7[0]; // @[Replacement.scala:198:38] wire _state_reg_T_53 = _state_reg_T_52[0]; // @[package.scala:163:13] wire _state_reg_T_57 = _state_reg_T_52[0]; // @[package.scala:163:13] wire _state_reg_T_54 = _state_reg_T_53; // @[package.scala:163:13] wire _state_reg_T_55 = ~_state_reg_T_54; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_56 = state_reg_set_left_older_9 ? state_reg_left_subtree_state_9 : _state_reg_T_55; // @[package.scala:163:13] wire _state_reg_T_58 = _state_reg_T_57; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_59 = ~_state_reg_T_58; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_60 = state_reg_set_left_older_9 ? _state_reg_T_59 : state_reg_right_subtree_state_9; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_9, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_61 = {state_reg_hi_6, _state_reg_T_60}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_62 = state_reg_set_left_older_7 ? _state_reg_T_61 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_7 = {state_reg_set_left_older_7, _state_reg_T_51}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_63 = {state_reg_hi_7, _state_reg_T_62}; // @[Replacement.scala:202:12, :206:16] wire [6:0] _state_reg_T_64 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_63; // @[package.scala:163:13] wire _state_reg_set_left_older_T_10 = _state_reg_T_65[2]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_10 = ~_state_reg_set_left_older_T_10; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_10 = state_reg_right_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state_10 = state_reg_right_subtree_state_6[2:0]; // @[Replacement.scala:198:38] wire [1:0] _state_reg_T_66 = _state_reg_T_65[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_77 = _state_reg_T_65[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_11 = _state_reg_T_66[1]; // @[package.scala:163:13] wire state_reg_set_left_older_11 = ~_state_reg_set_left_older_T_11; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_11 = state_reg_left_subtree_state_10[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_11 = state_reg_left_subtree_state_10[0]; // @[package.scala:163:13] wire _state_reg_T_67 = _state_reg_T_66[0]; // @[package.scala:163:13] wire _state_reg_T_71 = _state_reg_T_66[0]; // @[package.scala:163:13] wire _state_reg_T_68 = _state_reg_T_67; // @[package.scala:163:13] wire _state_reg_T_69 = ~_state_reg_T_68; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_70 = state_reg_set_left_older_11 ? state_reg_left_subtree_state_11 : _state_reg_T_69; // @[package.scala:163:13] wire _state_reg_T_72 = _state_reg_T_71; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_73 = ~_state_reg_T_72; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_74 = state_reg_set_left_older_11 ? _state_reg_T_73 : state_reg_right_subtree_state_11; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_8 = {state_reg_set_left_older_11, _state_reg_T_70}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_75 = {state_reg_hi_8, _state_reg_T_74}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_76 = state_reg_set_left_older_10 ? state_reg_left_subtree_state_10 : _state_reg_T_75; // @[package.scala:163:13] wire _state_reg_set_left_older_T_12 = _state_reg_T_77[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_12 = ~_state_reg_set_left_older_T_12; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_12 = state_reg_right_subtree_state_10[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_12 = state_reg_right_subtree_state_10[0]; // @[Replacement.scala:198:38] wire _state_reg_T_78 = _state_reg_T_77[0]; // @[package.scala:163:13] wire _state_reg_T_82 = _state_reg_T_77[0]; // @[package.scala:163:13] wire _state_reg_T_79 = _state_reg_T_78; // @[package.scala:163:13] wire _state_reg_T_80 = ~_state_reg_T_79; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_81 = state_reg_set_left_older_12 ? state_reg_left_subtree_state_12 : _state_reg_T_80; // @[package.scala:163:13] wire _state_reg_T_83 = _state_reg_T_82; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_84 = ~_state_reg_T_83; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_85 = state_reg_set_left_older_12 ? _state_reg_T_84 : state_reg_right_subtree_state_12; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_9 = {state_reg_set_left_older_12, _state_reg_T_81}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_86 = {state_reg_hi_9, _state_reg_T_85}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_87 = state_reg_set_left_older_10 ? _state_reg_T_86 : state_reg_right_subtree_state_10; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_10 = {state_reg_set_left_older_10, _state_reg_T_76}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_88 = {state_reg_hi_10, _state_reg_T_87}; // @[Replacement.scala:202:12, :206:16] wire [6:0] _state_reg_T_89 = state_reg_set_left_older_6 ? _state_reg_T_88 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [7:0] state_reg_hi_11 = {state_reg_set_left_older_6, _state_reg_T_64}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [14:0] _state_reg_T_90 = {state_reg_hi_11, _state_reg_T_89}; // @[Replacement.scala:202:12, :206:16] wire [14:0] _state_reg_T_91 = state_reg_set_left_older ? _state_reg_T_90 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [11:0] state_reg_hi_12 = {state_reg_set_left_older, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [26:0] _state_reg_T_92 = {state_reg_hi_12, _state_reg_T_91}; // @[Replacement.scala:202:12, :206:16] wire [31:0] mask = 32'h1 << waddr; // @[OneHot.scala:58:35] wire [12:0] _idxs_T = r_btb_update_bits_pc[13:1]; // @[Valid.scala:135:21] wire [3:0] _idxPages_T = {1'h0, idxPageUpdate} + 4'h1; // @[OneHot.scala:32:10] wire [31:0] _isValid_T = {4'h0, isValid} \| mask; // @[OneHot.scala:32:14, :58:35] wire [31:0] _isValid_T_1 = ~mask; // @[OneHot.scala:58:35] wire [31:0] _isValid_T_2 = {4'h0, _isValid_T_1[27:0] & isValid}; // @[OneHot.scala:32:14] wire [31:0] _isValid_T_3 = r_btb_update_bits_isValid ? _isValid_T : _isValid_T_2; // @[Valid.scala:135:21] wire [37:0] _brIdx_T = r_btb_update_bits_br_pc[38:1]; // @[Valid.scala:135:21] wire _idxWritesEven_T = idxPageUpdate[0]; // @[OneHot.scala:32:10] wire idxWritesEven = ~_idxWritesEven_T; // @[BTB.scala:274:{25,39}] wire [7:0] _pageValid_T = {2'h0, pageValid} \| tgtPageReplEn; // @[BTB.scala:204:26, :247:26, :284:28] wire [7:0] _pageValid_T_1 = _pageValid_T \| idxPageReplEn; // @[BTB.scala:241:26, :284:{28,44}] wire [6:0] _io_resp_valid_T = {pageHit, 1'h0}; // @[BTB.scala:214:15, :287:29] wire _io_resp_valid_T_1 = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_97 = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_valid_T_2 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_1 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_98 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_1 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_1 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_valid_T_3 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_2 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_99 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_2 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_2 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_valid_T_4 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_3 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_100 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_3 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_3 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_valid_T_5 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_4 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_101 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_4 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_4 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_valid_T_6 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_5 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_102 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_5 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_5 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_valid_T_7 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_6 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_103 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_6 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_6 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_valid_T_8 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_7 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_104 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_7 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_7 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_valid_T_9 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_8 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_105 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_8 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_8 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_valid_T_10 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_9 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_106 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_9 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_9 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_valid_T_11 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_10 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_107 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_10 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_10 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_valid_T_12 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_11 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_108 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_11 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_11 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_valid_T_13 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_12 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_109 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_12 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_12 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_valid_T_14 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_13 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_110 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_13 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_13 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_valid_T_15 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_14 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_111 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_14 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_14 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_valid_T_16 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_15 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_112 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_15 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_15 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_valid_T_17 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_16 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_113 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_16 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_16 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_valid_T_18 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_17 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_114 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_17 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_17 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_valid_T_19 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_18 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_115 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_18 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_18 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_valid_T_20 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_19 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_116 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_19 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_19 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_valid_T_21 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_20 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_117 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_20 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_20 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_valid_T_22 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_21 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_118 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_21 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_21 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_valid_T_23 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_22 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_119 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_22 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_22 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_valid_T_24 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_23 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_120 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_23 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_23 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_valid_T_25 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_24 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_121 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_24 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_24 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_valid_T_26 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_25 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_122 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_25 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_25 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_valid_T_27 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_26 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_123 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_26 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_26 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_valid_T_28 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_27 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_124 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_27 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_27 = idxHit[27]; // @[Mux.scala:32:36] wire [2:0] _io_resp_valid_T_29 = _io_resp_valid_T_1 ? idxPages_0 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_30 = _io_resp_valid_T_2 ? idxPages_1 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_31 = _io_resp_valid_T_3 ? idxPages_2 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_32 = _io_resp_valid_T_4 ? idxPages_3 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_33 = _io_resp_valid_T_5 ? idxPages_4 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_34 = _io_resp_valid_T_6 ? idxPages_5 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_35 = _io_resp_valid_T_7 ? idxPages_6 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_36 = _io_resp_valid_T_8 ? idxPages_7 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_37 = _io_resp_valid_T_9 ? idxPages_8 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_38 = _io_resp_valid_T_10 ? idxPages_9 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_39 = _io_resp_valid_T_11 ? idxPages_10 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_40 = _io_resp_valid_T_12 ? idxPages_11 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_41 = _io_resp_valid_T_13 ? idxPages_12 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_42 = _io_resp_valid_T_14 ? idxPages_13 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_43 = _io_resp_valid_T_15 ? idxPages_14 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_44 = _io_resp_valid_T_16 ? idxPages_15 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_45 = _io_resp_valid_T_17 ? idxPages_16 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_46 = _io_resp_valid_T_18 ? idxPages_17 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_47 = _io_resp_valid_T_19 ? idxPages_18 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_48 = _io_resp_valid_T_20 ? idxPages_19 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_49 = _io_resp_valid_T_21 ? idxPages_20 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_50 = _io_resp_valid_T_22 ? idxPages_21 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_51 = _io_resp_valid_T_23 ? idxPages_22 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_52 = _io_resp_valid_T_24 ? idxPages_23 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_53 = _io_resp_valid_T_25 ? idxPages_24 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_54 = _io_resp_valid_T_26 ? idxPages_25 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_55 = _io_resp_valid_T_27 ? idxPages_26 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_56 = _io_resp_valid_T_28 ? idxPages_27 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_57 = _io_resp_valid_T_29 \| _io_resp_valid_T_30; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_58 = _io_resp_valid_T_57 \| _io_resp_valid_T_31; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_59 = _io_resp_valid_T_58 \| _io_resp_valid_T_32; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_60 = _io_resp_valid_T_59 \| _io_resp_valid_T_33; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_61 = _io_resp_valid_T_60 \| _io_resp_valid_T_34; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_62 = _io_resp_valid_T_61 \| _io_resp_valid_T_35; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_63 = _io_resp_valid_T_62 \| _io_resp_valid_T_36; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_64 = _io_resp_valid_T_63 \| _io_resp_valid_T_37; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_65 = _io_resp_valid_T_64 \| _io_resp_valid_T_38; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_66 = _io_resp_valid_T_65 \| _io_resp_valid_T_39; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_67 = _io_resp_valid_T_66 \| _io_resp_valid_T_40; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_68 = _io_resp_valid_T_67 \| _io_resp_valid_T_41; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_69 = _io_resp_valid_T_68 \| _io_resp_valid_T_42; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_70 = _io_resp_valid_T_69 \| _io_resp_valid_T_43; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_71 = _io_resp_valid_T_70 \| _io_resp_valid_T_44; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_72 = _io_resp_valid_T_71 \| _io_resp_valid_T_45; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_73 = _io_resp_valid_T_72 \| _io_resp_valid_T_46; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_74 = _io_resp_valid_T_73 \| _io_resp_valid_T_47; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_75 = _io_resp_valid_T_74 \| _io_resp_valid_T_48; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_76 = _io_resp_valid_T_75 \| _io_resp_valid_T_49; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_77 = _io_resp_valid_T_76 \| _io_resp_valid_T_50; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_78 = _io_resp_valid_T_77 \| _io_resp_valid_T_51; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_79 = _io_resp_valid_T_78 \| _io_resp_valid_T_52; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_80 = _io_resp_valid_T_79 \| _io_resp_valid_T_53; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_81 = _io_resp_valid_T_80 \| _io_resp_valid_T_54; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_82 = _io_resp_valid_T_81 \| _io_resp_valid_T_55; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_83 = _io_resp_valid_T_82 \| _io_resp_valid_T_56; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_WIRE = _io_resp_valid_T_83; // @[Mux.scala:30:73] wire [6:0] _io_resp_valid_T_84 = _io_resp_valid_T >> _io_resp_valid_WIRE; // @[Mux.scala:30:73] assign _io_resp_valid_T_85 = _io_resp_valid_T_84[0]; // @[BTB.scala:287:34] assign io_resp_valid_0 = _io_resp_valid_T_85; // @[BTB.scala:187:7, :287:34] wire [2:0] _io_resp_bits_target_T_28 = _io_resp_bits_target_T ? tgtPages_0 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_29 = _io_resp_bits_target_T_1 ? tgtPages_1 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_30 = _io_resp_bits_target_T_2 ? tgtPages_2 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_31 = _io_resp_bits_target_T_3 ? tgtPages_3 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_32 = _io_resp_bits_target_T_4 ? tgtPages_4 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_33 = _io_resp_bits_target_T_5 ? tgtPages_5 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_34 = _io_resp_bits_target_T_6 ? tgtPages_6 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_35 = _io_resp_bits_target_T_7 ? tgtPages_7 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_36 = _io_resp_bits_target_T_8 ? tgtPages_8 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_37 = _io_resp_bits_target_T_9 ? tgtPages_9 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_38 = _io_resp_bits_target_T_10 ? tgtPages_10 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_39 = _io_resp_bits_target_T_11 ? tgtPages_11 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_40 = _io_resp_bits_target_T_12 ? tgtPages_12 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_41 = _io_resp_bits_target_T_13 ? tgtPages_13 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_42 = _io_resp_bits_target_T_14 ? tgtPages_14 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_43 = _io_resp_bits_target_T_15 ? tgtPages_15 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_44 = _io_resp_bits_target_T_16 ? tgtPages_16 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_45 = _io_resp_bits_target_T_17 ? tgtPages_17 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_46 = _io_resp_bits_target_T_18 ? tgtPages_18 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_47 = _io_resp_bits_target_T_19 ? tgtPages_19 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_48 = _io_resp_bits_target_T_20 ? tgtPages_20 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_49 = _io_resp_bits_target_T_21 ? tgtPages_21 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_50 = _io_resp_bits_target_T_22 ? tgtPages_22 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_51 = _io_resp_bits_target_T_23 ? tgtPages_23 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_52 = _io_resp_bits_target_T_24 ? tgtPages_24 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_53 = _io_resp_bits_target_T_25 ? tgtPages_25 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_54 = _io_resp_bits_target_T_26 ? tgtPages_26 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_55 = _io_resp_bits_target_T_27 ? tgtPages_27 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_56 = _io_resp_bits_target_T_28 \| _io_resp_bits_target_T_29; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_57 = _io_resp_bits_target_T_56 \| _io_resp_bits_target_T_30; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_58 = _io_resp_bits_target_T_57 \| _io_resp_bits_target_T_31; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_59 = _io_resp_bits_target_T_58 \| _io_resp_bits_target_T_32; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_60 = _io_resp_bits_target_T_59 \| _io_resp_bits_target_T_33; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_61 = _io_resp_bits_target_T_60 \| _io_resp_bits_target_T_34; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_62 = _io_resp_bits_target_T_61 \| _io_resp_bits_target_T_35; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_63 = _io_resp_bits_target_T_62 \| _io_resp_bits_target_T_36; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_64 = _io_resp_bits_target_T_63 \| _io_resp_bits_target_T_37; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_65 = _io_resp_bits_target_T_64 \| _io_resp_bits_target_T_38; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_66 = _io_resp_bits_target_T_65 \| _io_resp_bits_target_T_39; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_67 = _io_resp_bits_target_T_66 \| _io_resp_bits_target_T_40; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_68 = _io_resp_bits_target_T_67 \| _io_resp_bits_target_T_41; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_69 = _io_resp_bits_target_T_68 \| _io_resp_bits_target_T_42; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_70 = _io_resp_bits_target_T_69 \| _io_resp_bits_target_T_43; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_71 = _io_resp_bits_target_T_70 \| _io_resp_bits_target_T_44; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_72 = _io_resp_bits_target_T_71 \| _io_resp_bits_target_T_45; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_73 = _io_resp_bits_target_T_72 \| _io_resp_bits_target_T_46; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_74 = _io_resp_bits_target_T_73 \| _io_resp_bits_target_T_47; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_75 = _io_resp_bits_target_T_74 \| _io_resp_bits_target_T_48; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_76 = _io_resp_bits_target_T_75 \| _io_resp_bits_target_T_49; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_77 = _io_resp_bits_target_T_76 \| _io_resp_bits_target_T_50; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_78 = _io_resp_bits_target_T_77 \| _io_resp_bits_target_T_51; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_79 = _io_resp_bits_target_T_78 \| _io_resp_bits_target_T_52; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_80 = _io_resp_bits_target_T_79 \| _io_resp_bits_target_T_53; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_81 = _io_resp_bits_target_T_80 \| _io_resp_bits_target_T_54; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_82 = _io_resp_bits_target_T_81 \| _io_resp_bits_target_T_55; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_WIRE = _io_resp_bits_target_T_82; // @[Mux.scala:30:73] wire _io_resp_bits_target_T_83 = _io_resp_bits_target_WIRE == 3'h1; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_84 = _io_resp_bits_target_T_83 ? pagesMasked_1 : pagesMasked_0; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_85 = _io_resp_bits_target_WIRE == 3'h2; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_86 = _io_resp_bits_target_T_85 ? pagesMasked_2 : _io_resp_bits_target_T_84; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_87 = _io_resp_bits_target_WIRE == 3'h3; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_88 = _io_resp_bits_target_T_87 ? pagesMasked_3 : _io_resp_bits_target_T_86; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_89 = _io_resp_bits_target_WIRE == 3'h4; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_90 = _io_resp_bits_target_T_89 ? pagesMasked_4 : _io_resp_bits_target_T_88; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_91 = _io_resp_bits_target_WIRE == 3'h5; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_92 = _io_resp_bits_target_T_91 ? pagesMasked_5 : _io_resp_bits_target_T_90; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_93 = _io_resp_bits_target_WIRE == 3'h6; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_94 = _io_resp_bits_target_T_93 ? pagesMasked_4 : _io_resp_bits_target_T_92; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_95 = &_io_resp_bits_target_WIRE; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_96 = _io_resp_bits_target_T_95 ? pagesMasked_5 : _io_resp_bits_target_T_94; // @[package.scala:39:{76,86}] wire [12:0] _io_resp_bits_target_T_125 = _io_resp_bits_target_T_97 ? tgts_0 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_126 = _io_resp_bits_target_T_98 ? tgts_1 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_127 = _io_resp_bits_target_T_99 ? tgts_2 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_128 = _io_resp_bits_target_T_100 ? tgts_3 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_129 = _io_resp_bits_target_T_101 ? tgts_4 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_130 = _io_resp_bits_target_T_102 ? tgts_5 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_131 = _io_resp_bits_target_T_103 ? tgts_6 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_132 = _io_resp_bits_target_T_104 ? tgts_7 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_133 = _io_resp_bits_target_T_105 ? tgts_8 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_134 = _io_resp_bits_target_T_106 ? tgts_9 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_135 = _io_resp_bits_target_T_107 ? tgts_10 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_136 = _io_resp_bits_target_T_108 ? tgts_11 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_137 = _io_resp_bits_target_T_109 ? tgts_12 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_138 = _io_resp_bits_target_T_110 ? tgts_13 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_139 = _io_resp_bits_target_T_111 ? tgts_14 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_140 = _io_resp_bits_target_T_112 ? tgts_15 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_141 = _io_resp_bits_target_T_113 ? tgts_16 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_142 = _io_resp_bits_target_T_114 ? tgts_17 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_143 = _io_resp_bits_target_T_115 ? tgts_18 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_144 = _io_resp_bits_target_T_116 ? tgts_19 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_145 = _io_resp_bits_target_T_117 ? tgts_20 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_146 = _io_resp_bits_target_T_118 ? tgts_21 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_147 = _io_resp_bits_target_T_119 ? tgts_22 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_148 = _io_resp_bits_target_T_120 ? tgts_23 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_149 = _io_resp_bits_target_T_121 ? tgts_24 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_150 = _io_resp_bits_target_T_122 ? tgts_25 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_151 = _io_resp_bits_target_T_123 ? tgts_26 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_152 = _io_resp_bits_target_T_124 ? tgts_27 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_153 = _io_resp_bits_target_T_125 \| _io_resp_bits_target_T_126; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_154 = _io_resp_bits_target_T_153 \| _io_resp_bits_target_T_127; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_155 = _io_resp_bits_target_T_154 \| _io_resp_bits_target_T_128; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_156 = _io_resp_bits_target_T_155 \| _io_resp_bits_target_T_129; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_157 = _io_resp_bits_target_T_156 \| _io_resp_bits_target_T_130; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_158 = _io_resp_bits_target_T_157 \| _io_resp_bits_target_T_131; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_159 = _io_resp_bits_target_T_158 \| _io_resp_bits_target_T_132; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_160 = _io_resp_bits_target_T_159 \| _io_resp_bits_target_T_133; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_161 = _io_resp_bits_target_T_160 \| _io_resp_bits_target_T_134; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_162 = _io_resp_bits_target_T_161 \| _io_resp_bits_target_T_135; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_163 = _io_resp_bits_target_T_162 \| _io_resp_bits_target_T_136; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_164 = _io_resp_bits_target_T_163 \| _io_resp_bits_target_T_137; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_165 = _io_resp_bits_target_T_164 \| _io_resp_bits_target_T_138; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_166 = _io_resp_bits_target_T_165 \| _io_resp_bits_target_T_139; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_167 = _io_resp_bits_target_T_166 \| _io_resp_bits_target_T_140; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_168 = _io_resp_bits_target_T_167 \| _io_resp_bits_target_T_141; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_169 = _io_resp_bits_target_T_168 \| _io_resp_bits_target_T_142; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_170 = _io_resp_bits_target_T_169 \| _io_resp_bits_target_T_143; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_171 = _io_resp_bits_target_T_170 \| _io_resp_bits_target_T_144; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_172 = _io_resp_bits_target_T_171 \| _io_resp_bits_target_T_145; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_173 = _io_resp_bits_target_T_172 \| _io_resp_bits_target_T_146; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_174 = _io_resp_bits_target_T_173 \| _io_resp_bits_target_T_147; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_175 = _io_resp_bits_target_T_174 \| _io_resp_bits_target_T_148; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_176 = _io_resp_bits_target_T_175 \| _io_resp_bits_target_T_149; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_177 = _io_resp_bits_target_T_176 \| _io_resp_bits_target_T_150; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_178 = _io_resp_bits_target_T_177 \| _io_resp_bits_target_T_151; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_179 = _io_resp_bits_target_T_178 \| _io_resp_bits_target_T_152; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_WIRE_1 = _io_resp_bits_target_T_179; // @[Mux.scala:30:73] wire [13:0] _io_resp_bits_target_T_180 = {_io_resp_bits_target_WIRE_1, 1'h0}; // @[Mux.scala:30:73] wire [38:0] _io_resp_bits_target_T_181 = {_io_resp_bits_target_T_96, _io_resp_bits_target_T_180}; // @[package.scala:39:76] wire [11:0] io_resp_bits_entry_hi = idxHit[27:16]; // @[OneHot.scala:30:18] wire [15:0] io_resp_bits_entry_lo = idxHit[15:0]; // @[OneHot.scala:31:18] wire _io_resp_bits_entry_T = \|io_resp_bits_entry_hi; // @[OneHot.scala:30:18, :32:14] wire [15:0] _io_resp_bits_entry_T_1 = {4'h0, io_resp_bits_entry_hi} \| io_resp_bits_entry_lo; // @[OneHot.scala:30:18, :31:18, :32:{14,28}] wire [7:0] io_resp_bits_entry_hi_1 = _io_resp_bits_entry_T_1[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] io_resp_bits_entry_lo_1 = _io_resp_bits_entry_T_1[7:0]; // @[OneHot.scala:31:18, :32:28] wire _io_resp_bits_entry_T_2 = \|io_resp_bits_entry_hi_1; // @[OneHot.scala:30:18, :32:14] wire [7:0] _io_resp_bits_entry_T_3 = io_resp_bits_entry_hi_1 \| io_resp_bits_entry_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] io_resp_bits_entry_hi_2 = _io_resp_bits_entry_T_3[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] io_resp_bits_entry_lo_2 = _io_resp_bits_entry_T_3[3:0]; // @[OneHot.scala:31:18, :32:28] wire _io_resp_bits_entry_T_4 = \|io_resp_bits_entry_hi_2; // @[OneHot.scala:30:18, :32:14] wire [3:0] _io_resp_bits_entry_T_5 = io_resp_bits_entry_hi_2 \| io_resp_bits_entry_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] io_resp_bits_entry_hi_3 = _io_resp_bits_entry_T_5[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] io_resp_bits_entry_lo_3 = _io_resp_bits_entry_T_5[1:0]; // @[OneHot.scala:31:18, :32:28] wire _io_resp_bits_entry_T_6 = \|io_resp_bits_entry_hi_3; // @[OneHot.scala:30:18, :32:14] wire [1:0] _io_resp_bits_entry_T_7 = io_resp_bits_entry_hi_3 \| io_resp_bits_entry_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire _io_resp_bits_entry_T_8 = _io_resp_bits_entry_T_7[1]; // @[OneHot.scala:32:28] wire [1:0] _io_resp_bits_entry_T_9 = {_io_resp_bits_entry_T_6, _io_resp_bits_entry_T_8}; // @[OneHot.scala:32:{10,14}] wire [2:0] _io_resp_bits_entry_T_10 = {_io_resp_bits_entry_T_4, _io_resp_bits_entry_T_9}; // @[OneHot.scala:32:{10,14}] wire [3:0] _io_resp_bits_entry_T_11 = {_io_resp_bits_entry_T_2, _io_resp_bits_entry_T_10}; // @[OneHot.scala:32:{10,14}] assign _io_resp_bits_entry_T_12 = {_io_resp_bits_entry_T, _io_resp_bits_entry_T_11}; // @[OneHot.scala:32:{10,14}] assign io_resp_bits_entry_0 = _io_resp_bits_entry_T_12; // @[OneHot.scala:32:10] wire _io_resp_bits_bridx_T_28 = _io_resp_bits_bridx_T & brIdx_0; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_29 = _io_resp_bits_bridx_T_1 & brIdx_1; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_30 = _io_resp_bits_bridx_T_2 & brIdx_2; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_31 = _io_resp_bits_bridx_T_3 & brIdx_3; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_32 = _io_resp_bits_bridx_T_4 & brIdx_4; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_33 = _io_resp_bits_bridx_T_5 & brIdx_5; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_34 = _io_resp_bits_bridx_T_6 & brIdx_6; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_35 = _io_resp_bits_bridx_T_7 & brIdx_7; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_36 = _io_resp_bits_bridx_T_8 & brIdx_8; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_37 = _io_resp_bits_bridx_T_9 & brIdx_9; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_38 = _io_resp_bits_bridx_T_10 & brIdx_10; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_39 = _io_resp_bits_bridx_T_11 & brIdx_11; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_40 = _io_resp_bits_bridx_T_12 & brIdx_12; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_41 = _io_resp_bits_bridx_T_13 & brIdx_13; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_42 = _io_resp_bits_bridx_T_14 & brIdx_14; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_43 = _io_resp_bits_bridx_T_15 & brIdx_15; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_44 = _io_resp_bits_bridx_T_16 & brIdx_16; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_45 = _io_resp_bits_bridx_T_17 & brIdx_17; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_46 = _io_resp_bits_bridx_T_18 & brIdx_18; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_47 = _io_resp_bits_bridx_T_19 & brIdx_19; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_48 = _io_resp_bits_bridx_T_20 & brIdx_20; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_49 = _io_resp_bits_bridx_T_21 & brIdx_21; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_50 = _io_resp_bits_bridx_T_22 & brIdx_22; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_51 = _io_resp_bits_bridx_T_23 & brIdx_23; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_52 = _io_resp_bits_bridx_T_24 & brIdx_24; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_53 = _io_resp_bits_bridx_T_25 & brIdx_25; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_54 = _io_resp_bits_bridx_T_26 & brIdx_26; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_55 = _io_resp_bits_bridx_T_27 & brIdx_27; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_56 = _io_resp_bits_bridx_T_28 \| _io_resp_bits_bridx_T_29; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_57 = _io_resp_bits_bridx_T_56 \| _io_resp_bits_bridx_T_30; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_58 = _io_resp_bits_bridx_T_57 \| _io_resp_bits_bridx_T_31; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_59 = _io_resp_bits_bridx_T_58 \| _io_resp_bits_bridx_T_32; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_60 = _io_resp_bits_bridx_T_59 \| _io_resp_bits_bridx_T_33; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_61 = _io_resp_bits_bridx_T_60 \| _io_resp_bits_bridx_T_34; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_62 = _io_resp_bits_bridx_T_61 \| _io_resp_bits_bridx_T_35; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_63 = _io_resp_bits_bridx_T_62 \| _io_resp_bits_bridx_T_36; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_64 = _io_resp_bits_bridx_T_63 \| _io_resp_bits_bridx_T_37; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_65 = _io_resp_bits_bridx_T_64 \| _io_resp_bits_bridx_T_38; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_66 = _io_resp_bits_bridx_T_65 \| _io_resp_bits_bridx_T_39; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_67 = _io_resp_bits_bridx_T_66 \| _io_resp_bits_bridx_T_40; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_68 = _io_resp_bits_bridx_T_67 \| _io_resp_bits_bridx_T_41; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_69 = _io_resp_bits_bridx_T_68 \| _io_resp_bits_bridx_T_42; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_70 = _io_resp_bits_bridx_T_69 \| _io_resp_bits_bridx_T_43; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_71 = _io_resp_bits_bridx_T_70 \| _io_resp_bits_bridx_T_44; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_72 = _io_resp_bits_bridx_T_71 \| _io_resp_bits_bridx_T_45; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_73 = _io_resp_bits_bridx_T_72 \| _io_resp_bits_bridx_T_46; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_74 = _io_resp_bits_bridx_T_73 \| _io_resp_bits_bridx_T_47; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_75 = _io_resp_bits_bridx_T_74 \| _io_resp_bits_bridx_T_48; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_76 = _io_resp_bits_bridx_T_75 \| _io_resp_bits_bridx_T_49; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_77 = _io_resp_bits_bridx_T_76 \| _io_resp_bits_bridx_T_50; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_78 = _io_resp_bits_bridx_T_77 \| _io_resp_bits_bridx_T_51; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_79 = _io_resp_bits_bridx_T_78 \| _io_resp_bits_bridx_T_52; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_80 = _io_resp_bits_bridx_T_79 \| _io_resp_bits_bridx_T_53; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_81 = _io_resp_bits_bridx_T_80 \| _io_resp_bits_bridx_T_54; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_82 = _io_resp_bits_bridx_T_81 \| _io_resp_bits_bridx_T_55; // @[Mux.scala:30:73] assign _io_resp_bits_bridx_WIRE = _io_resp_bits_bridx_T_82; // @[Mux.scala:30:73] assign io_resp_bits_bridx_0 = _io_resp_bits_bridx_WIRE; // @[Mux.scala:30:73] wire _io_resp_bits_mask_T = ~io_resp_bits_bridx_0; // @[BTB.scala:187:7, :292:61] wire _io_resp_bits_mask_T_1 = io_resp_bits_taken_0 & _io_resp_bits_mask_T; // @[BTB.scala:187:7, :292:{40,61}] wire _io_resp_bits_mask_T_2 = ~_io_resp_bits_mask_T_1; // @[BTB.scala:292:{36,40}] wire [1:0] _io_resp_bits_mask_T_3 = 2'h1 << _io_resp_bits_mask_T_2; // @[BTB.scala:292:{33,36}] wire [2:0] _io_resp_bits_mask_T_4 = {1'h0, _io_resp_bits_mask_T_3} - 3'h1; // @[BTB.scala:292:{33,87}] wire [1:0] _io_resp_bits_mask_T_5 = _io_resp_bits_mask_T_4[1:0]; // @[BTB.scala:292:87] wire [2:0] _io_resp_bits_mask_T_6 = {_io_resp_bits_mask_T_5, 1'h1}; // @[BTB.scala:187:7, :292:{27,87}] assign io_resp_bits_mask_0 = _io_resp_bits_mask_T_6[1:0]; // @[BTB.scala:187:7, :292:{21,27}] wire [1:0] _io_resp_bits_cfiType_T_28 = _io_resp_bits_cfiType_T ? cfiType_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_29 = _io_resp_bits_cfiType_T_1 ? cfiType_1 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_30 = _io_resp_bits_cfiType_T_2 ? cfiType_2 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_31 = _io_resp_bits_cfiType_T_3 ? cfiType_3 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_32 = _io_resp_bits_cfiType_T_4 ? cfiType_4 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_33 = _io_resp_bits_cfiType_T_5 ? cfiType_5 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_34 = _io_resp_bits_cfiType_T_6 ? cfiType_6 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_35 = _io_resp_bits_cfiType_T_7 ? cfiType_7 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_36 = _io_resp_bits_cfiType_T_8 ? cfiType_8 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_37 = _io_resp_bits_cfiType_T_9 ? cfiType_9 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_38 = _io_resp_bits_cfiType_T_10 ? cfiType_10 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_39 = _io_resp_bits_cfiType_T_11 ? cfiType_11 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_40 = _io_resp_bits_cfiType_T_12 ? cfiType_12 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_41 = _io_resp_bits_cfiType_T_13 ? cfiType_13 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_42 = _io_resp_bits_cfiType_T_14 ? cfiType_14 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_43 = _io_resp_bits_cfiType_T_15 ? cfiType_15 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_44 = _io_resp_bits_cfiType_T_16 ? cfiType_16 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_45 = _io_resp_bits_cfiType_T_17 ? cfiType_17 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_46 = _io_resp_bits_cfiType_T_18 ? cfiType_18 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_47 = _io_resp_bits_cfiType_T_19 ? cfiType_19 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_48 = _io_resp_bits_cfiType_T_20 ? cfiType_20 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_49 = _io_resp_bits_cfiType_T_21 ? cfiType_21 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_50 = _io_resp_bits_cfiType_T_22 ? cfiType_22 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_51 = _io_resp_bits_cfiType_T_23 ? cfiType_23 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_52 = _io_resp_bits_cfiType_T_24 ? cfiType_24 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_53 = _io_resp_bits_cfiType_T_25 ? cfiType_25 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_54 = _io_resp_bits_cfiType_T_26 ? cfiType_26 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_55 = _io_resp_bits_cfiType_T_27 ? cfiType_27 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_56 = _io_resp_bits_cfiType_T_28 \| _io_resp_bits_cfiType_T_29; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_57 = _io_resp_bits_cfiType_T_56 \| _io_resp_bits_cfiType_T_30; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_58 = _io_resp_bits_cfiType_T_57 \| _io_resp_bits_cfiType_T_31; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_59 = _io_resp_bits_cfiType_T_58 \| _io_resp_bits_cfiType_T_32; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_60 = _io_resp_bits_cfiType_T_59 \| _io_resp_bits_cfiType_T_33; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_61 = _io_resp_bits_cfiType_T_60 \| _io_resp_bits_cfiType_T_34; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_62 = _io_resp_bits_cfiType_T_61 \| _io_resp_bits_cfiType_T_35; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_63 = _io_resp_bits_cfiType_T_62 \| _io_resp_bits_cfiType_T_36; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_64 = _io_resp_bits_cfiType_T_63 \| _io_resp_bits_cfiType_T_37; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_65 = _io_resp_bits_cfiType_T_64 \| _io_resp_bits_cfiType_T_38; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_66 = _io_resp_bits_cfiType_T_65 \| _io_resp_bits_cfiType_T_39; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_67 = _io_resp_bits_cfiType_T_66 \| _io_resp_bits_cfiType_T_40; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_68 = _io_resp_bits_cfiType_T_67 \| _io_resp_bits_cfiType_T_41; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_69 = _io_resp_bits_cfiType_T_68 \| _io_resp_bits_cfiType_T_42; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_70 = _io_resp_bits_cfiType_T_69 \| _io_resp_bits_cfiType_T_43; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_71 = _io_resp_bits_cfiType_T_70 \| _io_resp_bits_cfiType_T_44; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_72 = _io_resp_bits_cfiType_T_71 \| _io_resp_bits_cfiType_T_45; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_73 = _io_resp_bits_cfiType_T_72 \| _io_resp_bits_cfiType_T_46; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_74 = _io_resp_bits_cfiType_T_73 \| _io_resp_bits_cfiType_T_47; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_75 = _io_resp_bits_cfiType_T_74 \| _io_resp_bits_cfiType_T_48; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_76 = _io_resp_bits_cfiType_T_75 \| _io_resp_bits_cfiType_T_49; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_77 = _io_resp_bits_cfiType_T_76 \| _io_resp_bits_cfiType_T_50; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_78 = _io_resp_bits_cfiType_T_77 \| _io_resp_bits_cfiType_T_51; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_79 = _io_resp_bits_cfiType_T_78 \| _io_resp_bits_cfiType_T_52; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_80 = _io_resp_bits_cfiType_T_79 \| _io_resp_bits_cfiType_T_53; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_81 = _io_resp_bits_cfiType_T_80 \| _io_resp_bits_cfiType_T_54; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_82 = _io_resp_bits_cfiType_T_81 \| _io_resp_bits_cfiType_T_55; // @[Mux.scala:30:73] assign _io_resp_bits_cfiType_WIRE = _io_resp_bits_cfiType_T_82; // @[Mux.scala:30:73] assign io_resp_bits_cfiType_0 = _io_resp_bits_cfiType_WIRE; // @[Mux.scala:30:73] wire leftOne = idxHit[0]; // @[Misc.scala:178:18, :181:37] wire leftOne_1 = idxHit[1]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne = idxHit[2]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_1 = leftOne_1 \| rightOne; // @[Misc.scala:178:18, :183:16] wire rightTwo = leftOne_1 & rightOne; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_2 = leftOne \| rightOne_1; // @[Misc.scala:178:18, :183:16] wire leftTwo = rightTwo \| leftOne & rightOne_1; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_3 = idxHit[3]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_2 = idxHit[4]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_4 = leftOne_3 \| rightOne_2; // @[Misc.scala:178:18, :183:16] wire leftTwo_1 = leftOne_3 & rightOne_2; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_5 = idxHit[5]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_3 = idxHit[6]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_4 = leftOne_5 \| rightOne_3; // @[Misc.scala:178:18, :183:16] wire rightTwo_1 = leftOne_5 & rightOne_3; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_5 = leftOne_4 \| rightOne_4; // @[Misc.scala:183:16] wire rightTwo_2 = leftTwo_1 \| rightTwo_1 \| leftOne_4 & rightOne_4; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_6 = leftOne_2 \| rightOne_5; // @[Misc.scala:183:16] wire leftTwo_2 = leftTwo \| rightTwo_2 \| leftOne_2 & rightOne_5; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_7 = idxHit[7]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_8 = idxHit[8]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_6 = idxHit[9]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_7 = leftOne_8 \| rightOne_6; // @[Misc.scala:178:18, :183:16] wire rightTwo_3 = leftOne_8 & rightOne_6; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_9 = leftOne_7 \| rightOne_7; // @[Misc.scala:178:18, :183:16] wire leftTwo_3 = rightTwo_3 \| leftOne_7 & rightOne_7; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_10 = idxHit[10]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_8 = idxHit[11]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_11 = leftOne_10 \| rightOne_8; // @[Misc.scala:178:18, :183:16] wire leftTwo_4 = leftOne_10 & rightOne_8; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_12 = idxHit[12]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_9 = idxHit[13]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_10 = leftOne_12 \| rightOne_9; // @[Misc.scala:178:18, :183:16] wire rightTwo_4 = leftOne_12 & rightOne_9; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_11 = leftOne_11 \| rightOne_10; // @[Misc.scala:183:16] wire rightTwo_5 = leftTwo_4 \| rightTwo_4 \| leftOne_11 & rightOne_10; // @[Misc.scala:183:{16,37,49,61}] wire rightOne_12 = leftOne_9 \| rightOne_11; // @[Misc.scala:183:16] wire rightTwo_6 = leftTwo_3 \| rightTwo_5 \| leftOne_9 & rightOne_11; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_13 = leftOne_6 \| rightOne_12; // @[Misc.scala:183:16] wire leftTwo_5 = leftTwo_2 \| rightTwo_6 \| leftOne_6 & rightOne_12; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_14 = idxHit[14]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_15 = idxHit[15]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_13 = idxHit[16]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_14 = leftOne_15 \| rightOne_13; // @[Misc.scala:178:18, :183:16] wire rightTwo_7 = leftOne_15 & rightOne_13; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_16 = leftOne_14 \| rightOne_14; // @[Misc.scala:178:18, :183:16] wire leftTwo_6 = rightTwo_7 \| leftOne_14 & rightOne_14; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_17 = idxHit[17]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_15 = idxHit[18]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_18 = leftOne_17 \| rightOne_15; // @[Misc.scala:178:18, :183:16] wire leftTwo_7 = leftOne_17 & rightOne_15; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_19 = idxHit[19]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_16 = idxHit[20]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_17 = leftOne_19 \| rightOne_16; // @[Misc.scala:178:18, :183:16] wire rightTwo_8 = leftOne_19 & rightOne_16; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_18 = leftOne_18 \| rightOne_17; // @[Misc.scala:183:16] wire rightTwo_9 = leftTwo_7 \| rightTwo_8 \| leftOne_18 & rightOne_17; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_20 = leftOne_16 \| rightOne_18; // @[Misc.scala:183:16] wire leftTwo_8 = leftTwo_6 \| rightTwo_9 \| leftOne_16 & rightOne_18; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_21 = idxHit[21]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_22 = idxHit[22]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_19 = idxHit[23]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_20 = leftOne_22 \| rightOne_19; // @[Misc.scala:178:18, :183:16] wire rightTwo_10 = leftOne_22 & rightOne_19; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_23 = leftOne_21 \| rightOne_20; // @[Misc.scala:178:18, :183:16] wire leftTwo_9 = rightTwo_10 \| leftOne_21 & rightOne_20; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_24 = idxHit[24]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_21 = idxHit[25]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_25 = leftOne_24 \| rightOne_21; // @[Misc.scala:178:18, :183:16] wire leftTwo_10 = leftOne_24 & rightOne_21; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_26 = idxHit[26]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_22 = idxHit[27]; // @[Misc.scala:178:18, :182:39] wire rightOne_23 = leftOne_26 \| rightOne_22; // @[Misc.scala:178:18, :183:16] wire rightTwo_11 = leftOne_26 & rightOne_22; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_24 = leftOne_25 \| rightOne_23; // @[Misc.scala:183:16] wire rightTwo_12 = leftTwo_10 \| rightTwo_11 \| leftOne_25 & rightOne_23; // @[Misc.scala:183:{16,37,49,61}] wire rightOne_25 = leftOne_23 \| rightOne_24; // @[Misc.scala:183:16] wire rightTwo_13 = leftTwo_9 \| rightTwo_12 \| leftOne_23 & rightOne_24; // @[Misc.scala:183:{16,37,49,61}] wire rightOne_26 = leftOne_20 \| rightOne_25; // @[Misc.scala:183:16] wire rightTwo_14 = leftTwo_8 \| rightTwo_13 \| leftOne_20 & rightOne_25; // @[Misc.scala:183:{16,37,49,61}] wire [27:0] _isValid_T_4 = ~idxHit; // @[BTB.scala:218:32, :297:26] wire [27:0] _isValid_T_5 = isValid & _isValid_T_4; // @[BTB.scala:207:24, :297:{24,26}] reg [7:0] history; // @[BTB.scala:117:24] assign res_history = history; // @[BTB.scala:91:19, :117:24] reg [9:0] reset_waddr; // @[BTB.scala:119:36] wire _resetting_T = reset_waddr[9]; // @[BTB.scala:119:36, :120:39] wire resetting = ~_resetting_T; // @[BTB.scala:120:{27,39}] wire wen; // @[BTB.scala:121:29] wire [9:0] waddr_1; // @[BTB.scala:122:31] wire wdata; // @[BTB.scala:123:31] wire [10:0] _reset_waddr_T = {1'h0, reset_waddr} + 11'h1; // @[BTB.scala:119:36, :124:49] wire [9:0] _reset_waddr_T_1 = _reset_waddr_T[9:0]; // @[BTB.scala:124:49] wire _isBranch_T = cfiType_0 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_1 = cfiType_1 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_2 = cfiType_2 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_3 = cfiType_3 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_4 = cfiType_4 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_5 = cfiType_5 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_6 = cfiType_6 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_7 = cfiType_7 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_8 = cfiType_8 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_9 = cfiType_9 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_10 = cfiType_10 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_11 = cfiType_11 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_12 = cfiType_12 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_13 = cfiType_13 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_14 = cfiType_14 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_15 = cfiType_15 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_16 = cfiType_16 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_17 = cfiType_17 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_18 = cfiType_18 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_19 = cfiType_19 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_20 = cfiType_20 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_21 = cfiType_21 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_22 = cfiType_22 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_23 = cfiType_23 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_24 = cfiType_24 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_25 = cfiType_25 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_26 = cfiType_26 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_27 = cfiType_27 == 2'h0; // @[BTB.scala:208:20, :305:44] wire [1:0] isBranch_lo_lo_lo_hi = {_isBranch_T_2, _isBranch_T_1}; // @[package.scala:45:27] wire [2:0] isBranch_lo_lo_lo = {isBranch_lo_lo_lo_hi, _isBranch_T}; // @[package.scala:45:27] wire [1:0] isBranch_lo_lo_hi_lo = {_isBranch_T_4, _isBranch_T_3}; // @[package.scala:45:27] wire [1:0] isBranch_lo_lo_hi_hi = {_isBranch_T_6, _isBranch_T_5}; // @[package.scala:45:27] wire [3:0] isBranch_lo_lo_hi = {isBranch_lo_lo_hi_hi, isBranch_lo_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_lo_lo = {isBranch_lo_lo_hi, isBranch_lo_lo_lo}; // @[package.scala:45:27] wire [1:0] isBranch_lo_hi_lo_hi = {_isBranch_T_9, _isBranch_T_8}; // @[package.scala:45:27] wire [2:0] isBranch_lo_hi_lo = {isBranch_lo_hi_lo_hi, _isBranch_T_7}; // @[package.scala:45:27] wire [1:0] isBranch_lo_hi_hi_lo = {_isBranch_T_11, _isBranch_T_10}; // @[package.scala:45:27] wire [1:0] isBranch_lo_hi_hi_hi = {_isBranch_T_13, _isBranch_T_12}; // @[package.scala:45:27] wire [3:0] isBranch_lo_hi_hi = {isBranch_lo_hi_hi_hi, isBranch_lo_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_lo_hi = {isBranch_lo_hi_hi, isBranch_lo_hi_lo}; // @[package.scala:45:27] wire [13:0] isBranch_lo = {isBranch_lo_hi, isBranch_lo_lo}; // @[package.scala:45:27] wire [1:0] isBranch_hi_lo_lo_hi = {_isBranch_T_16, _isBranch_T_15}; // @[package.scala:45:27] wire [2:0] isBranch_hi_lo_lo = {isBranch_hi_lo_lo_hi, _isBranch_T_14}; // @[package.scala:45:27] wire [1:0] isBranch_hi_lo_hi_lo = {_isBranch_T_18, _isBranch_T_17}; // @[package.scala:45:27] wire [1:0] isBranch_hi_lo_hi_hi = {_isBranch_T_20, _isBranch_T_19}; // @[package.scala:45:27] wire [3:0] isBranch_hi_lo_hi = {isBranch_hi_lo_hi_hi, isBranch_hi_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_hi_lo = {isBranch_hi_lo_hi, isBranch_hi_lo_lo}; // @[package.scala:45:27] wire [1:0] isBranch_hi_hi_lo_hi = {_isBranch_T_23, _isBranch_T_22}; // @[package.scala:45:27] wire [2:0] isBranch_hi_hi_lo = {isBranch_hi_hi_lo_hi, _isBranch_T_21}; // @[package.scala:45:27] wire [1:0] isBranch_hi_hi_hi_lo = {_isBranch_T_25, _isBranch_T_24}; // @[package.scala:45:27] wire [1:0] isBranch_hi_hi_hi_hi = {_isBranch_T_27, _isBranch_T_26}; // @[package.scala:45:27] wire [3:0] isBranch_hi_hi_hi = {isBranch_hi_hi_hi_hi, isBranch_hi_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_hi_hi = {isBranch_hi_hi_hi, isBranch_hi_hi_lo}; // @[package.scala:45:27] wire [13:0] isBranch_hi = {isBranch_hi_hi, isBranch_hi_lo}; // @[package.scala:45:27] wire [27:0] _isBranch_T_28 = {isBranch_hi, isBranch_lo}; // @[package.scala:45:27] wire [27:0] _isBranch_T_29 = idxHit & _isBranch_T_28; // @[package.scala:45:27] wire isBranch = \|_isBranch_T_29; // @[BTB.scala:305:{28,72}] assign io_resp_bits_bht_history_0 = res_history; // @[BTB.scala:91:19, :187:7] wire _res_res_value_T_8; // @[BTB.scala:92:21] assign io_resp_bits_bht_value_0 = res_value; // @[BTB.scala:91:19, :187:7] wire [36:0] res_res_value_hi = io_req_bits_addr_0[38:2]; // @[BTB.scala:85:21, :187:7] wire [8:0] _res_res_value_T = res_res_value_hi[8:0]; // @[BTB.scala:85:21, :86:9] wire [27:0] _res_res_value_T_1 = res_res_value_hi[36:9]; // @[BTB.scala:85:21, :86:48] wire [1:0] _res_res_value_T_2 = _res_res_value_T_1[1:0]; // @[BTB.scala:86:{48,77}] wire [8:0] _res_res_value_T_3 = {_res_res_value_T[8:2], _res_res_value_T[1:0] ^ _res_res_value_T_2}; // @[BTB.scala:86:{9,42,77}] wire [15:0] _res_res_value_T_4 = {8'h0, history} * 16'hDD; // @[BTB.scala:82:12, :117:24] wire [2:0] _res_res_value_T_5 = _res_res_value_T_4[7:5]; // @[BTB.scala:82:{12,19}] wire [8:0] _res_res_value_T_6 = {_res_res_value_T_5, 6'h0}; // @[BTB.scala:82:19, :88:44] wire [8:0] _res_res_value_T_7 = _res_res_value_T_3 ^ _res_res_value_T_6; // @[BTB.scala:86:42, :88:{20,44}] assign _res_res_value_T_8 = ~resetting & _table_ext_R0_data; // @[BTB.scala:92:21, :116:26, :120:27] assign res_value = _res_res_value_T_8; // @[BTB.scala:91:19, :92:21] wire [6:0] _history_T = history[7:1]; // @[BTB.scala:113:35, :117:24] wire [7:0] _history_T_1 = {io_bht_advance_bits_bht_value_0, _history_T}; // @[BTB.scala:113:{19,35}, :187:7] wire _GEN = io_bht_update_valid_0 & io_bht_update_bits_branch_0; // @[BTB.scala:97:9, :121:29, :187:7, :310:32, :311:40] assign wen = _GEN \| resetting; // @[BTB.scala:97:9, :120:27, :121:29, :310:32, :311:40] wire [36:0] waddr_hi = io_bht_update_bits_pc_0[38:2]; // @[BTB.scala:85:21, :187:7] wire [8:0] _waddr_T_40 = waddr_hi[8:0]; // @[BTB.scala:85:21, :86:9] wire [27:0] _waddr_T_41 = waddr_hi[36:9]; // @[BTB.scala:85:21, :86:48] wire [1:0] _waddr_T_42 = _waddr_T_41[1:0]; // @[BTB.scala:86:{48,77}] wire [8:0] _waddr_T_43 = {_waddr_T_40[8:2], _waddr_T_40[1:0] ^ _waddr_T_42}; // @[BTB.scala:86:{9,42,77}] wire [15:0] _waddr_T_44 = {8'h0, io_bht_update_bits_prediction_history_0} * 16'hDD; // @[BTB.scala:82:12, :187:7] wire [2:0] _waddr_T_45 = _waddr_T_44[7:5]; // @[BTB.scala:82:{12,19}] wire [8:0] _waddr_T_46 = {_waddr_T_45, 6'h0}; // @[BTB.scala:82:19, :88:44] wire [8:0] _waddr_T_47 = _waddr_T_43 ^ _waddr_T_46; // @[BTB.scala:86:42, :88:{20,44}] assign waddr_1 = io_bht_update_valid_0 & io_bht_update_bits_branch_0 & ~resetting ? {1'h0, _waddr_T_47} : reset_waddr; // @[BTB.scala:88:20, :98:{11,23}, :99:13, :119:36, :120:27, :122:31, :187:7, :310:32, :311:40] assign wdata = _GEN & ~resetting & io_bht_update_bits_taken_0; // @[BTB.scala:97:9, :98:{11,23}, :100:13, :120:27, :121:29, :123:31, :187:7, :310:32, :311:40] wire [6:0] _history_T_2 = io_bht_update_bits_prediction_history_0[7:1]; // @[BTB.scala:110:37, :187:7] wire [7:0] _history_T_3 = {io_bht_update_bits_taken_0, _history_T_2}; // @[BTB.scala:110:{19,37}, :187:7] assign io_resp_bits_taken_0 = ~(~res_value & isBranch); // @[BTB.scala:91:19, :187:7, :288:22, :305:72, :320:{11,22,35,56}] reg [2:0] count; // @[BTB.scala:56:30] reg [2:0] pos; // @[BTB.scala:57:28] reg [38:0] stack_0; // @[BTB.scala:58:26] reg [38:0] stack_1; // @[BTB.scala:58:26] reg [38:0] stack_2; // @[BTB.scala:58:26] reg [38:0] stack_3; // @[BTB.scala:58:26] reg [38:0] stack_4; // @[BTB.scala:58:26] reg [38:0] stack_5; // @[BTB.scala:58:26] wire _doPeek_T = &cfiType_0; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_1 = &cfiType_1; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_2 = &cfiType_2; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_3 = &cfiType_3; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_4 = &cfiType_4; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_5 = &cfiType_5; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_6 = &cfiType_6; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_7 = &cfiType_7; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_8 = &cfiType_8; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_9 = &cfiType_9; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_10 = &cfiType_10; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_11 = &cfiType_11; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_12 = &cfiType_12; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_13 = &cfiType_13; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_14 = &cfiType_14; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_15 = &cfiType_15; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_16 = &cfiType_16; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_17 = &cfiType_17; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_18 = &cfiType_18; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_19 = &cfiType_19; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_20 = &cfiType_20; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_21 = &cfiType_21; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_22 = &cfiType_22; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_23 = &cfiType_23; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_24 = &cfiType_24; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_25 = &cfiType_25; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_26 = &cfiType_26; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_27 = &cfiType_27; // @[BTB.scala:208:20, :326:42] wire [1:0] doPeek_lo_lo_lo_hi = {_doPeek_T_2, _doPeek_T_1}; // @[package.scala:45:27] wire [2:0] doPeek_lo_lo_lo = {doPeek_lo_lo_lo_hi, _doPeek_T}; // @[package.scala:45:27] wire [1:0] doPeek_lo_lo_hi_lo = {_doPeek_T_4, _doPeek_T_3}; // @[package.scala:45:27] wire [1:0] doPeek_lo_lo_hi_hi = {_doPeek_T_6, _doPeek_T_5}; // @[package.scala:45:27] wire [3:0] doPeek_lo_lo_hi = {doPeek_lo_lo_hi_hi, doPeek_lo_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_lo_lo = {doPeek_lo_lo_hi, doPeek_lo_lo_lo}; // @[package.scala:45:27] wire [1:0] doPeek_lo_hi_lo_hi = {_doPeek_T_9, _doPeek_T_8}; // @[package.scala:45:27] wire [2:0] doPeek_lo_hi_lo = {doPeek_lo_hi_lo_hi, _doPeek_T_7}; // @[package.scala:45:27] wire [1:0] doPeek_lo_hi_hi_lo = {_doPeek_T_11, _doPeek_T_10}; // @[package.scala:45:27] wire [1:0] doPeek_lo_hi_hi_hi = {_doPeek_T_13, _doPeek_T_12}; // @[package.scala:45:27] wire [3:0] doPeek_lo_hi_hi = {doPeek_lo_hi_hi_hi, doPeek_lo_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_lo_hi = {doPeek_lo_hi_hi, doPeek_lo_hi_lo}; // @[package.scala:45:27] wire [13:0] doPeek_lo = {doPeek_lo_hi, doPeek_lo_lo}; // @[package.scala:45:27] wire [1:0] doPeek_hi_lo_lo_hi = {_doPeek_T_16, _doPeek_T_15}; // @[package.scala:45:27] wire [2:0] doPeek_hi_lo_lo = {doPeek_hi_lo_lo_hi, _doPeek_T_14}; // @[package.scala:45:27] wire [1:0] doPeek_hi_lo_hi_lo = {_doPeek_T_18, _doPeek_T_17}; // @[package.scala:45:27] wire [1:0] doPeek_hi_lo_hi_hi = {_doPeek_T_20, _doPeek_T_19}; // @[package.scala:45:27] wire [3:0] doPeek_hi_lo_hi = {doPeek_hi_lo_hi_hi, doPeek_hi_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_hi_lo = {doPeek_hi_lo_hi, doPeek_hi_lo_lo}; // @[package.scala:45:27] wire [1:0] doPeek_hi_hi_lo_hi = {_doPeek_T_23, _doPeek_T_22}; // @[package.scala:45:27] wire [2:0] doPeek_hi_hi_lo = {doPeek_hi_hi_lo_hi, _doPeek_T_21}; // @[package.scala:45:27] wire [1:0] doPeek_hi_hi_hi_lo = {_doPeek_T_25, _doPeek_T_24}; // @[package.scala:45:27] wire [1:0] doPeek_hi_hi_hi_hi = {_doPeek_T_27, _doPeek_T_26}; // @[package.scala:45:27] wire [3:0] doPeek_hi_hi_hi = {doPeek_hi_hi_hi_hi, doPeek_hi_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_hi_hi = {doPeek_hi_hi_hi, doPeek_hi_hi_lo}; // @[package.scala:45:27] wire [13:0] doPeek_hi = {doPeek_hi_hi, doPeek_hi_lo}; // @[package.scala:45:27] wire [27:0] _doPeek_T_28 = {doPeek_hi, doPeek_lo}; // @[package.scala:45:27] wire [27:0] _doPeek_T_29 = idxHit & _doPeek_T_28; // @[package.scala:45:27] wire doPeek = \|_doPeek_T_29; // @[BTB.scala:326:{26,67}] wire _io_ras_head_valid_T = ~(\|count); // @[BTB.scala:54:29, :56:30] assign _io_ras_head_valid_T_1 = ~_io_ras_head_valid_T; // @[BTB.scala:54:29, :327:26] assign io_ras_head_valid_0 = _io_ras_head_valid_T_1; // @[BTB.scala:187:7, :327:26] wire [7:0][38:0] _GEN_0 = {{stack_0}, {stack_0}, {stack_5}, {stack_4}, {stack_3}, {stack_2}, {stack_1}, {stack_0}}; // @[BTB.scala:58:26, :328:22] assign io_ras_head_bits_0 = _GEN_0[pos]; // @[BTB.scala:57:28, :187:7, :328:22] assign io_resp_bits_target_0 = (\|count) & doPeek ? io_ras_head_bits_0 : _io_resp_bits_target_T_181; // @[BTB.scala:54:29, :56:30, :187:7, :289:{23,29}, :326:67, :329:{24,35}, :330:27] wire [3:0] _GEN_1 = {1'h0, count}; // @[BTB.scala:43:44, :56:30] wire [3:0] _count_T = _GEN_1 + 4'h1; // @[BTB.scala:43:44] wire [2:0] _count_T_1 = _count_T[2:0]; // @[BTB.scala:43:44] wire _nextPos_T = pos < 3'h5; // @[BTB.scala:44:47, :57:28] wire _nextPos_T_1 = _nextPos_T; // @[BTB.scala:44:{40,47}] wire [3:0] _GEN_2 = {1'h0, pos}; // @[BTB.scala:44:64, :57:28] wire [3:0] _nextPos_T_2 = _GEN_2 + 4'h1; // @[BTB.scala:44:64] wire [2:0] _nextPos_T_3 = _nextPos_T_2[2:0]; // @[BTB.scala:44:64] wire [2:0] nextPos = _nextPos_T_1 ? _nextPos_T_3 : 3'h0; // @[BTB.scala:44:{22,40,64}, :51:40] wire [3:0] _count_T_2 = _GEN_1 - 4'h1; // @[BTB.scala:43:44, :50:20] wire [2:0] _count_T_3 = _count_T_2[2:0]; // @[BTB.scala:50:20] wire _pos_T = \|pos; // @[BTB.scala:51:40, :57:28] wire _pos_T_1 = _pos_T; // @[BTB.scala:51:{33,40}] wire [3:0] _pos_T_2 = _GEN_2 - 4'h1; // @[BTB.scala:44:64, :51:50] wire [2:0] _pos_T_3 = _pos_T_2[2:0]; // @[BTB.scala:51:50] wire [2:0] _pos_T_4 = _pos_T_1 ? _pos_T_3 : 3'h5; // @[BTB.scala:51:{15,33,50}] wire [4:0] _T_5 = idxWritesEven ? idxPageReplEn[4:0] : tgtPageReplEn[4:0]; // @[BTB.scala:241:26, :247:26, :274:25, :280:24] wire [24:0] _T_8 = idxWritesEven ? r_btb_update_bits_pc[38:14] : io_req_bits_addr_0[38:14]; // @[Valid.scala:135:21] wire [4:0] _T_12 = idxWritesEven ? tgtPageReplEn[5:1] : idxPageReplEn[5:1]; // @[BTB.scala:241:26, :247:26, :274:25, :282:24] wire [24:0] _T_15 = idxWritesEven ? io_req_bits_addr_0[38:14] : r_btb_update_bits_pc[38:14]; // @[Valid.scala:135:21] wire _T_139 = io_ras_update_bits_cfiType_0 == 2'h2; // @[BTB.scala:187:7, :333:40] always @(posedge clock) begin // @[BTB.scala:187:7] if (r_btb_update_valid & waddr == 5'h0) begin // @[Valid.scala:135:21] idxs_0 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_0 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_0 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_0 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_0 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_0 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h1) begin // @[Valid.scala:135:21] idxs_1 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_1 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_1 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_1 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_1 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_1 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h2) begin // @[Valid.scala:135:21] idxs_2 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_2 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_2 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_2 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_2 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_2 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h3) begin // @[Valid.scala:135:21] idxs_3 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_3 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_3 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_3 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_3 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_3 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h4) begin // @[Valid.scala:135:21] idxs_4 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_4 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_4 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_4 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_4 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_4 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h5) begin // @[Valid.scala:135:21] idxs_5 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_5 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_5 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_5 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_5 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_5 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h6) begin // @[Valid.scala:135:21] idxs_6 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_6 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_6 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_6 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_6 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_6 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h7) begin // @[Valid.scala:135:21] idxs_7 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_7 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_7 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_7 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_7 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_7 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h8) begin // @[Valid.scala:135:21] idxs_8 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_8 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_8 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_8 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_8 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_8 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h9) begin // @[Valid.scala:135:21] idxs_9 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_9 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_9 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_9 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_9 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_9 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hA) begin // @[Valid.scala:135:21] idxs_10 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_10 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_10 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_10 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_10 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_10 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hB) begin // @[Valid.scala:135:21] idxs_11 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_11 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_11 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_11 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_11 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_11 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hC) begin // @[Valid.scala:135:21] idxs_12 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_12 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_12 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_12 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_12 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_12 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hD) begin // @[Valid.scala:135:21] idxs_13 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_13 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_13 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_13 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_13 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_13 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hE) begin // @[Valid.scala:135:21] idxs_14 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_14 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_14 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_14 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_14 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_14 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hF) begin // @[Valid.scala:135:21] idxs_15 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_15 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_15 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_15 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_15 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_15 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h10) begin // @[Valid.scala:135:21] idxs_16 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_16 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_16 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_16 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_16 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_16 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h11) begin // @[Valid.scala:135:21] idxs_17 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_17 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_17 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_17 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_17 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_17 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h12) begin // @[Valid.scala:135:21] idxs_18 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_18 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_18 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_18 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_18 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_18 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h13) begin // @[Valid.scala:135:21] idxs_19 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_19 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_19 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_19 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_19 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_19 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h14) begin // @[Valid.scala:135:21] idxs_20 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_20 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_20 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_20 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_20 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_20 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h15) begin // @[Valid.scala:135:21] idxs_21 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_21 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_21 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_21 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_21 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_21 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h16) begin // @[Valid.scala:135:21] idxs_22 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_22 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_22 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_22 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_22 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_22 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h17) begin // @[Valid.scala:135:21] idxs_23 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_23 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_23 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_23 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_23 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_23 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h18) begin // @[Valid.scala:135:21] idxs_24 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_24 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_24 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_24 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_24 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_24 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h19) begin // @[Valid.scala:135:21] idxs_25 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_25 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_25 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_25 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_25 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_25 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h1A) begin // @[Valid.scala:135:21] idxs_26 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_26 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_26 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_26 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_26 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_26 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h1B) begin // @[Valid.scala:135:21] idxs_27 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_27 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_27 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_27 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_27 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_27 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & _T_5[0]) // @[Valid.scala:135:21] pages_0 <= _T_8; // @[BTB.scala:203:18, :281:10] if (r_btb_update_valid & _T_12[0]) // @[Valid.scala:135:21] pages_1 <= _T_15; // @[BTB.scala:203:18, :283:10] if (r_btb_update_valid & _T_5[2]) // @[Valid.scala:135:21] pages_2 <= _T_8; // @[BTB.scala:203:18, :281:10] if (r_btb_update_valid & _T_12[2]) // @[Valid.scala:135:21] pages_3 <= _T_15; // @[BTB.scala:203:18, :283:10] if (r_btb_update_valid & _T_5[4]) // @[Valid.scala:135:21] pages_4 <= _T_8; // @[BTB.scala:203:18, :281:10] if (r_btb_update_valid & _T_12[4]) // @[Valid.scala:135:21] pages_5 <= _T_15; // @[BTB.scala:203:18, :283:10] if (io_btb_update_valid_0) begin // @[BTB.scala:187:7] r_btb_update_pipe_b_prediction_cfiType <= io_btb_update_bits_prediction_cfiType_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_taken <= io_btb_update_bits_prediction_taken_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_mask <= io_btb_update_bits_prediction_mask_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_bridx <= io_btb_update_bits_prediction_bridx_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_target <= io_btb_update_bits_prediction_target_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_entry <= io_btb_update_bits_prediction_entry_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_bht_history <= io_btb_update_bits_prediction_bht_history_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_bht_value <= io_btb_update_bits_prediction_bht_value_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_pc <= io_btb_update_bits_pc_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_target <= io_btb_update_bits_target_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_isValid <= io_btb_update_bits_isValid_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_br_pc <= io_btb_update_bits_br_pc_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_cfiType <= io_btb_update_bits_cfiType_0; // @[Valid.scala:142:26] end if (io_resp_valid_0) begin // @[BTB.scala:187:7] r_resp_pipe_b_cfiType <= io_resp_bits_cfiType_0; // @[Valid.scala:142:26] r_resp_pipe_b_taken <= io_resp_bits_taken_0; // @[Valid.scala:142:26] r_resp_pipe_b_mask <= io_resp_bits_mask_0; // @[Valid.scala:142:26] r_resp_pipe_b_bridx <= io_resp_bits_bridx_0; // @[Valid.scala:142:26] r_resp_pipe_b_target <= io_resp_bits_target_0; // @[Valid.scala:142:26] r_resp_pipe_b_entry <= io_resp_bits_entry_0; // @[Valid.scala:142:26] r_resp_pipe_b_bht_history <= io_resp_bits_bht_history_0; // @[Valid.scala:142:26] r_resp_pipe_b_bht_value <= io_resp_bits_bht_value_0; // @[Valid.scala:142:26] end if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h0) // @[BTB.scala:44:22, :45:20, :51:40, :58:26, :187:7, :332:32, :333:{40,58}] stack_0 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h1) // @[package.scala:39:86] stack_1 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h2) // @[package.scala:39:86] stack_2 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h3) // @[package.scala:39:86] stack_3 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h4) // @[BTB.scala:44:22, :45:20, :58:26, :187:7, :332:32, :333:{40,58}] stack_4 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h5) // @[BTB.scala:44:22, :45:20, :58:26, :187:7, :332:32, :333:{40,58}] stack_5 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (reset) begin // @[BTB.scala:187:7] pageValid <= 6'h0; // @[BTB.scala:204:26] isValid <= 28'h0; // @[BTB.scala:207:24] r_btb_update_pipe_v <= 1'h0; // @[Valid.scala:141:24] nextPageRepl <= 3'h0; // @[BTB.scala:51:40, :237:29] state_reg <= 27'h0; // @[Replacement.scala:168:70] r_resp_pipe_v <= 1'h0; // @[Valid.scala:141:24] history <= 8'h0; // @[BTB.scala:117:24] reset_waddr <= 10'h0; // @[BTB.scala:119:36] count <= 3'h0; // @[BTB.scala:51:40, :56:30] pos <= 3'h0; // @[BTB.scala:51:40, :57:28] end else begin // @[BTB.scala:187:7] if (r_btb_update_valid) // @[Valid.scala:135:21] pageValid <= _pageValid_T_1[5:0]; // @[BTB.scala:204:26, :284:{15,44}] if (io_flush_0) // @[BTB.scala:187:7] isValid <= 28'h0; // @[BTB.scala:207:24] else if (leftTwo_5 \| rightTwo_14 \| leftOne_13 & rightOne_26) // @[Misc.scala:183:{16,37,49,61}] isValid <= _isValid_T_5; // @[BTB.scala:207:24, :297:24] else if (r_btb_update_valid) // @[Valid.scala:135:21] isValid <= _isValid_T_3[27:0]; // @[BTB.scala:207:24, :269:{13,19}] r_btb_update_pipe_v <= io_btb_update_valid_0; // @[Valid.scala:141:24] if (r_btb_update_valid & (doIdxPageRepl \| doTgtPageRepl)) // @[Valid.scala:135:21] nextPageRepl <= _nextPageRepl_T_2; // @[BTB.scala:237:29, :252:24] if (r_resp_valid & r_resp_bits_taken \| r_btb_update_valid) // @[Valid.scala:135:21] state_reg <= _state_reg_T_92; // @[Replacement.scala:168:70, :202:12] r_resp_pipe_v <= io_resp_valid_0; // @[Valid.scala:141:24] if (io_bht_update_valid_0 & io_bht_update_bits_mispredict_0) // @[BTB.scala:187:7, :307:33, :310:32, :311:40] history <= io_bht_update_bits_branch_0 ? _history_T_3 : io_bht_update_bits_prediction_history_0; // @[BTB.scala:107:13, :110:{13,19}, :117:24, :187:7, :307:33, :313:46, :316:50] else if (io_bht_advance_valid_0) // @[BTB.scala:187:7] history <= _history_T_1; // @[BTB.scala:113:19, :117:24] if (resetting) // @[BTB.scala:120:27] reset_waddr <= _reset_waddr_T_1; // @[BTB.scala:119:36, :124:49] if (io_ras_update_valid_0) begin // @[BTB.scala:187:7] if (_T_139) begin // @[BTB.scala:333:40] if (count[2:1] != 2'h3) // @[BTB.scala:43:17, :56:30] count <= _count_T_1; // @[BTB.scala:43:44, :56:30] pos <= nextPos; // @[BTB.scala:44:22, :57:28] end else if ((&io_ras_update_bits_cfiType_0) & (\|count)) begin // @[BTB.scala:49:37, :50:11, :54:29, :56:30, :187:7, :335:{46,63}] count <= _count_T_3; // @[BTB.scala:50:20, :56:30] pos <= _pos_T_4; // @[BTB.scala:51:15, :57:28] end end end always @(posedge) table_512x1 table_ext ( // @[BTB.scala:116:26] .R0_addr (_res_res_value_T_7), // @[BTB.scala:88:20] .R0_en (1'h1), // @[BTB.scala:187:7] .R0_clk (clock), .R0_data (_table_ext_R0_data), .W0_addr (waddr_1[8:0]), // @[BTB.scala:122:31, :125:21] .W0_en (wen), // @[BTB.scala:121:29] .W0_clk (clock), .W0_data (wdata) // @[BTB.scala:123:31] ); // @[BTB.scala:116:26] assign io_resp_valid = io_resp_valid_0; // @[BTB.scala:187:7] assign io_resp_bits_cfiType = io_resp_bits_cfiType_0; // @[BTB.scala:187:7] assign io_resp_bits_taken = io_resp_bits_taken_0; // @[BTB.scala:187:7] assign io_resp_bits_mask = io_resp_bits_mask_0; // @[BTB.scala:187:7] assign io_resp_bits_bridx = io_resp_bits_bridx_0; // @[BTB.scala:187:7] assign io_resp_bits_target = io_resp_bits_target_0; // @[BTB.scala:187:7] assign io_resp_bits_entry = io_resp_bits_entry_0; // @[BTB.scala:187:7] assign io_resp_bits_bht_history = io_resp_bits_bht_history_0; // @[BTB.scala:187:7] assign io_resp_bits_bht_value = io_resp_bits_bht_value_0; // @[BTB.scala:187:7] assign io_ras_head_valid = io_ras_head_valid_0; // @[BTB.scala:187:7] assign io_ras_head_bits = io_ras_head_bits_0; // @[BTB.scala:187:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File btb.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} import scala.math.min case class BoomBTBParams( nSets: Int = 128, nWays: Int = 2, offsetSz: Int = 13, extendedNSets: Int = 128 ) class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { override val nSets = params.nSets override val nWays = params.nWays val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1 val offsetSz = params.offsetSz val extendedNSets = params.extendedNSets require(isPow2(nSets)) require(isPow2(extendedNSets) \|\| extendedNSets == 0) require(extendedNSets <= nSets) require(extendedNSets >= 1) class BTBEntry extends Bundle { val offset = SInt(offsetSz.W) val extended = Bool() } val btbEntrySz = offsetSz + 1 class BTBMeta extends Bundle { val is_br = Bool() val tag = UInt(tagSz.W) } val btbMetaSz = tagSz + 1 class BTBPredictMeta extends Bundle { val write_way = UInt(log2Ceil(nWays).W) } val s1_meta = Wire(new BTBPredictMeta) val f3_meta = RegNext(RegNext(s1_meta)) io.f3_meta := f3_meta.asUInt override val metaSz = s1_meta.asUInt.getWidth val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) } val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) } val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W)) val mems = (((0 until nWays) map ({w:Int => Seq( (f"btb_meta_way$w", nSets, bankWidth * btbMetaSz), (f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended))) val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) }) val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) }) val s1_req_rebtb = ebtb.read(s0_idx, s0_valid) val s1_req_tag = s1_idx >> log2Ceil(nSets) val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W)))) val s1_is_br = Wire(Vec(bankWidth, Bool())) val s1_is_jal = Wire(Vec(bankWidth, Bool())) val s1_hit_ohs = VecInit((0 until bankWidth) map { i => VecInit((0 until nWays) map { w => s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0) }) }) val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_\|\|_) } val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) } for (w <- 0 until bankWidth) { val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w) val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w) s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w) s1_resp(w).bits := Mux( entry_btb.extended, s1_req_rebtb, (s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt) s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br io.resp.f2(w) := io.resp_in(0).f2(w) io.resp.f3(w) := io.resp_in(0).f3(w) when (RegNext(s1_hits(w))) { io.resp.f2(w).predicted_pc := RegNext(s1_resp(w)) io.resp.f2(w).is_br := RegNext(s1_is_br(w)) io.resp.f2(w).is_jal := RegNext(s1_is_jal(w)) when (RegNext(s1_is_jal(w))) { io.resp.f2(w).taken := true.B } } when (RegNext(RegNext(s1_hits(w)))) { io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc) io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br) io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal) when (RegNext(RegNext(s1_is_jal(w)))) { io.resp.f3(w).taken := true.B } } } val alloc_way = if (nWays > 1) { val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0)) val l = log2Ceil(nWays) val nChunks = (r_metas.getWidth + l - 1) / l val chunks = (0 until nChunks) map { i => r_metas(min((i+1)l, r_metas.getWidth)-1, il) } chunks.reduce(_^_) } else { 0.U } s1_meta.write_way := Mux(s1_hits.reduce(_\|\|_), PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_\|_)), alloc_way) val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta) val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt val new_offset_value = (s1_update.bits.target.asSInt - (s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt) val offset_is_extended = (new_offset_value > max_offset_value \|\| new_offset_value < min_offset_value) val s1_update_wbtb_data = Wire(new BTBEntry) s1_update_wbtb_data.extended := offset_is_extended s1_update_wbtb_data.offset := new_offset_value val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) & Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update)) val s1_update_wmeta_mask = ((s1_update_wbtb_mask \| s1_update.bits.br_mask) & (Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) \| (Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts) ) ) val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta)) for (w <- 0 until bankWidth) { s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets)) s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w) } for (w <- 0 until nWays) { when (doing_reset \|\| s1_update_meta.write_way === w.U \|\| (w == 0 && nWays == 1).B) { btb(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }), VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wbtb_mask).asBools ) meta(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }), VecInit(s1_update_wmeta_data.map(_.asUInt))), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wmeta_mask).asBools ) } } when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) { ebtb.write(s1_update_idx, s1_update.bits.target) } }	module btb_1( // @[btb.scala:66:47] input [6:0] R0_addr, input R0_en, input R0_clk, output [55:0] R0_data, input [6:0] W0_addr, input W0_en, input W0_clk, input [55:0] W0_data, input [3:0] W0_mask ); btb_0_ext btb_0_ext ( // @[btb.scala:66:47] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data), .W0_mask (W0_mask) ); // @[btb.scala:66:47] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels / // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /* Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) \| t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }	module NoCMonitor_18( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_152( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_272 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_34( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_311 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_312 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_313 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_314 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_124( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File INToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val signedIn = Input(Bool()) val in = Input(Bits(intWidth.W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in); val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( intAsRawFloat.expWidth, intWidth, expWidth, sigWidth, flRoundOpt_sigMSBitAlwaysZero \| flRoundOpt_neverUnderflows )) roundAnyRawFNToRecFN.io.invalidExc := false.B roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := intAsRawFloat roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File rawFloatFromIN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ object rawFloatFromIN { def apply(signedIn: Bool, in: Bits): RawFloat = { val expWidth = log2Up(in.getWidth) + 1 //*** CHANGE THIS; CAN BE VERY LARGE: val extIntWidth = 1<<(expWidth - 1) val sign = signedIn && in(in.getWidth - 1) val absIn = Mux(sign, -in.asUInt, in.asUInt) val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) val adjustedNormDist = countLeadingZeros(extAbsIn) val sig = (extAbsIn<<adjustedNormDist)( extIntWidth - 1, extIntWidth - in.getWidth) val out = Wire(new RawFloat(expWidth, in.getWidth)) out.isNaN := false.B out.isInf := false.B out.isZero := ! sig(in.getWidth - 1) out.sign := sign out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext out.sig := sig out } }	module INToRecFN_i1_e8_s24_4(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_4 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_28( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_263 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_264 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_265 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_266 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File TLChannelCompactor.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLBeat(val beatWidth: Int) extends Bundle { val payload = UInt(beatWidth.W) val head = Bool() val tail = Bool() } abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper { override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_") val beatWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val beat = Decoupled(new TLBeat(beatWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) q.io.enq <> io.protocol val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.beat.valid := protocol.valid protocol.ready := io.beat.ready && (is_body \|\| !has_body) io.beat.bits.head := head && !is_body io.beat.bits.tail := tail && (is_body \|\| !has_body) io.beat.bits.payload := Mux(is_body, body, const) when (io.beat.fire && io.beat.bits.head) { is_body := true.B } when (io.beat.fire && io.beat.bits.tail) { is_body := false.B } } abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper { override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_") val beatWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val beat = Flipped(Decoupled(new TLBeat(beatWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) io.protocol <> protocol val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg) io.beat.ready := (is_const && !io.beat.bits.tail) \|\| protocol.ready protocol.valid := (!is_const \|\| io.beat.bits.tail) && io.beat.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.beat.bits.payload, body_fields) when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload } when (io.beat.fire && io.beat.bits.tail) { is_const := true.B } } class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) { has_body := edgeIn.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) } class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) { when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) { has_body := edgeOut.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) } class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) { when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) { has_body := edgeIn.hasData(protocol.bits) } class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p) class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) { has_body := edgeOut.hasData(protocol.bits) } class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p) class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) { has_body := edgeIn.hasData(protocol.bits) } class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p) File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLAToBeat_SerialRAM_a64d64s8k8z8c( // @[TLChannelCompactor.scala:108:7] input clock, // @[TLChannelCompactor.scala:108:7] input reset, // @[TLChannelCompactor.scala:108:7] output io_protocol_ready, // @[TLChannelCompactor.scala:40:14] input io_protocol_valid, // @[TLChannelCompactor.scala:40:14] input [2:0] io_protocol_bits_opcode, // @[TLChannelCompactor.scala:40:14] input [2:0] io_protocol_bits_param, // @[TLChannelCompactor.scala:40:14] input [7:0] io_protocol_bits_size, // @[TLChannelCompactor.scala:40:14] input [7:0] io_protocol_bits_source, // @[TLChannelCompactor.scala:40:14] input [63:0] io_protocol_bits_address, // @[TLChannelCompactor.scala:40:14] input [7:0] io_protocol_bits_mask, // @[TLChannelCompactor.scala:40:14] input [63:0] io_protocol_bits_data, // @[TLChannelCompactor.scala:40:14] input io_protocol_bits_corrupt, // @[TLChannelCompactor.scala:40:14] input io_beat_ready, // @[TLChannelCompactor.scala:40:14] output io_beat_valid, // @[TLChannelCompactor.scala:40:14] output [85:0] io_beat_bits_payload, // @[TLChannelCompactor.scala:40:14] output io_beat_bits_head, // @[TLChannelCompactor.scala:40:14] output io_beat_bits_tail // @[TLChannelCompactor.scala:40:14] ); wire [8:0] _GEN; // @[TLChannelCompactor.scala:109:{45,69}] wire _q_io_deq_valid; // @[TLChannelCompactor.scala:47:17] wire [2:0] _q_io_deq_bits_opcode; // @[TLChannelCompactor.scala:47:17] wire [2:0] _q_io_deq_bits_param; // @[TLChannelCompactor.scala:47:17] wire [7:0] _q_io_deq_bits_size; // @[TLChannelCompactor.scala:47:17] wire [7:0] _q_io_deq_bits_source; // @[TLChannelCompactor.scala:47:17] wire [63:0] _q_io_deq_bits_address; // @[TLChannelCompactor.scala:47:17] wire [7:0] _q_io_deq_bits_mask; // @[TLChannelCompactor.scala:47:17] wire [63:0] _q_io_deq_bits_data; // @[TLChannelCompactor.scala:47:17] wire _q_io_deq_bits_corrupt; // @[TLChannelCompactor.scala:47:17] wire [266:0] _tail_beats1_decode_T = 267'hFFF << _q_io_deq_bits_size; // @[TLChannelCompactor.scala:47:17] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3]); // @[TLChannelCompactor.scala:47:17] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TLChannelCompactor.scala:60:24] wire _io_beat_bits_tail_T = _GEN == 9'h0; // @[TLChannelCompactor.scala:109:{45,69}] wire q_io_deq_ready = io_beat_ready & (is_body \| _io_beat_bits_tail_T); // @[TLChannelCompactor.scala:60:24, :62:{35,47}, :109:{45,69}] wire io_beat_bits_head_0 = head & ~is_body; // @[TLChannelCompactor.scala:60:24, :64:{35,38}] wire io_beat_bits_tail_0 = (tail_counter == 9'h1 \| tail_beats1 == 9'h0) & (is_body \| _io_beat_bits_tail_T); // @[TLChannelCompactor.scala:60:24, :65:{35,47}, :109:{45,69}] assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[TLChannelCompactor.scala:47:17, :109:{45,49,69}] wire _GEN_0 = io_beat_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TLChannelCompactor.scala:108:7] if (reset) begin // @[TLChannelCompactor.scala:108:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TLChannelCompactor.scala:60:24, :108:7] end else begin // @[TLChannelCompactor.scala:108:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3])) : head_counter - 9'h1; // @[TLChannelCompactor.scala:47:17] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN_0 & io_beat_bits_tail_0) & (_GEN_0 & io_beat_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundRawFNToRecFN_e8_s24_27( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_27 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File IterativeTrapCheck.scala: package saturn.frontend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.diplomacy._ import saturn.common._ class IndexMaskAccess(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val in = Input(Bool()) val inst = Input(new VectorIssueInst) val index_access = Flipped(new VectorIndexAccessIO) val mask_access = Flipped(new VectorMaskAccessIO) val access = new Bundle { val ready = Output(Bool()) val eidx = Input(UInt(log2Ceil(maxVLMax).W)) val index = Output(UInt(64.W)) val mask = Output(Bool()) } val pop = Input(Valid(UInt(log2Ceil(maxVLMax).W))) val flush = Input(Bool()) }) val valid = RegInit(false.B) val eidx = Reg(UInt(log2Ceil(maxVLMax).W)) // This all works only with pow2 buffers and eidx starting at 0 val valids = Reg(Vec(4, Bool())) val indices = Reg(Vec(4, UInt(64.W))) val masks = Reg(Vec(4, Bool())) when (io.in) { assert(!valid) valid := true.B eidx := 0.U valids.foreach(_ := false.B) } val needs_index = io.inst.mop.isOneOf(mopOrdered, mopUnordered) val needs_mask = !io.inst.vm val index_ready = io.index_access.ready \|\| !needs_index val mask_ready = io.mask_access.ready \|\| !needs_mask io.index_access.valid := valid && needs_index && !valids(eidx(1,0)) io.mask_access.valid := valid && needs_mask && !valids(eidx(1,0)) io.index_access.vrs := io.inst.rs2 io.index_access.eidx := eidx io.index_access.eew := io.inst.mem_idx_size io.mask_access.eidx := eidx when (valid && index_ready && mask_ready && !valids(eidx(1,0))) { val next_eidx = eidx +& 1.U eidx := eidx + 1.U when (next_eidx === io.inst.vconfig.vl) { valid := false.B } valids(eidx(1,0)) := true.B indices(eidx(1,0)) := io.index_access.idx masks(eidx(1,0)) := io.mask_access.mask } io.access.ready := valids(io.access.eidx(1,0)) io.access.index := indices(io.access.eidx(1,0)) io.access.mask := masks(io.access.eidx(1,0)) when (io.pop.fire) { valids(io.pop.bits(1,0)) := false.B } when (io.flush) { valid := false.B } } class IterativeTrapCheck(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val status = Input(new MStatus) val in = Input(Valid(new VectorIssueInst)) val busy = Output(Bool()) val s0_tlb_req = Valid(new TLBReq(3)) val s1_tlb_req = Valid(new TLBReq(3)) val tlb_resp = Input(new TLBResp) val retire = Output(Bool()) val pc = Output(UInt(vaddrBitsExtended.W)) val vstart = Valid(UInt(log2Ceil(maxVLMax).W)) val vconfig = Valid(new VConfig) val xcpt = Valid(new Bundle { val cause = UInt(xLen.W) val tval = UInt(coreMaxAddrBits.W) }) val inst = Output(new VectorIssueInst) val issue = Decoupled(new VectorIssueInst) val index_access = Flipped(new VectorIndexAccessIO) val mask_access = Flipped(new VectorMaskAccessIO) }) val replay_kill = WireInit(false.B) def nextPage(addr: UInt) = ((addr + (1 << pgIdxBits).U) >> pgIdxBits) << pgIdxBits val valid = RegInit(false.B) val seg_hi = Reg(Bool()) val inst = Reg(new VectorIssueInst) val eidx = Reg(UInt(log2Ceil(maxVLMax).W)) val addr = Reg(UInt(vaddrBitsExtended.W)) val tlb_backoff = RegInit(0.U(2.W)) when (tlb_backoff =/= 0.U) { tlb_backoff := tlb_backoff - 1.U } val im_access = Module(new IndexMaskAccess) im_access.io.in := io.in.valid im_access.io.inst := inst im_access.io.index_access <> io.index_access im_access.io.mask_access <> io.mask_access when (io.in.valid) { assert(!valid) valid := true.B seg_hi := false.B inst := io.in.bits eidx := 0.U addr := io.in.bits.rs1_data } val stride = MuxLookup(inst.mop, 0.U)(Seq( (mopUnit -> ((inst.seg_nf +& 1.U) << inst.mem_elem_size)), (mopStrided -> inst.rs2_data) )) val indexed = inst.mop.isOneOf(mopOrdered, mopUnordered) val index_ready = !indexed \|\| im_access.io.access.ready val mask_ready = inst.vm \|\| im_access.io.access.ready val index = Mux(indexed, im_access.io.access.index & eewBitMask(inst.mem_idx_size), 0.U) val base = Mux(indexed, inst.rs1_data, addr) val indexaddr = base + index val tlb_addr = Mux(seg_hi, nextPage(indexaddr), indexaddr) val seg_nf_consumed = ((1 << pgIdxBits).U - Mux(seg_hi, indexaddr, tlb_addr)(pgIdxBits-1,0)) >> inst.mem_elem_size val seg_single_page = seg_nf_consumed >= (inst.seg_nf +& 1.U) val masked = !im_access.io.access.mask && !inst.vm val tlb_valid = eidx < inst.vconfig.vl && eidx >= inst.vstart && !masked val ff = inst.umop === lumopFF && inst.mop === mopUnit io.busy := valid io.inst := inst im_access.io.access.eidx := eidx io.s0_tlb_req.valid := tlb_valid && tlb_backoff === 0.U && index_ready && mask_ready io.s0_tlb_req.bits.vaddr := tlb_addr io.s0_tlb_req.bits.passthrough := false.B io.s0_tlb_req.bits.size := inst.mem_elem_size io.s0_tlb_req.bits.cmd := Mux(inst.opcode(5), M_XWR, M_XRD) io.s0_tlb_req.bits.prv := io.status.prv io.s0_tlb_req.bits.v := io.status.v io.s1_tlb_req.valid := RegEnable(io.s0_tlb_req.valid, false.B, valid) io.s1_tlb_req.bits := RegEnable(io.s0_tlb_req.bits, valid) val replay_fire = valid && eidx < inst.vconfig.vl && tlb_backoff === 0.U && index_ready && mask_ready when (replay_fire) { when (seg_hi \|\| seg_single_page \|\| inst.seg_nf === 0.U) { eidx := eidx + 1.U addr := addr + stride seg_hi := false.B } .otherwise { seg_hi := true.B } } val s1_valid = RegNext(replay_fire && !replay_kill, false.B) val s1_eidx = RegEnable(eidx, valid) val s1_masked = RegEnable(masked, valid) val s1_seg_hi = RegEnable(seg_hi, valid) val s1_base = RegEnable(base, valid) val s1_tlb_valid = RegEnable(tlb_valid, valid) val s1_tlb_addr = RegEnable(tlb_addr, valid) val s1_seg_nf_consumed = RegEnable(seg_nf_consumed, valid) val s1_seg_single_page = RegEnable(seg_single_page, valid) when (io.tlb_resp.miss && s1_valid && tlb_backoff === 0.U) { tlb_backoff := 3.U } val tlb_resp = WireInit(io.tlb_resp) when (!s1_tlb_valid) { tlb_resp.miss := false.B } val xcpts = Seq( (tlb_resp.pf.st, Causes.store_page_fault.U), (tlb_resp.pf.ld, Causes.load_page_fault.U), (tlb_resp.gf.st, Causes.store_guest_page_fault.U), (tlb_resp.gf.ld, Causes.load_guest_page_fault.U), (tlb_resp.ae.st, Causes.store_access.U), (tlb_resp.ae.ld, Causes.load_access.U), (tlb_resp.ma.st, Causes.misaligned_store.U), (tlb_resp.ma.ld, Causes.misaligned_load.U) ) val xcpt = xcpts.map(_._1).orR && s1_eidx >= inst.vstart && !s1_masked val cause = PriorityMux(xcpts) io.issue.valid := false.B io.issue.bits := inst io.issue.bits.vstart := s1_eidx io.issue.bits.vconfig.vl := s1_eidx +& 1.U io.issue.bits.segend := inst.seg_nf io.issue.bits.segstart := 0.U io.issue.bits.page := tlb_resp.paddr >> pgIdxBits io.xcpt.valid := false.B io.pc := inst.pc io.xcpt.bits.cause := cause io.xcpt.bits.tval := s1_tlb_addr io.vstart.valid := false.B io.vstart.bits := s1_eidx io.retire := false.B io.vconfig.valid := false.B io.vconfig.bits := inst.vconfig io.vconfig.bits.vl := s1_eidx im_access.io.pop.valid := false.B im_access.io.pop.bits := s1_eidx im_access.io.flush := false.B when (s1_valid) { io.issue.valid := !tlb_resp.miss && !xcpt && s1_eidx >= inst.vstart && !s1_masked when (inst.seg_nf =/= 0.U && !s1_seg_single_page) { when (!s1_seg_hi) { io.issue.bits.segend := s1_seg_nf_consumed - 1.U } .otherwise { io.issue.bits.segstart := s1_seg_nf_consumed } } when (s1_seg_hi \|\| s1_seg_single_page \|\| inst.seg_nf === 0.U) { im_access.io.pop.valid := true.B } when (tlb_resp.miss \|\| !io.issue.ready) { tlb_backoff := 3.U replay_kill := true.B eidx := s1_eidx addr := s1_base seg_hi := s1_seg_hi im_access.io.pop.valid := false.B } .elsewhen (xcpt) { val ff_nofault = ff && s1_eidx =/= 0.U valid := false.B replay_kill := true.B io.retire := ff_nofault io.xcpt.valid := !ff_nofault io.vstart.valid := !ff_nofault io.vconfig.valid := ff_nofault im_access.io.flush := true.B } .elsewhen ((s1_eidx +& 1.U) === inst.vconfig.vl && (s1_seg_hi \|\| s1_seg_single_page \|\| inst.seg_nf === 0.U)) { valid := false.B replay_kill := true.B io.retire := true.B io.vstart.valid := true.B io.vstart.bits := 0.U im_access.io.flush := true.B } } }	module IterativeTrapCheck( // @[IterativeTrapCheck.scala:83:7] input clock, // @[IterativeTrapCheck.scala:83:7] input reset, // @[IterativeTrapCheck.scala:83:7] input [1:0] io_status_prv, // @[IterativeTrapCheck.scala:84:14] input io_in_valid, // @[IterativeTrapCheck.scala:84:14] input [39:0] io_in_bits_pc, // @[IterativeTrapCheck.scala:84:14] input [31:0] io_in_bits_bits, // @[IterativeTrapCheck.scala:84:14] input [7:0] io_in_bits_vconfig_vl, // @[IterativeTrapCheck.scala:84:14] input io_in_bits_vconfig_vtype_vill, // @[IterativeTrapCheck.scala:84:14] input [54:0] io_in_bits_vconfig_vtype_reserved, // @[IterativeTrapCheck.scala:84:14] input io_in_bits_vconfig_vtype_vma, // @[IterativeTrapCheck.scala:84:14] input io_in_bits_vconfig_vtype_vta, // @[IterativeTrapCheck.scala:84:14] input [2:0] io_in_bits_vconfig_vtype_vsew, // @[IterativeTrapCheck.scala:84:14] input io_in_bits_vconfig_vtype_vlmul_sign, // @[IterativeTrapCheck.scala:84:14] input [1:0] io_in_bits_vconfig_vtype_vlmul_mag, // @[IterativeTrapCheck.scala:84:14] input [6:0] io_in_bits_vstart, // @[IterativeTrapCheck.scala:84:14] input [63:0] io_in_bits_rs1_data, // @[IterativeTrapCheck.scala:84:14] input [63:0] io_in_bits_rs2_data, // @[IterativeTrapCheck.scala:84:14] input [2:0] io_in_bits_rm, // @[IterativeTrapCheck.scala:84:14] input [1:0] io_in_bits_emul, // @[IterativeTrapCheck.scala:84:14] input [1:0] io_in_bits_mop, // @[IterativeTrapCheck.scala:84:14] output io_busy, // @[IterativeTrapCheck.scala:84:14] output io_s0_tlb_req_valid, // @[IterativeTrapCheck.scala:84:14] output [39:0] io_s0_tlb_req_bits_vaddr, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_s0_tlb_req_bits_size, // @[IterativeTrapCheck.scala:84:14] output [4:0] io_s0_tlb_req_bits_cmd, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_s0_tlb_req_bits_prv, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_miss, // @[IterativeTrapCheck.scala:84:14] input [31:0] io_tlb_resp_paddr, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_pf_ld, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_pf_st, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_ae_ld, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_ae_st, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_ma_ld, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_ma_st, // @[IterativeTrapCheck.scala:84:14] output io_retire, // @[IterativeTrapCheck.scala:84:14] output [39:0] io_pc, // @[IterativeTrapCheck.scala:84:14] output io_vstart_valid, // @[IterativeTrapCheck.scala:84:14] output [6:0] io_vstart_bits, // @[IterativeTrapCheck.scala:84:14] output io_vconfig_valid, // @[IterativeTrapCheck.scala:84:14] output [7:0] io_vconfig_bits_vl, // @[IterativeTrapCheck.scala:84:14] output io_vconfig_bits_vtype_vill, // @[IterativeTrapCheck.scala:84:14] output [54:0] io_vconfig_bits_vtype_reserved, // @[IterativeTrapCheck.scala:84:14] output io_vconfig_bits_vtype_vma, // @[IterativeTrapCheck.scala:84:14] output io_vconfig_bits_vtype_vta, // @[IterativeTrapCheck.scala:84:14] output [2:0] io_vconfig_bits_vtype_vsew, // @[IterativeTrapCheck.scala:84:14] output io_vconfig_bits_vtype_vlmul_sign, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_vconfig_bits_vtype_vlmul_mag, // @[IterativeTrapCheck.scala:84:14] output io_xcpt_valid, // @[IterativeTrapCheck.scala:84:14] output [63:0] io_xcpt_bits_cause, // @[IterativeTrapCheck.scala:84:14] output [39:0] io_xcpt_bits_tval, // @[IterativeTrapCheck.scala:84:14] output [31:0] io_inst_bits, // @[IterativeTrapCheck.scala:84:14] input io_issue_ready, // @[IterativeTrapCheck.scala:84:14] output io_issue_valid, // @[IterativeTrapCheck.scala:84:14] output [31:0] io_issue_bits_bits, // @[IterativeTrapCheck.scala:84:14] output [7:0] io_issue_bits_vconfig_vl, // @[IterativeTrapCheck.scala:84:14] output [2:0] io_issue_bits_vconfig_vtype_vsew, // @[IterativeTrapCheck.scala:84:14] output io_issue_bits_vconfig_vtype_vlmul_sign, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_issue_bits_vconfig_vtype_vlmul_mag, // @[IterativeTrapCheck.scala:84:14] output [6:0] io_issue_bits_vstart, // @[IterativeTrapCheck.scala:84:14] output [2:0] io_issue_bits_segstart, // @[IterativeTrapCheck.scala:84:14] output [2:0] io_issue_bits_segend, // @[IterativeTrapCheck.scala:84:14] output [63:0] io_issue_bits_rs1_data, // @[IterativeTrapCheck.scala:84:14] output [63:0] io_issue_bits_rs2_data, // @[IterativeTrapCheck.scala:84:14] output [19:0] io_issue_bits_page, // @[IterativeTrapCheck.scala:84:14] output [2:0] io_issue_bits_rm, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_issue_bits_emul, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_issue_bits_mop, // @[IterativeTrapCheck.scala:84:14] input io_index_access_ready, // @[IterativeTrapCheck.scala:84:14] output io_index_access_valid, // @[IterativeTrapCheck.scala:84:14] output [4:0] io_index_access_vrs, // @[IterativeTrapCheck.scala:84:14] output [7:0] io_index_access_eidx, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_index_access_eew, // @[IterativeTrapCheck.scala:84:14] input [63:0] io_index_access_idx, // @[IterativeTrapCheck.scala:84:14] input io_mask_access_ready, // @[IterativeTrapCheck.scala:84:14] output io_mask_access_valid, // @[IterativeTrapCheck.scala:84:14] output [7:0] io_mask_access_eidx, // @[IterativeTrapCheck.scala:84:14] input io_mask_access_mask // @[IterativeTrapCheck.scala:84:14] ); wire _im_access_io_access_ready; // @[IterativeTrapCheck.scala:118:25] wire [63:0] _im_access_io_access_index; // @[IterativeTrapCheck.scala:118:25] wire _im_access_io_access_mask; // @[IterativeTrapCheck.scala:118:25] reg valid; // @[IterativeTrapCheck.scala:110:23] reg seg_hi; // @[IterativeTrapCheck.scala:111:19] reg [39:0] inst_pc; // @[IterativeTrapCheck.scala:112:19] reg [31:0] inst_bits; // @[IterativeTrapCheck.scala:112:19] reg [7:0] inst_vconfig_vl; // @[IterativeTrapCheck.scala:112:19] reg inst_vconfig_vtype_vill; // @[IterativeTrapCheck.scala:112:19] reg [54:0] inst_vconfig_vtype_reserved; // @[IterativeTrapCheck.scala:112:19] reg inst_vconfig_vtype_vma; // @[IterativeTrapCheck.scala:112:19] reg inst_vconfig_vtype_vta; // @[IterativeTrapCheck.scala:112:19] reg [2:0] inst_vconfig_vtype_vsew; // @[IterativeTrapCheck.scala:112:19] reg inst_vconfig_vtype_vlmul_sign; // @[IterativeTrapCheck.scala:112:19] reg [1:0] inst_vconfig_vtype_vlmul_mag; // @[IterativeTrapCheck.scala:112:19] reg [6:0] inst_vstart; // @[IterativeTrapCheck.scala:112:19] reg [63:0] inst_rs1_data; // @[IterativeTrapCheck.scala:112:19] reg [63:0] inst_rs2_data; // @[IterativeTrapCheck.scala:112:19] reg [2:0] inst_rm; // @[IterativeTrapCheck.scala:112:19] reg [1:0] inst_emul; // @[IterativeTrapCheck.scala:112:19] reg [1:0] inst_mop; // @[IterativeTrapCheck.scala:112:19] reg [6:0] eidx; // @[IterativeTrapCheck.scala:113:19] reg [39:0] addr; // @[IterativeTrapCheck.scala:114:19] reg [1:0] tlb_backoff; // @[IterativeTrapCheck.scala:115:28]
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid \|\| io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }	module PriorityQueueStage_188( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToIN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.log2Up import scala.math._ import consts._ class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module { override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}" val io = IO(new Bundle { val in = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val signedOut = Input(Bool()) val out = Output(Bits(intWidth.W)) val intExceptionFlags = Output(Bits(3.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in) val magGeOne = rawIn.sExp(expWidth) val posExp = rawIn.sExp(expWidth - 1, 0) val magJustBelowOne = !magGeOne && posExp.andR //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) /------------------------------------------------------------------------ \| Assuming the input floating-point value is not a NaN, its magnitude is \| at least 1, and it is not obviously so large as to lead to overflow, \| convert its significand to fixed-point (i.e., with the binary point in a \| fixed location). For a non-NaN input with a magnitude less than 1, this \| expression contrives to ensure that the integer bits of 'alignedSig' \| will all be zeros. ------------------------------------------------------------------------/ val shiftedSig = (magGeOne ## rawIn.sig(sigWidth - 2, 0))<< Mux(magGeOne, rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0), 0.U ) val alignedSig = (shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR val unroundedInt = 0.U(intWidth.W) \| alignedSig>>2 val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero) val roundIncr_near_even = (magGeOne && (alignedSig(2, 1).andR \|\| alignedSig(1, 0).andR)) \|\| (magJustBelowOne && alignedSig(1, 0).orR) val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) \|\| magJustBelowOne val roundIncr = (roundingMode_near_even && roundIncr_near_even ) \|\| (roundingMode_near_maxMag && roundIncr_near_maxMag) \|\| ((roundingMode_min \|\| roundingMode_odd) && (rawIn.sign && common_inexact)) \|\| (roundingMode_max && (!rawIn.sign && common_inexact)) val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt) val roundedInt = Mux(roundIncr ^ rawIn.sign, complUnroundedInt + 1.U, complUnroundedInt ) \| (roundingMode_odd && common_inexact) val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U) // CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM //* 'unroundedInt'?: val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr val common_overflow = Mux(magGeOne, (posExp >= intWidth.U) \|\| Mux(io.signedOut, Mux(rawIn.sign, magGeOne_atOverflowEdge && (unroundedInt(intWidth - 2, 0).orR \|\| roundIncr), magGeOne_atOverflowEdge \|\| ((posExp === (intWidth - 2).U) && roundCarryBut2) ), rawIn.sign \|\| (magGeOne_atOverflowEdge && unroundedInt(intWidth - 2) && roundCarryBut2) ), !io.signedOut && rawIn.sign && roundIncr ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val invalidExc = rawIn.isNaN \|\| rawIn.isInf val overflow = !invalidExc && common_overflow val inexact = !invalidExc && !common_overflow && common_inexact val excSign = !rawIn.isNaN && rawIn.sign val excOut = Mux((io.signedOut === excSign), (BigInt(1)<<(intWidth - 1)).U, 0.U ) \| Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U) io.out := Mux(invalidExc \|\| common_overflow, excOut, roundedInt) io.intExceptionFlags := invalidExc ## overflow ## inexact }	module RecFNToIN_e11_s53_i32( // @[RecFNToIN.scala:46:7] input [64:0] io_in, // @[RecFNToIN.scala:49:16] input [2:0] io_roundingMode, // @[RecFNToIN.scala:49:16] input io_signedOut, // @[RecFNToIN.scala:49:16] output [31:0] io_out, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire rawIn_isNaN = (&(io_in[63:62])) & io_in[61]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}] wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52])); // @[RecFNToIN.scala:61:30, :62:28, :63:{27,37,47}] wire roundingMode_odd = io_roundingMode == 3'h6; // @[RecFNToIN.scala:72:53] wire [83:0] shiftedSig = {31'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[56:52] : 5'h0); // @[rawFloatFromRecFN.scala:61:49] wire [1:0] _roundIncr_near_even_T_6 = {shiftedSig[51], \|(shiftedSig[50:0])}; // @[RecFNToIN.scala:83:49, :89:{51,69}, :92:50] wire common_inexact = io_in[63] ? (\|_roundIncr_near_even_T_6) : (\|(io_in[63:61])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}] wire roundIncr = io_roundingMode == 3'h0 & (io_in[63] & ((&(shiftedSig[52:51])) \| (&_roundIncr_near_even_T_6)) \| magJustBelowOne & (\|_roundIncr_near_even_T_6)) \| io_roundingMode == 3'h4 & (io_in[63] & shiftedSig[51] \| magJustBelowOne) \| (io_roundingMode == 3'h2 \| roundingMode_odd) & io_in[64] & common_inexact \| io_roundingMode == 3'h3 & ~(io_in[64]) & common_inexact; // @[rawFloatFromRecFN.scala:52:53, :59:25] wire [31:0] complUnroundedInt = {32{io_in[64]}} ^ shiftedSig[83:52]; // @[rawFloatFromRecFN.scala:59:25] wire [31:0] _roundedInt_T_3 = roundIncr ^ io_in[64] ? complUnroundedInt + 32'h1 : complUnroundedInt; // @[rawFloatFromRecFN.scala:59:25] wire magGeOne_atOverflowEdge = io_in[62:52] == 11'h1F; // @[RecFNToIN.scala:62:28, :110:43] wire roundCarryBut2 = (&(shiftedSig[81:52])) & roundIncr; // @[RecFNToIN.scala:83:49, :90:52, :98:61, :99:61, :101:46, :113:{38,56,61}] wire common_overflow = io_in[63] ? (\|(io_in[62:57])) \| (io_signedOut ? (io_in[64] ? magGeOne_atOverflowEdge & ((\|(shiftedSig[82:52])) \| roundIncr) : magGeOne_atOverflowEdge \| io_in[62:52] == 11'h1E & roundCarryBut2) : io_in[64] \| magGeOne_atOverflowEdge & shiftedSig[82] & roundCarryBut2) : ~io_signedOut & io_in[64] & roundIncr; // @[rawFloatFromRecFN.scala:59:25] wire invalidExc = rawIn_isNaN \| (&(io_in[63:62])) & ~(io_in[61]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}, :57:{33,36}] wire excSign = ~rawIn_isNaN & io_in[64]; // @[rawFloatFromRecFN.scala:56:33, :59:25] assign io_out = invalidExc \| common_overflow ? {io_signedOut == excSign, {31{~excSign}}} : {_roundedInt_T_3[31:1], _roundedInt_T_3[0] \| roundingMode_odd & common_inexact}; // @[RecFNToIN.scala:46:7, :72:53, :92:29, :105:12, :108:{11,31}, :115:12, :133:34, :137:32, :139:27, :142:11, :143:{12,13}, :145:{18,30}] assign io_intExceptionFlags = {invalidExc, ~invalidExc & common_overflow, ~invalidExc & ~common_overflow & common_inexact}; // @[RecFNToIN.scala:46:7, :92:29, :115:12, :133:34, :134:{20,32}, :135:{32,35,52}, :146:52] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_223( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File TraceGen.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. // This file was originally written by Matthew Naylor, University of // Cambridge, based on code already present in the groundtest repo. // // This software was partly developed by the University of Cambridge // Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 // ("CTSRD"), as part of the DARPA CRASH research programme. // // This software was partly developed by the University of Cambridge // Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 // ("MRC2"), as part of the DARPA MRC research programme. // // This software was partly developed by the University of Cambridge // Computer Laboratory as part of the Rigorous Engineering of // Mainstream Systems (REMS) project, funded by EPSRC grant // EP/K008528/1. package freechips.rocketchip.groundtest import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem.{HierarchicalElementCrossingParamsLike, CanAttachTile} import freechips.rocketchip.util._ import freechips.rocketchip.prci.{ClockSinkParameters, ClockCrossingType} // ======= // Outline // ======= // Generate memory traces that result from random sequences of memory // operations. These traces can then be validated by an external // tool. A trace is a simply sequence of memory requests and // responses. // ========================== // Trace-generator parameters // ========================== // Compile-time parameters: // // * The id of the generator (there may be more than one in a // multi-core system). // // * The total number of generators present in the system. // // * The desired number of requests to be sent by each generator. // // * A bag of physical addresses, shared by all cores, from which an // address can be drawn when generating a fresh request. // // * A number of random 'extra addresses', local to each core, from // which an address can be drawn when generating a fresh request. // (This is a way to generate a wider range of addresses without having // to repeatedly recompile with a different address bag.) case class TraceGenParams( wordBits: Int, addrBits: Int, addrBag: List[BigInt], maxRequests: Int, memStart: BigInt, numGens: Int, dcache: Option[DCacheParams] = Some(DCacheParams()), tileId: Int = 0 ) extends InstantiableTileParams[TraceGenTile] with GroundTestTileParams { def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): TraceGenTile = { new TraceGenTile(this, crossing, lookup) } val blockerCtrlAddr = None val baseName = "tracegentile" val uniqueName = s"${baseName}_$tileId" val clockSinkParams = ClockSinkParameters() } trait HasTraceGenParams { implicit val p: Parameters val params: TraceGenParams val pAddrBits = params.addrBits val numGens = params.numGens val numReqsPerGen = params.maxRequests val memStart = params.memStart val memRespTimeout = 8192 val numBitsInWord = params.wordBits val numBytesInWord = numBitsInWord / 8 val numBitsInWordOffset = log2Up(numBytesInWord) val addressBag = params.addrBag val addressBagLen = addressBag.length val logAddressBagLen = log2Up(addressBagLen) val genExtraAddrs = false val logNumExtraAddrs = 1 val numExtraAddrs = 1 << logNumExtraAddrs val maxTags = 8 require(numBytesInWord * 8 == numBitsInWord) require((1 << logAddressBagLen) == addressBagLen) } case class TraceGenTileAttachParams( tileParams: TraceGenParams, crossingParams: HierarchicalElementCrossingParamsLike ) extends CanAttachTile { type TileType = TraceGenTile val lookup: LookupByHartIdImpl = HartsWontDeduplicate(tileParams) } // ============ // Trace format // ============ // Let <id> denote a generator id; // <addr> denote an address (in hex); // <data> denote a value that is stored at an address; // <tag> denote a unique request/response id; // and <time> denote an integer representing a cycle-count. // Each line in the trace takes one of the following formats. // // <id>: load-req <addr> #<tag> @<time> // <id>: load-reserve-req <addr> #<tag> @<time> // <id>: store-req <data> <addr> #<tag> @<time> // <id>: store-cond-req <data> <addr> #<tag> @<time> // <id>: swap-req <data> <addr> #<tag> @<time> // <id>: resp <data> #<tag> @<time> // <id>: fence-req @<time> // <id>: fence-resp @<time> // NOTE: The (address, value) pair of every generated store is unique, // i.e. the same value is never written to the same address twice. // This aids trace validation. // ============ // Random seeds // ============ // The generator employs "unitialised registers" to seed its PRNGs; // these are randomly initialised by the C++ backend. This means that // the "-s" command-line argument to the Rocket emulator can be used // to generate new traces, or to replay specific ones. // =========== // Tag manager // =========== // This is used to obtain unique tags for memory requests: each // request must carry a unique tag since responses can come back // out-of-order. // // The tag manager can be viewed as a set of tags. The user can take // a tag out of the set (if there is one available) and later put it // back. class TagMan(val logNumTags : Int) extends Module { val io = IO(new Bundle { // Is there a tag available? val available = Output(Bool()) // If so, which one? val tagOut = Output(UInt(logNumTags.W)) // User pulses this to take the currently available tag val take = Input(Bool()) // User pulses this to put a tag back val put = Input(Bool()) // And the tag put back is val tagIn = Input(UInt((logNumTags.W))) }) // Total number of tags available val numTags = 1 << logNumTags // For each tag, record whether or not it is in use val inUse = List.fill(numTags)(RegInit(false.B)) // Mapping from each tag to its 'inUse' bit val inUseMap = (0 to numTags-1).map(i => i.U).zip(inUse) // Next tag to offer val nextTag = RegInit(0.U(logNumTags.W)) io.tagOut := nextTag // Is the next tag available? io.available := ~MuxLookup(nextTag, true.B)(inUseMap) // When user takes a tag when (io.take) { for ((i, b) <- inUseMap) { when (i === nextTag) { b := true.B } } nextTag := nextTag + 1.U } // When user puts a tag back when (io.put) { for ((i, b) <- inUseMap) { when (i === io.tagIn) { b := false.B } } } } // =============== // Trace generator // =============== class TraceGenerator(val params: TraceGenParams)(implicit val p: Parameters) extends Module with HasTraceGenParams { val io = IO(new Bundle { val finished = Output(Bool()) val timeout = Output(Bool()) val mem = new HellaCacheIO val hartid = Input(UInt(log2Up(numGens).W)) val fence_rdy = Input(Bool()) }) val totalNumAddrs = addressBag.size + numExtraAddrs val initCount = RegInit(0.U(log2Up(totalNumAddrs).W)) val initDone = RegInit(false.B) val reqTimer = Module(new Timer(8192, maxTags)) reqTimer.io.start.valid := io.mem.req.fire reqTimer.io.start.bits := io.mem.req.bits.tag reqTimer.io.stop.valid := io.mem.resp.valid reqTimer.io.stop.bits := io.mem.resp.bits.tag // Random addresses // ---------------- // Address bag, shared by all cores, taken from module parameters. // In addition, there is a per-core random selection of extra addresses. val bagOfAddrs = addressBag.map(x => (memStart + x).U(pAddrBits.W)) val extraAddrs = Seq.fill(numExtraAddrs) { (memStart + SeededRandom.fromSeed.nextInt(1 << 16) * numBytesInWord).U(pAddrBits.W) } // A random index into the address bag. val randAddrBagIndex = LCG(logAddressBagLen) // A random address from the address bag. val addrBagIndices = (0 to addressBagLen-1). map(i => i.U(logAddressBagLen.W)) val randAddrFromBag = MuxLookup(randAddrBagIndex, 0.U)( addrBagIndices.zip(bagOfAddrs)) // Random address from the address bag or the extra addresses. val extraAddrIndices = (0 to numExtraAddrs-1) .map(i => i.U(logNumExtraAddrs.W)) val randAddr = if (! genExtraAddrs) { randAddrFromBag } else { // A random index into the extra addresses. val randExtraAddrIndex = LCG(logNumExtraAddrs) // A random address from the extra addresses. val randAddrFromExtra = Cat(0.U, MuxLookup(randExtraAddrIndex, 0.U)( extraAddrIndices.zip(extraAddrs)), 0.U(3.W)) Frequency(List( (1, randAddrFromBag), (1, randAddrFromExtra))) } val allAddrs = extraAddrs ++ bagOfAddrs val allAddrIndices = (0 until totalNumAddrs) .map(i => i.U(log2Ceil(totalNumAddrs).W)) val initAddr = MuxLookup(initCount, 0.U)( allAddrIndices.zip(allAddrs)) // Random opcodes // -------------- // Generate random opcodes for memory operations according to the // given frequency distribution. // Opcodes val (opNop :: opLoad :: opStore :: opFence :: opLRSC :: opSwap :: opDelay :: Nil) = Enum(7) // Distribution specified as a list of (frequency,value) pairs. // NOTE: frequencies must sum to a power of two. val randOp = Frequency(List( (10, opLoad), (10, opStore), (4, opFence), (3, opLRSC), (3, opSwap), (2, opDelay))) // Request/response tags // --------------------- // Responses may come back out-of-order. Each request and response // therefore contains a unique 7-bit identifier, referred to as a // "tag", used to match each response with its corresponding request. // Create a tag manager giving out unique 3-bit tags val tagMan = Module(new TagMan(log2Ceil(maxTags))) // Default inputs tagMan.io.take := false.B; tagMan.io.put := false.B; tagMan.io.tagIn := 0.U; // Cycle counter // ------------- // 32-bit cycle count used to record send-times of requests and // receive-times of respones. val cycleCount = RegInit(0.U(32.W)) cycleCount := cycleCount + 1.U; // Delay timer // ----------- // Used to implement the delay operation and to insert random // delays between load-reserve and store-conditional commands. // A 16-bit timer is plenty val delayTimer = Module(new DynamicTimer(16)) // Used to generate a random delay period val randDelayBase = LCG16() // Random delay period: usually small, occasionally big val randDelay = Frequency(List( (14, 0.U(13.W) ## randDelayBase(2, 0)), (2, 0.U(11.W) ## randDelayBase(5, 0)))) // Default inputs delayTimer.io.start := false.B delayTimer.io.period := randDelay delayTimer.io.stop := false.B // Operation dispatch // ------------------ // Hardware thread id val tid = io.hartid // Request & response count val reqCount = RegInit(0.U(32.W)) val respCount = RegInit(0.U(32.W)) // Current operation being executed val currentOp = RegInit(opNop) // If larger than 0, a multi-cycle operation is in progress. // Value indicates stage of progress. val opInProgress = RegInit(0.U(2.W)) // Indicate when a fresh request is to be sent val sendFreshReq = Wire(Bool()) sendFreshReq := false.B // Used to generate unique data values val nextData = RegInit(1.U((numBitsInWord-tid.getWidth).W)) // Registers for all the interesting parts of a request val reqValid = RegInit(false.B) val reqAddr = RegInit(0.U(numBitsInWord.W)) val reqData = RegInit(0.U(numBitsInWord.W)) val reqCmd = RegInit(0.U(5.W)) val reqTag = RegInit(0.U(7.W)) // Condition on being allowed to send a fresh request val canSendFreshReq = (!reqValid \|\| io.mem.req.fire) && tagMan.io.available // Operation dispatch when (reqCount < numReqsPerGen.U) { // No-op when (currentOp === opNop) { // Move on to a new operation currentOp := Mux(initDone, randOp, opStore) } // Fence when (currentOp === opFence) { when (opInProgress === 0.U && !reqValid) { // Emit fence request printf("%d: fence-req @%d\n", tid, cycleCount) // Multi-cycle operation now in progress opInProgress := 1.U } // Wait until all requests have had a response .elsewhen (reqCount === respCount && io.fence_rdy) { // Emit fence response printf("%d: fence-resp @%d\n", tid, cycleCount) // Move on to a new operation currentOp := randOp // Operation finished opInProgress := 0.U } } // Delay when (currentOp === opDelay) { when (opInProgress === 0.U) { // Start timer delayTimer.io.start := true.B // Multi-cycle operation now in progress opInProgress := 1.U } .elsewhen (delayTimer.io.timeout) { // Move on to a new operation currentOp := randOp // Operation finished opInProgress := 0.U } } // Load, store, or atomic swap when (currentOp === opLoad \|\| currentOp === opStore \|\| currentOp === opSwap) { when (canSendFreshReq) { // Set address reqAddr := Mux(initDone, randAddr, initAddr) // Set command when (currentOp === opLoad) { reqCmd := M_XRD } .elsewhen (currentOp === opStore) { reqCmd := M_XWR } .elsewhen (currentOp === opSwap) { reqCmd := M_XA_SWAP } // Send request sendFreshReq := true.B // Move on to a new operation when (!initDone && initCount =/= (totalNumAddrs - 1).U) { initCount := initCount + 1.U currentOp := opStore } .otherwise { currentOp := randOp initDone := true.B } } } // Load-reserve and store-conditional // First issue an LR, then delay, then issue an SC when (currentOp === opLRSC) { // LR request has not yet been sent when (opInProgress === 0.U) { when (canSendFreshReq) { // Set address and command reqAddr := randAddr reqCmd := M_XLR // Send request sendFreshReq := true.B // Multi-cycle operation now in progress opInProgress := 1.U } } // LR request has been sent, start delay timer when (opInProgress === 1.U) { // Start timer delayTimer.io.start := true.B // Indicate that delay has started opInProgress := 2.U } // Delay in progress when (opInProgress === 2.U) { when (delayTimer.io.timeout) { // Delay finished opInProgress := 3.U } } // Delay finished, send SC request when (opInProgress === 3.U) { when (canSendFreshReq) { // Set command, but leave address // i.e. use same address as LR did reqCmd := M_XSC // Send request sendFreshReq := true.B // Multi-cycle operation finished opInProgress := 0.U // Move on to a new operation currentOp := randOp } } } } // Sending of requests // ------------------- when (sendFreshReq) { // Grab a unique tag for the request reqTag := tagMan.io.tagOut tagMan.io.take := true.B // Fill in unique data reqData := Cat(nextData, tid) nextData := nextData + 1.U // Request is good to go! reqValid := true.B // Increment request count reqCount := reqCount + 1.U } .elsewhen (io.mem.req.fire) { // Request has been sent and there is no new request ready reqValid := false.B } // Wire up interface to memory io.mem.req.valid := reqValid io.mem.req.bits.addr := reqAddr io.mem.req.bits.data := reqData io.mem.req.bits.size := log2Ceil(numBytesInWord).U io.mem.req.bits.signed := false.B io.mem.req.bits.cmd := reqCmd io.mem.req.bits.tag := reqTag io.mem.req.bits.no_alloc := false.B io.mem.req.bits.no_xcpt := false.B io.mem.req.bits.no_resp := false.B io.mem.req.bits.mask := ~(0.U((numBitsInWord / 8).W)) io.mem.req.bits.phys := false.B io.mem.req.bits.dprv := PRV.M.U io.mem.req.bits.dv := false.B io.mem.keep_clock_enabled := true.B // The below signals don't matter because this uses the SimpleHellaIF io.mem.s1_data.data := RegNext(io.mem.req.bits.data) io.mem.s1_data.mask := RegNext(io.mem.req.bits.mask) io.mem.s1_kill := false.B io.mem.s2_kill := false.B // On cycle when request is actually sent, print it when (io.mem.req.fire) { // Short-hand for address val addr = io.mem.req.bits.addr // Print thread id printf("%d:", tid) // Print command when (reqCmd === M_XRD) { printf(" load-req 0x%x", addr) } when (reqCmd === M_XLR) { printf(" load-reserve-req 0x%x", addr) } when (reqCmd === M_XWR) { printf(" store-req %d 0x%x", reqData, addr) } when (reqCmd === M_XSC) { printf(" store-cond-req %d 0x%x", reqData, addr) } when (reqCmd === M_XA_SWAP) { printf(" swap-req %d 0x%x", reqData, addr) } // Print tag printf(" #%d", reqTag) // Print time printf(" @%d\n", cycleCount) } // Handling of responses // --------------------- // When a response is received when (io.mem.resp.valid) { // Put tag back in tag set tagMan.io.tagIn := io.mem.resp.bits.tag tagMan.io.put := true.B // Print response printf("%d: resp %d #%d @%d\n", tid, io.mem.resp.bits.data, io.mem.resp.bits.tag, cycleCount) // Increment response count respCount := respCount + 1.U } // Termination condition // --------------------- val done = reqCount === numReqsPerGen.U && respCount === numReqsPerGen.U val donePulse = done && !RegNext(done, false.B) // Emit that this thread has completed when (donePulse) { printf(s"FINISHED ${numGens}\n") } io.finished := done io.timeout := reqTimer.io.timeout.valid } // ======================= // Trace-generator wrapper // ======================= class TraceGenTile private( val params: TraceGenParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, q: Parameters ) extends GroundTestTile(params, crossing, lookup, q) { def this(params: TraceGenParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcacheOpt.map(_.node).getOrElse(TLTempNode()) override lazy val module = new TraceGenTileModuleImp(this) } class TraceGenTileModuleImp(outer: TraceGenTile) extends GroundTestTileModuleImp(outer) { val tracegen = Module(new TraceGenerator(outer.params)) tracegen.io.hartid := outer.hartIdSinkNode.bundle outer.dcacheOpt foreach { dcache => val dcacheIF = Module(new SimpleHellaCacheIF()) dcacheIF.io.requestor <> tracegen.io.mem dcache.module.io.cpu <> dcacheIF.io.cache tracegen.io.fence_rdy := dcache.module.io.cpu.ordered } outer.reportCease(Some(tracegen.io.finished)) outer.reportHalt(Some(tracegen.io.timeout)) outer.reportWFI(None) status.timeout.valid := tracegen.io.timeout status.timeout.bits := 0.U status.error.valid := false.B assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.tileId}: request timed out") } File LCG.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.Cat /** A 16-bit psuedo-random generator based on a linear conguential * generator (LCG). The state is stored in an unitialised register. * When using the C++ backend, it is straigtforward to arrange a * random initial value for each uninitialised register, effectively * seeding each LCG16 instance with a different seed. / class LCG16 extends Module { val io = IO(new Bundle { val out = Output(UInt(16.W)) val inc = Input(Bool()) }) val state = Reg(UInt(32.W)) when (io.inc) { state := state 1103515245.U(32.W) + 12345.U(32.W) } io.out := state(30, 15) } /** An n-bit psuedo-random generator made from many instances of a * 16-bit LCG. Parameter 'width' must be larger than 0. / class LCG(val w: Int) extends Module { val io = IO(new Bundle { val out = Output(UInt(w.W)) val inc = Input(Bool()) }) require(w > 0) val numLCG16s : Int = (w+15)/16 val outs = Seq.fill(numLCG16s) { LCG16(io.inc) } io.out := Cat(outs) } object LCG16 { def apply(inc: Bool = true.B): UInt = { val lcg = Module(new LCG16) lcg.io.inc := inc lcg.io.out } } object LCG { def apply(w: Int, inc: Bool = true.B): UInt = { val lcg = Module(new LCG(w)) lcg.io.inc := inc lcg.io.out } } File Frequency.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ /* Given a list of (frequency, value) pairs, return a random value * according to the frequency distribution. The sum of the * frequencies in the distribution must be a power of two. */ object Frequency { def apply(dist : List[(Int, Bits)]) : Bits = { // Distribution must be non-empty require(dist.length > 0) // Require that the frequencies sum to a power of two val (freqs, vals) = dist.unzip val total = freqs.sum require(isPow2(total)) // First item in the distribution val (firstFreq, firstVal) = dist.head // Result wire val result = Wire(Bits(firstVal.getWidth.W)) result := 0.U // Random value val randVal = LCG(log2Up(total)) // Pick return value var count = firstFreq var select = when (randVal < firstFreq.U) { result := firstVal } for (p <- dist.drop(1)) { count = count + p._1 select = select.elsewhen(randVal < count.U) { result := p._2 } } return result } }	module TraceGenerator_1( // @[TraceGen.scala:212:7] input clock, // @[TraceGen.scala:212:7] input reset, // @[TraceGen.scala:212:7] output io_finished, // @[TraceGen.scala:214:14] output io_timeout, // @[TraceGen.scala:214:14] input io_mem_req_ready, // @[TraceGen.scala:214:14] output io_mem_req_valid, // @[TraceGen.scala:214:14] output [39:0] io_mem_req_bits_addr, // @[TraceGen.scala:214:14] output [6:0] io_mem_req_bits_tag, // @[TraceGen.scala:214:14] output [4:0] io_mem_req_bits_cmd, // @[TraceGen.scala:214:14] output [63:0] io_mem_req_bits_data, // @[TraceGen.scala:214:14] output [63:0] io_mem_s1_data_data, // @[TraceGen.scala:214:14] input io_mem_resp_valid, // @[TraceGen.scala:214:14] input [6:0] io_mem_resp_bits_tag, // @[TraceGen.scala:214:14] input [1:0] io_mem_resp_bits_size, // @[TraceGen.scala:214:14] input [63:0] io_mem_resp_bits_data, // @[TraceGen.scala:214:14] input io_mem_ordered, // @[TraceGen.scala:214:14] input io_hartid, // @[TraceGen.scala:214:14] input io_fence_rdy // @[TraceGen.scala:214:14] ); wire [3:0] _randDelay_randVal_lcg_io_out; // @[LCG.scala:51:21] wire [15:0] _randDelayBase_lcg_io_out; // @[LCG.scala:43:21] wire _delayTimer_io_timeout; // @[TraceGen.scala:339:26] wire _tagMan_io_available; // @[TraceGen.scala:316:22] wire [2:0] _tagMan_io_tagOut; // @[TraceGen.scala:316:22] wire [4:0] _randOp_randVal_lcg_io_out; // @[LCG.scala:51:21] wire [3:0] _randAddrBagIndex_lcg_io_out; // @[LCG.scala:51:21] wire io_mem_req_ready_0 = io_mem_req_ready; // @[TraceGen.scala:212:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[TraceGen.scala:212:7] wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[TraceGen.scala:212:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[TraceGen.scala:212:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[TraceGen.scala:212:7] wire io_mem_ordered_0 = io_mem_ordered; // @[TraceGen.scala:212:7] wire io_hartid_0 = io_hartid; // @[TraceGen.scala:212:7] wire io_fence_rdy_0 = io_fence_rdy; // @[TraceGen.scala:212:7] wire [7:0] io_mem_req_bits_mask = 8'hFF; // @[TraceGen.scala:212:7] wire [7:0] io_mem_s1_data_mask = 8'hFF; // @[TraceGen.scala:212:7] wire [7:0] _io_mem_req_bits_mask_T = 8'hFF; // @[TraceGen.scala:538:27] wire [1:0] io_mem_req_bits_size = 2'h3; // @[TraceGen.scala:212:7] wire [1:0] io_mem_req_bits_dprv = 2'h3; // @[TraceGen.scala:212:7] wire io_mem_req_bits_signed = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_req_bits_dv = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_req_bits_phys = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_req_bits_no_resp = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s1_kill = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_nack = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_nack_cause_raw = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_kill = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_uncached = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_resp_bits_signed = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_resp_bits_dv = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_resp_bits_replay = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_resp_bits_has_data = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_replay_next = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_ma_ld = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_ma_st = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_pf_ld = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_pf_st = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_ae_ld = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_ae_st = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_store_pending = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_acquire = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_release = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_grant = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_tlbMiss = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_blocked = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_clock_enabled = 1'h0; // @[TraceGen.scala:212:7] wire [31:0] io_mem_s2_paddr = 32'h0; // @[TraceGen.scala:212:7] wire [39:0] io_mem_resp_bits_addr = 40'h0; // @[TraceGen.scala:212:7] wire [39:0] io_mem_s2_gpa = 40'h0; // @[TraceGen.scala:212:7] wire [4:0] io_mem_resp_bits_cmd = 5'h0; // @[TraceGen.scala:212:7] wire [1:0] io_mem_resp_bits_dprv = 2'h0; // @[TraceGen.scala:212:7] wire [7:0] io_mem_resp_bits_mask = 8'h0; // @[TraceGen.scala:212:7] wire [63:0] io_mem_resp_bits_data_word_bypass = 64'h0; // @[TraceGen.scala:212:7] wire [63:0] io_mem_resp_bits_data_raw = 64'h0; // @[TraceGen.scala:212:7] wire [63:0] io_mem_resp_bits_store_data = 64'h0; // @[TraceGen.scala:212:7] wire io_mem_keep_clock_enabled = 1'h1; // @[TraceGen.scala:212:7] wire _randOp_T_5 = 1'h1; // @[Frequency.scala:38:40] wire _randDelay_T_5 = 1'h1; // @[Frequency.scala:38:40] wire done; // @[TraceGen.scala:596:44] wire [39:0] io_mem_req_bits_addr_0; // @[TraceGen.scala:212:7] wire [6:0] io_mem_req_bits_tag_0; // @[TraceGen.scala:212:7] wire [4:0] io_mem_req_bits_cmd_0; // @[TraceGen.scala:212:7] wire [63:0] io_mem_req_bits_data_0; // @[TraceGen.scala:212:7] wire io_mem_req_valid_0; // @[TraceGen.scala:212:7] wire [63:0] io_mem_s1_data_data_0; // @[TraceGen.scala:212:7] wire io_finished_0; // @[TraceGen.scala:212:7] wire io_timeout_0; // @[TraceGen.scala:212:7] reg [4:0] initCount; // @[TraceGen.scala:223:26] reg initDone; // @[TraceGen.scala:224:26] wire _T_31 = io_mem_req_ready_0 & io_mem_req_valid_0; // @[Decoupled.scala:51:35] wire _reqTimer_io_start_valid_T; // @[Decoupled.scala:51:35] assign _reqTimer_io_start_valid_T = _T_31; // @[Decoupled.scala:51:35] wire _canSendFreshReq_T_1; // @[Decoupled.scala:51:35] assign _canSendFreshReq_T_1 = _T_31; // @[Decoupled.scala:51:35] wire _randAddrFromBag_T = _randAddrBagIndex_lcg_io_out == 4'h1; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_1 = {44'h8000000, _randAddrFromBag_T, 3'h0}; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_2 = _randAddrBagIndex_lcg_io_out == 4'h2; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_3 = _randAddrFromBag_T_2 ? 48'h80000010 : _randAddrFromBag_T_1; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_4 = _randAddrBagIndex_lcg_io_out == 4'h3; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_5 = _randAddrFromBag_T_4 ? 48'h80000018 : _randAddrFromBag_T_3; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_6 = _randAddrBagIndex_lcg_io_out == 4'h4; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_7 = _randAddrFromBag_T_6 ? 48'h80000020 : _randAddrFromBag_T_5; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_8 = _randAddrBagIndex_lcg_io_out == 4'h5; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_9 = _randAddrFromBag_T_8 ? 48'h80000028 : _randAddrFromBag_T_7; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_10 = _randAddrBagIndex_lcg_io_out == 4'h6; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_11 = _randAddrFromBag_T_10 ? 48'h80000030 : _randAddrFromBag_T_9; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_12 = _randAddrBagIndex_lcg_io_out == 4'h7; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_13 = _randAddrFromBag_T_12 ? 48'h80000038 : _randAddrFromBag_T_11; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_14 = _randAddrBagIndex_lcg_io_out == 4'h8; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_15 = _randAddrFromBag_T_14 ? 48'h80000400 : _randAddrFromBag_T_13; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_16 = _randAddrBagIndex_lcg_io_out == 4'h9; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_17 = _randAddrFromBag_T_16 ? 48'h80000408 : _randAddrFromBag_T_15; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_18 = _randAddrBagIndex_lcg_io_out == 4'hA; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_19 = _randAddrFromBag_T_18 ? 48'h80000410 : _randAddrFromBag_T_17; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_20 = _randAddrBagIndex_lcg_io_out == 4'hB; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_21 = _randAddrFromBag_T_20 ? 48'h80000418 : _randAddrFromBag_T_19; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_22 = _randAddrBagIndex_lcg_io_out == 4'hC; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_23 = _randAddrFromBag_T_22 ? 48'h80000420 : _randAddrFromBag_T_21; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_24 = _randAddrBagIndex_lcg_io_out == 4'hD; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_25 = _randAddrFromBag_T_24 ? 48'h80000428 : _randAddrFromBag_T_23; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_26 = _randAddrBagIndex_lcg_io_out == 4'hE; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_27 = _randAddrFromBag_T_26 ? 48'h80000430 : _randAddrFromBag_T_25; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_28 = &_randAddrBagIndex_lcg_io_out; // @[LCG.scala:51:21] wire [47:0] randAddrFromBag = _randAddrFromBag_T_28 ? 48'h80000438 : _randAddrFromBag_T_27; // @[TraceGen.scala:253:57] wire _initAddr_T = initCount == 5'h0; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_1 = _initAddr_T ? 48'h80057738 : 48'h0; // @[TraceGen.scala:283:43] wire _initAddr_T_2 = initCount == 5'h1; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_3 = _initAddr_T_2 ? 48'h80006228 : _initAddr_T_1; // @[TraceGen.scala:283:43] wire _initAddr_T_4 = initCount == 5'h2; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_5 = _initAddr_T_4 ? 48'h80000000 : _initAddr_T_3; // @[TraceGen.scala:283:43] wire _initAddr_T_6 = initCount == 5'h3; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_7 = _initAddr_T_6 ? 48'h80000008 : _initAddr_T_5; // @[TraceGen.scala:283:43] wire _initAddr_T_8 = initCount == 5'h4; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_9 = _initAddr_T_8 ? 48'h80000010 : _initAddr_T_7; // @[TraceGen.scala:283:43] wire _initAddr_T_10 = initCount == 5'h5; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_11 = _initAddr_T_10 ? 48'h80000018 : _initAddr_T_9; // @[TraceGen.scala:283:43] wire _initAddr_T_12 = initCount == 5'h6; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_13 = _initAddr_T_12 ? 48'h80000020 : _initAddr_T_11; // @[TraceGen.scala:283:43] wire _initAddr_T_14 = initCount == 5'h7; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_15 = _initAddr_T_14 ? 48'h80000028 : _initAddr_T_13; // @[TraceGen.scala:283:43] wire _initAddr_T_16 = initCount == 5'h8; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_17 = _initAddr_T_16 ? 48'h80000030 : _initAddr_T_15; // @[TraceGen.scala:283:43] wire _initAddr_T_18 = initCount == 5'h9; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_19 = _initAddr_T_18 ? 48'h80000038 : _initAddr_T_17; // @[TraceGen.scala:283:43] wire _initAddr_T_20 = initCount == 5'hA; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_21 = _initAddr_T_20 ? 48'h80000400 : _initAddr_T_19; // @[TraceGen.scala:283:43] wire _initAddr_T_22 = initCount == 5'hB; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_23 = _initAddr_T_22 ? 48'h80000408 : _initAddr_T_21; // @[TraceGen.scala:283:43] wire _initAddr_T_24 = initCount == 5'hC; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_25 = _initAddr_T_24 ? 48'h80000410 : _initAddr_T_23; // @[TraceGen.scala:283:43] wire _initAddr_T_26 = initCount == 5'hD; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_27 = _initAddr_T_26 ? 48'h80000418 : _initAddr_T_25; // @[TraceGen.scala:283:43] wire _initAddr_T_28 = initCount == 5'hE; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_29 = _initAddr_T_28 ? 48'h80000420 : _initAddr_T_27; // @[TraceGen.scala:283:43] wire _initAddr_T_30 = initCount == 5'hF; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_31 = _initAddr_T_30 ? 48'h80000428 : _initAddr_T_29; // @[TraceGen.scala:283:43] wire _initAddr_T_32 = initCount == 5'h10; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_33 = _initAddr_T_32 ? 48'h80000430 : _initAddr_T_31; // @[TraceGen.scala:283:43] wire _initAddr_T_34 = initCount == 5'h11; // @[TraceGen.scala:223:26, :283:43] wire [47:0] initAddr = _initAddr_T_34 ? 48'h80000438 : _initAddr_T_33; // @[TraceGen.scala:283:43] wire [2:0] randOp; // @[Frequency.scala:27:22] wire _randOp_T = _randOp_randVal_lcg_io_out < 5'hA; // @[LCG.scala:51:21] wire _randOp_T_1 = _randOp_randVal_lcg_io_out < 5'h14; // @[LCG.scala:51:21] wire _randOp_T_2 = _randOp_randVal_lcg_io_out[4:3] != 2'h3; // @[LCG.scala:51:21] wire _randOp_T_3 = _randOp_randVal_lcg_io_out < 5'h1B; // @[LCG.scala:51:21] wire _randOp_T_4 = _randOp_randVal_lcg_io_out[4:1] != 4'hF; // @[LCG.scala:51:21] assign randOp = _randOp_T ? 3'h1 : _randOp_T_1 ? 3'h2 : _randOp_T_2 ? 3'h3 : _randOp_T_3 ? 3'h4 : _randOp_T_4 ? 3'h5 : 3'h6; // @[Frequency.scala:27:22, :35:{32,47,56}, :38:{40,51,60}] reg [31:0] cycleCount; // @[TraceGen.scala:329:27] wire [32:0] _cycleCount_T = {1'h0, cycleCount} + 33'h1; // @[TraceGen.scala:329:27, :330:28] wire [31:0] _cycleCount_T_1 = _cycleCount_T[31:0]; // @[TraceGen.scala:330:28] wire [2:0] _randDelay_T = _randDelayBase_lcg_io_out[2:0]; // @[LCG.scala:43:21] wire [15:0] _randDelay_T_1 = {13'h0, _randDelay_T}; // @[TraceGen.scala:346:{20,36}] wire [5:0] _randDelay_T_2 = _randDelayBase_lcg_io_out[5:0]; // @[LCG.scala:43:21] wire [16:0] _randDelay_T_3 = {11'h0, _randDelay_T_2}; // @[TraceGen.scala:347:{20,36}] wire [15:0] randDelay; // @[Frequency.scala:27:22] wire _randDelay_T_4 = _randDelay_randVal_lcg_io_out[3:1] != 3'h7; // @[LCG.scala:51:21] assign randDelay = _randDelay_T_4 ? _randDelay_T_1 : _randDelay_T_3[15:0]; // @[Frequency.scala:27:22, :35:{32,47,56}, :38:{51,60}] reg [31:0] reqCount; // @[TraceGen.scala:361:26] reg [31:0] respCount; // @[TraceGen.scala:362:26] reg [2:0] currentOp; // @[TraceGen.scala:365:26] reg [1:0] opInProgress; // @[TraceGen.scala:369:29] wire sendFreshReq; // @[TraceGen.scala:372:26] reg [62:0] nextData; // @[TraceGen.scala:376:25] reg reqValid; // @[TraceGen.scala:379:25] assign io_mem_req_valid_0 = reqValid; // @[TraceGen.scala:212:7, :379:25] reg [63:0] reqAddr; // @[TraceGen.scala:380:25] reg [63:0] reqData; // @[TraceGen.scala:381:25] assign io_mem_req_bits_data_0 = reqData; // @[TraceGen.scala:212:7, :381:25] reg [4:0] reqCmd; // @[TraceGen.scala:382:25] assign io_mem_req_bits_cmd_0 = reqCmd; // @[TraceGen.scala:212:7, :382:25] reg [6:0] reqTag; // @[TraceGen.scala:383:25] assign io_mem_req_bits_tag_0 = reqTag; // @[TraceGen.scala:212:7, :383:25] wire _canSendFreshReq_T = ~reqValid; // @[TraceGen.scala:379:25, :386:26] wire _canSendFreshReq_T_2 = _canSendFreshReq_T \| _canSendFreshReq_T_1; // @[Decoupled.scala:51:35] wire canSendFreshReq = _canSendFreshReq_T_2 & _tagMan_io_available; // @[TraceGen.scala:316:22, :386:{36,56}] wire _T = reqCount < 32'h2000; // @[TraceGen.scala:361:26, :390:18] wire [2:0] _currentOp_T = initDone ? randOp : 3'h2; // @[Frequency.scala:27:22] wire _T_2 = currentOp == 3'h3; // @[TraceGen.scala:365:26, :399:21] wire _T_5 = ~(\|opInProgress) & ~reqValid; // @[TraceGen.scala:369:29, :379:25, :386:26, :400:{26,34}] wire _T_9 = reqCount == respCount & io_fence_rdy_0; // @[TraceGen.scala:212:7, :361:26, :362:26, :407:{27,41}] wire _T_12 = currentOp == 3'h6; // @[TraceGen.scala:365:26, :418:21] wire _T_19 = currentOp == 3'h1; // @[TraceGen.scala:365:26, :434:21] wire _T_20 = currentOp == 3'h2; // @[TraceGen.scala:365:26, :435:21] wire _T_21 = currentOp == 3'h5; // @[TraceGen.scala:365:26, :436:21] wire _T_18 = _T_19 \| _T_20 \| _T_21; // @[TraceGen.scala:434:{21,33}, :435:{21,33}, :436:21] wire [47:0] _reqAddr_T = initDone ? randAddrFromBag : initAddr; // @[TraceGen.scala:224:26, :253:57, :283:43, :439:23] wire _GEN = _T_18 & canSendFreshReq; // @[TraceGen.scala:373:16, :386:56, :434:33, :435:33, :436:33, :437:30] wire [5:0] _initCount_T = {1'h0, initCount} + 6'h1; // @[TraceGen.scala:223:26, :452:34] wire [4:0] _initCount_T_1 = _initCount_T[4:0]; // @[TraceGen.scala:452:34] wire _T_25 = currentOp == 3'h4; // @[TraceGen.scala:365:26, :463:21] wire _GEN_0 = ~(\|opInProgress) & canSendFreshReq; // @[TraceGen.scala:369:29, :386:56, :400:26, :436:33, :465:{26,35}, :466:32, :468:19] wire _T_27 = opInProgress == 2'h1; // @[TraceGen.scala:369:29, :477:26] assign sendFreshReq = _T & (_T_25 ? ((&opInProgress) ? canSendFreshReq \| _GEN_0 \| _GEN : _GEN_0 \| _GEN) : _GEN); // @[TraceGen.scala:369:29, :372:26, :373:16, :386:56, :390:{18,37}, :436:33, :437:30, :463:{21,33}, :465:35, :466:32, :468:19, :471:24, :491:{26,35}, :492:32, :497:24] wire [63:0] _reqData_T = {nextData, io_hartid_0}; // @[TraceGen.scala:212:7, :376:25, :515:19] wire [63:0] _nextData_T = {1'h0, nextData} + 64'h1; // @[TraceGen.scala:376:25, :516:26] wire [62:0] _nextData_T_1 = _nextData_T[62:0]; // @[TraceGen.scala:516:26] wire [32:0] _reqCount_T = {1'h0, reqCount} + 33'h1; // @[TraceGen.scala:361:26, :520:26] wire [31:0] _reqCount_T_1 = _reqCount_T[31:0]; // @[TraceGen.scala:520:26] assign io_mem_req_bits_addr_0 = reqAddr[39:0]; // @[TraceGen.scala:212:7, :380:25, :529:24] reg [63:0] io_mem_s1_data_data_REG; // @[TraceGen.scala:545:33] assign io_mem_s1_data_data_0 = io_mem_s1_data_data_REG; // @[TraceGen.scala:212:7, :545:33] wire [32:0] _respCount_T = {1'h0, respCount} + 33'h1; // @[TraceGen.scala:362:26, :590:28] wire [31:0] _respCount_T_1 = _respCount_T[31:0]; // @[TraceGen.scala:590:28] wire _done_T = reqCount == 32'h2000; // @[TraceGen.scala:361:26, :596:24] wire _done_T_1 = respCount == 32'h2000; // @[TraceGen.scala:362:26, :597:24] assign done = _done_T & _done_T_1; // @[TraceGen.scala:596:{24,44}, :597:24] assign io_finished_0 = done; // @[TraceGen.scala:212:7, :596:44] reg donePulse_REG; // @[TraceGen.scala:599:35] wire _donePulse_T = ~donePulse_REG; // @[TraceGen.scala:599:{27,35}] wire donePulse = done & _donePulse_T; // @[TraceGen.scala:596:44, :599:{24,27}]
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid \|\| io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }	module PriorityQueueStage_103( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundRawFNToRecFN_e8_s24_43( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_43 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_43( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [511:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [511:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_16 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_17 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_18 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_19 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_20 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_21 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_22 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_23 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_24 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_25 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_26 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_27 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_28 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_29 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_30 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_31 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [5:0] _mask_sizeOH_T_2 = 6'h0; // @[OneHot.scala:65:27] wire [5:0] a_first_beats1_decode = 6'h0; // @[Edges.scala:220:59] wire [5:0] a_first_beats1 = 6'h0; // @[Edges.scala:221:14] wire [5:0] a_first_count = 6'h0; // @[Edges.scala:234:25] wire [5:0] a_first_beats1_decode_1 = 6'h0; // @[Edges.scala:220:59] wire [5:0] a_first_beats1_1 = 6'h0; // @[Edges.scala:221:14] wire [5:0] a_first_count_1 = 6'h0; // @[Edges.scala:234:25] wire [5:0] c_first_beats1_decode = 6'h0; // @[Edges.scala:220:59] wire [5:0] c_first_beats1 = 6'h0; // @[Edges.scala:221:14] wire [5:0] _c_first_count_T = 6'h0; // @[Edges.scala:234:27] wire [5:0] c_first_count = 6'h0; // @[Edges.scala:234:25] wire [5:0] _c_first_counter_T = 6'h0; // @[Edges.scala:236:21] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_8_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_9_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_10_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_11_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_12_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_13_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_14_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_15_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_8_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_9_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_10_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_11_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_12_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_13_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_14_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_15_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_16_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_17_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_18_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_19_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_20_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_21_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_22_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_23_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_24_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_25_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_26_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_27_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_28_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_29_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_30_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_31_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_32 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_33 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_34 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_35 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_36 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_37 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_38 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_39 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_40 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_41 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_42 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_43 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_44 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_45 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_46 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_47 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_48 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_49 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_50 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_51 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_52 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_53 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_54 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_55 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_56 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_57 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_58 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_59 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_60 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_61 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_62 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_63 = 1'h1; // @[Misc.scala:215:29] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [5:0] c_first_counter1 = 6'h3F; // @[Edges.scala:230:28] wire [6:0] _c_first_counter1_T = 7'h7F; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [63:0] io_in_a_bits_mask = 64'hFFFFFFFFFFFFFFFF; // @[Monitor.scala:36:7] wire [63:0] mask = 64'hFFFFFFFFFFFFFFFF; // @[Misc.scala:222:10] wire [511:0] io_in_a_bits_data = 512'h0; // @[Monitor.scala:36:7] wire [511:0] _c_first_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_first_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_first_WIRE_2_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_first_WIRE_3_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_set_wo_ready_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_set_wo_ready_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_set_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_set_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_opcodes_set_interm_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_opcodes_set_interm_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_sizes_set_interm_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_sizes_set_interm_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_opcodes_set_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_opcodes_set_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_sizes_set_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_sizes_set_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_probe_ack_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_probe_ack_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_probe_ack_WIRE_2_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_probe_ack_WIRE_3_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _same_cycle_resp_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _same_cycle_resp_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _same_cycle_resp_WIRE_2_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _same_cycle_resp_WIRE_3_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _same_cycle_resp_WIRE_4_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _same_cycle_resp_WIRE_5_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] mask_lo_lo_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi_hi = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [31:0] mask_lo = 32'hFFFFFFFF; // @[Misc.scala:222:10] wire [31:0] mask_hi = 32'hFFFFFFFF; // @[Misc.scala:222:10] wire [15:0] mask_lo_lo = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] mask_lo_hi = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] mask_hi_lo = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] mask_hi_hi = 16'hFFFF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [5:0] mask_sizeOH = 6'h1; // @[Misc.scala:202:81] wire [7:0] _mask_sizeOH_T_1 = 8'h40; // @[OneHot.scala:65:12] wire [2:0] mask_sizeOH_shiftAmount = 3'h6; // @[OneHot.scala:64:49] wire [5:0] _mask_sizeOH_T = 6'h6; // @[Misc.scala:202:34] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_sub_sub_bit = io_in_a_bits_address_0[5]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_4_2 = mask_sub_sub_sub_sub_2_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_5_2 = mask_sub_sub_sub_sub_2_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_6_2 = mask_sub_sub_sub_sub_3_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_7_2 = mask_sub_sub_sub_sub_3_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_8_2 = mask_sub_sub_sub_4_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_9_2 = mask_sub_sub_sub_4_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_10_2 = mask_sub_sub_sub_5_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_11_2 = mask_sub_sub_sub_5_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_12_2 = mask_sub_sub_sub_6_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_13_2 = mask_sub_sub_sub_6_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_14_2 = mask_sub_sub_sub_7_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_15_2 = mask_sub_sub_sub_7_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_16_2 = mask_sub_sub_8_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_17_2 = mask_sub_sub_8_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_18_2 = mask_sub_sub_9_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_19_2 = mask_sub_sub_9_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_20_2 = mask_sub_sub_10_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_21_2 = mask_sub_sub_10_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_22_2 = mask_sub_sub_11_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_23_2 = mask_sub_sub_11_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_24_2 = mask_sub_sub_12_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_25_2 = mask_sub_sub_12_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_26_2 = mask_sub_sub_13_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_27_2 = mask_sub_sub_13_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_28_2 = mask_sub_sub_14_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_29_2 = mask_sub_sub_14_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_30_2 = mask_sub_sub_15_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_31_2 = mask_sub_sub_15_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire mask_eq_32 = mask_sub_16_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_32 = mask_eq_32; // @[Misc.scala:214:27, :215:38] wire mask_eq_33 = mask_sub_16_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_33 = mask_eq_33; // @[Misc.scala:214:27, :215:38] wire mask_eq_34 = mask_sub_17_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_34 = mask_eq_34; // @[Misc.scala:214:27, :215:38] wire mask_eq_35 = mask_sub_17_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_35 = mask_eq_35; // @[Misc.scala:214:27, :215:38] wire mask_eq_36 = mask_sub_18_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_36 = mask_eq_36; // @[Misc.scala:214:27, :215:38] wire mask_eq_37 = mask_sub_18_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_37 = mask_eq_37; // @[Misc.scala:214:27, :215:38] wire mask_eq_38 = mask_sub_19_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_38 = mask_eq_38; // @[Misc.scala:214:27, :215:38] wire mask_eq_39 = mask_sub_19_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_39 = mask_eq_39; // @[Misc.scala:214:27, :215:38] wire mask_eq_40 = mask_sub_20_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_40 = mask_eq_40; // @[Misc.scala:214:27, :215:38] wire mask_eq_41 = mask_sub_20_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_41 = mask_eq_41; // @[Misc.scala:214:27, :215:38] wire mask_eq_42 = mask_sub_21_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_42 = mask_eq_42; // @[Misc.scala:214:27, :215:38] wire mask_eq_43 = mask_sub_21_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_43 = mask_eq_43; // @[Misc.scala:214:27, :215:38] wire mask_eq_44 = mask_sub_22_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_44 = mask_eq_44; // @[Misc.scala:214:27, :215:38] wire mask_eq_45 = mask_sub_22_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_45 = mask_eq_45; // @[Misc.scala:214:27, :215:38] wire mask_eq_46 = mask_sub_23_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_46 = mask_eq_46; // @[Misc.scala:214:27, :215:38] wire mask_eq_47 = mask_sub_23_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_47 = mask_eq_47; // @[Misc.scala:214:27, :215:38] wire mask_eq_48 = mask_sub_24_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_48 = mask_eq_48; // @[Misc.scala:214:27, :215:38] wire mask_eq_49 = mask_sub_24_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_49 = mask_eq_49; // @[Misc.scala:214:27, :215:38] wire mask_eq_50 = mask_sub_25_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_50 = mask_eq_50; // @[Misc.scala:214:27, :215:38] wire mask_eq_51 = mask_sub_25_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_51 = mask_eq_51; // @[Misc.scala:214:27, :215:38] wire mask_eq_52 = mask_sub_26_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_52 = mask_eq_52; // @[Misc.scala:214:27, :215:38] wire mask_eq_53 = mask_sub_26_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_53 = mask_eq_53; // @[Misc.scala:214:27, :215:38] wire mask_eq_54 = mask_sub_27_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_54 = mask_eq_54; // @[Misc.scala:214:27, :215:38] wire mask_eq_55 = mask_sub_27_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_55 = mask_eq_55; // @[Misc.scala:214:27, :215:38] wire mask_eq_56 = mask_sub_28_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_56 = mask_eq_56; // @[Misc.scala:214:27, :215:38] wire mask_eq_57 = mask_sub_28_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_57 = mask_eq_57; // @[Misc.scala:214:27, :215:38] wire mask_eq_58 = mask_sub_29_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_58 = mask_eq_58; // @[Misc.scala:214:27, :215:38] wire mask_eq_59 = mask_sub_29_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_59 = mask_eq_59; // @[Misc.scala:214:27, :215:38] wire mask_eq_60 = mask_sub_30_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_60 = mask_eq_60; // @[Misc.scala:214:27, :215:38] wire mask_eq_61 = mask_sub_30_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_61 = mask_eq_61; // @[Misc.scala:214:27, :215:38] wire mask_eq_62 = mask_sub_31_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_62 = mask_eq_62; // @[Misc.scala:214:27, :215:38] wire mask_eq_63 = mask_sub_31_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_63 = mask_eq_63; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [5:0] a_first_counter; // @[Edges.scala:229:27] wire [6:0] _a_first_counter1_T = {1'h0, a_first_counter} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] a_first_counter1 = _a_first_counter1_T[5:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 6'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 6'h1; // @[Edges.scala:229:27, :232:25] wire [5:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [5:0] _a_first_counter_T = a_first ? 6'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:6]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [5:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T = {1'h0, d_first_counter} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1 = _d_first_counter1_T[5:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [5:0] a_first_counter_1; // @[Edges.scala:229:27] wire [6:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] a_first_counter1_1 = _a_first_counter1_T_1[5:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 6'h1; // @[Edges.scala:229:27, :232:25] wire [5:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [5:0] _a_first_counter_T_1 = a_first_1 ? 6'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:6]; // @[package.scala:243:46] wire [5:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter_1; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1_1 = _d_first_counter1_T_1[5:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_1 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_2 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1138 = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1138 & _a_set_T[0]; // @[OneHot.scala:58:35] assign a_opcodes_set_interm = _T_1138 ? 4'h9 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:28] assign a_sizes_set_interm = _T_1138 ? 5'hD : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:28] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[package.scala:243:71] assign a_opcodes_set = _T_1138 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[package.scala:243:71] assign a_sizes_set = _T_1138 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_5 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_6 = 2'h1 << _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_6; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1184 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1153 = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :673:46, :674:74, :678:{25,70}] assign d_clr = _T_1153 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1153 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1153 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:6]; // @[package.scala:243:46] wire [5:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter_2; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1_2 = _d_first_counter1_T_2[5:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1238 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :783:46, :788:{25,70}] assign d_clr_1 = _T_1238 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1238 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1238 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File mshrs.scala: //***************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v3.common._ import boom.v3.exu.BrUpdateInfo import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc} class BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p) with HasL1HellaCacheParameters { // miss info val tag_match = Bool() val old_meta = new L1Metadata val way_en = UInt(nWays.W) // Used in the MSHRs val sdq_id = UInt(log2Ceil(cfg.nSDQ).W) } class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val id = Input(UInt()) val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) val req_sec_rdy = Output(Bool()) val clear_prefetch = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val req = Input(new BoomDCacheReqInternal) val req_is_probe = Input(Bool()) val idx = Output(Valid(UInt())) val way = Output(Valid(UInt())) val tag = Output(Valid(UInt())) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val wb_req = Decoupled(new WritebackReq(edge.bundle)) // To inform the prefetcher when we are commiting the fetch of this line val commit_val = Output(Bool()) val commit_addr = Output(UInt(coreMaxAddrBits.W)) val commit_coh = Output(new ClientMetadata) // Reading from the line buffer val lb_read = Decoupled(new LineBufferReadReq) val lb_resp = Input(UInt(encRowBits.W)) val lb_write = Decoupled(new LineBufferWriteReq) // Replays go through the cache pipeline again val replay = Decoupled(new BoomDCacheReqInternal) // Resp go straight out to the core val resp = Decoupled(new BoomDCacheResp) // Writeback unit tells us when it is done processing our wb val wb_resp = Input(Bool()) val probe_rdy = Output(Bool()) }) // TODO: Optimize this. We don't want to mess with cache during speculation // s_refill_req : Make a request for a new cache line // s_refill_resp : Store the refill response into our buffer // s_drain_rpq_loads : Drain out loads from the rpq // : If miss was misspeculated, go to s_invalid // s_wb_req : Write back the evicted cache line // s_wb_resp : Finish writing back the evicted cache line // s_meta_write_req : Write the metadata for new cache lne // s_meta_write_resp : val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18) val state = RegInit(s_invalid) val req = Reg(new BoomDCacheReqInternal) val req_idx = req.addr(untagBits-1, blockOffBits) val req_tag = req.addr >> untagBits val req_block_addr = (req.addr >> blockOffBits) << blockOffBits val req_needs_wb = RegInit(false.B) val new_coh = RegInit(ClientMetadata.onReset) val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH) val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2 val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param) // We only accept secondary misses if the original request had sufficient permissions val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) = new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd) val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe && !state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false)) rpq.io.brupdate := io.brupdate rpq.io.flush := io.exception assert(!(state === s_invalid && !rpq.io.empty)) rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) \|\| (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd) rpq.io.enq.bits := io.req rpq.io.deq.ready := false.B val grantack = Reg(Valid(new TLBundleE(edge.bundle))) val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W)) val commit_line = Reg(Bool()) val grant_had_data = Reg(Bool()) val finish_to_prefetch = Reg(Bool()) // Block probes if a tag write we started is still in the pipeline val meta_hazard = RegInit(0.U(2.W)) when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U } when (io.meta_write.fire) { meta_hazard := 1.U } io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) \|\| (state === s_meta_read && grantack.valid))) io.idx.valid := state =/= s_invalid io.tag.valid := state =/= s_invalid io.way.valid := !state.isOneOf(s_invalid, s_prefetch) io.idx.bits := req_idx io.tag.bits := req_tag io.way.bits := req.way_en io.meta_write.valid := false.B io.meta_write.bits := DontCare io.req_pri_rdy := false.B io.req_sec_rdy := sec_rdy && rpq.io.enq.ready io.mem_acquire.valid := false.B io.mem_acquire.bits := DontCare io.refill.valid := false.B io.refill.bits := DontCare io.replay.valid := false.B io.replay.bits := DontCare io.wb_req.valid := false.B io.wb_req.bits := DontCare io.resp.valid := false.B io.resp.bits := DontCare io.commit_val := false.B io.commit_addr := req.addr io.commit_coh := coh_on_grant io.meta_read.valid := false.B io.meta_read.bits := DontCare io.mem_finish.valid := false.B io.mem_finish.bits := DontCare io.lb_write.valid := false.B io.lb_write.bits := DontCare io.lb_read.valid := false.B io.lb_read.bits := DontCare io.mem_grant.ready := false.B when (io.req_sec_val && io.req_sec_rdy) { req.uop.mem_cmd := dirtier_cmd when (is_hit_again) { new_coh := dirtier_coh } } def handle_pri_req(old_state: UInt): UInt = { val new_state = WireInit(old_state) grantack.valid := false.B refill_ctr := 0.U assert(rpq.io.enq.ready) req := io.req val old_coh = io.req.old_meta.coh req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back when (io.req.tag_match) { val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // set dirty bit assert(isWrite(io.req.uop.mem_cmd)) new_coh := coh_on_hit new_state := s_drain_rpq } .otherwise { // upgrade permissions new_coh := old_coh new_state := s_refill_req } } .otherwise { // refill and writeback if necessary new_coh := ClientMetadata.onReset new_state := s_refill_req } new_state } when (state === s_invalid) { io.req_pri_rdy := true.B grant_had_data := false.B when (io.req_pri_val && io.req_pri_rdy) { state := handle_pri_req(state) } } .elsewhen (state === s_refill_req) { io.mem_acquire.valid := true.B // TODO: Use AcquirePerm if just doing permissions acquire io.mem_acquire.bits := edge.AcquireBlock( fromSource = io.id, toAddress = Cat(req_tag, req_idx) << blockOffBits, lgSize = lgCacheBlockBytes.U, growPermissions = grow_param)._2 when (io.mem_acquire.fire) { state := s_refill_resp } } .elsewhen (state === s_refill_resp) { when (edge.hasData(io.mem_grant.bits)) { io.mem_grant.ready := io.lb_write.ready io.lb_write.valid := io.mem_grant.valid io.lb_write.bits.id := io.id io.lb_write.bits.offset := refill_address_inc >> rowOffBits io.lb_write.bits.data := io.mem_grant.bits.data } .otherwise { io.mem_grant.ready := true.B } when (io.mem_grant.fire) { grant_had_data := edge.hasData(io.mem_grant.bits) } when (refill_done) { grantack.valid := edge.isRequest(io.mem_grant.bits) grantack.bits := edge.GrantAck(io.mem_grant.bits) state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq) assert(!(!grant_had_data && req_needs_wb)) commit_line := false.B new_coh := coh_on_grant } } .elsewhen (state === s_drain_rpq_loads) { val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) && !isWrite(rpq.io.deq.bits.uop.mem_cmd) && (rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay // drain all loads for now val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWordscoreDataBytes)-1, log2Up(wordBytes)) val data = io.lb_resp val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W)) val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed, Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)), data_word, false.B, wordBytes) rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load io.lb_read.valid := rpq.io.deq.valid && drain_load io.lb_read.bits.id := io.id io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load io.resp.bits.uop := rpq.io.deq.bits.uop io.resp.bits.data := loadgen.data io.resp.bits.is_hella := rpq.io.deq.bits.is_hella when (rpq.io.deq.fire) { commit_line := true.B } .elsewhen (rpq.io.empty && !commit_line) { when (!rpq.io.enq.fire) { state := s_mem_finish_1 finish_to_prefetch := enablePrefetching.B } } .elsewhen (rpq.io.empty \|\| (rpq.io.deq.valid && !drain_load)) { // io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired // The prefetcher should consider fetching the next line io.commit_val := true.B state := s_meta_read } } .elsewhen (state === s_meta_read) { io.meta_read.valid := !io.prober_state.valid \|\| !grantack.valid \|\| (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx) io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := req.way_en when (io.meta_read.fire) { state := s_meta_resp_1 } } .elsewhen (state === s_meta_resp_1) { state := s_meta_resp_2 } .elsewhen (state === s_meta_resp_2) { val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1 state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read Mux(needs_wb, s_meta_clear, s_commit_line)) } .elsewhen (state === s_meta_clear) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := coh_on_clear io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_wb_req } } .elsewhen (state === s_wb_req) { io.wb_req.valid := true.B io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.param := shrink_param io.wb_req.bits.way_en := req.way_en io.wb_req.bits.source := io.id io.wb_req.bits.voluntary := true.B when (io.wb_req.fire) { state := s_wb_resp } } .elsewhen (state === s_wb_resp) { when (io.wb_resp) { state := s_commit_line } } .elsewhen (state === s_commit_line) { io.lb_read.valid := true.B io.lb_read.bits.id := io.id io.lb_read.bits.offset := refill_ctr io.refill.valid := io.lb_read.fire io.refill.bits.addr := req_block_addr \| (refill_ctr << rowOffBits) io.refill.bits.way_en := req.way_en io.refill.bits.wmask := ~(0.U(rowWords.W)) io.refill.bits.data := io.lb_resp when (io.refill.fire) { refill_ctr := refill_ctr + 1.U when (refill_ctr === (cacheDataBeats - 1).U) { state := s_drain_rpq } } } .elsewhen (state === s_drain_rpq) { io.replay <> rpq.io.deq io.replay.bits.way_en := req.way_en io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) { // Set dirty bit val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd) assert(is_hit, "We still don't have permissions for this store") new_coh := coh_on_hit } when (rpq.io.empty && !rpq.io.enq.valid) { state := s_meta_write_req } } .elsewhen (state === s_meta_write_req) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := new_coh io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_mem_finish_1 finish_to_prefetch := false.B } } .elsewhen (state === s_mem_finish_1) { io.mem_finish.valid := grantack.valid io.mem_finish.bits := grantack.bits when (io.mem_finish.fire \|\| !grantack.valid) { grantack.valid := false.B state := s_mem_finish_2 } } .elsewhen (state === s_mem_finish_2) { state := Mux(finish_to_prefetch, s_prefetch, s_invalid) } .elsewhen (state === s_prefetch) { io.req_pri_rdy := true.B when ((io.req_sec_val && !io.req_sec_rdy) \|\| io.clear_prefetch) { state := s_invalid } .elsewhen (io.req_sec_val && io.req_sec_rdy) { val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // Proceed with refill new_coh := coh_on_hit state := s_meta_read } .otherwise { // Reacquire this line new_coh := ClientMetadata.onReset state := s_refill_req } } .elsewhen (io.req_pri_val && io.req_pri_rdy) { grant_had_data := false.B state := handle_pri_req(state) } } } class BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Decoupled(new BoomDCacheReq)) val resp = Decoupled(new BoomDCacheResp) val mem_access = Decoupled(new TLBundleA(edge.bundle)) val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle))) // We don't need brupdate in here because uncacheable operations are guaranteed non-speculative }) def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits) def wordFromBeat(addr: UInt, dat: UInt) = { val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W)) (dat >> shift)(wordBits-1, 0) } val req = Reg(new BoomDCacheReq) val grant_word = Reg(UInt(wordBits.W)) val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.req.ready := state === s_idle val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes) val a_source = id.U val a_address = req.addr val a_size = req.uop.mem_size val a_data = Fill(beatWords, req.data) val get = edge.Get(a_source, a_address, a_size)._2 val put = edge.Put(a_source, a_address, a_size, a_data)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array( M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert(state === s_idle \|\| !isAMO(req.uop.mem_cmd)) (0.U).asTypeOf(new TLBundleA(edge.bundle)) } assert(state === s_idle \|\| req.uop.mem_cmd =/= M_XSC) io.mem_access.valid := state === s_mem_access io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put)) val send_resp = isRead(req.uop.mem_cmd) io.resp.valid := (state === s_resp) && send_resp io.resp.bits.is_hella := req.is_hella io.resp.bits.uop := req.uop io.resp.bits.data := loadgen.data when (io.req.fire) { req := io.req.bits state := s_mem_access } when (io.mem_access.fire) { state := s_mem_ack } when (state === s_mem_ack && io.mem_ack.valid) { state := s_resp when (isRead(req.uop.mem_cmd)) { grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data) } } when (state === s_resp) { when (!send_resp \|\| io.resp.fire) { state := s_idle } } } class LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val id = UInt(log2Ceil(nLBEntries).W) val offset = UInt(log2Ceil(cacheDataBeats).W) def lb_addr = Cat(id, offset) } class LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p) { val data = UInt(encRowBits.W) } class LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p) { val id = UInt(log2Ceil(nLBEntries).W) val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe val req_is_probe = Input(Vec(memWidth, Bool())) val resp = Decoupled(new BoomDCacheResp) val secondary_miss = Output(Vec(memWidth, Bool())) val block_hit = Output(Vec(memWidth, Bool())) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val replay = Decoupled(new BoomDCacheReqInternal) val prefetch = Decoupled(new BoomDCacheReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence val wb_resp = Input(Bool()) val fence_rdy = Output(Bool()) val probe_rdy = Output(Bool()) }) val req_idx = OHToUInt(io.req.map(_.valid)) val req = io.req(req_idx) val req_is_probe = io.req_is_probe(0) for (w <- 0 until memWidth) io.req(w).ready := false.B val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher) else Module(new NullPrefetcher) io.prefetch <> prefetcher.io.prefetch val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U) // -------------------- // The MSHR SDQ val sdq_val = RegInit(0.U(cfg.nSDQ.W)) val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0)) val sdq_rdy = !sdq_val.andR val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd) val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W)) when (sdq_enq) { sdq(sdq_alloc_id) := req.bits.data } // -------------------- // The LineBuffer Data // Holds refilling lines, prefetched lines val lb = Mem(nLBEntries cacheDataBeats, UInt(encRowBits.W)) val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs)) val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs)) lb_read_arb.io.out.ready := false.B lb_write_arb.io.out.ready := true.B val lb_read_data = WireInit(0.U(encRowBits.W)) when (lb_write_arb.io.out.fire) { lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data) } .otherwise { lb_read_arb.io.out.ready := true.B when (lb_read_arb.io.out.fire) { lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr) } } def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w))) val idx_match = widthMap(w => idx_matches(w).reduce(_\|\|_)) val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w))) val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W))) val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs)) val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs)) val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs)) val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs)) val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs)) val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs)) val commit_vals = Wire(Vec(cfg.nMSHRs, Bool())) val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W))) val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata)) var sec_rdy = false.B io.fence_rdy := true.B io.probe_rdy := true.B io.mem_grant.ready := false.B val mshr_alloc_idx = Wire(UInt()) val pri_rdy = WireInit(false.B) val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx) val mshrs = (0 until cfg.nMSHRs) map { i => val mshr = Module(new BoomMSHR) mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W) for (w <- 0 until memWidth) { idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits) tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en } wb_tag_list(i) := mshr.io.wb_req.bits.tag mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val when (i.U === mshr_alloc_idx) { pri_rdy := mshr.io.req_pri_rdy } mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable mshr.io.req := req.bits mshr.io.req_is_probe := req_is_probe mshr.io.req.sdq_id := sdq_alloc_id // Clear because of a FENCE, a request to the same idx as a prefetched line, // a probe to that prefetched line, all mshrs are in use mshr.io.clear_prefetch := ((io.clear_all && !req.valid)\|\| (req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) \|\| (req_is_probe && idx_matches(req_idx)(i))) mshr.io.brupdate := io.brupdate mshr.io.exception := io.exception mshr.io.rob_pnr_idx := io.rob_pnr_idx mshr.io.rob_head_idx := io.rob_head_idx mshr.io.prober_state := io.prober_state mshr.io.wb_resp := io.wb_resp meta_write_arb.io.in(i) <> mshr.io.meta_write meta_read_arb.io.in(i) <> mshr.io.meta_read mshr.io.meta_resp := io.meta_resp wb_req_arb.io.in(i) <> mshr.io.wb_req replay_arb.io.in(i) <> mshr.io.replay refill_arb.io.in(i) <> mshr.io.refill lb_read_arb.io.in(i) <> mshr.io.lb_read mshr.io.lb_resp := lb_read_data lb_write_arb.io.in(i) <> mshr.io.lb_write commit_vals(i) := mshr.io.commit_val commit_addrs(i) := mshr.io.commit_addr commit_cohs(i) := mshr.io.commit_coh mshr.io.mem_grant.valid := false.B mshr.io.mem_grant.bits := DontCare when (io.mem_grant.bits.source === i.U) { mshr.io.mem_grant <> io.mem_grant } sec_rdy = sec_rdy \|\| (mshr.io.req_sec_rdy && mshr.io.req_sec_val) resp_arb.io.in(i) <> mshr.io.resp when (!mshr.io.req_pri_rdy) { io.fence_rdy := false.B } for (w <- 0 until memWidth) { when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) { io.probe_rdy := false.B } } mshr } // Try to round-robin the MSHRs val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W)) mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head)) when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) } io.meta_write <> meta_write_arb.io.out io.meta_read <> meta_read_arb.io.out io.wb_req <> wb_req_arb.io.out val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs)) var mmio_rdy = false.B val mmios = (0 until nIOMSHRs) map { i => val id = cfg.nMSHRs + 1 + i // +1 for wb unit val mshr = Module(new BoomIOMSHR(id)) mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready mmio_alloc_arb.io.in(i).bits := DontCare mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready mshr.io.req.bits := req.bits mmio_rdy = mmio_rdy \|\| mshr.io.req.ready mshr.io.mem_ack.bits := io.mem_grant.bits mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U when (io.mem_grant.bits.source === id.U) { io.mem_grant.ready := true.B } resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp when (!mshr.io.req.ready) { io.fence_rdy := false.B } mshr } mmio_alloc_arb.io.out.ready := req.valid && !cacheable TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access)) TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish)) val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false)) respq.io.brupdate := io.brupdate respq.io.flush := io.exception respq.io.enq <> resp_arb.io.out io.resp <> respq.io.deq for (w <- 0 until memWidth) { io.req(w).ready := (w.U === req_idx) && Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy)) io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w) io.block_hit(w) := idx_match(w) && tag_match(w) } io.refill <> refill_arb.io.out val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd) io.replay <> replay_arb.io.out io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id) when (io.replay.valid \|\| sdq_enq) { sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) \| PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq) } prefetcher.io.mshr_avail := RegNext(pri_rdy) prefetcher.io.req_val := RegNext(commit_vals.reduce(_\|\|_)) prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs)) prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out }	module BoomIOMSHR( // @[mshrs.scala:402:7] input clock, // @[mshrs.scala:402:7] input reset, // @[mshrs.scala:402:7] output io_req_ready, // @[mshrs.scala:405:14] input io_req_valid, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_uopc, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_inst, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_debug_inst, // @[mshrs.scala:405:14] input io_req_bits_uop_is_rvc, // @[mshrs.scala:405:14] input [39:0] io_req_bits_uop_debug_pc, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_iq_type, // @[mshrs.scala:405:14] input [9:0] io_req_bits_uop_fu_code, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_iw_state, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_is_br, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jalr, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jal, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sfb, // @[mshrs.scala:405:14] input [15:0] io_req_bits_uop_br_mask, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_br_tag, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ftq_idx, // @[mshrs.scala:405:14] input io_req_bits_uop_edge_inst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_pc_lob, // @[mshrs.scala:405:14] input io_req_bits_uop_taken, // @[mshrs.scala:405:14] input [19:0] io_req_bits_uop_imm_packed, // @[mshrs.scala:405:14] input [11:0] io_req_bits_uop_csr_addr, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_rob_idx, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ldq_idx, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_stq_idx, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_rxq_idx, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_pdst, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs1, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs2, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs3, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ppred, // @[mshrs.scala:405:14] input io_req_bits_uop_prs1_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs2_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs3_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_ppred_busy, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_stale_pdst, // @[mshrs.scala:405:14] input io_req_bits_uop_exception, // @[mshrs.scala:405:14] input [63:0] io_req_bits_uop_exc_cause, // @[mshrs.scala:405:14] input io_req_bits_uop_bypassable, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_mem_cmd, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_mem_size, // @[mshrs.scala:405:14] input io_req_bits_uop_mem_signed, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fence, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fencei, // @[mshrs.scala:405:14] input io_req_bits_uop_is_amo, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_ldq, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_stq, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] input io_req_bits_uop_is_unique, // @[mshrs.scala:405:14] input io_req_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_ldst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs2, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs3, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_val, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_dst_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] input io_req_bits_uop_frs3_en, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_val, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_single, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] input [39:0] io_req_bits_addr, // @[mshrs.scala:405:14] input [63:0] io_req_bits_data, // @[mshrs.scala:405:14] input io_req_bits_is_hella, // @[mshrs.scala:405:14] input io_resp_ready, // @[mshrs.scala:405:14] output io_resp_valid, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:405:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:405:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:405:14] output [15:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:405:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:405:14] output io_resp_bits_uop_taken, // @[mshrs.scala:405:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:405:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:405:14] output io_resp_bits_uop_exception, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:405:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:405:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:405:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:405:14] output io_resp_bits_is_hella, // @[mshrs.scala:405:14] input io_mem_access_ready, // @[mshrs.scala:405:14] output io_mem_access_valid, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_opcode, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_param, // @[mshrs.scala:405:14] output [3:0] io_mem_access_bits_size, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_source, // @[mshrs.scala:405:14] output [31:0] io_mem_access_bits_address, // @[mshrs.scala:405:14] output [15:0] io_mem_access_bits_mask, // @[mshrs.scala:405:14] output [127:0] io_mem_access_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_valid, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_opcode, // @[mshrs.scala:405:14] input [1:0] io_mem_ack_bits_param, // @[mshrs.scala:405:14] input [3:0] io_mem_ack_bits_size, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_source, // @[mshrs.scala:405:14] input [3:0] io_mem_ack_bits_sink, // @[mshrs.scala:405:14] input io_mem_ack_bits_denied, // @[mshrs.scala:405:14] input [127:0] io_mem_ack_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_bits_corrupt // @[mshrs.scala:405:14] ); wire io_req_valid_0 = io_req_valid; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[mshrs.scala:402:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[mshrs.scala:402:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[mshrs.scala:402:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[mshrs.scala:402:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[mshrs.scala:402:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[mshrs.scala:402:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[mshrs.scala:402:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[mshrs.scala:402:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[mshrs.scala:402:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[mshrs.scala:402:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[mshrs.scala:402:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[mshrs.scala:402:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[mshrs.scala:402:7] wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[mshrs.scala:402:7] wire io_req_bits_is_hella_0 = io_req_bits_is_hella; // @[mshrs.scala:402:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:402:7] wire io_mem_access_ready_0 = io_mem_access_ready; // @[mshrs.scala:402:7] wire io_mem_ack_valid_0 = io_mem_ack_valid; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_opcode_0 = io_mem_ack_bits_opcode; // @[mshrs.scala:402:7] wire [1:0] io_mem_ack_bits_param_0 = io_mem_ack_bits_param; // @[mshrs.scala:402:7] wire [3:0] io_mem_ack_bits_size_0 = io_mem_ack_bits_size; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_source_0 = io_mem_ack_bits_source; // @[mshrs.scala:402:7] wire [3:0] io_mem_ack_bits_sink_0 = io_mem_ack_bits_sink; // @[mshrs.scala:402:7] wire io_mem_ack_bits_denied_0 = io_mem_ack_bits_denied; // @[mshrs.scala:402:7] wire [127:0] io_mem_ack_bits_data_0 = io_mem_ack_bits_data; // @[mshrs.scala:402:7] wire io_mem_ack_bits_corrupt_0 = io_mem_ack_bits_corrupt; // @[mshrs.scala:402:7] wire io_mem_access_bits_corrupt = 1'h0; // @[mshrs.scala:402:7] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire get_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_74 = 1'h0; // @[Parameters.scala:684:54] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire put_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_WIRE_corrupt = 1'h0; // @[mshrs.scala:439:46] wire _atomics_legal_T_34 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_40 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_93 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_99 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_152 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_158 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_2 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_211 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_217 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_3 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_270 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_276 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_4 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_329 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_335 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_5 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_388 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_394 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_6 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_447 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_453 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_7 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_506 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_512 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_8 = 1'h0; // @[Misc.scala:206:21] wire _atomics_T_1_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_3_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_5_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_7_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_9_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_11_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_13_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_15_corrupt = 1'h0; // @[mshrs.scala:439:75] wire atomics_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_42_corrupt = 1'h0; // @[mshrs.scala:457:66] wire _io_mem_access_bits_T_43_corrupt = 1'h0; // @[mshrs.scala:457:29] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire [2:0] get_source = 3'h5; // @[Edges.scala:460:17] wire [2:0] put_source = 3'h5; // @[Edges.scala:480:17] wire [2:0] atomics_a_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_source = 3'h5; // @[mshrs.scala:457:66] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[mshrs.scala:439:46] wire [2:0] _atomics_WIRE_param = 3'h0; // @[mshrs.scala:439:46] wire [2:0] _atomics_WIRE_source = 3'h0; // @[mshrs.scala:439:46] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_param = 3'h0; // @[mshrs.scala:457:66] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_41 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_42 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_43 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_44 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_59 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_60 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_61 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_62 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_100 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_101 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_102 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_103 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_118 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_119 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_120 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_121 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_159 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_160 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_161 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_177 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_178 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_179 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_180 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_220 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_221 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_236 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_237 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_238 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_239 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_277 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_278 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_279 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_280 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_295 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_296 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_297 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_298 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_336 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_337 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_338 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_339 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_354 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_355 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_356 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_357 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_395 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_396 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_397 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_398 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_413 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_414 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_415 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_416 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_454 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_455 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_456 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_457 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_472 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_473 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_474 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_475 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_513 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_514 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_515 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_516 = 1'h1; // @[Parameters.scala:684:29] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [127:0] get_data = 128'h0; // @[Edges.scala:460:17] wire [127:0] _atomics_WIRE_data = 128'h0; // @[mshrs.scala:439:46] wire [15:0] _atomics_WIRE_mask = 16'h0; // @[mshrs.scala:439:46] wire [31:0] _atomics_WIRE_address = 32'h0; // @[mshrs.scala:439:46] wire [3:0] _atomics_WIRE_size = 4'h0; // @[mshrs.scala:439:46] wire _io_req_ready_T; // @[mshrs.scala:427:25] wire _io_resp_valid_T_1; // @[mshrs.scala:461:43] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_mem_access_valid_T; // @[mshrs.scala:456:32] wire [2:0] _io_mem_access_bits_T_43_opcode; // @[mshrs.scala:457:29] wire [2:0] _io_mem_access_bits_T_43_param; // @[mshrs.scala:457:29] wire [3:0] _io_mem_access_bits_T_43_size; // @[mshrs.scala:457:29] wire [2:0] _io_mem_access_bits_T_43_source; // @[mshrs.scala:457:29] wire [31:0] _io_mem_access_bits_T_43_address; // @[mshrs.scala:457:29] wire [15:0] _io_mem_access_bits_T_43_mask; // @[mshrs.scala:457:29] wire [127:0] _io_mem_access_bits_T_43_data; // @[mshrs.scala:457:29] wire io_req_ready_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:402:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:402:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:402:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:402:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:402:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:402:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:402:7] wire io_resp_valid_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_opcode_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_param_0; // @[mshrs.scala:402:7] wire [3:0] io_mem_access_bits_size_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_source_0; // @[mshrs.scala:402:7] wire [31:0] io_mem_access_bits_address_0; // @[mshrs.scala:402:7] wire [15:0] io_mem_access_bits_mask_0; // @[mshrs.scala:402:7] wire [127:0] io_mem_access_bits_data_0; // @[mshrs.scala:402:7] wire io_mem_access_valid_0; // @[mshrs.scala:402:7] reg [6:0] req_uop_uopc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uopc_0 = req_uop_uopc; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_inst_0 = req_uop_inst; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_inst_0 = req_uop_debug_inst; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_rvc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_rvc_0 = req_uop_is_rvc; // @[mshrs.scala:402:7, :421:16] reg [39:0] req_uop_debug_pc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_pc_0 = req_uop_debug_pc; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_iq_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iq_type_0 = req_uop_iq_type; // @[mshrs.scala:402:7, :421:16] reg [9:0] req_uop_fu_code; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fu_code_0 = req_uop_fu_code; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_br_type_0 = req_uop_ctrl_br_type; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op1_sel_0 = req_uop_ctrl_op1_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op2_sel_0 = req_uop_ctrl_op2_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_imm_sel_0 = req_uop_ctrl_imm_sel; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op_fcn_0 = req_uop_ctrl_op_fcn; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_fcn_dw_0 = req_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_csr_cmd_0 = req_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_load; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_load_0 = req_uop_ctrl_is_load; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_sta; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_sta_0 = req_uop_ctrl_is_sta; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_std; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_std_0 = req_uop_ctrl_is_std; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_iw_state; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_state_0 = req_uop_iw_state; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p1_poisoned_0 = req_uop_iw_p1_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p2_poisoned_0 = req_uop_iw_p2_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_br; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_br_0 = req_uop_is_br; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jalr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jalr_0 = req_uop_is_jalr; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jal; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jal_0 = req_uop_is_jal; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sfb; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sfb_0 = req_uop_is_sfb; // @[mshrs.scala:402:7, :421:16] reg [15:0] req_uop_br_mask; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_mask_0 = req_uop_br_mask; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_br_tag; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_tag_0 = req_uop_br_tag; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ftq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ftq_idx_0 = req_uop_ftq_idx; // @[mshrs.scala:402:7, :421:16] reg req_uop_edge_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_edge_inst_0 = req_uop_edge_inst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pc_lob_0 = req_uop_pc_lob; // @[mshrs.scala:402:7, :421:16] reg req_uop_taken; // @[mshrs.scala:421:16] assign io_resp_bits_uop_taken_0 = req_uop_taken; // @[mshrs.scala:402:7, :421:16] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_imm_packed_0 = req_uop_imm_packed; // @[mshrs.scala:402:7, :421:16] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_csr_addr_0 = req_uop_csr_addr; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_rob_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rob_idx_0 = req_uop_rob_idx; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ldq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldq_idx_0 = req_uop_ldq_idx; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_stq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stq_idx_0 = req_uop_stq_idx; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rxq_idx_0 = req_uop_rxq_idx; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pdst_0 = req_uop_pdst; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_0 = req_uop_prs1; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_0 = req_uop_prs2; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_0 = req_uop_prs3; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ppred; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_0 = req_uop_ppred; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs1_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_busy_0 = req_uop_prs1_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs2_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_busy_0 = req_uop_prs2_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs3_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_busy_0 = req_uop_prs3_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_ppred_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_busy_0 = req_uop_ppred_busy; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stale_pdst_0 = req_uop_stale_pdst; // @[mshrs.scala:402:7, :421:16] reg req_uop_exception; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exception_0 = req_uop_exception; // @[mshrs.scala:402:7, :421:16] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exc_cause_0 = req_uop_exc_cause; // @[mshrs.scala:402:7, :421:16] reg req_uop_bypassable; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bypassable_0 = req_uop_bypassable; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_cmd_0 = req_uop_mem_cmd; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_mem_size; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_size_0 = req_uop_mem_size; // @[mshrs.scala:402:7, :421:16] wire [1:0] size = req_uop_mem_size; // @[AMOALU.scala:11:18] reg req_uop_mem_signed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_signed_0 = req_uop_mem_signed; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fence; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fence_0 = req_uop_is_fence; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fencei; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fencei_0 = req_uop_is_fencei; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_amo; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_amo_0 = req_uop_is_amo; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_ldq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_ldq_0 = req_uop_uses_ldq; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_stq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_stq_0 = req_uop_uses_stq; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sys_pc2epc_0 = req_uop_is_sys_pc2epc; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_unique; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_unique_0 = req_uop_is_unique; // @[mshrs.scala:402:7, :421:16] reg req_uop_flush_on_commit; // @[mshrs.scala:421:16] assign io_resp_bits_uop_flush_on_commit_0 = req_uop_flush_on_commit; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_is_rs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_is_rs1_0 = req_uop_ldst_is_rs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_ldst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_0 = req_uop_ldst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_0 = req_uop_lrs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_0 = req_uop_lrs2; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs3_0 = req_uop_lrs3; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_val_0 = req_uop_ldst_val; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_dst_rtype_0 = req_uop_dst_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_rtype_0 = req_uop_lrs1_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_rtype_0 = req_uop_lrs2_rtype; // @[mshrs.scala:402:7, :421:16] reg req_uop_frs3_en; // @[mshrs.scala:421:16] assign io_resp_bits_uop_frs3_en_0 = req_uop_frs3_en; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_val_0 = req_uop_fp_val; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_single; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_single_0 = req_uop_fp_single; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_pf_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_pf_if_0 = req_uop_xcpt_pf_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ae_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ae_if_0 = req_uop_xcpt_ae_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ma_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ma_if_0 = req_uop_xcpt_ma_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_debug_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_debug_if_0 = req_uop_bp_debug_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_xcpt_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_xcpt_if_0 = req_uop_bp_xcpt_if; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_fsrc_0 = req_uop_debug_fsrc; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_tsrc_0 = req_uop_debug_tsrc; // @[mshrs.scala:402:7, :421:16] reg [39:0] req_addr; // @[mshrs.scala:421:16] wire [39:0] _get_legal_T_14 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_14 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_4 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_63 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_122 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_181 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_240 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_299 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_358 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_417 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_476 = req_addr; // @[Parameters.scala:137:31] reg [63:0] req_data; // @[mshrs.scala:421:16] reg req_is_hella; // @[mshrs.scala:421:16] assign io_resp_bits_is_hella_0 = req_is_hella; // @[mshrs.scala:402:7, :421:16] reg [63:0] grant_word; // @[mshrs.scala:422:23] reg [1:0] state; // @[mshrs.scala:426:22] assign _io_req_ready_T = state == 2'h0; // @[mshrs.scala:426:22, :427:25] assign io_req_ready_0 = _io_req_ready_T; // @[mshrs.scala:402:7, :427:25] wire [127:0] a_data = {2{req_data}}; // @[mshrs.scala:421:16, :434:23] wire [127:0] put_data = a_data; // @[Edges.scala:480:17] wire [127:0] atomics_a_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_1_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_2_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_3_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_4_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_5_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_6_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_7_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_8_data = a_data; // @[Edges.scala:517:17] wire [39:0] _GEN = {req_addr[39:14], req_addr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_68 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_0 = {req_addr[39:17], req_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_69; // @[Parameters.scala:137:31] assign _put_legal_T_69 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_35; // @[Parameters.scala:137:31] assign _atomics_legal_T_35 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_94; // @[Parameters.scala:137:31] assign _atomics_legal_T_94 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_153; // @[Parameters.scala:137:31] assign _atomics_legal_T_153 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_212; // @[Parameters.scala:137:31] assign _atomics_legal_T_212 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_271; // @[Parameters.scala:137:31] assign _atomics_legal_T_271 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_330; // @[Parameters.scala:137:31] assign _atomics_legal_T_330 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_389; // @[Parameters.scala:137:31] assign _atomics_legal_T_389 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_448; // @[Parameters.scala:137:31] assign _atomics_legal_T_448 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_507; // @[Parameters.scala:137:31] assign _atomics_legal_T_507 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {req_addr[39:26], req_addr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {req_addr[39:28], req_addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31] assign _put_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_45; // @[Parameters.scala:137:31] assign _atomics_legal_T_45 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_104; // @[Parameters.scala:137:31] assign _atomics_legal_T_104 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_163; // @[Parameters.scala:137:31] assign _atomics_legal_T_163 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_222; // @[Parameters.scala:137:31] assign _atomics_legal_T_222 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_281; // @[Parameters.scala:137:31] assign _atomics_legal_T_281 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_340; // @[Parameters.scala:137:31] assign _atomics_legal_T_340 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_399; // @[Parameters.scala:137:31] assign _atomics_legal_T_399 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_458; // @[Parameters.scala:137:31] assign _atomics_legal_T_458 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_517; // @[Parameters.scala:137:31] assign _atomics_legal_T_517 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {req_addr[39:29], req_addr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31] assign _get_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31] assign _put_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31] assign _atomics_legal_T_24 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31] assign _atomics_legal_T_142 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_201; // @[Parameters.scala:137:31] assign _atomics_legal_T_201 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_260; // @[Parameters.scala:137:31] assign _atomics_legal_T_260 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_319; // @[Parameters.scala:137:31] assign _atomics_legal_T_319 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_378; // @[Parameters.scala:137:31] assign _atomics_legal_T_378 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_437; // @[Parameters.scala:137:31] assign _atomics_legal_T_437 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_496; // @[Parameters.scala:137:31] assign _atomics_legal_T_496 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46] wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_4 = {req_addr[39:29], req_addr[28:0] ^ 29'h10012000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31] assign _get_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31] assign _put_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46] wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] get_address = req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] atomics_a_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [39:0] _GEN_5 = {req_addr[39:32], req_addr[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_54; // @[Parameters.scala:137:31] assign _get_legal_T_54 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_54; // @[Parameters.scala:137:31] assign _put_legal_T_54 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_50; // @[Parameters.scala:137:31] assign _atomics_legal_T_50 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_109; // @[Parameters.scala:137:31] assign _atomics_legal_T_109 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_168; // @[Parameters.scala:137:31] assign _atomics_legal_T_168 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_227; // @[Parameters.scala:137:31] assign _atomics_legal_T_227 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_286; // @[Parameters.scala:137:31] assign _atomics_legal_T_286 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_345; // @[Parameters.scala:137:31] assign _atomics_legal_T_345 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_404; // @[Parameters.scala:137:31] assign _atomics_legal_T_404 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_463; // @[Parameters.scala:137:31] assign _atomics_legal_T_463 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_522; // @[Parameters.scala:137:31] assign _atomics_legal_T_522 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_55 = {1'h0, _get_legal_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_56 = _get_legal_T_55 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_57 = _get_legal_T_56; // @[Parameters.scala:137:46] wire _get_legal_T_58 = _get_legal_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_59 = _get_legal_T_18 \| _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_60 = _get_legal_T_59 \| _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_61 = _get_legal_T_60 \| _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_62 = _get_legal_T_61 \| _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_63 = _get_legal_T_62 \| _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_64 = _get_legal_T_63 \| _get_legal_T_48; // @[Parameters.scala:685:42] wire _get_legal_T_65 = _get_legal_T_64 \| _get_legal_T_53; // @[Parameters.scala:685:42] wire _get_legal_T_66 = _get_legal_T_65 \| _get_legal_T_58; // @[Parameters.scala:685:42] wire _get_legal_T_67 = _get_legal_T_66; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_68 \| _get_legal_T_67; // @[Parameters.scala:684:54, :686:26] wire [15:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [15:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_6 = {2'h0, req_uop_mem_size}; // @[Edges.scala:463:15] assign get_size = _GEN_6; // @[Edges.scala:460:17, :463:15] wire [3:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_6; // @[Edges.scala:463:15, :480:17] wire [3:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_6; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_6; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_6; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_6; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_6; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_6; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_6; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_6; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_6; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_6; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_size = get_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_sub_bit = req_addr[3]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_sub_bit = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_1 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_2 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_3 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_4 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_5 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_6 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_7 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_8 = req_addr[3]; // @[Misc.scala:210:26] wire _grant_word_shift_T = req_addr[3]; // @[package.scala:163:13] wire get_a_mask_sub_sub_sub_1_2 = get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_sub_nbit = ~get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_sub_0_2 = get_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_sub_acc_T = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_0_1 = _get_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _get_a_mask_sub_sub_sub_acc_T_1 = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_1_1 = _get_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = req_addr[2]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T = req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_2_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T_2 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_2_1 = get_a_mask_sub_sub_sub_1_1 \| _get_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_3_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_3 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_3_1 = get_a_mask_sub_sub_sub_1_1 \| _get_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = req_addr[1]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_3 = req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_4_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_4 = get_a_mask_sub_size & get_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_4_1 = get_a_mask_sub_sub_2_1 \| _get_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_5_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_5 = get_a_mask_sub_size & get_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_5_1 = get_a_mask_sub_sub_2_1 \| _get_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_6_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_6 = get_a_mask_sub_size & get_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_6_1 = get_a_mask_sub_sub_3_1 \| _get_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_7_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_7 = get_a_mask_sub_size & get_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_7_1 = get_a_mask_sub_sub_3_1 \| _get_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = req_addr[0]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_6 = req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 \| _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 \| _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_8 = get_a_mask_sub_4_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_8 = get_a_mask_size & get_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_8 = get_a_mask_sub_4_1 \| _get_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_9 = get_a_mask_sub_4_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_9 = get_a_mask_size & get_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_9 = get_a_mask_sub_4_1 \| _get_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_10 = get_a_mask_sub_5_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_10 = get_a_mask_size & get_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_10 = get_a_mask_sub_5_1 \| _get_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_11 = get_a_mask_sub_5_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_11 = get_a_mask_size & get_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_11 = get_a_mask_sub_5_1 \| _get_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_12 = get_a_mask_sub_6_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_12 = get_a_mask_size & get_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_12 = get_a_mask_sub_6_1 \| _get_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_13 = get_a_mask_sub_6_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_13 = get_a_mask_size & get_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_13 = get_a_mask_sub_6_1 \| _get_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_14 = get_a_mask_sub_7_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_14 = get_a_mask_size & get_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_14 = get_a_mask_sub_7_1 \| _get_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_15 = get_a_mask_sub_7_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_15 = get_a_mask_size & get_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_15 = get_a_mask_sub_7_1 \| _get_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_lo = {get_a_mask_lo_lo_hi, get_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_lo_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_hi = {get_a_mask_lo_hi_hi, get_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo_lo = {get_a_mask_acc_9, get_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_lo_hi = {get_a_mask_acc_11, get_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_lo = {get_a_mask_hi_lo_hi, get_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_hi_lo = {get_a_mask_acc_13, get_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi_hi = {get_a_mask_acc_15, get_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_hi = {get_a_mask_hi_hi_hi, get_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_75 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_7 = {req_addr[39:21], req_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31] assign _atomics_legal_T_68 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31] assign _atomics_legal_T_127 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31] assign _atomics_legal_T_186 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31] assign _atomics_legal_T_245 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31] assign _atomics_legal_T_304 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_363; // @[Parameters.scala:137:31] assign _atomics_legal_T_363 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_422; // @[Parameters.scala:137:31] assign _atomics_legal_T_422 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_481; // @[Parameters.scala:137:31] assign _atomics_legal_T_481 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_8 = {req_addr[39:26], req_addr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31] assign _atomics_legal_T_73 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31] assign _atomics_legal_T_132 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31] assign _atomics_legal_T_191 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31] assign _atomics_legal_T_250 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_309; // @[Parameters.scala:137:31] assign _atomics_legal_T_309 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_368; // @[Parameters.scala:137:31] assign _atomics_legal_T_368 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_427; // @[Parameters.scala:137:31] assign _atomics_legal_T_427 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_486; // @[Parameters.scala:137:31] assign _atomics_legal_T_486 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46] wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46] wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46] wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_55 = {1'h0, _put_legal_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_56 = _put_legal_T_55 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_57 = _put_legal_T_56; // @[Parameters.scala:137:46] wire _put_legal_T_58 = _put_legal_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_59 = _put_legal_T_18 \| _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_60 = _put_legal_T_59 \| _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_61 = _put_legal_T_60 \| _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_62 = _put_legal_T_61 \| _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_63 = _put_legal_T_62 \| _put_legal_T_43; // @[Parameters.scala:685:42] wire _put_legal_T_64 = _put_legal_T_63 \| _put_legal_T_48; // @[Parameters.scala:685:42] wire _put_legal_T_65 = _put_legal_T_64 \| _put_legal_T_53; // @[Parameters.scala:685:42] wire _put_legal_T_66 = _put_legal_T_65 \| _put_legal_T_58; // @[Parameters.scala:685:42] wire _put_legal_T_67 = _put_legal_T_66; // @[Parameters.scala:684:54, :685:42] wire [40:0] _put_legal_T_70 = {1'h0, _put_legal_T_69}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_71 = _put_legal_T_70 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_72 = _put_legal_T_71; // @[Parameters.scala:137:46] wire _put_legal_T_73 = _put_legal_T_72 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_76 = _put_legal_T_75 \| _put_legal_T_67; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_76; // @[Parameters.scala:686:26] wire [15:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [15:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_size = put_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_sub_1_2 = put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_sub_nbit = ~put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_sub_0_2 = put_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_sub_acc_T = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_0_1 = _put_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _put_a_mask_sub_sub_sub_acc_T_1 = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_1_1 = _put_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_2_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T_2 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_2_1 = put_a_mask_sub_sub_sub_1_1 \| _put_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_3_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_3 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_3_1 = put_a_mask_sub_sub_sub_1_1 \| _put_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_4_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_4 = put_a_mask_sub_size & put_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_4_1 = put_a_mask_sub_sub_2_1 \| _put_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_5_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_5 = put_a_mask_sub_size & put_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_5_1 = put_a_mask_sub_sub_2_1 \| _put_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_6_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_6 = put_a_mask_sub_size & put_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_6_1 = put_a_mask_sub_sub_3_1 \| _put_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_7_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_7 = put_a_mask_sub_size & put_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_7_1 = put_a_mask_sub_sub_3_1 \| _put_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 \| _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 \| _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_8 = put_a_mask_sub_4_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_8 = put_a_mask_size & put_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_8 = put_a_mask_sub_4_1 \| _put_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_9 = put_a_mask_sub_4_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_9 = put_a_mask_size & put_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_9 = put_a_mask_sub_4_1 \| _put_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_10 = put_a_mask_sub_5_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_10 = put_a_mask_size & put_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_10 = put_a_mask_sub_5_1 \| _put_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_11 = put_a_mask_sub_5_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_11 = put_a_mask_size & put_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_11 = put_a_mask_sub_5_1 \| _put_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_12 = put_a_mask_sub_6_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_12 = put_a_mask_size & put_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_12 = put_a_mask_sub_6_1 \| _put_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_13 = put_a_mask_sub_6_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_13 = put_a_mask_size & put_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_13 = put_a_mask_sub_6_1 \| _put_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_14 = put_a_mask_sub_7_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_14 = put_a_mask_size & put_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_14 = put_a_mask_sub_7_1 \| _put_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_15 = put_a_mask_sub_7_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_15 = put_a_mask_size & put_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_15 = put_a_mask_sub_7_1 \| _put_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_lo = {put_a_mask_lo_lo_hi, put_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_lo_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_hi = {put_a_mask_lo_hi_hi, put_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo_lo = {put_a_mask_acc_9, put_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_lo_hi = {put_a_mask_acc_11, put_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_lo = {put_a_mask_hi_lo_hi, put_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_hi_lo = {put_a_mask_acc_13, put_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi_hi = {put_a_mask_acc_15, put_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_hi = {put_a_mask_hi_hi_hi, put_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_9 = {req_addr[39:28], req_addr[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31] assign _atomics_legal_T_19 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31] assign _atomics_legal_T_78 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31] assign _atomics_legal_T_137 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31] assign _atomics_legal_T_196 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_255; // @[Parameters.scala:137:31] assign _atomics_legal_T_255 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_314; // @[Parameters.scala:137:31] assign _atomics_legal_T_314 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_373; // @[Parameters.scala:137:31] assign _atomics_legal_T_373 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_432; // @[Parameters.scala:137:31] assign _atomics_legal_T_432 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_491; // @[Parameters.scala:137:31] assign _atomics_legal_T_491 = _GEN_9; // @[Parameters.scala:137:31] wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46] wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46] wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_29 = _atomics_legal_T_8 \| _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_30 = _atomics_legal_T_29 \| _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_31 = _atomics_legal_T_30 \| _atomics_legal_T_23; // @[Parameters.scala:685:42] wire _atomics_legal_T_32 = _atomics_legal_T_31 \| _atomics_legal_T_28; // @[Parameters.scala:685:42] wire _atomics_legal_T_33 = _atomics_legal_T_32; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_57 = _atomics_legal_T_33; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_36 = {1'h0, _atomics_legal_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_38 = _atomics_legal_T_37; // @[Parameters.scala:137:46] wire _atomics_legal_T_39 = _atomics_legal_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_46 = {1'h0, _atomics_legal_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_47 = _atomics_legal_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_48 = _atomics_legal_T_47; // @[Parameters.scala:137:46] wire _atomics_legal_T_49 = _atomics_legal_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_51 = {1'h0, _atomics_legal_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_52 = _atomics_legal_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_53 = _atomics_legal_T_52; // @[Parameters.scala:137:46] wire _atomics_legal_T_54 = _atomics_legal_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_55 = _atomics_legal_T_49 \| _atomics_legal_T_54; // @[Parameters.scala:685:42] wire _atomics_legal_T_56 = _atomics_legal_T_55; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_58 = _atomics_legal_T_57; // @[Parameters.scala:686:26] wire atomics_legal = _atomics_legal_T_58 \| _atomics_legal_T_56; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [15:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size = atomics_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit = ~atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1 = _atomics_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1 = atomics_a_mask_sub_sub_sub_1_1 \| _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1 = atomics_a_mask_sub_sub_sub_1_1 \| _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size & atomics_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1 = atomics_a_mask_sub_sub_2_1 \| _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size & atomics_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1 = atomics_a_mask_sub_sub_2_1 \| _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size & atomics_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1 = atomics_a_mask_sub_sub_3_1 \| _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size & atomics_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1 = atomics_a_mask_sub_sub_3_1 \| _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_4_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_4_1 \| _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_4_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_4_1 \| _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_5_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_5_1 \| _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_5_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_5_1 \| _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_6_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_6_1 \| _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_6_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_6_1 \| _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_7_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_7_1 \| _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_7_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_7_1 \| _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo = {atomics_a_mask_lo_lo_hi, atomics_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi = {atomics_a_mask_lo_hi_hi, atomics_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo = {atomics_a_mask_hi_lo_hi, atomics_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi = {atomics_a_mask_hi_hi_hi, atomics_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46] wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46] wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46] wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46] wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_88 = _atomics_legal_T_67 \| _atomics_legal_T_72; // @[Parameters.scala:685:42] wire _atomics_legal_T_89 = _atomics_legal_T_88 \| _atomics_legal_T_77; // @[Parameters.scala:685:42] wire _atomics_legal_T_90 = _atomics_legal_T_89 \| _atomics_legal_T_82; // @[Parameters.scala:685:42] wire _atomics_legal_T_91 = _atomics_legal_T_90 \| _atomics_legal_T_87; // @[Parameters.scala:685:42] wire _atomics_legal_T_92 = _atomics_legal_T_91; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_116 = _atomics_legal_T_92; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_95 = {1'h0, _atomics_legal_T_94}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_96 = _atomics_legal_T_95 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_97 = _atomics_legal_T_96; // @[Parameters.scala:137:46] wire _atomics_legal_T_98 = _atomics_legal_T_97 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_105 = {1'h0, _atomics_legal_T_104}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_106 = _atomics_legal_T_105 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_107 = _atomics_legal_T_106; // @[Parameters.scala:137:46] wire _atomics_legal_T_108 = _atomics_legal_T_107 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_110 = {1'h0, _atomics_legal_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_111 = _atomics_legal_T_110 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_112 = _atomics_legal_T_111; // @[Parameters.scala:137:46] wire _atomics_legal_T_113 = _atomics_legal_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_114 = _atomics_legal_T_108 \| _atomics_legal_T_113; // @[Parameters.scala:685:42] wire _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_117 = _atomics_legal_T_116; // @[Parameters.scala:686:26] wire atomics_legal_1 = _atomics_legal_T_117 \| _atomics_legal_T_115; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [15:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_1 = atomics_a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 \| _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 \| _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_1 = atomics_a_mask_sub_sub_2_1_1 \| _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_1 = atomics_a_mask_sub_sub_2_1_1 \| _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_1 = atomics_a_mask_sub_sub_3_1_1 \| _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_1 = atomics_a_mask_sub_sub_3_1_1 \| _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_1 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_1 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_1 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_1 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_1 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_1 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_1 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_1 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_1 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_4_1_1 \| _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_1 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_4_1_1 \| _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_1 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_5_1_1 \| _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_1 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_5_1_1 \| _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_1 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_6_1_1 \| _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_1 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_6_1_1 \| _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_1 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_7_1_1 \| _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_1 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_7_1_1 \| _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_1 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_1 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_lo_lo_hi_1, atomics_a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_1 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_1 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_lo_hi_hi_1, atomics_a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_1 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_1 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_hi_lo_hi_1, atomics_a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_1 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_1 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_hi_hi_hi_1, atomics_a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46] wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46] wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46] wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46] wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46] wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_147 = _atomics_legal_T_126 \| _atomics_legal_T_131; // @[Parameters.scala:685:42] wire _atomics_legal_T_148 = _atomics_legal_T_147 \| _atomics_legal_T_136; // @[Parameters.scala:685:42] wire _atomics_legal_T_149 = _atomics_legal_T_148 \| _atomics_legal_T_141; // @[Parameters.scala:685:42] wire _atomics_legal_T_150 = _atomics_legal_T_149 \| _atomics_legal_T_146; // @[Parameters.scala:685:42] wire _atomics_legal_T_151 = _atomics_legal_T_150; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_175 = _atomics_legal_T_151; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_154 = {1'h0, _atomics_legal_T_153}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_155 = _atomics_legal_T_154 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_156 = _atomics_legal_T_155; // @[Parameters.scala:137:46] wire _atomics_legal_T_157 = _atomics_legal_T_156 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_164 = {1'h0, _atomics_legal_T_163}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_165 = _atomics_legal_T_164 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_166 = _atomics_legal_T_165; // @[Parameters.scala:137:46] wire _atomics_legal_T_167 = _atomics_legal_T_166 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_169 = {1'h0, _atomics_legal_T_168}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_170 = _atomics_legal_T_169 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_171 = _atomics_legal_T_170; // @[Parameters.scala:137:46] wire _atomics_legal_T_172 = _atomics_legal_T_171 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_173 = _atomics_legal_T_167 \| _atomics_legal_T_172; // @[Parameters.scala:685:42] wire _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_176 = _atomics_legal_T_175; // @[Parameters.scala:686:26] wire atomics_legal_2 = _atomics_legal_T_176 \| _atomics_legal_T_174; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [15:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_2 = atomics_a_mask_sizeOH_2[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 \| _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 \| _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_4_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_2 = atomics_a_mask_sub_sub_2_1_2 \| _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_5_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_2 = atomics_a_mask_sub_sub_2_1_2 \| _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_6_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_2 = atomics_a_mask_sub_sub_3_1_2 \| _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_7_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_2 = atomics_a_mask_sub_sub_3_1_2 \| _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_2 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_2 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_2 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_2 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_2 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_2 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_2 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_2 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_2 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_4_1_2 \| _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_2 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_4_1_2 \| _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_2 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_5_1_2 \| _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_2 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_5_1_2 \| _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_2 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_6_1_2 \| _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_2 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_6_1_2 \| _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_2 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_7_1_2 \| _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_2 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_7_1_2 \| _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_2 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_2 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_lo_lo_hi_2, atomics_a_mask_lo_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_2 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_2 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_lo_hi_hi_2, atomics_a_mask_lo_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_2 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_2 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_hi_lo_hi_2, atomics_a_mask_hi_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_2 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_2 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_hi_hi_hi_2, atomics_a_mask_hi_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46] wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46] wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46] wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46] wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_202 = {1'h0, _atomics_legal_T_201}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_203 = _atomics_legal_T_202 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_204 = _atomics_legal_T_203; // @[Parameters.scala:137:46] wire _atomics_legal_T_205 = _atomics_legal_T_204 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_206 = _atomics_legal_T_185 \| _atomics_legal_T_190; // @[Parameters.scala:685:42] wire _atomics_legal_T_207 = _atomics_legal_T_206 \| _atomics_legal_T_195; // @[Parameters.scala:685:42] wire _atomics_legal_T_208 = _atomics_legal_T_207 \| _atomics_legal_T_200; // @[Parameters.scala:685:42] wire _atomics_legal_T_209 = _atomics_legal_T_208 \| _atomics_legal_T_205; // @[Parameters.scala:685:42] wire _atomics_legal_T_210 = _atomics_legal_T_209; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_234 = _atomics_legal_T_210; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_213 = {1'h0, _atomics_legal_T_212}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_214 = _atomics_legal_T_213 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_215 = _atomics_legal_T_214; // @[Parameters.scala:137:46] wire _atomics_legal_T_216 = _atomics_legal_T_215 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_223 = {1'h0, _atomics_legal_T_222}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_224 = _atomics_legal_T_223 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_225 = _atomics_legal_T_224; // @[Parameters.scala:137:46] wire _atomics_legal_T_226 = _atomics_legal_T_225 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_228 = {1'h0, _atomics_legal_T_227}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_229 = _atomics_legal_T_228 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_230 = _atomics_legal_T_229; // @[Parameters.scala:137:46] wire _atomics_legal_T_231 = _atomics_legal_T_230 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_232 = _atomics_legal_T_226 \| _atomics_legal_T_231; // @[Parameters.scala:685:42] wire _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_235 = _atomics_legal_T_234; // @[Parameters.scala:686:26] wire atomics_legal_3 = _atomics_legal_T_235 \| _atomics_legal_T_233; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [15:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_3 = atomics_a_mask_sizeOH_3[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 \| _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 \| _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_4_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_3 = atomics_a_mask_sub_sub_2_1_3 \| _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_5_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_3 = atomics_a_mask_sub_sub_2_1_3 \| _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_6_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_3 = atomics_a_mask_sub_sub_3_1_3 \| _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_7_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_3 = atomics_a_mask_sub_sub_3_1_3 \| _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_3 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_3 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_3 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_3 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_3 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_3 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_3 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_3 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_3 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_4_1_3 \| _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_3 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_4_1_3 \| _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_3 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_5_1_3 \| _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_3 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_5_1_3 \| _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_3 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_6_1_3 \| _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_3 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_6_1_3 \| _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_3 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_7_1_3 \| _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_3 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_7_1_3 \| _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_3 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_3 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_lo_lo_hi_3, atomics_a_mask_lo_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_3 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_3 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_lo_hi_hi_3, atomics_a_mask_lo_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_3 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_3 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_hi_lo_hi_3, atomics_a_mask_hi_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_3 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_3 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_hi_hi_hi_3, atomics_a_mask_hi_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46] wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46] wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46] wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_256 = {1'h0, _atomics_legal_T_255}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_257 = _atomics_legal_T_256 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_258 = _atomics_legal_T_257; // @[Parameters.scala:137:46] wire _atomics_legal_T_259 = _atomics_legal_T_258 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_261 = {1'h0, _atomics_legal_T_260}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_262 = _atomics_legal_T_261 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_263 = _atomics_legal_T_262; // @[Parameters.scala:137:46] wire _atomics_legal_T_264 = _atomics_legal_T_263 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_265 = _atomics_legal_T_244 \| _atomics_legal_T_249; // @[Parameters.scala:685:42] wire _atomics_legal_T_266 = _atomics_legal_T_265 \| _atomics_legal_T_254; // @[Parameters.scala:685:42] wire _atomics_legal_T_267 = _atomics_legal_T_266 \| _atomics_legal_T_259; // @[Parameters.scala:685:42] wire _atomics_legal_T_268 = _atomics_legal_T_267 \| _atomics_legal_T_264; // @[Parameters.scala:685:42] wire _atomics_legal_T_269 = _atomics_legal_T_268; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_293 = _atomics_legal_T_269; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_272 = {1'h0, _atomics_legal_T_271}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_273 = _atomics_legal_T_272 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_274 = _atomics_legal_T_273; // @[Parameters.scala:137:46] wire _atomics_legal_T_275 = _atomics_legal_T_274 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_282 = {1'h0, _atomics_legal_T_281}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_283 = _atomics_legal_T_282 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_284 = _atomics_legal_T_283; // @[Parameters.scala:137:46] wire _atomics_legal_T_285 = _atomics_legal_T_284 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_287 = {1'h0, _atomics_legal_T_286}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_288 = _atomics_legal_T_287 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_289 = _atomics_legal_T_288; // @[Parameters.scala:137:46] wire _atomics_legal_T_290 = _atomics_legal_T_289 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_291 = _atomics_legal_T_285 \| _atomics_legal_T_290; // @[Parameters.scala:685:42] wire _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_294 = _atomics_legal_T_293; // @[Parameters.scala:686:26] wire atomics_legal_4 = _atomics_legal_T_294 \| _atomics_legal_T_292; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [15:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_4 = atomics_a_mask_sizeOH_4[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_18 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 \| _atomics_a_mask_sub_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_19 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 \| _atomics_a_mask_sub_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_36 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_4_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_4 = atomics_a_mask_sub_sub_2_1_4 \| _atomics_a_mask_sub_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_37 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_5_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_4 = atomics_a_mask_sub_sub_2_1_4 \| _atomics_a_mask_sub_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_38 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_6_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_4 = atomics_a_mask_sub_sub_3_1_4 \| _atomics_a_mask_sub_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_39 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_7_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_4 = atomics_a_mask_sub_sub_3_1_4 \| _atomics_a_mask_sub_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_4 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_4 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_4 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_4 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_4 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_4 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_4 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_4 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_72 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_72 = atomics_a_mask_size_4 & atomics_a_mask_eq_72; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_72 = atomics_a_mask_sub_4_1_4 \| _atomics_a_mask_acc_T_72; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_73 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_73 = atomics_a_mask_size_4 & atomics_a_mask_eq_73; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_73 = atomics_a_mask_sub_4_1_4 \| _atomics_a_mask_acc_T_73; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_74 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_74 = atomics_a_mask_size_4 & atomics_a_mask_eq_74; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_74 = atomics_a_mask_sub_5_1_4 \| _atomics_a_mask_acc_T_74; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_75 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_75 = atomics_a_mask_size_4 & atomics_a_mask_eq_75; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_75 = atomics_a_mask_sub_5_1_4 \| _atomics_a_mask_acc_T_75; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_76 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_76 = atomics_a_mask_size_4 & atomics_a_mask_eq_76; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_76 = atomics_a_mask_sub_6_1_4 \| _atomics_a_mask_acc_T_76; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_77 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_77 = atomics_a_mask_size_4 & atomics_a_mask_eq_77; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_77 = atomics_a_mask_sub_6_1_4 \| _atomics_a_mask_acc_T_77; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_78 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_78 = atomics_a_mask_size_4 & atomics_a_mask_eq_78; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_78 = atomics_a_mask_sub_7_1_4 \| _atomics_a_mask_acc_T_78; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_79 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_79 = atomics_a_mask_size_4 & atomics_a_mask_eq_79; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_79 = atomics_a_mask_sub_7_1_4 \| _atomics_a_mask_acc_T_79; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_4 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_4 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_lo_lo_hi_4, atomics_a_mask_lo_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_4 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_4 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_lo_hi_hi_4, atomics_a_mask_lo_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_4 = {atomics_a_mask_acc_73, atomics_a_mask_acc_72}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_4 = {atomics_a_mask_acc_75, atomics_a_mask_acc_74}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_hi_lo_hi_4, atomics_a_mask_hi_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_4 = {atomics_a_mask_acc_77, atomics_a_mask_acc_76}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_4 = {atomics_a_mask_acc_79, atomics_a_mask_acc_78}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_hi_hi_hi_4, atomics_a_mask_hi_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46] wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46] wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_310 = {1'h0, _atomics_legal_T_309}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_311 = _atomics_legal_T_310 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_312 = _atomics_legal_T_311; // @[Parameters.scala:137:46] wire _atomics_legal_T_313 = _atomics_legal_T_312 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_315 = {1'h0, _atomics_legal_T_314}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_316 = _atomics_legal_T_315 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_317 = _atomics_legal_T_316; // @[Parameters.scala:137:46] wire _atomics_legal_T_318 = _atomics_legal_T_317 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_320 = {1'h0, _atomics_legal_T_319}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_321 = _atomics_legal_T_320 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_322 = _atomics_legal_T_321; // @[Parameters.scala:137:46] wire _atomics_legal_T_323 = _atomics_legal_T_322 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_324 = _atomics_legal_T_303 \| _atomics_legal_T_308; // @[Parameters.scala:685:42] wire _atomics_legal_T_325 = _atomics_legal_T_324 \| _atomics_legal_T_313; // @[Parameters.scala:685:42] wire _atomics_legal_T_326 = _atomics_legal_T_325 \| _atomics_legal_T_318; // @[Parameters.scala:685:42] wire _atomics_legal_T_327 = _atomics_legal_T_326 \| _atomics_legal_T_323; // @[Parameters.scala:685:42] wire _atomics_legal_T_328 = _atomics_legal_T_327; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_352 = _atomics_legal_T_328; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_331 = {1'h0, _atomics_legal_T_330}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_332 = _atomics_legal_T_331 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_333 = _atomics_legal_T_332; // @[Parameters.scala:137:46] wire _atomics_legal_T_334 = _atomics_legal_T_333 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_341 = {1'h0, _atomics_legal_T_340}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_342 = _atomics_legal_T_341 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_343 = _atomics_legal_T_342; // @[Parameters.scala:137:46] wire _atomics_legal_T_344 = _atomics_legal_T_343 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_346 = {1'h0, _atomics_legal_T_345}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_347 = _atomics_legal_T_346 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_348 = _atomics_legal_T_347; // @[Parameters.scala:137:46] wire _atomics_legal_T_349 = _atomics_legal_T_348 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_350 = _atomics_legal_T_344 \| _atomics_legal_T_349; // @[Parameters.scala:685:42] wire _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_353 = _atomics_legal_T_352; // @[Parameters.scala:686:26] wire atomics_legal_5 = _atomics_legal_T_353 \| _atomics_legal_T_351; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [15:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_5 = atomics_a_mask_sizeOH_5[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_20 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_21 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_22 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 \| _atomics_a_mask_sub_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_23 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 \| _atomics_a_mask_sub_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_40 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_41 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_42 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_43 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_44 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_4_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_5 = atomics_a_mask_sub_sub_2_1_5 \| _atomics_a_mask_sub_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_45 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_5_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_5 = atomics_a_mask_sub_sub_2_1_5 \| _atomics_a_mask_sub_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_46 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_6_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_5 = atomics_a_mask_sub_sub_3_1_5 \| _atomics_a_mask_sub_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_47 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_7_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_5 = atomics_a_mask_sub_sub_3_1_5 \| _atomics_a_mask_sub_acc_T_47; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_80 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_80 = atomics_a_mask_size_5 & atomics_a_mask_eq_80; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_80 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_80; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_81 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_81 = atomics_a_mask_size_5 & atomics_a_mask_eq_81; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_81 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_81; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_82 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_82 = atomics_a_mask_size_5 & atomics_a_mask_eq_82; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_82 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_82; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_83 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_83 = atomics_a_mask_size_5 & atomics_a_mask_eq_83; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_83 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_83; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_84 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_84 = atomics_a_mask_size_5 & atomics_a_mask_eq_84; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_84 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_84; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_85 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_85 = atomics_a_mask_size_5 & atomics_a_mask_eq_85; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_85 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_85; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_86 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_86 = atomics_a_mask_size_5 & atomics_a_mask_eq_86; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_86 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_86; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_87 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_87 = atomics_a_mask_size_5 & atomics_a_mask_eq_87; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_87 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_87; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_88 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_88 = atomics_a_mask_size_5 & atomics_a_mask_eq_88; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_88 = atomics_a_mask_sub_4_1_5 \| _atomics_a_mask_acc_T_88; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_89 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_89 = atomics_a_mask_size_5 & atomics_a_mask_eq_89; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_89 = atomics_a_mask_sub_4_1_5 \| _atomics_a_mask_acc_T_89; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_90 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_90 = atomics_a_mask_size_5 & atomics_a_mask_eq_90; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_90 = atomics_a_mask_sub_5_1_5 \| _atomics_a_mask_acc_T_90; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_91 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_91 = atomics_a_mask_size_5 & atomics_a_mask_eq_91; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_91 = atomics_a_mask_sub_5_1_5 \| _atomics_a_mask_acc_T_91; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_92 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_92 = atomics_a_mask_size_5 & atomics_a_mask_eq_92; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_92 = atomics_a_mask_sub_6_1_5 \| _atomics_a_mask_acc_T_92; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_93 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_93 = atomics_a_mask_size_5 & atomics_a_mask_eq_93; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_93 = atomics_a_mask_sub_6_1_5 \| _atomics_a_mask_acc_T_93; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_94 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_94 = atomics_a_mask_size_5 & atomics_a_mask_eq_94; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_94 = atomics_a_mask_sub_7_1_5 \| _atomics_a_mask_acc_T_94; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_95 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_95 = atomics_a_mask_size_5 & atomics_a_mask_eq_95; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_95 = atomics_a_mask_sub_7_1_5 \| _atomics_a_mask_acc_T_95; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_5 = {atomics_a_mask_acc_81, atomics_a_mask_acc_80}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_5 = {atomics_a_mask_acc_83, atomics_a_mask_acc_82}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_lo_lo_hi_5, atomics_a_mask_lo_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_5 = {atomics_a_mask_acc_85, atomics_a_mask_acc_84}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_5 = {atomics_a_mask_acc_87, atomics_a_mask_acc_86}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_lo_hi_hi_5, atomics_a_mask_lo_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_5 = {atomics_a_mask_acc_89, atomics_a_mask_acc_88}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_5 = {atomics_a_mask_acc_91, atomics_a_mask_acc_90}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_hi_lo_hi_5, atomics_a_mask_hi_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_5 = {atomics_a_mask_acc_93, atomics_a_mask_acc_92}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_5 = {atomics_a_mask_acc_95, atomics_a_mask_acc_94}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_hi_hi_hi_5, atomics_a_mask_hi_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46] wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_364 = {1'h0, _atomics_legal_T_363}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_365 = _atomics_legal_T_364 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_366 = _atomics_legal_T_365; // @[Parameters.scala:137:46] wire _atomics_legal_T_367 = _atomics_legal_T_366 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_369 = {1'h0, _atomics_legal_T_368}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_370 = _atomics_legal_T_369 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_371 = _atomics_legal_T_370; // @[Parameters.scala:137:46] wire _atomics_legal_T_372 = _atomics_legal_T_371 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_374 = {1'h0, _atomics_legal_T_373}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_375 = _atomics_legal_T_374 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_376 = _atomics_legal_T_375; // @[Parameters.scala:137:46] wire _atomics_legal_T_377 = _atomics_legal_T_376 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_379 = {1'h0, _atomics_legal_T_378}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_380 = _atomics_legal_T_379 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_381 = _atomics_legal_T_380; // @[Parameters.scala:137:46] wire _atomics_legal_T_382 = _atomics_legal_T_381 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_383 = _atomics_legal_T_362 \| _atomics_legal_T_367; // @[Parameters.scala:685:42] wire _atomics_legal_T_384 = _atomics_legal_T_383 \| _atomics_legal_T_372; // @[Parameters.scala:685:42] wire _atomics_legal_T_385 = _atomics_legal_T_384 \| _atomics_legal_T_377; // @[Parameters.scala:685:42] wire _atomics_legal_T_386 = _atomics_legal_T_385 \| _atomics_legal_T_382; // @[Parameters.scala:685:42] wire _atomics_legal_T_387 = _atomics_legal_T_386; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_411 = _atomics_legal_T_387; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_390 = {1'h0, _atomics_legal_T_389}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_391 = _atomics_legal_T_390 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_392 = _atomics_legal_T_391; // @[Parameters.scala:137:46] wire _atomics_legal_T_393 = _atomics_legal_T_392 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_400 = {1'h0, _atomics_legal_T_399}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_401 = _atomics_legal_T_400 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_402 = _atomics_legal_T_401; // @[Parameters.scala:137:46] wire _atomics_legal_T_403 = _atomics_legal_T_402 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_405 = {1'h0, _atomics_legal_T_404}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_406 = _atomics_legal_T_405 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_407 = _atomics_legal_T_406; // @[Parameters.scala:137:46] wire _atomics_legal_T_408 = _atomics_legal_T_407 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_409 = _atomics_legal_T_403 \| _atomics_legal_T_408; // @[Parameters.scala:685:42] wire _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_412 = _atomics_legal_T_411; // @[Parameters.scala:686:26] wire atomics_legal_6 = _atomics_legal_T_412 \| _atomics_legal_T_410; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [15:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_6 = atomics_a_mask_sizeOH_6[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_24 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_25 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_26 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 \| _atomics_a_mask_sub_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_27 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 \| _atomics_a_mask_sub_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_48 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_49 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_50 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_51 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_52 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_4_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_6 = atomics_a_mask_sub_sub_2_1_6 \| _atomics_a_mask_sub_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_53 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_5_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_6 = atomics_a_mask_sub_sub_2_1_6 \| _atomics_a_mask_sub_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_54 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_6_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_6 = atomics_a_mask_sub_sub_3_1_6 \| _atomics_a_mask_sub_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_55 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_7_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_6 = atomics_a_mask_sub_sub_3_1_6 \| _atomics_a_mask_sub_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_96 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_96 = atomics_a_mask_size_6 & atomics_a_mask_eq_96; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_96 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_96; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_97 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_97 = atomics_a_mask_size_6 & atomics_a_mask_eq_97; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_97 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_97; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_98 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_98 = atomics_a_mask_size_6 & atomics_a_mask_eq_98; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_98 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_98; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_99 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_99 = atomics_a_mask_size_6 & atomics_a_mask_eq_99; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_99 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_99; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_100 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_100 = atomics_a_mask_size_6 & atomics_a_mask_eq_100; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_100 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_100; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_101 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_101 = atomics_a_mask_size_6 & atomics_a_mask_eq_101; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_101 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_101; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_102 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_102 = atomics_a_mask_size_6 & atomics_a_mask_eq_102; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_102 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_102; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_103 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_103 = atomics_a_mask_size_6 & atomics_a_mask_eq_103; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_103 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_103; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_104 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_104 = atomics_a_mask_size_6 & atomics_a_mask_eq_104; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_104 = atomics_a_mask_sub_4_1_6 \| _atomics_a_mask_acc_T_104; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_105 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_105 = atomics_a_mask_size_6 & atomics_a_mask_eq_105; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_105 = atomics_a_mask_sub_4_1_6 \| _atomics_a_mask_acc_T_105; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_106 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_106 = atomics_a_mask_size_6 & atomics_a_mask_eq_106; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_106 = atomics_a_mask_sub_5_1_6 \| _atomics_a_mask_acc_T_106; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_107 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_107 = atomics_a_mask_size_6 & atomics_a_mask_eq_107; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_107 = atomics_a_mask_sub_5_1_6 \| _atomics_a_mask_acc_T_107; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_108 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_108 = atomics_a_mask_size_6 & atomics_a_mask_eq_108; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_108 = atomics_a_mask_sub_6_1_6 \| _atomics_a_mask_acc_T_108; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_109 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_109 = atomics_a_mask_size_6 & atomics_a_mask_eq_109; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_109 = atomics_a_mask_sub_6_1_6 \| _atomics_a_mask_acc_T_109; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_110 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_110 = atomics_a_mask_size_6 & atomics_a_mask_eq_110; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_110 = atomics_a_mask_sub_7_1_6 \| _atomics_a_mask_acc_T_110; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_111 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_111 = atomics_a_mask_size_6 & atomics_a_mask_eq_111; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_111 = atomics_a_mask_sub_7_1_6 \| _atomics_a_mask_acc_T_111; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_6 = {atomics_a_mask_acc_97, atomics_a_mask_acc_96}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_6 = {atomics_a_mask_acc_99, atomics_a_mask_acc_98}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_lo_lo_hi_6, atomics_a_mask_lo_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_6 = {atomics_a_mask_acc_101, atomics_a_mask_acc_100}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_6 = {atomics_a_mask_acc_103, atomics_a_mask_acc_102}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_lo_hi_hi_6, atomics_a_mask_lo_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_6 = {atomics_a_mask_acc_105, atomics_a_mask_acc_104}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_6 = {atomics_a_mask_acc_107, atomics_a_mask_acc_106}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_hi_lo_hi_6, atomics_a_mask_hi_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_6 = {atomics_a_mask_acc_109, atomics_a_mask_acc_108}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_6 = {atomics_a_mask_acc_111, atomics_a_mask_acc_110}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_hi_hi_hi_6, atomics_a_mask_hi_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_418 = {1'h0, _atomics_legal_T_417}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_419 = _atomics_legal_T_418 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_420 = _atomics_legal_T_419; // @[Parameters.scala:137:46] wire _atomics_legal_T_421 = _atomics_legal_T_420 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_423 = {1'h0, _atomics_legal_T_422}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_424 = _atomics_legal_T_423 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_425 = _atomics_legal_T_424; // @[Parameters.scala:137:46] wire _atomics_legal_T_426 = _atomics_legal_T_425 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_428 = {1'h0, _atomics_legal_T_427}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_429 = _atomics_legal_T_428 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_430 = _atomics_legal_T_429; // @[Parameters.scala:137:46] wire _atomics_legal_T_431 = _atomics_legal_T_430 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_433 = {1'h0, _atomics_legal_T_432}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_434 = _atomics_legal_T_433 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_435 = _atomics_legal_T_434; // @[Parameters.scala:137:46] wire _atomics_legal_T_436 = _atomics_legal_T_435 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_438 = {1'h0, _atomics_legal_T_437}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_440 = _atomics_legal_T_439; // @[Parameters.scala:137:46] wire _atomics_legal_T_441 = _atomics_legal_T_440 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_442 = _atomics_legal_T_421 \| _atomics_legal_T_426; // @[Parameters.scala:685:42] wire _atomics_legal_T_443 = _atomics_legal_T_442 \| _atomics_legal_T_431; // @[Parameters.scala:685:42] wire _atomics_legal_T_444 = _atomics_legal_T_443 \| _atomics_legal_T_436; // @[Parameters.scala:685:42] wire _atomics_legal_T_445 = _atomics_legal_T_444 \| _atomics_legal_T_441; // @[Parameters.scala:685:42] wire _atomics_legal_T_446 = _atomics_legal_T_445; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_470 = _atomics_legal_T_446; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_449 = {1'h0, _atomics_legal_T_448}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_450 = _atomics_legal_T_449 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_451 = _atomics_legal_T_450; // @[Parameters.scala:137:46] wire _atomics_legal_T_452 = _atomics_legal_T_451 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_459 = {1'h0, _atomics_legal_T_458}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_460 = _atomics_legal_T_459 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_461 = _atomics_legal_T_460; // @[Parameters.scala:137:46] wire _atomics_legal_T_462 = _atomics_legal_T_461 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_464 = {1'h0, _atomics_legal_T_463}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_465 = _atomics_legal_T_464 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_466 = _atomics_legal_T_465; // @[Parameters.scala:137:46] wire _atomics_legal_T_467 = _atomics_legal_T_466 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_468 = _atomics_legal_T_462 \| _atomics_legal_T_467; // @[Parameters.scala:685:42] wire _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_471 = _atomics_legal_T_470; // @[Parameters.scala:686:26] wire atomics_legal_7 = _atomics_legal_T_471 \| _atomics_legal_T_469; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [15:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_7 = atomics_a_mask_sizeOH_7[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_28 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_29 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_30 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 \| _atomics_a_mask_sub_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_31 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 \| _atomics_a_mask_sub_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_56 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_57 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_58 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_59 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_60 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_4_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_7 = atomics_a_mask_sub_sub_2_1_7 \| _atomics_a_mask_sub_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_61 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_5_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_7 = atomics_a_mask_sub_sub_2_1_7 \| _atomics_a_mask_sub_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_62 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_6_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_7 = atomics_a_mask_sub_sub_3_1_7 \| _atomics_a_mask_sub_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_63 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_7_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_7 = atomics_a_mask_sub_sub_3_1_7 \| _atomics_a_mask_sub_acc_T_63; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_112 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_112 = atomics_a_mask_size_7 & atomics_a_mask_eq_112; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_112 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_112; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_113 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_113 = atomics_a_mask_size_7 & atomics_a_mask_eq_113; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_113 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_113; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_114 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_114 = atomics_a_mask_size_7 & atomics_a_mask_eq_114; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_114 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_114; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_115 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_115 = atomics_a_mask_size_7 & atomics_a_mask_eq_115; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_115 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_115; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_116 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_116 = atomics_a_mask_size_7 & atomics_a_mask_eq_116; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_116 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_116; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_117 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_117 = atomics_a_mask_size_7 & atomics_a_mask_eq_117; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_117 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_117; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_118 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_118 = atomics_a_mask_size_7 & atomics_a_mask_eq_118; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_118 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_118; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_119 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_119 = atomics_a_mask_size_7 & atomics_a_mask_eq_119; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_119 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_119; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_120 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_120 = atomics_a_mask_size_7 & atomics_a_mask_eq_120; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_120 = atomics_a_mask_sub_4_1_7 \| _atomics_a_mask_acc_T_120; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_121 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_121 = atomics_a_mask_size_7 & atomics_a_mask_eq_121; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_121 = atomics_a_mask_sub_4_1_7 \| _atomics_a_mask_acc_T_121; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_122 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_122 = atomics_a_mask_size_7 & atomics_a_mask_eq_122; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_122 = atomics_a_mask_sub_5_1_7 \| _atomics_a_mask_acc_T_122; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_123 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_123 = atomics_a_mask_size_7 & atomics_a_mask_eq_123; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_123 = atomics_a_mask_sub_5_1_7 \| _atomics_a_mask_acc_T_123; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_124 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_124 = atomics_a_mask_size_7 & atomics_a_mask_eq_124; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_124 = atomics_a_mask_sub_6_1_7 \| _atomics_a_mask_acc_T_124; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_125 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_125 = atomics_a_mask_size_7 & atomics_a_mask_eq_125; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_125 = atomics_a_mask_sub_6_1_7 \| _atomics_a_mask_acc_T_125; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_126 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_126 = atomics_a_mask_size_7 & atomics_a_mask_eq_126; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_126 = atomics_a_mask_sub_7_1_7 \| _atomics_a_mask_acc_T_126; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_127 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_127 = atomics_a_mask_size_7 & atomics_a_mask_eq_127; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_127 = atomics_a_mask_sub_7_1_7 \| _atomics_a_mask_acc_T_127; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_7 = {atomics_a_mask_acc_113, atomics_a_mask_acc_112}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_7 = {atomics_a_mask_acc_115, atomics_a_mask_acc_114}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_lo_lo_hi_7, atomics_a_mask_lo_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_7 = {atomics_a_mask_acc_117, atomics_a_mask_acc_116}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_7 = {atomics_a_mask_acc_119, atomics_a_mask_acc_118}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_lo_hi_hi_7, atomics_a_mask_lo_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_7 = {atomics_a_mask_acc_121, atomics_a_mask_acc_120}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_7 = {atomics_a_mask_acc_123, atomics_a_mask_acc_122}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_hi_lo_hi_7, atomics_a_mask_hi_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_7 = {atomics_a_mask_acc_125, atomics_a_mask_acc_124}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_7 = {atomics_a_mask_acc_127, atomics_a_mask_acc_126}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_hi_hi_hi_7, atomics_a_mask_hi_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_477 = {1'h0, _atomics_legal_T_476}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_478 = _atomics_legal_T_477 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_479 = _atomics_legal_T_478; // @[Parameters.scala:137:46] wire _atomics_legal_T_480 = _atomics_legal_T_479 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_482 = {1'h0, _atomics_legal_T_481}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_483 = _atomics_legal_T_482 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_484 = _atomics_legal_T_483; // @[Parameters.scala:137:46] wire _atomics_legal_T_485 = _atomics_legal_T_484 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_487 = {1'h0, _atomics_legal_T_486}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_488 = _atomics_legal_T_487 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_489 = _atomics_legal_T_488; // @[Parameters.scala:137:46] wire _atomics_legal_T_490 = _atomics_legal_T_489 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_492 = {1'h0, _atomics_legal_T_491}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_493 = _atomics_legal_T_492 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_494 = _atomics_legal_T_493; // @[Parameters.scala:137:46] wire _atomics_legal_T_495 = _atomics_legal_T_494 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_497 = {1'h0, _atomics_legal_T_496}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_498 = _atomics_legal_T_497 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_499 = _atomics_legal_T_498; // @[Parameters.scala:137:46] wire _atomics_legal_T_500 = _atomics_legal_T_499 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_501 = _atomics_legal_T_480 \| _atomics_legal_T_485; // @[Parameters.scala:685:42] wire _atomics_legal_T_502 = _atomics_legal_T_501 \| _atomics_legal_T_490; // @[Parameters.scala:685:42] wire _atomics_legal_T_503 = _atomics_legal_T_502 \| _atomics_legal_T_495; // @[Parameters.scala:685:42] wire _atomics_legal_T_504 = _atomics_legal_T_503 \| _atomics_legal_T_500; // @[Parameters.scala:685:42] wire _atomics_legal_T_505 = _atomics_legal_T_504; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_529 = _atomics_legal_T_505; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_508 = {1'h0, _atomics_legal_T_507}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_509 = _atomics_legal_T_508 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_510 = _atomics_legal_T_509; // @[Parameters.scala:137:46] wire _atomics_legal_T_511 = _atomics_legal_T_510 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_518 = {1'h0, _atomics_legal_T_517}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_519 = _atomics_legal_T_518 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_520 = _atomics_legal_T_519; // @[Parameters.scala:137:46] wire _atomics_legal_T_521 = _atomics_legal_T_520 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_523 = {1'h0, _atomics_legal_T_522}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_524 = _atomics_legal_T_523 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_525 = _atomics_legal_T_524; // @[Parameters.scala:137:46] wire _atomics_legal_T_526 = _atomics_legal_T_525 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_527 = _atomics_legal_T_521 \| _atomics_legal_T_526; // @[Parameters.scala:685:42] wire _atomics_legal_T_528 = _atomics_legal_T_527; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_530 = _atomics_legal_T_529; // @[Parameters.scala:686:26] wire atomics_legal_8 = _atomics_legal_T_530 \| _atomics_legal_T_528; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [15:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_8 = atomics_a_mask_sizeOH_8[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_32 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_33 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_34 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 \| _atomics_a_mask_sub_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_35 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 \| _atomics_a_mask_sub_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_64 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_65 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_66 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_67 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_68 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_4_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_8 = atomics_a_mask_sub_sub_2_1_8 \| _atomics_a_mask_sub_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_69 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_5_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_8 = atomics_a_mask_sub_sub_2_1_8 \| _atomics_a_mask_sub_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_70 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_6_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_8 = atomics_a_mask_sub_sub_3_1_8 \| _atomics_a_mask_sub_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_71 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_7_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_8 = atomics_a_mask_sub_sub_3_1_8 \| _atomics_a_mask_sub_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_128 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_128 = atomics_a_mask_size_8 & atomics_a_mask_eq_128; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_128 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_128; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_129 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_129 = atomics_a_mask_size_8 & atomics_a_mask_eq_129; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_129 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_129; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_130 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_130 = atomics_a_mask_size_8 & atomics_a_mask_eq_130; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_130 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_130; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_131 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_131 = atomics_a_mask_size_8 & atomics_a_mask_eq_131; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_131 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_131; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_132 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_132 = atomics_a_mask_size_8 & atomics_a_mask_eq_132; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_132 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_132; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_133 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_133 = atomics_a_mask_size_8 & atomics_a_mask_eq_133; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_133 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_133; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_134 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_134 = atomics_a_mask_size_8 & atomics_a_mask_eq_134; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_134 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_134; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_135 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_135 = atomics_a_mask_size_8 & atomics_a_mask_eq_135; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_135 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_135; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_136 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_136 = atomics_a_mask_size_8 & atomics_a_mask_eq_136; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_136 = atomics_a_mask_sub_4_1_8 \| _atomics_a_mask_acc_T_136; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_137 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_137 = atomics_a_mask_size_8 & atomics_a_mask_eq_137; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_137 = atomics_a_mask_sub_4_1_8 \| _atomics_a_mask_acc_T_137; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_138 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_138 = atomics_a_mask_size_8 & atomics_a_mask_eq_138; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_138 = atomics_a_mask_sub_5_1_8 \| _atomics_a_mask_acc_T_138; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_139 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_139 = atomics_a_mask_size_8 & atomics_a_mask_eq_139; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_139 = atomics_a_mask_sub_5_1_8 \| _atomics_a_mask_acc_T_139; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_140 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_140 = atomics_a_mask_size_8 & atomics_a_mask_eq_140; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_140 = atomics_a_mask_sub_6_1_8 \| _atomics_a_mask_acc_T_140; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_141 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_141 = atomics_a_mask_size_8 & atomics_a_mask_eq_141; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_141 = atomics_a_mask_sub_6_1_8 \| _atomics_a_mask_acc_T_141; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_142 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_142 = atomics_a_mask_size_8 & atomics_a_mask_eq_142; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_142 = atomics_a_mask_sub_7_1_8 \| _atomics_a_mask_acc_T_142; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_143 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_143 = atomics_a_mask_size_8 & atomics_a_mask_eq_143; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_143 = atomics_a_mask_sub_7_1_8 \| _atomics_a_mask_acc_T_143; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_8 = {atomics_a_mask_acc_129, atomics_a_mask_acc_128}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_8 = {atomics_a_mask_acc_131, atomics_a_mask_acc_130}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_lo_lo_hi_8, atomics_a_mask_lo_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_8 = {atomics_a_mask_acc_133, atomics_a_mask_acc_132}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_8 = {atomics_a_mask_acc_135, atomics_a_mask_acc_134}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_lo_hi_hi_8, atomics_a_mask_lo_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_8 = {atomics_a_mask_acc_137, atomics_a_mask_acc_136}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_8 = {atomics_a_mask_acc_139, atomics_a_mask_acc_138}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_hi_lo_hi_8, atomics_a_mask_hi_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_8 = {atomics_a_mask_acc_141, atomics_a_mask_acc_140}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_8 = {atomics_a_mask_acc_143, atomics_a_mask_acc_142}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_hi_hi_hi_8, atomics_a_mask_hi_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire _T_17 = req_uop_mem_cmd == 5'h4; // @[mshrs.scala:421:16, :439:75] wire _atomics_T; // @[mshrs.scala:439:75] assign _atomics_T = _T_17; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T; // @[package.scala:16:47] assign _io_mem_access_bits_T = _T_17; // @[package.scala:16:47] wire _io_mem_access_bits_T_24; // @[package.scala:16:47] assign _io_mem_access_bits_T_24 = _T_17; // @[package.scala:16:47] wire _send_resp_T_7; // @[package.scala:16:47] assign _send_resp_T_7 = _T_17; // @[package.scala:16:47] wire [2:0] _GEN_10 = _atomics_T ? 3'h3 : 3'h0; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_opcode; // @[mshrs.scala:439:75] assign _atomics_T_1_opcode = _GEN_10; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_param; // @[mshrs.scala:439:75] assign _atomics_T_1_param = _GEN_10; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire [2:0] _atomics_T_1_source = _atomics_T ? 3'h5 : 3'h0; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [15:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 16'h0; // @[Edges.scala:534:17] wire [127:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 128'h0; // @[Edges.scala:534:17] wire _T_18 = req_uop_mem_cmd == 5'h9; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_2; // @[mshrs.scala:439:75] assign _atomics_T_2 = _T_18; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_1; // @[package.scala:16:47] assign _io_mem_access_bits_T_1 = _T_18; // @[package.scala:16:47] wire _io_mem_access_bits_T_25; // @[package.scala:16:47] assign _io_mem_access_bits_T_25 = _T_18; // @[package.scala:16:47] wire _send_resp_T_8; // @[package.scala:16:47] assign _send_resp_T_8 = _T_18; // @[package.scala:16:47] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire [2:0] _atomics_T_3_source = _atomics_T_2 ? 3'h5 : _atomics_T_1_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire _T_19 = req_uop_mem_cmd == 5'hA; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_4; // @[mshrs.scala:439:75] assign _atomics_T_4 = _T_19; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_2; // @[package.scala:16:47] assign _io_mem_access_bits_T_2 = _T_19; // @[package.scala:16:47] wire _io_mem_access_bits_T_26; // @[package.scala:16:47] assign _io_mem_access_bits_T_26 = _T_19; // @[package.scala:16:47] wire _send_resp_T_9; // @[package.scala:16:47] assign _send_resp_T_9 = _T_19; // @[package.scala:16:47] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire [2:0] _atomics_T_5_source = _atomics_T_4 ? 3'h5 : _atomics_T_3_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire _T_20 = req_uop_mem_cmd == 5'hB; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_6; // @[mshrs.scala:439:75] assign _atomics_T_6 = _T_20; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_3; // @[package.scala:16:47] assign _io_mem_access_bits_T_3 = _T_20; // @[package.scala:16:47] wire _io_mem_access_bits_T_27; // @[package.scala:16:47] assign _io_mem_access_bits_T_27 = _T_20; // @[package.scala:16:47] wire _send_resp_T_10; // @[package.scala:16:47] assign _send_resp_T_10 = _T_20; // @[package.scala:16:47] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire [2:0] _atomics_T_7_source = _atomics_T_6 ? 3'h5 : _atomics_T_5_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire _T_24 = req_uop_mem_cmd == 5'h8; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_8; // @[mshrs.scala:439:75] assign _atomics_T_8 = _T_24; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_7; // @[package.scala:16:47] assign _io_mem_access_bits_T_7 = _T_24; // @[package.scala:16:47] wire _io_mem_access_bits_T_31; // @[package.scala:16:47] assign _io_mem_access_bits_T_31 = _T_24; // @[package.scala:16:47] wire _send_resp_T_14; // @[package.scala:16:47] assign _send_resp_T_14 = _T_24; // @[package.scala:16:47] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_9_source = _atomics_T_8 ? 3'h5 : _atomics_T_7_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire _T_25 = req_uop_mem_cmd == 5'hC; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_10; // @[mshrs.scala:439:75] assign _atomics_T_10 = _T_25; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_8; // @[package.scala:16:47] assign _io_mem_access_bits_T_8 = _T_25; // @[package.scala:16:47] wire _io_mem_access_bits_T_32; // @[package.scala:16:47] assign _io_mem_access_bits_T_32 = _T_25; // @[package.scala:16:47] wire _send_resp_T_15; // @[package.scala:16:47] assign _send_resp_T_15 = _T_25; // @[package.scala:16:47] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_11_source = _atomics_T_10 ? 3'h5 : _atomics_T_9_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire _T_26 = req_uop_mem_cmd == 5'hD; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_12; // @[mshrs.scala:439:75] assign _atomics_T_12 = _T_26; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_9; // @[package.scala:16:47] assign _io_mem_access_bits_T_9 = _T_26; // @[package.scala:16:47] wire _io_mem_access_bits_T_33; // @[package.scala:16:47] assign _io_mem_access_bits_T_33 = _T_26; // @[package.scala:16:47] wire _send_resp_T_16; // @[package.scala:16:47] assign _send_resp_T_16 = _T_26; // @[package.scala:16:47] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_13_source = _atomics_T_12 ? 3'h5 : _atomics_T_11_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire _T_27 = req_uop_mem_cmd == 5'hE; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_14; // @[mshrs.scala:439:75] assign _atomics_T_14 = _T_27; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_10; // @[package.scala:16:47] assign _io_mem_access_bits_T_10 = _T_27; // @[package.scala:16:47] wire _io_mem_access_bits_T_34; // @[package.scala:16:47] assign _io_mem_access_bits_T_34 = _T_27; // @[package.scala:16:47] wire _send_resp_T_17; // @[package.scala:16:47] assign _send_resp_T_17 = _T_27; // @[package.scala:16:47] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_15_source = _atomics_T_14 ? 3'h5 : _atomics_T_13_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire _T_28 = req_uop_mem_cmd == 5'hF; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_16; // @[mshrs.scala:439:75] assign _atomics_T_16 = _T_28; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_11; // @[package.scala:16:47] assign _io_mem_access_bits_T_11 = _T_28; // @[package.scala:16:47] wire _io_mem_access_bits_T_35; // @[package.scala:16:47] assign _io_mem_access_bits_T_35 = _T_28; // @[package.scala:16:47] wire _send_resp_T_18; // @[package.scala:16:47] assign _send_resp_T_18 = _T_28; // @[package.scala:16:47] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[mshrs.scala:439:75] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[mshrs.scala:439:75] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire [2:0] atomics_source = _atomics_T_16 ? 3'h5 : _atomics_T_15_source; // @[mshrs.scala:439:75] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [15:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [127:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17]
Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth2 - 1)) }) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) \|\| (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf \|\| io.b.isInf val notNaN_isZeroOut = io.a.isZero \|\| io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth2 - 1, 0) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ io.invalidExc := isSigNaNRawFloat(io.a) \|\| isSigNaNRawFloat(io.b) \|\| notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN \|\| io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulRawFN_30( // @[MulRecFN.scala:75:7] input io_a_isNaN, // @[MulRecFN.scala:77:16] input io_a_isInf, // @[MulRecFN.scala:77:16] input io_a_isZero, // @[MulRecFN.scala:77:16] input io_a_sign, // @[MulRecFN.scala:77:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_a_sig, // @[MulRecFN.scala:77:16] input io_b_isNaN, // @[MulRecFN.scala:77:16] input io_b_isInf, // @[MulRecFN.scala:77:16] input io_b_isZero, // @[MulRecFN.scala:77:16] input io_b_sign, // @[MulRecFN.scala:77:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_b_sig, // @[MulRecFN.scala:77:16] output io_invalidExc, // @[MulRecFN.scala:77:16] output io_rawOut_isNaN, // @[MulRecFN.scala:77:16] output io_rawOut_isInf, // @[MulRecFN.scala:77:16] output io_rawOut_isZero, // @[MulRecFN.scala:77:16] output io_rawOut_sign, // @[MulRecFN.scala:77:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16] output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16] ); wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28] wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7] wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7] wire io_invalidExc_0; // @[MulRecFN.scala:75:7] wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15] wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37] wire _io_rawOut_sig_T_2 = \|_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}] assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10] MulFullRawFN_30 mulFullRaw ( // @[MulRecFN.scala:84:28] .io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7] .io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7] .io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7] .io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7] .io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7] .io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7] .io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7] .io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7] .io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7] .io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7] .io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7] .io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7] .io_invalidExc (io_invalidExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (_mulFullRaw_io_rawOut_sig) ); // @[MulRecFN.scala:84:28] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_50( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [13:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [13:0] source_1; // @[Monitor.scala:541:22] reg [8207:0] inflight; // @[Monitor.scala:614:27] reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [8207:0] inflight_1; // @[Monitor.scala:726:35] reg [32831:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_194( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie6_is32_oe8_os24( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [7:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [32:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire roundingMode_near_even = io_roundingMode == 3'h0; // @[RoundAnyRawFNToRecFN.scala:90:53] wire [1:0] _GEN = {io_in_sig[7], \|(io_in_sig[6:0])}; // @[RoundAnyRawFNToRecFN.scala:116:66, :117:{26,60}, :164:56, :165:62, :166:36] wire [25:0] roundedSig = (roundingMode_near_even \| io_roundingMode == 3'h4) & io_in_sig[7] \| (io_roundingMode == 3'h2 & io_in_sign \| io_roundingMode == 3'h3 & ~io_in_sign) & (\|_GEN) ? {1'h0, io_in_sig[32:8]} + 26'h1 & {25'h1FFFFFF, ~(roundingMode_near_even & io_in_sig[7] & ~(\|(io_in_sig[6:0])))} : {1'h0, io_in_sig[32:9], io_in_sig[8] \| io_roundingMode == 3'h6 & (\|_GEN)}; // @[RoundAnyRawFNToRecFN.scala:90:53, :92:53, :93:53, :94:53, :95:53, :98:{27,42,63,66}, :106:31, :116:66, :117:{26,60}, :164:{40,56}, :165:62, :166:36, :169:{38,67}, :170:31, :171:29, :173:16, :174:{49,57}, :175:{21,25,49,64}, :176:30, :180:47, :181:42] assign io_out = {io_in_sign, {io_in_sExp[7], io_in_sExp} + {7'h0, roundedSig[25:24]} + 9'hC0 & ~(io_in_isZero ? 9'h1C0 : 9'h0), io_in_isZero ? 23'h0 : roundedSig[22:0]}; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25, :173:16, :185:{40,54}, :191:27, :252:24, :253:{14,18}, :280:12, :281:16, :286:33] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_239( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth2 - 1)) }) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) \|\| (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf \|\| io.b.isInf val notNaN_isZeroOut = io.a.isZero \|\| io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth2 - 1, 0) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ io.invalidExc := isSigNaNRawFloat(io.a) \|\| isSigNaNRawFloat(io.b) \|\| notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN \|\| io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulRawFN_8( // @[MulRecFN.scala:75:7] input io_a_isNaN, // @[MulRecFN.scala:77:16] input io_a_isInf, // @[MulRecFN.scala:77:16] input io_a_isZero, // @[MulRecFN.scala:77:16] input io_a_sign, // @[MulRecFN.scala:77:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_a_sig, // @[MulRecFN.scala:77:16] input io_b_isNaN, // @[MulRecFN.scala:77:16] input io_b_isInf, // @[MulRecFN.scala:77:16] input io_b_isZero, // @[MulRecFN.scala:77:16] input io_b_sign, // @[MulRecFN.scala:77:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_b_sig, // @[MulRecFN.scala:77:16] output io_invalidExc, // @[MulRecFN.scala:77:16] output io_rawOut_isNaN, // @[MulRecFN.scala:77:16] output io_rawOut_isInf, // @[MulRecFN.scala:77:16] output io_rawOut_isZero, // @[MulRecFN.scala:77:16] output io_rawOut_sign, // @[MulRecFN.scala:77:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16] output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16] ); wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28] wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7] wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7] wire io_invalidExc_0; // @[MulRecFN.scala:75:7] wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15] wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37] wire _io_rawOut_sig_T_2 = \|_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}] assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10] MulFullRawFN_8 mulFullRaw ( // @[MulRecFN.scala:84:28] .io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7] .io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7] .io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7] .io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7] .io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7] .io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7] .io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7] .io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7] .io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7] .io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7] .io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7] .io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7] .io_invalidExc (io_invalidExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (_mulFullRaw_io_rawOut_sig) ); // @[MulRecFN.scala:84:28] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File RVC.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class ExpandedInstruction extends Bundle { val bits = UInt(32.W) val rd = UInt(5.W) val rs1 = UInt(5.W) val rs2 = UInt(5.W) val rs3 = UInt(5.W) } class RVCDecoder(x: UInt, xLen: Int, fLen: Int, useAddiForMv: Boolean = false) { def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = { val res = Wire(new ExpandedInstruction) res.bits := bits res.rd := rd res.rs1 := rs1 res.rs2 := rs2 res.rs3 := rs3 res } def rs1p = Cat(1.U(2.W), x(9,7)) def rs2p = Cat(1.U(2.W), x(4,2)) def rs2 = x(6,2) def rd = x(11,7) def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W)) def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W)) def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W)) def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W)) def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W)) def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W)) def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W)) def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W)) def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W)) def addiImm = Cat(Fill(7, x(12)), x(6,2)) def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W)) def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W)) def shamt = Cat(x(12), x(6,2)) def x0 = 0.U(5.W) def ra = 1.U(5.W) def sp = 2.U(5.W) def q0 = { def addi4spn = { val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W)) inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p) } def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) def flw = { if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) else ld } def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p) def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) def fsw = { if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) else sd } Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw) } def q1 = { def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p) def addiw = { val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W)) inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p) } def jal = { if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p) else addiw } def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p) def addi16sp = { val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W)) inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p) } def lui = { val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W)) val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p) Mux(rd === x0 \|\| rd === sp, addi16sp, me) } def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p) def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0) def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0) def arith = { def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)) def srai = srli \| (1 << 30).U def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)) def rtype = { val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5))) val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U) val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W)) Cat(rs2p, rs1p, funct, rs1p, opc) \| sub } inst(Seq(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p) } Seq(addi, jal, li, lui, arith, j, beqz, bnez) } def q2 = { val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W)) def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2) def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2) def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2) def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2) def flwsp = { if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2) else ldsp } def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2) def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2) def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2) def fswsp = { if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2) else sdsp } def jalr = { val mv = { if (useAddiForMv) inst(Cat(rs2, 0.U(3.W), rd, 0x13.U(7.W)), rd, rs2, x0) else inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2) } val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2) val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W)) val reserved = Cat(jr >> 7, 0x1F.U(7.W)) val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2) val jr_mv = Mux(rs2.orR, mv, jr_reserved) val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W)) val ebreak = Cat(jr >> 7, 0x73.U(7.W)) \| (1 << 20).U val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2) val jalr_add = Mux(rs2.orR, add, jalr_ebreak) Mux(x(12), jalr_add, jr_mv) } Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp) } def q3 = Seq.fill(8)(passthrough) def passthrough = inst(x) def decode = { val s = q0 ++ q1 ++ q2 ++ q3 s(Cat(x(1,0), x(15,13))) } def q0_ill = { def allz = !(x(12, 2).orR) def fld = if (fLen >= 64) false.B else true.B def flw32 = if (xLen == 64 \|\| fLen >= 32) false.B else true.B def fsd = if (fLen >= 64) false.B else true.B def fsw32 = if (xLen == 64 \|\| fLen >= 32) false.B else true.B Seq(allz, fld, false.B, flw32, true.B, fsd, false.B, fsw32) } def q1_ill = { def rd0 = if (xLen == 32) false.B else rd === 0.U def immz = !(x(12) \| x(6, 2).orR) def arith_res = x(12, 10).andR && (if (xLen == 32) true.B else x(6) === 1.U) Seq(false.B, rd0, false.B, immz, arith_res, false.B, false.B, false.B) } def q2_ill = { def fldsp = if (fLen >= 64) false.B else true.B def rd0 = rd === 0.U def flwsp = if (xLen == 64) rd0 else if (fLen >= 32) false.B else true.B def jr_res = !(x(12 ,2).orR) def fsdsp = if (fLen >= 64) false.B else true.B def fswsp32 = if (xLen == 64) false.B else if (fLen >= 32) false.B else true.B Seq(false.B, fldsp, rd0, flwsp, jr_res, fsdsp, false.B, fswsp32) } def q3_ill = Seq.fill(8)(false.B) def ill = { val s = q0_ill ++ q1_ill ++ q2_ill ++ q3_ill s(Cat(x(1,0), x(15,13))) } } class RVCExpander(useAddiForMv: Boolean = false)(implicit val p: Parameters) extends Module with HasCoreParameters { val io = IO(new Bundle { val in = Input(UInt(32.W)) val out = Output(new ExpandedInstruction) val rvc = Output(Bool()) val ill = Output(Bool()) }) if (usingCompressed) { io.rvc := io.in(1,0) =/= 3.U val decoder = new RVCDecoder(io.in, xLen, fLen, useAddiForMv) io.out := decoder.decode io.ill := decoder.ill } else { io.rvc := false.B io.out := new RVCDecoder(io.in, xLen, fLen, useAddiForMv).passthrough io.ill := false.B // only used for RVC } }	module RVCExpander_1( // @[RVC.scala:190:7] input clock, // @[RVC.scala:190:7] input reset, // @[RVC.scala:190:7] input [31:0] io_in, // @[RVC.scala:191:14] output [31:0] io_out_bits, // @[RVC.scala:191:14] output io_rvc // @[RVC.scala:191:14] ); wire [31:0] io_in_0 = io_in; // @[RVC.scala:190:7] wire [11:0] io_out_s_jr_lo = 12'h67; // @[RVC.scala:135:19] wire [4:0] io_out_s_10_rs1 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_13_rd = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_14_rs2 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_15_rd = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_15_rs2 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_mv_rs1 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_jr_reserved_rd = 5'h0; // @[RVC.scala:21:19] wire [11:0] io_out_s_jalr_lo = 12'hE7; // @[RVC.scala:139:21] wire [4:0] io_out_s_jalr_ebreak_rd = 5'h1; // @[package.scala:39:86] wire [4:0] io_out_s_0_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_17_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_18_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_19_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_21_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_22_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_23_rs1 = 5'h2; // @[package.scala:39:86] wire [31:0] io_out_s_24_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_25_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_26_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_27_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_28_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_29_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_30_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_31_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] _io_out_T_64_bits; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rd; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs1; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs2; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs3; // @[package.scala:39:76] wire _io_rvc_T_1; // @[RVC.scala:199:26] wire _io_ill_T_64; // @[package.scala:39:76] wire [31:0] io_out_bits_0; // @[RVC.scala:190:7] wire [4:0] io_out_rd; // @[RVC.scala:190:7] wire [4:0] io_out_rs1; // @[RVC.scala:190:7] wire [4:0] io_out_rs2; // @[RVC.scala:190:7] wire [4:0] io_out_rs3; // @[RVC.scala:190:7] wire io_rvc_0; // @[RVC.scala:190:7] wire io_ill; // @[RVC.scala:190:7] wire [1:0] _io_rvc_T = io_in_0[1:0]; // @[RVC.scala:190:7, :199:20] wire [1:0] _io_out_T = io_in_0[1:0]; // @[RVC.scala:154:12, :190:7, :199:20] wire [1:0] _io_ill_T = io_in_0[1:0]; // @[RVC.scala:186:12, :190:7, :199:20] assign _io_rvc_T_1 = _io_rvc_T != 2'h3; // @[RVC.scala:199:{20,26}] assign io_rvc_0 = _io_rvc_T_1; // @[RVC.scala:190:7, :199:26] wire [7:0] _io_out_s_opc_T = io_in_0[12:5]; // @[RVC.scala:53:22, :190:7] wire _io_out_s_opc_T_1 = \|_io_out_s_opc_T; // @[RVC.scala:53:{22,29}] wire [6:0] io_out_s_opc = _io_out_s_opc_T_1 ? 7'h13 : 7'h1F; // @[RVC.scala:53:{20,29}] wire [3:0] _io_out_s_T = io_in_0[10:7]; // @[RVC.scala:34:26, :190:7] wire [1:0] _io_out_s_T_1 = io_in_0[12:11]; // @[RVC.scala:34:35, :190:7] wire _io_out_s_T_2 = io_in_0[5]; // @[RVC.scala:34:45, :190:7] wire _io_out_s_T_28 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_59 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_68 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_101 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_110 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_185 = io_in_0[5]; // @[RVC.scala:34:45, :42:50, :190:7] wire _io_out_s_T_3 = io_in_0[6]; // @[RVC.scala:34:51, :190:7] wire _io_out_s_T_30 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_61 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_70 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_103 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_112 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_187 = io_in_0[6]; // @[RVC.scala:34:51, :42:62, :190:7] wire _io_out_s_T_249 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_260 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_271 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_282 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_ill_s_T_9 = io_in_0[6]; // @[RVC.scala:34:51, :169:69, :190:7] wire [2:0] io_out_s_lo = {_io_out_s_T_3, 2'h0}; // @[RVC.scala:34:{24,51}] wire [5:0] io_out_s_hi_hi = {_io_out_s_T, _io_out_s_T_1}; // @[RVC.scala:34:{24,26,35}] wire [6:0] io_out_s_hi = {io_out_s_hi_hi, _io_out_s_T_2}; // @[RVC.scala:34:{24,45}] wire [9:0] _io_out_s_T_4 = {io_out_s_hi, io_out_s_lo}; // @[RVC.scala:34:24] wire [2:0] _io_out_s_T_5 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_8 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_10 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_18 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_21 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_25 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_34 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_37 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_41 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_49 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_52 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_56 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_64 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_74 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_78 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_85 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_94 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_98 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_106 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_116 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_120 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_127 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_136 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_140 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_152 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_164 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_174 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_me_T_9 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_194 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_223 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_242 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_292 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_383 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7] wire [2:0] _io_out_s_T_401 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7] wire [4:0] _io_out_s_T_6 = {2'h1, _io_out_s_T_5}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_1 = {_io_out_s_T_6, io_out_s_opc}; // @[RVC.scala:31:17, :53:20, :54:15] wire [14:0] io_out_s_hi_hi_1 = {_io_out_s_T_4, 5'h2}; // @[package.scala:39:86] wire [17:0] io_out_s_hi_1 = {io_out_s_hi_hi_1, 3'h0}; // @[RVC.scala:54:15] wire [29:0] _io_out_s_T_7 = {io_out_s_hi_1, io_out_s_lo_1}; // @[RVC.scala:54:15] wire [4:0] _io_out_s_T_9 = {2'h1, _io_out_s_T_8}; // @[package.scala:39:86] wire [4:0] io_out_s_0_rd = _io_out_s_T_9; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_11 = {2'h1, _io_out_s_T_10}; // @[package.scala:39:86] wire [4:0] io_out_s_0_rs2 = _io_out_s_T_11; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_12 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_27 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_43 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_58 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_80 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_100 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_122 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_142 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_154 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_166 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_176 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_me_T_11 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_196 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_244 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_294 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_334 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_372 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_382 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_391 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_400 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_409 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_mv_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_add_T_7 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_jr_reserved_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_423 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_436 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_449 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_453 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_457 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_461 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_465 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_469 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_473 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_477 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_481 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] io_out_s_0_rs3 = _io_out_s_T_12; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_0_bits; // @[RVC.scala:21:19] assign io_out_s_0_bits = {2'h0, _io_out_s_T_7}; // @[RVC.scala:21:19, :22:14, :54:15] wire [1:0] _io_out_s_T_13 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_44 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_81 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_89 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_123 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_131 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_funct_T_1 = io_in_0[6:5]; // @[RVC.scala:36:20, :102:77, :190:7] wire [1:0] _io_out_s_sub_T = io_in_0[6:5]; // @[RVC.scala:36:20, :103:24, :190:7] wire [1:0] _io_out_s_T_297 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_305 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_315 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_323 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_337 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_345 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_355 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_363 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_385 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7] wire [1:0] _io_out_s_T_403 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7] wire [2:0] _io_out_s_T_14 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_29 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_45 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_60 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_69 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_82 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_90 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_102 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_111 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_124 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_132 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_412 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_417 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_438 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_443 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_ill_s_T_7 = io_in_0[12:10]; // @[RVC.scala:36:28, :169:22, :190:7] wire [4:0] io_out_s_hi_2 = {_io_out_s_T_13, _io_out_s_T_14}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_15 = {io_out_s_hi_2, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_16 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_23 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_32 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_39 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_47 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_54 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_66 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_76 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_87 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_96 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_108 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_118 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_129 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_138 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_200 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_202 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_208 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_210 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_218 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_220 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_225 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_227 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_238 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_240 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_290 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_311 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_330 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_332 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_351 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_370 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_411 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_416 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_437 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_442 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [4:0] _io_out_s_T_17 = {2'h1, _io_out_s_T_16}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_19 = {2'h1, _io_out_s_T_18}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_2 = {_io_out_s_T_19, 7'h7}; // @[RVC.scala:31:17, :58:23] wire [12:0] io_out_s_hi_hi_2 = {_io_out_s_T_15, _io_out_s_T_17}; // @[RVC.scala:30:17, :36:18, :58:23] wire [15:0] io_out_s_hi_3 = {io_out_s_hi_hi_2, 3'h3}; // @[RVC.scala:58:23] wire [27:0] _io_out_s_T_20 = {io_out_s_hi_3, io_out_s_lo_2}; // @[RVC.scala:58:23] wire [4:0] _io_out_s_T_22 = {2'h1, _io_out_s_T_21}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rd = _io_out_s_T_22; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_24 = {2'h1, _io_out_s_T_23}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rs1 = _io_out_s_T_24; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_26 = {2'h1, _io_out_s_T_25}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rs2 = _io_out_s_T_26; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_1_rs3 = _io_out_s_T_27; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_1_bits; // @[RVC.scala:21:19] assign io_out_s_1_bits = {4'h0, _io_out_s_T_20}; // @[RVC.scala:21:19, :22:14, :58:23] wire [2:0] io_out_s_lo_3 = {_io_out_s_T_30, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_4 = {_io_out_s_T_28, _io_out_s_T_29}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_31 = {io_out_s_hi_4, io_out_s_lo_3}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_33 = {2'h1, _io_out_s_T_32}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_35 = {2'h1, _io_out_s_T_34}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_4 = {_io_out_s_T_35, 7'h3}; // @[RVC.scala:31:17, :57:22] wire [11:0] io_out_s_hi_hi_3 = {_io_out_s_T_31, _io_out_s_T_33}; // @[RVC.scala:30:17, :35:18, :57:22] wire [14:0] io_out_s_hi_5 = {io_out_s_hi_hi_3, 3'h2}; // @[package.scala:39:86] wire [26:0] _io_out_s_T_36 = {io_out_s_hi_5, io_out_s_lo_4}; // @[RVC.scala:57:22] wire [4:0] _io_out_s_T_38 = {2'h1, _io_out_s_T_37}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rd = _io_out_s_T_38; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_40 = {2'h1, _io_out_s_T_39}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rs1 = _io_out_s_T_40; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_42 = {2'h1, _io_out_s_T_41}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rs2 = _io_out_s_T_42; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_2_rs3 = _io_out_s_T_43; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_2_bits; // @[RVC.scala:21:19] assign io_out_s_2_bits = {5'h0, _io_out_s_T_36}; // @[RVC.scala:21:19, :22:14, :57:22] wire [4:0] io_out_s_hi_6 = {_io_out_s_T_44, _io_out_s_T_45}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_46 = {io_out_s_hi_6, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_48 = {2'h1, _io_out_s_T_47}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_50 = {2'h1, _io_out_s_T_49}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_5 = {_io_out_s_T_50, 7'h3}; // @[RVC.scala:31:17, :56:22] wire [12:0] io_out_s_hi_hi_4 = {_io_out_s_T_46, _io_out_s_T_48}; // @[RVC.scala:30:17, :36:18, :56:22] wire [15:0] io_out_s_hi_7 = {io_out_s_hi_hi_4, 3'h3}; // @[RVC.scala:56:22] wire [27:0] _io_out_s_T_51 = {io_out_s_hi_7, io_out_s_lo_5}; // @[RVC.scala:56:22] wire [4:0] _io_out_s_T_53 = {2'h1, _io_out_s_T_52}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rd = _io_out_s_T_53; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_55 = {2'h1, _io_out_s_T_54}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rs1 = _io_out_s_T_55; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_57 = {2'h1, _io_out_s_T_56}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rs2 = _io_out_s_T_57; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_3_rs3 = _io_out_s_T_58; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_3_bits; // @[RVC.scala:21:19] assign io_out_s_3_bits = {4'h0, _io_out_s_T_51}; // @[RVC.scala:21:19, :22:14, :56:22] wire [2:0] io_out_s_lo_6 = {_io_out_s_T_61, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_8 = {_io_out_s_T_59, _io_out_s_T_60}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_62 = {io_out_s_hi_8, io_out_s_lo_6}; // @[RVC.scala:35:18] wire [1:0] _io_out_s_T_63 = _io_out_s_T_62[6:5]; // @[RVC.scala:35:18, :63:32] wire [4:0] _io_out_s_T_65 = {2'h1, _io_out_s_T_64}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_67 = {2'h1, _io_out_s_T_66}; // @[package.scala:39:86] wire [2:0] io_out_s_lo_7 = {_io_out_s_T_70, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_9 = {_io_out_s_T_68, _io_out_s_T_69}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_71 = {io_out_s_hi_9, io_out_s_lo_7}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_72 = _io_out_s_T_71[4:0]; // @[RVC.scala:35:18, :63:65] wire [7:0] io_out_s_lo_hi = {3'h2, _io_out_s_T_72}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_8 = {io_out_s_lo_hi, 7'h3F}; // @[RVC.scala:63:25] wire [6:0] io_out_s_hi_hi_5 = {_io_out_s_T_63, _io_out_s_T_65}; // @[RVC.scala:31:17, :63:{25,32}] wire [11:0] io_out_s_hi_10 = {io_out_s_hi_hi_5, _io_out_s_T_67}; // @[RVC.scala:30:17, :63:25] wire [26:0] _io_out_s_T_73 = {io_out_s_hi_10, io_out_s_lo_8}; // @[RVC.scala:63:25] wire [4:0] _io_out_s_T_75 = {2'h1, _io_out_s_T_74}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rd = _io_out_s_T_75; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_77 = {2'h1, _io_out_s_T_76}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rs1 = _io_out_s_T_77; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_79 = {2'h1, _io_out_s_T_78}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rs2 = _io_out_s_T_79; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_4_rs3 = _io_out_s_T_80; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_4_bits; // @[RVC.scala:21:19] assign io_out_s_4_bits = {5'h0, _io_out_s_T_73}; // @[RVC.scala:21:19, :22:14, :63:25] wire [4:0] io_out_s_hi_11 = {_io_out_s_T_81, _io_out_s_T_82}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_83 = {io_out_s_hi_11, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_84 = _io_out_s_T_83[7:5]; // @[RVC.scala:36:18, :66:30] wire [4:0] _io_out_s_T_86 = {2'h1, _io_out_s_T_85}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_88 = {2'h1, _io_out_s_T_87}; // @[package.scala:39:86] wire [4:0] io_out_s_hi_12 = {_io_out_s_T_89, _io_out_s_T_90}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_91 = {io_out_s_hi_12, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_92 = _io_out_s_T_91[4:0]; // @[RVC.scala:36:18, :66:63] wire [7:0] io_out_s_lo_hi_1 = {3'h3, _io_out_s_T_92}; // @[RVC.scala:66:{23,63}] wire [14:0] io_out_s_lo_9 = {io_out_s_lo_hi_1, 7'h27}; // @[RVC.scala:66:23] wire [7:0] io_out_s_hi_hi_6 = {_io_out_s_T_84, _io_out_s_T_86}; // @[RVC.scala:31:17, :66:{23,30}] wire [12:0] io_out_s_hi_13 = {io_out_s_hi_hi_6, _io_out_s_T_88}; // @[RVC.scala:30:17, :66:23] wire [27:0] _io_out_s_T_93 = {io_out_s_hi_13, io_out_s_lo_9}; // @[RVC.scala:66:23] wire [4:0] _io_out_s_T_95 = {2'h1, _io_out_s_T_94}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rd = _io_out_s_T_95; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_97 = {2'h1, _io_out_s_T_96}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rs1 = _io_out_s_T_97; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_99 = {2'h1, _io_out_s_T_98}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rs2 = _io_out_s_T_99; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_5_rs3 = _io_out_s_T_100; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_5_bits; // @[RVC.scala:21:19] assign io_out_s_5_bits = {4'h0, _io_out_s_T_93}; // @[RVC.scala:21:19, :22:14, :66:23] wire [2:0] io_out_s_lo_10 = {_io_out_s_T_103, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_14 = {_io_out_s_T_101, _io_out_s_T_102}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_104 = {io_out_s_hi_14, io_out_s_lo_10}; // @[RVC.scala:35:18] wire [1:0] _io_out_s_T_105 = _io_out_s_T_104[6:5]; // @[RVC.scala:35:18, :65:29] wire [4:0] _io_out_s_T_107 = {2'h1, _io_out_s_T_106}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_109 = {2'h1, _io_out_s_T_108}; // @[package.scala:39:86] wire [2:0] io_out_s_lo_11 = {_io_out_s_T_112, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_15 = {_io_out_s_T_110, _io_out_s_T_111}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_113 = {io_out_s_hi_15, io_out_s_lo_11}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_114 = _io_out_s_T_113[4:0]; // @[RVC.scala:35:18, :65:62] wire [7:0] io_out_s_lo_hi_2 = {3'h2, _io_out_s_T_114}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_12 = {io_out_s_lo_hi_2, 7'h23}; // @[RVC.scala:65:22] wire [6:0] io_out_s_hi_hi_7 = {_io_out_s_T_105, _io_out_s_T_107}; // @[RVC.scala:31:17, :65:{22,29}] wire [11:0] io_out_s_hi_16 = {io_out_s_hi_hi_7, _io_out_s_T_109}; // @[RVC.scala:30:17, :65:22] wire [26:0] _io_out_s_T_115 = {io_out_s_hi_16, io_out_s_lo_12}; // @[RVC.scala:65:22] wire [4:0] _io_out_s_T_117 = {2'h1, _io_out_s_T_116}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rd = _io_out_s_T_117; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_119 = {2'h1, _io_out_s_T_118}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rs1 = _io_out_s_T_119; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_121 = {2'h1, _io_out_s_T_120}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rs2 = _io_out_s_T_121; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_6_rs3 = _io_out_s_T_122; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_6_bits; // @[RVC.scala:21:19] assign io_out_s_6_bits = {5'h0, _io_out_s_T_115}; // @[RVC.scala:21:19, :22:14, :65:22] wire [4:0] io_out_s_hi_17 = {_io_out_s_T_123, _io_out_s_T_124}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_125 = {io_out_s_hi_17, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_126 = _io_out_s_T_125[7:5]; // @[RVC.scala:36:18, :64:29] wire [4:0] _io_out_s_T_128 = {2'h1, _io_out_s_T_127}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_130 = {2'h1, _io_out_s_T_129}; // @[package.scala:39:86] wire [4:0] io_out_s_hi_18 = {_io_out_s_T_131, _io_out_s_T_132}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_133 = {io_out_s_hi_18, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_134 = _io_out_s_T_133[4:0]; // @[RVC.scala:36:18, :64:62] wire [7:0] io_out_s_lo_hi_3 = {3'h3, _io_out_s_T_134}; // @[RVC.scala:64:{22,62}] wire [14:0] io_out_s_lo_13 = {io_out_s_lo_hi_3, 7'h23}; // @[RVC.scala:64:22] wire [7:0] io_out_s_hi_hi_8 = {_io_out_s_T_126, _io_out_s_T_128}; // @[RVC.scala:31:17, :64:{22,29}] wire [12:0] io_out_s_hi_19 = {io_out_s_hi_hi_8, _io_out_s_T_130}; // @[RVC.scala:30:17, :64:22] wire [27:0] _io_out_s_T_135 = {io_out_s_hi_19, io_out_s_lo_13}; // @[RVC.scala:64:22] wire [4:0] _io_out_s_T_137 = {2'h1, _io_out_s_T_136}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rd = _io_out_s_T_137; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_139 = {2'h1, _io_out_s_T_138}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rs1 = _io_out_s_T_139; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_141 = {2'h1, _io_out_s_T_140}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rs2 = _io_out_s_T_141; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_7_rs3 = _io_out_s_T_142; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_7_bits; // @[RVC.scala:21:19] assign io_out_s_7_bits = {4'h0, _io_out_s_T_135}; // @[RVC.scala:21:19, :22:14, :64:22] wire _io_out_s_T_143 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_155 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_167 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_opc_T_4 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_me_T = io_in_0[12]; // @[RVC.scala:41:30, :43:30, :190:7] wire _io_out_s_opc_T_9 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_182 = io_in_0[12]; // @[RVC.scala:42:34, :43:30, :190:7] wire _io_out_s_T_197 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_205 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_214 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_funct_T = io_in_0[12]; // @[RVC.scala:43:30, :102:70, :190:7] wire _io_out_s_opc_T_14 = io_in_0[12]; // @[RVC.scala:43:30, :104:24, :190:7] wire _io_out_s_T_245 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_256 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_267 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_278 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_295 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_303 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_313 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_321 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_335 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_343 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_353 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_361 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_373 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_384 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7] wire _io_out_s_T_393 = io_in_0[12]; // @[RVC.scala:37:30, :43:30, :190:7] wire _io_out_s_T_402 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7] wire _io_out_s_T_410 = io_in_0[12]; // @[RVC.scala:43:30, :143:12, :190:7] wire _io_ill_s_T_3 = io_in_0[12]; // @[RVC.scala:43:30, :168:19, :190:7] wire [6:0] _io_out_s_T_144 = {7{_io_out_s_T_143}}; // @[RVC.scala:43:{25,30}] wire [4:0] _io_out_s_T_145 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_157 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_169 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_opc_T_6 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_me_T_2 = io_in_0[6:2]; // @[RVC.scala:41:38, :43:38, :190:7] wire [4:0] _io_out_s_opc_T_11 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_198 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_206 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_216 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_374 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_381 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_390 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_399 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_408 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_mv_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_add_T_6 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_reserved_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_415 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_422 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_428 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_435 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_441 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_448 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_ill_s_T_4 = io_in_0[6:2]; // @[RVC.scala:43:38, :168:27, :190:7] wire [11:0] _io_out_s_T_146 = {_io_out_s_T_144, _io_out_s_T_145}; // @[RVC.scala:43:{20,25,38}] wire [4:0] _io_out_s_T_147 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_148 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_150 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_151 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_opc_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_159 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_160 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_162 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_163 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_171 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_173 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_7 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_8 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_177 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_179 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_189 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_190 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_192 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_193 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_load_opc_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_376 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_377 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_379 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_380 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_387 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_389 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_396 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_398 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_405 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_407 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_mv_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_mv_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_4 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_reserved_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_reserved_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_421 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_434 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_447 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_450 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_454 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_458 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_462 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_466 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_470 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_474 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_478 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_ill_s_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_ill_s_T_11 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_ill_s_T_12 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [11:0] io_out_s_lo_14 = {_io_out_s_T_148, 7'h13}; // @[RVC.scala:33:13, :75:24] wire [16:0] io_out_s_hi_hi_9 = {_io_out_s_T_146, _io_out_s_T_147}; // @[RVC.scala:33:13, :43:20, :75:24] wire [19:0] io_out_s_hi_20 = {io_out_s_hi_hi_9, 3'h0}; // @[RVC.scala:75:24] wire [31:0] _io_out_s_T_149 = {io_out_s_hi_20, io_out_s_lo_14}; // @[RVC.scala:75:24] wire [31:0] io_out_s_8_bits = _io_out_s_T_149; // @[RVC.scala:21:19, :75:24] wire [4:0] io_out_s_8_rd = _io_out_s_T_150; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_8_rs1 = _io_out_s_T_151; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_153 = {2'h1, _io_out_s_T_152}; // @[package.scala:39:86] wire [4:0] io_out_s_8_rs2 = _io_out_s_T_153; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_8_rs3 = _io_out_s_T_154; // @[RVC.scala:20:101, :21:19] wire _io_out_s_opc_T_3 = \|_io_out_s_opc_T_2; // @[RVC.scala:33:13, :77:24] wire [6:0] io_out_s_opc_1 = {4'h3, ~_io_out_s_opc_T_3, 2'h3}; // @[RVC.scala:77:{20,24}] wire [6:0] _io_out_s_T_156 = {7{_io_out_s_T_155}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_158 = {_io_out_s_T_156, _io_out_s_T_157}; // @[RVC.scala:43:{20,25,38}] wire [11:0] io_out_s_lo_15 = {_io_out_s_T_160, io_out_s_opc_1}; // @[RVC.scala:33:13, :77:20, :78:15] wire [16:0] io_out_s_hi_hi_10 = {_io_out_s_T_158, _io_out_s_T_159}; // @[RVC.scala:33:13, :43:20, :78:15] wire [19:0] io_out_s_hi_21 = {io_out_s_hi_hi_10, 3'h0}; // @[RVC.scala:78:15] wire [31:0] _io_out_s_T_161 = {io_out_s_hi_21, io_out_s_lo_15}; // @[RVC.scala:78:15] wire [31:0] io_out_s_9_bits = _io_out_s_T_161; // @[RVC.scala:21:19, :78:15] wire [4:0] io_out_s_9_rd = _io_out_s_T_162; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_9_rs1 = _io_out_s_T_163; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_165 = {2'h1, _io_out_s_T_164}; // @[package.scala:39:86] wire [4:0] io_out_s_9_rs2 = _io_out_s_T_165; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_9_rs3 = _io_out_s_T_166; // @[RVC.scala:20:101, :21:19] wire [6:0] _io_out_s_T_168 = {7{_io_out_s_T_167}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_170 = {_io_out_s_T_168, _io_out_s_T_169}; // @[RVC.scala:43:{20,25,38}] wire [11:0] io_out_s_lo_16 = {_io_out_s_T_171, 7'h13}; // @[RVC.scala:33:13, :84:22] wire [16:0] io_out_s_hi_hi_11 = {_io_out_s_T_170, 5'h0}; // @[RVC.scala:43:20, :84:22] wire [19:0] io_out_s_hi_22 = {io_out_s_hi_hi_11, 3'h0}; // @[RVC.scala:84:22] wire [31:0] _io_out_s_T_172 = {io_out_s_hi_22, io_out_s_lo_16}; // @[RVC.scala:84:22] wire [31:0] io_out_s_10_bits = _io_out_s_T_172; // @[RVC.scala:21:19, :84:22] wire [4:0] io_out_s_10_rd = _io_out_s_T_173; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_175 = {2'h1, _io_out_s_T_174}; // @[package.scala:39:86] wire [4:0] io_out_s_10_rs2 = _io_out_s_T_175; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_10_rs3 = _io_out_s_T_176; // @[RVC.scala:20:101, :21:19] wire [6:0] _io_out_s_opc_T_5 = {7{_io_out_s_opc_T_4}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_opc_T_7 = {_io_out_s_opc_T_5, _io_out_s_opc_T_6}; // @[RVC.scala:43:{20,25,38}] wire _io_out_s_opc_T_8 = \|_io_out_s_opc_T_7; // @[RVC.scala:43:20, :90:29] wire [6:0] io_out_s_opc_2 = {3'h3, ~_io_out_s_opc_T_8, 3'h7}; // @[RVC.scala:90:{20,29}] wire [14:0] _io_out_s_me_T_1 = {15{_io_out_s_me_T}}; // @[RVC.scala:41:{24,30}] wire [19:0] io_out_s_me_hi = {_io_out_s_me_T_1, _io_out_s_me_T_2}; // @[RVC.scala:41:{19,24,38}] wire [31:0] _io_out_s_me_T_3 = {io_out_s_me_hi, 12'h0}; // @[RVC.scala:41:19] wire [19:0] _io_out_s_me_T_4 = _io_out_s_me_T_3[31:12]; // @[RVC.scala:41:19, :91:31] wire [24:0] io_out_s_me_hi_1 = {_io_out_s_me_T_4, _io_out_s_me_T_5}; // @[RVC.scala:33:13, :91:{24,31}] wire [31:0] _io_out_s_me_T_6 = {io_out_s_me_hi_1, io_out_s_opc_2}; // @[RVC.scala:90:20, :91:24] wire [31:0] io_out_s_me_bits = _io_out_s_me_T_6; // @[RVC.scala:21:19, :91:24] wire [4:0] io_out_s_me_rd = _io_out_s_me_T_7; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_me_rs1 = _io_out_s_me_T_8; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_me_T_10 = {2'h1, _io_out_s_me_T_9}; // @[package.scala:39:86] wire [4:0] io_out_s_me_rs2 = _io_out_s_me_T_10; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_me_rs3 = _io_out_s_me_T_11; // @[RVC.scala:20:101, :21:19] wire _io_out_s_T_178 = _io_out_s_T_177 == 5'h0; // @[RVC.scala:33:13, :92:14] wire _io_out_s_T_180 = _io_out_s_T_179 == 5'h2; // @[package.scala:39:86] wire _io_out_s_T_181 = _io_out_s_T_178 \| _io_out_s_T_180; // @[RVC.scala:92:{14,21,27}] wire [6:0] _io_out_s_opc_T_10 = {7{_io_out_s_opc_T_9}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_opc_T_12 = {_io_out_s_opc_T_10, _io_out_s_opc_T_11}; // @[RVC.scala:43:{20,25,38}] wire _io_out_s_opc_T_13 = \|_io_out_s_opc_T_12; // @[RVC.scala:43:20, :86:29] wire [6:0] io_out_s_opc_3 = _io_out_s_opc_T_13 ? 7'h13 : 7'h1F; // @[RVC.scala:86:{20,29}] wire [2:0] _io_out_s_T_183 = {3{_io_out_s_T_182}}; // @[RVC.scala:42:{29,34}] wire [1:0] _io_out_s_T_184 = io_in_0[4:3]; // @[RVC.scala:42:42, :190:7] wire [1:0] _io_out_s_T_300 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_308 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_318 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_326 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_340 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_348 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_358 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_366 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire _io_out_s_T_186 = io_in_0[2]; // @[RVC.scala:42:56, :190:7] wire _io_out_s_T_251 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_262 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_273 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_284 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_298 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_306 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_316 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_324 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_338 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_346 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_356 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_364 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire [1:0] io_out_s_lo_hi_4 = {_io_out_s_T_186, _io_out_s_T_187}; // @[RVC.scala:42:{24,56,62}] wire [5:0] io_out_s_lo_17 = {io_out_s_lo_hi_4, 4'h0}; // @[RVC.scala:42:24] wire [4:0] io_out_s_hi_hi_12 = {_io_out_s_T_183, _io_out_s_T_184}; // @[RVC.scala:42:{24,29,42}] wire [5:0] io_out_s_hi_23 = {io_out_s_hi_hi_12, _io_out_s_T_185}; // @[RVC.scala:42:{24,50}] wire [11:0] _io_out_s_T_188 = {io_out_s_hi_23, io_out_s_lo_17}; // @[RVC.scala:42:24] wire [11:0] io_out_s_lo_18 = {_io_out_s_T_190, io_out_s_opc_3}; // @[RVC.scala:33:13, :86:20, :87:15] wire [16:0] io_out_s_hi_hi_13 = {_io_out_s_T_188, _io_out_s_T_189}; // @[RVC.scala:33:13, :42:24, :87:15] wire [19:0] io_out_s_hi_24 = {io_out_s_hi_hi_13, 3'h0}; // @[RVC.scala:87:15] wire [31:0] _io_out_s_T_191 = {io_out_s_hi_24, io_out_s_lo_18}; // @[RVC.scala:87:15] wire [31:0] io_out_s_res_bits = _io_out_s_T_191; // @[RVC.scala:21:19, :87:15] wire [4:0] io_out_s_res_rd = _io_out_s_T_192; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_res_rs1 = _io_out_s_T_193; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_195 = {2'h1, _io_out_s_T_194}; // @[package.scala:39:86] wire [4:0] io_out_s_res_rs2 = _io_out_s_T_195; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_res_rs3 = _io_out_s_T_196; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_11_bits = _io_out_s_T_181 ? io_out_s_res_bits : io_out_s_me_bits; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rd = _io_out_s_T_181 ? io_out_s_res_rd : io_out_s_me_rd; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs1 = _io_out_s_T_181 ? io_out_s_res_rs1 : io_out_s_me_rs1; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs2 = _io_out_s_T_181 ? io_out_s_res_rs2 : io_out_s_me_rs2; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs3 = _io_out_s_T_181 ? io_out_s_res_rs3 : io_out_s_me_rs3; // @[RVC.scala:21:19, :92:{10,21}] wire [5:0] _io_out_s_T_199 = {_io_out_s_T_197, _io_out_s_T_198}; // @[RVC.scala:46:{18,20,27}] wire [4:0] _io_out_s_T_201 = {2'h1, _io_out_s_T_200}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_203 = {2'h1, _io_out_s_T_202}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_19 = {_io_out_s_T_203, 7'h13}; // @[RVC.scala:30:17, :98:21] wire [10:0] io_out_s_hi_hi_14 = {_io_out_s_T_199, _io_out_s_T_201}; // @[RVC.scala:30:17, :46:18, :98:21] wire [13:0] io_out_s_hi_25 = {io_out_s_hi_hi_14, 3'h5}; // @[RVC.scala:98:21] wire [25:0] _io_out_s_T_204 = {io_out_s_hi_25, io_out_s_lo_19}; // @[RVC.scala:98:21] wire [5:0] _io_out_s_T_207 = {_io_out_s_T_205, _io_out_s_T_206}; // @[RVC.scala:46:{18,20,27}] wire [4:0] _io_out_s_T_209 = {2'h1, _io_out_s_T_208}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_211 = {2'h1, _io_out_s_T_210}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_20 = {_io_out_s_T_211, 7'h13}; // @[RVC.scala:30:17, :98:21] wire [10:0] io_out_s_hi_hi_15 = {_io_out_s_T_207, _io_out_s_T_209}; // @[RVC.scala:30:17, :46:18, :98:21] wire [13:0] io_out_s_hi_26 = {io_out_s_hi_hi_15, 3'h5}; // @[RVC.scala:98:21] wire [25:0] _io_out_s_T_212 = {io_out_s_hi_26, io_out_s_lo_20}; // @[RVC.scala:98:21] wire [30:0] _io_out_s_T_213 = {5'h10, _io_out_s_T_212}; // @[RVC.scala:98:21, :99:23] wire [6:0] _io_out_s_T_215 = {7{_io_out_s_T_214}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_217 = {_io_out_s_T_215, _io_out_s_T_216}; // @[RVC.scala:43:{20,25,38}] wire [4:0] _io_out_s_T_219 = {2'h1, _io_out_s_T_218}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_221 = {2'h1, _io_out_s_T_220}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_21 = {_io_out_s_T_221, 7'h13}; // @[RVC.scala:30:17, :100:21] wire [16:0] io_out_s_hi_hi_16 = {_io_out_s_T_217, _io_out_s_T_219}; // @[RVC.scala:30:17, :43:20, :100:21] wire [19:0] io_out_s_hi_27 = {io_out_s_hi_hi_16, 3'h7}; // @[RVC.scala:100:21] wire [31:0] _io_out_s_T_222 = {io_out_s_hi_27, io_out_s_lo_21}; // @[RVC.scala:100:21] wire [2:0] _io_out_s_funct_T_2 = {_io_out_s_funct_T, _io_out_s_funct_T_1}; // @[RVC.scala:102:{68,70,77}] wire _io_out_s_funct_T_3 = _io_out_s_funct_T_2 == 3'h1; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_4 = {_io_out_s_funct_T_3, 2'h0}; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_5 = _io_out_s_funct_T_2 == 3'h2; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_6 = _io_out_s_funct_T_5 ? 3'h6 : _io_out_s_funct_T_4; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_7 = _io_out_s_funct_T_2 == 3'h3; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_8 = _io_out_s_funct_T_7 ? 3'h7 : _io_out_s_funct_T_6; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_9 = _io_out_s_funct_T_2 == 3'h4; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_10 = _io_out_s_funct_T_9 ? 3'h0 : _io_out_s_funct_T_8; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_11 = _io_out_s_funct_T_2 == 3'h5; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_12 = _io_out_s_funct_T_11 ? 3'h0 : _io_out_s_funct_T_10; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_13 = _io_out_s_funct_T_2 == 3'h6; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_14 = _io_out_s_funct_T_13 ? 3'h2 : _io_out_s_funct_T_12; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_15 = &_io_out_s_funct_T_2; // @[package.scala:39:86] wire [2:0] io_out_s_funct = _io_out_s_funct_T_15 ? 3'h3 : _io_out_s_funct_T_14; // @[package.scala:39:{76,86}] wire _io_out_s_sub_T_1 = _io_out_s_sub_T == 2'h0; // @[RVC.scala:103:{24,30}] wire [30:0] io_out_s_sub = {_io_out_s_sub_T_1, 30'h0}; // @[RVC.scala:103:{22,30}] wire [6:0] io_out_s_opc_4 = {3'h3, _io_out_s_opc_T_14, 3'h3}; // @[RVC.scala:104:{22,24}] wire [4:0] _io_out_s_T_224 = {2'h1, _io_out_s_T_223}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_226 = {2'h1, _io_out_s_T_225}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_228 = {2'h1, _io_out_s_T_227}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_22 = {_io_out_s_T_228, io_out_s_opc_4}; // @[RVC.scala:30:17, :104:22, :105:12] wire [9:0] io_out_s_hi_hi_17 = {_io_out_s_T_224, _io_out_s_T_226}; // @[RVC.scala:30:17, :31:17, :105:12] wire [12:0] io_out_s_hi_28 = {io_out_s_hi_hi_17, io_out_s_funct}; // @[package.scala:39:76] wire [24:0] _io_out_s_T_229 = {io_out_s_hi_28, io_out_s_lo_22}; // @[RVC.scala:105:12] wire [30:0] _io_out_s_T_230 = {6'h0, _io_out_s_T_229} \| io_out_s_sub; // @[RVC.scala:103:22, :105:{12,43}] wire [1:0] _io_out_s_T_231 = io_in_0[11:10]; // @[RVC.scala:107:42, :190:7] wire [1:0] _io_out_s_T_299 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_307 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_317 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_325 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_339 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_347 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_357 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_365 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire _io_out_s_T_232 = _io_out_s_T_231 == 2'h1; // @[package.scala:39:86] wire [30:0] _io_out_s_T_233 = _io_out_s_T_232 ? _io_out_s_T_213 : {5'h0, _io_out_s_T_204}; // @[package.scala:39:{76,86}] wire _io_out_s_T_234 = _io_out_s_T_231 == 2'h2; // @[package.scala:39:86] wire [31:0] _io_out_s_T_235 = _io_out_s_T_234 ? _io_out_s_T_222 : {1'h0, _io_out_s_T_233}; // @[package.scala:39:{76,86}] wire _io_out_s_T_236 = &_io_out_s_T_231; // @[package.scala:39:86] wire [31:0] _io_out_s_T_237 = _io_out_s_T_236 ? {1'h0, _io_out_s_T_230} : _io_out_s_T_235; // @[package.scala:39:{76,86}] wire [31:0] io_out_s_12_bits = _io_out_s_T_237; // @[package.scala:39:76] wire [4:0] _io_out_s_T_239 = {2'h1, _io_out_s_T_238}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rd = _io_out_s_T_239; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_241 = {2'h1, _io_out_s_T_240}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rs1 = _io_out_s_T_241; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_243 = {2'h1, _io_out_s_T_242}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rs2 = _io_out_s_T_243; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_12_rs3 = _io_out_s_T_244; // @[RVC.scala:20:101, :21:19] wire [9:0] _io_out_s_T_246 = {10{_io_out_s_T_245}}; // @[RVC.scala:44:{22,28}] wire _io_out_s_T_247 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_258 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_269 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_280 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire [1:0] _io_out_s_T_248 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_259 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_270 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_281 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire _io_out_s_T_250 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_261 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_272 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_283 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_252 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_263 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_274 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_285 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire [2:0] _io_out_s_T_253 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_264 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_275 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_286 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [3:0] io_out_s_lo_lo = {_io_out_s_T_253, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_5 = {_io_out_s_T_251, _io_out_s_T_252}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_23 = {io_out_s_lo_hi_5, io_out_s_lo_lo}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo = {_io_out_s_T_249, _io_out_s_T_250}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi = {_io_out_s_T_246, _io_out_s_T_247}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_18 = {io_out_s_hi_hi_hi, _io_out_s_T_248}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_29 = {io_out_s_hi_hi_18, io_out_s_hi_lo}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_254 = {io_out_s_hi_29, io_out_s_lo_23}; // @[RVC.scala:44:17] wire _io_out_s_T_255 = _io_out_s_T_254[20]; // @[RVC.scala:44:17, :94:26] wire [9:0] _io_out_s_T_257 = {10{_io_out_s_T_256}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_1 = {_io_out_s_T_264, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_6 = {_io_out_s_T_262, _io_out_s_T_263}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_24 = {io_out_s_lo_hi_6, io_out_s_lo_lo_1}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_1 = {_io_out_s_T_260, _io_out_s_T_261}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_1 = {_io_out_s_T_257, _io_out_s_T_258}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_19 = {io_out_s_hi_hi_hi_1, _io_out_s_T_259}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_30 = {io_out_s_hi_hi_19, io_out_s_hi_lo_1}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_265 = {io_out_s_hi_30, io_out_s_lo_24}; // @[RVC.scala:44:17] wire [9:0] _io_out_s_T_266 = _io_out_s_T_265[10:1]; // @[RVC.scala:44:17, :94:36] wire [9:0] _io_out_s_T_268 = {10{_io_out_s_T_267}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_2 = {_io_out_s_T_275, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_7 = {_io_out_s_T_273, _io_out_s_T_274}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_25 = {io_out_s_lo_hi_7, io_out_s_lo_lo_2}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_2 = {_io_out_s_T_271, _io_out_s_T_272}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_2 = {_io_out_s_T_268, _io_out_s_T_269}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_20 = {io_out_s_hi_hi_hi_2, _io_out_s_T_270}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_31 = {io_out_s_hi_hi_20, io_out_s_hi_lo_2}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_276 = {io_out_s_hi_31, io_out_s_lo_25}; // @[RVC.scala:44:17] wire _io_out_s_T_277 = _io_out_s_T_276[11]; // @[RVC.scala:44:17, :94:48] wire [9:0] _io_out_s_T_279 = {10{_io_out_s_T_278}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_3 = {_io_out_s_T_286, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_8 = {_io_out_s_T_284, _io_out_s_T_285}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_26 = {io_out_s_lo_hi_8, io_out_s_lo_lo_3}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_3 = {_io_out_s_T_282, _io_out_s_T_283}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_3 = {_io_out_s_T_279, _io_out_s_T_280}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_21 = {io_out_s_hi_hi_hi_3, _io_out_s_T_281}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_32 = {io_out_s_hi_hi_21, io_out_s_hi_lo_3}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_287 = {io_out_s_hi_32, io_out_s_lo_26}; // @[RVC.scala:44:17] wire [7:0] _io_out_s_T_288 = _io_out_s_T_287[19:12]; // @[RVC.scala:44:17, :94:58] wire [12:0] io_out_s_lo_hi_9 = {_io_out_s_T_288, 5'h0}; // @[RVC.scala:94:{21,58}] wire [19:0] io_out_s_lo_27 = {io_out_s_lo_hi_9, 7'h6F}; // @[RVC.scala:94:21] wire [10:0] io_out_s_hi_hi_22 = {_io_out_s_T_255, _io_out_s_T_266}; // @[RVC.scala:94:{21,26,36}] wire [11:0] io_out_s_hi_33 = {io_out_s_hi_hi_22, _io_out_s_T_277}; // @[RVC.scala:94:{21,48}] wire [31:0] _io_out_s_T_289 = {io_out_s_hi_33, io_out_s_lo_27}; // @[RVC.scala:94:21] wire [31:0] io_out_s_13_bits = _io_out_s_T_289; // @[RVC.scala:21:19, :94:21] wire [4:0] _io_out_s_T_291 = {2'h1, _io_out_s_T_290}; // @[package.scala:39:86] wire [4:0] io_out_s_13_rs1 = _io_out_s_T_291; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_293 = {2'h1, _io_out_s_T_292}; // @[package.scala:39:86] wire [4:0] io_out_s_13_rs2 = _io_out_s_T_293; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_13_rs3 = _io_out_s_T_294; // @[RVC.scala:20:101, :21:19] wire [4:0] _io_out_s_T_296 = {5{_io_out_s_T_295}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_10 = {_io_out_s_T_299, _io_out_s_T_300}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_28 = {io_out_s_lo_hi_10, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_23 = {_io_out_s_T_296, _io_out_s_T_297}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_34 = {io_out_s_hi_hi_23, _io_out_s_T_298}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_301 = {io_out_s_hi_34, io_out_s_lo_28}; // @[RVC.scala:45:17] wire _io_out_s_T_302 = _io_out_s_T_301[12]; // @[RVC.scala:45:17, :95:29] wire [4:0] _io_out_s_T_304 = {5{_io_out_s_T_303}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_11 = {_io_out_s_T_307, _io_out_s_T_308}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_29 = {io_out_s_lo_hi_11, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_24 = {_io_out_s_T_304, _io_out_s_T_305}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_35 = {io_out_s_hi_hi_24, _io_out_s_T_306}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_309 = {io_out_s_hi_35, io_out_s_lo_29}; // @[RVC.scala:45:17] wire [5:0] _io_out_s_T_310 = _io_out_s_T_309[10:5]; // @[RVC.scala:45:17, :95:39] wire [4:0] _io_out_s_T_312 = {2'h1, _io_out_s_T_311}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_314 = {5{_io_out_s_T_313}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_12 = {_io_out_s_T_317, _io_out_s_T_318}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_30 = {io_out_s_lo_hi_12, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_25 = {_io_out_s_T_314, _io_out_s_T_315}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_36 = {io_out_s_hi_hi_25, _io_out_s_T_316}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_319 = {io_out_s_hi_36, io_out_s_lo_30}; // @[RVC.scala:45:17] wire [3:0] _io_out_s_T_320 = _io_out_s_T_319[4:1]; // @[RVC.scala:45:17, :95:71] wire [4:0] _io_out_s_T_322 = {5{_io_out_s_T_321}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_13 = {_io_out_s_T_325, _io_out_s_T_326}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_31 = {io_out_s_lo_hi_13, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_26 = {_io_out_s_T_322, _io_out_s_T_323}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_37 = {io_out_s_hi_hi_26, _io_out_s_T_324}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_327 = {io_out_s_hi_37, io_out_s_lo_31}; // @[RVC.scala:45:17] wire _io_out_s_T_328 = _io_out_s_T_327[11]; // @[RVC.scala:45:17, :95:82] wire [7:0] io_out_s_lo_lo_4 = {_io_out_s_T_328, 7'h63}; // @[RVC.scala:95:{24,82}] wire [6:0] io_out_s_lo_hi_14 = {3'h0, _io_out_s_T_320}; // @[RVC.scala:95:{24,71}] wire [14:0] io_out_s_lo_32 = {io_out_s_lo_hi_14, io_out_s_lo_lo_4}; // @[RVC.scala:95:24] wire [9:0] io_out_s_hi_lo_4 = {5'h0, _io_out_s_T_312}; // @[RVC.scala:30:17, :95:24] wire [6:0] io_out_s_hi_hi_27 = {_io_out_s_T_302, _io_out_s_T_310}; // @[RVC.scala:95:{24,29,39}] wire [16:0] io_out_s_hi_38 = {io_out_s_hi_hi_27, io_out_s_hi_lo_4}; // @[RVC.scala:95:24] wire [31:0] _io_out_s_T_329 = {io_out_s_hi_38, io_out_s_lo_32}; // @[RVC.scala:95:24] wire [31:0] io_out_s_14_bits = _io_out_s_T_329; // @[RVC.scala:21:19, :95:24] wire [4:0] _io_out_s_T_331 = {2'h1, _io_out_s_T_330}; // @[package.scala:39:86] wire [4:0] io_out_s_14_rd = _io_out_s_T_331; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_333 = {2'h1, _io_out_s_T_332}; // @[package.scala:39:86] wire [4:0] io_out_s_14_rs1 = _io_out_s_T_333; // @[RVC.scala:21:19, :30:17] wire [4:0] io_out_s_14_rs3 = _io_out_s_T_334; // @[RVC.scala:20:101, :21:19] wire [4:0] _io_out_s_T_336 = {5{_io_out_s_T_335}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_15 = {_io_out_s_T_339, _io_out_s_T_340}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_33 = {io_out_s_lo_hi_15, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_28 = {_io_out_s_T_336, _io_out_s_T_337}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_39 = {io_out_s_hi_hi_28, _io_out_s_T_338}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_341 = {io_out_s_hi_39, io_out_s_lo_33}; // @[RVC.scala:45:17] wire _io_out_s_T_342 = _io_out_s_T_341[12]; // @[RVC.scala:45:17, :96:29] wire [4:0] _io_out_s_T_344 = {5{_io_out_s_T_343}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_16 = {_io_out_s_T_347, _io_out_s_T_348}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_34 = {io_out_s_lo_hi_16, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_29 = {_io_out_s_T_344, _io_out_s_T_345}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_40 = {io_out_s_hi_hi_29, _io_out_s_T_346}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_349 = {io_out_s_hi_40, io_out_s_lo_34}; // @[RVC.scala:45:17] wire [5:0] _io_out_s_T_350 = _io_out_s_T_349[10:5]; // @[RVC.scala:45:17, :96:39] wire [4:0] _io_out_s_T_352 = {2'h1, _io_out_s_T_351}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_354 = {5{_io_out_s_T_353}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_17 = {_io_out_s_T_357, _io_out_s_T_358}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_35 = {io_out_s_lo_hi_17, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_30 = {_io_out_s_T_354, _io_out_s_T_355}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_41 = {io_out_s_hi_hi_30, _io_out_s_T_356}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_359 = {io_out_s_hi_41, io_out_s_lo_35}; // @[RVC.scala:45:17] wire [3:0] _io_out_s_T_360 = _io_out_s_T_359[4:1]; // @[RVC.scala:45:17, :96:71] wire [4:0] _io_out_s_T_362 = {5{_io_out_s_T_361}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_18 = {_io_out_s_T_365, _io_out_s_T_366}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_36 = {io_out_s_lo_hi_18, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_31 = {_io_out_s_T_362, _io_out_s_T_363}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_42 = {io_out_s_hi_hi_31, _io_out_s_T_364}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_367 = {io_out_s_hi_42, io_out_s_lo_36}; // @[RVC.scala:45:17] wire _io_out_s_T_368 = _io_out_s_T_367[11]; // @[RVC.scala:45:17, :96:82] wire [7:0] io_out_s_lo_lo_5 = {_io_out_s_T_368, 7'h63}; // @[RVC.scala:96:{24,82}] wire [6:0] io_out_s_lo_hi_19 = {3'h1, _io_out_s_T_360}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_37 = {io_out_s_lo_hi_19, io_out_s_lo_lo_5}; // @[RVC.scala:96:24] wire [9:0] io_out_s_hi_lo_5 = {5'h0, _io_out_s_T_352}; // @[RVC.scala:30:17, :96:24] wire [6:0] io_out_s_hi_hi_32 = {_io_out_s_T_342, _io_out_s_T_350}; // @[RVC.scala:96:{24,29,39}] wire [16:0] io_out_s_hi_43 = {io_out_s_hi_hi_32, io_out_s_hi_lo_5}; // @[RVC.scala:96:24] wire [31:0] _io_out_s_T_369 = {io_out_s_hi_43, io_out_s_lo_37}; // @[RVC.scala:96:24] wire [31:0] io_out_s_15_bits = _io_out_s_T_369; // @[RVC.scala:21:19, :96:24] wire [4:0] _io_out_s_T_371 = {2'h1, _io_out_s_T_370}; // @[package.scala:39:86] wire [4:0] io_out_s_15_rs1 = _io_out_s_T_371; // @[RVC.scala:21:19, :30:17] wire [4:0] io_out_s_15_rs3 = _io_out_s_T_372; // @[RVC.scala:20:101, :21:19] wire _io_out_s_load_opc_T_1 = \|_io_out_s_load_opc_T; // @[RVC.scala:33:13, :113:27] wire [6:0] io_out_s_load_opc = _io_out_s_load_opc_T_1 ? 7'h3 : 7'h1F; // @[RVC.scala:113:{23,27}] wire [5:0] _io_out_s_T_375 = {_io_out_s_T_373, _io_out_s_T_374}; // @[RVC.scala:46:{18,20,27}] wire [11:0] io_out_s_lo_38 = {_io_out_s_T_377, 7'h13}; // @[RVC.scala:33:13, :114:24] wire [10:0] io_out_s_hi_hi_33 = {_io_out_s_T_375, _io_out_s_T_376}; // @[RVC.scala:33:13, :46:18, :114:24] wire [13:0] io_out_s_hi_44 = {io_out_s_hi_hi_33, 3'h1}; // @[package.scala:39:86] wire [25:0] _io_out_s_T_378 = {io_out_s_hi_44, io_out_s_lo_38}; // @[RVC.scala:114:24] wire [4:0] io_out_s_16_rd = _io_out_s_T_379; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_16_rs1 = _io_out_s_T_380; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_16_rs2 = _io_out_s_T_381; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_16_rs3 = _io_out_s_T_382; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_16_bits; // @[RVC.scala:21:19] assign io_out_s_16_bits = {6'h0, _io_out_s_T_378}; // @[RVC.scala:21:19, :22:14, :105:43, :114:24] wire [4:0] io_out_s_lo_39 = {_io_out_s_T_385, 3'h0}; // @[RVC.scala:38:{20,37}] wire [3:0] io_out_s_hi_45 = {_io_out_s_T_383, _io_out_s_T_384}; // @[RVC.scala:38:{20,22,30}] wire [8:0] _io_out_s_T_386 = {io_out_s_hi_45, io_out_s_lo_39}; // @[RVC.scala:38:20] wire [11:0] io_out_s_lo_40 = {_io_out_s_T_387, 7'h7}; // @[RVC.scala:33:13, :117:25] wire [13:0] io_out_s_hi_hi_34 = {_io_out_s_T_386, 5'h2}; // @[package.scala:39:86] wire [16:0] io_out_s_hi_46 = {io_out_s_hi_hi_34, 3'h3}; // @[RVC.scala:117:25] wire [28:0] _io_out_s_T_388 = {io_out_s_hi_46, io_out_s_lo_40}; // @[RVC.scala:117:25] wire [4:0] io_out_s_17_rd = _io_out_s_T_389; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_17_rs2 = _io_out_s_T_390; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_17_rs3 = _io_out_s_T_391; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_17_bits; // @[RVC.scala:21:19] assign io_out_s_17_bits = {3'h0, _io_out_s_T_388}; // @[RVC.scala:21:19, :22:14, :117:25] wire [1:0] _io_out_s_T_392 = io_in_0[3:2]; // @[RVC.scala:37:22, :190:7] wire [2:0] _io_out_s_T_394 = io_in_0[6:4]; // @[RVC.scala:37:37, :190:7] wire [4:0] io_out_s_lo_41 = {_io_out_s_T_394, 2'h0}; // @[RVC.scala:37:{20,37}] wire [2:0] io_out_s_hi_47 = {_io_out_s_T_392, _io_out_s_T_393}; // @[RVC.scala:37:{20,22,30}] wire [7:0] _io_out_s_T_395 = {io_out_s_hi_47, io_out_s_lo_41}; // @[RVC.scala:37:20] wire [11:0] io_out_s_lo_42 = {_io_out_s_T_396, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :116:24] wire [12:0] io_out_s_hi_hi_35 = {_io_out_s_T_395, 5'h2}; // @[package.scala:39:86] wire [15:0] io_out_s_hi_48 = {io_out_s_hi_hi_35, 3'h2}; // @[package.scala:39:86] wire [27:0] _io_out_s_T_397 = {io_out_s_hi_48, io_out_s_lo_42}; // @[RVC.scala:116:24] wire [4:0] io_out_s_18_rd = _io_out_s_T_398; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_18_rs2 = _io_out_s_T_399; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_18_rs3 = _io_out_s_T_400; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_18_bits; // @[RVC.scala:21:19] assign io_out_s_18_bits = {4'h0, _io_out_s_T_397}; // @[RVC.scala:21:19, :22:14, :116:24] wire [4:0] io_out_s_lo_43 = {_io_out_s_T_403, 3'h0}; // @[RVC.scala:38:{20,37}] wire [3:0] io_out_s_hi_49 = {_io_out_s_T_401, _io_out_s_T_402}; // @[RVC.scala:38:{20,22,30}] wire [8:0] _io_out_s_T_404 = {io_out_s_hi_49, io_out_s_lo_43}; // @[RVC.scala:38:20] wire [11:0] io_out_s_lo_44 = {_io_out_s_T_405, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :115:24] wire [13:0] io_out_s_hi_hi_36 = {_io_out_s_T_404, 5'h2}; // @[package.scala:39:86] wire [16:0] io_out_s_hi_50 = {io_out_s_hi_hi_36, 3'h3}; // @[RVC.scala:115:24] wire [28:0] _io_out_s_T_406 = {io_out_s_hi_50, io_out_s_lo_44}; // @[RVC.scala:115:24] wire [4:0] io_out_s_19_rd = _io_out_s_T_407; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_19_rs2 = _io_out_s_T_408; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_19_rs3 = _io_out_s_T_409; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_19_bits; // @[RVC.scala:21:19] assign io_out_s_19_bits = {3'h0, _io_out_s_T_406}; // @[RVC.scala:21:19, :22:14, :115:24] wire [11:0] io_out_s_mv_lo = {_io_out_s_mv_T_1, 7'h33}; // @[RVC.scala:33:13, :132:22] wire [9:0] io_out_s_mv_hi_hi = {_io_out_s_mv_T, 5'h0}; // @[RVC.scala:32:14, :132:22] wire [12:0] io_out_s_mv_hi = {io_out_s_mv_hi_hi, 3'h0}; // @[RVC.scala:132:22] wire [24:0] _io_out_s_mv_T_2 = {io_out_s_mv_hi, io_out_s_mv_lo}; // @[RVC.scala:132:22] wire [4:0] io_out_s_mv_rd = _io_out_s_mv_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_mv_rs2 = _io_out_s_mv_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_mv_rs3 = _io_out_s_mv_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_mv_bits; // @[RVC.scala:21:19] assign io_out_s_mv_bits = {7'h0, _io_out_s_mv_T_2}; // @[RVC.scala:21:19, :22:14, :132:22] wire [11:0] io_out_s_add_lo = {_io_out_s_add_T_2, 7'h33}; // @[RVC.scala:33:13, :134:25] wire [9:0] io_out_s_add_hi_hi = {_io_out_s_add_T, _io_out_s_add_T_1}; // @[RVC.scala:32:14, :33:13, :134:25] wire [12:0] io_out_s_add_hi = {io_out_s_add_hi_hi, 3'h0}; // @[RVC.scala:134:25] wire [24:0] _io_out_s_add_T_3 = {io_out_s_add_hi, io_out_s_add_lo}; // @[RVC.scala:134:25] wire [4:0] io_out_s_add_rd = _io_out_s_add_T_4; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_add_rs1 = _io_out_s_add_T_5; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_add_rs2 = _io_out_s_add_T_6; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_add_rs3 = _io_out_s_add_T_7; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_add_bits; // @[RVC.scala:21:19] assign io_out_s_add_bits = {7'h0, _io_out_s_add_T_3}; // @[RVC.scala:21:19, :22:14, :134:25] wire [9:0] io_out_s_jr_hi_hi = {_io_out_s_jr_T, _io_out_s_jr_T_1}; // @[RVC.scala:32:14, :33:13, :135:19] wire [12:0] io_out_s_jr_hi = {io_out_s_jr_hi_hi, 3'h0}; // @[RVC.scala:135:19] wire [24:0] io_out_s_jr = {io_out_s_jr_hi, 12'h67}; // @[RVC.scala:135:19] wire [17:0] _io_out_s_reserved_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29] wire [17:0] _io_out_s_ebreak_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29, :140:27] wire [24:0] io_out_s_reserved = {_io_out_s_reserved_T, 7'h1F}; // @[RVC.scala:136:{25,29}] wire _io_out_s_jr_reserved_T_1 = \|_io_out_s_jr_reserved_T; // @[RVC.scala:33:13, :137:37] wire [24:0] _io_out_s_jr_reserved_T_2 = _io_out_s_jr_reserved_T_1 ? io_out_s_jr : io_out_s_reserved; // @[RVC.scala:135:19, :136:25, :137:{33,37}] wire [4:0] io_out_s_jr_reserved_rs1 = _io_out_s_jr_reserved_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_jr_reserved_rs2 = _io_out_s_jr_reserved_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_jr_reserved_rs3 = _io_out_s_jr_reserved_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_jr_reserved_bits; // @[RVC.scala:21:19] assign io_out_s_jr_reserved_bits = {7'h0, _io_out_s_jr_reserved_T_2}; // @[RVC.scala:21:19, :22:14, :137:33] wire _io_out_s_jr_mv_T_1 = \|_io_out_s_jr_mv_T; // @[RVC.scala:32:14, :138:27] wire [31:0] io_out_s_jr_mv_bits = _io_out_s_jr_mv_T_1 ? io_out_s_mv_bits : io_out_s_jr_reserved_bits; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rd = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rd : 5'h0; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs1 = _io_out_s_jr_mv_T_1 ? 5'h0 : io_out_s_jr_reserved_rs1; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs2 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs2 : io_out_s_jr_reserved_rs2; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs3 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs3 : io_out_s_jr_reserved_rs3; // @[RVC.scala:21:19, :138:{22,27}] wire [9:0] io_out_s_jalr_hi_hi = {_io_out_s_jalr_T, _io_out_s_jalr_T_1}; // @[RVC.scala:32:14, :33:13, :139:21] wire [12:0] io_out_s_jalr_hi = {io_out_s_jalr_hi_hi, 3'h0}; // @[RVC.scala:139:21] wire [24:0] io_out_s_jalr = {io_out_s_jalr_hi, 12'hE7}; // @[RVC.scala:139:21] wire [24:0] _io_out_s_ebreak_T_1 = {_io_out_s_ebreak_T, 7'h73}; // @[RVC.scala:140:{23,27}] wire [24:0] io_out_s_ebreak = {_io_out_s_ebreak_T_1[24:21], _io_out_s_ebreak_T_1[20:0] \| 21'h100000}; // @[RVC.scala:140:{23,46}] wire _io_out_s_jalr_ebreak_T_1 = \|_io_out_s_jalr_ebreak_T; // @[RVC.scala:33:13, :141:37] wire [24:0] _io_out_s_jalr_ebreak_T_2 = _io_out_s_jalr_ebreak_T_1 ? io_out_s_jalr : io_out_s_ebreak; // @[RVC.scala:139:21, :140:46, :141:{33,37}] wire [4:0] io_out_s_jalr_ebreak_rs1 = _io_out_s_jalr_ebreak_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_jalr_ebreak_rs2 = _io_out_s_jalr_ebreak_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_jalr_ebreak_rs3 = _io_out_s_jalr_ebreak_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19] assign io_out_s_jalr_ebreak_bits = {7'h0, _io_out_s_jalr_ebreak_T_2}; // @[RVC.scala:21:19, :22:14, :141:33] wire _io_out_s_jalr_add_T_1 = \|_io_out_s_jalr_add_T; // @[RVC.scala:32:14, :142:30] wire [31:0] io_out_s_jalr_add_bits = _io_out_s_jalr_add_T_1 ? io_out_s_add_bits : io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rd = _io_out_s_jalr_add_T_1 ? io_out_s_add_rd : 5'h1; // @[package.scala:39:86] wire [4:0] io_out_s_jalr_add_rs1 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs1 : io_out_s_jalr_ebreak_rs1; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rs2 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs2 : io_out_s_jalr_ebreak_rs2; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rs3 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs3 : io_out_s_jalr_ebreak_rs3; // @[RVC.scala:21:19, :142:{25,30}] wire [31:0] io_out_s_20_bits = _io_out_s_T_410 ? io_out_s_jalr_add_bits : io_out_s_jr_mv_bits; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rd = _io_out_s_T_410 ? io_out_s_jalr_add_rd : io_out_s_jr_mv_rd; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs1 = _io_out_s_T_410 ? io_out_s_jalr_add_rs1 : io_out_s_jr_mv_rs1; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs2 = _io_out_s_T_410 ? io_out_s_jalr_add_rs2 : io_out_s_jr_mv_rs2; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs3 = _io_out_s_T_410 ? io_out_s_jalr_add_rs3 : io_out_s_jr_mv_rs3; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [5:0] io_out_s_hi_51 = {_io_out_s_T_411, _io_out_s_T_412}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_413 = {io_out_s_hi_51, 3'h0}; // @[RVC.scala:40:20] wire [3:0] _io_out_s_T_414 = _io_out_s_T_413[8:5]; // @[RVC.scala:40:20, :124:34] wire [5:0] io_out_s_hi_52 = {_io_out_s_T_416, _io_out_s_T_417}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_418 = {io_out_s_hi_52, 3'h0}; // @[RVC.scala:40:20] wire [4:0] _io_out_s_T_419 = _io_out_s_T_418[4:0]; // @[RVC.scala:40:20, :124:66] wire [7:0] io_out_s_lo_hi_20 = {3'h3, _io_out_s_T_419}; // @[RVC.scala:124:{25,66}] wire [14:0] io_out_s_lo_45 = {io_out_s_lo_hi_20, 7'h27}; // @[RVC.scala:124:25] wire [8:0] io_out_s_hi_hi_37 = {_io_out_s_T_414, _io_out_s_T_415}; // @[RVC.scala:32:14, :124:{25,34}] wire [13:0] io_out_s_hi_53 = {io_out_s_hi_hi_37, 5'h2}; // @[package.scala:39:86] wire [28:0] _io_out_s_T_420 = {io_out_s_hi_53, io_out_s_lo_45}; // @[RVC.scala:124:25] wire [4:0] io_out_s_21_rd = _io_out_s_T_421; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_21_rs2 = _io_out_s_T_422; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_21_rs3 = _io_out_s_T_423; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_21_bits; // @[RVC.scala:21:19] assign io_out_s_21_bits = {3'h0, _io_out_s_T_420}; // @[RVC.scala:21:19, :22:14, :124:25] wire [1:0] _io_out_s_T_424 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7] wire [1:0] _io_out_s_T_429 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7] wire [3:0] _io_out_s_T_425 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7] wire [3:0] _io_out_s_T_430 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7] wire [5:0] io_out_s_hi_54 = {_io_out_s_T_424, _io_out_s_T_425}; // @[RVC.scala:39:{20,22,30}] wire [7:0] _io_out_s_T_426 = {io_out_s_hi_54, 2'h0}; // @[RVC.scala:39:20] wire [2:0] _io_out_s_T_427 = _io_out_s_T_426[7:5]; // @[RVC.scala:39:20, :123:33] wire [5:0] io_out_s_hi_55 = {_io_out_s_T_429, _io_out_s_T_430}; // @[RVC.scala:39:{20,22,30}] wire [7:0] _io_out_s_T_431 = {io_out_s_hi_55, 2'h0}; // @[RVC.scala:39:20] wire [4:0] _io_out_s_T_432 = _io_out_s_T_431[4:0]; // @[RVC.scala:39:20, :123:65] wire [7:0] io_out_s_lo_hi_21 = {3'h2, _io_out_s_T_432}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_46 = {io_out_s_lo_hi_21, 7'h23}; // @[RVC.scala:123:24] wire [7:0] io_out_s_hi_hi_38 = {_io_out_s_T_427, _io_out_s_T_428}; // @[RVC.scala:32:14, :123:{24,33}] wire [12:0] io_out_s_hi_56 = {io_out_s_hi_hi_38, 5'h2}; // @[package.scala:39:86] wire [27:0] _io_out_s_T_433 = {io_out_s_hi_56, io_out_s_lo_46}; // @[RVC.scala:123:24] wire [4:0] io_out_s_22_rd = _io_out_s_T_434; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_22_rs2 = _io_out_s_T_435; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_22_rs3 = _io_out_s_T_436; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_22_bits; // @[RVC.scala:21:19] assign io_out_s_22_bits = {4'h0, _io_out_s_T_433}; // @[RVC.scala:21:19, :22:14, :123:24] wire [5:0] io_out_s_hi_57 = {_io_out_s_T_437, _io_out_s_T_438}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_439 = {io_out_s_hi_57, 3'h0}; // @[RVC.scala:40:20] wire [3:0] _io_out_s_T_440 = _io_out_s_T_439[8:5]; // @[RVC.scala:40:20, :122:33] wire [5:0] io_out_s_hi_58 = {_io_out_s_T_442, _io_out_s_T_443}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_444 = {io_out_s_hi_58, 3'h0}; // @[RVC.scala:40:20] wire [4:0] _io_out_s_T_445 = _io_out_s_T_444[4:0]; // @[RVC.scala:40:20, :122:65] wire [7:0] io_out_s_lo_hi_22 = {3'h3, _io_out_s_T_445}; // @[RVC.scala:122:{24,65}] wire [14:0] io_out_s_lo_47 = {io_out_s_lo_hi_22, 7'h23}; // @[RVC.scala:122:24] wire [8:0] io_out_s_hi_hi_39 = {_io_out_s_T_440, _io_out_s_T_441}; // @[RVC.scala:32:14, :122:{24,33}] wire [13:0] io_out_s_hi_59 = {io_out_s_hi_hi_39, 5'h2}; // @[package.scala:39:86] wire [28:0] _io_out_s_T_446 = {io_out_s_hi_59, io_out_s_lo_47}; // @[RVC.scala:122:24] wire [4:0] io_out_s_23_rd = _io_out_s_T_447; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_23_rs2 = _io_out_s_T_448; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_23_rs3 = _io_out_s_T_449; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_23_bits; // @[RVC.scala:21:19] assign io_out_s_23_bits = {3'h0, _io_out_s_T_446}; // @[RVC.scala:21:19, :22:14, :122:24] wire [4:0] io_out_s_24_rd = _io_out_s_T_450; // @[RVC.scala:20:36, :21:19] wire [4:0] _io_out_s_T_451 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_455 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_459 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_463 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_467 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_471 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_475 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_479 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] io_out_s_24_rs1 = _io_out_s_T_451; // @[RVC.scala:20:57, :21:19] wire [4:0] _io_out_s_T_452 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_456 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_460 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_464 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_468 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_472 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_476 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_480 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] io_out_s_24_rs2 = _io_out_s_T_452; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_24_rs3 = _io_out_s_T_453; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_25_rd = _io_out_s_T_454; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_25_rs1 = _io_out_s_T_455; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_25_rs2 = _io_out_s_T_456; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_25_rs3 = _io_out_s_T_457; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_26_rd = _io_out_s_T_458; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_26_rs1 = _io_out_s_T_459; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_26_rs2 = _io_out_s_T_460; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_26_rs3 = _io_out_s_T_461; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_27_rd = _io_out_s_T_462; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_27_rs1 = _io_out_s_T_463; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_27_rs2 = _io_out_s_T_464; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_27_rs3 = _io_out_s_T_465; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_28_rd = _io_out_s_T_466; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_28_rs1 = _io_out_s_T_467; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_28_rs2 = _io_out_s_T_468; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_28_rs3 = _io_out_s_T_469; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_29_rd = _io_out_s_T_470; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_29_rs1 = _io_out_s_T_471; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_29_rs2 = _io_out_s_T_472; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_29_rs3 = _io_out_s_T_473; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_30_rd = _io_out_s_T_474; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_30_rs1 = _io_out_s_T_475; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_30_rs2 = _io_out_s_T_476; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_30_rs3 = _io_out_s_T_477; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_31_rd = _io_out_s_T_478; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_31_rs1 = _io_out_s_T_479; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_31_rs2 = _io_out_s_T_480; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_31_rs3 = _io_out_s_T_481; // @[RVC.scala:20:101, :21:19] wire [2:0] _io_out_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :190:7] wire [2:0] _io_ill_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :186:20, :190:7] wire [4:0] _io_out_T_2 = {_io_out_T, _io_out_T_1}; // @[RVC.scala:154:{10,12,20}] wire _io_out_T_3 = _io_out_T_2 == 5'h1; // @[package.scala:39:86] wire [31:0] _io_out_T_4_bits = _io_out_T_3 ? io_out_s_1_bits : io_out_s_0_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rd = _io_out_T_3 ? io_out_s_1_rd : io_out_s_0_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs1 = _io_out_T_3 ? io_out_s_1_rs1 : 5'h2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs2 = _io_out_T_3 ? io_out_s_1_rs2 : io_out_s_0_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs3 = _io_out_T_3 ? io_out_s_1_rs3 : io_out_s_0_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_5 = _io_out_T_2 == 5'h2; // @[package.scala:39:86] wire [31:0] _io_out_T_6_bits = _io_out_T_5 ? io_out_s_2_bits : _io_out_T_4_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rd = _io_out_T_5 ? io_out_s_2_rd : _io_out_T_4_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs1 = _io_out_T_5 ? io_out_s_2_rs1 : _io_out_T_4_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs2 = _io_out_T_5 ? io_out_s_2_rs2 : _io_out_T_4_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs3 = _io_out_T_5 ? io_out_s_2_rs3 : _io_out_T_4_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_7 = _io_out_T_2 == 5'h3; // @[package.scala:39:86] wire [31:0] _io_out_T_8_bits = _io_out_T_7 ? io_out_s_3_bits : _io_out_T_6_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rd = _io_out_T_7 ? io_out_s_3_rd : _io_out_T_6_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs1 = _io_out_T_7 ? io_out_s_3_rs1 : _io_out_T_6_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs2 = _io_out_T_7 ? io_out_s_3_rs2 : _io_out_T_6_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs3 = _io_out_T_7 ? io_out_s_3_rs3 : _io_out_T_6_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_9 = _io_out_T_2 == 5'h4; // @[package.scala:39:86] wire [31:0] _io_out_T_10_bits = _io_out_T_9 ? io_out_s_4_bits : _io_out_T_8_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rd = _io_out_T_9 ? io_out_s_4_rd : _io_out_T_8_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs1 = _io_out_T_9 ? io_out_s_4_rs1 : _io_out_T_8_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs2 = _io_out_T_9 ? io_out_s_4_rs2 : _io_out_T_8_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs3 = _io_out_T_9 ? io_out_s_4_rs3 : _io_out_T_8_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_11 = _io_out_T_2 == 5'h5; // @[package.scala:39:86] wire [31:0] _io_out_T_12_bits = _io_out_T_11 ? io_out_s_5_bits : _io_out_T_10_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rd = _io_out_T_11 ? io_out_s_5_rd : _io_out_T_10_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs1 = _io_out_T_11 ? io_out_s_5_rs1 : _io_out_T_10_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs2 = _io_out_T_11 ? io_out_s_5_rs2 : _io_out_T_10_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs3 = _io_out_T_11 ? io_out_s_5_rs3 : _io_out_T_10_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_13 = _io_out_T_2 == 5'h6; // @[package.scala:39:86] wire [31:0] _io_out_T_14_bits = _io_out_T_13 ? io_out_s_6_bits : _io_out_T_12_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rd = _io_out_T_13 ? io_out_s_6_rd : _io_out_T_12_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs1 = _io_out_T_13 ? io_out_s_6_rs1 : _io_out_T_12_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs2 = _io_out_T_13 ? io_out_s_6_rs2 : _io_out_T_12_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs3 = _io_out_T_13 ? io_out_s_6_rs3 : _io_out_T_12_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_15 = _io_out_T_2 == 5'h7; // @[package.scala:39:86] wire [31:0] _io_out_T_16_bits = _io_out_T_15 ? io_out_s_7_bits : _io_out_T_14_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rd = _io_out_T_15 ? io_out_s_7_rd : _io_out_T_14_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs1 = _io_out_T_15 ? io_out_s_7_rs1 : _io_out_T_14_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs2 = _io_out_T_15 ? io_out_s_7_rs2 : _io_out_T_14_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs3 = _io_out_T_15 ? io_out_s_7_rs3 : _io_out_T_14_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_17 = _io_out_T_2 == 5'h8; // @[package.scala:39:86] wire [31:0] _io_out_T_18_bits = _io_out_T_17 ? io_out_s_8_bits : _io_out_T_16_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rd = _io_out_T_17 ? io_out_s_8_rd : _io_out_T_16_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs1 = _io_out_T_17 ? io_out_s_8_rs1 : _io_out_T_16_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs2 = _io_out_T_17 ? io_out_s_8_rs2 : _io_out_T_16_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs3 = _io_out_T_17 ? io_out_s_8_rs3 : _io_out_T_16_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_19 = _io_out_T_2 == 5'h9; // @[package.scala:39:86] wire [31:0] _io_out_T_20_bits = _io_out_T_19 ? io_out_s_9_bits : _io_out_T_18_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rd = _io_out_T_19 ? io_out_s_9_rd : _io_out_T_18_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs1 = _io_out_T_19 ? io_out_s_9_rs1 : _io_out_T_18_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs2 = _io_out_T_19 ? io_out_s_9_rs2 : _io_out_T_18_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs3 = _io_out_T_19 ? io_out_s_9_rs3 : _io_out_T_18_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_21 = _io_out_T_2 == 5'hA; // @[package.scala:39:86] wire [31:0] _io_out_T_22_bits = _io_out_T_21 ? io_out_s_10_bits : _io_out_T_20_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rd = _io_out_T_21 ? io_out_s_10_rd : _io_out_T_20_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs1 = _io_out_T_21 ? 5'h0 : _io_out_T_20_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs2 = _io_out_T_21 ? io_out_s_10_rs2 : _io_out_T_20_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs3 = _io_out_T_21 ? io_out_s_10_rs3 : _io_out_T_20_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_23 = _io_out_T_2 == 5'hB; // @[package.scala:39:86] wire [31:0] _io_out_T_24_bits = _io_out_T_23 ? io_out_s_11_bits : _io_out_T_22_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rd = _io_out_T_23 ? io_out_s_11_rd : _io_out_T_22_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs1 = _io_out_T_23 ? io_out_s_11_rs1 : _io_out_T_22_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs2 = _io_out_T_23 ? io_out_s_11_rs2 : _io_out_T_22_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs3 = _io_out_T_23 ? io_out_s_11_rs3 : _io_out_T_22_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_25 = _io_out_T_2 == 5'hC; // @[package.scala:39:86] wire [31:0] _io_out_T_26_bits = _io_out_T_25 ? io_out_s_12_bits : _io_out_T_24_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rd = _io_out_T_25 ? io_out_s_12_rd : _io_out_T_24_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs1 = _io_out_T_25 ? io_out_s_12_rs1 : _io_out_T_24_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs2 = _io_out_T_25 ? io_out_s_12_rs2 : _io_out_T_24_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs3 = _io_out_T_25 ? io_out_s_12_rs3 : _io_out_T_24_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_27 = _io_out_T_2 == 5'hD; // @[package.scala:39:86] wire [31:0] _io_out_T_28_bits = _io_out_T_27 ? io_out_s_13_bits : _io_out_T_26_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rd = _io_out_T_27 ? 5'h0 : _io_out_T_26_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs1 = _io_out_T_27 ? io_out_s_13_rs1 : _io_out_T_26_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs2 = _io_out_T_27 ? io_out_s_13_rs2 : _io_out_T_26_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs3 = _io_out_T_27 ? io_out_s_13_rs3 : _io_out_T_26_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_29 = _io_out_T_2 == 5'hE; // @[package.scala:39:86] wire [31:0] _io_out_T_30_bits = _io_out_T_29 ? io_out_s_14_bits : _io_out_T_28_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rd = _io_out_T_29 ? io_out_s_14_rd : _io_out_T_28_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs1 = _io_out_T_29 ? io_out_s_14_rs1 : _io_out_T_28_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs2 = _io_out_T_29 ? 5'h0 : _io_out_T_28_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs3 = _io_out_T_29 ? io_out_s_14_rs3 : _io_out_T_28_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_31 = _io_out_T_2 == 5'hF; // @[package.scala:39:86] wire [31:0] _io_out_T_32_bits = _io_out_T_31 ? io_out_s_15_bits : _io_out_T_30_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rd = _io_out_T_31 ? 5'h0 : _io_out_T_30_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs1 = _io_out_T_31 ? io_out_s_15_rs1 : _io_out_T_30_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs2 = _io_out_T_31 ? 5'h0 : _io_out_T_30_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs3 = _io_out_T_31 ? io_out_s_15_rs3 : _io_out_T_30_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_33 = _io_out_T_2 == 5'h10; // @[package.scala:39:86] wire [31:0] _io_out_T_34_bits = _io_out_T_33 ? io_out_s_16_bits : _io_out_T_32_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rd = _io_out_T_33 ? io_out_s_16_rd : _io_out_T_32_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs1 = _io_out_T_33 ? io_out_s_16_rs1 : _io_out_T_32_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs2 = _io_out_T_33 ? io_out_s_16_rs2 : _io_out_T_32_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs3 = _io_out_T_33 ? io_out_s_16_rs3 : _io_out_T_32_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_35 = _io_out_T_2 == 5'h11; // @[package.scala:39:86] wire [31:0] _io_out_T_36_bits = _io_out_T_35 ? io_out_s_17_bits : _io_out_T_34_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rd = _io_out_T_35 ? io_out_s_17_rd : _io_out_T_34_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs1 = _io_out_T_35 ? 5'h2 : _io_out_T_34_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs2 = _io_out_T_35 ? io_out_s_17_rs2 : _io_out_T_34_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs3 = _io_out_T_35 ? io_out_s_17_rs3 : _io_out_T_34_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_37 = _io_out_T_2 == 5'h12; // @[package.scala:39:86] wire [31:0] _io_out_T_38_bits = _io_out_T_37 ? io_out_s_18_bits : _io_out_T_36_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rd = _io_out_T_37 ? io_out_s_18_rd : _io_out_T_36_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs1 = _io_out_T_37 ? 5'h2 : _io_out_T_36_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs2 = _io_out_T_37 ? io_out_s_18_rs2 : _io_out_T_36_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs3 = _io_out_T_37 ? io_out_s_18_rs3 : _io_out_T_36_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_39 = _io_out_T_2 == 5'h13; // @[package.scala:39:86] wire [31:0] _io_out_T_40_bits = _io_out_T_39 ? io_out_s_19_bits : _io_out_T_38_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rd = _io_out_T_39 ? io_out_s_19_rd : _io_out_T_38_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs1 = _io_out_T_39 ? 5'h2 : _io_out_T_38_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs2 = _io_out_T_39 ? io_out_s_19_rs2 : _io_out_T_38_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs3 = _io_out_T_39 ? io_out_s_19_rs3 : _io_out_T_38_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_41 = _io_out_T_2 == 5'h14; // @[package.scala:39:86] wire [31:0] _io_out_T_42_bits = _io_out_T_41 ? io_out_s_20_bits : _io_out_T_40_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rd = _io_out_T_41 ? io_out_s_20_rd : _io_out_T_40_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs1 = _io_out_T_41 ? io_out_s_20_rs1 : _io_out_T_40_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs2 = _io_out_T_41 ? io_out_s_20_rs2 : _io_out_T_40_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs3 = _io_out_T_41 ? io_out_s_20_rs3 : _io_out_T_40_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_43 = _io_out_T_2 == 5'h15; // @[package.scala:39:86] wire [31:0] _io_out_T_44_bits = _io_out_T_43 ? io_out_s_21_bits : _io_out_T_42_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rd = _io_out_T_43 ? io_out_s_21_rd : _io_out_T_42_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs1 = _io_out_T_43 ? 5'h2 : _io_out_T_42_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs2 = _io_out_T_43 ? io_out_s_21_rs2 : _io_out_T_42_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs3 = _io_out_T_43 ? io_out_s_21_rs3 : _io_out_T_42_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_45 = _io_out_T_2 == 5'h16; // @[package.scala:39:86] wire [31:0] _io_out_T_46_bits = _io_out_T_45 ? io_out_s_22_bits : _io_out_T_44_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rd = _io_out_T_45 ? io_out_s_22_rd : _io_out_T_44_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs1 = _io_out_T_45 ? 5'h2 : _io_out_T_44_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs2 = _io_out_T_45 ? io_out_s_22_rs2 : _io_out_T_44_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs3 = _io_out_T_45 ? io_out_s_22_rs3 : _io_out_T_44_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_47 = _io_out_T_2 == 5'h17; // @[package.scala:39:86] wire [31:0] _io_out_T_48_bits = _io_out_T_47 ? io_out_s_23_bits : _io_out_T_46_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rd = _io_out_T_47 ? io_out_s_23_rd : _io_out_T_46_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs1 = _io_out_T_47 ? 5'h2 : _io_out_T_46_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs2 = _io_out_T_47 ? io_out_s_23_rs2 : _io_out_T_46_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs3 = _io_out_T_47 ? io_out_s_23_rs3 : _io_out_T_46_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_49 = _io_out_T_2 == 5'h18; // @[package.scala:39:86] wire [31:0] _io_out_T_50_bits = _io_out_T_49 ? io_out_s_24_bits : _io_out_T_48_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rd = _io_out_T_49 ? io_out_s_24_rd : _io_out_T_48_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs1 = _io_out_T_49 ? io_out_s_24_rs1 : _io_out_T_48_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs2 = _io_out_T_49 ? io_out_s_24_rs2 : _io_out_T_48_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs3 = _io_out_T_49 ? io_out_s_24_rs3 : _io_out_T_48_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_51 = _io_out_T_2 == 5'h19; // @[package.scala:39:86] wire [31:0] _io_out_T_52_bits = _io_out_T_51 ? io_out_s_25_bits : _io_out_T_50_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rd = _io_out_T_51 ? io_out_s_25_rd : _io_out_T_50_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs1 = _io_out_T_51 ? io_out_s_25_rs1 : _io_out_T_50_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs2 = _io_out_T_51 ? io_out_s_25_rs2 : _io_out_T_50_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs3 = _io_out_T_51 ? io_out_s_25_rs3 : _io_out_T_50_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_53 = _io_out_T_2 == 5'h1A; // @[package.scala:39:86] wire [31:0] _io_out_T_54_bits = _io_out_T_53 ? io_out_s_26_bits : _io_out_T_52_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rd = _io_out_T_53 ? io_out_s_26_rd : _io_out_T_52_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs1 = _io_out_T_53 ? io_out_s_26_rs1 : _io_out_T_52_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs2 = _io_out_T_53 ? io_out_s_26_rs2 : _io_out_T_52_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs3 = _io_out_T_53 ? io_out_s_26_rs3 : _io_out_T_52_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_55 = _io_out_T_2 == 5'h1B; // @[package.scala:39:86] wire [31:0] _io_out_T_56_bits = _io_out_T_55 ? io_out_s_27_bits : _io_out_T_54_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rd = _io_out_T_55 ? io_out_s_27_rd : _io_out_T_54_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs1 = _io_out_T_55 ? io_out_s_27_rs1 : _io_out_T_54_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs2 = _io_out_T_55 ? io_out_s_27_rs2 : _io_out_T_54_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs3 = _io_out_T_55 ? io_out_s_27_rs3 : _io_out_T_54_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_57 = _io_out_T_2 == 5'h1C; // @[package.scala:39:86] wire [31:0] _io_out_T_58_bits = _io_out_T_57 ? io_out_s_28_bits : _io_out_T_56_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rd = _io_out_T_57 ? io_out_s_28_rd : _io_out_T_56_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs1 = _io_out_T_57 ? io_out_s_28_rs1 : _io_out_T_56_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs2 = _io_out_T_57 ? io_out_s_28_rs2 : _io_out_T_56_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs3 = _io_out_T_57 ? io_out_s_28_rs3 : _io_out_T_56_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_59 = _io_out_T_2 == 5'h1D; // @[package.scala:39:86] wire [31:0] _io_out_T_60_bits = _io_out_T_59 ? io_out_s_29_bits : _io_out_T_58_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rd = _io_out_T_59 ? io_out_s_29_rd : _io_out_T_58_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs1 = _io_out_T_59 ? io_out_s_29_rs1 : _io_out_T_58_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs2 = _io_out_T_59 ? io_out_s_29_rs2 : _io_out_T_58_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs3 = _io_out_T_59 ? io_out_s_29_rs3 : _io_out_T_58_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_61 = _io_out_T_2 == 5'h1E; // @[package.scala:39:86] wire [31:0] _io_out_T_62_bits = _io_out_T_61 ? io_out_s_30_bits : _io_out_T_60_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rd = _io_out_T_61 ? io_out_s_30_rd : _io_out_T_60_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs1 = _io_out_T_61 ? io_out_s_30_rs1 : _io_out_T_60_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs2 = _io_out_T_61 ? io_out_s_30_rs2 : _io_out_T_60_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs3 = _io_out_T_61 ? io_out_s_30_rs3 : _io_out_T_60_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_63 = &_io_out_T_2; // @[package.scala:39:86] assign _io_out_T_64_bits = _io_out_T_63 ? io_out_s_31_bits : _io_out_T_62_bits; // @[package.scala:39:{76,86}] assign _io_out_T_64_rd = _io_out_T_63 ? io_out_s_31_rd : _io_out_T_62_rd; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs1 = _io_out_T_63 ? io_out_s_31_rs1 : _io_out_T_62_rs1; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs2 = _io_out_T_63 ? io_out_s_31_rs2 : _io_out_T_62_rs2; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs3 = _io_out_T_63 ? io_out_s_31_rs3 : _io_out_T_62_rs3; // @[package.scala:39:{76,86}] assign io_out_bits_0 = _io_out_T_64_bits; // @[package.scala:39:76] assign io_out_rd = _io_out_T_64_rd; // @[package.scala:39:76] assign io_out_rs1 = _io_out_T_64_rs1; // @[package.scala:39:76] assign io_out_rs2 = _io_out_T_64_rs2; // @[package.scala:39:76] assign io_out_rs3 = _io_out_T_64_rs3; // @[package.scala:39:76] wire [10:0] _io_ill_s_T = io_in_0[12:2]; // @[RVC.scala:158:19, :190:7] wire [10:0] _io_ill_s_T_13 = io_in_0[12:2]; // @[RVC.scala:158:19, :177:21, :190:7] wire _io_ill_s_T_1 = \|_io_ill_s_T; // @[RVC.scala:158:{19,27}] wire io_ill_s_0 = ~_io_ill_s_T_1; // @[RVC.scala:158:{16,27}] wire io_ill_s_9 = _io_ill_s_T_2 == 5'h0; // @[RVC.scala:33:13, :167:47] wire _io_ill_s_T_5 = \|_io_ill_s_T_4; // @[RVC.scala:168:{27,34}] wire _io_ill_s_T_6 = _io_ill_s_T_3 \| _io_ill_s_T_5; // @[RVC.scala:168:{19,24,34}] wire io_ill_s_11 = ~_io_ill_s_T_6; // @[RVC.scala:168:{16,24}] wire _io_ill_s_T_8 = &_io_ill_s_T_7; // @[RVC.scala:169:{22,31}] wire _io_ill_s_T_10 = _io_ill_s_T_9; // @[RVC.scala:169:{69,73}] wire io_ill_s_12 = _io_ill_s_T_8 & _io_ill_s_T_10; // @[RVC.scala:169:{31,36,73}] wire io_ill_s_18 = _io_ill_s_T_11 == 5'h0; // @[RVC.scala:33:13, :175:18] wire io_ill_s_19 = _io_ill_s_T_12 == 5'h0; // @[RVC.scala:33:13, :175:18] wire _io_ill_s_T_14 = \|_io_ill_s_T_13; // @[RVC.scala:177:{21,29}] wire io_ill_s_20 = ~_io_ill_s_T_14; // @[RVC.scala:177:{18,29}] wire [4:0] _io_ill_T_2 = {_io_ill_T, _io_ill_T_1}; // @[RVC.scala:186:{10,12,20}] wire _io_ill_T_3 = _io_ill_T_2 == 5'h1; // @[package.scala:39:86] wire _io_ill_T_4 = ~_io_ill_T_3 & io_ill_s_0; // @[package.scala:39:{76,86}] wire _io_ill_T_5 = _io_ill_T_2 == 5'h2; // @[package.scala:39:86] wire _io_ill_T_6 = ~_io_ill_T_5 & _io_ill_T_4; // @[package.scala:39:{76,86}] wire _io_ill_T_7 = _io_ill_T_2 == 5'h3; // @[package.scala:39:86] wire _io_ill_T_8 = ~_io_ill_T_7 & _io_ill_T_6; // @[package.scala:39:{76,86}] wire _io_ill_T_9 = _io_ill_T_2 == 5'h4; // @[package.scala:39:86] wire _io_ill_T_10 = _io_ill_T_9 \| _io_ill_T_8; // @[package.scala:39:{76,86}] wire _io_ill_T_11 = _io_ill_T_2 == 5'h5; // @[package.scala:39:86] wire _io_ill_T_12 = ~_io_ill_T_11 & _io_ill_T_10; // @[package.scala:39:{76,86}] wire _io_ill_T_13 = _io_ill_T_2 == 5'h6; // @[package.scala:39:86] wire _io_ill_T_14 = ~_io_ill_T_13 & _io_ill_T_12; // @[package.scala:39:{76,86}] wire _io_ill_T_15 = _io_ill_T_2 == 5'h7; // @[package.scala:39:86] wire _io_ill_T_16 = ~_io_ill_T_15 & _io_ill_T_14; // @[package.scala:39:{76,86}] wire _io_ill_T_17 = _io_ill_T_2 == 5'h8; // @[package.scala:39:86] wire _io_ill_T_18 = ~_io_ill_T_17 & _io_ill_T_16; // @[package.scala:39:{76,86}] wire _io_ill_T_19 = _io_ill_T_2 == 5'h9; // @[package.scala:39:86] wire _io_ill_T_20 = _io_ill_T_19 ? io_ill_s_9 : _io_ill_T_18; // @[package.scala:39:{76,86}] wire _io_ill_T_21 = _io_ill_T_2 == 5'hA; // @[package.scala:39:86] wire _io_ill_T_22 = ~_io_ill_T_21 & _io_ill_T_20; // @[package.scala:39:{76,86}] wire _io_ill_T_23 = _io_ill_T_2 == 5'hB; // @[package.scala:39:86] wire _io_ill_T_24 = _io_ill_T_23 ? io_ill_s_11 : _io_ill_T_22; // @[package.scala:39:{76,86}] wire _io_ill_T_25 = _io_ill_T_2 == 5'hC; // @[package.scala:39:86] wire _io_ill_T_26 = _io_ill_T_25 ? io_ill_s_12 : _io_ill_T_24; // @[package.scala:39:{76,86}] wire _io_ill_T_27 = _io_ill_T_2 == 5'hD; // @[package.scala:39:86] wire _io_ill_T_28 = ~_io_ill_T_27 & _io_ill_T_26; // @[package.scala:39:{76,86}] wire _io_ill_T_29 = _io_ill_T_2 == 5'hE; // @[package.scala:39:86] wire _io_ill_T_30 = ~_io_ill_T_29 & _io_ill_T_28; // @[package.scala:39:{76,86}] wire _io_ill_T_31 = _io_ill_T_2 == 5'hF; // @[package.scala:39:86] wire _io_ill_T_32 = ~_io_ill_T_31 & _io_ill_T_30; // @[package.scala:39:{76,86}] wire _io_ill_T_33 = _io_ill_T_2 == 5'h10; // @[package.scala:39:86] wire _io_ill_T_34 = ~_io_ill_T_33 & _io_ill_T_32; // @[package.scala:39:{76,86}] wire _io_ill_T_35 = _io_ill_T_2 == 5'h11; // @[package.scala:39:86] wire _io_ill_T_36 = ~_io_ill_T_35 & _io_ill_T_34; // @[package.scala:39:{76,86}] wire _io_ill_T_37 = _io_ill_T_2 == 5'h12; // @[package.scala:39:86] wire _io_ill_T_38 = _io_ill_T_37 ? io_ill_s_18 : _io_ill_T_36; // @[package.scala:39:{76,86}] wire _io_ill_T_39 = _io_ill_T_2 == 5'h13; // @[package.scala:39:86] wire _io_ill_T_40 = _io_ill_T_39 ? io_ill_s_19 : _io_ill_T_38; // @[package.scala:39:{76,86}] wire _io_ill_T_41 = _io_ill_T_2 == 5'h14; // @[package.scala:39:86] wire _io_ill_T_42 = _io_ill_T_41 ? io_ill_s_20 : _io_ill_T_40; // @[package.scala:39:{76,86}] wire _io_ill_T_43 = _io_ill_T_2 == 5'h15; // @[package.scala:39:86] wire _io_ill_T_44 = ~_io_ill_T_43 & _io_ill_T_42; // @[package.scala:39:{76,86}] wire _io_ill_T_45 = _io_ill_T_2 == 5'h16; // @[package.scala:39:86] wire _io_ill_T_46 = ~_io_ill_T_45 & _io_ill_T_44; // @[package.scala:39:{76,86}] wire _io_ill_T_47 = _io_ill_T_2 == 5'h17; // @[package.scala:39:86] wire _io_ill_T_48 = ~_io_ill_T_47 & _io_ill_T_46; // @[package.scala:39:{76,86}] wire _io_ill_T_49 = _io_ill_T_2 == 5'h18; // @[package.scala:39:86] wire _io_ill_T_50 = ~_io_ill_T_49 & _io_ill_T_48; // @[package.scala:39:{76,86}] wire _io_ill_T_51 = _io_ill_T_2 == 5'h19; // @[package.scala:39:86] wire _io_ill_T_52 = ~_io_ill_T_51 & _io_ill_T_50; // @[package.scala:39:{76,86}] wire _io_ill_T_53 = _io_ill_T_2 == 5'h1A; // @[package.scala:39:86] wire _io_ill_T_54 = ~_io_ill_T_53 & _io_ill_T_52; // @[package.scala:39:{76,86}] wire _io_ill_T_55 = _io_ill_T_2 == 5'h1B; // @[package.scala:39:86] wire _io_ill_T_56 = ~_io_ill_T_55 & _io_ill_T_54; // @[package.scala:39:{76,86}] wire _io_ill_T_57 = _io_ill_T_2 == 5'h1C; // @[package.scala:39:86] wire _io_ill_T_58 = ~_io_ill_T_57 & _io_ill_T_56; // @[package.scala:39:{76,86}] wire _io_ill_T_59 = _io_ill_T_2 == 5'h1D; // @[package.scala:39:86] wire _io_ill_T_60 = ~_io_ill_T_59 & _io_ill_T_58; // @[package.scala:39:{76,86}] wire _io_ill_T_61 = _io_ill_T_2 == 5'h1E; // @[package.scala:39:86] wire _io_ill_T_62 = ~_io_ill_T_61 & _io_ill_T_60; // @[package.scala:39:{76,86}] wire _io_ill_T_63 = &_io_ill_T_2; // @[package.scala:39:86] assign _io_ill_T_64 = ~_io_ill_T_63 & _io_ill_T_62; // @[package.scala:39:{76,86}] assign io_ill = _io_ill_T_64; // @[package.scala:39:76] assign io_out_bits = io_out_bits_0; // @[RVC.scala:190:7] assign io_rvc = io_rvc_0; // @[RVC.scala:190:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_9( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_109 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_110 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_111 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_112 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_26( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_242 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_243 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_244 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_245 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File tage.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f3_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)l, histLength)-1, il) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry))) val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f3_resp(w).valid := RegNext(s2_req_rhits(w)) io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w))) io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr) } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) table.write( Mux(doing_reset, reset_idx , update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))), Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools ) val update_hi_wdata = Wire(Vec(bankWidth, Bool())) hi_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)), Mux(doing_reset \|\| doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata), Mux(doing_reset \|\| doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val update_lo_wdata = Wire(Vec(bankWidth, Bool())) lo_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)), Mux(doing_reset \|\| doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata), Mux(doing_reset \|\| doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_\|\|_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag update_hi_wdata(w) := io.update_u(w)(1) update_lo_wdata(w) := io.update_u(w)(0) } when (io.update_mask.reduce(_\|\|_)) { when (wrbypass_hits.reduce(_\|\|_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048 ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(io.f0_pc) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f3_resps = VecInit(tables.map(_.io.f3_resp)) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var altpred = io.resp_in(0).f3(w).taken val final_altpred = WireInit(io.resp_in(0).f3(w).taken) var provided = false.B var provider = 0.U io.resp.f3(w).taken := io.resp_in(0).f3(w).taken for (i <- 0 until tageNTables) { val hit = f3_resps(i)(w).valid val ctr = f3_resps(i)(w).bits.ctr when (hit) { io.resp.f3(w).taken := Mux(ctr === 3.U \|\| ctr === 4.U, altpred, ctr(2)) final_altpred := altpred } provided = provided \|\| hit provider = Mux(hit, i.U, provider) altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred) } f3_meta.provider(w).valid := provided f3_meta.provider(w).bits := provider f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }	module lo_us_20( // @[tage.scala:90:27] input [7:0] R0_addr, input R0_en, input R0_clk, output [3:0] R0_data, input [7:0] W0_addr, input W0_clk, input [3:0] W0_data, input [3:0] W0_mask ); hi_us_0_ext hi_us_0_ext ( // @[tage.scala:90:27] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (1'h1), // @[tage.scala:90:27] .W0_clk (W0_clk), .W0_data (W0_data), .W0_mask (W0_mask) ); // @[tage.scala:90:27] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module InputUnit_84( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output io_debug_va_stall, // @[InputUnit.scala:170:14] output io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [1:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_1_0; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_0_0; // @[MixedVec.scala:116:9] wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_\|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel \| (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens \| chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_\|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) \| 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_\|\|_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_\|\|_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }	module SwitchArbiter_90( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_3_ready, // @[SwitchAllocator.scala:18:14] input io_in_3_valid, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [3:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [3:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [3:0] unassigned = {io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [3:0] mask; // @[SwitchAllocator.scala:27:21] wire [3:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [7:0] sel = _sel_T_1[0] ? 8'h1 : _sel_T_1[1] ? 8'h2 : _sel_T_1[2] ? 8'h4 : _sel_T_1[3] ? 8'h8 : unassigned[0] ? 8'h10 : unassigned[1] ? 8'h20 : unassigned[2] ? 8'h40 : {unassigned[3], 7'h0}; // @[OneHot.scala:85:71] wire [3:0] in_valids = {io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [3:0] chosen = (\|(in_valids & lock_0)) ? lock_0 : sel[3:0] \| sel[7:4]; // @[Mux.scala:50:70] wire [3:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire [2:0] _GEN = chosen[2:0] \| chosen[3:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [1:0] _GEN_0 = _GEN[1:0] \| chosen[3:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 4'h0; // @[SwitchAllocator.scala:24:38] mask <= 4'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (\|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_3_bits_tail, io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (\|_io_out_0_valid_T) ? {chosen[3], _GEN[2], _GEN_0[1], _GEN_0[0] \| chosen[3]} : (&mask) ? 4'h0 : {mask[2:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncQueueSource_Phit_19( // @[AsyncQueue.scala:70:7] input clock, // @[AsyncQueue.scala:70:7] input reset, // @[AsyncQueue.scala:70:7] output io_enq_ready, // @[AsyncQueue.scala:73:14] input io_enq_valid, // @[AsyncQueue.scala:73:14] input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:73:14] input [3:0] io_async_ridx, // @[AsyncQueue.scala:73:14] output [3:0] io_async_widx, // @[AsyncQueue.scala:73:14] input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14] input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14] ); wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30] wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32] wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:70:7] wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_ridx_0 = io_async_ridx; // @[AsyncQueue.scala:70:7] wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid; // @[AsyncQueue.scala:70:7] wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n; // @[AsyncQueue.scala:70:7] wire _widx_T = reset; // @[AsyncQueue.scala:83:30] wire _ready_reg_T = reset; // @[AsyncQueue.scala:90:35] wire _widx_reg_T = reset; // @[AsyncQueue.scala:93:34] wire _source_valid_0_reset_T = reset; // @[AsyncQueue.scala:107:36] wire _source_valid_1_reset_T = reset; // @[AsyncQueue.scala:108:36] wire _sink_extend_reset_T = reset; // @[AsyncQueue.scala:109:36] wire _sink_valid_reset_T = reset; // @[AsyncQueue.scala:110:35] wire _io_async_safe_source_reset_n_T = reset; // @[AsyncQueue.scala:123:34] wire _io_enq_ready_T; // @[AsyncQueue.scala:91:29] wire _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:123:27] wire io_enq_ready_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_0_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_1_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_2_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_3_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_4_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_5_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_6_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_7_phit_0; // @[AsyncQueue.scala:70:7] wire io_async_safe_widx_valid_0; // @[AsyncQueue.scala:70:7] wire io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_widx_0; // @[AsyncQueue.scala:70:7] wire sink_ready; // @[AsyncQueue.scala:81:28] reg [31:0] mem_0_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_phit_0 = mem_0_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_1_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_phit_0 = mem_1_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_2_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_phit_0 = mem_2_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_3_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_phit_0 = mem_3_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_4_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_phit_0 = mem_4_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_5_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_phit_0 = mem_5_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_6_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_phit_0 = mem_6_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_7_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_phit_0 = mem_7_phit; // @[AsyncQueue.scala:70:7, :82:16] wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala:81:28, :83:77] wire [3:0] _widx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] widx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] widx_widx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77] assign widx_incremented = _widx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _widx_T_3 = widx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] ridx; // @[ShiftReg.scala:48:24] wire [3:0] _ready_T = ridx ^ 4'hC; // @[ShiftReg.scala:48:24] wire _ready_T_1 = widx != _ready_T; // @[AsyncQueue.scala:54:17, :85:{34,44}] wire ready = sink_ready & _ready_T_1; // @[AsyncQueue.scala:81:28, :85:{26,34}] wire [2:0] _index_T = io_async_widx_0[2:0]; // @[AsyncQueue.scala:70:7, :87:52] wire _index_T_1 = io_async_widx_0[3]; // @[AsyncQueue.scala:70:7, :87:80] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:87:{80,93}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:87:{52,64,93}] reg ready_reg; // @[AsyncQueue.scala:90:56] assign _io_enq_ready_T = ready_reg & sink_ready; // @[AsyncQueue.scala:81:28, :90:56, :91:29] assign io_enq_ready_0 = _io_enq_ready_T; // @[AsyncQueue.scala:70:7, :91:29] reg [3:0] widx_gray; // @[AsyncQueue.scala:93:55] assign io_async_widx_0 = widx_gray; // @[AsyncQueue.scala:70:7, :93:55] wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46] wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T \| _source_valid_0_reset_T_1; // @[AsyncQueue.scala:107:{36,43,46}] wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2; // @[AsyncQueue.scala:107:{43,65}] wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :108:46] wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T \| _source_valid_1_reset_T_1; // @[AsyncQueue.scala:108:{36,43,46}] wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2; // @[AsyncQueue.scala:108:{43,65}] wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :109:46] wire _sink_extend_reset_T_2 = _sink_extend_reset_T \| _sink_extend_reset_T_1; // @[AsyncQueue.scala:109:{36,43,46}] wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2; // @[AsyncQueue.scala:109:{43,65}] assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T; // @[AsyncQueue.scala:123:{27,34}] assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:70:7, :123:27] always @(posedge clock) begin // @[AsyncQueue.scala:70:7] if (_widx_T_1 & index == 3'h0) // @[Decoupled.scala:51:35] mem_0_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h1) // @[Decoupled.scala:51:35] mem_1_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h2) // @[Decoupled.scala:51:35] mem_2_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h3) // @[Decoupled.scala:51:35] mem_3_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h4) // @[Decoupled.scala:51:35] mem_4_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h5) // @[Decoupled.scala:51:35] mem_5_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h6) // @[Decoupled.scala:51:35] mem_6_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & (&index)) // @[Decoupled.scala:51:35] mem_7_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] always @(posedge) always @(posedge clock or posedge _widx_T) begin // @[AsyncQueue.scala:70:7, :83:30] if (_widx_T) // @[AsyncQueue.scala:70:7, :83:30] widx_widx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:70:7] widx_widx_bin <= widx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _ready_reg_T) begin // @[AsyncQueue.scala:70:7, :90:35] if (_ready_reg_T) // @[AsyncQueue.scala:70:7, :90:35] ready_reg <= 1'h0; // @[AsyncQueue.scala:90:56] else // @[AsyncQueue.scala:70:7] ready_reg <= ready; // @[AsyncQueue.scala:85:26, :90:56] always @(posedge, posedge) always @(posedge clock or posedge _widx_reg_T) begin // @[AsyncQueue.scala:70:7, :93:34] if (_widx_reg_T) // @[AsyncQueue.scala:70:7, :93:34] widx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :93:55] else // @[AsyncQueue.scala:70:7] widx_gray <= widx; // @[AsyncQueue.scala:54:17, :93:55] always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_61( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_33 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_37 = source_ok_uncommonBits_5 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_38 = _source_ok_T_36 & _source_ok_T_37; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire _source_ok_T_42 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_51 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_52 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_54 = _source_ok_T_53 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_60 = _source_ok_T_59 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_66 = _source_ok_T_65 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = _source_ok_T_71 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = _source_ok_T_77 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_81 = source_ok_uncommonBits_10 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_82 = _source_ok_T_80 & _source_ok_T_81; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_83; // @[Parameters.scala:1138:31] wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_89 = source_ok_uncommonBits_11 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_90 = _source_ok_T_88 & _source_ok_T_89; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_8 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_100 = _source_ok_T_99 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_101 = _source_ok_T_100 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_103 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _T_1299 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1299; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1299; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1367 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1367; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1367; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1367; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1232 = _T_1299 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1232 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1232 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1232 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1232 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1232 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1278 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1278 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1247 = _T_1367 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1247 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1247 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1247 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1343 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1343 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1325 = _T_1367 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1325 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1325 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1325 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body \|\| !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body \|\| !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) \|\| protocol.ready protocol.valid := (!is_const \|\| io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_\|\|_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink \| sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLCToNoC_7( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [7:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0; // @[package.scala:243:{46,71,76}] reg [7:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 8'h1 \| tail_beats1 == 8'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 8'h0; // @[Edges.scala:229:27] tail_counter <= 8'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0) : head_counter - 8'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 8'h0 ? tail_beats1 : tail_counter - 8'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_257( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_176( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module ClockCrossingReg_w83( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [82:0] io_d, // @[SynchronizerReg.scala:195:14] output [82:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [82:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [82:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [82:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_90( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_101 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File TSIToTileLink.scala: package testchipip.tsi import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import testchipip.serdes._ object TSI { val WIDTH = 32 // hardcoded in FESVR } class TSIIO extends SerialIO(TSI.WIDTH) object TSIIO { def apply(ser: SerialIO): TSIIO = { require(ser.w == TSI.WIDTH) val wire = Wire(new TSIIO) wire <> ser wire } } class TSIToTileLink(sourceIds: Int = 1)(implicit p: Parameters) extends LazyModule { val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( name = "serial", sourceId = IdRange(0, sourceIds)))))) lazy val module = new TSIToTileLinkModule(this) } class TSIToTileLinkModule(outer: TSIToTileLink) extends LazyModuleImp(outer) { val io = IO(new Bundle { val tsi = new TSIIO val state = Output(UInt()) }) val (mem, edge) = outer.node.out(0) require (edge.manager.minLatency > 0) val pAddrBits = edge.bundle.addressBits val wordLen = 64 val nChunksPerWord = wordLen / TSI.WIDTH val dataBits = mem.params.dataBits val beatBytes = dataBits / 8 val nChunksPerBeat = dataBits / TSI.WIDTH val byteAddrBits = log2Ceil(beatBytes) require(nChunksPerWord > 0, s"Serial interface width must be <= $wordLen") val cmd = Reg(UInt(TSI.WIDTH.W)) val addr = Reg(UInt(wordLen.W)) val len = Reg(UInt(wordLen.W)) val body = Reg(Vec(nChunksPerBeat, UInt(TSI.WIDTH.W))) val bodyValid = Reg(UInt(nChunksPerBeat.W)) val idx = Reg(UInt(log2Up(nChunksPerBeat).W)) val (cmd_read :: cmd_write :: Nil) = Enum(2) val (s_cmd :: s_addr :: s_len :: s_read_req :: s_read_data :: s_read_body :: s_write_body :: s_write_data :: s_write_ack :: Nil) = Enum(9) val state = RegInit(s_cmd) io.state := state io.tsi.in.ready := state.isOneOf(s_cmd, s_addr, s_len, s_write_body) io.tsi.out.valid := state === s_read_body io.tsi.out.bits := body(idx) val beatAddr = addr(pAddrBits - 1, byteAddrBits) val nextAddr = Cat(beatAddr + 1.U, 0.U(byteAddrBits.W)) val wmask = FillInterleaved(TSI.WIDTH/8, bodyValid) val addr_size = nextAddr - addr val len_size = Cat(len + 1.U, 0.U(log2Ceil(TSI.WIDTH/8).W)) val raw_size = Mux(len_size < addr_size, len_size, addr_size) val rsize = MuxLookup(raw_size, byteAddrBits.U)( (0 until log2Ceil(beatBytes)).map(i => ((1 << i).U -> i.U))) val pow2size = PopCount(raw_size) === 1.U val byteAddr = Mux(pow2size, addr(byteAddrBits - 1, 0), 0.U) val put_acquire = edge.Put( 0.U, beatAddr << byteAddrBits.U, log2Ceil(beatBytes).U, body.asUInt, wmask)._2 val get_acquire = edge.Get( 0.U, Cat(beatAddr, byteAddr), rsize)._2 mem.a.valid := state.isOneOf(s_write_data, s_read_req) mem.a.bits := Mux(state === s_write_data, put_acquire, get_acquire) mem.b.ready := false.B mem.c.valid := false.B mem.d.ready := state.isOneOf(s_write_ack, s_read_data) mem.e.valid := false.B def shiftBits(bits: UInt, idx: UInt): UInt = if (nChunksPerWord > 1) bits << Cat(idx(log2Ceil(nChunksPerWord) - 1, 0), 0.U(log2Up(TSI.WIDTH).W)) else bits def addrToIdx(addr: UInt): UInt = if (nChunksPerBeat > 1) addr(byteAddrBits - 1, log2Up(TSI.WIDTH/8)) else 0.U when (state === s_cmd && io.tsi.in.valid) { cmd := io.tsi.in.bits idx := 0.U addr := 0.U len := 0.U state := s_addr } when (state === s_addr && io.tsi.in.valid) { addr := addr \| shiftBits(io.tsi.in.bits, idx) idx := idx + 1.U when (idx === (nChunksPerWord - 1).U) { idx := 0.U state := s_len } } when (state === s_len && io.tsi.in.valid) { len := len \| shiftBits(io.tsi.in.bits, idx) idx := idx + 1.U when (idx === (nChunksPerWord - 1).U) { idx := addrToIdx(addr) when (cmd === cmd_write) { bodyValid := 0.U state := s_write_body } .elsewhen (cmd === cmd_read) { state := s_read_req } .otherwise { assert(false.B, "Bad TSI command") } } } when (state === s_read_req && mem.a.ready) { state := s_read_data } when (state === s_read_data && mem.d.valid) { body := mem.d.bits.data.asTypeOf(body) idx := addrToIdx(addr) addr := nextAddr state := s_read_body } when (state === s_read_body && io.tsi.out.ready) { idx := idx + 1.U len := len - 1.U when (len === 0.U) { state := s_cmd } .elsewhen (idx === (nChunksPerBeat - 1).U) { state := s_read_req } } when (state === s_write_body && io.tsi.in.valid) { body(idx) := io.tsi.in.bits bodyValid := bodyValid \| UIntToOH(idx) when (idx === (nChunksPerBeat - 1).U \|\| len === 0.U) { state := s_write_data } .otherwise { idx := idx + 1.U len := len - 1.U } } when (state === s_write_data && mem.a.ready) { state := s_write_ack } when (state === s_write_ack && mem.d.valid) { when (len === 0.U) { state := s_cmd } .otherwise { addr := nextAddr len := len - 1.U idx := 0.U bodyValid := 0.U state := s_write_body } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TSIToTileLink( // @[TSIToTileLink.scala:36:7] input clock, // @[TSIToTileLink.scala:36:7] input reset, // @[TSIToTileLink.scala:36:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_tsi_in_ready, // @[TSIToTileLink.scala:37:14] input io_tsi_in_valid, // @[TSIToTileLink.scala:37:14] input [31:0] io_tsi_in_bits, // @[TSIToTileLink.scala:37:14] input io_tsi_out_ready, // @[TSIToTileLink.scala:37:14] output io_tsi_out_valid, // @[TSIToTileLink.scala:37:14] output [31:0] io_tsi_out_bits, // @[TSIToTileLink.scala:37:14] output [3:0] io_state // @[TSIToTileLink.scala:37:14] ); wire auto_out_a_ready_0 = auto_out_a_ready; // @[TSIToTileLink.scala:36:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[TSIToTileLink.scala:36:7] wire [4:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_valid_0 = io_tsi_in_valid; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_in_bits_0 = io_tsi_in_bits; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_ready_0 = io_tsi_out_ready; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_a_bits_param = 3'h0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] put_acquire_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] get_acquire_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] _nodeOut_a_bits_T_1_param = 3'h0; // @[TSIToTileLink.scala:95:20] wire auto_out_a_bits_source = 1'h0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_bits_corrupt = 1'h0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _put_acquire_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_acquire_source = 1'h0; // @[Edges.scala:500:17] wire put_acquire_corrupt = 1'h0; // @[Edges.scala:500:17] wire get_acquire_source = 1'h0; // @[Edges.scala:460:17] wire get_acquire_corrupt = 1'h0; // @[Edges.scala:460:17] wire _nodeOut_a_bits_T_1_source = 1'h0; // @[TSIToTileLink.scala:95:20] wire _nodeOut_a_bits_T_1_corrupt = 1'h0; // @[TSIToTileLink.scala:95:20] wire [63:0] get_acquire_data = 64'h0; // @[Edges.scala:460:17] wire [2:0] get_acquire_opcode = 3'h4; // @[Edges.scala:460:17] wire _put_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire [3:0] put_acquire_size = 4'h3; // @[Edges.scala:500:17] wire [2:0] put_acquire_opcode = 3'h1; // @[Edges.scala:500:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[TSIToTileLink.scala:36:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[TSIToTileLink.scala:36:7] wire [4:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[TSIToTileLink.scala:36:7] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[TSIToTileLink.scala:36:7] wire _io_tsi_in_ready_T_6; // @[package.scala:81:59] wire _io_tsi_out_valid_T; // @[TSIToTileLink.scala:71:29] wire [2:0] auto_out_a_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_a_bits_size_0; // @[TSIToTileLink.scala:36:7] wire [31:0] auto_out_a_bits_address_0; // @[TSIToTileLink.scala:36:7] wire [7:0] auto_out_a_bits_mask_0; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_a_bits_data_0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_valid_0; // @[TSIToTileLink.scala:36:7] wire auto_out_d_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_valid_0; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_out_bits_0; // @[TSIToTileLink.scala:36:7] wire [3:0] io_state_0; // @[TSIToTileLink.scala:36:7] wire _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [3:0] _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[TSIToTileLink.scala:36:7] wire [31:0] _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[TSIToTileLink.scala:36:7] wire [7:0] _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[TSIToTileLink.scala:36:7] wire [63:0] _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[TSIToTileLink.scala:36:7] wire _nodeOut_d_ready_T_2; // @[package.scala:81:59] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[TSIToTileLink.scala:36:7] reg [31:0] cmd; // @[TSIToTileLink.scala:56:16] reg [63:0] addr; // @[TSIToTileLink.scala:57:17] reg [63:0] len; // @[TSIToTileLink.scala:58:16] reg [31:0] body_0; // @[TSIToTileLink.scala:59:17] reg [31:0] body_1; // @[TSIToTileLink.scala:59:17] reg [1:0] bodyValid; // @[TSIToTileLink.scala:60:22] reg idx; // @[TSIToTileLink.scala:61:16] wire _addr_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] wire _len_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] reg [3:0] state; // @[TSIToTileLink.scala:67:22] assign io_state_0 = state; // @[TSIToTileLink.scala:36:7, :67:22] wire _io_tsi_in_ready_T = state == 4'h0; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_1 = state == 4'h1; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_2 = state == 4'h2; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_3 = state == 4'h6; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_4 = _io_tsi_in_ready_T \| _io_tsi_in_ready_T_1; // @[package.scala:16:47, :81:59] wire _io_tsi_in_ready_T_5 = _io_tsi_in_ready_T_4 \| _io_tsi_in_ready_T_2; // @[package.scala:16:47, :81:59] assign _io_tsi_in_ready_T_6 = _io_tsi_in_ready_T_5 \| _io_tsi_in_ready_T_3; // @[package.scala:16:47, :81:59] assign io_tsi_in_ready_0 = _io_tsi_in_ready_T_6; // @[TSIToTileLink.scala:36:7] assign _io_tsi_out_valid_T = state == 4'h5; // @[TSIToTileLink.scala:67:22, :71:29] assign io_tsi_out_valid_0 = _io_tsi_out_valid_T; // @[TSIToTileLink.scala:36:7, :71:29] assign io_tsi_out_bits_0 = idx ? body_1 : body_0; // @[TSIToTileLink.scala:36:7, :59:17, :61:16, :72:19] wire [28:0] beatAddr = addr[31:3]; // @[TSIToTileLink.scala:57:17, :74:22] wire [29:0] _nextAddr_T = {1'h0, beatAddr} + 30'h1; // @[TSIToTileLink.scala:74:22, :75:31] wire [28:0] _nextAddr_T_1 = _nextAddr_T[28:0]; // @[TSIToTileLink.scala:75:31] wire [31:0] nextAddr = {_nextAddr_T_1, 3'h0}; // @[TSIToTileLink.scala:75:{21,31}] wire _wmask_T = bodyValid[0]; // @[TSIToTileLink.scala:60:22, :77:30] wire _wmask_T_1 = bodyValid[1]; // @[TSIToTileLink.scala:60:22, :77:30] wire [3:0] _wmask_T_2 = {4{_wmask_T}}; // @[TSIToTileLink.scala:77:30] wire [3:0] _wmask_T_3 = {4{_wmask_T_1}}; // @[TSIToTileLink.scala:77:30] wire [7:0] wmask = {_wmask_T_3, _wmask_T_2}; // @[TSIToTileLink.scala:77:30] wire [7:0] put_acquire_mask = wmask; // @[TSIToTileLink.scala:77:30] wire [64:0] _addr_size_T = {33'h0, nextAddr} - {1'h0, addr}; // @[TSIToTileLink.scala:57:17, :75:21, :78:28] wire [63:0] addr_size = _addr_size_T[63:0]; // @[TSIToTileLink.scala:78:28] wire [64:0] _GEN = {1'h0, len}; // @[TSIToTileLink.scala:58:16, :79:26] wire [64:0] _len_size_T = _GEN + 65'h1; // @[TSIToTileLink.scala:79:26] wire [63:0] _len_size_T_1 = _len_size_T[63:0]; // @[TSIToTileLink.scala:79:26] wire [65:0] len_size = {_len_size_T_1, 2'h0}; // @[TSIToTileLink.scala:79:{21,26}] wire [65:0] _GEN_0 = {2'h0, addr_size}; // @[TSIToTileLink.scala:78:28, :80:31] wire _raw_size_T = len_size < _GEN_0; // @[TSIToTileLink.scala:79:21, :80:31] wire [65:0] raw_size = _raw_size_T ? len_size : _GEN_0; // @[TSIToTileLink.scala:79:21, :80:{21,31}] wire _rsize_T = raw_size == 66'h1; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_1 = _rsize_T ? 2'h0 : 2'h3; // @[TSIToTileLink.scala:81:50] wire _rsize_T_2 = raw_size == 66'h2; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_3 = _rsize_T_2 ? 2'h1 : _rsize_T_1; // @[TSIToTileLink.scala:81:50] wire _rsize_T_4 = raw_size == 66'h4; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] rsize = _rsize_T_4 ? 2'h2 : _rsize_T_3; // @[TSIToTileLink.scala:81:50] wire _pow2size_T = raw_size[0]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_1 = raw_size[1]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_2 = raw_size[2]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_3 = raw_size[3]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_4 = raw_size[4]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_5 = raw_size[5]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_6 = raw_size[6]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_7 = raw_size[7]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_8 = raw_size[8]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_9 = raw_size[9]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_10 = raw_size[10]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_11 = raw_size[11]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_12 = raw_size[12]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_13 = raw_size[13]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_14 = raw_size[14]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_15 = raw_size[15]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_16 = raw_size[16]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_17 = raw_size[17]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_18 = raw_size[18]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_19 = raw_size[19]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_20 = raw_size[20]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_21 = raw_size[21]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_22 = raw_size[22]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_23 = raw_size[23]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_24 = raw_size[24]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_25 = raw_size[25]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_26 = raw_size[26]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_27 = raw_size[27]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_28 = raw_size[28]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_29 = raw_size[29]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_30 = raw_size[30]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_31 = raw_size[31]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_32 = raw_size[32]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_33 = raw_size[33]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_34 = raw_size[34]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_35 = raw_size[35]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_36 = raw_size[36]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_37 = raw_size[37]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_38 = raw_size[38]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_39 = raw_size[39]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_40 = raw_size[40]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_41 = raw_size[41]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_42 = raw_size[42]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_43 = raw_size[43]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_44 = raw_size[44]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_45 = raw_size[45]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_46 = raw_size[46]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_47 = raw_size[47]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_48 = raw_size[48]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_49 = raw_size[49]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_50 = raw_size[50]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_51 = raw_size[51]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_52 = raw_size[52]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_53 = raw_size[53]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_54 = raw_size[54]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_55 = raw_size[55]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_56 = raw_size[56]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_57 = raw_size[57]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_58 = raw_size[58]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_59 = raw_size[59]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_60 = raw_size[60]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_61 = raw_size[61]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_62 = raw_size[62]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_63 = raw_size[63]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_64 = raw_size[64]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_65 = raw_size[65]; // @[TSIToTileLink.scala:80:21, :84:26] wire [1:0] _pow2size_T_66 = {1'h0, _pow2size_T} + {1'h0, _pow2size_T_1}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_67 = _pow2size_T_66; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_68 = {1'h0, _pow2size_T_2} + {1'h0, _pow2size_T_3}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_69 = _pow2size_T_68; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_70 = {1'h0, _pow2size_T_67} + {1'h0, _pow2size_T_69}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_71 = _pow2size_T_70; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_72 = {1'h0, _pow2size_T_4} + {1'h0, _pow2size_T_5}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_73 = _pow2size_T_72; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_74 = {1'h0, _pow2size_T_6} + {1'h0, _pow2size_T_7}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_75 = _pow2size_T_74; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_76 = {1'h0, _pow2size_T_73} + {1'h0, _pow2size_T_75}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_77 = _pow2size_T_76; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_78 = {1'h0, _pow2size_T_71} + {1'h0, _pow2size_T_77}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_79 = _pow2size_T_78; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_80 = {1'h0, _pow2size_T_8} + {1'h0, _pow2size_T_9}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_81 = _pow2size_T_80; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_82 = {1'h0, _pow2size_T_10} + {1'h0, _pow2size_T_11}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_83 = _pow2size_T_82; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_84 = {1'h0, _pow2size_T_81} + {1'h0, _pow2size_T_83}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_85 = _pow2size_T_84; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_86 = {1'h0, _pow2size_T_12} + {1'h0, _pow2size_T_13}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_87 = _pow2size_T_86; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_88 = {1'h0, _pow2size_T_14} + {1'h0, _pow2size_T_15}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_89 = _pow2size_T_88; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_90 = {1'h0, _pow2size_T_87} + {1'h0, _pow2size_T_89}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_91 = _pow2size_T_90; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_92 = {1'h0, _pow2size_T_85} + {1'h0, _pow2size_T_91}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_93 = _pow2size_T_92; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_94 = {1'h0, _pow2size_T_79} + {1'h0, _pow2size_T_93}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_95 = _pow2size_T_94; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_96 = {1'h0, _pow2size_T_16} + {1'h0, _pow2size_T_17}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_97 = _pow2size_T_96; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_98 = {1'h0, _pow2size_T_18} + {1'h0, _pow2size_T_19}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_99 = _pow2size_T_98; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_100 = {1'h0, _pow2size_T_97} + {1'h0, _pow2size_T_99}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_101 = _pow2size_T_100; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_102 = {1'h0, _pow2size_T_20} + {1'h0, _pow2size_T_21}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_103 = _pow2size_T_102; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_104 = {1'h0, _pow2size_T_22} + {1'h0, _pow2size_T_23}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_105 = _pow2size_T_104; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_106 = {1'h0, _pow2size_T_103} + {1'h0, _pow2size_T_105}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_107 = _pow2size_T_106; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_108 = {1'h0, _pow2size_T_101} + {1'h0, _pow2size_T_107}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_109 = _pow2size_T_108; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_110 = {1'h0, _pow2size_T_24} + {1'h0, _pow2size_T_25}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_111 = _pow2size_T_110; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_112 = {1'h0, _pow2size_T_26} + {1'h0, _pow2size_T_27}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_113 = _pow2size_T_112; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_114 = {1'h0, _pow2size_T_111} + {1'h0, _pow2size_T_113}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_115 = _pow2size_T_114; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_116 = {1'h0, _pow2size_T_28} + {1'h0, _pow2size_T_29}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_117 = _pow2size_T_116; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_118 = {1'h0, _pow2size_T_31} + {1'h0, _pow2size_T_32}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_119 = _pow2size_T_118; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_120 = {2'h0, _pow2size_T_30} + {1'h0, _pow2size_T_119}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_121 = _pow2size_T_120[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_122 = {1'h0, _pow2size_T_117} + {1'h0, _pow2size_T_121}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_123 = _pow2size_T_122; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_124 = {1'h0, _pow2size_T_115} + {1'h0, _pow2size_T_123}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_125 = _pow2size_T_124; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_126 = {1'h0, _pow2size_T_109} + {1'h0, _pow2size_T_125}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_127 = _pow2size_T_126; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_128 = {1'h0, _pow2size_T_95} + {1'h0, _pow2size_T_127}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_129 = _pow2size_T_128; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_130 = {1'h0, _pow2size_T_33} + {1'h0, _pow2size_T_34}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_131 = _pow2size_T_130; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_132 = {1'h0, _pow2size_T_35} + {1'h0, _pow2size_T_36}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_133 = _pow2size_T_132; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_134 = {1'h0, _pow2size_T_131} + {1'h0, _pow2size_T_133}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_135 = _pow2size_T_134; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_136 = {1'h0, _pow2size_T_37} + {1'h0, _pow2size_T_38}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_137 = _pow2size_T_136; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_138 = {1'h0, _pow2size_T_39} + {1'h0, _pow2size_T_40}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_139 = _pow2size_T_138; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_140 = {1'h0, _pow2size_T_137} + {1'h0, _pow2size_T_139}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_141 = _pow2size_T_140; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_142 = {1'h0, _pow2size_T_135} + {1'h0, _pow2size_T_141}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_143 = _pow2size_T_142; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_144 = {1'h0, _pow2size_T_41} + {1'h0, _pow2size_T_42}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_145 = _pow2size_T_144; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_146 = {1'h0, _pow2size_T_43} + {1'h0, _pow2size_T_44}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_147 = _pow2size_T_146; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_148 = {1'h0, _pow2size_T_145} + {1'h0, _pow2size_T_147}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_149 = _pow2size_T_148; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_150 = {1'h0, _pow2size_T_45} + {1'h0, _pow2size_T_46}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_151 = _pow2size_T_150; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_152 = {1'h0, _pow2size_T_47} + {1'h0, _pow2size_T_48}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_153 = _pow2size_T_152; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_154 = {1'h0, _pow2size_T_151} + {1'h0, _pow2size_T_153}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_155 = _pow2size_T_154; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_156 = {1'h0, _pow2size_T_149} + {1'h0, _pow2size_T_155}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_157 = _pow2size_T_156; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_158 = {1'h0, _pow2size_T_143} + {1'h0, _pow2size_T_157}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_159 = _pow2size_T_158; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_160 = {1'h0, _pow2size_T_49} + {1'h0, _pow2size_T_50}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_161 = _pow2size_T_160; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_162 = {1'h0, _pow2size_T_51} + {1'h0, _pow2size_T_52}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_163 = _pow2size_T_162; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_164 = {1'h0, _pow2size_T_161} + {1'h0, _pow2size_T_163}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_165 = _pow2size_T_164; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_166 = {1'h0, _pow2size_T_53} + {1'h0, _pow2size_T_54}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_167 = _pow2size_T_166; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_168 = {1'h0, _pow2size_T_55} + {1'h0, _pow2size_T_56}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_169 = _pow2size_T_168; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_170 = {1'h0, _pow2size_T_167} + {1'h0, _pow2size_T_169}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_171 = _pow2size_T_170; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_172 = {1'h0, _pow2size_T_165} + {1'h0, _pow2size_T_171}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_173 = _pow2size_T_172; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_174 = {1'h0, _pow2size_T_57} + {1'h0, _pow2size_T_58}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_175 = _pow2size_T_174; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_176 = {1'h0, _pow2size_T_59} + {1'h0, _pow2size_T_60}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_177 = _pow2size_T_176; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_178 = {1'h0, _pow2size_T_175} + {1'h0, _pow2size_T_177}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_179 = _pow2size_T_178; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_180 = {1'h0, _pow2size_T_61} + {1'h0, _pow2size_T_62}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_181 = _pow2size_T_180; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_182 = {1'h0, _pow2size_T_64} + {1'h0, _pow2size_T_65}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_183 = _pow2size_T_182; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_184 = {2'h0, _pow2size_T_63} + {1'h0, _pow2size_T_183}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_185 = _pow2size_T_184[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_186 = {1'h0, _pow2size_T_181} + {1'h0, _pow2size_T_185}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_187 = _pow2size_T_186; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_188 = {1'h0, _pow2size_T_179} + {1'h0, _pow2size_T_187}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_189 = _pow2size_T_188; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_190 = {1'h0, _pow2size_T_173} + {1'h0, _pow2size_T_189}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_191 = _pow2size_T_190; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_192 = {1'h0, _pow2size_T_159} + {1'h0, _pow2size_T_191}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_193 = _pow2size_T_192; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_194 = {1'h0, _pow2size_T_129} + {1'h0, _pow2size_T_193}; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_195 = _pow2size_T_194; // @[TSIToTileLink.scala:84:26] wire pow2size = _pow2size_T_195 == 7'h1; // @[TSIToTileLink.scala:84:{26,37}] wire [2:0] _byteAddr_T = addr[2:0]; // @[TSIToTileLink.scala:57:17, :85:36] wire [2:0] byteAddr = pow2size ? _byteAddr_T : 3'h0; // @[TSIToTileLink.scala:84:37, :85:{21,36}] wire [31:0] _put_acquire_T = {beatAddr, 3'h0}; // @[TSIToTileLink.scala:74:22, :88:19] wire [31:0] _put_acquire_legal_T_14 = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [31:0] put_acquire_address = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [63:0] _put_acquire_T_1 = {body_1, body_0}; // @[TSIToTileLink.scala:59:17, :89:10] wire [63:0] put_acquire_data = _put_acquire_T_1; // @[TSIToTileLink.scala:89:10] wire [31:0] _put_acquire_legal_T_4 = {_put_acquire_T[31:14], _put_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_5 = {1'h0, _put_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_6 = _put_acquire_legal_T_5 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_7 = _put_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_8 = _put_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_9 = _put_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _put_acquire_legal_T_69 = _put_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _put_acquire_legal_T_15 = {1'h0, _put_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_16 = _put_acquire_legal_T_15 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_17 = _put_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_18 = _put_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_19 = {_put_acquire_T[31:21], _put_acquire_T[20:0] ^ 21'h100000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_20 = {1'h0, _put_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_21 = _put_acquire_legal_T_20 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_22 = _put_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_23 = _put_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_24 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_25 = {1'h0, _put_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_26 = _put_acquire_legal_T_25 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_27 = _put_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_28 = _put_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_29 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2010000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_30 = {1'h0, _put_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_31 = _put_acquire_legal_T_30 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_32 = _put_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_33 = _put_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_1 = {_put_acquire_T[31:28], _put_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:88:19] wire [31:0] _put_acquire_legal_T_34; // @[Parameters.scala:137:31] assign _put_acquire_legal_T_34 = _GEN_1; // @[Parameters.scala:137:31] wire [31:0] _put_acquire_legal_T_39; // @[Parameters.scala:137:31] assign _put_acquire_legal_T_39 = _GEN_1; // @[Parameters.scala:137:31] wire [32:0] _put_acquire_legal_T_35 = {1'h0, _put_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_36 = _put_acquire_legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_37 = _put_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_38 = _put_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _put_acquire_legal_T_40 = {1'h0, _put_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_41 = _put_acquire_legal_T_40 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_42 = _put_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_43 = _put_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_44 = {_put_acquire_T[31:29], _put_acquire_T[28:0] ^ 29'h10000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_45 = {1'h0, _put_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_46 = _put_acquire_legal_T_45 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_47 = _put_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_48 = _put_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_49 = _put_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_50 = {1'h0, _put_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_51 = _put_acquire_legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_52 = _put_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_53 = _put_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_54 = _put_acquire_legal_T_18 \| _put_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_55 = _put_acquire_legal_T_54 \| _put_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_56 = _put_acquire_legal_T_55 \| _put_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_57 = _put_acquire_legal_T_56 \| _put_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_58 = _put_acquire_legal_T_57 \| _put_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_59 = _put_acquire_legal_T_58 \| _put_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_60 = _put_acquire_legal_T_59 \| _put_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_61 = _put_acquire_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [31:0] _put_acquire_legal_T_63 = {_put_acquire_T[31:17], _put_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_64 = {1'h0, _put_acquire_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_65 = _put_acquire_legal_T_64 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_66 = _put_acquire_legal_T_65; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_67 = _put_acquire_legal_T_66 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_70 = _put_acquire_legal_T_69 \| _put_acquire_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_acquire_legal = _put_acquire_legal_T_70; // @[Parameters.scala:686:26] wire [31:0] _get_acquire_T = {beatAddr, byteAddr}; // @[TSIToTileLink.scala:74:22, :85:21, :92:13] wire [31:0] _get_acquire_legal_T_14 = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] get_acquire_address = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_4 = {_get_acquire_T[31:14], _get_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_5 = {1'h0, _get_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_6 = _get_acquire_legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_7 = _get_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_8 = _get_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_9 = _get_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _get_acquire_legal_T_62 = _get_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _get_acquire_legal_T_15 = {1'h0, _get_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_16 = _get_acquire_legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_17 = _get_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_18 = _get_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_2 = {_get_acquire_T[31:17], _get_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_19; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _get_acquire_legal_T_24; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _get_acquire_legal_T_20 = {1'h0, _get_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_21 = _get_acquire_legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_22 = _get_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_23 = _get_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _get_acquire_legal_T_25 = {1'h0, _get_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_26 = _get_acquire_legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_27 = _get_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_28 = _get_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_29 = {_get_acquire_T[31:26], _get_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_30 = {1'h0, _get_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_31 = _get_acquire_legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_32 = _get_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_33 = _get_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_3 = {_get_acquire_T[31:28], _get_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_34; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_34 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _get_acquire_legal_T_39; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [32:0] _get_acquire_legal_T_35 = {1'h0, _get_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_36 = _get_acquire_legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_37 = _get_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_38 = _get_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _get_acquire_legal_T_40 = {1'h0, _get_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_41 = _get_acquire_legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_42 = _get_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_43 = _get_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_44 = {_get_acquire_T[31:29], _get_acquire_T[28:0] ^ 29'h10000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_45 = {1'h0, _get_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_46 = _get_acquire_legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_47 = _get_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_48 = _get_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_49 = _get_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_50 = {1'h0, _get_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_51 = _get_acquire_legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_52 = _get_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_53 = _get_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_54 = _get_acquire_legal_T_18 \| _get_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_55 = _get_acquire_legal_T_54 \| _get_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_56 = _get_acquire_legal_T_55 \| _get_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_57 = _get_acquire_legal_T_56 \| _get_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_58 = _get_acquire_legal_T_57 \| _get_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_59 = _get_acquire_legal_T_58 \| _get_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_60 = _get_acquire_legal_T_59 \| _get_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_61 = _get_acquire_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_acquire_legal = _get_acquire_legal_T_62 \| _get_acquire_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_acquire_size; // @[Edges.scala:460:17] wire [7:0] get_acquire_mask; // @[Edges.scala:460:17] assign get_acquire_size = {2'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [2:0] _get_acquire_a_mask_sizeOH_T = {1'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [1:0] get_acquire_a_mask_sizeOH_shiftAmount = _get_acquire_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_acquire_a_mask_sizeOH_T_1 = 4'h1 << get_acquire_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_acquire_a_mask_sizeOH_T_2 = _get_acquire_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_acquire_a_mask_sizeOH = {_get_acquire_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_acquire_a_mask_sub_sub_sub_0_1 = &rsize; // @[TSIToTileLink.scala:81:50] wire get_acquire_a_mask_sub_sub_size = get_acquire_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_sub_bit = _get_acquire_T[2]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_sub_1_2 = get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_acquire_a_mask_sub_sub_nbit = ~get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_sub_0_2 = get_acquire_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_sub_acc_T = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_0_1 = get_acquire_a_mask_sub_sub_sub_0_1 \| _get_acquire_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_acquire_a_mask_sub_sub_acc_T_1 = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_1_1 = get_acquire_a_mask_sub_sub_sub_0_1 \| _get_acquire_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_acquire_a_mask_sub_size = get_acquire_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_bit = _get_acquire_T[1]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_nbit = ~get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_0_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_0_1 = get_acquire_a_mask_sub_sub_0_1 \| _get_acquire_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_1_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_1 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_1_1 = get_acquire_a_mask_sub_sub_0_1 \| _get_acquire_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_2_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T_2 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_2_1 = get_acquire_a_mask_sub_sub_1_1 \| _get_acquire_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_3_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_3 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_3_1 = get_acquire_a_mask_sub_sub_1_1 \| _get_acquire_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_size = get_acquire_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_bit = _get_acquire_T[0]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_nbit = ~get_acquire_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_eq = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T = get_acquire_a_mask_size & get_acquire_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc = get_acquire_a_mask_sub_0_1 \| _get_acquire_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_1 = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_1 = get_acquire_a_mask_size & get_acquire_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_1 = get_acquire_a_mask_sub_0_1 \| _get_acquire_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_2 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_2 = get_acquire_a_mask_size & get_acquire_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_2 = get_acquire_a_mask_sub_1_1 \| _get_acquire_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_3 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_3 = get_acquire_a_mask_size & get_acquire_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_3 = get_acquire_a_mask_sub_1_1 \| _get_acquire_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_4 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_4 = get_acquire_a_mask_size & get_acquire_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_4 = get_acquire_a_mask_sub_2_1 \| _get_acquire_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_5 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_5 = get_acquire_a_mask_size & get_acquire_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_5 = get_acquire_a_mask_sub_2_1 \| _get_acquire_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_6 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_6 = get_acquire_a_mask_size & get_acquire_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_6 = get_acquire_a_mask_sub_3_1 \| _get_acquire_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_7 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_7 = get_acquire_a_mask_size & get_acquire_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_7 = get_acquire_a_mask_sub_3_1 \| _get_acquire_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_acquire_a_mask_lo_lo = {get_acquire_a_mask_acc_1, get_acquire_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_lo_hi = {get_acquire_a_mask_acc_3, get_acquire_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_lo = {get_acquire_a_mask_lo_hi, get_acquire_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_acquire_a_mask_hi_lo = {get_acquire_a_mask_acc_5, get_acquire_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_hi_hi = {get_acquire_a_mask_acc_7, get_acquire_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_hi = {get_acquire_a_mask_hi_hi, get_acquire_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_acquire_a_mask_T = {get_acquire_a_mask_hi, get_acquire_a_mask_lo}; // @[Misc.scala:222:10] assign get_acquire_mask = _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire _T_28 = state == 4'h7; // @[TSIToTileLink.scala:67:22] wire _nodeOut_a_valid_T; // @[package.scala:16:47] assign _nodeOut_a_valid_T = _T_28; // @[package.scala:16:47] wire _nodeOut_a_bits_T; // @[TSIToTileLink.scala:95:27] assign _nodeOut_a_bits_T = _T_28; // @[TSIToTileLink.scala:95:27] wire _nodeOut_a_valid_T_1 = state == 4'h3; // @[TSIToTileLink.scala:67:22] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T \| _nodeOut_a_valid_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign _nodeOut_a_bits_T_1_opcode = _nodeOut_a_bits_T ? 3'h1 : 3'h4; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_size = _nodeOut_a_bits_T ? 4'h3 : get_acquire_size; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_address = _nodeOut_a_bits_T ? put_acquire_address : get_acquire_address; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_mask = _nodeOut_a_bits_T ? put_acquire_mask : get_acquire_mask; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_data = _nodeOut_a_bits_T ? put_acquire_data : 64'h0; // @[TSIToTileLink.scala:95:{20,27}] assign nodeOut_a_bits_opcode = _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_size = _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_address = _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_mask = _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_data = _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] wire _nodeOut_d_ready_T = state == 4'h8; // @[TSIToTileLink.scala:67:22] wire _nodeOut_d_ready_T_1 = state == 4'h4; // @[TSIToTileLink.scala:67:22] assign _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T \| _nodeOut_d_ready_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire [5:0] _addr_T_1 = {_addr_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _GEN_4 = {63'h0, io_tsi_in_bits_0}; // @[TSIToTileLink.scala:36:7, :103:12] wire [94:0] _addr_T_2 = _GEN_4 << _addr_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _addr_T_3 = {31'h0, addr} \| _addr_T_2; // @[TSIToTileLink.scala:57:17, :103:12, :118:18] wire [1:0] _GEN_5 = {1'h0, idx}; // @[TSIToTileLink.scala:61:16, :119:16] wire [1:0] _GEN_6 = _GEN_5 + 2'h1; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T; // @[TSIToTileLink.scala:119:16] assign _idx_T = _GEN_6; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T_2; // @[TSIToTileLink.scala:128:16] assign _idx_T_2 = _GEN_6; // @[TSIToTileLink.scala:119:16, :128:16] wire [1:0] _idx_T_6; // @[TSIToTileLink.scala:154:16] assign _idx_T_6 = _GEN_6; // @[TSIToTileLink.scala:119:16, :154:16] wire [1:0] _idx_T_8; // @[TSIToTileLink.scala:166:18] assign _idx_T_8 = _GEN_6; // @[TSIToTileLink.scala:119:16, :166:18] wire _idx_T_1 = _idx_T[0]; // @[TSIToTileLink.scala:119:16] wire _T_6 = _io_tsi_in_ready_T_2 & io_tsi_in_valid_0; // @[TSIToTileLink.scala:36:7, :126:25] wire [5:0] _len_T_1 = {_len_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _len_T_2 = _GEN_4 << _len_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _len_T_3 = {31'h0, len} \| _len_T_2; // @[TSIToTileLink.scala:58:16, :103:12, :127:16] wire _idx_T_3 = _idx_T_2[0]; // @[TSIToTileLink.scala:128:16] wire _GEN_7 = _T_6 & idx; // @[TSIToTileLink.scala:61:16, :126:25, :129:43] wire _idx_T_4 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33] wire _idx_T_5 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33]
Generate the Verilog code corresponding to the following Chisel files. File Multiplier.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe} import freechips.rocketchip.util._ import ALU._ class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle { val fn = Bits(SZ_ALU_FN.W) val dw = Bits(SZ_DW.W) val in1 = Bits(dataBits.W) val in2 = Bits(dataBits.W) val tag = UInt(tagBits.W) } class MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle { val data = Bits(dataBits.W) val full_data = Bits((2dataBits).W) val tag = UInt(tagBits.W) } class MultiplierIO(val dataBits: Int, val tagBits: Int) extends Bundle { val req = Flipped(Decoupled(new MultiplierReq(dataBits, tagBits))) val kill = Input(Bool()) val resp = Decoupled(new MultiplierResp(dataBits, tagBits)) } case class MulDivParams( mulUnroll: Int = 1, divUnroll: Int = 1, mulEarlyOut: Boolean = false, divEarlyOut: Boolean = false, divEarlyOutGranularity: Int = 1 ) class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module { private def minDivLatency = (cfg.divUnroll > 0).option(if (cfg.divEarlyOut) 3 else 1 + w/cfg.divUnroll) private def minMulLatency = (cfg.mulUnroll > 0).option(if (cfg.mulEarlyOut) 2 else w/cfg.mulUnroll) def minLatency: Int = (minDivLatency ++ minMulLatency).min val io = IO(new MultiplierIO(width, log2Up(nXpr))) val w = io.req.bits.in1.getWidth val mulw = if (cfg.mulUnroll == 0) w else (w + cfg.mulUnroll - 1) / cfg.mulUnroll cfg.mulUnroll val fastMulW = if (cfg.mulUnroll == 0) false else w/2 > cfg.mulUnroll && w % (2cfg.mulUnroll) == 0 val s_ready :: s_neg_inputs :: s_mul :: s_div :: s_dummy :: s_neg_output :: s_done_mul :: s_done_div :: Nil = Enum(8) val state = RegInit(s_ready) val req = Reg(chiselTypeOf(io.req.bits)) val count = Reg(UInt(log2Ceil( ((cfg.divUnroll != 0).option(w/cfg.divUnroll + 1).toSeq ++ (cfg.mulUnroll != 0).option(mulw/cfg.mulUnroll)).reduce(_ max _)).W)) val neg_out = Reg(Bool()) val isHi = Reg(Bool()) val resHi = Reg(Bool()) val divisor = Reg(Bits((w+1).W)) // div only needs w bits val remainder = Reg(Bits((2mulw+2).W)) // div only needs 2w+1 bits val mulDecode = List( FN_MUL -> List(Y, N, X, X), FN_MULH -> List(Y, Y, Y, Y), FN_MULHU -> List(Y, Y, N, N), FN_MULHSU -> List(Y, Y, Y, N)) val divDecode = List( FN_DIV -> List(N, N, Y, Y), FN_REM -> List(N, Y, Y, Y), FN_DIVU -> List(N, N, N, N), FN_REMU -> List(N, Y, N, N)) val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil = DecodeLogic(io.req.bits.fn, List(X, X, X, X), (if (cfg.divUnroll != 0) divDecode else Nil) ++ (if (cfg.mulUnroll != 0) mulDecode else Nil)).map(_.asBool) require(w == 32 \|\| w == 64) def halfWidth(req: MultiplierReq) = (w > 32).B && req.dw === DW_32 def sext(x: Bits, halfW: Bool, signed: Bool) = { val sign = signed && Mux(halfW, x(w/2-1), x(w-1)) val hi = Mux(halfW, Fill(w/2, sign), x(w-1,w/2)) (Cat(hi, x(w/2-1,0)), sign) } val (lhs_in, lhs_sign) = sext(io.req.bits.in1, halfWidth(io.req.bits), lhsSigned) val (rhs_in, rhs_sign) = sext(io.req.bits.in2, halfWidth(io.req.bits), rhsSigned) val subtractor = remainder(2w,w) - divisor val result = Mux(resHi, remainder(2w, w+1), remainder(w-1, 0)) val negated_remainder = -result if (cfg.divUnroll != 0) when (state === s_neg_inputs) { when (remainder(w-1)) { remainder := negated_remainder } when (divisor(w-1)) { divisor := subtractor } state := s_div } if (cfg.divUnroll != 0) when (state === s_neg_output) { remainder := negated_remainder state := s_done_div resHi := false.B } if (cfg.mulUnroll != 0) when (state === s_mul) { val mulReg = Cat(remainder(2mulw+1,w+1),remainder(w-1,0)) val mplierSign = remainder(w) val mplier = mulReg(mulw-1,0) val accum = mulReg(2mulw,mulw).asSInt val mpcand = divisor.asSInt val prod = Cat(mplierSign, mplier(cfg.mulUnroll-1, 0)).asSInt mpcand + accum val nextMulReg = Cat(prod, mplier(mulw-1, cfg.mulUnroll)) val nextMplierSign = count === (mulw/cfg.mulUnroll-2).U && neg_out val eOutMask = ((BigInt(-1) << mulw).S >> (count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))(mulw-1,0) val eOut = (cfg.mulEarlyOut).B && count =/= (mulw/cfg.mulUnroll-1).U && count =/= 0.U && !isHi && (mplier & ~eOutMask) === 0.U val eOutRes = (mulReg >> (mulw.U - count * cfg.mulUnroll.U)(log2Up(mulw)-1,0)) val nextMulReg1 = Cat(nextMulReg(2mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0)) remainder := Cat(nextMulReg1 >> w, nextMplierSign, nextMulReg1(w-1,0)) count := count + 1.U when (eOut \|\| count === (mulw/cfg.mulUnroll-1).U) { state := s_done_mul resHi := isHi } } if (cfg.divUnroll != 0) when (state === s_div) { val unrolls = ((0 until cfg.divUnroll) scanLeft remainder) { case (rem, i) => // the special case for iteration 0 is to save HW, not for correctness val difference = if (i == 0) subtractor else rem(2w,w) - divisor(w-1,0) val less = difference(w) Cat(Mux(less, rem(2w-1,w), difference(w-1,0)), rem(w-1,0), !less) }.tail remainder := unrolls.last when (count === (w/cfg.divUnroll).U) { state := Mux(neg_out, s_neg_output, s_done_div) resHi := isHi if (w % cfg.divUnroll < cfg.divUnroll - 1) remainder := unrolls(w % cfg.divUnroll) } count := count + 1.U val divby0 = count === 0.U && !subtractor(w) if (cfg.divEarlyOut) { val align = 1 << log2Floor(cfg.divUnroll max cfg.divEarlyOutGranularity) val alignMask = ~((align-1).U(log2Ceil(w).W)) val divisorMSB = Log2(divisor(w-1,0), w) & alignMask val dividendMSB = Log2(remainder(w-1,0), w) \| ~alignMask val eOutPos = ~(dividendMSB - divisorMSB) val eOut = count === 0.U && !divby0 && eOutPos >= align.U when (eOut) { remainder := remainder(w-1,0) << eOutPos count := eOutPos >> log2Floor(cfg.divUnroll) } } when (divby0 && !isHi) { neg_out := false.B } } when (io.resp.fire \|\| io.kill) { state := s_ready } when (io.req.fire) { state := Mux(cmdMul, s_mul, Mux(lhs_sign \|\| rhs_sign, s_neg_inputs, s_div)) isHi := cmdHi resHi := false.B count := (if (fastMulW) Mux[UInt](cmdMul && halfWidth(io.req.bits), (w/cfg.mulUnroll/2).U, 0.U) else 0.U) neg_out := Mux(cmdHi, lhs_sign, lhs_sign =/= rhs_sign) divisor := Cat(rhs_sign, rhs_in) remainder := lhs_in req := io.req.bits } val outMul = (state & (s_done_mul ^ s_done_div)) === (s_done_mul & ~s_done_div) val loOut = Mux(fastMulW.B && halfWidth(req) && outMul, result(w-1,w/2), result(w/2-1,0)) val hiOut = Mux(halfWidth(req), Fill(w/2, loOut(w/2-1)), result(w-1,w/2)) io.resp.bits.tag := req.tag io.resp.bits.data := Cat(hiOut, loOut) io.resp.bits.full_data := Cat(remainder(2w, w+1), remainder(w-1, 0)) io.resp.valid := (state === s_done_mul \|\| state === s_done_div) io.req.ready := state === s_ready } class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed { val io = IO(new Bundle { val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr)))) val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr))) }) val in = Pipe(io.req) val decode = List( FN_MUL -> List(N, X, X), FN_MULH -> List(Y, Y, Y), FN_MULHU -> List(Y, N, N), FN_MULHSU -> List(Y, Y, N)) val cmdHi :: lhsSigned :: rhsSigned :: Nil = DecodeLogic(in.bits.fn, List(X, X, X), decode).map(_.asBool) val cmdHalf = (width > 32).B && in.bits.dw === DW_32 val lhs = Cat(lhsSigned && in.bits.in1(width-1), in.bits.in1).asSInt val rhs = Cat(rhsSigned && in.bits.in2(width-1), in.bits.in2).asSInt val prod = lhs * rhs val muxed = Mux(cmdHi, prod(2*width-1, width), Mux(cmdHalf, prod(width/2-1, 0).sextTo(width), prod(width-1, 0))) val resp = Pipe(in, latency-1) io.resp.valid := resp.valid io.resp.bits.tag := resp.bits.tag io.resp.bits.data := Pipe(in.valid, muxed, latency-1).bits io.resp.bits.full_data := Pipe(in.valid, prod, latency-1).bits.asUInt }	module MulDiv_1( // @[Multiplier.scala:40:7] input clock, // @[Multiplier.scala:40:7] input reset, // @[Multiplier.scala:40:7] output io_req_ready, // @[Multiplier.scala:45:14] input io_req_valid, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_fn, // @[Multiplier.scala:45:14] input io_req_bits_dw, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in1, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in2, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_tag, // @[Multiplier.scala:45:14] input io_resp_ready, // @[Multiplier.scala:45:14] output io_resp_valid, // @[Multiplier.scala:45:14] output [63:0] io_resp_bits_data, // @[Multiplier.scala:45:14] output [4:0] io_resp_bits_tag // @[Multiplier.scala:45:14] ); reg [2:0] state; // @[Multiplier.scala:51:22] reg req_dw; // @[Multiplier.scala:53:16] reg [4:0] req_tag; // @[Multiplier.scala:53:16] reg [6:0] count; // @[Multiplier.scala:54:18] reg neg_out; // @[Multiplier.scala:57:20] reg isHi; // @[Multiplier.scala:58:17] reg resHi; // @[Multiplier.scala:59:18] reg [64:0] divisor; // @[Multiplier.scala:60:20] reg [129:0] remainder; // @[Multiplier.scala:61:22] wire [63:0] result = resHi ? remainder[128:65] : remainder[63:0]; // @[Multiplier.scala:59:18, :61:22, :89:{19,36,57}] wire io_resp_valid_0 = state == 3'h6 \| (&state); // @[Multiplier.scala:51:22, :182:{27,42,51}] wire io_req_ready_0 = state == 3'h0; // @[Multiplier.scala:51:22, :183:25] wire [5:0] _eOutPos_T = {\|(remainder[63:32]), (\|(remainder[63:32])) ? {\|(remainder[63:48]), (\|(remainder[63:48])) ? {\|(remainder[63:56]), (\|(remainder[63:56])) ? {\|(remainder[63:60]), (\|(remainder[63:60])) ? (remainder[63] ? 2'h3 : remainder[62] ? 2'h2 : {1'h0, remainder[61]}) : remainder[59] ? 2'h3 : remainder[58] ? 2'h2 : {1'h0, remainder[57]}} : {\|(remainder[55:52]), (\|(remainder[55:52])) ? (remainder[55] ? 2'h3 : remainder[54] ? 2'h2 : {1'h0, remainder[53]}) : remainder[51] ? 2'h3 : remainder[50] ? 2'h2 : {1'h0, remainder[49]}}} : {\|(remainder[47:40]), (\|(remainder[47:40])) ? {\|(remainder[47:44]), (\|(remainder[47:44])) ? (remainder[47] ? 2'h3 : remainder[46] ? 2'h2 : {1'h0, remainder[45]}) : remainder[43] ? 2'h3 : remainder[42] ? 2'h2 : {1'h0, remainder[41]}} : {\|(remainder[39:36]), (\|(remainder[39:36])) ? (remainder[39] ? 2'h3 : remainder[38] ? 2'h2 : {1'h0, remainder[37]}) : remainder[35] ? 2'h3 : remainder[34] ? 2'h2 : {1'h0, remainder[33]}}}} : {\|(remainder[31:16]), (\|(remainder[31:16])) ? {\|(remainder[31:24]), (\|(remainder[31:24])) ? {\|(remainder[31:28]), (\|(remainder[31:28])) ? (remainder[31] ? 2'h3 : remainder[30] ? 2'h2 : {1'h0, remainder[29]}) : remainder[27] ? 2'h3 : remainder[26] ? 2'h2 : {1'h0, remainder[25]}} : {\|(remainder[23:20]), (\|(remainder[23:20])) ? (remainder[23] ? 2'h3 : remainder[22] ? 2'h2 : {1'h0, remainder[21]}) : remainder[19] ? 2'h3 : remainder[18] ? 2'h2 : {1'h0, remainder[17]}}} : {\|(remainder[15:8]), (\|(remainder[15:8])) ? {\|(remainder[15:12]), (\|(remainder[15:12])) ? (remainder[15] ? 2'h3 : remainder[14] ? 2'h2 : {1'h0, remainder[13]}) : remainder[11] ? 2'h3 : remainder[10] ? 2'h2 : {1'h0, remainder[9]}} : {\|(remainder[7:4]), (\|(remainder[7:4])) ? (remainder[7] ? 2'h3 : remainder[6] ? 2'h2 : {1'h0, remainder[5]}) : remainder[3] ? 2'h3 : remainder[2] ? 2'h2 : {1'h0, remainder[1]}}}}} - {\|(divisor[63:32]), (\|(divisor[63:32])) ? {\|(divisor[63:48]), (\|(divisor[63:48])) ? {\|(divisor[63:56]), (\|(divisor[63:56])) ? {\|(divisor[63:60]), (\|(divisor[63:60])) ? (divisor[63] ? 2'h3 : divisor[62] ? 2'h2 : {1'h0, divisor[61]}) : divisor[59] ? 2'h3 : divisor[58] ? 2'h2 : {1'h0, divisor[57]}} : {\|(divisor[55:52]), (\|(divisor[55:52])) ? (divisor[55] ? 2'h3 : divisor[54] ? 2'h2 : {1'h0, divisor[53]}) : divisor[51] ? 2'h3 : divisor[50] ? 2'h2 : {1'h0, divisor[49]}}} : {\|(divisor[47:40]), (\|(divisor[47:40])) ? {\|(divisor[47:44]), (\|(divisor[47:44])) ? (divisor[47] ? 2'h3 : divisor[46] ? 2'h2 : {1'h0, divisor[45]}) : divisor[43] ? 2'h3 : divisor[42] ? 2'h2 : {1'h0, divisor[41]}} : {\|(divisor[39:36]), (\|(divisor[39:36])) ? (divisor[39] ? 2'h3 : divisor[38] ? 2'h2 : {1'h0, divisor[37]}) : divisor[35] ? 2'h3 : divisor[34] ? 2'h2 : {1'h0, divisor[33]}}}} : {\|(divisor[31:16]), (\|(divisor[31:16])) ? {\|(divisor[31:24]), (\|(divisor[31:24])) ? {\|(divisor[31:28]), (\|(divisor[31:28])) ? (divisor[31] ? 2'h3 : divisor[30] ? 2'h2 : {1'h0, divisor[29]}) : divisor[27] ? 2'h3 : divisor[26] ? 2'h2 : {1'h0, divisor[25]}} : {\|(divisor[23:20]), (\|(divisor[23:20])) ? (divisor[23] ? 2'h3 : divisor[22] ? 2'h2 : {1'h0, divisor[21]}) : divisor[19] ? 2'h3 : divisor[18] ? 2'h2 : {1'h0, divisor[17]}}} : {\|(divisor[15:8]), (\|(divisor[15:8])) ? {\|(divisor[15:12]), (\|(divisor[15:12])) ? (divisor[15] ? 2'h3 : divisor[14] ? 2'h2 : {1'h0, divisor[13]}) : divisor[11] ? 2'h3 : divisor[10] ? 2'h2 : {1'h0, divisor[9]}} : {\|(divisor[7:4]), (\|(divisor[7:4])) ? (divisor[7] ? 2'h3 : divisor[6] ? 2'h2 : {1'h0, divisor[5]}) : divisor[3] ? 2'h3 : divisor[2] ? 2'h2 : {1'h0, divisor[1]}}}}}; // @[CircuitMath.scala:28:8, :30:{10,12}, :33:17, :34:17, :35:22, :36:{10,21}] wire [1:0] _decoded_andMatrixOutputs_T = {~(io_req_bits_fn[0]), io_req_bits_fn[2]}; // @[pla.scala:78:21, :90:45, :98:53] wire [1:0] _decoded_andMatrixOutputs_T_1 = {io_req_bits_fn[1], io_req_bits_fn[2]}; // @[pla.scala:90:45, :98:53] wire lhs_sign = (&_decoded_andMatrixOutputs_T) & (io_req_bits_dw ? io_req_bits_in1[63] : io_req_bits_in1[31]); // @[pla.scala:98:{53,70}] wire rhs_sign = (&_decoded_andMatrixOutputs_T) & (io_req_bits_dw ? io_req_bits_in2[63] : io_req_bits_in2[31]); // @[pla.scala:98:{53,70}] wire [64:0] _subtractor_T_1 = remainder[128:64] - divisor; // @[Multiplier.scala:60:20, :61:22, :88:{29,37}] wire _GEN = state == 3'h1; // @[Multiplier.scala:51:22, :92:39] wire _GEN_0 = state == 3'h5; // @[Multiplier.scala:51:22, :101:39] wire _GEN_1 = state == 3'h3; // @[Multiplier.scala:51:22, :129:39] wire _GEN_2 = _GEN_1 & count == 7'h40; // @[Multiplier.scala:54:18, :101:57, :129:{39,50}, :138:{17,42}, :139:13] wire _eOut_T = count == 7'h0; // @[Multiplier.scala:54:18, :146:24] wire divby0 = _eOut_T & ~(_subtractor_T_1[64]); // @[Multiplier.scala:88:37, :133:28, :146:{24,32,35}] wire _GEN_3 = io_req_ready_0 & io_req_valid; // @[Decoupled.scala:51:35] wire eOut = _eOut_T & ~divby0 & _eOutPos_T != 6'h3F; // @[Multiplier.scala:146:{24,32}, :152:35, :153:{32,35,43,54}] always @(posedge clock) begin // @[Multiplier.scala:40:7] if (reset) // @[Multiplier.scala:40:7] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_GEN_3) // @[Decoupled.scala:51:35] state <= {1'h0, ~(lhs_sign \| rhs_sign), 1'h1}; // @[Multiplier.scala:51:22, :81:23, :165:{36,46}] else if (io_resp_ready & io_resp_valid_0) // @[Decoupled.scala:51:35] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_GEN_2) // @[Multiplier.scala:101:57, :129:50, :138:42, :139:13] state <= {1'h1, ~neg_out, 1'h1}; // @[Multiplier.scala:51:22, :57:20, :139:19] else if (_GEN_0) // @[Multiplier.scala:101:39] state <= 3'h7; // @[Multiplier.scala:51:22] else if (_GEN) // @[Multiplier.scala:92:39] state <= 3'h3; // @[Multiplier.scala:51:22] if (_GEN_3) begin // @[Decoupled.scala:51:35] req_dw <= io_req_bits_dw; // @[Multiplier.scala:53:16] req_tag <= io_req_bits_tag; // @[Multiplier.scala:53:16] count <= 7'h0; // @[Multiplier.scala:54:18] isHi <= &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] divisor <= {rhs_sign, io_req_bits_dw ? io_req_bits_in2[63:32] : {32{rhs_sign}}, io_req_bits_in2[31:0]}; // @[Multiplier.scala:60:20, :81:23, :82:{17,29,43}, :83:15, :170:19] remainder <= {66'h0, io_req_bits_dw ? io_req_bits_in1[63:32] : {32{lhs_sign}}, io_req_bits_in1[31:0]}; // @[Multiplier.scala:61:22, :81:23, :82:{17,29,43}, :83:15, :94:17, :171:15] end else begin // @[Decoupled.scala:51:35] if (_GEN_1) begin // @[Multiplier.scala:129:39] count <= eOut ? {1'h0, ~_eOutPos_T} : count + 7'h1; // @[Multiplier.scala:54:18, :144:{11,20}, :152:{21,35}, :153:{32,43}, :154:19, :156:15] remainder <= eOut ? {3'h0, {63'h0, remainder[63:0]} << ~_eOutPos_T} : {1'h0, _subtractor_T_1[64] ? remainder[127:64] : _subtractor_T_1[63:0], remainder[63:0], ~(_subtractor_T_1[64])}; // @[Multiplier.scala:61:22, :88:37, :89:57, :133:28, :134:{14,24,45,67}, :137:15, :152:{21,35}, :153:{32,43}, :154:19, :155:{19,39}] end else if (_GEN_0 \| _GEN & remainder[63]) // @[Multiplier.scala:61:22, :92:{39,57}, :93:{20,27}, :94:17, :101:{39,57}, :102:15] remainder <= {66'h0, 64'h0 - result}; // @[Multiplier.scala:61:22, :89:19, :90:27, :94:17] if (_GEN & divisor[63]) // @[Multiplier.scala:60:20, :92:{39,57}, :96:{18,25}, :97:15] divisor <= _subtractor_T_1; // @[Multiplier.scala:60:20, :88:37] end neg_out <= _GEN_3 ? ((&_decoded_andMatrixOutputs_T_1) ? lhs_sign : lhs_sign != rhs_sign) : ~(_GEN_1 & divby0 & ~isHi) & neg_out; // @[pla.scala:98:{53,70}] resHi <= ~_GEN_3 & (_GEN_2 ? isHi : ~_GEN_0 & resHi); // @[Decoupled.scala:51:35] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /* Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. / class ClientMetadata extends Bundle { /* Actual state information stored in this bundle / val state = UInt(ClientStates.width.W) /* Metadata equality / def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /* Is the block's data present in this cache / def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /* Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) / private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /* Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). / private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd \|\| param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /* Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). / def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /* Does a secondary miss on the block require another Acquire message / def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /* Metadata change on a returned Grant / def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /* Determine what state to go to based on Probe param / private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /* Translate cache control cmds into Probe param / private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /* Factories for ClientMetadata, including on reset / object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File MSHR.scala: package shuttle.dmem import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ class ShuttleDCacheMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) val req_sec_rdy = Output(Bool()) val req_bits = Input(new ShuttleMSHRReq()) val probe_addr = Input(UInt(paddrBits.W)) val idx_match = Output(Bool()) val tag = Output(Bits(tagBits.W)) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Valid(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val refill = Output(new L1RefillReq()) // Data is bypassed val meta_write = Decoupled(new L1MetaWriteReq) val replay = Decoupled(new ShuttleMSHRReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val probe_rdy = Output(Bool()) }) val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(9) val state = RegInit(s_invalid) val req = Reg(new ShuttleMSHRReq) val req_idx = req.addr(untagBits-1,blockOffBits) val req_tag = req.addr >> untagBits val req_block_addr = (req.addr >> blockOffBits) << blockOffBits val idx_match = req_idx === io.req_bits.addr(untagBits-1,blockOffBits) val probe_idx_match = req_idx === io.probe_addr(untagBits-1,blockOffBits) val new_coh = RegInit(ClientMetadata.onReset) val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH) val grow_param = new_coh.onAccess(req.cmd)._2 val coh_on_grant = new_coh.onGrant(req.cmd, io.mem_grant.bits.param) // We only accept secondary misses if we haven't yet sent an Acquire to outer memory // or if the Acquire that was sent will obtain a Grant with sufficient permissions // to let us replay this new request. I.e. we don't handle multiple outstanding // Acquires on the same block for now. val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) = new_coh.onSecondaryAccess(req.cmd, io.req_bits.cmd) val states_before_refill = Seq(s_wb_req, s_wb_resp, s_meta_clear) val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) val sec_rdy = idx_match && (state.isOneOf(states_before_refill) \|\| (state.isOneOf(s_refill_req, s_refill_resp) && !cmd_requires_second_acquire && !refill_done)) val rpq = Module(new Queue(new ShuttleMSHRReq, cfg.nRPQ)) rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy \|\| io.req_sec_val && sec_rdy) && !isPrefetch(io.req_bits.cmd) rpq.io.enq.bits := io.req_bits rpq.io.deq.ready := (io.replay.ready && state === s_drain_rpq) \|\| state === s_invalid val acked = Reg(Bool()) when (io.mem_grant.valid) { acked := true.B } when (state === s_drain_rpq && !rpq.io.deq.valid) { state := s_invalid } when (state === s_meta_write_resp) { // this wait state allows us to catch RAW hazards on the tags via nack_victim state := s_drain_rpq } when (state === s_meta_write_req && io.meta_write.ready) { state := s_meta_write_resp } when (state === s_refill_resp && refill_done) { new_coh := coh_on_grant state := s_meta_write_req } when (io.mem_acquire.fire) { // s_refill_req state := s_refill_resp } when (state === s_meta_clear && io.meta_write.ready) { state := s_refill_req } when (state === s_wb_resp && io.wb_req.ready && acked) { state := s_meta_clear } when (io.wb_req.fire) { // s_wb_req state := s_wb_resp } when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req //If we get a secondary miss that needs more permissions before we've sent // out the primary miss's Acquire, we can upgrade the permissions we're // going to ask for in s_refill_req req.cmd := dirtier_cmd when (is_hit_again) { new_coh := dirtier_coh } } when (io.req_pri_val && io.req_pri_rdy) { req := io.req_bits acked := false.B val old_coh = io.req_bits.old_meta.coh val needs_wb = old_coh.onCacheControl(M_FLUSH)._1 val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req_bits.cmd) when (io.req_bits.tag_match) { when (is_hit) { // set dirty bit new_coh := coh_on_hit state := s_meta_write_req }.otherwise { // upgrade permissions new_coh := old_coh state := s_refill_req } }.otherwise { // writback if necessary and refill new_coh := ClientMetadata.onReset state := Mux(needs_wb, s_wb_req, s_meta_clear) } } val grantackq = Module(new Queue(new TLBundleE(edge.bundle), 1)) val can_finish = state.isOneOf(s_invalid, s_refill_req) grantackq.io.enq.valid := refill_done && edge.isRequest(io.mem_grant.bits) grantackq.io.enq.bits := edge.GrantAck(io.mem_grant.bits) io.mem_finish.valid := grantackq.io.deq.valid && can_finish io.mem_finish.bits := grantackq.io.deq.bits grantackq.io.deq.ready := io.mem_finish.ready && can_finish io.idx_match := (state =/= s_invalid) && idx_match io.refill.way_en := req.way_en io.refill.addr := req_block_addr \| refill_address_inc io.tag := req_tag io.req_pri_rdy := state === s_invalid io.req_sec_rdy := sec_rdy && rpq.io.enq.ready val meta_hazard = RegInit(0.U(2.W)) when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U } when (io.meta_write.fire) { meta_hazard := 1.U } io.probe_rdy := !(state =/= s_invalid && probe_idx_match) \|\| (!state.isOneOf(states_before_refill) && meta_hazard === 0.U) io.meta_write.valid := state.isOneOf(s_meta_write_req, s_meta_clear) io.meta_write.bits.idx := req_idx io.meta_write.bits.tag := io.tag io.meta_write.bits.data.coh := Mux(state === s_meta_clear, coh_on_clear, new_coh) io.meta_write.bits.data.tag := io.tag io.meta_write.bits.way_en := req.way_en io.wb_req.valid := state === s_wb_req io.wb_req.bits.source := id.U io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.param := shrink_param io.wb_req.bits.way_en := req.way_en io.wb_req.bits.voluntary := true.B io.mem_acquire.valid := state === s_refill_req && grantackq.io.enq.ready io.mem_acquire.bits := edge.AcquireBlock( fromSource = id.U, toAddress = Cat(io.tag, req_idx) << blockOffBits, lgSize = lgCacheBlockBytes.U, growPermissions = grow_param)._2 io.replay.valid := state === s_drain_rpq && rpq.io.deq.valid io.replay.bits := rpq.io.deq.bits io.replay.bits.addr := Cat(io.tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) io.replay.bits.cmd := rpq.io.deq.bits.cmd when (state === s_drain_rpq && !rpq.io.deq.valid) { state := Mux(RegNext(!rpq.io.deq.valid), s_invalid, state) } rpq.io.deq.ready := io.replay.ready && state === s_drain_rpq } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module ShuttleDCacheMSHR_2( // @[MSHR.scala:12:7] input clock, // @[MSHR.scala:12:7] input reset, // @[MSHR.scala:12:7] input io_req_pri_val, // @[MSHR.scala:13:14] output io_req_pri_rdy, // @[MSHR.scala:13:14] input io_req_sec_val, // @[MSHR.scala:13:14] output io_req_sec_rdy, // @[MSHR.scala:13:14] input [39:0] io_req_bits_addr, // @[MSHR.scala:13:14] input [6:0] io_req_bits_tag, // @[MSHR.scala:13:14] input [4:0] io_req_bits_cmd, // @[MSHR.scala:13:14] input [1:0] io_req_bits_size, // @[MSHR.scala:13:14] input io_req_bits_signed, // @[MSHR.scala:13:14] input [63:0] io_req_bits_data, // @[MSHR.scala:13:14] input [7:0] io_req_bits_mask, // @[MSHR.scala:13:14] input io_req_bits_tag_match, // @[MSHR.scala:13:14] input [1:0] io_req_bits_old_meta_coh_state, // @[MSHR.scala:13:14] input [19:0] io_req_bits_old_meta_tag, // @[MSHR.scala:13:14] input [3:0] io_req_bits_way_en, // @[MSHR.scala:13:14] input [4:0] io_req_bits_sdq_id, // @[MSHR.scala:13:14] input [31:0] io_probe_addr, // @[MSHR.scala:13:14] output io_idx_match, // @[MSHR.scala:13:14] output [19:0] io_tag, // @[MSHR.scala:13:14] input io_mem_acquire_ready, // @[MSHR.scala:13:14] output io_mem_acquire_valid, // @[MSHR.scala:13:14] output [2:0] io_mem_acquire_bits_param, // @[MSHR.scala:13:14] output [31:0] io_mem_acquire_bits_address, // @[MSHR.scala:13:14] input io_mem_grant_valid, // @[MSHR.scala:13:14] input [2:0] io_mem_grant_bits_opcode, // @[MSHR.scala:13:14] input [1:0] io_mem_grant_bits_param, // @[MSHR.scala:13:14] input [3:0] io_mem_grant_bits_size, // @[MSHR.scala:13:14] input [2:0] io_mem_grant_bits_source, // @[MSHR.scala:13:14] input [2:0] io_mem_grant_bits_sink, // @[MSHR.scala:13:14] input io_mem_grant_bits_denied, // @[MSHR.scala:13:14] input [63:0] io_mem_grant_bits_data, // @[MSHR.scala:13:14] input io_mem_grant_bits_corrupt, // @[MSHR.scala:13:14] input io_mem_finish_ready, // @[MSHR.scala:13:14] output io_mem_finish_valid, // @[MSHR.scala:13:14] output [2:0] io_mem_finish_bits_sink, // @[MSHR.scala:13:14] output [3:0] io_refill_way_en, // @[MSHR.scala:13:14] output [11:0] io_refill_addr, // @[MSHR.scala:13:14] input io_meta_write_ready, // @[MSHR.scala:13:14] output io_meta_write_valid, // @[MSHR.scala:13:14] output [5:0] io_meta_write_bits_idx, // @[MSHR.scala:13:14] output [3:0] io_meta_write_bits_way_en, // @[MSHR.scala:13:14] output [19:0] io_meta_write_bits_tag, // @[MSHR.scala:13:14] output [1:0] io_meta_write_bits_data_coh_state, // @[MSHR.scala:13:14] output [19:0] io_meta_write_bits_data_tag, // @[MSHR.scala:13:14] input io_replay_ready, // @[MSHR.scala:13:14] output io_replay_valid, // @[MSHR.scala:13:14] output [39:0] io_replay_bits_addr, // @[MSHR.scala:13:14] output [6:0] io_replay_bits_tag, // @[MSHR.scala:13:14] output [4:0] io_replay_bits_cmd, // @[MSHR.scala:13:14] output [1:0] io_replay_bits_size, // @[MSHR.scala:13:14] output io_replay_bits_signed, // @[MSHR.scala:13:14] output [63:0] io_replay_bits_data, // @[MSHR.scala:13:14] output [7:0] io_replay_bits_mask, // @[MSHR.scala:13:14] output io_replay_bits_tag_match, // @[MSHR.scala:13:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[MSHR.scala:13:14] output [19:0] io_replay_bits_old_meta_tag, // @[MSHR.scala:13:14] output [3:0] io_replay_bits_way_en, // @[MSHR.scala:13:14] output [4:0] io_replay_bits_sdq_id, // @[MSHR.scala:13:14] input io_wb_req_ready, // @[MSHR.scala:13:14] output io_wb_req_valid, // @[MSHR.scala:13:14] output [19:0] io_wb_req_bits_tag, // @[MSHR.scala:13:14] output [5:0] io_wb_req_bits_idx, // @[MSHR.scala:13:14] output [2:0] io_wb_req_bits_param, // @[MSHR.scala:13:14] output [3:0] io_wb_req_bits_way_en, // @[MSHR.scala:13:14] output io_probe_rdy // @[MSHR.scala:13:14] ); wire [19:0] io_tag_0; // @[MSHR.scala:12:7] wire _grantackq_io_enq_ready; // @[MSHR.scala:126:25] wire _grantackq_io_deq_valid; // @[MSHR.scala:126:25] wire _rpq_io_enq_ready; // @[MSHR.scala:63:19] wire _rpq_io_deq_valid; // @[MSHR.scala:63:19] wire [39:0] _rpq_io_deq_bits_addr; // @[MSHR.scala:63:19] wire io_req_pri_val_0 = io_req_pri_val; // @[MSHR.scala:12:7] wire io_req_sec_val_0 = io_req_sec_val; // @[MSHR.scala:12:7] wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[MSHR.scala:12:7] wire [6:0] io_req_bits_tag_0 = io_req_bits_tag; // @[MSHR.scala:12:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[MSHR.scala:12:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[MSHR.scala:12:7] wire io_req_bits_signed_0 = io_req_bits_signed; // @[MSHR.scala:12:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[MSHR.scala:12:7] wire [7:0] io_req_bits_mask_0 = io_req_bits_mask; // @[MSHR.scala:12:7] wire io_req_bits_tag_match_0 = io_req_bits_tag_match; // @[MSHR.scala:12:7] wire [1:0] io_req_bits_old_meta_coh_state_0 = io_req_bits_old_meta_coh_state; // @[MSHR.scala:12:7] wire [19:0] io_req_bits_old_meta_tag_0 = io_req_bits_old_meta_tag; // @[MSHR.scala:12:7] wire [3:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[MSHR.scala:12:7] wire [4:0] io_req_bits_sdq_id_0 = io_req_bits_sdq_id; // @[MSHR.scala:12:7] wire [31:0] io_probe_addr_0 = io_probe_addr; // @[MSHR.scala:12:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[MSHR.scala:12:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[MSHR.scala:12:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[MSHR.scala:12:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[MSHR.scala:12:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[MSHR.scala:12:7] wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[MSHR.scala:12:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[MSHR.scala:12:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[MSHR.scala:12:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[MSHR.scala:12:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[MSHR.scala:12:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[MSHR.scala:12:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[MSHR.scala:12:7] wire io_replay_ready_0 = io_replay_ready; // @[MSHR.scala:12:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[MSHR.scala:12:7] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire io_wb_req_bits_voluntary = 1'h1; // @[MSHR.scala:12:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_corrupt = 1'h0; // @[MSHR.scala:12:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[MSHR.scala:12:7] wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[MSHR.scala:12:7, :13:14] wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[MSHR.scala:12:7, :13:14] wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[MSHR.scala:12:7, :13:14] wire [2:0] io_mem_acquire_bits_source = 3'h2; // @[MSHR.scala:12:7] wire [2:0] io_wb_req_bits_source = 3'h2; // @[MSHR.scala:12:7] wire [2:0] io_mem_acquire_bits_a_source = 3'h2; // @[Edges.scala:346:17] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[MSHR.scala:12:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[MSHR.scala:12:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire _io_req_pri_rdy_T; // @[MSHR.scala:138:27] wire _io_req_sec_rdy_T; // @[MSHR.scala:139:29] wire _io_idx_match_T_1; // @[MSHR.scala:134:41] wire [19:0] io_meta_write_bits_tag_0 = io_tag_0; // @[MSHR.scala:12:7] wire [19:0] io_meta_write_bits_data_tag_0 = io_tag_0; // @[MSHR.scala:12:7] wire _io_mem_acquire_valid_T_1; // @[MSHR.scala:161:50] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [2:0] grantackq_io_enq_bits_e_sink = io_mem_grant_bits_sink_0; // @[MSHR.scala:12:7] wire _io_mem_finish_valid_T; // @[MSHR.scala:130:49] wire _io_meta_write_valid_T_2; // @[package.scala:81:59] wire [5:0] req_idx; // @[MSHR.scala:39:25] wire [1:0] _io_meta_write_bits_data_coh_T_1_state; // @[MSHR.scala:149:37] wire _io_replay_valid_T_1; // @[MSHR.scala:168:44] wire _io_wb_req_valid_T; // @[MSHR.scala:153:28] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire _io_probe_rdy_T_11; // @[MSHR.scala:144:61] wire [2:0] io_mem_acquire_bits_param_0; // @[MSHR.scala:12:7] wire [31:0] io_mem_acquire_bits_address_0; // @[MSHR.scala:12:7] wire io_mem_acquire_valid_0; // @[MSHR.scala:12:7] wire [2:0] io_mem_finish_bits_sink_0; // @[MSHR.scala:12:7] wire io_mem_finish_valid_0; // @[MSHR.scala:12:7] wire [3:0] io_refill_way_en_0; // @[MSHR.scala:12:7] wire [11:0] io_refill_addr_0; // @[MSHR.scala:12:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[MSHR.scala:12:7] wire [5:0] io_meta_write_bits_idx_0; // @[MSHR.scala:12:7] wire [3:0] io_meta_write_bits_way_en_0; // @[MSHR.scala:12:7] wire io_meta_write_valid_0; // @[MSHR.scala:12:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7] wire [19:0] io_replay_bits_old_meta_tag_0; // @[MSHR.scala:12:7] wire [39:0] io_replay_bits_addr_0; // @[MSHR.scala:12:7] wire [6:0] io_replay_bits_tag_0; // @[MSHR.scala:12:7] wire [4:0] io_replay_bits_cmd_0; // @[MSHR.scala:12:7] wire [1:0] io_replay_bits_size_0; // @[MSHR.scala:12:7] wire io_replay_bits_signed_0; // @[MSHR.scala:12:7] wire [63:0] io_replay_bits_data_0; // @[MSHR.scala:12:7] wire [7:0] io_replay_bits_mask_0; // @[MSHR.scala:12:7] wire io_replay_bits_tag_match_0; // @[MSHR.scala:12:7] wire [3:0] io_replay_bits_way_en_0; // @[MSHR.scala:12:7] wire [4:0] io_replay_bits_sdq_id_0; // @[MSHR.scala:12:7] wire io_replay_valid_0; // @[MSHR.scala:12:7] wire [19:0] io_wb_req_bits_tag_0; // @[MSHR.scala:12:7] wire [5:0] io_wb_req_bits_idx_0; // @[MSHR.scala:12:7] wire [2:0] io_wb_req_bits_param_0; // @[MSHR.scala:12:7] wire [3:0] io_wb_req_bits_way_en_0; // @[MSHR.scala:12:7] wire io_wb_req_valid_0; // @[MSHR.scala:12:7] wire io_req_pri_rdy_0; // @[MSHR.scala:12:7] wire io_req_sec_rdy_0; // @[MSHR.scala:12:7] wire io_idx_match_0; // @[MSHR.scala:12:7] wire io_probe_rdy_0; // @[MSHR.scala:12:7] reg [3:0] state; // @[MSHR.scala:36:22] reg [39:0] req_addr; // @[MSHR.scala:38:16] reg [6:0] req_tag; // @[MSHR.scala:38:16] reg [4:0] req_cmd; // @[MSHR.scala:38:16] reg [1:0] req_size; // @[MSHR.scala:38:16] reg req_signed; // @[MSHR.scala:38:16] reg [63:0] req_data; // @[MSHR.scala:38:16] reg [7:0] req_mask; // @[MSHR.scala:38:16] reg req_tag_match; // @[MSHR.scala:38:16] reg [1:0] req_old_meta_coh_state; // @[MSHR.scala:38:16] reg [19:0] req_old_meta_tag; // @[MSHR.scala:38:16] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[MSHR.scala:12:7, :38:16] reg [3:0] req_way_en; // @[MSHR.scala:38:16] assign io_refill_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16] assign io_meta_write_bits_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16] assign io_wb_req_bits_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16] reg [4:0] req_sdq_id; // @[MSHR.scala:38:16] assign req_idx = req_addr[11:6]; // @[MSHR.scala:38:16, :39:25] assign io_meta_write_bits_idx_0 = req_idx; // @[MSHR.scala:12:7, :39:25] assign io_wb_req_bits_idx_0 = req_idx; // @[MSHR.scala:12:7, :39:25] wire [27:0] req_tag_0 = req_addr[39:12]; // @[MSHR.scala:38:16, :40:26] wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[MSHR.scala:38:16, :41:34] wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[MSHR.scala:41:{34,51}] wire [5:0] _idx_match_T = io_req_bits_addr_0[11:6]; // @[MSHR.scala:12:7, :42:47] wire idx_match = req_idx == _idx_match_T; // @[MSHR.scala:39:25, :42:{27,47}] wire [5:0] _probe_idx_match_T = io_probe_addr_0[11:6]; // @[MSHR.scala:12:7, :43:50] wire probe_idx_match = req_idx == _probe_idx_match_T; // @[MSHR.scala:39:25, :43:{33,50}] reg [1:0] new_coh_state; // @[MSHR.scala:45:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[MSHR.scala:38:16] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[MSHR.scala:142:59] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[MSHR.scala:142:59] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 \| _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 \| _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[MSHR.scala:12:7] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_cmd == 5'h1; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_cmd == 5'h11; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T \| _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_cmd == 5'h7; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 \| _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_cmd == 5'h4; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_cmd == 5'h9; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_cmd == 5'hA; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_cmd == 5'hB; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 \| _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 \| _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 \| _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_cmd == 5'h8; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_cmd == 5'hC; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_cmd == 5'hD; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_cmd == 5'hE; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_cmd == 5'hF; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 \| _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 \| _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 \| _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 \| _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 \| _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 \| _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 \| _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 \| _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 \| _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 \| _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 \| _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 \| _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 \| _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 \| _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 \| _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 \| _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 \| _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_cmd == 5'h3; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 \| _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_cmd == 5'h6; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 \| _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[MSHR.scala:45:24] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 \| _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 \| _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 \| _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 \| _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 \| _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 \| _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T \| _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 \| _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 \| _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 \| _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 \| _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 \| _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 \| _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 \| _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 \| _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 \| _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 \| _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 \| _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 \| _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 \| _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 \| _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 \| _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 \| _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 \| _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 \| _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 \| _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 \| _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 \| _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 \| _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 \| _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[MSHR.scala:12:7] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] wire [1:0] coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T \| _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 \| _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 \| _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 \| _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 \| _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 \| _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 \| _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 \| _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 \| _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 \| _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 \| _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 \| _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 \| _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 \| _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 \| _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 \| _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 \| _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 \| _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 \| _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 \| _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 \| _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 \| _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 \| _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 \| _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[MSHR.scala:45:24] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 \| _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 \| _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 \| _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 \| _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 \| _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 \| _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_bits_cmd_0 == 5'h1; // @[MSHR.scala:12:7] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_bits_cmd_0 == 5'h11; // @[MSHR.scala:12:7] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T \| _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_bits_cmd_0 == 5'h7; // @[MSHR.scala:12:7] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 \| _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_bits_cmd_0 == 5'h4; // @[MSHR.scala:12:7] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_bits_cmd_0 == 5'h9; // @[MSHR.scala:12:7] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_bits_cmd_0 == 5'hA; // @[MSHR.scala:12:7] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_bits_cmd_0 == 5'hB; // @[MSHR.scala:12:7] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 \| _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 \| _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 \| _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_bits_cmd_0 == 5'h8; // @[MSHR.scala:12:7] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_bits_cmd_0 == 5'hC; // @[MSHR.scala:12:7] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_bits_cmd_0 == 5'hD; // @[MSHR.scala:12:7] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_bits_cmd_0 == 5'hE; // @[MSHR.scala:12:7] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_bits_cmd_0 == 5'hF; // @[MSHR.scala:12:7] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 \| _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 \| _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 \| _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 \| _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 \| _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 \| _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 \| _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 \| _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 \| _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 \| _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 \| _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 \| _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 \| _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 \| _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 \| _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 \| _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 \| _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_bits_cmd_0 == 5'h3; // @[MSHR.scala:12:7] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _r_c_cat_T_46; // @[Consts.scala:91:54] assign _r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 \| _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_bits_cmd_0 == 5'h6; // @[MSHR.scala:12:7] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 \| _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[MSHR.scala:45:24] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 \| _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 \| _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 \| _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 \| _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 \| _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 \| _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T \| _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 \| _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 \| _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 \| _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 \| _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 \| _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 \| _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 \| _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 \| _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 \| _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 \| _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 \| _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 \| _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 \| _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 \| _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 \| _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 \| _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 \| _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 \| _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 \| _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 \| _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 \| _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 \| _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 \| _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 \| _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 \| _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T \| _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 \| _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 \| _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 \| _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 \| _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 \| _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 \| _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 \| _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 \| _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 \| _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 \| _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 \| _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 \| _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 \| _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 \| _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 \| _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 \| _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 \| _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 \| _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 \| _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 \| _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 \| _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 \| _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 \| _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_bits_cmd_0 : req_cmd; // @[MSHR.scala:12:7, :38:16] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[MSHR.scala:12:7] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[MSHR.scala:12:7] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & io_mem_grant_valid_0; // @[MSHR.scala:12:7] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire _GEN_27 = state == 4'h1; // @[MSHR.scala:36:22] wire _sec_rdy_T; // @[package.scala:16:47] assign _sec_rdy_T = _GEN_27; // @[package.scala:16:47] wire _io_probe_rdy_T_3; // @[package.scala:16:47] assign _io_probe_rdy_T_3 = _GEN_27; // @[package.scala:16:47] assign _io_wb_req_valid_T = _GEN_27; // @[MSHR.scala:153:28] wire _T_11 = state == 4'h2; // @[MSHR.scala:36:22] wire _sec_rdy_T_1; // @[package.scala:16:47] assign _sec_rdy_T_1 = _T_11; // @[package.scala:16:47] wire _io_probe_rdy_T_4; // @[package.scala:16:47] assign _io_probe_rdy_T_4 = _T_11; // @[package.scala:16:47] wire _T_9 = state == 4'h3; // @[MSHR.scala:36:22] wire _sec_rdy_T_2; // @[package.scala:16:47] assign _sec_rdy_T_2 = _T_9; // @[package.scala:16:47] wire _io_probe_rdy_T_5; // @[package.scala:16:47] assign _io_probe_rdy_T_5 = _T_9; // @[package.scala:16:47] wire _io_meta_write_valid_T_1; // @[package.scala:16:47] assign _io_meta_write_valid_T_1 = _T_9; // @[package.scala:16:47] wire _io_meta_write_bits_data_coh_T; // @[MSHR.scala:149:44] assign _io_meta_write_bits_data_coh_T = _T_9; // @[MSHR.scala:149:44] wire _sec_rdy_T_3 = _sec_rdy_T \| _sec_rdy_T_1; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_4 = _sec_rdy_T_3 \| _sec_rdy_T_2; // @[package.scala:16:47, :81:59] wire _GEN_28 = state == 4'h4; // @[MSHR.scala:36:22] wire _sec_rdy_T_5; // @[package.scala:16:47] assign _sec_rdy_T_5 = _GEN_28; // @[package.scala:16:47] wire _can_finish_T_1; // @[package.scala:16:47] assign _can_finish_T_1 = _GEN_28; // @[package.scala:16:47] wire _io_mem_acquire_valid_T; // @[MSHR.scala:161:33] assign _io_mem_acquire_valid_T = _GEN_28; // @[MSHR.scala:161:33] wire _sec_rdy_T_6 = state == 4'h5; // @[MSHR.scala:36:22] wire _sec_rdy_T_7 = _sec_rdy_T_5 \| _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = ~cmd_requires_second_acquire; // @[MSHR.scala:61:23] wire _sec_rdy_T_9 = _sec_rdy_T_7 & _sec_rdy_T_8; // @[MSHR.scala:60:65, :61:23] wire _sec_rdy_T_10 = ~refill_done; // @[MSHR.scala:61:55] wire _sec_rdy_T_11 = _sec_rdy_T_9 & _sec_rdy_T_10; // @[MSHR.scala:60:65, :61:{52,55}] wire _sec_rdy_T_12 = _sec_rdy_T_4 \| _sec_rdy_T_11; // @[MSHR.scala:59:56, :61:52] wire sec_rdy = idx_match & _sec_rdy_T_12; // @[MSHR.scala:42:27, :58:27, :59:56] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[MSHR.scala:12:7, :64:39] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & sec_rdy; // @[MSHR.scala:12:7, :58:27, :64:75] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T \| _rpq_io_enq_valid_T_1; // @[MSHR.scala:64:{39,57,75}] wire _rpq_io_enq_valid_T_3 = io_req_bits_cmd_0 == 5'h2; // @[MSHR.scala:12:7] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 \| _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[MSHR.scala:64:90] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[MSHR.scala:64:{57,87,90}] wire _T_19 = state == 4'h8; // @[MSHR.scala:36:22, :66:49] wire _rpq_io_deq_ready_T; // @[MSHR.scala:66:49] assign _rpq_io_deq_ready_T = _T_19; // @[MSHR.scala:66:49] wire _io_replay_valid_T; // @[MSHR.scala:168:28] assign _io_replay_valid_T = _T_19; // @[MSHR.scala:66:49, :168:28] wire _rpq_io_deq_ready_T_4; // @[MSHR.scala:176:48] assign _rpq_io_deq_ready_T_4 = _T_19; // @[MSHR.scala:66:49, :176:48] wire _rpq_io_deq_ready_T_1 = io_replay_ready_0 & _rpq_io_deq_ready_T; // @[MSHR.scala:12:7, :66:{40,49}] wire _rpq_io_deq_ready_T_2 = ~(\|state); // @[MSHR.scala:36:22, :66:75] wire _rpq_io_deq_ready_T_3 = _rpq_io_deq_ready_T_1 \| _rpq_io_deq_ready_T_2; // @[MSHR.scala:66:{40,66,75}] reg acked; // @[MSHR.scala:68:18] wire _io_meta_write_valid_T = state == 4'h6; // @[MSHR.scala:36:22, :78:15] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_req_bits_old_meta_coh_state_0}; // @[MSHR.scala:12:7] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[MSHR.scala:142:59] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[MSHR.scala:142:59] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 \| _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 \| _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, io_req_bits_old_meta_coh_state_0}; // @[MSHR.scala:12:7] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 \| _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 \| _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 \| _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 \| _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 \| _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 \| _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire [3:0] _state_T = {2'h0, ~needs_wb, 1'h1}; // @[MSHR.scala:122:19] wire _can_finish_T = ~(\|state); // @[MSHR.scala:36:22, :66:75] wire can_finish = _can_finish_T \| _can_finish_T_1; // @[package.scala:16:47, :81:59] wire _grantackq_io_enq_valid_T = io_mem_grant_bits_opcode_0[2]; // @[MSHR.scala:12:7] wire _grantackq_io_enq_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[MSHR.scala:12:7] wire _grantackq_io_enq_valid_T_2 = ~_grantackq_io_enq_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantackq_io_enq_valid_T_3 = _grantackq_io_enq_valid_T & _grantackq_io_enq_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire _grantackq_io_enq_valid_T_4 = refill_done & _grantackq_io_enq_valid_T_3; // @[MSHR.scala:128:41] assign _io_mem_finish_valid_T = _grantackq_io_deq_valid & can_finish; // @[MSHR.scala:126:25, :130:49] assign io_mem_finish_valid_0 = _io_mem_finish_valid_T; // @[MSHR.scala:12:7, :130:49] wire _grantackq_io_deq_ready_T = io_mem_finish_ready_0 & can_finish; // @[MSHR.scala:12:7, :132:49] wire _io_idx_match_T = \|state; // @[MSHR.scala:36:22, :66:75, :134:26] assign _io_idx_match_T_1 = _io_idx_match_T & idx_match; // @[MSHR.scala:42:27, :134:{26,41}] assign io_idx_match_0 = _io_idx_match_T_1; // @[MSHR.scala:12:7, :134:41] wire [39:0] _io_refill_addr_T = {req_block_addr[39:12], req_block_addr[11:0] \| refill_address_inc}; // @[MSHR.scala:41:51, :136:36] assign io_refill_addr_0 = _io_refill_addr_T[11:0]; // @[MSHR.scala:12:7, :136:{18,36}] assign io_tag_0 = req_tag_0[19:0]; // @[MSHR.scala:12:7, :40:26, :137:10] assign _io_req_pri_rdy_T = ~(\|state); // @[MSHR.scala:36:22, :66:75, :138:27] assign io_req_pri_rdy_0 = _io_req_pri_rdy_T; // @[MSHR.scala:12:7, :138:27] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[MSHR.scala:58:27, :63:19, :139:29] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[MSHR.scala:12:7, :139:29] reg [1:0] meta_hazard; // @[MSHR.scala:141:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[MSHR.scala:141:28, :142:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[MSHR.scala:142:59] wire _io_probe_rdy_T = \|state; // @[MSHR.scala:36:22, :66:75, :144:27] wire _io_probe_rdy_T_1 = _io_probe_rdy_T & probe_idx_match; // @[MSHR.scala:43:33, :144:{27,41}] wire _io_probe_rdy_T_2 = ~_io_probe_rdy_T_1; // @[MSHR.scala:144:{19,41}] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_3 \| _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 \| _io_probe_rdy_T_5; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = ~_io_probe_rdy_T_7; // @[MSHR.scala:144:65] wire _io_probe_rdy_T_9 = meta_hazard == 2'h0; // @[MSHR.scala:141:28, :144:117] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_8 & _io_probe_rdy_T_9; // @[MSHR.scala:144:{65,102,117}] assign _io_probe_rdy_T_11 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_10; // @[MSHR.scala:144:{19,61,102}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[MSHR.scala:12:7, :144:61] assign _io_meta_write_valid_T_2 = _io_meta_write_valid_T \| _io_meta_write_valid_T_1; // @[package.scala:16:47, :81:59] assign io_meta_write_valid_0 = _io_meta_write_valid_T_2; // @[MSHR.scala:12:7] assign _io_meta_write_bits_data_coh_T_1_state = _io_meta_write_bits_data_coh_T ? coh_on_clear_state : new_coh_state; // @[MSHR.scala:45:24, :149:{37,44}] assign io_meta_write_bits_data_coh_state_0 = _io_meta_write_bits_data_coh_T_1_state; // @[MSHR.scala:12:7, :149:37] assign io_wb_req_valid_0 = _io_wb_req_valid_T; // @[MSHR.scala:12:7, :153:28] assign _io_mem_acquire_valid_T_1 = _io_mem_acquire_valid_T & _grantackq_io_enq_ready; // @[MSHR.scala:126:25, :161:{33,50}] assign io_mem_acquire_valid_0 = _io_mem_acquire_valid_T_1; // @[MSHR.scala:12:7, :161:50] wire [25:0] _GEN_29 = {io_tag_0, req_idx}; // @[MSHR.scala:12:7, :39:25, :164:48] wire [25:0] _io_mem_acquire_bits_T; // @[MSHR.scala:164:48] assign _io_mem_acquire_bits_T = _GEN_29; // @[MSHR.scala:164:48] wire [25:0] io_replay_bits_addr_hi; // @[MSHR.scala:170:29] assign io_replay_bits_addr_hi = _GEN_29; // @[MSHR.scala:164:48, :170:29] wire [31:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[MSHR.scala:41:51, :164:{48,66}] wire [31:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[MSHR.scala:164:66] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[31:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 \| _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 \| _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42] wire [31:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_26 = _io_mem_acquire_bits_T_1 ^ 32'h80000000; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 \| _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[MSHR.scala:164:66] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[MSHR.scala:164:66] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[MSHR.scala:164:66] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] assign _io_replay_valid_T_1 = _io_replay_valid_T & _rpq_io_deq_valid; // @[MSHR.scala:63:19, :168:{28,44}] assign io_replay_valid_0 = _io_replay_valid_T_1; // @[MSHR.scala:12:7, :168:44] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[MSHR.scala:63:19, :170:67] wire [31:0] _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[MSHR.scala:170:{29,67}] assign io_replay_bits_addr_0 = {8'h0, _io_replay_bits_addr_T_1}; // @[MSHR.scala:12:7, :170:{23,29}] wire _state_T_1 = ~_rpq_io_deq_valid; // @[MSHR.scala:63:19, :71:34, :174:26] reg state_REG; // @[MSHR.scala:174:25] wire [3:0] _state_T_2 = state_REG ? 4'h0 : state; // @[MSHR.scala:36:22, :174:{17,25}] wire _rpq_io_deq_ready_T_5 = io_replay_ready_0 & _rpq_io_deq_ready_T_4; // @[MSHR.scala:12:7, :176:{39,48}] wire _T_7 = _sec_rdy_T_6 & refill_done; // @[MSHR.scala:81:33] wire _T_15 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[MSHR.scala:12:7, :97:24] always @(posedge clock) begin // @[MSHR.scala:12:7] if (reset) begin // @[MSHR.scala:12:7] state <= 4'h0; // @[MSHR.scala:36:22] new_coh_state <= 2'h0; // @[MSHR.scala:45:24] r_counter <= 9'h0; // @[Edges.scala:229:27] meta_hazard <= 2'h0; // @[MSHR.scala:141:28] end else begin // @[MSHR.scala:12:7] if (_T_19 & ~_rpq_io_deq_valid) // @[MSHR.scala:63:19, :66:49, :71:34, :173:31] state <= _state_T_2; // @[MSHR.scala:36:22, :174:17] else if (_rpq_io_enq_valid_T) // @[MSHR.scala:64:39] state <= io_req_bits_tag_match_0 ? {2'h1, is_hit, 1'h0} : _state_T; // @[MSHR.scala:12:7, :36:22, :112:34, :113:21, :115:15, :118:15, :122:{13,19}] else if (io_wb_req_ready_0 & io_wb_req_valid_0) // @[Decoupled.scala:51:35] state <= 4'h2; // @[MSHR.scala:36:22] else if (_T_11 & io_wb_req_ready_0 & acked) // @[MSHR.scala:12:7, :68:18, :91:{29,48}] state <= 4'h3; // @[MSHR.scala:36:22] else if (_T_9 & io_meta_write_ready_0) // @[MSHR.scala:12:7, :88:32] state <= 4'h4; // @[MSHR.scala:36:22] else if (io_mem_acquire_ready_0 & io_mem_acquire_valid_0) // @[Decoupled.scala:51:35] state <= 4'h5; // @[MSHR.scala:36:22] else if (_T_7) // @[MSHR.scala:81:33] state <= 4'h6; // @[MSHR.scala:36:22] else if (_io_meta_write_valid_T & io_meta_write_ready_0) // @[MSHR.scala:12:7, :78:36] state <= 4'h7; // @[MSHR.scala:36:22] else if (state == 4'h7) // @[MSHR.scala:36:22, :74:15] state <= 4'h8; // @[MSHR.scala:36:22] else if (_T_19 & ~_rpq_io_deq_valid) // @[MSHR.scala:63:19, :66:49, :71:{31,34}] state <= 4'h0; // @[MSHR.scala:36:22] if (_rpq_io_enq_valid_T) // @[MSHR.scala:64:39] new_coh_state <= io_req_bits_tag_match_0 ? (is_hit ? coh_on_hit_state : io_req_bits_old_meta_coh_state_0) : 2'h0; // @[MSHR.scala:12:7, :45:24, :112:34, :113:21, :114:17, :117:17, :121:15] else if (_T_15 & is_hit_again) // @[MSHR.scala:81:49, :97:{24,43}, :102:25, :103:15] new_coh_state <= dirtier_coh_state; // @[MSHR.scala:45:24] else if (_T_7) // @[MSHR.scala:81:33] new_coh_state <= coh_on_grant_state; // @[MSHR.scala:45:24] if (io_mem_grant_valid_0) // @[MSHR.scala:12:7] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (io_meta_write_ready_0 & io_meta_write_valid_0) // @[Decoupled.scala:51:35] meta_hazard <= 2'h1; // @[MSHR.scala:141:28] else if (\|meta_hazard) // @[MSHR.scala:141:28, :142:21] meta_hazard <= _meta_hazard_T_1; // @[MSHR.scala:141:28, :142:59] end if (_rpq_io_enq_valid_T) begin // @[MSHR.scala:64:39] req_addr <= io_req_bits_addr_0; // @[MSHR.scala:12:7, :38:16] req_tag <= io_req_bits_tag_0; // @[MSHR.scala:12:7, :38:16] req_cmd <= io_req_bits_cmd_0; // @[MSHR.scala:12:7, :38:16] req_size <= io_req_bits_size_0; // @[MSHR.scala:12:7, :38:16] req_signed <= io_req_bits_signed_0; // @[MSHR.scala:12:7, :38:16] req_data <= io_req_bits_data_0; // @[MSHR.scala:12:7, :38:16] req_mask <= io_req_bits_mask_0; // @[MSHR.scala:12:7, :38:16] req_tag_match <= io_req_bits_tag_match_0; // @[MSHR.scala:12:7, :38:16] req_old_meta_coh_state <= io_req_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7, :38:16] req_old_meta_tag <= io_req_bits_old_meta_tag_0; // @[MSHR.scala:12:7, :38:16] req_way_en <= io_req_bits_way_en_0; // @[MSHR.scala:12:7, :38:16] req_sdq_id <= io_req_bits_sdq_id_0; // @[MSHR.scala:12:7, :38:16] end else if (_T_15) // @[MSHR.scala:97:24] req_cmd <= dirtier_cmd; // @[MSHR.scala:38:16] acked <= ~_rpq_io_enq_valid_T & (io_mem_grant_valid_0 \| acked); // @[MSHR.scala:12:7, :64:39, :68:18, :69:{29,37}, :106:43, :108:11] state_REG <= _state_T_1; // @[MSHR.scala:174:{25,26}] always @(posedge) Queue16_ShuttleMSHRReq_2 rpq ( // @[MSHR.scala:63:19] .clock (clock), .reset (reset), .io_enq_ready (_rpq_io_enq_ready), .io_enq_valid (_rpq_io_enq_valid_T_7), // @[MSHR.scala:64:87] .io_enq_bits_addr (io_req_bits_addr_0), // @[MSHR.scala:12:7] .io_enq_bits_tag (io_req_bits_tag_0), // @[MSHR.scala:12:7] .io_enq_bits_cmd (io_req_bits_cmd_0), // @[MSHR.scala:12:7] .io_enq_bits_size (io_req_bits_size_0), // @[MSHR.scala:12:7] .io_enq_bits_signed (io_req_bits_signed_0), // @[MSHR.scala:12:7] .io_enq_bits_data (io_req_bits_data_0), // @[MSHR.scala:12:7] .io_enq_bits_mask (io_req_bits_mask_0), // @[MSHR.scala:12:7] .io_enq_bits_tag_match (io_req_bits_tag_match_0), // @[MSHR.scala:12:7] .io_enq_bits_old_meta_coh_state (io_req_bits_old_meta_coh_state_0), // @[MSHR.scala:12:7] .io_enq_bits_old_meta_tag (io_req_bits_old_meta_tag_0), // @[MSHR.scala:12:7] .io_enq_bits_way_en (io_req_bits_way_en_0), // @[MSHR.scala:12:7] .io_enq_bits_sdq_id (io_req_bits_sdq_id_0), // @[MSHR.scala:12:7] .io_deq_ready (_rpq_io_deq_ready_T_5), // @[MSHR.scala:176:39] .io_deq_valid (_rpq_io_deq_valid), .io_deq_bits_addr (_rpq_io_deq_bits_addr), .io_deq_bits_tag (io_replay_bits_tag_0), .io_deq_bits_cmd (io_replay_bits_cmd_0), .io_deq_bits_size (io_replay_bits_size_0), .io_deq_bits_signed (io_replay_bits_signed_0), .io_deq_bits_data (io_replay_bits_data_0), .io_deq_bits_mask (io_replay_bits_mask_0), .io_deq_bits_tag_match (io_replay_bits_tag_match_0), .io_deq_bits_old_meta_coh_state (io_replay_bits_old_meta_coh_state_0), .io_deq_bits_old_meta_tag (io_replay_bits_old_meta_tag_0), .io_deq_bits_way_en (io_replay_bits_way_en_0), .io_deq_bits_sdq_id (io_replay_bits_sdq_id_0) ); // @[MSHR.scala:63:19] Queue1_TLBundleE_a32d64s3k3z4c_2 grantackq ( // @[MSHR.scala:126:25] .clock (clock), .reset (reset), .io_enq_ready (_grantackq_io_enq_ready), .io_enq_valid (_grantackq_io_enq_valid_T_4), // @[MSHR.scala:128:41] .io_enq_bits_sink (grantackq_io_enq_bits_e_sink), // @[Edges.scala:451:17] .io_deq_ready (_grantackq_io_deq_ready_T), // @[MSHR.scala:132:49] .io_deq_valid (_grantackq_io_deq_valid), .io_deq_bits_sink (io_mem_finish_bits_sink_0) ); // @[MSHR.scala:126:25] assign io_req_pri_rdy = io_req_pri_rdy_0; // @[MSHR.scala:12:7] assign io_req_sec_rdy = io_req_sec_rdy_0; // @[MSHR.scala:12:7] assign io_idx_match = io_idx_match_0; // @[MSHR.scala:12:7] assign io_tag = io_tag_0; // @[MSHR.scala:12:7] assign io_mem_acquire_valid = io_mem_acquire_valid_0; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_param = io_mem_acquire_bits_param_0; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_address = io_mem_acquire_bits_address_0; // @[MSHR.scala:12:7] assign io_mem_finish_valid = io_mem_finish_valid_0; // @[MSHR.scala:12:7] assign io_mem_finish_bits_sink = io_mem_finish_bits_sink_0; // @[MSHR.scala:12:7] assign io_refill_way_en = io_refill_way_en_0; // @[MSHR.scala:12:7] assign io_refill_addr = io_refill_addr_0; // @[MSHR.scala:12:7] assign io_meta_write_valid = io_meta_write_valid_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_idx = io_meta_write_bits_idx_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_way_en = io_meta_write_bits_way_en_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_tag = io_meta_write_bits_tag_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_data_coh_state = io_meta_write_bits_data_coh_state_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_data_tag = io_meta_write_bits_data_tag_0; // @[MSHR.scala:12:7] assign io_replay_valid = io_replay_valid_0; // @[MSHR.scala:12:7] assign io_replay_bits_addr = io_replay_bits_addr_0; // @[MSHR.scala:12:7] assign io_replay_bits_tag = io_replay_bits_tag_0; // @[MSHR.scala:12:7] assign io_replay_bits_cmd = io_replay_bits_cmd_0; // @[MSHR.scala:12:7] assign io_replay_bits_size = io_replay_bits_size_0; // @[MSHR.scala:12:7] assign io_replay_bits_signed = io_replay_bits_signed_0; // @[MSHR.scala:12:7] assign io_replay_bits_data = io_replay_bits_data_0; // @[MSHR.scala:12:7] assign io_replay_bits_mask = io_replay_bits_mask_0; // @[MSHR.scala:12:7] assign io_replay_bits_tag_match = io_replay_bits_tag_match_0; // @[MSHR.scala:12:7] assign io_replay_bits_old_meta_coh_state = io_replay_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7] assign io_replay_bits_old_meta_tag = io_replay_bits_old_meta_tag_0; // @[MSHR.scala:12:7] assign io_replay_bits_way_en = io_replay_bits_way_en_0; // @[MSHR.scala:12:7] assign io_replay_bits_sdq_id = io_replay_bits_sdq_id_0; // @[MSHR.scala:12:7] assign io_wb_req_valid = io_wb_req_valid_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_tag = io_wb_req_bits_tag_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_idx = io_wb_req_bits_idx_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_param = io_wb_req_bits_param_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_way_en = io_wb_req_bits_way_en_0; // @[MSHR.scala:12:7] assign io_probe_rdy = io_probe_rdy_0; // @[MSHR.scala:12:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a32d64s6k3z3c( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_e_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_out_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeIn_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_e_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_in_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [63:0] auto_in_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [63:0] auto_out_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [63:0] nodeIn_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [7:0] auto_in_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [7:0] nodeIn_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [5:0] auto_in_b_bits_source = 6'h10; // @[Nodes.scala:27:25] wire [5:0] auto_out_b_bits_source = 6'h10; // @[Nodes.scala:27:25] wire [5:0] nodeIn_b_bits_source = 6'h10; // @[Nodes.scala:27:25] wire [5:0] nodeOut_b_bits_source = 6'h10; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_out_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeIn_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeOut_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign nodeOut_c_valid = nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_opcode = nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_param = nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_size = nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_source = nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_address = nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_data = nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_corrupt = nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign nodeOut_e_valid = nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_e_bits_sink = nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_param = nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_address = nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_c_ready = nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_41 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a32d64s6k3z3c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a32d64s6k3z3c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Debug.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBFanout, APBToTL} import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule} import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError} import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode} import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.rocket.{CSRs, Instructions} import freechips.rocketchip.tile.MaxHartIdBits import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar} import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle} import freechips.rocketchip.util.SeqBoolBitwiseOps import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.BooleanToAugmentedBoolean object DsbBusConsts { def sbAddrWidth = 12 def sbIdWidth = 10 } object DsbRegAddrs{ // These are used by the ROM. def HALTED = 0x100 def GOING = 0x104 def RESUMING = 0x108 def EXCEPTION = 0x10C def WHERETO = 0x300 // This needs to be aligned for up to lq/sq // This shows up in HartInfo, and needs to be aligned // to enable up to LQ/SQ instructions. def DATA = 0x380 // We want DATA to immediately follow PROGBUF so that we can // use them interchangeably. Leave another slot if there is an // implicit ebreak. def PROGBUF(cfg:DebugModuleParams) = { val tmp = DATA - (cfg.nProgramBufferWords 4) if (cfg.hasImplicitEbreak) (tmp - 4) else tmp } // This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF. def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 } // We want abstract to be immediately before PROGBUF // because we auto-generate 2 (or 5) instructions. def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4) def FLAGS = 0x400 def ROMBASE = 0x800 } /** Enumerations used both in the hardware * and in the configuration specification. / object DebugModuleAccessType extends scala.Enumeration { type DebugModuleAccessType = Value val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value } object DebugAbstractCommandError extends scala.Enumeration { type DebugAbstractCommandError = Value val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value } object DebugAbstractCommandType extends scala.Enumeration { type DebugAbstractCommandType = Value val AccessRegister, QuickAccess = Value } /* Parameters exposed to the top-level design, set based on * external requirements, etc. * * This object checks that the parameters conform to the * full specification. The implementation which receives this * object can perform more checks on what that implementation * actually supports. * @param nComponents Number of components to support debugging. * @param baseAddress Base offest for debugEntry and debugException * @param nDMIAddrSize Size of the Debug Bus Address * @param nAbstractDataWords Number of 32-bit words for Abstract Commands * @param nProgamBufferWords Number of 32-bit words for Program Buffer * @param hasBusMaster Whether or not a bus master should be included * @param clockGate Whether or not to use dmactive as the clockgate for debug module * @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic. * @param supportQuickAccess Whether or not to support the quick access command. * @param supportHartArray Whether or not to implement the hart array register (if >1 hart). * @param nHaltGroups Number of halt groups * @param nExtTriggers Number of external triggers * @param hasHartResets Feature to reset all the currently selected harts * @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak * @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset. / case class DebugModuleParams ( baseAddress : BigInt = BigInt(0), nDMIAddrSize : Int = 7, nProgramBufferWords: Int = 16, nAbstractDataWords : Int = 4, nScratch : Int = 1, hasBusMaster : Boolean = false, clockGate : Boolean = true, maxSupportedSBAccess : Int = 32, supportQuickAccess : Boolean = false, supportHartArray : Boolean = true, nHaltGroups : Int = 1, nExtTriggers : Int = 0, hasHartResets : Boolean = false, hasImplicitEbreak : Boolean = false, hasAuthentication : Boolean = false, crossingHasSafeReset : Boolean = true ) { require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}") require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}") require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}") require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}") require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}") if (supportQuickAccess) { // TODO: Check that quick access requirements are met. } def address = AddressSet(baseAddress, 0xFFF) /* the base address of DM / def atzero = (baseAddress == 0) /* The number of generated instructions * * When the base address is not zero, we need more instruction also, * more dscratch registers) to load/store memory mapped data register * because they may no longer be directly addressible with x0 + 12-bit imm / def nAbstractInstructions = if (atzero) 2 else 5 def debugEntry: BigInt = baseAddress + 0x800 def debugException: BigInt = baseAddress + 0x808 def nDscratch: Int = if (atzero) 1 else 2 } object DefaultDebugModuleParams { def apply(xlen:Int /TODO , val configStringAddr: Int/): DebugModuleParams = { new DebugModuleParams().copy( nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4), maxSupportedSBAccess = xlen ) } } case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams())) /* Functional parameters exposed to the design configuration. * * hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping. * hartSelToHartId: Provide inverse mapping of the above / case class DebugModuleHartSelFuncs ( hartIdToHartSel : (UInt) => UInt = (x:UInt) => x, hartSelToHartId : (UInt) => UInt = (x:UInt) => x ) case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs()) class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle { val req = Output(UInt(nExtTriggers.W)) val ack = Input(UInt(nExtTriggers.W)) } class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle { val req = Input(UInt(nExtTriggers.W)) val ack = Output(UInt(nExtTriggers.W)) } class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers) val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers) } class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val dmactive = Output(Bool()) val dmAuthWrite = Output(Bool()) val dmAuthRead = Output(Bool()) val dmAuthWdata = Output(UInt(32.W)) val dmAuthBusy = Input(Bool()) val dmAuthRdata = Input(UInt(32.W)) val dmAuthenticated = Input(Bool()) } // ************************************** // Module Interfaces // // ************************************* / Control signals for Inner, generated in Outer * {{{ * run control: resumreq, ackhavereset, halt-on-reset mask * hart select: hasel, hartsel and the hart array mask * }}} / class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /* resume request / val resumereq = Bool() /* hart select / val hartsel = UInt(10.W) /* reset acknowledge / val ackhavereset = Bool() /* hart array enable / val hasel = Bool() /* hart array mask / val hamask = Vec(nComponents, Bool()) /* halt-on-reset mask / val hrmask = Vec(nComponents, Bool()) } /* structure for top-level Debug Module signals which aren't the bus interfaces. / class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /* debug availability status for all harts / val debugUnavail = Input(Vec(nComponents, Bool())) /* reset signal * * for every part of the hardware platform, * including every hart, except for the DM and any * logic required to access the DM / val ndreset = Output(Bool()) /* reset signal for the DM itself / val dmactive = Output(Bool()) /* dmactive acknowlege / val dmactiveAck = Input(Bool()) } // ************************************** // Debug Module // // ************************************* / Parameterized version of the Debug Module defined in the * RISC-V Debug Specification * * DebugModule is a slave to two asynchronous masters: * The Debug Bus (DMI) -- This is driven by an external debugger * * The System Bus -- This services requests from the cores. Generally * this interface should only be active at the request * of the debugger, but the Debug Module may also * provide the default MTVEC since it is mapped * to address 0x0. * * DebugModule is responsible for control registers and RAM, and * Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and * the TL clock. Therefore, it is divided into "Outer" portion (running * off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset). * This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive, * and ndreset to be modified even while the Core is in reset or not being clocked. * Not all reads from the Debugger to the Debug Module will actually complete * in these scenarios either, they will just block until tl_clock and tl_reset * allow them to complete. This is not strictly necessary for * proper debugger functionality. / // Local reg mapper function : Notify when written, but give the value as well. object WNotifyWire { def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = { RegField(n, 0.U, RegWriteFn((valid, data) => { set := valid value := data true.B }), Some(RegFieldDesc(name = name, desc = desc, access = RegFieldAccessType.W))) } } // Local reg mapper function : Notify when accessed either as read or write. object RWNotify { def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = { RegField(n, RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}), RegWriteFn((valid, data) => { wNotify := valid when (valid) {wVal := data} true.B } ), desc) } } // Local reg mapper function : Notify with value when written, take read input as presented. // This allows checking or correcting the write value before storing it in the register field. object WNotifyVal { def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = { RegField(n, rVal, RegWriteFn((valid, data) => { wNotify := valid wVal := data true.B } ), desc) } } class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get val intnode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) val dmiNode = TLRegisterNode ( address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++ AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOW << 2, 4), device = device, beatBytes = 4, executable = false ) lazy val module = new Impl class Impl extends LazyModuleImp(this) { require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts") val nComponents = intnode.out.size def getNComponents = () => nComponents val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart val io = IO(new Bundle { /* structure for top-level Debug Module signals which aren't the bus interfaces. / val ctrl = (new DebugCtrlBundle(nComponents)) /* control signals for Inner, generated in Outer / val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents)) /* debug interruption from Inner to Outer * * contains 2 type of debug interruption causes: * - halt group * - halt-on-reset / val hgDebugInt = Input(Vec(nComponents, Bool())) /* hart reset request to core / val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* authentication support / val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool())) }) val omRegMap = withReset(reset.asAsyncReset) { // FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available) val dmAuthenticated = io.dmAuthenticated.map( dma => ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B) //----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it // can be written even if 'Inner' is not being clocked or is in reset. This allows halting // harts while the rest of the system is in reset. It doesn't really allow any other // register accesses, which will keep returning 'busy' to the debugger interface. val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg") val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val dmactiveWrEn = WireInit(false.B) val ndmresetWrEn = WireInit(false.B) val clrresethaltreqWrEn = WireInit(false.B) val setresethaltreqWrEn = WireInit(false.B) val hartselloWrEn = WireInit(false.B) val haselWrEn = WireInit(false.B) val ackhaveresetWrEn = WireInit(false.B) val hartresetWrEn = WireInit(false.B) val resumereqWrEn = WireInit(false.B) val haltreqWrEn = WireInit(false.B) val dmactive = DMCONTROLReg.dmactive DMCONTROLNxt := DMCONTROLReg when (~dmactive) { DMCONTROLNxt := DMCONTROLReset } .otherwise { when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset } when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask} when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel } when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset } when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq } } // Put this last to override its own effects. when (dmactiveWrEn) { DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive } //----HARTINFO // DATA registers are mapped to memory. The dataaddr field of HARTINFO has only // 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0 // (implying nonexistence according to the Debug Spec). val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields())) if (cfg.atzero) when (dmAuthenticated) { HARTINFORdData.dataaccess := true.B HARTINFORdData.datasize := cfg.nAbstractDataWords.U HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U HARTINFORdData.nscratch := cfg.nScratch.U } //-------------------------------------------------------------- // Hart array mask and window // hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello // HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW //-------------------------------------------------------------- val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) def haWindowSize = 32 // The following need to be declared even if supportHartArray is false due to reference // at compile time by dmiNode.regmap val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELWrEn = WireInit(false.B) val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrEn = WireInit(false.B) /* whether the hart is selected / def hartSelected(hart: Int): Bool = { ((io.innerCtrl.bits.hartsel === hart.U) \|\| (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B)) } val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt)) if (supportHartArray) { val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) HAWINDOWSELNxt := HAWINDOWSELReg when (~dmactive \|\| ~dmAuthenticated) { HAWINDOWSELNxt := HAWINDOWSELReset } .otherwise { when (HAWINDOWSELWrEn) { // Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window if (nComponents > haWindowSize) { HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U } else { HAWINDOWSELNxt.hawindowsel := 0.U } } } val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1 HAWINDOWRdData.maskdata := 0.U // default, overridden below // for each slice,use a hamaskReg to store the selection info for (ii <- 0 until numHAMASKSlices) { val sliceMask = if (nComponents > ((iihaWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist else (BigInt(1)<<(nComponents - (iihaWindowSize))) - 1 // Partial last slice val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt)) when (ii.U === HAWINDOWSELReg.hawindowsel) { HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U } HAMASKNxt.maskdata := HAMASKReg.asUInt when (~dmactive \|\| ~dmAuthenticated) { HAMASKNxt := HAMASKRst }.otherwise { when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { HAMASKNxt.maskdata := HAWINDOWWrData.maskdata } } // drive each slice of hamask with stored HAMASKReg or with new value being written for (jj <- 0 until haWindowSize) { if (((iihaWindowSize) + jj) < nComponents) { val tempWrData = HAWINDOWWrData.maskdata.asBools val tempMaskReg = HAMASKReg.asUInt.asBools when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { hamask(iihaWindowSize + jj) := tempWrData(jj) }.otherwise { hamask(iihaWindowSize + jj) := tempMaskReg(jj) } } } } } //-------------------------------------------------------------- // Halt-on-reset // hrmaskReg is current set of harts that should halt-on-reset // Reset state (dmactive=0) is all zeroes // Bits are set by writing 1 to DMCONTROL.setresethaltreq // Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq // Spec says if both are 1, then clrresethaltreq is executed // hrmask is the halt-on-reset mask which will be sent to inner //-------------------------------------------------------------- val hrmask = Wire(Vec(nComponents, Bool())) val hrmaskNxt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg") hrmaskNxt := hrmaskReg for (component <- 0 until nComponents) { when (~dmactive \|\| ~dmAuthenticated) { hrmaskNxt(component) := false.B }.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) { hrmaskNxt(component) := false.B }.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) { hrmaskNxt(component) := true.B } } hrmask := hrmaskNxt val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq( WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn, RegFieldDesc("dmactive", "debug module active", reset=Some(0))), WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn, RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))), WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn, RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn, RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)), RegField(12), if (nComponents > 1) WNotifyVal(p(MaxHartIdBits), DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn, RegFieldDesc("hartsello", "hart select low", reset=Some(0))) else RegField(1), if (nComponents > 1) RegField(10-p(MaxHartIdBits)) else RegField(9), if (supportHartArray) WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn, RegFieldDesc("hasel", "hart array select", reset=Some(0))) else RegField(1), RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn, RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)), if (cfg.hasHartResets) WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn, RegFieldDesc("hartreset", "hart reset request", reset=Some(0))) else RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn, RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior RegFieldDesc("haltreq", "halt request", reset=Some(0))) )) val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq( RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))), RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))), RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))), RegField(3), RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0))) )) //-------------------------------------------------------------- // DMI register decoder for Outer //-------------------------------------------------------------- // regmap addresses are byte offsets from lowest address def DMI_DMCONTROL_OFFSET = 0 def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2) def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2) def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2) val omRegMap = dmiNode.regmap( DMI_DMCONTROL_OFFSET -> dmControlRegFields, DMI_HARTINFO_OFFSET -> hartinfoRegFields, DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq( WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn, RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil), DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq( WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn, RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil) ) //-------------------------------------------------------------- // Interrupt Registers //-------------------------------------------------------------- val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs") debugIntNxt := debugIntRegs val (intnode_out, _) = intnode.out.unzip for (component <- 0 until nComponents) { intnode_out(component)(0) := debugIntRegs(component) \| io.hgDebugInt(component) } // sends debug interruption to Core when dmcs.haltreq is set, for (component <- 0 until nComponents) { when (~dmactive \|\| ~dmAuthenticated) { debugIntNxt(component) := false.B }. otherwise { when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U) \|\| (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) { debugIntNxt(component) := DMCONTROLWrData.haltreq } } } // Halt request registers are set & cleared by writes to DMCONTROL.haltreq // resumereq also causes the core to execute a 'dret', // so resumereq is passed through to Inner. // hartsel/hasel/hamask must also be used by the DebugModule state machine, // so it is passed to Inner. // These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together. // If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received. // Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent. // Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received. val innerCtrlValid = Wire(Bool()) val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg") val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg") val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg") innerCtrlValid := hartselloWrEn \| resumereqWrEn \| ackhaveresetWrEn \| setresethaltreqWrEn \| clrresethaltreqWrEn \| haselWrEn \| (HAWINDOWWrEn & supportHartArray.B) innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted io.innerCtrl.valid := innerCtrlValid \| innerCtrlValidReg io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello) io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) \| innerCtrlResumeReqReg io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) \| innerCtrlAckHaveResetReg io.innerCtrl.bits.hrmask := hrmask if (supportHartArray) { io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel) io.innerCtrl.bits.hamask := hamask } else { io.innerCtrl.bits.hasel := DontCare io.innerCtrl.bits.hamask := DontCare } io.ctrl.ndreset := DMCONTROLReg.ndmreset io.ctrl.dmactive := DMCONTROLReg.dmactive // hart reset mechanism implementation if (cfg.hasHartResets) { val hartResetNxt = Wire(Vec(nComponents, Bool())) val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt)) for (component <- 0 until nComponents) { hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component) io.hartResetReq.get(component) := hartResetReg(component) } } omRegMap // FIXME: Remove this when withReset is removed }} } // wrap a Outer with a DMIToTL, derived by dmi clock & reset class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar"))) val dmi2tlOpt = (!p(ExportDebug).apb).option({ val dmi2tl = LazyModule(new DMIToTL()) dmiXbar.node := dmi2tl.node dmi2tl }) val apbNodeOpt = p(ExportDebug).apb.option({ val apb2tl = LazyModule(new APBToTL()) val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe)) val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4) val tlError = LazyModule(new TLError(tlErrorParams, buffer=false)) val apbXbar = LazyModule(new APBFanout()) val apbRegs = LazyModule(new APBDebugRegisters()) apbRegs.node := apbXbar.node apb2tl.node := apbXbar.node apb2tlBuffer.node := apb2tl.node dmiXbar.node := apb2tlBuffer.node tlError.node := dmiXbar.node apbXbar.node }) val dmOuter = LazyModule( new TLDebugModuleOuter(device)) val intnode = IntSyncIdentityNode() intnode := IntSyncCrossingSource(alreadyRegistered = true) := dmOuter.intnode val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4)) val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node dmOuter.dmiNode := dmiXbar.node lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.intnode.edges.out.size val io = IO(new Bundle { val dmi_clock = Input(Clock()) val dmi_reset = Input(Reset()) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI / val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p))) // Optional APB Interface is fully diplomatic so is not listed here. val ctrl = new DebugCtrlBundle(nComponents) /* conrol signals for Inner, generated in Outer / val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) /* debug interruption generated in Inner / val hgDebugInt = Input(Vec(nComponents, Bool())) /* hart reset request to core / val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* Authentication signal from core / val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool())) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.dmi_clock childReset := io.dmi_reset override def provideImplicitClockToLazyChildren = true withClockAndReset(childClock, childReset) { dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get } val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync")) dmiBypass.module.io.bypass := ~io.ctrl.dmactive \| ~dmactiveAck io.ctrl <> dmOuter.module.io.ctrl dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) dmOuter.module.io.hgDebugInt := io.hgDebugInt io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}} } } } class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get def getCfg = () => cfg val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 /* dmiNode address set / val dmiNode = TLRegisterNode( // Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++ AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++ AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++ AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))), device = device, beatBytes = 4, executable = false ) val tlNode = TLRegisterNode( address=Seq(cfg.address), device=device, beatBytes=beatBytes, executable=true ) val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL())) // If we want to support custom registers read through Abstract Commands, // provide a place to bring them into the debug module. What this connects // to is up to the implementation. val customNode = new DebugCustomSink() lazy val module = new Impl class Impl extends LazyModuleImp(this){ val nComponents = getNComponents() Annotated.params(this, cfg) val supportHartArray = cfg.supportHartArray & (nComponents > 1) val nExtTriggers = cfg.nExtTriggers val nHaltGroups = if ((nComponents > 1) \| (nExtTriggers > 0)) cfg.nHaltGroups else 0 // no halt groups possible if single hart with no external triggers val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs( hartIdToHartSel = (x) => 0.U, hartSelToHartId = (x) => x ) val io = IO(new Bundle { /* dm reset signal passed in from Outer / val dmactive = Input(Bool()) /* conrol signals for Inner * * it's generated by Outer and comes in / val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents))) /* debug unavail signal passed in from Outer/ val debugUnavail = Input(Vec(nComponents, Bool())) /* debug interruption from Inner to Outer * * contain 2 type of debug interruption causes: * - halt group * - halt-on-reset / val hgDebugInt = Output(Vec(nComponents, Bool())) /* interface for trigger / val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(nComponents, Bool())) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /* Debug Authentication signals from core / val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO()) }) sb2tlOpt.map { sb => sb.module.clock := io.tl_clock sb.module.reset := io.tl_reset sb.module.rf_reset := io.tl_reset } //-------------------------------------------------------------- // Import constants for shorter variable names //-------------------------------------------------------------- import DMI_RegAddrs._ import DsbRegAddrs._ import DsbBusConsts._ //-------------------------------------------------------------- // Sanity Check Configuration For this implementation. //-------------------------------------------------------------- require (cfg.supportQuickAccess == false, "No Quick Access support yet") require ((nHaltGroups > 0) \|\| (nExtTriggers == 0), "External triggers require at least 1 halt group") //-------------------------------------------------------------- // Register & Wire Declarations (which need to be pre-declared) //-------------------------------------------------------------- // run control regs: tracking all the harts // implements: see implementation-specific bits part /* all harts halted status / val haltedBitRegs = Reg(UInt(nComponents.W)) /* all harts resume request status / val resumeReqRegs = Reg(UInt(nComponents.W)) /* all harts have reset status / val haveResetBitRegs = Reg(UInt(nComponents.W)) // default is 1,after resume, resumeAcks get 0 /* all harts resume ack status / val resumeAcks = Wire(UInt(nComponents.W)) // --- regmapper outputs // hart state Id and En // in Hart Bus Access ROM val hartHaltedWrEn = Wire(Bool()) val hartHaltedId = Wire(UInt(sbIdWidth.W)) val hartGoingWrEn = Wire(Bool()) val hartGoingId = Wire(UInt(sbIdWidth.W)) val hartResumingWrEn = Wire(Bool()) val hartResumingId = Wire(UInt(sbIdWidth.W)) val hartExceptionWrEn = Wire(Bool()) val hartExceptionId = Wire(UInt(sbIdWidth.W)) // progbuf and abstract data: byte-addressable control logic // AccessLegal is set only when state = waiting // RdEn and WrEnMaybe : contrl signal drived by DMI bus val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords 4) {false.B} )) val dmiProgramBufferAccessLegal = WireInit(false.B) val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) val dmiAbstractDataAccessLegal = WireInit(false.B) val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) //-------------------------------------------------------------- // Registers coming from 'CONTROL' in Outer //-------------------------------------------------------------- val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B) val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W)) // hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nComponents > 1) { when (~io.dmactive) { selectedHartReg := 0.U }.elsewhen (io.innerCtrl.fire){ selectedHartReg := io.innerCtrl.bits.hartsel } } if (supportHartArray) { val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val hamaskReg = Reg(Vec(nComponents, Bool())) when (~io.dmactive \|\| ~dmAuthenticated) { hamaskReg := hamaskZero }.elsewhen (io.innerCtrl.fire){ hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero) } hamaskFull := hamaskReg } // Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello, // so append it here when (selectedHartReg < nComponents.U) { hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B } io.innerCtrl.ready := true.B // Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write // A hart may be selected by hartsel field or by hart array val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) for (component <- 0 until nComponents ) { hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) \|\| (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B)) } //------------------------------------- // Halt-on-reset logic // hrmask is set in dmOuter and passed in // Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set // Debug interrupt is maintained until the hart enters halted state //------------------------------------- val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } )) val hrDebugInt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegInit(hrReset) val hartIsInResetSync = Wire(Vec(nComponents, Bool())) for (component <- 0 until nComponents) { hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component")) } when (~io.dmactive \|\| ~dmAuthenticated) { hrmaskReg := hrReset }.elsewhen (io.innerCtrl.fire){ hrmaskReg := io.innerCtrl.bits.hrmask } withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } )) when (~io.dmactive \|\| ~dmAuthenticated) { hrDebugIntReg := hrReset }.otherwise { hrDebugIntReg := hrmaskReg & (hartIsInResetSync \| // set debugInt during reset (hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts } hrDebugInt := hrDebugIntReg } //-------------------------------------------------------------- // DMI Registers //-------------------------------------------------------------- //----DMSTATUS val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields())) DMSTATUSRdData.authenticated := dmAuthenticated DMSTATUSRdData.version := 2.U // Version 0.13 io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy) val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq when (dmAuthenticated) { DMSTATUSRdData.hasresethaltreq := true.B DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent // all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ \| _)) when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ \| _) when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set DMSTATUSRdData.allunavail := (io.debugUnavail \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allresumeack := (resumeAcks.asBools \| ~hamaskFull).reduce(_ & _) } } //TODO DMSTATUSRdData.confstrptrvalid := false.B DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B } when(~io.dmactive \|\| ~dmAuthenticated) { haveResetBitRegs := 0.U }.otherwise { when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) { haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) \| hartIsInResetSync.asUInt }.otherwise { haveResetBitRegs := haveResetBitRegs \| hartIsInResetSync.asUInt } } //----DMCS2 (Halt Groups) val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val hgselectWrEn = WireInit(false.B) val hgwriteWrEn = WireInit(false.B) val haltgroupWrEn = WireInit(false.B) val exttriggerWrEn = WireInit(false.B) val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup val hgBits = log2Up(nHaltGroups) // hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned. val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W)))) val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil // assign group index to current seledcted harts for (component <- 0 until nComponents) { when (~io.dmactive \|\| ~dmAuthenticated) { hgParticipateHart(component) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect & hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateHart(component) := DMCS2WrData.haltgroup } } } DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg) if (nExtTriggers > 0) { val hgSelect = Reg(Bool()) when (~io.dmactive \|\| ~dmAuthenticated) { hgSelect := false.B }.otherwise { when (hgselectWrEn) { hgSelect := DMCS2WrData.hgselect } } // assign group index to trigger for (trigger <- 0 until nExtTriggers) { when (~io.dmactive \|\| ~dmAuthenticated) { hgParticipateTrig(trigger) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect & (DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateTrig(trigger) := DMCS2WrData.haltgroup } } } DMCS2RdData.hgselect := hgSelect when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(0) } // If there is only 1 ext trigger, then the exttrigger field is fixed at 0 // Otherwise, instantiate a register with only the number of bits required if (nExtTriggers > 1) { val trigBits = log2Up(nExtTriggers-1) val hgExtTrigger = Reg(UInt(trigBits.W)) when (~io.dmactive \|\| ~dmAuthenticated) { hgExtTrigger := 0.U }.otherwise { when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) { hgExtTrigger := DMCS2WrData.exttrigger } } DMCS2RdData.exttrigger := hgExtTrigger when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger) } } } // Halt group state machine // IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0 // or when any trigin assigned to this hg occurs // FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs // and all trig out in this hg have been acknowledged val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} )) val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked io.extTrigger.foreach {extTrigger => val extTriggerInReq = Wire(Vec(nExtTriggers, Bool())) val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool())) extTriggerInReq := extTrigger.in.req.asBools extTriggerOutAck := extTrigger.out.ack.asBools val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync")) val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync")) for (hg <- 1 to nHaltGroups) { hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ \| _) hgTrigsAllAcked(hg) := (trigOutAck \| hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _) } extTrigger.in.ack := trigInReq.asUInt } for (hg <- 1 to nHaltGroups) { hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U) hgHartsAllHalted(hg) := (haltedBitRegs.asBools \| hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _) when (~io.dmactive \|\| ~dmAuthenticated) { hgFired(hg) := false.B }.elsewhen (~hgFired(hg) & (hgHartFiring(hg) \| hgTrigFiring(hg))) { hgFired(hg) := true.B }.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) { hgFired(hg) := false.B } } // For each hg that has fired, assert debug interrupt to each hart in that hg for (component <- 0 until nComponents) { hgDebugInt(component) := hgFired(hgParticipateHart(component)) } // For each hg that has fired, assert trigger out for all external triggers in that hg io.extTrigger.foreach {extTrigger => val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} )) for (trig <- 0 until nExtTriggers) { extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig)) } extTrigger.out.req := extTriggerOutReq.asUInt } } io.hgDebugInt := hgDebugInt \| hrDebugInt //----HALTSUM* val numHaltedStatus = ((nComponents - 1) / 32) + 1 val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W))) for (ii <- 0 until numHaltedStatus) { when (dmAuthenticated) { haltedStatus(ii) := haltedBitRegs >> (ii32) }.otherwise { haltedStatus(ii) := 0.U } } val haltedSummary = Cat(haltedStatus.map(_.orR).reverse) val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields()) val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5)) val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields()) // Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3 //----ABSTRACTCS val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U val ABSTRACTCSReg = Reg(new ABSTRACTCSFields()) val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg) val ABSTRACTCSRdEn = WireInit(false.B) val ABSTRACTCSWrEnMaybe = WireInit(false.B) val ABSTRACTCSWrEnLegal = WireInit(false.B) val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal // multiple error types // find implement in the state machine part val errorBusy = WireInit(false.B) val errorException = WireInit(false.B) val errorUnsupported = WireInit(false.B) val errorHaltResume = WireInit(false.B) when (~io.dmactive \|\| ~dmAuthenticated) { ABSTRACTCSReg := ABSTRACTCSReset }.otherwise { when (errorBusy){ ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U }.elsewhen (errorException) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U }.elsewhen (errorUnsupported) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U }.elsewhen (errorHaltResume) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U }.otherwise { //W1C when (ABSTRACTCSWrEn){ ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr); } } } // For busy, see below state machine. val abstractCommandBusy = WireInit(true.B) ABSTRACTCSRdData.busy := abstractCommandBusy when (~dmAuthenticated) { // read value must be 0 when not authenticated ABSTRACTCSRdData.datacount := 0.U ABSTRACTCSRdData.progbufsize := 0.U } //---- ABSTRACTAUTO // It is a mask indicating whether datai/probufi have the autoexcution permisson // this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec // first two specify which reg supports autoexec // autoexec is a control signal, meaning there is at least one enabled autoexec reg // when autoexec is set, generate instructions using COMMAND register val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields()) val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg) val ABSTRACTAUTORdEn = WireInit(false.B) val autoexecdataWrEnMaybe = WireInit(false.B) val autoexecprogbufWrEnMaybe = WireInit(false.B) val ABSTRACTAUTOWrEnLegal = WireInit(false.B) when (~io.dmactive \|\| ~dmAuthenticated) { ABSTRACTAUTOReg := ABSTRACTAUTOReset }.otherwise { when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U } when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U } } // Abstract Data access vector(byte-addressable) val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords 4) {false.B} )) dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r \| w} // Program Buffer access vector(byte-addressable) val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r \| w} // at least one word access val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ \|\| _ ) val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ \|\| _) // This will take the shorter of the lists, which is what we want. val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} )) val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} )) (autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 } (autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2} val autoexec = autoexecData.reduce(_ \|\| _) \|\| autoexecProg.reduce(_ \|\| _) //---- COMMAND val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields())) val COMMANDReg = Reg(new COMMANDFields()) val COMMANDWrDataVal = WireInit(0.U(32.W)) val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields())) val COMMANDWrEnMaybe = WireInit(false.B) val COMMANDWrEnLegal = WireInit(false.B) val COMMANDRdEn = WireInit(false.B) val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal val COMMANDRdData = COMMANDReg when (~io.dmactive \|\| ~dmAuthenticated) { COMMANDReg := COMMANDReset }.otherwise { when (COMMANDWrEn) { COMMANDReg := COMMANDWrData } } // --- Abstract Data // These are byte addressible, s.t. the Processor can use // byte-addressible instructions to store to them. val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords4, UInt(8.W))) val abstractDataNxt = WireInit(abstractDataMem) // --- Program Buffer // byte-addressible mem val programBufferMem = Reg(Vec(cfg.nProgramBufferWords4, UInt(8.W))) val programBufferNxt = WireInit(programBufferMem) //-------------------------------------------------------------- // These bits are implementation-specific bits set // by harts executing code. //-------------------------------------------------------------- // Run control logic when (~io.dmactive \|\| ~dmAuthenticated) { haltedBitRegs := 0.U resumeReqRegs := 0.U }.otherwise { //remove those harts in reset resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt) val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId)) val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId)) val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel) when (hartHaltedWrEn) { // add those harts halting and remove those in reset haltedBitRegs := (haltedBitRegs \| hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt) }.elsewhen (hartResumingWrEn) { // remove those harts in reset and those in resume haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) }.otherwise { // remove those harts in reset haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt) } when (hartResumingWrEn) { // remove those harts in resume and those in reset resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) } when (resumereq) { // set all sleceted harts to resumeReq, remove those in reset resumeReqRegs := (resumeReqRegs \| hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt) } } when (resumereq) { // next cycle resumeAcls will be the negation of next cycle resumeReqRegs resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt)) }.otherwise { resumeAcks := ~resumeReqRegs } //---- AUTHDATA val authRdEnMaybe = WireInit(false.B) val authWrEnMaybe = WireInit(false.B) io.auth.map { a => a.dmactive := io.dmactive a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy } val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq( RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))), RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))), RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))), RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))), RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))), RegField(2), RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0))) )) val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq( WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn, RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)), WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn, RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)), WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn, RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)), if (nExtTriggers > 1) WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn, RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true)) else RegField(4) )) val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq( RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))), RegField(4), WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe, RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(1), RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))), RegField(11), RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords))) )) val (sbcsFields, sbAddrFields, sbDataFields): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl => SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p) }.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]))) //-------------------------------------------------------------- // Program Buffer Access (DMI ... System Bus can override) //-------------------------------------------------------------- val omRegMap = dmiNode.regmap( (DMI_DMSTATUS << 2) -> dmstatusRegFields, //TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields, (DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil), (DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"), Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))), (DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"), Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))), (DMI_ABSTRACTCS << 2) -> abstractcsRegFields, (DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq( WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe, RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))), RegField(16-cfg.nAbstractDataWords), WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe, RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))), (DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"), Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe, Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))), (DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i), dmiAbstractDataRdEn(i), dmiAbstractDataWrEnMaybe(i), Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false), (DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i), dmiProgramBufferRdEn(i), dmiProgramBufferWrEnMaybe(i), Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false), (DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"), Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe, Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil), (DMI_SBCS << 2) -> sbcsFields, (DMI_SBDATA0 << 2) -> sbDataFields(0), (DMI_SBDATA1 << 2) -> sbDataFields(1), (DMI_SBDATA2 << 2) -> sbDataFields(2), (DMI_SBDATA3 << 2) -> sbDataFields(3), (DMI_SBADDRESS0 << 2) -> sbAddrFields(0), (DMI_SBADDRESS1 << 2) -> sbAddrFields(1), (DMI_SBADDRESS2 << 2) -> sbAddrFields(2), (DMI_SBADDRESS3 << 2) -> sbAddrFields(3) ) // Abstract data mem is written by both the tile link interface and DMI... abstractDataMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) { x := abstractDataNxt(i) } } // ... and also by custom register read (if implemented) val (customs, customParams) = customNode.in.unzip val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0) def getNeedCustom = () => needCustom if (needCustom) { val (custom, customP) = customNode.in.head require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}") val custom_data = custom.data.asBools val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i8, (i+1)8).asUInt} when (custom.ready && custom.valid) { (abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) => a := b } } } programBufferMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) { x := programBufferNxt(i) } } //-------------------------------------------------------------- // "Variable" ROM Generation //-------------------------------------------------------------- val goReg = Reg(Bool()) val goAbstract = WireInit(false.B) val goCustom = WireInit(false.B) val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ())) jalAbstract.setImm(ABSTRACT(cfg) - WHERETO) when (~io.dmactive){ goReg := false.B }.otherwise { when (goAbstract) { goReg := true.B }.elsewhen (hartGoingWrEn){ assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U) goReg := false.B } } class flagBundle extends Bundle { val reserved = UInt(6.W) val resume = Bool() val go = Bool() } val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} )) assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U), s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.") flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg for (component <- 0 until nComponents) { val componentSel = WireInit(component.U) flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component) } //---------------------------- // Abstract Command Decoding & Generation //---------------------------- val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields())) /** real COMMAND/ val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields())) // TODO: Quick Access class GeneratedI extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedS extends Bundle { val immhi = UInt(7.W) val rs2 = UInt(5.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val immlo = UInt(5.W) val opcode = UInt(7.W) } class GeneratedCSR extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedUJ extends Bundle { val imm3 = UInt(1.W) val imm0 = UInt(10.W) val imm1 = UInt(1.W) val imm2 = UInt(8.W) val rd = UInt(5.W) val opcode = UInt(7.W) def setImm(imm: Int) : Unit = { // TODO: Check bounds of imm. require(imm % 2 == 0, "Immediate must be even for UJ encoding.") val immWire = WireInit(imm.S(21.W)) val immBits = WireInit(VecInit(immWire.asBools)) imm0 := immBits.slice(1, 1 + 10).asUInt imm1 := immBits.slice(11, 11 + 11).asUInt imm2 := immBits.slice(12, 12 + 8).asUInt imm3 := immBits.slice(20, 20 + 1).asUInt } } require((cfg.atzero && cfg.nAbstractInstructions == 2) \|\| (!cfg.atzero && cfg.nAbstractInstructions == 5), "Mismatch between DebugModuleParams atzero and nAbstractInstructions") val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W)))) def abstractGeneratedI(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedI()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode inst.rd := (accessRegisterCommandReg.regno & 0x1F.U) inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.imm := offset.U inst.asUInt } def abstractGeneratedS(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedS()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode inst.immlo := (offset & 0x1F).U inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U) inst.immhi := (offset >> 5).U inst.asUInt } def abstractGeneratedCSR: UInt = { val inst = Wire(new GeneratedCSR()) val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR())) inst.imm := CSRs.dscratch1.U inst.rs1 := base inst.rd := base inst.asUInt } val nop = Wire(new GeneratedI()) nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI()) nop.rd := 0.U nop.rs1 := 0.U nop.imm := 0.U val isa = Wire(new GeneratedI()) isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI()) isa.rd := 0.U isa.rs1 := 0.U isa.imm := 0.U when (goAbstract) { if (cfg.nAbstractInstructions == 2) { // ABSTRACT(0): Transfer: LW or SW, else NOP // ABSTRACT(1): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } else { // Entry: All regs in GPRs, dscratch1=offset 0x800 in DM // ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64) // ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP // ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(4): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt) abstractGeneratedMem(1) := abstractGeneratedCSR abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(3) := abstractGeneratedCSR abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } } //-------------------------------------------------------------- // Drive Custom Access //-------------------------------------------------------------- if (needCustom) { val (custom, customP) = customNode.in.head custom.addr := accessRegisterCommandReg.regno custom.valid := goCustom } //-------------------------------------------------------------- // Hart Bus Access //-------------------------------------------------------------- tlNode.regmap( // This memory is writable. HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn, "debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")), GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn, "debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")), RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn, "debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")), EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn, "debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")), DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"), abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}), PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"), programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}), // These sections are read-only. IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U, RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil}, WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))), ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"), abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}), FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"), if (nComponents == 1) { Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) } } else { flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))} }), ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"), (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))}) ) // Override System Bus accesses with dmactive reset. when (~io.dmactive){ abstractDataMem.foreach {x => x := 0.U} programBufferMem.foreach {x => x := 0.U} } //-------------------------------------------------------------- // Abstract Command State Machine //-------------------------------------------------------------- object CtrlState extends scala.Enumeration { type CtrlState = Value val Waiting, CheckGenerate, Exec, Custom = Value def apply( t : Value) : UInt = { t.id.U(log2Up(values.size).W) } } import CtrlState._ // This is not an initialization! val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting))) val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg) val ctrlStateNxt = WireInit(ctrlStateReg) //------------------------ // DMI Register Control and Status abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting)) ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting)) dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting)) errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) \|\| (autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) \|\| (autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) \|\| (COMMANDWrEnMaybe && ~COMMANDWrEnLegal) \|\| (dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) \|\| (dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal) // TODO: Maybe Quick Access val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister val commandRegIsUnsupported = WireInit(true.B) val commandRegBadHaltResume = WireInit(false.B) // We only support abstract commands for GPRs and any custom registers, if specified. val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) \|\| (accessRegisterCommandReg.size === 3.U) val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize val accessRegIsCustom = if (needCustom) { val (custom, customP) = customNode.in.head customP.addrs.foldLeft(false.B){ (result, current) => result \|\| (current.U === accessRegisterCommandReg.regno)} } else false.B when (commandRegIsAccessRegister) { when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) { commandRegIsUnsupported := false.B }.elsewhen (!accessRegisterCommandReg.transfer \|\| accessRegIsGPR) { commandRegIsUnsupported := false.B commandRegBadHaltResume := ~hartHalted } } val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) //------------------------ // Variable ROM STATE MACHINE // ----------------------- when (ctrlStateReg === CtrlState(Waiting)){ when (wrAccessRegisterCommand \|\| regAccessRegisterCommand) { ctrlStateNxt := CtrlState(CheckGenerate) }.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type. errorUnsupported := true.B }.elsewhen (autoexec && commandRegIsUnsupported) { errorUnsupported := true.B } }.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){ // We use this state to ensure that the COMMAND has been // registered by the time that we need to use it, to avoid // generating it directly from the COMMANDWrData. // This 'commandRegIsUnsupported' is really just checking the // AccessRegisterCommand parameters (regno) when (commandRegIsUnsupported) { errorUnsupported := true.B ctrlStateNxt := CtrlState(Waiting) }.elsewhen (commandRegBadHaltResume){ errorHaltResume := true.B ctrlStateNxt := CtrlState(Waiting) }.otherwise { when(accessRegIsCustom) { ctrlStateNxt := CtrlState(Custom) }.otherwise { ctrlStateNxt := CtrlState(Exec) goAbstract := true.B } } }.elsewhen (ctrlStateReg === CtrlState(Exec)) { // We can't just look at 'hartHalted' here, because // hartHaltedWrEn is overloaded to mean 'got an ebreak' // which may have happened when we were already halted. when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){ ctrlStateNxt := CtrlState(Waiting) } when(hartExceptionWrEn) { assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U) ctrlStateNxt := CtrlState(Waiting) errorException := true.B } }.elsewhen (ctrlStateReg === CtrlState(Custom)) { assert(needCustom.B, "Should not be in custom state unless we need it.") goCustom := true.B val (custom, customP) = customNode.in.head when (custom.ready && custom.valid) { ctrlStateNxt := CtrlState(Waiting) } } when (~io.dmactive \|\| ~dmAuthenticated) { ctrlStateReg := CtrlState(Waiting) }.otherwise { ctrlStateReg := ctrlStateNxt } assert ((!io.dmactive \|\| !hartExceptionWrEn \|\| ctrlStateReg === CtrlState(Exec)), "Unexpected EXCEPTION write: should only get it in Debug Module EXEC state") } } // Wrapper around TL Debug Module Inner and an Async DMI Sink interface. // Handles the synchronization of dmactive, which is used as a synchronous reset // inside the Inner block. // Also is the Sink side of hartsel & resumereq fields of DMCONTROL. class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{ val cfg = p(DebugModuleKey).get val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes)) val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) val dmiNode = dmiXing.node val tlNode = dmInner.tlNode dmInner.dmiNode := dmiXing.node // Require that there are no registers in TL interface, so that spurious // processor accesses to the DM don't need to enable the clock. We don't // require this property of the SBA, because the debugger is responsible for // raising dmactive (hence enabling the clock) during these transactions. require(dmInner.tlNode.concurrency == 0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { // Clock/reset domains: // debug_clock / debug_reset = Debug inner domain // tl_clock / tl_reset = tilelink domain (External: clock / reset) // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) // These are all asynchronous and come from Outer /* reset signal for DM / val dmactive = Input(Bool()) /* conrol signals for Inner * * generated in Outer / val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) // This comes from tlClk domain. /* debug available status / val debugUnavail = Input(Vec(getNComponents(), Bool())) /* debug interruption/ val hgDebugInt = Output(Vec(getNComponents(), Bool())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(getNComponents(), Bool())) /* Debug Authentication signals from core / val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.debug_clock childReset := io.debug_reset override def provideImplicitClockToLazyChildren = true val dmactive_synced = withClockAndReset(childClock, childReset) { val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync")) dmInner.module.clock := io.debug_clock dmInner.module.reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.dmactive := dmactive_synced dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl) dmInner.module.io.debugUnavail := io.debugUnavail io.hgDebugInt := dmInner.module.io.hgDebugInt io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} dmactive_synced } } } /* Create a version of the TLDebugModule which includes a synchronization interface * internally for the DMI. This is no longer optional outside of this module * because the Clock must run when tl_clock isn't running or tl_reset is asserted. / class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){ override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val attach = Map( "debug-attach" -> ( (if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++ (if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++ (if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++ (if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq()))) Description(name, mapping ++ attach) } } val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p)) val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p)) val node = dmInner.tlNode val intnode = dmOuter.intnode val apbNodeOpt = dmOuter.apbNodeOpt dmInner.dmiNode := dmOuter.dmiInnerNode lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.dmOuter.intnode.edges.out.size // Clock/reset domains: // tl_clock / tl_reset = tilelink domain // debug_clock / debug_reset = Inner debug (synchronous to tl_clock) // apb_clock / apb_reset = Outer debug with APB // dmiClock / dmiReset = Outer debug without APB // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /* Debug control signals generated in Outer / val ctrl = new DebugCtrlBundle(nComponents) /* Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI / val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO())) val apb_clock = p(ExportDebug).apb.option(Input(Clock())) val apb_reset = p(ExportDebug).apb.option(Input(Reset())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(nComponents, Bool())) /* hart reset request generated by hartreset-logic in Outer / val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* Debug Authentication signals from core / val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) childClock := io.tl_clock childReset := io.tl_reset override def provideImplicitClockToLazyChildren = true dmOuter.module.io.dmi.foreach { dmOuterDMI => dmOuterDMI <> io.dmi.get.dmi dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock dmOuter.module.rf_reset := io.dmi.get.dmiReset } (io.apb_clock zip io.apb_reset) foreach { case (c, r) => dmOuter.module.io.dmi_reset := r dmOuter.module.io.dmi_clock := c dmOuter.module.rf_reset := r } dmInner.module.rf_reset := io.debug_reset dmInner.module.io.debug_clock := io.debug_clock dmInner.module.io.debug_reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive dmInner.module.io.debugUnavail := io.ctrl.debugUnavail dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt io.ctrl <> dmOuter.module.io.ctrl io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated } io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} } } File SBA.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug.systembusaccess import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} import freechips.rocketchip.devices.debug.{DebugModuleKey, RWNotify, SBCSFields, WNotifyVal} import freechips.rocketchip.diplomacy.TransferSizes import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType} import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters} import freechips.rocketchip.util.property object SystemBusAccessState extends scala.Enumeration { type SystemBusAccessState = Value val Idle, SBReadRequest, SBWriteRequest, SBReadResponse, SBWriteResponse = Value } object SBErrorCode extends scala.Enumeration { type SBErrorCode = Value val NoError = Value(0) val Timeout = Value(1) val BadAddr = Value(2) val AlgnError = Value(3) val BadAccess = Value(4) val OtherError = Value(7) } object SystemBusAccessModule { def apply(sb2tl: SBToTL, dmactive: Bool, dmAuthenticated: Bool)(implicit p: Parameters): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = { import SBErrorCode._ val cfg = p(DebugModuleKey).get val anyAddressWrEn = WireInit(false.B).suggestName("anyAddressWrEn") val anyDataRdEn = WireInit(false.B).suggestName("anyDataRdEn") val anyDataWrEn = WireInit(false.B).suggestName("anyDataWrEn") // --- SBCS Status Register --- val SBCSFieldsReg = Reg(new SBCSFields()).suggestName("SBCSFieldsReg") val SBCSFieldsRegReset = WireInit(0.U.asTypeOf(new SBCSFields())) SBCSFieldsRegReset.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018 SBCSFieldsRegReset.sbbusy := (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U) SBCSFieldsRegReset.sbaccess := 2.U SBCSFieldsRegReset.sbasize := sb2tl.module.edge.bundle.addressBits.U SBCSFieldsRegReset.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B SBCSFieldsRegReset.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B SBCSFieldsRegReset.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B SBCSFieldsRegReset.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B SBCSFieldsRegReset.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B val SBCSRdData = WireInit(0.U.asTypeOf(new SBCSFields())).suggestName("SBCSRdData") val SBCSWrDataVal = WireInit(0.U(32.W)) val SBCSWrData = WireInit(SBCSWrDataVal.asTypeOf(new SBCSFields())) val sberrorWrEn = WireInit(false.B) val sbreadondataWrEn = WireInit(false.B) val sbautoincrementWrEn= WireInit(false.B) val sbaccessWrEn = WireInit(false.B) val sbreadonaddrWrEn = WireInit(false.B) val sbbusyerrorWrEn = WireInit(false.B) val sbcsfields = RegFieldGroup("sbcs", Some("system bus access control and status"), Seq( RegField.r(1, SBCSRdData.sbaccess8, RegFieldDesc("sbaccess8", "8-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 8) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess16, RegFieldDesc("sbaccess16", "16-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 16) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess32, RegFieldDesc("sbaccess32", "32-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 32) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess64, RegFieldDesc("sbaccess64", "64-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 64) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess128, RegFieldDesc("sbaccess128", "128-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess == 128) 1 else 0))), RegField.r(7, SBCSRdData.sbasize, RegFieldDesc("sbasize", "bits in address", reset=Some(sb2tl.module.edge.bundle.addressBits))), WNotifyVal(3, SBCSRdData.sberror, SBCSWrData.sberror, sberrorWrEn, RegFieldDesc("sberror", "system bus error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), WNotifyVal(1, SBCSRdData.sbreadondata, SBCSWrData.sbreadondata, sbreadondataWrEn, RegFieldDesc("sbreadondata", "system bus read on data", reset=Some(0))), WNotifyVal(1, SBCSRdData.sbautoincrement, SBCSWrData.sbautoincrement, sbautoincrementWrEn, RegFieldDesc("sbautoincrement", "system bus auto-increment address", reset=Some(0))), WNotifyVal(3, SBCSRdData.sbaccess, SBCSWrData.sbaccess, sbaccessWrEn, RegFieldDesc("sbaccess", "system bus access size", reset=Some(2))), WNotifyVal(1, SBCSRdData.sbreadonaddr, SBCSWrData.sbreadonaddr, sbreadonaddrWrEn, RegFieldDesc("sbreadonaddr", "system bus read on data", reset=Some(0))), RegField.r(1, SBCSRdData.sbbusy, RegFieldDesc("sbbusy", "system bus access is busy", reset=Some(0))), WNotifyVal(1, SBCSRdData.sbbusyerror, SBCSWrData.sbbusyerror, sbbusyerrorWrEn, RegFieldDesc("sbbusyerror", "system bus busy error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(6), RegField.r(3, SBCSRdData.sbversion, RegFieldDesc("sbversion", "system bus access version", reset=Some(1))), )) // --- System Bus Address Registers --- // ADDR0 Register is required // Instantiate ADDR1-3 registers as needed depending on system bus address width val hasSBAddr1 = (sb2tl.module.edge.bundle.addressBits >= 33) val hasSBAddr2 = (sb2tl.module.edge.bundle.addressBits >= 65) val hasSBAddr3 = (sb2tl.module.edge.bundle.addressBits >= 97) val hasAddr = Seq(true, hasSBAddr1, hasSBAddr2, hasSBAddr3) val SBADDRESSFieldsReg = Reg(Vec(4, UInt(32.W))) SBADDRESSFieldsReg.zipWithIndex.foreach { case(a,i) => a.suggestName("SBADDRESS"+i+"FieldsReg")} val SBADDRESSWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) val SBADDRESSRdEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val SBADDRESSWrEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val autoIncrementedAddr = WireInit(0.U(128.W)) autoIncrementedAddr := Cat(SBADDRESSFieldsReg.reverse) + (1.U << SBCSFieldsReg.sbaccess) autoIncrementedAddr.suggestName("autoIncrementedAddr") val sbaddrfields: Seq[Seq[RegField]] = SBADDRESSFieldsReg.zipWithIndex.map { case(a,i) => if(hasAddr(i)) { when (~dmactive \|\| ~dmAuthenticated) { a := 0.U(32.W) }.otherwise { a := Mux(SBADDRESSWrEn(i) && !SBCSRdData.sberror && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror, SBADDRESSWrData(i), Mux((sb2tl.module.io.rdDone \|\| sb2tl.module.io.wrDone) && SBCSFieldsReg.sbautoincrement, autoIncrementedAddr(32i+31,32i), a)) } RegFieldGroup("dmi_sbaddr"+i, Some("SBA Address Register"), Seq(RWNotify(32, a, SBADDRESSWrData(i), SBADDRESSRdEn(i), SBADDRESSWrEn(i), Some(RegFieldDesc("dmi_sbaddr"+i, "SBA address register", reset=Some(0), volatile=true))))) } else { a := DontCare Seq.empty[RegField] } } sb2tl.module.io.addrIn := Mux(SBADDRESSWrEn(0), Cat(Cat(SBADDRESSFieldsReg.drop(1).reverse), SBADDRESSWrData(0)), Cat(SBADDRESSFieldsReg.reverse)) anyAddressWrEn := SBADDRESSWrEn.reduce(_ \|\| _) // --- System Bus Data Registers --- // DATA0 Register is required // DATA1-3 Registers may not be needed depending on implementation val hasSBData1 = (cfg.maxSupportedSBAccess > 32) val hasSBData2And3 = (cfg.maxSupportedSBAccess == 128) val hasData = Seq(true, hasSBData1, hasSBData2And3, hasSBData2And3) val SBDATAFieldsReg = Reg(Vec(4, Vec(4, UInt(8.W)))) SBDATAFieldsReg.zipWithIndex.foreach { case(d,i) => d.zipWithIndex.foreach { case(d,j) => d.suggestName("SBDATA"+i+"BYTE"+j) }} val SBDATARdData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) SBDATARdData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATARdData"+i) } val SBDATAWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) SBDATAWrData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrData"+i) } val SBDATARdEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val SBDATAWrEn = WireInit(VecInit(Seq.fill(4) {false.B} )) SBDATAWrEn.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrEn"+i) } val sbdatafields: Seq[Seq[RegField]] = SBDATAFieldsReg.zipWithIndex.map { case(d,i) => if(hasData(i)) { // For data registers, load enable per-byte for (j <- 0 to 3) { when (~dmactive \|\| ~dmAuthenticated) { d(j) := 0.U(8.W) }.otherwise { d(j) := Mux(SBDATAWrEn(i) && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror, SBDATAWrData(i)(8j+7,8j), Mux(sb2tl.module.io.rdLoad(4i+j), sb2tl.module.io.dataOut, d(j))) } } SBDATARdData(i) := Cat(d.reverse) RegFieldGroup("dmi_sbdata"+i, Some("SBA Data Register"), Seq(RWNotify(32, SBDATARdData(i), SBDATAWrData(i), SBDATARdEn(i), SBDATAWrEn(i), Some(RegFieldDesc("dmi_sbdata"+i, "SBA data register", reset=Some(0), volatile=true))))) } else { for (j <- 0 to 3) { d(j) := DontCare } Seq.empty[RegField] } } sb2tl.module.io.dataIn := Mux(sb2tl.module.io.wrEn,Cat(SBDATAWrData.reverse),Cat(SBDATAFieldsReg.flatten.reverse)) anyDataRdEn := SBDATARdEn.reduce(_ \|\| _) anyDataWrEn := SBDATAWrEn.reduce(_ \|\| _) val tryWrEn = SBDATAWrEn(0) val tryRdEn = (SBADDRESSWrEn(0) && SBCSFieldsReg.sbreadonaddr) \|\| (SBDATARdEn(0) && SBCSFieldsReg.sbreadondata) val sbAccessError = (SBCSFieldsReg.sbaccess === 0.U) && (SBCSFieldsReg.sbaccess8 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess === 1.U) && (SBCSFieldsReg.sbaccess16 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess === 2.U) && (SBCSFieldsReg.sbaccess32 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess === 3.U) && (SBCSFieldsReg.sbaccess64 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess === 4.U) && (SBCSFieldsReg.sbaccess128 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess > 4.U) val compareAddr = Wire(UInt(32.W)) // Need use written or latched address to detect error case depending on how transaction is initiated compareAddr := Mux(SBADDRESSWrEn(0),SBADDRESSWrData(0),SBADDRESSFieldsReg(0)) val sbAlignmentError = (SBCSFieldsReg.sbaccess === 1.U) && (compareAddr(0) =/= 0.U) \|\| (SBCSFieldsReg.sbaccess === 2.U) && (compareAddr(1,0) =/= 0.U) \|\| (SBCSFieldsReg.sbaccess === 3.U) && (compareAddr(2,0) =/= 0.U) \|\| (SBCSFieldsReg.sbaccess === 4.U) && (compareAddr(3,0) =/= 0.U) sbAccessError.suggestName("sbAccessError") sbAlignmentError.suggestName("sbAlignmentError") sb2tl.module.io.wrEn := dmAuthenticated && tryWrEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError sb2tl.module.io.rdEn := dmAuthenticated && tryRdEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError sb2tl.module.io.sizeIn := SBCSFieldsReg.sbaccess val sbBusy = (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U) when (~dmactive \|\| ~dmAuthenticated) { SBCSFieldsReg := SBCSFieldsRegReset }.otherwise { SBCSFieldsReg.sbbusyerror := Mux(sbbusyerrorWrEn && SBCSWrData.sbbusyerror, false.B, // W1C Mux(anyAddressWrEn && sbBusy, true.B, // Set if a write to SBADDRESS occurs while busy Mux((anyDataRdEn \|\| anyDataWrEn) && sbBusy, true.B, SBCSFieldsReg.sbbusyerror))) // Set if any access to SBDATA occurs while busy SBCSFieldsReg.sbreadonaddr := Mux(sbreadonaddrWrEn, SBCSWrData.sbreadonaddr , SBCSFieldsReg.sbreadonaddr) SBCSFieldsReg.sbautoincrement := Mux(sbautoincrementWrEn, SBCSWrData.sbautoincrement, SBCSFieldsReg.sbautoincrement) SBCSFieldsReg.sbreadondata := Mux(sbreadondataWrEn, SBCSWrData.sbreadondata , SBCSFieldsReg.sbreadondata) SBCSFieldsReg.sbaccess := Mux(sbaccessWrEn, SBCSWrData.sbaccess, SBCSFieldsReg.sbaccess) SBCSFieldsReg.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018 } // sbErrorReg has a per-bit load enable since each bit can be individually cleared by writing a 1 to it val sbErrorReg = Reg(Vec(4, UInt(1.W))) when(~dmactive \|\| ~dmAuthenticated) { for (i <- 0 until 3) sbErrorReg(i) := 0.U }.otherwise { for (i <- 0 until 3) sbErrorReg(i) := Mux(sberrorWrEn && SBCSWrData.sberror(i) === 1.U, NoError.id.U.extract(i), // W1C Mux((sb2tl.module.io.wrEn && !sb2tl.module.io.wrLegal) \|\| (sb2tl.module.io.rdEn && !sb2tl.module.io.rdLegal), BadAddr.id.U.extract(i), // Bad address accessed Mux((tryWrEn \|\| tryRdEn) && sbAlignmentError, AlgnError.id.U.extract(i), // Address alignment error Mux((tryWrEn \|\| tryRdEn) && sbAccessError, BadAccess.id.U.extract(i), // Access size error Mux((sb2tl.module.io.rdDone \|\| sb2tl.module.io.wrDone) && sb2tl.module.io.respError, OtherError.id.U.extract(i), sbErrorReg(i)))))) // Response error from TL } SBCSRdData := SBCSFieldsReg SBCSRdData.sbasize := sb2tl.module.edge.bundle.addressBits.U SBCSRdData.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B SBCSRdData.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B SBCSRdData.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B SBCSRdData.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B SBCSRdData.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B SBCSRdData.sbbusy := sbBusy SBCSRdData.sberror := sbErrorReg.asUInt when (~dmAuthenticated) { // Read value must be 0 if not authenticated SBCSRdData := 0.U.asTypeOf(new SBCSFields()) } property.cover(SBCSFieldsReg.sbbusyerror, "SBCS Cover", "sberror set") property.cover(SBCSFieldsReg.sbbusy === 3.U, "SBCS Cover", "sbbusyerror alignment error") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 0.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "8-bit access") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 1.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "16-bit access") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 2.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "32-bit access") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 3.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "64-bit access") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 4.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "128-bit access") property.cover(SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access with autoincrement set") property.cover(!SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access without autoincrement set") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess > 4.U, "SBCS Cover", "Invalid sbaccess value") (sbcsfields, sbaddrfields, sbdatafields) } } class SBToTL(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1("debug")), requestFields = Seq(AMBAProtField())))) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val rdEn = Input(Bool()) val wrEn = Input(Bool()) val addrIn = Input(UInt(128.W)) // TODO: Parameterize these widths val dataIn = Input(UInt(128.W)) val sizeIn = Input(UInt(3.W)) val rdLegal = Output(Bool()) val wrLegal = Output(Bool()) val rdDone = Output(Bool()) val wrDone = Output(Bool()) val respError = Output(Bool()) val dataOut = Output(UInt(8.W)) val rdLoad = Output(Vec(cfg.maxSupportedSBAccess/8, Bool())) val sbStateOut = Output(UInt(log2Ceil(SystemBusAccessState.maxId).W)) }) val rf_reset = IO(Input(Reset())) import SystemBusAccessState._ val (tl, edge) = node.out(0) val sbState = RegInit(0.U) // --- Drive payloads on bus to TileLink --- val d = Queue(tl.d, 2) // Add a small buffer since response could arrive on same cycle as request d.ready := (sbState === SBReadResponse.id.U) \|\| (sbState === SBWriteResponse.id.U) val muxedData = WireInit(0.U(8.W)) val requestValid = tl.a.valid val requestReady = tl.a.ready val responseValid = d.valid val responseReady = d.ready val counter = RegInit(0.U((log2Ceil(cfg.maxSupportedSBAccess/8)+1).W)) val vecData = Wire(Vec(cfg.maxSupportedSBAccess/8, UInt(8.W))) vecData.zipWithIndex.map { case (vd, i) => vd := io.dataIn(8i+7,8i) } muxedData := vecData(counter(log2Ceil(vecData.size)-1,0)) // Need an additional check to determine if address is safe for Get/Put val rdLegal_addr = edge.manager.supportsGetSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8))) val wrLegal_addr = edge.manager.supportsPutFullSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8))) val (_, gbits) = edge.Get(0.U, io.addrIn, io.sizeIn) val (_, pfbits) = edge.Put(0.U, io.addrIn, io.sizeIn, muxedData) io.rdLegal := rdLegal_addr io.wrLegal := wrLegal_addr io.sbStateOut := sbState when(sbState === SBReadRequest.id.U) { tl.a.bits := gbits } .otherwise { tl.a.bits := pfbits } tl.a.bits.user.lift(AMBAProt).foreach { x => x.bufferable := false.B x.modifiable := false.B x.readalloc := false.B x.writealloc := false.B x.privileged := true.B x.secure := true.B x.fetch := false.B } val respError = d.bits.denied \|\| d.bits.corrupt io.respError := respError val wrTxValid = sbState === SBWriteRequest.id.U && requestValid && requestReady val rdTxValid = sbState === SBReadResponse.id.U && responseValid && responseReady val txLast = counter === ((1.U << io.sizeIn) - 1.U) counter := Mux((wrTxValid \|\| rdTxValid) && txLast, 0.U, Mux((wrTxValid \|\| rdTxValid) , counter+1.U, counter)) for (i <- 0 until (cfg.maxSupportedSBAccess/8)) { io.rdLoad(i) := rdTxValid && (counter === i.U) } // --- State Machine to interface with TileLink --- when (sbState === Idle.id.U){ sbState := Mux(io.rdEn && io.rdLegal, SBReadRequest.id.U, Mux(io.wrEn && io.wrLegal, SBWriteRequest.id.U, sbState)) }.elsewhen (sbState === SBReadRequest.id.U){ sbState := Mux(requestValid && requestReady, SBReadResponse.id.U, sbState) }.elsewhen (sbState === SBWriteRequest.id.U){ sbState := Mux(wrTxValid && txLast, SBWriteResponse.id.U, sbState) }.elsewhen (sbState === SBReadResponse.id.U){ sbState := Mux(rdTxValid && txLast, Idle.id.U, sbState) }.elsewhen (sbState === SBWriteResponse.id.U){ sbState := Mux(responseValid && responseReady, Idle.id.U, sbState) } io.rdDone := rdTxValid && txLast io.wrDone := (sbState === SBWriteResponse.id.U) && responseValid && responseReady io.dataOut := d.bits.data tl.a.valid := (sbState === SBReadRequest.id.U) \|\| (sbState === SBWriteRequest.id.U) // Tie off unused channels tl.b.ready := false.B tl.c.valid := false.B tl.e.valid := false.B assert (sbState === Idle.id.U \|\| sbState === SBReadRequest.id.U \|\| sbState === SBWriteRequest.id.U \|\| sbState === SBReadResponse.id.U \|\| sbState === SBWriteResponse.id.U, "SBA state machine in undefined state") property.cover (sbState === Idle.id.U, "SBA State Cover", "SBA Access Idle") property.cover (sbState === SBReadRequest.id.U, "SBA State Cover", "SBA Access Read Req") property.cover (sbState === SBWriteRequest.id.U, "SBA State Cover", "SBA Access Write Req") property.cover (sbState === SBReadResponse.id.U, "SBA State Cover", "SBA Access Read Resp") property.cover (sbState === SBWriteResponse.id.U, "SBA State Cover", "SBA Access Write Resp") property.cover (io.rdEn && !io.rdLegal, "SB Legality Cover", "SBA Rd Address Illegal") property.cover (io.wrEn && !io.wrLegal, "SB Legality Cover", "SBA Wr Address Illegal") } }	module TLDebugModuleInner( // @[Debug.scala:790:9] input clock, // @[Debug.scala:790:9] input reset, // @[Debug.scala:790:9] input auto_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmi_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmi_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmi_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [8:0] auto_dmi_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmi_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmi_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmi_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmi_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmi_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_dmactive, // @[Debug.scala:803:16] input io_innerCtrl_valid, // @[Debug.scala:803:16] input io_innerCtrl_bits_resumereq, // @[Debug.scala:803:16] input [9:0] io_innerCtrl_bits_hartsel, // @[Debug.scala:803:16] input io_innerCtrl_bits_ackhavereset, // @[Debug.scala:803:16] input io_innerCtrl_bits_hrmask_0, // @[Debug.scala:803:16] output io_hgDebugInt_0, // @[Debug.scala:803:16] input io_hartIsInReset_0, // @[Debug.scala:803:16] input io_tl_clock, // @[Debug.scala:803:16] input io_tl_reset // @[Debug.scala:803:16] ); wire abstractCommandBusy; // @[Debug.scala:1740:42] reg [1:0] ctrlStateReg; // @[Debug.scala:1732:27] wire out_woready_1_353; // @[RegisterRouter.scala:87:24] wire out_woready_1_536; // @[RegisterRouter.scala:87:24] wire out_woready_45; // @[RegisterRouter.scala:87:24] wire out_woready_28; // @[RegisterRouter.scala:87:24] wire out_woready_62; // @[RegisterRouter.scala:87:24] wire out_woready_80; // @[RegisterRouter.scala:87:24] wire out_woready_119; // @[RegisterRouter.scala:87:24] wire out_woready_135; // @[RegisterRouter.scala:87:24] wire out_woready_51; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_139; // @[RegisterRouter.scala:87:24] wire out_woready_127; // @[RegisterRouter.scala:87:24] wire out_woready_72; // @[RegisterRouter.scala:87:24] wire out_woready_58; // @[RegisterRouter.scala:87:24] wire out_woready_144; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_108; // @[RegisterRouter.scala:87:24] wire out_woready_76; // @[RegisterRouter.scala:87:24] wire out_woready_104; // @[RegisterRouter.scala:87:24] wire out_woready_54; // @[RegisterRouter.scala:87:24] wire out_woready_131; // @[RegisterRouter.scala:87:24] wire out_woready_32; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_20; // @[RegisterRouter.scala:87:24] wire out_woready_123; // @[RegisterRouter.scala:87:24] wire out_woready_67; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] wire out_roready_28; // @[RegisterRouter.scala:87:24] wire out_roready_62; // @[RegisterRouter.scala:87:24] wire out_roready_80; // @[RegisterRouter.scala:87:24] wire out_roready_119; // @[RegisterRouter.scala:87:24] wire out_roready_135; // @[RegisterRouter.scala:87:24] wire out_roready_51; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_139; // @[RegisterRouter.scala:87:24] wire out_roready_127; // @[RegisterRouter.scala:87:24] wire out_roready_72; // @[RegisterRouter.scala:87:24] wire out_roready_58; // @[RegisterRouter.scala:87:24] wire out_roready_144; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_108; // @[RegisterRouter.scala:87:24] wire out_roready_76; // @[RegisterRouter.scala:87:24] wire out_roready_104; // @[RegisterRouter.scala:87:24] wire out_roready_131; // @[RegisterRouter.scala:87:24] wire out_roready_32; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_20; // @[RegisterRouter.scala:87:24] wire out_roready_123; // @[RegisterRouter.scala:87:24] wire out_roready_67; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_24; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] wire out_backSel_61; // @[RegisterRouter.scala:87:24] wire out_backSel_60; // @[RegisterRouter.scala:87:24] wire out_backSel_57; // @[RegisterRouter.scala:87:24] wire out_backSel_23; // @[RegisterRouter.scala:87:24] wire out_backSel_22; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_19; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_19; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_18; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_18; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_17; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_17; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_16; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_16; // @[RegisterRouter.scala:87:24] wire [31:0] COMMANDWrDataVal; // @[Debug.scala:297:{24,30}, :1279:39] wire COMMANDWrEnMaybe; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_35; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_35; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_34; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_34; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_33; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_33; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_32; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_32; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_47; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_47; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_46; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_46; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_45; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_45; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_44; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_44; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_31; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_31; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_30; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_30; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_29; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_29; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_28; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_31; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_31; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_30; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_30; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_29; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_29; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_28; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_15; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_15; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_14; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_14; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_13; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_13; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_12; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_12; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_51; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_51; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_50; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_50; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_49; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_49; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_48; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_48; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_11; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_11; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_10; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_10; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_9; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_9; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_8; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_8; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_3; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_3; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_2; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_2; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_1; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_1; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_0; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_0; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_55; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_55; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_54; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_54; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_53; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_53; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_52; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_52; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_7; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_7; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_6; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_6; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_5; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_5; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_4; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_4; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_27; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_27; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_26; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_26; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_25; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_25; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_24; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_24; // @[RegisterRouter.scala:87:24] wire [31:0] SBDATAWrData_0; // @[SBA.scala:147:35] wire SBDATAWrEn_0; // @[RegisterRouter.scala:87:24] wire SBDATARdEn_0; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_11; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_11; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_10; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_10; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_9; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_9; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_8; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_8; // @[RegisterRouter.scala:87:24] wire SBADDRESSWrEn_0; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_59; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_59; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_58; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_58; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_57; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_57; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_56; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_56; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_23; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_23; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_22; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_22; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_21; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_21; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_20; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_20; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_43; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_43; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_42; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_42; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_41; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_41; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_40; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_40; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_27; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_27; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_26; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_26; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_25; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_25; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_24; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_24; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_63; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_63; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_62; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_62; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_61; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_61; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_60; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_60; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_3; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_3; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_2; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_2; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_1; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_1; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_0; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_0; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_19; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_19; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_18; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_18; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_17; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_17; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_16; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_16; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_15; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_15; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_14; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_14; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_13; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_13; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_12; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_12; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_39; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_39; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_38; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_38; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_37; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_37; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_36; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_36; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_23; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_23; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_22; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_22; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_21; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_21; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_20; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_20; // @[RegisterRouter.scala:87:24] wire [31:0] SBDATAWrData_1; // @[SBA.scala:147:35] wire dmiAbstractDataWrEnMaybe_7; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_7; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_6; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_6; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_5; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_5; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_4; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_4; // @[RegisterRouter.scala:87:24] wire [2:0] SBCSRdData_sberror; // @[SBA.scala:240:28] wire sb2tlOpt_io_wrEn; // @[SBA.scala:199:{60,85,115,138,156}] wire _hartIsInResetSync_0_debug_hartReset_0_io_q; // @[ShiftReg.scala:45:23] wire _sb2tlOpt_io_rdLegal; // @[Debug.scala:782:52] wire _sb2tlOpt_io_wrLegal; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdDone; // @[Debug.scala:782:52] wire _sb2tlOpt_io_wrDone; // @[Debug.scala:782:52] wire _sb2tlOpt_io_respError; // @[Debug.scala:782:52] wire [7:0] _sb2tlOpt_io_dataOut; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_0; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_1; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_2; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_3; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_4; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_5; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_6; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_7; // @[Debug.scala:782:52] wire [2:0] _sb2tlOpt_io_sbStateOut; // @[Debug.scala:782:52] reg hartHalted; // @[Debug.scala:861:31] reg resumeReqRegs; // @[Debug.scala:863:31] reg haveResetBitRegs; // @[Debug.scala:865:31] wire hamaskWrSel_0 = io_innerCtrl_bits_hartsel == 10'h0; // @[Debug.scala:935:61] reg hrmaskReg_0; // @[Debug.scala:947:29] reg hrDebugIntReg_0; // @[Debug.scala:961:34] wire resumereq = io_innerCtrl_valid & io_innerCtrl_bits_resumereq; // @[Debug.scala:983:39] reg [2:0] ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34] reg [15:0] ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36] reg [11:0] ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36] wire dmiAbstractDataAccessVec_0 = dmiAbstractDataWrEnMaybe_0 \| dmiAbstractDataRdEn_0; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_4 = dmiAbstractDataWrEnMaybe_4 \| dmiAbstractDataRdEn_4; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_8 = dmiAbstractDataWrEnMaybe_8 \| dmiAbstractDataRdEn_8; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_12 = dmiAbstractDataWrEnMaybe_12 \| dmiAbstractDataRdEn_12; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_16 = dmiAbstractDataWrEnMaybe_16 \| dmiAbstractDataRdEn_16; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_20 = dmiAbstractDataWrEnMaybe_20 \| dmiAbstractDataRdEn_20; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_24 = dmiAbstractDataWrEnMaybe_24 \| dmiAbstractDataRdEn_24; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_28 = dmiAbstractDataWrEnMaybe_28 \| dmiAbstractDataRdEn_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_0 = dmiProgramBufferWrEnMaybe_0 \| dmiProgramBufferRdEn_0; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_4 = dmiProgramBufferWrEnMaybe_4 \| dmiProgramBufferRdEn_4; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_8 = dmiProgramBufferWrEnMaybe_8 \| dmiProgramBufferRdEn_8; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_12 = dmiProgramBufferWrEnMaybe_12 \| dmiProgramBufferRdEn_12; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_16 = dmiProgramBufferWrEnMaybe_16 \| dmiProgramBufferRdEn_16; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_20 = dmiProgramBufferWrEnMaybe_20 \| dmiProgramBufferRdEn_20; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_24 = dmiProgramBufferWrEnMaybe_24 \| dmiProgramBufferRdEn_24; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_28 = dmiProgramBufferWrEnMaybe_28 \| dmiProgramBufferRdEn_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_32 = dmiProgramBufferWrEnMaybe_32 \| dmiProgramBufferRdEn_32; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_36 = dmiProgramBufferWrEnMaybe_36 \| dmiProgramBufferRdEn_36; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_40 = dmiProgramBufferWrEnMaybe_40 \| dmiProgramBufferRdEn_40; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_44 = dmiProgramBufferWrEnMaybe_44 \| dmiProgramBufferRdEn_44; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_48 = dmiProgramBufferWrEnMaybe_48 \| dmiProgramBufferRdEn_48; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_52 = dmiProgramBufferWrEnMaybe_52 \| dmiProgramBufferRdEn_52; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_56 = dmiProgramBufferWrEnMaybe_56 \| dmiProgramBufferRdEn_56; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_60 = dmiProgramBufferWrEnMaybe_60 \| dmiProgramBufferRdEn_60; // @[RegisterRouter.scala:87:24] wire autoexec = dmiAbstractDataAccessVec_0 & ABSTRACTAUTOReg_autoexecdata[0] \| dmiAbstractDataAccessVec_4 & ABSTRACTAUTOReg_autoexecdata[1] \| dmiAbstractDataAccessVec_8 & ABSTRACTAUTOReg_autoexecdata[2] \| dmiAbstractDataAccessVec_12 & ABSTRACTAUTOReg_autoexecdata[3] \| dmiAbstractDataAccessVec_16 & ABSTRACTAUTOReg_autoexecdata[4] \| dmiAbstractDataAccessVec_20 & ABSTRACTAUTOReg_autoexecdata[5] \| dmiAbstractDataAccessVec_24 & ABSTRACTAUTOReg_autoexecdata[6] \| dmiAbstractDataAccessVec_28 & ABSTRACTAUTOReg_autoexecdata[7] \| dmiProgramBufferAccessVec_0 & ABSTRACTAUTOReg_autoexecprogbuf[0] \| dmiProgramBufferAccessVec_4 & ABSTRACTAUTOReg_autoexecprogbuf[1] \| dmiProgramBufferAccessVec_8 & ABSTRACTAUTOReg_autoexecprogbuf[2] \| dmiProgramBufferAccessVec_12 & ABSTRACTAUTOReg_autoexecprogbuf[3] \| dmiProgramBufferAccessVec_16 & ABSTRACTAUTOReg_autoexecprogbuf[4] \| dmiProgramBufferAccessVec_20 & ABSTRACTAUTOReg_autoexecprogbuf[5] \| dmiProgramBufferAccessVec_24 & ABSTRACTAUTOReg_autoexecprogbuf[6] \| dmiProgramBufferAccessVec_28 & ABSTRACTAUTOReg_autoexecprogbuf[7] \| dmiProgramBufferAccessVec_32 & ABSTRACTAUTOReg_autoexecprogbuf[8] \| dmiProgramBufferAccessVec_36 & ABSTRACTAUTOReg_autoexecprogbuf[9] \| dmiProgramBufferAccessVec_40 & ABSTRACTAUTOReg_autoexecprogbuf[10] \| dmiProgramBufferAccessVec_44 & ABSTRACTAUTOReg_autoexecprogbuf[11] \| dmiProgramBufferAccessVec_48 & ABSTRACTAUTOReg_autoexecprogbuf[12] \| dmiProgramBufferAccessVec_52 & ABSTRACTAUTOReg_autoexecprogbuf[13] \| dmiProgramBufferAccessVec_56 & ABSTRACTAUTOReg_autoexecprogbuf[14] \| dmiProgramBufferAccessVec_60 & ABSTRACTAUTOReg_autoexecprogbuf[15]; // @[Debug.scala:1235:36, :1258:105, :1261:108, :1269:{54,140}, :1270:{57,144}, :1272:{42,48,73}] reg [7:0] COMMANDReg_cmdtype; // @[Debug.scala:1277:25] reg [23:0] COMMANDReg_control; // @[Debug.scala:1277:25] wire COMMANDWrEn = COMMANDWrEnMaybe & ~(\|ctrlStateReg); // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_0; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_1; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_2; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_3; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_4; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_5; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_6; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_7; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_8; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_9; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_10; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_11; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_12; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_13; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_14; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_15; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_16; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_17; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_18; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_19; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_20; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_21; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_22; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_23; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_24; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_25; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_26; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_27; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_28; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_29; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_30; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_31; // @[Debug.scala:1300:36] reg [7:0] programBufferMem_0; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_1; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_2; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_3; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_4; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_5; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_6; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_7; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_8; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_9; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_10; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_11; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_12; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_13; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_14; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_15; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_16; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_17; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_18; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_19; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_20; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_21; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_22; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_23; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_24; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_25; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_26; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_27; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_28; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_29; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_30; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_31; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_32; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_33; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_34; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_35; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_36; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_37; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_38; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_39; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_40; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_41; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_42; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_43; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_44; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_45; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_46; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_47; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_48; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_49; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_50; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_51; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_52; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_53; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_54; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_55; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_56; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_57; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_58; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_59; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_60; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_61; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_62; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_63; // @[Debug.scala:1306:34] reg SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28] reg SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28] reg SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28] reg [2:0] SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28] reg SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28] reg SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28] reg [31:0] SBADDRESSFieldsReg_0; // @[SBA.scala:104:33] reg [7:0] SBDATAFieldsReg_0_0; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_1; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_2; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_3; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_0; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_1; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_2; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_3; // @[SBA.scala:143:30] wire tryRdEn = SBADDRESSWrEn_0 & SBCSFieldsReg_sbreadonaddr \| SBDATARdEn_0 & SBCSFieldsReg_sbreadondata; // @[RegisterRouter.scala:87:24] wire _sbAlignmentError_T_14 = SBCSFieldsReg_sbaccess == 3'h4; // @[SBA.scala:47:28, :186:49] wire sbAccessError = _sbAlignmentError_T_14 \| SBCSFieldsReg_sbaccess > 3'h4; // @[SBA.scala:47:28, :186:{49,97,124}] wire [3:0] compareAddr = SBADDRESSWrEn_0 ? auto_dmi_in_a_bits_data[3:0] : SBADDRESSFieldsReg_0[3:0]; // @[RegisterRouter.scala:87:24] wire sbAlignmentError = SBCSFieldsReg_sbaccess == 3'h1 & compareAddr[0] \| SBCSFieldsReg_sbaccess == 3'h2 & (\|(compareAddr[1:0])) \| SBCSFieldsReg_sbaccess == 3'h3 & (\|(compareAddr[2:0])) \| _sbAlignmentError_T_14 & (\|compareAddr); // @[SBA.scala:47:28, :183:49, :184:49, :185:49, :186:49, :189:23, :191:{61,76,91}, :192:{61,76,82,91}, :193:{61,76,82,91}, :194:{61,82}] assign sb2tlOpt_io_wrEn = SBDATAWrEn_0 & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~(\|SBCSRdData_sberror) & ~sbAccessError & ~sbAlignmentError; // @[RegisterRouter.scala:87:24] wire sb2tlOpt_io_rdEn = tryRdEn & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~(\|SBCSRdData_sberror) & ~sbAccessError & ~sbAlignmentError; // @[SBA.scala:47:28, :119:40, :180:68, :186:97, :191:91, :192:91, :193:91, :199:{63,88,118,141,159}, :200:{60,85,115,138,156}, :240:28] reg sbErrorReg_0; // @[SBA.scala:219:25] reg sbErrorReg_1; // @[SBA.scala:219:25] reg sbErrorReg_2; // @[SBA.scala:219:25] assign SBCSRdData_sberror = {sbErrorReg_2, sbErrorReg_1, sbErrorReg_0}; // @[SBA.scala:219:25, :240:28] wire in_bits_read = auto_dmi_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire [7:0] _out_backMask_T_6 = {8{auto_dmi_in_a_bits_mask[2]}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_7 = {8{auto_dmi_in_a_bits_mask[3]}}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask = {_out_backMask_T_7, _out_backMask_T_6, {8{auto_dmi_in_a_bits_mask[1]}}, {8{auto_dmi_in_a_bits_mask[0]}}}; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_4 = out_roready_3 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_4 = out_woready_3 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_5 = out_roready_3 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_5 = out_woready_3 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_6 = out_roready_3 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_6 = out_woready_3 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_7 = out_roready_3 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_7 = out_woready_3 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire SBDATAWrEn_1 = _out_wofireMux_T_2 & out_backSel_61 & ~(auto_dmi_in_a_bits_address[8]) & (&out_backMask); // @[RegisterRouter.scala:87:24] assign SBDATAWrData_1 = SBDATAWrEn_1 ? auto_dmi_in_a_bits_data : 32'h0; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_20 = out_roready_8 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_20 = out_woready_8 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_21 = out_roready_8 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_21 = out_woready_8 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_22 = out_roready_8 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_22 = out_woready_8 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_23 = out_roready_8 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_23 = out_woready_8 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_36 = out_roready_9 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_36 = out_woready_9 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_37 = out_roready_9 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_37 = out_woready_9 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_38 = out_roready_9 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_38 = out_woready_9 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_39 = out_roready_9 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_39 = out_woready_9 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_12 = out_roready_16 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_12 = out_woready_16 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_13 = out_roready_16 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_13 = out_woready_16 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_14 = out_roready_16 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_14 = out_woready_16 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_15 = out_roready_16 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_15 = out_woready_16 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_16 = out_roready_20 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_16 = out_woready_20 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_17 = out_roready_20 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_17 = out_woready_20 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_18 = out_roready_20 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_18 = out_woready_20 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_19 = out_roready_20 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_19 = out_woready_20 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_0 = out_roready_24 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_0 = out_woready_24 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_1 = out_roready_24 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_1 = out_woready_24 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_2 = out_roready_24 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_2 = out_woready_24 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_3 = out_roready_24 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_3 = out_woready_24 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_60 = out_roready_28 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_60 = out_woready_28 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_61 = out_roready_28 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_61 = out_woready_28 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_62 = out_roready_28 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_62 = out_woready_28 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_63 = out_roready_28 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_63 = out_woready_28 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_24 = out_roready_32 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_24 = out_woready_32 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_25 = out_roready_32 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_25 = out_woready_32 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_26 = out_roready_32 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_26 = out_woready_32 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_27 = out_roready_32 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_27 = out_woready_32 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire sberrorWrEn = out_woready_45 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_40 = out_roready_51 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_40 = out_woready_51 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_41 = out_roready_51 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_41 = out_woready_51 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_42 = out_roready_51 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_42 = out_woready_51 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_43 = out_roready_51 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_43 = out_woready_51 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire autoexecdataWrEnMaybe = out_woready_54 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire autoexecprogbufWrEnMaybe = out_woready_54 & (&{_out_backMask_T_7, _out_backMask_T_6}); // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_20 = out_roready_58 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_20 = out_woready_58 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_21 = out_roready_58 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_21 = out_woready_58 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_22 = out_roready_58 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_22 = out_woready_58 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_23 = out_roready_58 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_23 = out_woready_58 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_56 = out_roready_62 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_56 = out_woready_62 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_57 = out_roready_62 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_57 = out_woready_62 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_58 = out_roready_62 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_58 = out_woready_62 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_59 = out_roready_62 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_59 = out_woready_62 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign SBADDRESSWrEn_0 = _out_wofireMux_T_2 & out_backSel_57 & ~(auto_dmi_in_a_bits_address[8]) & (&out_backMask); // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_8 = out_roready_67 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_8 = out_woready_67 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_9 = out_roready_67 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_9 = out_woready_67 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_10 = out_roready_67 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_10 = out_woready_67 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_11 = out_roready_67 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_11 = out_woready_67 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign SBDATARdEn_0 = _out_rofireMux_T_1 & out_backSel_60 & ~(auto_dmi_in_a_bits_address[8]) & (\|out_backMask); // @[RegisterRouter.scala:87:24] assign SBDATAWrEn_0 = _out_wofireMux_T_2 & out_backSel_60 & ~(auto_dmi_in_a_bits_address[8]) & (&out_backMask); // @[RegisterRouter.scala:87:24] assign SBDATAWrData_0 = SBDATAWrEn_0 ? auto_dmi_in_a_bits_data : 32'h0; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_24 = out_roready_72 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_24 = out_woready_72 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_25 = out_roready_72 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_25 = out_woready_72 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_26 = out_roready_72 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_26 = out_woready_72 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_27 = out_roready_72 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_27 = out_woready_72 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_4 = out_roready_76 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_4 = out_woready_76 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_5 = out_roready_76 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_5 = out_woready_76 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_6 = out_roready_76 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_6 = out_woready_76 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_7 = out_roready_76 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_7 = out_woready_76 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_52 = out_roready_80 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_52 = out_woready_80 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_53 = out_roready_80 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_53 = out_woready_80 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_54 = out_roready_80 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_54 = out_woready_80 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_55 = out_roready_80 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_55 = out_woready_80 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_0 = out_roready_104 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_0 = out_woready_104 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_1 = out_roready_104 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_1 = out_woready_104 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_2 = out_roready_104 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_2 = out_woready_104 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_3 = out_roready_104 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_3 = out_woready_104 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_8 = out_roready_108 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_8 = out_woready_108 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_9 = out_roready_108 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_9 = out_woready_108 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_10 = out_roready_108 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_10 = out_woready_108 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_11 = out_roready_108 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_11 = out_woready_108 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire ABSTRACTCSWrEnMaybe = _out_wofireMux_T_2 & out_backSel_22 & ~(auto_dmi_in_a_bits_address[8]) & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_48 = out_roready_119 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_48 = out_woready_119 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_49 = out_roready_119 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_49 = out_woready_119 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_50 = out_roready_119 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_50 = out_woready_119 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_51 = out_roready_119 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_51 = out_woready_119 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_12 = out_roready_123 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_12 = out_woready_123 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_13 = out_roready_123 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_13 = out_woready_123 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_14 = out_roready_123 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_14 = out_woready_123 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_15 = out_roready_123 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_15 = out_woready_123 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_28 = out_roready_127 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_28 = out_woready_127 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_29 = out_roready_127 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_29 = out_woready_127 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_30 = out_roready_127 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_30 = out_woready_127 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_31 = out_roready_127 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_31 = out_woready_127 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_28 = out_roready_131 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_28 = out_woready_131 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_29 = out_roready_131 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_29 = out_woready_131 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_30 = out_roready_131 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_30 = out_woready_131 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_31 = out_roready_131 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_31 = out_woready_131 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_44 = out_roready_135 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_44 = out_woready_135 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_45 = out_roready_135 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_45 = out_woready_135 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_46 = out_roready_135 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_46 = out_woready_135 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_47 = out_roready_135 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_47 = out_woready_135 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_32 = out_roready_139 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_32 = out_woready_139 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_33 = out_roready_139 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_33 = out_woready_139 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_34 = out_roready_139 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_34 = out_woready_139 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_35 = out_roready_139 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_35 = out_woready_139 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign COMMANDWrEnMaybe = _out_wofireMux_T_2 & out_backSel_23 & ~(auto_dmi_in_a_bits_address[8]) & (&out_backMask); // @[RegisterRouter.scala:87:24] assign COMMANDWrDataVal = COMMANDWrEnMaybe ? auto_dmi_in_a_bits_data : 32'h0; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_16 = out_roready_144 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_16 = out_woready_144 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_17 = out_roready_144 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_17 = out_woready_144 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_18 = out_roready_144 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_18 = out_woready_144 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_19 = out_roready_144 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_19 = out_woready_144 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire out_backSel_4 = auto_dmi_in_a_bits_address[7:2] == 6'h4; // @[RegisterRouter.scala:87:24] wire out_backSel_5 = auto_dmi_in_a_bits_address[7:2] == 6'h5; // @[RegisterRouter.scala:87:24] wire out_backSel_6 = auto_dmi_in_a_bits_address[7:2] == 6'h6; // @[RegisterRouter.scala:87:24] wire out_backSel_7 = auto_dmi_in_a_bits_address[7:2] == 6'h7; // @[RegisterRouter.scala:87:24] wire out_backSel_8 = auto_dmi_in_a_bits_address[7:2] == 6'h8; // @[RegisterRouter.scala:87:24] wire out_backSel_9 = auto_dmi_in_a_bits_address[7:2] == 6'h9; // @[RegisterRouter.scala:87:24] wire out_backSel_10 = auto_dmi_in_a_bits_address[7:2] == 6'hA; // @[RegisterRouter.scala:87:24] wire out_backSel_11 = auto_dmi_in_a_bits_address[7:2] == 6'hB; // @[RegisterRouter.scala:87:24] assign out_backSel_22 = auto_dmi_in_a_bits_address[7:2] == 6'h16; // @[RegisterRouter.scala:87:24] assign out_backSel_23 = auto_dmi_in_a_bits_address[7:2] == 6'h17; // @[RegisterRouter.scala:87:24] wire out_backSel_32 = auto_dmi_in_a_bits_address[7:2] == 6'h20; // @[RegisterRouter.scala:87:24] wire out_backSel_33 = auto_dmi_in_a_bits_address[7:2] == 6'h21; // @[RegisterRouter.scala:87:24] wire out_backSel_34 = auto_dmi_in_a_bits_address[7:2] == 6'h22; // @[RegisterRouter.scala:87:24] wire out_backSel_35 = auto_dmi_in_a_bits_address[7:2] == 6'h23; // @[RegisterRouter.scala:87:24] wire out_backSel_36 = auto_dmi_in_a_bits_address[7:2] == 6'h24; // @[RegisterRouter.scala:87:24] wire out_backSel_37 = auto_dmi_in_a_bits_address[7:2] == 6'h25; // @[RegisterRouter.scala:87:24] wire out_backSel_38 = auto_dmi_in_a_bits_address[7:2] == 6'h26; // @[RegisterRouter.scala:87:24] wire out_backSel_39 = auto_dmi_in_a_bits_address[7:2] == 6'h27; // @[RegisterRouter.scala:87:24] wire out_backSel_40 = auto_dmi_in_a_bits_address[7:2] == 6'h28; // @[RegisterRouter.scala:87:24] wire out_backSel_41 = auto_dmi_in_a_bits_address[7:2] == 6'h29; // @[RegisterRouter.scala:87:24] wire out_backSel_42 = auto_dmi_in_a_bits_address[7:2] == 6'h2A; // @[RegisterRouter.scala:87:24] wire out_backSel_43 = auto_dmi_in_a_bits_address[7:2] == 6'h2B; // @[RegisterRouter.scala:87:24] wire out_backSel_44 = auto_dmi_in_a_bits_address[7:2] == 6'h2C; // @[RegisterRouter.scala:87:24] wire out_backSel_45 = auto_dmi_in_a_bits_address[7:2] == 6'h2D; // @[RegisterRouter.scala:87:24] wire out_backSel_46 = auto_dmi_in_a_bits_address[7:2] == 6'h2E; // @[RegisterRouter.scala:87:24] wire out_backSel_47 = auto_dmi_in_a_bits_address[7:2] == 6'h2F; // @[RegisterRouter.scala:87:24] assign out_backSel_57 = auto_dmi_in_a_bits_address[7:2] == 6'h39; // @[RegisterRouter.scala:87:24] assign out_backSel_60 = auto_dmi_in_a_bits_address[7:2] == 6'h3C; // @[RegisterRouter.scala:87:24] assign out_backSel_61 = auto_dmi_in_a_bits_address[7:2] == 6'h3D; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T = auto_dmi_in_a_valid & auto_dmi_in_d_ready; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1 = _out_wofireMux_T & in_bits_read; // @[RegisterRouter.scala:74:36, :87:24] assign out_roready_24 = _out_rofireMux_T_1 & out_backSel_4 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_1 & out_backSel_5 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_67 = _out_rofireMux_T_1 & out_backSel_6 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_123 = _out_rofireMux_T_1 & out_backSel_7 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_20 = _out_rofireMux_T_1 & out_backSel_8 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_1 & out_backSel_9 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_32 = _out_rofireMux_T_1 & out_backSel_10 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_131 = _out_rofireMux_T_1 & out_backSel_11 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_104 = _out_rofireMux_T_1 & out_backSel_32 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_76 = _out_rofireMux_T_1 & out_backSel_33 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_108 = _out_rofireMux_T_1 & out_backSel_34 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_1 & out_backSel_35 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_144 = _out_rofireMux_T_1 & out_backSel_36 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_58 = _out_rofireMux_T_1 & out_backSel_37 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_72 = _out_rofireMux_T_1 & out_backSel_38 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_127 = _out_rofireMux_T_1 & out_backSel_39 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_139 = _out_rofireMux_T_1 & out_backSel_40 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_1 & out_backSel_41 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_51 = _out_rofireMux_T_1 & out_backSel_42 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_135 = _out_rofireMux_T_1 & out_backSel_43 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_119 = _out_rofireMux_T_1 & out_backSel_44 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_80 = _out_rofireMux_T_1 & out_backSel_45 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_62 = _out_rofireMux_T_1 & out_backSel_46 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_28 = _out_rofireMux_T_1 & out_backSel_47 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_2 = _out_wofireMux_T & ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24] assign out_woready_24 = _out_wofireMux_T_2 & out_backSel_4 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_2 & out_backSel_5 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_67 = _out_wofireMux_T_2 & out_backSel_6 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_123 = _out_wofireMux_T_2 & out_backSel_7 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_20 = _out_wofireMux_T_2 & out_backSel_8 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_2 & out_backSel_9 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_32 = _out_wofireMux_T_2 & out_backSel_10 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_131 = _out_wofireMux_T_2 & out_backSel_11 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_54 = _out_wofireMux_T_2 & auto_dmi_in_a_bits_address[7:2] == 6'h18 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_104 = _out_wofireMux_T_2 & out_backSel_32 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_76 = _out_wofireMux_T_2 & out_backSel_33 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_108 = _out_wofireMux_T_2 & out_backSel_34 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_2 & out_backSel_35 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_144 = _out_wofireMux_T_2 & out_backSel_36 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_58 = _out_wofireMux_T_2 & out_backSel_37 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_72 = _out_wofireMux_T_2 & out_backSel_38 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_127 = _out_wofireMux_T_2 & out_backSel_39 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_139 = _out_wofireMux_T_2 & out_backSel_40 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_2 & out_backSel_41 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_51 = _out_wofireMux_T_2 & out_backSel_42 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_135 = _out_wofireMux_T_2 & out_backSel_43 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_119 = _out_wofireMux_T_2 & out_backSel_44 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_80 = _out_wofireMux_T_2 & out_backSel_45 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_62 = _out_wofireMux_T_2 & out_backSel_46 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_28 = _out_wofireMux_T_2 & out_backSel_47 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_45 = _out_wofireMux_T_2 & auto_dmi_in_a_bits_address[7:2] == 6'h38 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] wire [63:0] _GEN = {{1'h1}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {1'h1}, {1'h1}, {auto_dmi_in_a_bits_address[8]}}; // @[MuxLiteral.scala:49:10] wire [63:0][31:0] _GEN_0 = {{32'h0}, {32'h0}, {{SBDATAFieldsReg_1_3, SBDATAFieldsReg_1_2, SBDATAFieldsReg_1_1, SBDATAFieldsReg_1_0}}, {{SBDATAFieldsReg_0_3, SBDATAFieldsReg_0_2, SBDATAFieldsReg_0_1, SBDATAFieldsReg_0_0}}, {32'h0}, {32'h0}, {SBADDRESSFieldsReg_0}, {{9'h40, SBCSFieldsReg_sbbusyerror, \|_sb2tlOpt_io_sbStateOut, SBCSFieldsReg_sbreadonaddr, SBCSFieldsReg_sbaccess, SBCSFieldsReg_sbautoincrement, SBCSFieldsReg_sbreadondata, sbErrorReg_2, sbErrorReg_1, sbErrorReg_0, 12'h40F}}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {{programBufferMem_63, programBufferMem_62, programBufferMem_61, programBufferMem_60}}, {{programBufferMem_59, programBufferMem_58, programBufferMem_57, programBufferMem_56}}, {{programBufferMem_55, programBufferMem_54, programBufferMem_53, programBufferMem_52}}, {{programBufferMem_51, programBufferMem_50, programBufferMem_49, programBufferMem_48}}, {{programBufferMem_47, programBufferMem_46, programBufferMem_45, programBufferMem_44}}, {{programBufferMem_43, programBufferMem_42, programBufferMem_41, programBufferMem_40}}, {{programBufferMem_39, programBufferMem_38, programBufferMem_37, programBufferMem_36}}, {{programBufferMem_35, programBufferMem_34, programBufferMem_33, programBufferMem_32}}, {{programBufferMem_31, programBufferMem_30, programBufferMem_29, programBufferMem_28}}, {{programBufferMem_27, programBufferMem_26, programBufferMem_25, programBufferMem_24}}, {{programBufferMem_23, programBufferMem_22, programBufferMem_21, programBufferMem_20}}, {{programBufferMem_19, programBufferMem_18, programBufferMem_17, programBufferMem_16}}, {{programBufferMem_15, programBufferMem_14, programBufferMem_13, programBufferMem_12}}, {{programBufferMem_11, programBufferMem_10, programBufferMem_9, programBufferMem_8}}, {{programBufferMem_7, programBufferMem_6, programBufferMem_5, programBufferMem_4}}, {{programBufferMem_3, programBufferMem_2, programBufferMem_1, programBufferMem_0}}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {{ABSTRACTAUTOReg_autoexecprogbuf, 8'h0, ABSTRACTAUTOReg_autoexecdata[7:0]}}, {{COMMANDReg_cmdtype, COMMANDReg_control}}, {{19'h8000, abstractCommandBusy, 1'h0, ABSTRACTCSReg_cmderr, 8'h8}}, {32'h0}, {32'h0}, {{31'h0, hartHalted}}, {32'h0}, {{12'h0, {2{haveResetBitRegs}}, {2{resumereq ? ~resumeReqRegs & ~hamaskWrSel_0 : ~resumeReqRegs}}, 4'h0, ~hartHalted, ~hartHalted, {2{hartHalted}}, 8'hA2}}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {{abstractDataMem_31, abstractDataMem_30, abstractDataMem_29, abstractDataMem_28}}, {{abstractDataMem_27, abstractDataMem_26, abstractDataMem_25, abstractDataMem_24}}, {{abstractDataMem_23, abstractDataMem_22, abstractDataMem_21, abstractDataMem_20}}, {{abstractDataMem_19, abstractDataMem_18, abstractDataMem_17, abstractDataMem_16}}, {{abstractDataMem_15, abstractDataMem_14, abstractDataMem_13, abstractDataMem_12}}, {{abstractDataMem_11, abstractDataMem_10, abstractDataMem_9, abstractDataMem_8}}, {{abstractDataMem_7, abstractDataMem_6, abstractDataMem_5, abstractDataMem_4}}, {{abstractDataMem_3, abstractDataMem_2, abstractDataMem_1, abstractDataMem_0}}, {32'h0}, {32'h0}, {32'h0}, {{31'h0, hartHalted}}}; // @[package.scala:79:37] wire [2:0] dmiNodeIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] reg goReg; // @[Debug.scala:1494:27] reg [31:0] abstractGeneratedMem_0; // @[Debug.scala:1586:35] reg [31:0] abstractGeneratedMem_1; // @[Debug.scala:1586:35] wire in_1_bits_read = auto_tl_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire [9:0] _out_womask_T_681 = {{2{auto_tl_in_a_bits_mask[1]}}, {8{auto_tl_in_a_bits_mask[0]}}}; // @[RegisterRouter.scala:87:24] wire hartResumingWrEn = out_woready_1_353 & (&_out_womask_T_681); // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_682 = {{2{auto_tl_in_a_bits_mask[5]}}, {8{auto_tl_in_a_bits_mask[4]}}}; // @[RegisterRouter.scala:87:24] wire hartExceptionWrEn = out_woready_1_353 & (&_out_womask_T_682); // @[RegisterRouter.scala:87:24] wire hartHaltedWrEn = out_woready_1_536 & (&_out_womask_T_681); // @[RegisterRouter.scala:87:24] wire hartGoingWrEn = out_woready_1_536 & (&_out_womask_T_682); // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_262 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read; // @[RegisterRouter.scala:74:36, :87:24] assign out_woready_1_536 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h20 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] assign out_woready_1_353 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h21 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_938 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h68 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_518 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h69 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_199 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h6A & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_1098 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h6B & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_738 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h6C & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_450 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h6D & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_119 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h6E & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_1170 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h6F & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_834 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h70 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_664 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h71 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_986 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h72 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_39 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h73 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire [255:0] _GEN_1 = {{~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {~(auto_tl_in_a_bits_address[11])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}}; // @[MuxLiteral.scala:49:10] wire [255:0][63:0] _GEN_2 = {{{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 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6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {{abstractDataMem_31, abstractDataMem_30, abstractDataMem_29, abstractDataMem_28, abstractDataMem_27, abstractDataMem_26, abstractDataMem_25, abstractDataMem_24}}, {{abstractDataMem_23, abstractDataMem_22, abstractDataMem_21, abstractDataMem_20, abstractDataMem_19, abstractDataMem_18, abstractDataMem_17, abstractDataMem_16}}, {{abstractDataMem_15, abstractDataMem_14, abstractDataMem_13, abstractDataMem_12, abstractDataMem_11, abstractDataMem_10, abstractDataMem_9, abstractDataMem_8}}, {{abstractDataMem_7, abstractDataMem_6, abstractDataMem_5, abstractDataMem_4, abstractDataMem_3, abstractDataMem_2, abstractDataMem_1, abstractDataMem_0}}, {{programBufferMem_63, programBufferMem_62, programBufferMem_61, programBufferMem_60, programBufferMem_59, programBufferMem_58, programBufferMem_57, programBufferMem_56}}, {{programBufferMem_55, programBufferMem_54, programBufferMem_53, programBufferMem_52, programBufferMem_51, programBufferMem_50, programBufferMem_49, programBufferMem_48}}, {{programBufferMem_47, programBufferMem_46, programBufferMem_45, programBufferMem_44, programBufferMem_43, programBufferMem_42, programBufferMem_41, programBufferMem_40}}, {{programBufferMem_39, programBufferMem_38, programBufferMem_37, programBufferMem_36, programBufferMem_35, programBufferMem_34, programBufferMem_33, programBufferMem_32}}, {{programBufferMem_31, programBufferMem_30, programBufferMem_29, programBufferMem_28, programBufferMem_27, programBufferMem_26, programBufferMem_25, programBufferMem_24}}, {{programBufferMem_23, programBufferMem_22, programBufferMem_21, programBufferMem_20, programBufferMem_19, programBufferMem_18, programBufferMem_17, programBufferMem_16}}, {{programBufferMem_15, programBufferMem_14, programBufferMem_13, programBufferMem_12, programBufferMem_11, programBufferMem_10, programBufferMem_9, programBufferMem_8}}, {{programBufferMem_7, programBufferMem_6, programBufferMem_5, programBufferMem_4, programBufferMem_3, programBufferMem_2, programBufferMem_1, programBufferMem_0}}, {{abstractGeneratedMem_1, abstractGeneratedMem_0}}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h380006F}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h100073}, {64'h100026237B200073}, {64'h7B20247310802423}, {64'hF140247330000067}, {64'h100022237B202473}, {64'h4086300147413}, {64'hFE0408E300347413}, {64'h4004440310802023}, {64'hF14024737B241073}, {64'hFF0000F0440006F}, {64'h380006F00C0006F}}; // @[MuxLiteral.scala:49:10] wire [2:0] tlNodeIn_d_bits_opcode = {2'h0, in_1_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] assign abstractCommandBusy = \|ctrlStateReg; // @[Debug.scala:1732:27, :1740:42] wire commandRegIsAccessRegister = COMMANDReg_cmdtype == 8'h0; // @[Debug.scala:1277:25, :1757:58] wire _GEN_3 = ~(COMMANDReg_control[17]) \| (\|(COMMANDReg_control[15:12])) & COMMANDReg_control[15:0] < 16'h1020 & (COMMANDReg_control[22:20] == 3'h2 \| COMMANDReg_control[22:20] == 3'h3); // @[Debug.scala:1277:25, :1533:71, :1765:{63,72,106}, :1766:{58,70,104,117}, :1776:{19,54}] wire commandRegIsUnsupported = ~commandRegIsAccessRegister \| ~_GEN_3; // @[Debug.scala:1757:58, :1761:43, :1773:39, :1774:115, :1775:33, :1776:{54,73}, :1777:33] wire commandRegBadHaltResume = commandRegIsAccessRegister & _GEN_3 & ~hartHalted; // @[Debug.scala:861:31, :1757:58, :1762:43, :1773:39, :1774:115, :1776:{54,73}, :1778:{33,36}] wire _regAccessRegisterCommand_T_1 = ABSTRACTCSReg_cmderr == 3'h0; // @[Debug.scala:1183:34, :1782:103] wire _GEN_4 = COMMANDWrEn & ~(\|(COMMANDWrDataVal[31:24])) & _regAccessRegisterCommand_T_1 \| autoexec & commandRegIsAccessRegister & _regAccessRegisterCommand_T_1; // @[Debug.scala:297:{24,30}, :1272:{42,48,73}, :1279:39, :1280:65, :1285:40, :1756:60, :1757:58, :1782:{48,78,103}, :1783:{48,78}, :1790:37] wire _GEN_5 = ctrlStateReg == 2'h1; // @[Debug.scala:1732:27, :1797:30] wire _GEN_6 = commandRegIsUnsupported \| commandRegBadHaltResume; // @[Debug.scala:1761:43, :1762:43, :1773:39, :1774:115, :1776:73, :1778:33, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33] wire goAbstract = (\|ctrlStateReg) & _GEN_5 & ~_GEN_6; // @[Debug.scala:1495:32, :1732:27, :1742:44, :1789:47, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33] wire _GEN_7 = ctrlStateReg == 2'h2; // @[Debug.scala:1732:27, :1818:30]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_32( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_68 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_20( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }	module FPUFMAPipe_l3_f16_2( // @[FPU.scala:697:7] input clock, // @[FPU.scala:697:7] input reset, // @[FPU.scala:697:7] input io_in_valid, // @[FPU.scala:702:14] input io_in_bits_ldst, // @[FPU.scala:702:14] input io_in_bits_wen, // @[FPU.scala:702:14] input io_in_bits_ren1, // @[FPU.scala:702:14] input io_in_bits_ren2, // @[FPU.scala:702:14] input io_in_bits_ren3, // @[FPU.scala:702:14] input io_in_bits_swap12, // @[FPU.scala:702:14] input io_in_bits_swap23, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14] input io_in_bits_fromint, // @[FPU.scala:702:14] input io_in_bits_toint, // @[FPU.scala:702:14] input io_in_bits_fastpipe, // @[FPU.scala:702:14] input io_in_bits_fma, // @[FPU.scala:702:14] input io_in_bits_div, // @[FPU.scala:702:14] input io_in_bits_sqrt, // @[FPU.scala:702:14] input io_in_bits_wflags, // @[FPU.scala:702:14] input io_in_bits_vec, // @[FPU.scala:702:14] input [2:0] io_in_bits_rm, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14] input [1:0] io_in_bits_typ, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14] input [64:0] io_in_bits_in1, // @[FPU.scala:702:14] input [64:0] io_in_bits_in2, // @[FPU.scala:702:14] input [64:0] io_in_bits_in3, // @[FPU.scala:702:14] output [64:0] io_out_bits_data, // @[FPU.scala:702:14] output [4:0] io_out_bits_exc // @[FPU.scala:702:14] ); wire [64:0] res_data; // @[FPU.scala:728:17] wire [16:0] _fma_io_out; // @[FPU.scala:719:19] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:697:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7] wire [15:0] one = 16'h8000; // @[FPU.scala:710:19] wire [16:0] _zero_T_1 = 17'h10000; // @[FPU.scala:711:57] wire io_out_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7] wire io_out_valid; // @[FPU.scala:697:7] reg valid; // @[FPU.scala:707:22] reg in_ldst; // @[FPU.scala:708:15] reg in_wen; // @[FPU.scala:708:15] reg in_ren1; // @[FPU.scala:708:15] reg in_ren2; // @[FPU.scala:708:15] reg in_ren3; // @[FPU.scala:708:15] reg in_swap12; // @[FPU.scala:708:15] reg in_swap23; // @[FPU.scala:708:15] reg [1:0] in_typeTagIn; // @[FPU.scala:708:15] reg [1:0] in_typeTagOut; // @[FPU.scala:708:15] reg in_fromint; // @[FPU.scala:708:15] reg in_toint; // @[FPU.scala:708:15] reg in_fastpipe; // @[FPU.scala:708:15] reg in_fma; // @[FPU.scala:708:15] reg in_div; // @[FPU.scala:708:15] reg in_sqrt; // @[FPU.scala:708:15] reg in_wflags; // @[FPU.scala:708:15] reg in_vec; // @[FPU.scala:708:15] reg [2:0] in_rm; // @[FPU.scala:708:15] reg [1:0] in_fmaCmd; // @[FPU.scala:708:15] reg [1:0] in_typ; // @[FPU.scala:708:15] reg [1:0] in_fmt; // @[FPU.scala:708:15] reg [64:0] in_in1; // @[FPU.scala:708:15] reg [64:0] in_in2; // @[FPU.scala:708:15] reg [64:0] in_in3; // @[FPU.scala:708:15] wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32] wire [64:0] zero = {48'h0, _zero_T[16], 16'h0}; // @[FPU.scala:711:{32,50}] assign io_out_out_bits_data = res_data; // @[Valid.scala:135:21] wire [4:0] res_exc; // @[FPU.scala:728:17] assign io_out_out_bits_exc = res_exc; // @[Valid.scala:135:21] assign res_data = {48'h0, _fma_io_out}; // @[FPU.scala:711:50, :719:19, :728:17, :729:12] assign io_out_valid = io_out_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:697:7] valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22] if (io_in_valid_0) begin // @[FPU.scala:697:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15] in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15] in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15] in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15] in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15] in_vec <= io_in_bits_vec_0; // @[FPU.scala:697:7, :708:15] in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15] in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15] in_in2 <= io_in_bits_swap23_0 ? 65'h8000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}] in_in3 <= io_in_bits_ren3_0 \| io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}] end always @(posedge) MulAddRecFNPipe_l2_e5_s11_2 fma ( // @[FPU.scala:719:19] .clock (clock), .reset (reset), .io_validin (valid), // @[FPU.scala:707:22] .io_op (in_fmaCmd), // @[FPU.scala:708:15] .io_a (in_in1[16:0]), // @[FPU.scala:708:15, :724:12] .io_b (in_in2[16:0]), // @[FPU.scala:708:15, :725:12] .io_c (in_in3[16:0]), // @[FPU.scala:708:15, :726:12] .io_roundingMode (in_rm), // @[FPU.scala:708:15] .io_out (_fma_io_out), .io_exceptionFlags (res_exc), .io_validout (io_out_out_valid) ); // @[FPU.scala:719:19] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_70( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [13:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [13:0] source_1; // @[Monitor.scala:541:22] reg [8207:0] inflight; // @[Monitor.scala:614:27] reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [8207:0] inflight_1; // @[Monitor.scala:726:35] reg [32831:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File FIFOFixer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.util.property class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule { private def fifoMap(seq: Seq[TLSlaveParameters]) = { val (flatManagers, keepManagers) = seq.partition(policy) // We need to be careful if one flatManager and one keepManager share an existing domain // Erring on the side of caution, we will also flatten the keepManager in this case val flatDomains = Set(flatManagers.flatMap(_.fifoId):_) // => ID 0 val keepDomains = Set(keepManagers.flatMap(_.fifoId):_) -- flatDomains // => IDs compacted // Calculate what the FIFO domains look like after the fixer is applied val flatMap = flatDomains.map { x => (x, 0) }.toMap val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap val map = flatMap ++ keepMap val fixMap = seq.map { m => m.fifoId match { case None => if (policy(m)) Some(0) else None case Some(id) => Some(map(id)) // also flattens some who did not ask } } // Compress the FIFO domain space of those we are combining val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap val splatMap = seq.map { m => m.fifoId match { case None => None case Some(id) => reMap.lift(id) } } (fixMap, splatMap) } val node = new AdapterNode(TLImp)( { cp => cp }, { mp => val (fixMap, _) = fifoMap(mp.managers) mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) }) }) with TLFormatNode { override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers) // Do we need to serialize the request to this manager? val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B) // Compact the IDs of the cases we serialize val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap { case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None } val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0 val a_id = if (compacted.isEmpty) 0.U else edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address) val a_noDomain = a_id === 0.U if (false) { println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}") println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}") println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}") println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}") println("") } // Count beats val a_first = edgeIn.first(in.a) val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck // Keep one bit for each source recording if there is an outstanding request that must be made FIFO // Sources unused in the stall signal calculation should be pruned by DCE val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B })) when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO } when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B } val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c => val a_sel = c.sourceId.contains(in.a.bits.source) val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO) val track = flight.slice(c.sourceId.start, c.sourceId.end) a_sel && a_first && track.reduce(_ \|\| _) && (a_noDomain \|\| id =/= a_id) } val stall = stalls.foldLeft(false.B)(_\|\|_) out.a <> in.a in.d <> out.d out.a.valid := in.a.valid && (a_notFIFO \|\| !stall) in.a.ready := out.a.ready && (a_notFIFO \|\| !stall) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> out.b out.c <> in .c out.e <> in .e } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } //Functional cover properties property.cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction") val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W)) val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W)) val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W)) when (a_first && in.a.fire && !a_notFIFO) { SourceIdSet := UIntToOH(in.a.bits.source) } when (d_first && in.d.fire) { SourceIdClear := UIntToOH(in.d.bits.source) } SourceIdFIFOed := SourceIdFIFOed \| SourceIdSet val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U) property.cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs") //property.cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs") property.cover(!(flight.reduce(_ \|\| _)), "COVER empty", "Cover: FIFO is empty") property.cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed") property.cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped") } } } object TLFIFOFixer { // Which slaves should have their FIFOness combined? // NOTE: this transformation is still only applied for masters with requestFifo type Policy = TLSlaveParameters => Boolean import RegionType._ val all: Policy = m => true val allFIFO: Policy = m => m.fifoId.isDefined val allVolatile: Policy = m => m.regionType <= VOLATILE def apply(policy: Policy = all)(implicit p: Parameters): TLNode = { val fixer = LazyModule(new TLFIFOFixer(policy)) fixer.node } } File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File MemoryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInDevices, HasBuiltInDeviceParams, BuiltInErrorDeviceParams, BuiltInZeroDeviceParams} import freechips.rocketchip.tilelink.{ ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, RegionReplicator, TLXbar, TLInwardNode, TLOutwardNode, ProbePicker, TLEdge, TLFIFOFixer } import freechips.rocketchip.util.Location /* Parameterization of the memory-side bus created for each memory channel / case class MemoryBusParams( beatBytes: Int, blockBytes: Int, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): MemoryBus = { val mbus = LazyModule(new MemoryBus(this, loc.name)) mbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> mbus) mbus } } /* Wrapper for creating TL nodes from a bus connected to the back of each mem channel / class MemoryBus(params: MemoryBusParams, name: String = "memory_bus")(implicit p: Parameters) extends TLBusWrapper(params, name)(p) { private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val xbar = LazyModule(new TLXbar(nameSuffix = Some(name))).suggestName(busName + "_xbar") val inwardNode: TLInwardNode = replicator.map(xbar.node :=* TLFIFOFixer(TLFIFOFixer.all) := _.node) .getOrElse(xbar.node := TLFIFOFixer(TLFIFOFixer.all)) val outwardNode: TLOutwardNode = ProbePicker() := xbar.node def busView: TLEdge = xbar.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File ProbePicker.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, IdRange} /* A ProbePicker is used to unify multiple cache banks into one logical cache / class ProbePicker(implicit p: Parameters) extends LazyModule { val node = TLAdapterNode( clientFn = { p => // The ProbePicker assembles multiple clients based on the assumption they are contiguous in the clients list // This should be true for custers of xbar := BankBinder connections def combine(next: TLMasterParameters, pair: (TLMasterParameters, Seq[TLMasterParameters])) = { val (head, output) = pair if (head.visibility.exists(x => next.visibility.exists(_.overlaps(x)))) { (next, head +: output) // pair is not banked, push head without merging } else { def redact(x: TLMasterParameters) = x.v1copy(sourceId = IdRange(0,1), nodePath = Nil, visibility = Seq(AddressSet(0, ~0))) require (redact(next) == redact(head), s"${redact(next)} != ${redact(head)}") val merge = head.v1copy( sourceId = IdRange( head.sourceId.start min next.sourceId.start, head.sourceId.end max next.sourceId.end), visibility = AddressSet.unify(head.visibility ++ next.visibility)) (merge, output) } } val myNil: Seq[TLMasterParameters] = Nil val (head, output) = p.clients.init.foldRight((p.clients.last, myNil))(combine) p.v1copy(clients = head +: output) }, managerFn = { p => p }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out <> in // Based on address, adjust source to route to the correct bank if (edgeIn.client.clients.size != edgeOut.client.clients.size) { in.b.bits.source := Mux1H( edgeOut.client.clients.map(_.sourceId contains out.b.bits.source), edgeOut.client.clients.map { c => val banks = edgeIn.client.clients.filter(c.sourceId contains _.sourceId) if (banks.size == 1) { out.b.bits.source // allow sharing the value between single-bank cases } else { Mux1H( banks.map(_.visibility.map(_ contains out.b.bits.address).reduce(_ \|\| _)), banks.map(_.sourceId.start.U)) } } ) } } } } object ProbePicker { def apply()(implicit p: Parameters): TLNode = { val picker = LazyModule(new ProbePicker) picker.node } } File LazyScope.scala: package org.chipsalliance.diplomacy.lazymodule import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.ValName /** Allows dynamic creation of [[Module]] hierarchy and "shoving" logic into a [[LazyModule]]. / trait LazyScope { this: LazyModule => override def toString: String = s"LazyScope named $name" /* Evaluate `body` in the current [[LazyModule.scope]] / def apply[T](body: => T): T = { // Preserve the previous value of the [[LazyModule.scope]], because when calling [[apply]] function, // [[LazyModule.scope]] will be altered. val saved = LazyModule.scope // [[LazyModule.scope]] stack push. LazyModule.scope = Some(this) // Evaluate [[body]] in the current `scope`, saving the result to [[out]]. val out = body // Check that the `scope` after evaluating `body` is the same as when we started. require(LazyModule.scope.isDefined, s"LazyScope $name tried to exit, but scope was empty!") require( LazyModule.scope.get eq this, s"LazyScope $name exited before LazyModule ${LazyModule.scope.get.name} was closed" ) // [[LazyModule.scope]] stack pop. LazyModule.scope = saved out } } /* Used to automatically create a level of module hierarchy (a [[SimpleLazyModule]]) within which [[LazyModule]]s can * be instantiated and connected. * * It will instantiate a [[SimpleLazyModule]] to manage evaluation of `body` and evaluate `body` code snippets in this * scope. / object LazyScope { /* Create a [[LazyScope]] with an implicit instance name. * * @param body * code executed within the generated [[SimpleLazyModule]]. * @param valName * instance name of generated [[SimpleLazyModule]]. * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( body: => T )( implicit valName: ValName, p: Parameters ): T = { apply(valName.value, "SimpleLazyModule", None)(body)(p) } /* Create a [[LazyScope]] with an explicitly defined instance name. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( name: String )(body: => T )( implicit p: Parameters ): T = { apply(name, "SimpleLazyModule", None)(body)(p) } /* Create a [[LazyScope]] with an explicit instance and class name, and control inlining. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param desiredModuleName * class name of generated [[SimpleLazyModule]]. * @param overrideInlining * tell FIRRTL that this [[SimpleLazyModule]]'s module should be inlined. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( name: String, desiredModuleName: String, overrideInlining: Option[Boolean] = None )(body: => T )( implicit p: Parameters ): T = { val scope = LazyModule(new SimpleLazyModule with LazyScope { override lazy val desiredName = desiredModuleName override def shouldBeInlined = overrideInlining.getOrElse(super.shouldBeInlined) }).suggestName(name) scope { body } } /* Create a [[LazyScope]] to temporarily group children for some reason, but tell Firrtl to inline it. * * For example, we might want to control a set of children's clocks but then not keep the parent wrapper. * * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def inline[T]( body: => T )( implicit p: Parameters ): T = { apply("noname", "ShouldBeInlined", Some(false))(body)(p) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module MemoryBus( // @[ClockDomain.scala:14:9] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_mbus_clock_groups_in_member_mbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_mbus_clock_groups_in_member_mbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire coupler_to_mbusscratchpad00_auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_mbusscratchpad00_auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_mbusscratchpad00_auto_tl_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_mbusscratchpad00_auto_tl_out_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [27:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [3:0] xbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire [3:0] xbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire [7:0] xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire mbus_clock_groups_auto_out_member_mbus_0_reset; // @[ClockGroup.scala:53:9] wire mbus_clock_groups_auto_out_member_mbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [3:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _picker_auto_in_1_a_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_1_d_bits_opcode; // @[ProbePicker.scala:69:28] wire [1:0] _picker_auto_in_1_d_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_1_d_bits_size; // @[ProbePicker.scala:69:28] wire [3:0] _picker_auto_in_1_d_bits_source; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_sink; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_denied; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_in_1_d_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_a_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_0_d_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_0_d_bits_size; // @[ProbePicker.scala:69:28] wire [3:0] _picker_auto_in_0_d_bits_source; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_bits_denied; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_in_0_d_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_a_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_size; // @[ProbePicker.scala:69:28] wire [3:0] _picker_auto_out_0_a_bits_source; // @[ProbePicker.scala:69:28] wire [31:0] _picker_auto_out_0_a_bits_address; // @[ProbePicker.scala:69:28] wire [7:0] _picker_auto_out_0_a_bits_mask; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_out_0_a_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_a_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_d_ready; // @[ProbePicker.scala:69:28] wire _mbus_xbar_auto_anon_out_1_a_valid; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_opcode; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_param; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_size; // @[MemoryBus.scala:47:32] wire [3:0] _mbus_xbar_auto_anon_out_1_a_bits_source; // @[MemoryBus.scala:47:32] wire [27:0] _mbus_xbar_auto_anon_out_1_a_bits_address; // @[MemoryBus.scala:47:32] wire [7:0] _mbus_xbar_auto_anon_out_1_a_bits_mask; // @[MemoryBus.scala:47:32] wire [63:0] _mbus_xbar_auto_anon_out_1_a_bits_data; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_1_a_bits_corrupt; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_1_d_ready; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_0_a_valid; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_opcode; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_param; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_size; // @[MemoryBus.scala:47:32] wire [3:0] _mbus_xbar_auto_anon_out_0_a_bits_source; // @[MemoryBus.scala:47:32] wire [31:0] _mbus_xbar_auto_anon_out_0_a_bits_address; // @[MemoryBus.scala:47:32] wire [7:0] _mbus_xbar_auto_anon_out_0_a_bits_mask; // @[MemoryBus.scala:47:32] wire [63:0] _mbus_xbar_auto_anon_out_0_a_bits_data; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_0_a_bits_corrupt; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_0_d_ready; // @[MemoryBus.scala:47:32] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last; // @[ClockDomain.scala:14:9] wire auto_mbus_clock_groups_in_member_mbus_0_clock_0 = auto_mbus_clock_groups_in_member_mbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_mbus_clock_groups_in_member_mbus_0_reset_0 = auto_mbus_clock_groups_in_member_mbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire mbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire mbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire mbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire xbar_auto_anon_in_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire xbar_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire xbar_anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire xbar_in_0_d_bits_sink = 1'h0; // @[Xbar.scala:159:18] wire xbar_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire xbar__out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire xbar_portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire [1:0] xbar_auto_anon_in_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] xbar_auto_anon_out_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] xbar_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] xbar_anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] xbar_in_0_d_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] xbar_out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] xbar_portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire [63:0] xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [31:0] xbar__addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] xbar__addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] xbar__requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] xbar__requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] xbar__requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] xbar__beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] xbar__beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] xbar__beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] xbar__beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] xbar__portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] xbar__portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] xbar_portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] xbar__portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] xbar__portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] xbar_portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [3:0] xbar__addressC_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] xbar__addressC_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] xbar__requestBOI_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74] wire [3:0] xbar__requestBOI_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:264:61] wire [3:0] xbar__requestBOI_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29] wire [3:0] xbar_requestBOI_uncommonBits = 4'h0; // @[Parameters.scala:52:56] wire [3:0] xbar__beatsBO_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74] wire [3:0] xbar__beatsBO_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:264:61] wire [3:0] xbar__beatsCI_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] xbar__beatsCI_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] xbar__portsBIO_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74] wire [3:0] xbar__portsBIO_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:264:61] wire [3:0] xbar_portsBIO_filtered_0_bits_source = 4'h0; // @[Xbar.scala:352:24] wire [3:0] xbar__portsCOI_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] xbar__portsCOI_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] xbar_portsCOI_filtered_0_bits_source = 4'h0; // @[Xbar.scala:352:24] wire [2:0] xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [7:0] xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [9:0] fixer__allIDs_FIFOed_T = 10'h3FF; // @[FIFOFixer.scala:127:48] wire [32:0] fixer__a_notFIFO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_notFIFO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] xbar__requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire mbus_clock_groups_auto_in_member_mbus_0_clock = auto_mbus_clock_groups_in_member_mbus_0_clock_0; // @[ClockGroup.scala:53:9] wire mbus_clock_groups_auto_in_member_mbus_0_reset = auto_mbus_clock_groups_in_member_mbus_0_reset_0; // @[ClockGroup.scala:53:9] wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [27:0] auto_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire mbus_clock_groups_nodeIn_member_mbus_0_clock = mbus_clock_groups_auto_in_member_mbus_0_clock; // @[ClockGroup.scala:53:9] wire mbus_clock_groups_nodeOut_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire mbus_clock_groups_nodeIn_member_mbus_0_reset = mbus_clock_groups_auto_in_member_mbus_0_reset; // @[ClockGroup.scala:53:9] wire mbus_clock_groups_nodeOut_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_mbus_0_clock = mbus_clock_groups_auto_out_member_mbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_mbus_0_reset = mbus_clock_groups_auto_out_member_mbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign mbus_clock_groups_auto_out_member_mbus_0_clock = mbus_clock_groups_nodeOut_member_mbus_0_clock; // @[ClockGroup.scala:53:9] assign mbus_clock_groups_auto_out_member_mbus_0_reset = mbus_clock_groups_nodeOut_member_mbus_0_reset; // @[ClockGroup.scala:53:9] assign mbus_clock_groups_nodeOut_member_mbus_0_clock = mbus_clock_groups_nodeIn_member_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign mbus_clock_groups_nodeOut_member_mbus_0_reset = mbus_clock_groups_nodeIn_member_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_mbus_0_clock = clockGroup_auto_in_member_mbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_mbus_0_reset = clockGroup_auto_in_member_mbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire buffer_auto_out_a_ready = fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [31:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire buffer_auto_out_d_valid = fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] buffer_auto_out_d_bits_opcode = fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] buffer_auto_out_d_bits_param = fixer_auto_anon_in_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] buffer_auto_out_d_bits_size = fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [3:0] buffer_auto_out_d_bits_source = fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire buffer_auto_out_d_bits_sink = fixer_auto_anon_in_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire buffer_auto_out_d_bits_denied = fixer_auto_anon_in_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] buffer_auto_out_d_bits_data = fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire buffer_auto_out_d_bits_corrupt = fixer_auto_anon_in_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_sink = fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [32:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46] wire fixer__a_id_T_4 = fixer__a_id_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_id_T_5 = fixer_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46] wire fixer__a_id_T_9 = fixer__a_id_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_11 = fixer__a_id_T_9; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_10 = {fixer__a_id_T_4, 1'h0}; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_12 = {fixer__a_id_T_10[1], fixer__a_id_T_10[0] \| fixer__a_id_T_11}; // @[Mux.scala:30:73] wire [1:0] fixer_a_id = fixer__a_id_T_12; // @[Mux.scala:30:73] wire fixer_a_noDomain = fixer_a_id == 2'h0; // @[Mux.scala:30:73] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__a_first_beats1_decode_T = 13'h3F << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [5:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T \| fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__d_first_beats1_decode_T = 13'h3F << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [5:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T \| fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [9:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [9:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [9:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [15:0] fixer__SourceIdSet_T = 16'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [15:0] fixer__SourceIdClear_T = 16'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [9:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed \| fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire bus_xingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] bus_xingOut_d_bits_param = buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] bus_xingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [3:0] bus_xingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] bus_xingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_valid = buffer_auto_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_param = buffer_auto_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_size = buffer_auto_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [3:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_source = buffer_auto_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_address = buffer_auto_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_data = buffer_auto_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_d_ready = buffer_auto_out_d_ready; // @[FIFOFixer.scala:50:9] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_sink = buffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_denied = buffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] wire xbar_anonIn_a_ready; // @[MixedNode.scala:551:17] wire xbar_anonIn_a_valid = xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_anonIn_a_bits_opcode = xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_anonIn_a_bits_param = xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_anonIn_a_bits_size = xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [3:0] xbar_anonIn_a_bits_source = xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_anonIn_a_bits_address = xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_anonIn_a_bits_mask = xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_anonIn_a_bits_data = xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire xbar_anonIn_a_bits_corrupt = xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_anonIn_d_ready = xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire xbar_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire xbar_anonOut_a_ready = xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire xbar_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire xbar_anonOut_d_ready; // @[MixedNode.scala:542:17] wire xbar_anonOut_d_valid = xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_anonOut_d_bits_opcode = xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_anonOut_d_bits_size = xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] xbar_anonOut_d_bits_source = xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire xbar_anonOut_d_bits_denied = xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] xbar_anonOut_d_bits_data = xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire xbar_anonOut_d_bits_corrupt = xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9] wire xbar_out_0_a_ready = xbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_valid = xbar_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_opcode = xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_param = xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_size = xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [3:0] xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_source = xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_address = xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_mask = xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_data = xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_corrupt = xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_out_0_d_ready; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_d_ready = xbar_anonOut_d_ready; // @[Xbar.scala:74:9] wire xbar_out_0_d_valid = xbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] xbar_out_0_d_bits_opcode = xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] xbar_out_0_d_bits_size = xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [3:0] xbar_out_0_d_bits_source = xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire xbar_out_0_d_bits_denied = xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] xbar_out_0_d_bits_data = xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire xbar_out_0_d_bits_corrupt = xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire xbar_in_0_a_ready; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_a_ready = xbar_anonIn_a_ready; // @[Xbar.scala:74:9] wire xbar_in_0_a_valid = xbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_a_bits_opcode = xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_a_bits_param = xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_a_bits_size = xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [3:0] xbar__in_0_a_bits_source_T = xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] xbar_in_0_a_bits_address = xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] xbar_in_0_a_bits_mask = xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] xbar_in_0_a_bits_data = xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire xbar_in_0_a_bits_corrupt = xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire xbar_in_0_d_ready = xbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire xbar_in_0_d_valid; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_valid = xbar_anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_opcode = xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_size = xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign xbar_auto_anon_in_d_bits_source = xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9] wire xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_denied = xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_data = xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9] wire xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_corrupt = xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign xbar_anonIn_a_ready = xbar_in_0_a_ready; // @[Xbar.scala:159:18] wire xbar__portsAOI_filtered_0_valid_T_1 = xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] xbar_portsAOI_filtered_0_bits_opcode = xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] xbar_portsAOI_filtered_0_bits_param = xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] xbar_portsAOI_filtered_0_bits_size = xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] xbar_portsAOI_filtered_0_bits_source = xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] xbar__requestAIO_T = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] xbar_portsAOI_filtered_0_bits_address = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] xbar_portsAOI_filtered_0_bits_mask = xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] xbar_portsAOI_filtered_0_bits_data = xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire xbar_portsAOI_filtered_0_bits_corrupt = xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire xbar_portsDIO_filtered_0_ready = xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonIn_d_valid = xbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_opcode = xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_size = xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire [3:0] xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign xbar__anonIn_d_bits_source_T = xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_denied = xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_data = xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_corrupt = xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign xbar_in_0_a_bits_source = xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign xbar_anonIn_d_bits_source = xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign xbar_portsAOI_filtered_0_ready = xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonOut_a_valid = xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_opcode = xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_param = xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_size = xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_source = xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_address = xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_mask = xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_data = xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_corrupt = xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign xbar_anonOut_d_ready = xbar_out_0_d_ready; // @[Xbar.scala:216:19] wire xbar__portsDIO_filtered_0_valid_T_1 = xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign xbar_portsDIO_filtered_0_bits_opcode = xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_size = xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] xbar__requestDOI_uncommonBits_T = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign xbar_portsDIO_filtered_0_bits_source = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_denied = xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_data = xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_corrupt = xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire [32:0] xbar__requestAIO_T_1 = {1'h0, xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [3:0] xbar_requestDOI_uncommonBits = xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] xbar__beatsAI_decode_T = 13'h3F << xbar_in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] xbar__beatsAI_decode_T_1 = xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] xbar__beatsAI_decode_T_2 = ~xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] xbar_beatsAI_decode = xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire xbar__beatsAI_opdata_T = xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire xbar_beatsAI_opdata = ~xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] xbar_beatsAI_0 = xbar_beatsAI_opdata ? xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] xbar__beatsDO_decode_T = 13'h3F << xbar_out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] xbar__beatsDO_decode_T_1 = xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] xbar__beatsDO_decode_T_2 = ~xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] xbar_beatsDO_decode = xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire xbar_beatsDO_opdata = xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] xbar_beatsDO_0 = xbar_beatsDO_opdata ? xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign xbar_in_0_a_ready = xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign xbar_out_0_a_valid = xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_opcode = xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_param = xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_size = xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_source = xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_address = xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_mask = xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_data = xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_corrupt = xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign xbar_portsAOI_filtered_0_valid = xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign xbar_out_0_d_ready = xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign xbar_in_0_d_valid = xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_opcode = xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_size = xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_source = xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_denied = xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_data = xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_corrupt = xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign xbar_portsDIO_filtered_0_valid = xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire coupler_to_mbusscratchpad00_tlIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_a_valid = coupler_to_mbusscratchpad00_auto_tl_in_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_mbusscratchpad00_tlIn_a_bits_opcode = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_mbusscratchpad00_tlIn_a_bits_param = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_mbusscratchpad00_tlIn_a_bits_size = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_size; // @[MixedNode.scala:551:17] wire [3:0] coupler_to_mbusscratchpad00_tlIn_a_bits_source = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_source; // @[MixedNode.scala:551:17] wire [27:0] coupler_to_mbusscratchpad00_tlIn_a_bits_address = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] coupler_to_mbusscratchpad00_tlIn_a_bits_mask = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_mbusscratchpad00_tlIn_a_bits_data = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_a_bits_corrupt = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_d_ready = coupler_to_mbusscratchpad00_auto_tl_in_d_ready; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_mbusscratchpad00_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] coupler_to_mbusscratchpad00_tlIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_mbusscratchpad00_tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] coupler_to_mbusscratchpad00_tlIn_d_bits_source; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_mbusscratchpad00_tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlOut_a_ready = coupler_to_mbusscratchpad00_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_mbusscratchpad00_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_mbusscratchpad00_tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_mbusscratchpad00_tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] coupler_to_mbusscratchpad00_tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] coupler_to_mbusscratchpad00_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_to_mbusscratchpad00_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_mbusscratchpad00_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_d_valid = coupler_to_mbusscratchpad00_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_mbusscratchpad00_tlOut_d_bits_opcode = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_to_mbusscratchpad00_tlOut_d_bits_param = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_mbusscratchpad00_tlOut_d_bits_size = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire [3:0] coupler_to_mbusscratchpad00_tlOut_d_bits_source = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_d_bits_sink = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_d_bits_denied = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_mbusscratchpad00_tlOut_d_bits_data = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_d_bits_corrupt = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_auto_tl_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_mbusscratchpad00_auto_tl_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_mbusscratchpad00_auto_tl_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_mbusscratchpad00_auto_tl_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [27:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7] assign coupler_to_mbusscratchpad00_tlIn_a_ready = coupler_to_mbusscratchpad00_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_valid = coupler_to_mbusscratchpad00_tlOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_opcode = coupler_to_mbusscratchpad00_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_param = coupler_to_mbusscratchpad00_tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_size = coupler_to_mbusscratchpad00_tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_source = coupler_to_mbusscratchpad00_tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_address = coupler_to_mbusscratchpad00_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_mask = coupler_to_mbusscratchpad00_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_data = coupler_to_mbusscratchpad00_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_corrupt = coupler_to_mbusscratchpad00_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_d_ready = coupler_to_mbusscratchpad00_tlOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_tlIn_d_valid = coupler_to_mbusscratchpad00_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_opcode = coupler_to_mbusscratchpad00_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_param = coupler_to_mbusscratchpad00_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_size = coupler_to_mbusscratchpad00_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_source = coupler_to_mbusscratchpad00_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_sink = coupler_to_mbusscratchpad00_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_denied = coupler_to_mbusscratchpad00_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_data = coupler_to_mbusscratchpad00_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_corrupt = coupler_to_mbusscratchpad00_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_a_ready = coupler_to_mbusscratchpad00_tlIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_tlOut_a_valid = coupler_to_mbusscratchpad00_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_opcode = coupler_to_mbusscratchpad00_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_param = coupler_to_mbusscratchpad00_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_size = coupler_to_mbusscratchpad00_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_source = coupler_to_mbusscratchpad00_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_address = coupler_to_mbusscratchpad00_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_mask = coupler_to_mbusscratchpad00_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_data = coupler_to_mbusscratchpad00_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_corrupt = coupler_to_mbusscratchpad00_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_d_ready = coupler_to_mbusscratchpad00_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_valid = coupler_to_mbusscratchpad00_tlIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_opcode = coupler_to_mbusscratchpad00_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_param = coupler_to_mbusscratchpad00_tlIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_size = coupler_to_mbusscratchpad00_tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_source = coupler_to_mbusscratchpad00_tlIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_sink = coupler_to_mbusscratchpad00_tlIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_denied = coupler_to_mbusscratchpad00_tlIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_data = coupler_to_mbusscratchpad00_tlIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_corrupt = coupler_to_mbusscratchpad00_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_valid = bus_xingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_opcode = bus_xingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_param = bus_xingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_size = bus_xingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_source = bus_xingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_address = bus_xingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_mask = bus_xingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_data = bus_xingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_corrupt = bus_xingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_d_ready = bus_xingOut_d_ready; // @[Buffer.scala:40:9] assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 10'h0; // @[FIFOFixer.scala:115:35] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h0 \| fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h1 \| fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h2 \| fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h3 \| fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h4 \| fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h5 \| fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h6 \| fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h7 \| fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h8 \| fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h9 \| fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] end always @(posedge) FixedClockBroadcast_3_1 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0), .auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_mbus_i1_o2_a32d64s4k1z3u mbus_xbar ( // @[MemoryBus.scala:47:32] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (fixer_auto_anon_out_a_ready), .auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_valid (fixer_auto_anon_out_d_valid), .auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode), .auto_anon_in_d_bits_param (fixer_auto_anon_out_d_bits_param), .auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size), .auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source), .auto_anon_in_d_bits_sink (fixer_auto_anon_out_d_bits_sink), .auto_anon_in_d_bits_denied (fixer_auto_anon_out_d_bits_denied), .auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data), .auto_anon_in_d_bits_corrupt (fixer_auto_anon_out_d_bits_corrupt), .auto_anon_out_1_a_ready (_picker_auto_in_1_a_ready), // @[ProbePicker.scala:69:28] .auto_anon_out_1_a_valid (_mbus_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_mbus_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_mbus_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_mbus_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_mbus_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_mbus_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_mbus_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_mbus_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_mbus_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_mbus_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_picker_auto_in_1_d_valid), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_opcode (_picker_auto_in_1_d_bits_opcode), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_param (_picker_auto_in_1_d_bits_param), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_size (_picker_auto_in_1_d_bits_size), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_source (_picker_auto_in_1_d_bits_source), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_sink (_picker_auto_in_1_d_bits_sink), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_denied (_picker_auto_in_1_d_bits_denied), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_data (_picker_auto_in_1_d_bits_data), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_corrupt (_picker_auto_in_1_d_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_anon_out_0_a_ready (_picker_auto_in_0_a_ready), // @[ProbePicker.scala:69:28] .auto_anon_out_0_a_valid (_mbus_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_mbus_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_mbus_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_mbus_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_mbus_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_mbus_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_mbus_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_mbus_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_mbus_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_mbus_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_picker_auto_in_0_d_valid), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_opcode (_picker_auto_in_0_d_bits_opcode), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_size (_picker_auto_in_0_d_bits_size), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_source (_picker_auto_in_0_d_bits_source), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_denied (_picker_auto_in_0_d_bits_denied), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_data (_picker_auto_in_0_d_bits_data), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_corrupt (_picker_auto_in_0_d_bits_corrupt) // @[ProbePicker.scala:69:28] ); // @[MemoryBus.scala:47:32] ProbePicker picker ( // @[ProbePicker.scala:69:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_1_a_ready (_picker_auto_in_1_a_ready), .auto_in_1_a_valid (_mbus_xbar_auto_anon_out_1_a_valid), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_opcode (_mbus_xbar_auto_anon_out_1_a_bits_opcode), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_param (_mbus_xbar_auto_anon_out_1_a_bits_param), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_size (_mbus_xbar_auto_anon_out_1_a_bits_size), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_source (_mbus_xbar_auto_anon_out_1_a_bits_source), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_address (_mbus_xbar_auto_anon_out_1_a_bits_address), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_mask (_mbus_xbar_auto_anon_out_1_a_bits_mask), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_data (_mbus_xbar_auto_anon_out_1_a_bits_data), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_corrupt (_mbus_xbar_auto_anon_out_1_a_bits_corrupt), // @[MemoryBus.scala:47:32] .auto_in_1_d_ready (_mbus_xbar_auto_anon_out_1_d_ready), // @[MemoryBus.scala:47:32] .auto_in_1_d_valid (_picker_auto_in_1_d_valid), .auto_in_1_d_bits_opcode (_picker_auto_in_1_d_bits_opcode), .auto_in_1_d_bits_param (_picker_auto_in_1_d_bits_param), .auto_in_1_d_bits_size (_picker_auto_in_1_d_bits_size), .auto_in_1_d_bits_source (_picker_auto_in_1_d_bits_source), .auto_in_1_d_bits_sink (_picker_auto_in_1_d_bits_sink), .auto_in_1_d_bits_denied (_picker_auto_in_1_d_bits_denied), .auto_in_1_d_bits_data (_picker_auto_in_1_d_bits_data), .auto_in_1_d_bits_corrupt (_picker_auto_in_1_d_bits_corrupt), .auto_in_0_a_ready (_picker_auto_in_0_a_ready), .auto_in_0_a_valid (_mbus_xbar_auto_anon_out_0_a_valid), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_opcode (_mbus_xbar_auto_anon_out_0_a_bits_opcode), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_param (_mbus_xbar_auto_anon_out_0_a_bits_param), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_size (_mbus_xbar_auto_anon_out_0_a_bits_size), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_source (_mbus_xbar_auto_anon_out_0_a_bits_source), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_address (_mbus_xbar_auto_anon_out_0_a_bits_address), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_mask (_mbus_xbar_auto_anon_out_0_a_bits_mask), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_data (_mbus_xbar_auto_anon_out_0_a_bits_data), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_corrupt (_mbus_xbar_auto_anon_out_0_a_bits_corrupt), // @[MemoryBus.scala:47:32] .auto_in_0_d_ready (_mbus_xbar_auto_anon_out_0_d_ready), // @[MemoryBus.scala:47:32] .auto_in_0_d_valid (_picker_auto_in_0_d_valid), .auto_in_0_d_bits_opcode (_picker_auto_in_0_d_bits_opcode), .auto_in_0_d_bits_size (_picker_auto_in_0_d_bits_size), .auto_in_0_d_bits_source (_picker_auto_in_0_d_bits_source), .auto_in_0_d_bits_denied (_picker_auto_in_0_d_bits_denied), .auto_in_0_d_bits_data (_picker_auto_in_0_d_bits_data), .auto_in_0_d_bits_corrupt (_picker_auto_in_0_d_bits_corrupt), .auto_out_1_a_ready (coupler_to_mbusscratchpad00_auto_tl_in_a_ready), // @[LazyModuleImp.scala:138:7] .auto_out_1_a_valid (coupler_to_mbusscratchpad00_auto_tl_in_a_valid), .auto_out_1_a_bits_opcode (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_opcode), .auto_out_1_a_bits_param (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_param), .auto_out_1_a_bits_size (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_size), .auto_out_1_a_bits_source (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_source), .auto_out_1_a_bits_address (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_address), .auto_out_1_a_bits_mask (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_mask), .auto_out_1_a_bits_data (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_data), .auto_out_1_a_bits_corrupt (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_corrupt), .auto_out_1_d_ready (coupler_to_mbusscratchpad00_auto_tl_in_d_ready), .auto_out_1_d_valid (coupler_to_mbusscratchpad00_auto_tl_in_d_valid), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_opcode (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_param (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_size (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_source (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_sink (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_denied (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_data (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_corrupt (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_out_0_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_out_0_a_valid (_picker_auto_out_0_a_valid), .auto_out_0_a_bits_opcode (_picker_auto_out_0_a_bits_opcode), .auto_out_0_a_bits_param (_picker_auto_out_0_a_bits_param), .auto_out_0_a_bits_size (_picker_auto_out_0_a_bits_size), .auto_out_0_a_bits_source (_picker_auto_out_0_a_bits_source), .auto_out_0_a_bits_address (_picker_auto_out_0_a_bits_address), .auto_out_0_a_bits_mask (_picker_auto_out_0_a_bits_mask), .auto_out_0_a_bits_data (_picker_auto_out_0_a_bits_data), .auto_out_0_a_bits_corrupt (_picker_auto_out_0_a_bits_corrupt), .auto_out_0_d_ready (_picker_auto_out_0_d_ready), .auto_out_0_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[ProbePicker.scala:69:28] TLInterconnectCoupler_mbus_to_memory_controller_port_named_tl_mem coupler_to_memory_controller_port_named_tl_mem ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 coupler_to_memory_controller_port_named_axi4 ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_widget_anon_in_a_ready (xbar_auto_anon_out_a_ready), .auto_widget_anon_in_a_valid (xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_opcode (xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_param (xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_size (xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_source (xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_address (xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_mask (xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_data (xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_corrupt (xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9] .auto_widget_anon_in_d_ready (xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9] .auto_widget_anon_in_d_valid (xbar_auto_anon_out_d_valid), .auto_widget_anon_in_d_bits_opcode (xbar_auto_anon_out_d_bits_opcode), .auto_widget_anon_in_d_bits_size (xbar_auto_anon_out_d_bits_size), .auto_widget_anon_in_d_bits_source (xbar_auto_anon_out_d_bits_source), .auto_widget_anon_in_d_bits_denied (xbar_auto_anon_out_d_bits_denied), .auto_widget_anon_in_d_bits_data (xbar_auto_anon_out_d_bits_data), .auto_widget_anon_in_d_bits_corrupt (xbar_auto_anon_out_d_bits_corrupt), .auto_axi4yank_out_aw_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_aw_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid_0), .auto_axi4yank_out_aw_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id_0), .auto_axi4yank_out_aw_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr_0), .auto_axi4yank_out_aw_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len_0), .auto_axi4yank_out_aw_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size_0), .auto_axi4yank_out_aw_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst_0), .auto_axi4yank_out_aw_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock_0), .auto_axi4yank_out_aw_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache_0), .auto_axi4yank_out_aw_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot_0), .auto_axi4yank_out_aw_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos_0), .auto_axi4yank_out_w_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_w_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid_0), .auto_axi4yank_out_w_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data_0), .auto_axi4yank_out_w_bits_strb (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb_0), .auto_axi4yank_out_w_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last_0), .auto_axi4yank_out_b_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready_0), .auto_axi4yank_out_b_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_b_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_b_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_ar_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_ar_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid_0), .auto_axi4yank_out_ar_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id_0), .auto_axi4yank_out_ar_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr_0), .auto_axi4yank_out_ar_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len_0), .auto_axi4yank_out_ar_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size_0), .auto_axi4yank_out_ar_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst_0), .auto_axi4yank_out_ar_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock_0), .auto_axi4yank_out_ar_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache_0), .auto_axi4yank_out_ar_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot_0), .auto_axi4yank_out_ar_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos_0), .auto_axi4yank_out_r_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready_0), .auto_axi4yank_out_r_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_r_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_r_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_r_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_r_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready), .auto_tl_in_a_valid (_picker_auto_out_0_a_valid), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_opcode (_picker_auto_out_0_a_bits_opcode), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_param (_picker_auto_out_0_a_bits_param), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_size (_picker_auto_out_0_a_bits_size), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_source (_picker_auto_out_0_a_bits_source), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_address (_picker_auto_out_0_a_bits_address), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_mask (_picker_auto_out_0_a_bits_mask), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_data (_picker_auto_out_0_a_bits_data), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_corrupt (_picker_auto_out_0_a_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_tl_in_d_ready (_picker_auto_out_0_d_ready), // @[ProbePicker.scala:69:28] .auto_tl_in_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt), .auto_tl_out_a_ready (xbar_auto_anon_in_a_ready), // @[Xbar.scala:74:9] .auto_tl_out_a_valid (xbar_auto_anon_in_a_valid), .auto_tl_out_a_bits_opcode (xbar_auto_anon_in_a_bits_opcode), .auto_tl_out_a_bits_param (xbar_auto_anon_in_a_bits_param), .auto_tl_out_a_bits_size (xbar_auto_anon_in_a_bits_size), .auto_tl_out_a_bits_source (xbar_auto_anon_in_a_bits_source), .auto_tl_out_a_bits_address (xbar_auto_anon_in_a_bits_address), .auto_tl_out_a_bits_mask (xbar_auto_anon_in_a_bits_mask), .auto_tl_out_a_bits_data (xbar_auto_anon_in_a_bits_data), .auto_tl_out_a_bits_corrupt (xbar_auto_anon_in_a_bits_corrupt), .auto_tl_out_d_ready (xbar_auto_anon_in_d_ready), .auto_tl_out_d_valid (xbar_auto_anon_in_d_valid), // @[Xbar.scala:74:9] .auto_tl_out_d_bits_opcode (xbar_auto_anon_in_d_bits_opcode), // @[Xbar.scala:74:9] .auto_tl_out_d_bits_size (xbar_auto_anon_in_d_bits_size), // @[Xbar.scala:74:9] .auto_tl_out_d_bits_source (xbar_auto_anon_in_d_bits_source), // @[Xbar.scala:74:9] .auto_tl_out_d_bits_denied (xbar_auto_anon_in_d_bits_denied), // @[Xbar.scala:74:9] .auto_tl_out_d_bits_data (xbar_auto_anon_in_d_bits_data), // @[Xbar.scala:74:9] .auto_tl_out_d_bits_corrupt (xbar_auto_anon_in_d_bits_corrupt) // @[Xbar.scala:74:9] ); // @[LazyScope.scala:98:27] TLBuffer_a28d64s4k1z3u buffer_1 ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (coupler_to_mbusscratchpad00_auto_tl_out_a_ready), .auto_in_a_valid (coupler_to_mbusscratchpad00_auto_tl_out_a_valid), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_opcode (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_param (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_param), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_size (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_size), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_source (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_source), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_address (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_address), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_mask (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_mask), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_data (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_data), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_corrupt (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_in_d_ready (coupler_to_mbusscratchpad00_auto_tl_out_d_ready), // @[LazyModuleImp.scala:138:7] .auto_in_d_valid (coupler_to_mbusscratchpad00_auto_tl_out_d_valid), .auto_in_d_bits_opcode (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_opcode), .auto_in_d_bits_param (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_param), .auto_in_d_bits_size (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_size), .auto_in_d_bits_source (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_source), .auto_in_d_bits_sink (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_sink), .auto_in_d_bits_denied (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_denied), .auto_in_d_bits_data (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_data), .auto_in_d_bits_corrupt (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_corrupt), .auto_out_a_ready (auto_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_out_a_valid (auto_buffer_out_a_valid_0), .auto_out_a_bits_opcode (auto_buffer_out_a_bits_opcode_0), .auto_out_a_bits_param (auto_buffer_out_a_bits_param_0), .auto_out_a_bits_size (auto_buffer_out_a_bits_size_0), .auto_out_a_bits_source (auto_buffer_out_a_bits_source_0), .auto_out_a_bits_address (auto_buffer_out_a_bits_address_0), .auto_out_a_bits_mask (auto_buffer_out_a_bits_mask_0), .auto_out_a_bits_data (auto_buffer_out_a_bits_data_0), .auto_out_a_bits_corrupt (auto_buffer_out_a_bits_corrupt_0), .auto_out_d_ready (auto_buffer_out_d_ready_0), .auto_out_d_valid (auto_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_opcode (auto_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_param (auto_buffer_out_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_size (auto_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_source (auto_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_sink (auto_buffer_out_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_denied (auto_buffer_out_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_data (auto_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_corrupt (auto_buffer_out_d_bits_corrupt_0) // @[ClockDomain.scala:14:9] ); // @[Buffer.scala:75:28] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_corrupt = auto_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired || fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module Router_31( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [4:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_2_vc_sel_1_12; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_13; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_16; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_17; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_20; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_21; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_12; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_13; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_16; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_17; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_20; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_21; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_10; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_11; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_14; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_15; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_18; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_19; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_20; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_21; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_10; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_11; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_14; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_15; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_18; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_19; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_20; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_21; // @[Router.scala:136:32] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_12; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_13; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_16; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_17; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_21; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_12; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_13; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_16; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_17; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_21; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_10; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_11; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_14; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_15; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_18; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_19; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_21; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_10; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_11; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_14; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_15; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_18; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_19; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_21; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_10_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_11_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_14_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_15_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_18_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_19_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_21_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_12_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_13_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_16_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_17_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_21_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_12_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_13_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_16_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_17_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_21_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_10_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_11_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_14_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_15_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_18_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_19_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_12_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_13_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_16_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_17_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_12_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_13_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_16_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_17_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_2_to_37_io_credit_available_10; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_11; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_14; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_15; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_18; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_19; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_10_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_11_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_14_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_15_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_18_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_19_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_37_io_channel_status_21_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_credit_available_12; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_credit_available_13; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_credit_available_16; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_credit_available_17; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_channel_status_12_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_channel_status_13_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_channel_status_16_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_channel_status_17_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_35_io_channel_status_21_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_credit_available_12; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_credit_available_13; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_credit_available_16; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_credit_available_17; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_channel_status_12_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_channel_status_13_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_channel_status_16_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_channel_status_17_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_channel_status_21_occupied; // @[Router.scala:122:13] wire [4:0] _input_unit_2_from_37_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_37_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_2_from_37_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_37_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_2_from_37_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_37_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_vcalloc_req_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_10; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_11; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_12; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_13; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_14; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_15; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_16; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_17; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_18; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_19; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_20; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_2_21; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_37_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_2_from_37_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_37_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_2_from_37_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_37_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_2_from_37_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_37_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_37_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_35_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_35_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_35_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_35_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_35_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_35_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_10; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_11; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_14; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_15; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_18; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_19; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_20; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_21; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_10; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_11; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_12; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_13; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_14; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_15; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_16; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_17; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_18; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_19; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_20; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_21; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_35_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_35_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_35_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_35_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_35_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_35_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_35_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_35_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_16_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_16_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_16_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_16_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_16_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_16_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_10; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_11; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_14; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_15; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_18; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_19; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_20; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_21; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_10; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_11; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_12; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_13; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_14; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_15; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_16; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_17; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_18; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_19; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_20; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_21; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_16_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_16_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_16_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_35_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_37_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }

module NoCMonitor_16( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26]

Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel | (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens | chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) | 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_||_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_||_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }

module SwitchArbiter( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_3_ready, // @[SwitchAllocator.scala:18:14] input io_in_3_valid, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_4_ready, // @[SwitchAllocator.scala:18:14] input io_in_4_valid, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_5_ready, // @[SwitchAllocator.scala:18:14] input io_in_5_valid, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_6_ready, // @[SwitchAllocator.scala:18:14] input io_in_6_valid, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_7_ready, // @[SwitchAllocator.scala:18:14] input io_in_7_valid, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_tail, // @[SwitchAllocator.scala:18:14] input io_out_0_ready, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [7:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [7:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [7:0] unassigned = {io_in_7_valid, io_in_6_valid, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, 1'h0} & ~lock_0; // @[SwitchAllocator.scala:17:7, :24:38, :25:{23,52,54}] reg [7:0] mask; // @[SwitchAllocator.scala:27:21] wire [7:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [15:0] sel = _sel_T_1[0] ? 16'h1 : _sel_T_1[1] ? 16'h2 : _sel_T_1[2] ? 16'h4 : _sel_T_1[3] ? 16'h8 : _sel_T_1[4] ? 16'h10 : _sel_T_1[5] ? 16'h20 : _sel_T_1[6] ? 16'h40 : _sel_T_1[7] ? 16'h80 : unassigned[0] ? 16'h100 : unassigned[1] ? 16'h200 : unassigned[2] ? 16'h400 : unassigned[3] ? 16'h800 : unassigned[4] ? 16'h1000 : unassigned[5] ? 16'h2000 : unassigned[6] ? 16'h4000 : {unassigned[7], 15'h0}; // @[OneHot.scala:85:71] wire [6:0] _GEN = {io_in_7_valid, io_in_6_valid, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid}; // @[SwitchAllocator.scala:41:24] wire [7:0] chosen = (|(_GEN & lock_0[7:1])) ? lock_0 : sel[7:0] | sel[15:8]; // @[Mux.scala:50:70] wire [6:0] _io_out_0_valid_T = _GEN & chosen[7:1]; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire _GEN_0 = io_out_0_ready & (|_io_out_0_valid_T); // @[Decoupled.scala:51:35] wire [6:0] _GEN_1 = chosen[6:0] | chosen[7:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [5:0] _GEN_2 = _GEN_1[5:0] | chosen[7:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [4:0] _GEN_3 = _GEN_2[4:0] | chosen[7:3]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [3:0] _GEN_4 = _GEN_3[3:0] | chosen[7:4]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [2:0] _GEN_5 = _GEN_4[2:0] | chosen[7:5]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [1:0] _GEN_6 = _GEN_5[1:0] | chosen[7:6]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 8'h0; // @[SwitchAllocator.scala:24:38] mask <= 8'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (_GEN_0) // @[Decoupled.scala:51:35] lock_0 <= chosen & {~io_in_7_bits_tail, ~io_in_6_bits_tail, ~io_in_5_bits_tail, ~io_in_4_bits_tail, ~io_in_3_bits_tail, ~io_in_2_bits_tail, ~io_in_1_bits_tail, 1'h1}; // @[SwitchAllocator.scala:17:7, :24:38, :39:21, :42:21, :53:{25,27}] mask <= _GEN_0 ? {chosen[7], _GEN_1[6], _GEN_2[5], _GEN_3[4], _GEN_4[3], _GEN_5[2], _GEN_6[1], _GEN_6[0] | chosen[7]} : (&mask) ? 8'h0 : {mask[6:0], 1'h1}; // @[Decoupled.scala:51:35] end always @(posedge)

Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }

module dataMems_310( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule

Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel | (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens | chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) | 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_||_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_||_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }

module SwitchAllocator_38( // @[SwitchAllocator.scala:64:7] input clock, // @[SwitchAllocator.scala:64:7] input reset, // @[SwitchAllocator.scala:64:7] output io_req_1_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_1_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_1_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_4_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_1_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_4_alloc, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_0_0 // @[SwitchAllocator.scala:74:14] ); wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_vc_sel_1_1; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_vc_sel_1_4; // @[SwitchAllocator.scala:83:45] wire [1:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:83:45] wire [1:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire arbs_0_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_0_1 | io_req_0_0_bits_vc_sel_0_4); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_1_1 | io_req_0_0_bits_vc_sel_1_4); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_0_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_0_1 | io_req_1_0_bits_vc_sel_0_4); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_1_1 | io_req_1_0_bits_vc_sel_1_4); // @[SwitchAllocator.scala:95:{37,65}] SwitchArbiter_223 arbs_0 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_0_io_in_0_ready), .io_in_0_valid (arbs_0_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_1_1 (io_req_0_0_bits_vc_sel_1_1), .io_in_0_bits_vc_sel_1_4 (io_req_0_0_bits_vc_sel_1_4), .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1), .io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_0_io_in_1_ready), .io_in_1_valid (arbs_0_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_1_1 (io_req_1_0_bits_vc_sel_1_1), .io_in_1_bits_vc_sel_1_4 (io_req_1_0_bits_vc_sel_1_4), .io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1), .io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_out_0_valid (_arbs_0_io_out_0_valid), .io_out_0_bits_vc_sel_1_1 (/* unused */), .io_out_0_bits_vc_sel_1_4 (/* unused */), .io_out_0_bits_vc_sel_0_1 (_arbs_0_io_out_0_bits_vc_sel_0_1), .io_out_0_bits_vc_sel_0_4 (_arbs_0_io_out_0_bits_vc_sel_0_4), .io_chosen_oh_0 (_arbs_0_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_223 arbs_1 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_1_1 (io_req_0_0_bits_vc_sel_1_1), .io_in_0_bits_vc_sel_1_4 (io_req_0_0_bits_vc_sel_1_4), .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1), .io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_1_io_in_1_ready), .io_in_1_valid (arbs_1_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_1_1 (io_req_1_0_bits_vc_sel_1_1), .io_in_1_bits_vc_sel_1_4 (io_req_1_0_bits_vc_sel_1_4), .io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1), .io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_out_0_valid (_arbs_1_io_out_0_valid), .io_out_0_bits_vc_sel_1_1 (_arbs_1_io_out_0_bits_vc_sel_1_1), .io_out_0_bits_vc_sel_1_4 (_arbs_1_io_out_0_bits_vc_sel_1_4), .io_out_0_bits_vc_sel_0_1 (/* unused */), .io_out_0_bits_vc_sel_0_4 (/* unused */), .io_chosen_oh_0 (_arbs_1_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] assign io_req_1_0_ready = _arbs_0_io_in_1_ready & arbs_0_io_in_1_valid | _arbs_1_io_in_1_ready & arbs_1_io_in_1_valid; // @[Decoupled.scala:51:35] assign io_req_0_0_ready = _arbs_0_io_in_0_ready & arbs_0_io_in_0_valid | _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid; // @[Decoupled.scala:51:35] assign io_credit_alloc_1_1_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_1_4_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_4; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_1_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_4_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_switch_sel_1_0_1_0 = arbs_1_io_in_1_valid & _arbs_1_io_chosen_oh_0[1] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_1_0 = arbs_0_io_in_1_valid & _arbs_0_io_chosen_oh_0[1] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_0_0 = arbs_0_io_in_0_valid & _arbs_0_io_chosen_oh_0[0] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_36( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34] wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34] wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34] wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_732; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [19:0] inflight; // @[Monitor.scala:614:27] reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [79:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [19:0] a_set; // @[Monitor.scala:626:34] wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [79:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_658 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [19:0] d_clr; // @[Monitor.scala:664:34] wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_673 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [19:0] inflight_1; // @[Monitor.scala:726:35] wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [19:0] d_clr_1; // @[Monitor.scala:774:34] wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_758 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_12( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [31:0] _GEN_0 = {27'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [31:0] _GEN_3 = {27'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [16:0] inflight_1; // @[Monitor.scala:726:35] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_47( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [8255:0] _inflight_opcodes_T_4 = 8256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [8255:0] _inflight_sizes_T_4 = 8256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [2063:0] _inflight_T_4 = 2064'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [8255:0] d_opcodes_clr_1 = 8256'h0; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1 = 8256'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2063:0] d_clr_1 = 2064'h0; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1 = 2064'h0; // @[Monitor.scala:775:34] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_659; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_592 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_4 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_605 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }

module dataMems_297( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule

Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready || !io.in.bits.head || at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready || !io.in.bits.head || at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) && (vcalloc_q.io.enq.ready || !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }

module IngressUnit_2( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset // @[IngressUnit.scala:11:7] ); endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_245( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_262 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData_223( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }

module TLXbar_MasterXbar_SodorTile_i2_o1_a32d32s1k1z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_0_d_bits_sink; // @[Xbar.scala:216:19] wire in_1_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire requestBOI_0_0 = 1'h0; // @[Parameters.scala:46:9] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire in_0_a_bits_source = 1'h1; // @[Xbar.scala:159:18] wire _in_0_a_bits_source_T = 1'h1; // @[Xbar.scala:166:55] wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire requestBOI_0_1 = 1'h1; // @[Parameters.scala:46:9] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire portsAOI_filtered_0_bits_source = 1'h1; // @[Xbar.scala:352:24] wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _portsBIO_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsCOI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsCOI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_2_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_3_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _portsBIO_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_0_bits_mask = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_mask = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [9:0] beatsBO_decode = 10'h0; // @[Edges.scala:220:59] wire [9:0] beatsBO_0 = 10'h0; // @[Edges.scala:221:14] wire [9:0] beatsCI_decode = 10'h0; // @[Edges.scala:220:59] wire [9:0] beatsCI_0 = 10'h0; // @[Edges.scala:221:14] wire [9:0] beatsCI_decode_1 = 10'h0; // @[Edges.scala:220:59] wire [9:0] beatsCI_1 = 10'h0; // @[Edges.scala:221:14] wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [31:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18] wire _in_1_a_bits_source_T = anonIn_1_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire [3:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [31:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [31:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_ready = in_1_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [31:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_bits_source; // @[Xbar.scala:159:18] wire in_1_d_bits_source; // @[Xbar.scala:159:18] assign in_1_a_bits_source = _in_1_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire requestDOI_0_0 = out_0_d_bits_source; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_0_1 = ~out_0_d_bits_source; // @[Xbar.scala:216:19] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] beatsAI_decode = _beatsAI_decode_T_2[11:2]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [9:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:2]; // @[package.scala:243:46] wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [9:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] beatsDO_decode = _beatsDO_decode_T_2[11:2]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [9:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] reg [9:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 10'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_35( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_291 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_172( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_428 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RouteComputer.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.experimental.decode.{TruthTable, decoder} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import freechips.rocketchip.rocket.DecodeLogic import constellation.channel._ import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo} import constellation.noc.{HasNoCParams} class RouteComputerReq(implicit val p: Parameters) extends Bundle with HasNoCParams { val src_virt_id = UInt(virtualChannelBits.W) val flow = new FlowRoutingBundle } class RouteComputerResp( val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } class RouteComputer( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams with HasNoCParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new RouteComputerReq)) }) val resp = MixedVec(allInParams.map { u => Output(new RouteComputerResp(outParams, egressParams)) }) }) (io.req zip io.resp).zipWithIndex.map { case ((req, resp), i) => req.ready := true.B if (outParams.size == 0) { assert(!req.valid) resp.vc_sel := DontCare } else { def toUInt(t: (Int, FlowRoutingInfo)): UInt = { val l2 = (BigInt(t._1) << req.bits.flow.vnet_id .getWidth) | t._2.vNetId val l3 = ( l2 << req.bits.flow.ingress_node .getWidth) | t._2.ingressNode val l4 = ( l3 << req.bits.flow.ingress_node_id.getWidth) | t._2.ingressNodeId val l5 = ( l4 << req.bits.flow.egress_node .getWidth) | t._2.egressNode val l6 = ( l5 << req.bits.flow.egress_node_id .getWidth) | t._2.egressNodeId l6.U(req.bits.getWidth.W) } val flow = req.bits.flow val table = allInParams(i).possibleFlows.toSeq.distinct.map { pI => allInParams(i).channelRoutingInfos.map { cI => var row: String = "b" (0 until nOutputs).foreach { o => (0 until outParams(o).nVirtualChannels).foreach { outVId => row = row + (if (routingRelation(cI, outParams(o).channelRoutingInfos(outVId), pI)) "1" else "0") } } ((cI.vc, pI), row) } }.flatten val addr = req.bits.asUInt val width = outParams.map(_.nVirtualChannels).reduce(_+_) val decoded = if (table.size > 0) { val truthTable = TruthTable( table.map { e => (BitPat(toUInt(e._1)), BitPat(e._2)) }, BitPat("b" + "?" * width) ) Reverse(decoder(addr, truthTable)) } else { 0.U(width.W) } var idx = 0 (0 until nAllOutputs).foreach { o => if (o < nOutputs) { (0 until outParams(o).nVirtualChannels).foreach { outVId => resp.vc_sel(o)(outVId) := decoded(idx) idx += 1 } } else { resp.vc_sel(o)(0) := false.B } } } } }

module RouteComputer_61( // @[RouteComputer.scala:29:7] input [3:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_3, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_8, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_9, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_8, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_9, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_9, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_9 // @[RouteComputer.scala:40:14] ); wire [12:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id[2:0], io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node[3]}; // @[pla.scala:78:21] wire [1:0] decoded_invInputs_1 = ~(io_req_1_bits_src_virt_id[2:1]); // @[pla.scala:78:21] wire [18:0] decoded_invInputs_2 = ~{io_req_2_bits_src_virt_id, io_req_2_bits_flow_vnet_id, io_req_2_bits_flow_ingress_node, io_req_2_bits_flow_ingress_node_id, io_req_2_bits_flow_egress_node, io_req_2_bits_flow_egress_node_id[2:1]}; // @[pla.scala:78:21] wire [15:0] _decoded_andMatrixOutputs_T_4 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[1], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_5 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[1], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_7 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_8 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_9 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_11 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_13 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[16], decoded_invInputs_2[17], io_req_2_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_14 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[16], decoded_invInputs_2[17], io_req_2_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_15 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[16], decoded_invInputs_2[17], io_req_2_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] assign io_resp_2_vc_sel_1_2 = |{&{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[1], decoded_invInputs_2[18]}, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_13}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_3 = |{&{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1], decoded_invInputs_2[18]}, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_13}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_4 = |{&_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_13}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_5 = |{&{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_13}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_6 = |{&_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_13}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_7 = |{&{decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}, &_decoded_andMatrixOutputs_T_13}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_8 = &_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] assign io_resp_2_vc_sel_1_9 = &{decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_src_virt_id[0], decoded_invInputs_2[16], decoded_invInputs_2[17], io_req_2_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_2_vc_sel_0_2 = |{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_3 = |{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_4 = |{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_5 = |{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_6 = |{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_7 = |{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_8 = |{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_9 = |{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_9 = &{io_req_1_bits_src_virt_id[0], decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_0_vc_sel_2_9 = &{decoded_invInputs[0], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] endmodule

Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle

module MSHR_94( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire excluded_client = 1'h0; // @[MSHR.scala:279:28] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53] wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File RegField.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.regmapper import chisel3._ import chisel3.util.{DecoupledIO, ReadyValidIO} import org.json4s.JsonDSL._ import org.json4s.JsonAST.JValue import freechips.rocketchip.util.{SimpleRegIO} case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt)) object RegReadFn { // (ivalid: Bool, oready: Bool) => (iready: Bool, ovalid: Bool, data: UInt) // iready may combinationally depend on oready // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data is only inspected when ovalid && oready implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) = new RegReadFn(false, x) implicit def apply(x: RegisterReadIO[UInt]): RegReadFn = RegReadFn((ivalid, oready) => { x.request.valid := ivalid x.response.ready := oready (x.request.ready, x.response.valid, x.response.bits) }) // (ready: Bool) => (valid: Bool, data: UInt) // valid must not combinationally depend on ready // effects must become visible on the cycle after valid && ready implicit def apply(x: Bool => (Bool, UInt)) = new RegReadFn(true, { case (_, oready) => val (ovalid, data) = x(oready) (true.B, ovalid, data) }) // read from a ReadyValidIO (only safe if there is a consistent source of data) implicit def apply(x: ReadyValidIO[UInt]):RegReadFn = RegReadFn(ready => { x.ready := ready; (x.valid, x.bits) }) // read from a register implicit def apply(x: UInt):RegReadFn = RegReadFn(ready => (true.B, x)) // noop implicit def apply(x: Unit):RegReadFn = RegReadFn(0.U) } case class RegWriteFn private(combinational: Boolean, fn: (Bool, Bool, UInt) => (Bool, Bool)) object RegWriteFn { // (ivalid: Bool, oready: Bool, data: UInt) => (iready: Bool, ovalid: Bool) // iready may combinationally depend on both oready and data // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data should only be used for an effect when ivalid && iready implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) = new RegWriteFn(false, x) implicit def apply(x: RegisterWriteIO[UInt]): RegWriteFn = RegWriteFn((ivalid, oready, data) => { x.request.valid := ivalid x.request.bits := data x.response.ready := oready (x.request.ready, x.response.valid) }) // (valid: Bool, data: UInt) => (ready: Bool) // ready may combinationally depend on data (but not valid) // effects must become visible on the cycle after valid && ready implicit def apply(x: (Bool, UInt) => Bool) = // combinational => data valid on oready new RegWriteFn(true, { case (_, oready, data) => (true.B, x(oready, data)) }) // write to a DecoupledIO (only safe if there is a consistent sink draining data) // NOTE: this is not an IrrevocableIO (even on TL2) because other fields could cause a lowered valid implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready }) // updates a register (or adds a mux to a wire) implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; true.B }) // noop implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { true.B }) } case class RegField(width: Int, read: RegReadFn, write: RegWriteFn, desc: Option[RegFieldDesc]) { require (width >= 0, s"RegField width must be >= 0, not $width") def pipelined = !read.combinational || !write.combinational def readOnly = this.copy(write = (), desc = this.desc.map(_.copy(access = RegFieldAccessType.R))) def toJson(byteOffset: Int, bitOffset: Int): JValue = { ( ("byteOffset" -> s"0x${byteOffset.toHexString}") ~ ("bitOffset" -> bitOffset) ~ ("bitWidth" -> width) ~ ("name" -> desc.map(_.name)) ~ ("description" -> desc.map{ d=> if (d.desc == "") None else Some(d.desc)}) ~ ("resetValue" -> desc.map{_.reset}) ~ ("group" -> desc.map{_.group}) ~ ("groupDesc" -> desc.map{_.groupDesc}) ~ ("accessType" -> desc.map {d => d.access.toString}) ~ ("writeType" -> desc.map {d => d.wrType.map(_.toString)}) ~ ("readAction" -> desc.map {d => d.rdAction.map(_.toString)}) ~ ("volatile" -> desc.map {d => if (d.volatile) Some(true) else None}) ~ ("enumerations" -> desc.map {d => Option(d.enumerations.map { case (key, (name, edesc)) => (("value" -> key) ~ ("name" -> name) ~ ("description" -> edesc)) }).filter(_.nonEmpty)}) ) } } object RegField { // Byte address => sequence of bitfields, lowest index => lowest address type Map = (Int, Seq[RegField]) def apply(n: Int) : RegField = apply(n, (), (), Some(RegFieldDesc.reserved)) def apply(n: Int, desc: RegFieldDesc) : RegField = apply(n, (), (), Some(desc)) def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None) def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc)) def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw, None) def apply(n: Int, rw: UInt, desc: RegFieldDesc) : RegField = apply(n, rw, rw, Some(desc)) def r(n: Int, r: RegReadFn) : RegField = apply(n, r, (), None) def r(n: Int, r: RegReadFn, desc: RegFieldDesc) : RegField = apply(n, r, (), Some(desc.copy(access = RegFieldAccessType.R))) def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w, None) def w(n: Int, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, (), w, Some(desc.copy(access = RegFieldAccessType.W))) // This RegField allows 'set' to set bits in 'reg'. // and to clear bits when the bus writes bits of value 1. // Setting takes priority over clearing. def w1ToClear(n: Int, reg: UInt, set: UInt, desc: Option[RegFieldDesc] = None): RegField = RegField(n, reg, RegWriteFn((valid, data) => { reg := (~((~reg) | Mux(valid, data, 0.U))) | set; true.B }), desc.map{_.copy(access = RegFieldAccessType.RW, wrType=Some(RegFieldWrType.ONE_TO_CLEAR), volatile = true)}) // This RegField wraps an explicit register // (e.g. Black-Boxed Register) to create a R/W register. def rwReg(n: Int, bb: SimpleRegIO, desc: Option[RegFieldDesc] = None) : RegField = RegField(n, bb.q, RegWriteFn((valid, data) => { bb.en := valid bb.d := data true.B }), desc) // Create byte-sized read-write RegFields out of a large UInt register. // It is updated when any of the (implemented) bytes are written, the non-written // bytes are just copied over from their current value. // Because the RegField are all byte-sized, this is also suitable when a register is larger // than the intended bus width of the device (atomic updates are impossible). def bytes(reg: UInt, numBytes: Int, desc: Option[RegFieldDesc]): Seq[RegField] = { require(reg.getWidth * 8 >= numBytes, "Can't break a ${reg.getWidth}-bit-wide register into only ${numBytes} bytes.") val numFullBytes = reg.getWidth/8 val numPartialBytes = if ((reg.getWidth % 8) > 0) 1 else 0 val numPadBytes = numBytes - numFullBytes - numPartialBytes val pad = reg | 0.U((8*numBytes).W) val oldBytes = VecInit.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) } val newBytes = WireDefault(oldBytes) val valids = WireDefault(VecInit.fill(numBytes) { false.B }) when (valids.reduce(_ || _)) { reg := newBytes.asUInt } def wrFn(i: Int): RegWriteFn = RegWriteFn((valid, data) => { valids(i) := valid when (valid) {newBytes(i) := data} true.B }) val fullBytes = Seq.tabulate(numFullBytes) { i => val newDesc = desc.map {d => d.copy(name = d.name + s"_$i")} RegField(8, oldBytes(i), wrFn(i), newDesc)} val partialBytes = if (numPartialBytes > 0) { val newDesc = desc.map {d => d.copy(name = d.name + s"_$numFullBytes")} Seq(RegField(reg.getWidth % 8, oldBytes(numFullBytes), wrFn(numFullBytes), newDesc), RegField(8 - (reg.getWidth % 8))) } else Nil val padBytes = Seq.fill(numPadBytes){RegField(8)} fullBytes ++ partialBytes ++ padBytes } def bytes(reg: UInt, desc: Option[RegFieldDesc]): Seq[RegField] = { val width = reg.getWidth require (width % 8 == 0, s"RegField.bytes must be called on byte-sized reg, not ${width} bits") bytes(reg, width/8, desc) } def bytes(reg: UInt, numBytes: Int): Seq[RegField] = bytes(reg, numBytes, None) def bytes(reg: UInt): Seq[RegField] = bytes(reg, None) } trait HasRegMap { def regmap(mapping: RegField.Map*): Unit val interrupts: Vec[Bool] } // See Example.scala for an example of how to use regmap File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. */ object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct */ cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) /* Filter out any cases identical to the default */ val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2*simple.size) { /* The dense encoding case uses a Vec */ val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { /* The sparse encoding case uses switch */ val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File CLINT.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Resource, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.Annotated object CLINTConsts { def msipOffset(hart: Int) = hart * msipBytes def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes def timeOffset = 0xbff8 def msipBytes = 4 def timecmpBytes = 8 def size = 0x10000 def timeWidth = 64 def ipiWidth = 32 def ints = 2 } case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0) { def address = AddressSet(baseAddress, CLINTConsts.size-1) } case object CLINTKey extends Field[Option[CLINTParams]](None) case class CLINTAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object CLINTAttachKey extends Field(CLINTAttachParams()) class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { import CLINTConsts._ // clint0 => at most 4095 devices val device = new SimpleDevice("clint", Seq("riscv,clint0")) { override val alwaysExtended = true } val node: TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes) val intnode : IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them") val io = IO(new Bundle { val rtcTick = Input(Bool()) }) val time = RegInit(0.U(timeWidth.W)) when (io.rtcTick) { time := time + 1.U } val nTiles = intnode.out.size val timecmp = Seq.fill(nTiles) { Reg(UInt(timeWidth.W)) } val ipi = Seq.fill(nTiles) { RegInit(0.U(1.W)) } val (intnode_out, _) = intnode.out.unzip intnode_out.zipWithIndex.foreach { case (int, i) => int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip } /* 0000 msip hart 0 * 0004 msip hart 1 * 4000 mtimecmp hart 0 lo * 4004 mtimecmp hart 0 hi * 4008 mtimecmp hart 1 lo * 400c mtimecmp hart 1 hi * bff8 mtime lo * bffc mtime hi */ node.regmap( 0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) => RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }), timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"), RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))}, timeOffset -> RegFieldGroup("mtime", Some("Timer Register"), RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true)))) ) } } /** Trait that will connect a CLINT to a subsystem */ trait CanHavePeripheryCLINT { this: BaseSubsystem => val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params => val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere) val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain") val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) } clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus, Some("CLINT")) := _ } } val clintTick = clintDomainWrapper { InModuleBody { val tick = IO(Input(Bool())) clint.module.io.rtcTick := tick tick }} (clint, clintDomainWrapper, clintTick) }.unzip3 }

module CLINT( // @[CLINT.scala:65:9] input clock, // @[CLINT.scala:65:9] input reset, // @[CLINT.scala:65:9] output auto_int_out_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_rtcTick // @[CLINT.scala:69:16] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [12:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CLINT.scala:65:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CLINT.scala:65:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CLINT.scala:65:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CLINT.scala:65:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CLINT.scala:65:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CLINT.scala:65:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CLINT.scala:65:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CLINT.scala:65:9] wire io_rtcTick_0 = io_rtcTick; // @[CLINT.scala:65:9] wire [12:0] out_maskMatch = 13'h7FF; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_denied = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_corrupt = 1'h0; // @[CLINT.scala:65:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_7 = 1'h0; // @[RegField.scala:153:53] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire intnodeOut_1; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CLINT.scala:65:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CLINT.scala:65:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CLINT.scala:65:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CLINT.scala:65:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CLINT.scala:65:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CLINT.scala:65:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CLINT.scala:65:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_0_0; // @[CLINT.scala:65:9] wire auto_int_out_1_0; // @[CLINT.scala:65:9] wire auto_in_a_ready_0; // @[CLINT.scala:65:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] wire [1:0] auto_in_d_bits_size_0; // @[CLINT.scala:65:9] wire [10:0] auto_in_d_bits_source_0; // @[CLINT.scala:65:9] wire [63:0] auto_in_d_bits_data_0; // @[CLINT.scala:65:9] wire auto_in_d_valid_0; // @[CLINT.scala:65:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CLINT.scala:65:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CLINT.scala:65:9] wire [10:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CLINT.scala:65:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CLINT.scala:65:9] wire _intnodeOut_0_T; // @[CLINT.scala:82:37] assign auto_int_out_0_0 = intnodeOut_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T; // @[CLINT.scala:83:43] assign auto_int_out_1_0 = intnodeOut_1; // @[CLINT.scala:65:9] reg [63:0] time_0; // @[CLINT.scala:73:23] wire [63:0] pad_1 = time_0; // @[RegField.scala:150:19] wire [64:0] _time_T = {1'h0, time_0} + 65'h1; // @[CLINT.scala:73:23, :74:38] wire [63:0] _time_T_1 = _time_T[63:0]; // @[CLINT.scala:74:38] reg [63:0] timecmp_0; // @[CLINT.scala:77:41] wire [63:0] pad = timecmp_0; // @[RegField.scala:150:19] reg ipi_0; // @[CLINT.scala:78:41] assign _intnodeOut_0_T = ipi_0; // @[CLINT.scala:78:41, :82:37] wire _out_T_15 = ipi_0; // @[RegisterRouter.scala:87:24] assign intnodeOut_0 = _intnodeOut_0_T; // @[CLINT.scala:82:37] assign _intnodeOut_1_T = time_0 >= timecmp_0; // @[CLINT.scala:73:23, :77:41, :83:43] assign intnodeOut_1 = _intnodeOut_1_T; // @[CLINT.scala:83:43] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_123 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] timecmp_0_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_lo = {timecmp_0_lo_hi, timecmp_0_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_0_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_hi = {timecmp_0_hi_hi, timecmp_0_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_0_T = {timecmp_0_hi, timecmp_0_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_8 = pad_1[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_0 = _oldBytes_T_8; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_9 = pad_1[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_1 = _oldBytes_T_9; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_10 = pad_1[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_2 = _oldBytes_T_10; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_11 = pad_1[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_3 = _oldBytes_T_11; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_12 = pad_1[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_4 = _oldBytes_T_12; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_13 = pad_1[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_5 = _oldBytes_T_13; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_14 = pad_1[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_6 = _oldBytes_T_14; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_15 = pad_1[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_7 = _oldBytes_T_15; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_35 = oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_1_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1_1; // @[RegField.scala:152:31] wire [7:0] newBytes_1_2; // @[RegField.scala:152:31] wire [7:0] newBytes_1_3; // @[RegField.scala:152:31] wire [7:0] newBytes_1_4; // @[RegField.scala:152:31] wire [7:0] newBytes_1_5; // @[RegField.scala:152:31] wire [7:0] newBytes_1_6; // @[RegField.scala:152:31] wire [7:0] newBytes_1_7; // @[RegField.scala:152:31] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire valids_1_0; // @[RegField.scala:153:29] wire valids_1_1; // @[RegField.scala:153:29] wire valids_1_2; // @[RegField.scala:153:29] wire valids_1_3; // @[RegField.scala:153:29] wire valids_1_4; // @[RegField.scala:153:29] wire valids_1_5; // @[RegField.scala:153:29] wire valids_1_6; // @[RegField.scala:153:29] wire valids_1_7; // @[RegField.scala:153:29] wire [15:0] time_lo_lo = {newBytes_1_1, newBytes_1_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_lo_hi = {newBytes_1_3, newBytes_1_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_lo = {time_lo_hi, time_lo_lo}; // @[RegField.scala:154:52] wire [15:0] time_hi_lo = {newBytes_1_5, newBytes_1_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_hi_hi = {newBytes_1_7, newBytes_1_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_hi = {time_hi_hi, time_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _time_T_2 = {time_hi, time_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = nodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[12:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [12:0] _GEN = out_front_bits_index & 13'h7FF; // @[RegisterRouter.scala:87:24] wire [12:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [12:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_T_2 = out_findex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_T_3 = out_bindex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_6 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = _out_T_15; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = _out_T_16; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_17 = out_front_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {1'h0, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_24 = {30'h0, out_prepend}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_25 = _out_T_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_1_0 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_26 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_114 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_1_0 = out_f_woready_2 ? _out_T_26 : oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_1_1 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_125 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1_1 = out_f_woready_3 ? _out_T_37 : oldBytes_1_1; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1 = {oldBytes_1_1, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_46 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_47 = _out_T_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_2 = _out_T_47; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_1_2 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_48 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_136 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_1_2 = out_f_woready_4 ? _out_T_48 : oldBytes_1_2; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_2 = {oldBytes_1_2, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_57 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_58 = _out_T_57; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_3 = _out_T_58; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_1_3 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_59 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_147 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_1_3 = out_f_woready_5 ? _out_T_59 : oldBytes_1_3; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_3 = {oldBytes_1_3, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_4 = _out_T_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_1_4 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_70 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_158 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_1_4 = out_f_woready_6 ? _out_T_70 : oldBytes_1_4; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_4 = {oldBytes_1_4, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_79 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_80 = _out_T_79; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_5 = _out_T_80; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_84 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_1_5 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_81 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_169 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_1_5 = out_f_woready_7 ? _out_T_81 : oldBytes_1_5; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_5 = {oldBytes_1_5, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_90 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_6 = _out_T_91; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign valids_1_6 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_92 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_180 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_1_6 = out_f_woready_8 ? _out_T_92 : oldBytes_1_6; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_6 = {oldBytes_1_6, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_101 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_7 = _out_T_102; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_106 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign valids_1_7 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_103 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_191 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_1_7 = out_f_woready_9 ? _out_T_103 : oldBytes_1_7; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_110 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_7 = {oldBytes_1_7, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_112 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_113 = _out_T_112; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_2 = _out_T_113; // @[MuxLiteral.scala:49:48] wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready_10 ? _out_T_114 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_121 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_124 = _out_T_123; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_8 = _out_T_124; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = |_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = |_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_11 ? _out_T_125 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_132 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_8 = {oldBytes_1, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_134 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_135 = _out_T_134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_9 = _out_T_135; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_12 ? _out_T_136 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_9 = {oldBytes_2, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_145 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_146 = _out_T_145; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_10 = _out_T_146; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = |_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = |_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_151 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_13 ? _out_T_147 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_155 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_10 = {oldBytes_3, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_156 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_157 = _out_T_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_11 = _out_T_157; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = |_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = |_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_162 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_14 ? _out_T_158 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_166 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_11 = {oldBytes_4, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_167 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_168 = _out_T_167; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_12 = _out_T_168; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_172 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_173 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_15 ? _out_T_169 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_176 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_177 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_12 = {oldBytes_5, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_178 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_179 = _out_T_178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_13 = _out_T_179; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = |_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = |_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_183 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_184 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_16 ? _out_T_180 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_187 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_188 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_13 = {oldBytes_6, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_189 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_190 = _out_T_189; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_14 = _out_T_190; // @[RegisterRouter.scala:87:24] wire out_rimask_17 = |_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = |_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_194 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_195 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_17 ? _out_T_191 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_198 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_199 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_14 = {oldBytes_7, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_200 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_201 = _out_T_200; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = _out_T_201; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{1'h1}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_0 = {32'h0, _out_T_25}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{64'h0}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[CLINT.scala:65:9] if (reset) begin // @[CLINT.scala:65:9] time_0 <= 64'h0; // @[CLINT.scala:73:23] ipi_0 <= 1'h0; // @[CLINT.scala:78:41] end else begin // @[CLINT.scala:65:9] if (valids_1_0 | valids_1_1 | valids_1_2 | valids_1_3 | valids_1_4 | valids_1_5 | valids_1_6 | valids_1_7) // @[RegField.scala:153:29, :154:27] time_0 <= _time_T_2; // @[RegField.scala:154:52] else if (io_rtcTick_0) // @[CLINT.scala:65:9] time_0 <= _time_T_1; // @[CLINT.scala:73:23, :74:38] if (out_f_woready) // @[RegisterRouter.scala:87:24] ipi_0 <= _out_T_6; // @[RegisterRouter.scala:87:24] end if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegField.scala:153:29, :154:27] timecmp_0 <= _timecmp_0_T; // @[RegField.scala:154:52] always @(posedge) TLMonitor_46 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_int_out_0 = auto_int_out_0_0; // @[CLINT.scala:65:9] assign auto_int_out_1 = auto_int_out_1_0; // @[CLINT.scala:65:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[CLINT.scala:65:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[CLINT.scala:65:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w1_d3_i0_58( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_82 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }

module PriorityQueueStage_123( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tilelink.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLMasterToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2)) a.io.protocol <> io.tilelink.a io.tilelink.b <> b.io.protocol c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol e.io.protocol <> io.tilelink.e io.flits.a <> a.io.flit b.io.flit <> io.flits.b io.flits.c <> c.io.flit d.io.flit <> io.flits.d io.flits.e <> e.io.flit } class TLMasterACDToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) a.io.protocol <> io.tilelink.a c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol io.flits.a <> a.io.flit io.flits.c <> c.io.flit d.io.flit <> io.flits.d } class TLMasterBEToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0)) io.tilelink.b <> b.io.protocol e.io.protocol <> io.tilelink.e b.io.flit <> io.flits.b io.flits.e <> e.io.flit } class TLSlaveToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val b = Decoupled(new IngressFlit(flitWidth)) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) io.tilelink.a <> a.io.protocol b.io.protocol <> io.tilelink.b io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d io.tilelink.e <> e.io.protocol a.io.flit <> io.flits.a io.flits.b <> b.io.flit c.io.flit <> io.flits.c io.flits.d <> d.io.flit e.io.flit <> io.flits.e } class TLSlaveACDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart)) io.tilelink.a <> a.io.protocol io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d a.io.flit <> io.flits.a c.io.flit <> io.flits.c io.flits.d <> d.io.flit } class TLSlaveBEToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val b = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) b.io.protocol <> io.tilelink.b io.tilelink.e <> e.io.protocol io.flits.b <> b.io.flit e.io.flit <> io.flits.e } class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle { val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) }) val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) }) } trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper { def edgesIn: Seq[TLEdge] def edgesOut: Seq[TLEdge] def edgeInNodes: Seq[Int] def edgeOutNodes: Seq[Int] require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size) def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle)) def genBundle = new TLBundle(wideBundle) def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut) } object TLConnect { def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = { l.valid := r.valid r.ready := l.ready l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll } } // BEGIN: TileLinkProtocolParams case class TileLinkABCDEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int] ) extends TileLinkProtocolParams { // END: TileLinkProtocolParams val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten val nVirtualNetworks = 5 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A (if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B (if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D (if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { edgesIn.zipWithIndex.map { case (e,i) => val nif_master = Module(new TLMasterToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 3 + edgesIn.size * 2 + egressOffset, minPayloadWidth )) nif_master.io.tilelink := DontCare nif_master.io.tilelink.a.valid := false.B nif_master.io.tilelink.c.valid := false.B nif_master.io.tilelink.e.valid := false.B TLConnect(nif_master.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master.io.tilelink.b) TLConnect(nif_master.io.tilelink.c, protocol.in(i).c) TLConnect(nif_master.io.tilelink.e, protocol.in(i).e) } ingresses(i * 3 + 0).flit <> nif_master.io.flits.a ingresses(i * 3 + 1).flit <> nif_master.io.flits.c ingresses(i * 3 + 2).flit <> nif_master.io.flits.e nif_master.io.flits.b <> egresses(i * 2 + 0).flit nif_master.io.flits.d <> egresses(i * 2 + 1).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave = Module(new TLSlaveToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 2 + egressOffset, minPayloadWidth )) nif_slave.io.tilelink := DontCare nif_slave.io.tilelink.b.valid := false.B nif_slave.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a) TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b) TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c) TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e) } ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit } } } } } case class TileLinkACDProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val nVirtualNetworks = 3 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A (if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_acd = Module(new TLMasterACDToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 2 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_acd.io.tilelink := DontCare nif_master_acd.io.tilelink.a.valid := false.B nif_master_acd.io.tilelink.c.valid := false.B nif_master_acd.io.tilelink.e.valid := false.B TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c) } ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_acd = Module(new TLSlaveACDToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_acd.io.tilelink := DontCare nif_slave_acd.io.tilelink.b.valid := false.B nif_slave_acd.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a) TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c) } ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit } }} } } case class TileLinkBEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val nVirtualNetworks = 2 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B (if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_be = Module(new TLMasterBEToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 1 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_be.io.tilelink := DontCare nif_master_be.io.tilelink.a.valid := false.B nif_master_be.io.tilelink.c.valid := false.B nif_master_be.io.tilelink.e.valid := false.B if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b) TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e) } ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_be = Module(new TLSlaveBEToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_be.io.tilelink := DontCare nif_slave_be.io.tilelink.b.valid := false.B nif_slave_be.io.tilelink.d.valid := false.B if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e) TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b) } ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit } }} } } abstract class TLNoCLike(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") // TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers port.managers map { manager => manager.v1copy(fifoId = None) } } ) } ) } abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) { val edgesIn: Seq[TLEdge] val edgesOut: Seq[TLEdge] val nodeMapping: DiplomaticNetworkNodeMapping val nocName: String lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name))) lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name))) lazy val edgeInNodes = nodeMapping.getNodesIn(inNames) lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames) def printNodeMappings() { println(s"Constellation: TLNoC $nocName inwards mapping:") for ((n, i) <- inNames zip edgeInNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } println(s"Constellation: TLNoC $nocName outwards mapping:") for ((n, i) <- outNames zip edgeOutNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } } } trait TLNoCParams // Instantiates a private TLNoC. Replaces the TLXbar // BEGIN: TLNoCParams case class SimpleTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, nocParams: NoCParams = NoCParams(), ) extends TLNoCParams class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { // END: TLNoCParams override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val noc = Module(new ProtocolNoC(ProtocolNoCParams( params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC), Seq(protocolParams), inlineNoC = inlineNoC ))) noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } } case class SplitACDxBETLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, acdNoCParams: NoCParams = NoCParams(), beNoCParams: NoCParams = NoCParams(), beDivision: Int = 2 ) extends TLNoCParams class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val acdProtocolParams = TileLinkACDProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val beProtocolParams = TileLinkBEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC), Seq(acdProtocolParams), inlineNoC = inlineNoC ))) val be_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC), Seq(beProtocolParams), widthDivision = params.beDivision, inlineNoC = inlineNoC ))) acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } }} be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.b <> r.b l.e <> r.e } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.b <> r.b l.e <> r.e } }} } } case class GlobalTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping ) extends TLNoCParams // Maps this interconnect onto a global NoC class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike { lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) printNodeMappings() val io_global = IO(Flipped(protocolParams.genIO())) io_global match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } }

module TLSlaveACDToNoC_4( // @[Tilelink.scala:161:7] input clock, // @[Tilelink.scala:161:7] input reset, // @[Tilelink.scala:161:7] input io_tilelink_a_ready, // @[Tilelink.scala:168:14] output io_tilelink_a_valid, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:168:14] output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:168:14] output [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:168:14] output [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:168:14] output [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:168:14] output [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:168:14] output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:168:14] input io_tilelink_c_ready, // @[Tilelink.scala:168:14] output io_tilelink_c_valid, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:168:14] output [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:168:14] output [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:168:14] output [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:168:14] output [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:168:14] output io_tilelink_c_bits_corrupt, // @[Tilelink.scala:168:14] output io_tilelink_d_ready, // @[Tilelink.scala:168:14] input io_tilelink_d_valid, // @[Tilelink.scala:168:14] input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:168:14] input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:168:14] input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:168:14] input [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:168:14] input [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:168:14] input io_tilelink_d_bits_denied, // @[Tilelink.scala:168:14] input [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:168:14] input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:168:14] output io_flits_a_ready, // @[Tilelink.scala:168:14] input io_flits_a_valid, // @[Tilelink.scala:168:14] input io_flits_a_bits_head, // @[Tilelink.scala:168:14] input io_flits_a_bits_tail, // @[Tilelink.scala:168:14] input [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:168:14] output io_flits_c_ready, // @[Tilelink.scala:168:14] input io_flits_c_valid, // @[Tilelink.scala:168:14] input io_flits_c_bits_head, // @[Tilelink.scala:168:14] input io_flits_c_bits_tail, // @[Tilelink.scala:168:14] input [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:168:14] input io_flits_d_ready, // @[Tilelink.scala:168:14] output io_flits_d_valid, // @[Tilelink.scala:168:14] output io_flits_d_bits_head, // @[Tilelink.scala:168:14] output io_flits_d_bits_tail, // @[Tilelink.scala:168:14] output [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:168:14] output [3:0] io_flits_d_bits_egress_id // @[Tilelink.scala:168:14] ); wire [64:0] _d_io_flit_bits_payload; // @[Tilelink.scala:179:17] TLAFromNoC a ( // @[Tilelink.scala:177:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload) ); // @[Tilelink.scala:177:17] TLCFromNoC_1 c ( // @[Tilelink.scala:178:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (io_flits_c_bits_payload[64:0]) // @[Tilelink.scala:185:14] ); // @[Tilelink.scala:178:17] TLDToNoC_4 d ( // @[Tilelink.scala:179:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (_d_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_d_bits_egress_id) ); // @[Tilelink.scala:179:17] assign io_flits_d_bits_payload = {8'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:161:7, :179:17, :186:14] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }

module IssueSlot_3( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [5:0] io_spec_ld_wakeup_0_bits = 6'h0; // @[issue-slot.scala:69:7] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]

Generate the Verilog code corresponding to the following Chisel files. File arbiter.scala: //************************************************************************** // Arbiter for Princeton Architectures //-------------------------------------------------------------------------- // // Arbitrates instruction and data accesses to a single port memory. package sodor.stage3 import chisel3._ import chisel3.util._ import sodor.common._ // arbitrates memory access class SodorMemArbiter(implicit val conf: SodorCoreParams) extends Module { val io = IO(new Bundle { // TODO I need to come up with better names... this is too confusing // from the point of view of the other modules val imem = Flipped(new MemPortIo(conf.xprlen)) // instruction fetch val dmem = Flipped(new MemPortIo(conf.xprlen)) // load/store val mem = new MemPortIo(conf.xprlen) // the single-ported memory }) val d_resp = RegInit(false.B) // hook up requests // d_resp ensures that data req gets access to bus only // for one cycle // alternate between data and instr to avoid starvation when (d_resp) { // Last request is a data request - do not allow data request this cycle io.dmem.req.ready := false.B io.imem.req.ready := io.mem.req.ready // We only clear the d_resp flag when the next request fired since it also indicates the allowed type of the next request when (io.mem.req.fire) { d_resp := false.B } } .otherwise { // Last request is not a data request - if this cycle has a new data request, dispatch it io.dmem.req.ready := io.mem.req.ready io.imem.req.ready := io.mem.req.ready && !io.dmem.req.valid when (io.dmem.req.fire) { d_resp := true.B } } // SWITCH BET DATA AND INST REQ FOR SINGLE PORT when (io.dmem.req.fire) { io.mem.req.valid := io.dmem.req.valid io.mem.req.bits.addr := io.dmem.req.bits.addr io.mem.req.bits.fcn := io.dmem.req.bits.fcn io.mem.req.bits.typ := io.dmem.req.bits.typ } .otherwise { io.mem.req.valid := io.imem.req.valid io.mem.req.bits.addr := io.imem.req.bits.addr io.mem.req.bits.fcn := io.imem.req.bits.fcn io.mem.req.bits.typ := io.imem.req.bits.typ } // Control valid signal when (d_resp) { io.imem.resp.valid := false.B io.dmem.resp.valid := io.mem.resp.valid } .otherwise { io.imem.resp.valid := io.mem.resp.valid io.dmem.resp.valid := false.B } // No need to switch data since instruction port doesn't write io.mem.req.bits.data := io.dmem.req.bits.data // Simply connect response data to both ports since we only have one inflight request // the validity of the data is controlled above io.imem.resp.bits.data := io.mem.resp.bits.data io.dmem.resp.bits.data := io.mem.resp.bits.data }

module SodorMemArbiter( // @[arbiter.scala:15:7] input clock, // @[arbiter.scala:15:7] input reset, // @[arbiter.scala:15:7] output io_imem_req_ready, // @[arbiter.scala:17:14] input io_imem_req_valid, // @[arbiter.scala:17:14] input [31:0] io_imem_req_bits_addr, // @[arbiter.scala:17:14] output io_imem_resp_valid, // @[arbiter.scala:17:14] output [31:0] io_imem_resp_bits_data, // @[arbiter.scala:17:14] output io_dmem_req_ready, // @[arbiter.scala:17:14] input io_dmem_req_valid, // @[arbiter.scala:17:14] input [31:0] io_dmem_req_bits_addr, // @[arbiter.scala:17:14] input [31:0] io_dmem_req_bits_data, // @[arbiter.scala:17:14] input io_dmem_req_bits_fcn, // @[arbiter.scala:17:14] input [2:0] io_dmem_req_bits_typ, // @[arbiter.scala:17:14] output io_dmem_resp_valid, // @[arbiter.scala:17:14] output [31:0] io_dmem_resp_bits_data, // @[arbiter.scala:17:14] output io_mem_req_valid, // @[arbiter.scala:17:14] output [31:0] io_mem_req_bits_addr, // @[arbiter.scala:17:14] output [31:0] io_mem_req_bits_data, // @[arbiter.scala:17:14] output io_mem_req_bits_fcn, // @[arbiter.scala:17:14] output [2:0] io_mem_req_bits_typ, // @[arbiter.scala:17:14] input io_mem_resp_valid, // @[arbiter.scala:17:14] input [31:0] io_mem_resp_bits_data // @[arbiter.scala:17:14] ); wire io_imem_req_valid_0 = io_imem_req_valid; // @[arbiter.scala:15:7] wire [31:0] io_imem_req_bits_addr_0 = io_imem_req_bits_addr; // @[arbiter.scala:15:7] wire io_dmem_req_valid_0 = io_dmem_req_valid; // @[arbiter.scala:15:7] wire [31:0] io_dmem_req_bits_addr_0 = io_dmem_req_bits_addr; // @[arbiter.scala:15:7] wire [31:0] io_dmem_req_bits_data_0 = io_dmem_req_bits_data; // @[arbiter.scala:15:7] wire io_dmem_req_bits_fcn_0 = io_dmem_req_bits_fcn; // @[arbiter.scala:15:7] wire [2:0] io_dmem_req_bits_typ_0 = io_dmem_req_bits_typ; // @[arbiter.scala:15:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[arbiter.scala:15:7] wire [31:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[arbiter.scala:15:7] wire io_mem_req_ready = 1'h1; // @[arbiter.scala:15:7] wire [2:0] io_imem_req_bits_typ = 3'h7; // @[arbiter.scala:15:7, :17:14] wire io_imem_req_bits_fcn = 1'h0; // @[arbiter.scala:15:7] wire [31:0] io_imem_req_bits_data = 32'h0; // @[arbiter.scala:15:7, :17:14] wire [31:0] io_mem_req_bits_data_0 = io_dmem_req_bits_data_0; // @[arbiter.scala:15:7] wire [31:0] io_imem_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[arbiter.scala:15:7] wire [31:0] io_dmem_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[arbiter.scala:15:7] wire io_imem_req_ready_0; // @[arbiter.scala:15:7] wire io_imem_resp_valid_0; // @[arbiter.scala:15:7] wire io_dmem_req_ready_0; // @[arbiter.scala:15:7] wire io_dmem_resp_valid_0; // @[arbiter.scala:15:7] wire [31:0] io_mem_req_bits_addr_0; // @[arbiter.scala:15:7] wire io_mem_req_bits_fcn_0; // @[arbiter.scala:15:7] wire [2:0] io_mem_req_bits_typ_0; // @[arbiter.scala:15:7] wire io_mem_req_valid_0; // @[arbiter.scala:15:7] reg d_resp; // @[arbiter.scala:26:23] assign io_dmem_req_ready_0 = ~d_resp; // @[arbiter.scala:15:7, :26:23, :33:3, :35:23, :47:23] wire _io_imem_req_ready_T = ~io_dmem_req_valid_0; // @[arbiter.scala:15:7, :48:46] wire _io_imem_req_ready_T_1 = _io_imem_req_ready_T; // @[arbiter.scala:48:{43,46}] assign io_imem_req_ready_0 = d_resp | _io_imem_req_ready_T_1; // @[arbiter.scala:15:7, :26:23, :33:3, :36:23, :48:{23,43}] wire _T_2 = io_dmem_req_ready_0 & io_dmem_req_valid_0; // @[Decoupled.scala:51:35] assign io_mem_req_valid_0 = _T_2 ? io_dmem_req_valid_0 : io_imem_req_valid_0; // @[Decoupled.scala:51:35] assign io_mem_req_bits_addr_0 = _T_2 ? io_dmem_req_bits_addr_0 : io_imem_req_bits_addr_0; // @[Decoupled.scala:51:35] assign io_mem_req_bits_fcn_0 = _T_2 & io_dmem_req_bits_fcn_0; // @[Decoupled.scala:51:35] assign io_mem_req_bits_typ_0 = _T_2 ? io_dmem_req_bits_typ_0 : 3'h7; // @[Decoupled.scala:51:35] assign io_imem_resp_valid_0 = ~d_resp & io_mem_resp_valid_0; // @[arbiter.scala:15:7, :26:23, :72:3, :73:24, :77:24] assign io_dmem_resp_valid_0 = d_resp & io_mem_resp_valid_0; // @[arbiter.scala:15:7, :26:23, :72:3, :74:24, :78:24] always @(posedge clock) begin // @[arbiter.scala:15:7] if (reset) // @[arbiter.scala:15:7] d_resp <= 1'h0; // @[arbiter.scala:26:23] else if (d_resp) // @[arbiter.scala:26:23] d_resp <= ~io_mem_req_valid_0 & d_resp; // @[arbiter.scala:15:7, :26:23, :40:5, :41:14] else // @[arbiter.scala:26:23] d_resp <= io_dmem_req_ready_0 & io_dmem_req_valid_0 | d_resp; // @[Decoupled.scala:51:35] always @(posedge) assign io_imem_req_ready = io_imem_req_ready_0; // @[arbiter.scala:15:7] assign io_imem_resp_valid = io_imem_resp_valid_0; // @[arbiter.scala:15:7] assign io_imem_resp_bits_data = io_imem_resp_bits_data_0; // @[arbiter.scala:15:7] assign io_dmem_req_ready = io_dmem_req_ready_0; // @[arbiter.scala:15:7] assign io_dmem_resp_valid = io_dmem_resp_valid_0; // @[arbiter.scala:15:7] assign io_dmem_resp_bits_data = io_dmem_resp_bits_data_0; // @[arbiter.scala:15:7] assign io_mem_req_valid = io_mem_req_valid_0; // @[arbiter.scala:15:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[arbiter.scala:15:7] assign io_mem_req_bits_data = io_mem_req_bits_data_0; // @[arbiter.scala:15:7] assign io_mem_req_bits_fcn = io_mem_req_bits_fcn_0; // @[arbiter.scala:15:7] assign io_mem_req_bits_typ = io_mem_req_bits_typ_0; // @[arbiter.scala:15:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module TLFragmenter_2( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [13:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [13:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [1:0] _maxLgHint_T = {2{~(_repeater_io_deq_bits_address[8])}}; // @[Mux.scala:30:73] wire [1:0] _maxLgHint_T_1 = {2{_repeater_io_deq_bits_address[8]}}; // @[Mux.scala:30:73] wire [7:0][1:0] _GEN_0 = {{2'h3}, {2'h3}, {_maxLgHint_T | _maxLgHint_T_1}, {_maxLgHint_T | _maxLgHint_T_1}, {_maxLgHint_T | _maxLgHint_T_1}, {_maxLgHint_T | _maxLgHint_T_1}, {_maxLgHint_T | _maxLgHint_T_1}, {_maxLgHint_T | _maxLgHint_T_1}}; // @[Mux.scala:30:73] wire [1:0] limit = _GEN_0[_repeater_io_deq_bits_opcode]; // @[Fragmenter.scala:274:30, :288:49] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]

Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }

module PE_175( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty || floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) || helper(unswizzled, prevT) val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL*/fmv.*.x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) | x, maxType) } // implement NaN unboxing and un-recoding for FS*/fmv.x.* def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out | (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma || cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg || io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid || io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm || io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx || mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 | memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) || divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) | Mux(divSqrt_wen, divSqrt_flags, 0.U) | Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight) io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B || io.keep_clock_enabled || // chicken bit io.valid || // ID stage req_valid || // EX stage mem_reg_valid || mem_cp_valid || // MEM stage wb_reg_valid || wb_cp_valid || // WB stage wen.orR || divSqrt_inFlight || // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) } File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File fpu.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ package boom.v3.exu import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile.FPConstants._ import freechips.rocketchip.tile.{FPUCtrlSigs, HasFPUParameters} import freechips.rocketchip.tile import freechips.rocketchip.rocket import freechips.rocketchip.util.uintToBitPat import boom.v3.common._ import boom.v3.util.{ImmGenRm, ImmGenTyp} /** * FP Decoder for the FPU * * TODO get rid of this decoder and move into the Decode stage? Or the RRd stage? * most of these signals are already created, just need to be translated * to the Rocket FPU-speak */ class UOPCodeFPUDecoder(implicit p: Parameters) extends BoomModule with HasFPUParameters { val io = IO(new Bundle { val uopc = Input(Bits(UOPC_SZ.W)) val sigs = Output(new FPUCtrlSigs()) }) // TODO change N,Y,X to BitPat("b1"), BitPat("b0"), and BitPat("b?") val N = false.B val Y = true.B val X = false.B val default: List[BitPat] = List(X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) val f_table: Array[(BitPat, List[BitPat])] = // Note: not all of these signals are used or necessary, but we're // constrained by the need to fit the rocket.FPU units' ctrl signals. // swap12 fma // | swap32 | div // | | typeTagIn | | sqrt // ldst | | | typeTagOut | | wflags // | wen | | | | from_int | | | // | | ren1 | | | | | to_int | | | // | | | ren2 | | | | | | fastpipe | // | | | | ren3 | | | | | | | | | | // | | | | | | | | | | | | | | | | Array( BitPat(uopFCLASS_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,N), BitPat(uopFMV_W_X) -> List(X,X,N,N,N, X,X,S,D,Y,N,N, N,N,N,N), BitPat(uopFMV_X_W) -> List(X,X,Y,N,N, N,X,D,S,N,Y,N, N,N,N,N), BitPat(uopFCVT_S_X) -> List(X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), BitPat(uopFCVT_X_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), BitPat(uopCMPR_S) -> List(X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), BitPat(uopFSGNJ_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), BitPat(uopFMINMAX_S)-> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y), BitPat(uopFADD_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), BitPat(uopFSUB_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), BitPat(uopFMUL_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,N, Y,N,N,Y), BitPat(uopFMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), BitPat(uopFMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), BitPat(uopFNMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), BitPat(uopFNMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y) ) val d_table: Array[(BitPat, List[BitPat])] = Array( BitPat(uopFCLASS_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), BitPat(uopFMV_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,N), BitPat(uopFMV_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), BitPat(uopFCVT_S_D) -> List(X,X,Y,N,N, N,X,D,S,N,N,Y, N,N,N,Y), BitPat(uopFCVT_D_S) -> List(X,X,Y,N,N, N,X,S,D,N,N,Y, N,N,N,Y), BitPat(uopFCVT_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), BitPat(uopFCVT_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), BitPat(uopCMPR_D) -> List(X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), BitPat(uopFSGNJ_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), BitPat(uopFMINMAX_D)-> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y), BitPat(uopFADD_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), BitPat(uopFSUB_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), BitPat(uopFMUL_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,N, Y,N,N,Y), BitPat(uopFMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), BitPat(uopFMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), BitPat(uopFNMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), BitPat(uopFNMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y) ) // val insns = fLen match { // case 32 => f_table // case 64 => f_table ++ d_table // } val insns = f_table ++ d_table val decoder = rocket.DecodeLogic(io.uopc, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags) sigs zip decoder map {case(s,d) => s := d} s.vec := false.B } /** * FP fused multiple add decoder for the FPU */ class FMADecoder extends Module { val io = IO(new Bundle { val uopc = Input(UInt(UOPC_SZ.W)) val cmd = Output(UInt(2.W)) }) val default: List[BitPat] = List(BitPat("b??")) val table: Array[(BitPat, List[BitPat])] = Array( BitPat(uopFADD_S) -> List(BitPat("b00")), BitPat(uopFSUB_S) -> List(BitPat("b01")), BitPat(uopFMUL_S) -> List(BitPat("b00")), BitPat(uopFMADD_S) -> List(BitPat("b00")), BitPat(uopFMSUB_S) -> List(BitPat("b01")), BitPat(uopFNMADD_S) -> List(BitPat("b11")), BitPat(uopFNMSUB_S) -> List(BitPat("b10")), BitPat(uopFADD_D) -> List(BitPat("b00")), BitPat(uopFSUB_D) -> List(BitPat("b01")), BitPat(uopFMUL_D) -> List(BitPat("b00")), BitPat(uopFMADD_D) -> List(BitPat("b00")), BitPat(uopFMSUB_D) -> List(BitPat("b01")), BitPat(uopFNMADD_D) -> List(BitPat("b11")), BitPat(uopFNMSUB_D) -> List(BitPat("b10")) ) val decoder = rocket.DecodeLogic(io.uopc, default, table) val (cmd: UInt) :: Nil = decoder io.cmd := cmd } /** * Bundle representing data to be sent to the FPU */ class FpuReq()(implicit p: Parameters) extends BoomBundle { val uop = new MicroOp() val rs1_data = Bits(65.W) val rs2_data = Bits(65.W) val rs3_data = Bits(65.W) val fcsr_rm = Bits(tile.FPConstants.RM_SZ.W) } /** * FPU unit that wraps the RocketChip FPU units (which in turn wrap hardfloat) */ class FPU(implicit p: Parameters) extends BoomModule with tile.HasFPUParameters { val io = IO(new Bundle { val req = Flipped(new ValidIO(new FpuReq)) val resp = new ValidIO(new ExeUnitResp(65)) }) io.resp.bits := DontCare // all FP units are padded out to the same latency for easy scheduling of the write port val fpu_latency = dfmaLatency val io_req = io.req.bits val fp_decoder = Module(new UOPCodeFPUDecoder) fp_decoder.io.uopc := io_req.uop.uopc val fp_ctrl = fp_decoder.io.sigs val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io_req.fcsr_rm, ImmGenRm(io_req.uop.imm_packed)) def fuInput(minT: Option[tile.FType]): tile.FPInput = { val req = Wire(new tile.FPInput) val tag = fp_ctrl.typeTagIn req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl req.rm := fp_rm req.in1 := unbox(io_req.rs1_data, tag, minT) req.in2 := unbox(io_req.rs2_data, tag, minT) req.in3 := unbox(io_req.rs3_data, tag, minT) when (fp_ctrl.swap23) { req.in3 := req.in2 } req.typ := ImmGenTyp(io_req.uop.imm_packed) req.fmt := Mux(tag === S, 0.U, 1.U) // TODO support Zfh and avoid special-case below when (io_req.uop.uopc === uopFMV_X_W) { req.fmt := 0.U } val fma_decoder = Module(new FMADecoder) fma_decoder.io.uopc := io_req.uop.uopc req.fmaCmd := fma_decoder.io.cmd // ex_reg_inst(3,2) | (!fp_ctrl.ren3 && ex_reg_inst(27)) req } val dfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.D)) dfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === D) dfma.io.in.bits := fuInput(Some(dfma.t)) val sfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.S)) sfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === S) sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new tile.FPToInt) fpiu.io.in.valid := io.req.valid && (fp_ctrl.toint || (fp_ctrl.fastpipe && fp_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) val fpiu_out = Pipe(RegNext(fpiu.io.in.valid && !fp_ctrl.fastpipe), fpiu.io.out.bits, fpu_latency-1) val fpiu_result = Wire(new tile.FPResult) fpiu_result.data := fpiu_out.bits.toint fpiu_result.exc := fpiu_out.bits.exc val fpmu = Module(new tile.FPToFP(fpu_latency)) // latency 2 for rocket fpmu.io.in.valid := io.req.valid && fp_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val fpmu_double = Pipe(io.req.valid && fp_ctrl.fastpipe, fp_ctrl.typeTagOut === D, fpu_latency).bits // Response (all FP units have been padded out to the same latency) io.resp.valid := fpiu_out.valid || fpmu.io.out.valid || sfma.io.out.valid || dfma.io.out.valid val fpu_out_data = Mux(dfma.io.out.valid, box(dfma.io.out.bits.data, true.B), Mux(sfma.io.out.valid, box(sfma.io.out.bits.data, false.B), Mux(fpiu_out.valid, fpiu_result.data, box(fpmu.io.out.bits.data, fpmu_double)))) val fpu_out_exc = Mux(dfma.io.out.valid, dfma.io.out.bits.exc, Mux(sfma.io.out.valid, sfma.io.out.bits.exc, Mux(fpiu_out.valid, fpiu_result.exc, fpmu.io.out.bits.exc))) io.resp.bits.data := fpu_out_data io.resp.bits.fflags.valid := io.resp.valid io.resp.bits.fflags.bits.flags := fpu_out_exc }

module FPU( // @[fpu.scala:170:7] input clock, // @[fpu.scala:170:7] input reset, // @[fpu.scala:170:7] input io_req_valid, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_uopc, // @[fpu.scala:172:14] input [31:0] io_req_bits_uop_inst, // @[fpu.scala:172:14] input [31:0] io_req_bits_uop_debug_inst, // @[fpu.scala:172:14] input io_req_bits_uop_is_rvc, // @[fpu.scala:172:14] input [39:0] io_req_bits_uop_debug_pc, // @[fpu.scala:172:14] input [2:0] io_req_bits_uop_iq_type, // @[fpu.scala:172:14] input [9:0] io_req_bits_uop_fu_code, // @[fpu.scala:172:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[fpu.scala:172:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[fpu.scala:172:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[fpu.scala:172:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[fpu.scala:172:14] input io_req_bits_uop_ctrl_fcn_dw, // @[fpu.scala:172:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[fpu.scala:172:14] input io_req_bits_uop_ctrl_is_load, // @[fpu.scala:172:14] input io_req_bits_uop_ctrl_is_sta, // @[fpu.scala:172:14] input io_req_bits_uop_ctrl_is_std, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_iw_state, // @[fpu.scala:172:14] input io_req_bits_uop_iw_p1_poisoned, // @[fpu.scala:172:14] input io_req_bits_uop_iw_p2_poisoned, // @[fpu.scala:172:14] input io_req_bits_uop_is_br, // @[fpu.scala:172:14] input io_req_bits_uop_is_jalr, // @[fpu.scala:172:14] input io_req_bits_uop_is_jal, // @[fpu.scala:172:14] input io_req_bits_uop_is_sfb, // @[fpu.scala:172:14] input [15:0] io_req_bits_uop_br_mask, // @[fpu.scala:172:14] input [3:0] io_req_bits_uop_br_tag, // @[fpu.scala:172:14] input [4:0] io_req_bits_uop_ftq_idx, // @[fpu.scala:172:14] input io_req_bits_uop_edge_inst, // @[fpu.scala:172:14] input [5:0] io_req_bits_uop_pc_lob, // @[fpu.scala:172:14] input io_req_bits_uop_taken, // @[fpu.scala:172:14] input [19:0] io_req_bits_uop_imm_packed, // @[fpu.scala:172:14] input [11:0] io_req_bits_uop_csr_addr, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_rob_idx, // @[fpu.scala:172:14] input [4:0] io_req_bits_uop_ldq_idx, // @[fpu.scala:172:14] input [4:0] io_req_bits_uop_stq_idx, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_rxq_idx, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_pdst, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_prs1, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_prs2, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_prs3, // @[fpu.scala:172:14] input [4:0] io_req_bits_uop_ppred, // @[fpu.scala:172:14] input io_req_bits_uop_prs1_busy, // @[fpu.scala:172:14] input io_req_bits_uop_prs2_busy, // @[fpu.scala:172:14] input io_req_bits_uop_prs3_busy, // @[fpu.scala:172:14] input io_req_bits_uop_ppred_busy, // @[fpu.scala:172:14] input [6:0] io_req_bits_uop_stale_pdst, // @[fpu.scala:172:14] input io_req_bits_uop_exception, // @[fpu.scala:172:14] input [63:0] io_req_bits_uop_exc_cause, // @[fpu.scala:172:14] input io_req_bits_uop_bypassable, // @[fpu.scala:172:14] input [4:0] io_req_bits_uop_mem_cmd, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_mem_size, // @[fpu.scala:172:14] input io_req_bits_uop_mem_signed, // @[fpu.scala:172:14] input io_req_bits_uop_is_fence, // @[fpu.scala:172:14] input io_req_bits_uop_is_fencei, // @[fpu.scala:172:14] input io_req_bits_uop_is_amo, // @[fpu.scala:172:14] input io_req_bits_uop_uses_ldq, // @[fpu.scala:172:14] input io_req_bits_uop_uses_stq, // @[fpu.scala:172:14] input io_req_bits_uop_is_sys_pc2epc, // @[fpu.scala:172:14] input io_req_bits_uop_is_unique, // @[fpu.scala:172:14] input io_req_bits_uop_flush_on_commit, // @[fpu.scala:172:14] input io_req_bits_uop_ldst_is_rs1, // @[fpu.scala:172:14] input [5:0] io_req_bits_uop_ldst, // @[fpu.scala:172:14] input [5:0] io_req_bits_uop_lrs1, // @[fpu.scala:172:14] input [5:0] io_req_bits_uop_lrs2, // @[fpu.scala:172:14] input [5:0] io_req_bits_uop_lrs3, // @[fpu.scala:172:14] input io_req_bits_uop_ldst_val, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_dst_rtype, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[fpu.scala:172:14] input io_req_bits_uop_frs3_en, // @[fpu.scala:172:14] input io_req_bits_uop_fp_val, // @[fpu.scala:172:14] input io_req_bits_uop_fp_single, // @[fpu.scala:172:14] input io_req_bits_uop_xcpt_pf_if, // @[fpu.scala:172:14] input io_req_bits_uop_xcpt_ae_if, // @[fpu.scala:172:14] input io_req_bits_uop_xcpt_ma_if, // @[fpu.scala:172:14] input io_req_bits_uop_bp_debug_if, // @[fpu.scala:172:14] input io_req_bits_uop_bp_xcpt_if, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[fpu.scala:172:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[fpu.scala:172:14] input [64:0] io_req_bits_rs1_data, // @[fpu.scala:172:14] input [64:0] io_req_bits_rs2_data, // @[fpu.scala:172:14] input [64:0] io_req_bits_rs3_data, // @[fpu.scala:172:14] input [2:0] io_req_bits_fcsr_rm, // @[fpu.scala:172:14] output [64:0] io_resp_bits_data, // @[fpu.scala:172:14] output io_resp_bits_fflags_valid, // @[fpu.scala:172:14] output [4:0] io_resp_bits_fflags_bits_flags // @[fpu.scala:172:14] ); wire io_resp_valid; // @[fpu.scala:170:7] wire _fpmu_io_out_valid; // @[fpu.scala:225:20] wire [64:0] _fpmu_io_out_bits_data; // @[fpu.scala:225:20] wire [4:0] _fpmu_io_out_bits_exc; // @[fpu.scala:225:20] wire _fpiu_io_out_bits_in_ldst; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_wen; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_ren1; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_ren2; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_ren3; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_swap12; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_swap23; // @[fpu.scala:216:20] wire [1:0] _fpiu_io_out_bits_in_typeTagIn; // @[fpu.scala:216:20] wire [1:0] _fpiu_io_out_bits_in_typeTagOut; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_fromint; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_toint; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_fastpipe; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_fma; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_div; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_sqrt; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_in_wflags; // @[fpu.scala:216:20] wire [2:0] _fpiu_io_out_bits_in_rm; // @[fpu.scala:216:20] wire [1:0] _fpiu_io_out_bits_in_fmaCmd; // @[fpu.scala:216:20] wire [1:0] _fpiu_io_out_bits_in_typ; // @[fpu.scala:216:20] wire [1:0] _fpiu_io_out_bits_in_fmt; // @[fpu.scala:216:20] wire [64:0] _fpiu_io_out_bits_in_in1; // @[fpu.scala:216:20] wire [64:0] _fpiu_io_out_bits_in_in2; // @[fpu.scala:216:20] wire [64:0] _fpiu_io_out_bits_in_in3; // @[fpu.scala:216:20] wire _fpiu_io_out_bits_lt; // @[fpu.scala:216:20] wire [63:0] _fpiu_io_out_bits_store; // @[fpu.scala:216:20] wire [63:0] _fpiu_io_out_bits_toint; // @[fpu.scala:216:20] wire [4:0] _fpiu_io_out_bits_exc; // @[fpu.scala:216:20] wire _sfma_io_out_valid; // @[fpu.scala:212:20] wire [64:0] _sfma_io_out_bits_data; // @[fpu.scala:212:20] wire [4:0] _sfma_io_out_bits_exc; // @[fpu.scala:212:20] wire _dfma_io_out_valid; // @[fpu.scala:208:20] wire [64:0] _dfma_io_out_bits_data; // @[fpu.scala:208:20] wire [4:0] _dfma_io_out_bits_exc; // @[fpu.scala:208:20] wire _fp_decoder_io_sigs_ldst; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_wen; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_ren1; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_ren2; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_ren3; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_swap12; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_swap23; // @[fpu.scala:182:26] wire [1:0] _fp_decoder_io_sigs_typeTagIn; // @[fpu.scala:182:26] wire [1:0] _fp_decoder_io_sigs_typeTagOut; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_fromint; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_toint; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_fma; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_div; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_sqrt; // @[fpu.scala:182:26] wire _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26] wire io_req_valid_0 = io_req_valid; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[fpu.scala:170:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[fpu.scala:170:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[fpu.scala:170:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[fpu.scala:170:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[fpu.scala:170:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[fpu.scala:170:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[fpu.scala:170:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[fpu.scala:170:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[fpu.scala:170:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[fpu.scala:170:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[fpu.scala:170:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[fpu.scala:170:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[fpu.scala:170:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[fpu.scala:170:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[fpu.scala:170:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[fpu.scala:170:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[fpu.scala:170:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[fpu.scala:170:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[fpu.scala:170:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[fpu.scala:170:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[fpu.scala:170:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[fpu.scala:170:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[fpu.scala:170:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[fpu.scala:170:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[fpu.scala:170:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[fpu.scala:170:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[fpu.scala:170:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[fpu.scala:170:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[fpu.scala:170:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[fpu.scala:170:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[fpu.scala:170:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[fpu.scala:170:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[fpu.scala:170:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[fpu.scala:170:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[fpu.scala:170:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[fpu.scala:170:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[fpu.scala:170:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[fpu.scala:170:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[fpu.scala:170:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[fpu.scala:170:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[fpu.scala:170:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[fpu.scala:170:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[fpu.scala:170:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[fpu.scala:170:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[fpu.scala:170:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[fpu.scala:170:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[fpu.scala:170:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[fpu.scala:170:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[fpu.scala:170:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[fpu.scala:170:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[fpu.scala:170:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[fpu.scala:170:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[fpu.scala:170:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[fpu.scala:170:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[fpu.scala:170:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[fpu.scala:170:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[fpu.scala:170:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[fpu.scala:170:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[fpu.scala:170:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[fpu.scala:170:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[fpu.scala:170:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[fpu.scala:170:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[fpu.scala:170:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[fpu.scala:170:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[fpu.scala:170:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[fpu.scala:170:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[fpu.scala:170:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[fpu.scala:170:7] wire [64:0] io_req_bits_rs3_data_0 = io_req_bits_rs3_data; // @[fpu.scala:170:7] wire [2:0] io_req_bits_fcsr_rm_0 = io_req_bits_fcsr_rm; // @[fpu.scala:170:7] wire [64:0] _dfma_io_in_bits_req_in1_T = 65'h0; // @[FPU.scala:372:31] wire [64:0] _dfma_io_in_bits_req_in2_T = 65'h0; // @[FPU.scala:372:31] wire [64:0] _dfma_io_in_bits_req_in3_T = 65'h0; // @[FPU.scala:372:31] wire [4:0] fpu_out_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [4:0] fpu_out_data_opts_bigger_swizzledNaN_hi_hi_1 = 5'h1F; // @[FPU.scala:336:26] wire [4:0] fpu_out_data_opts_bigger_swizzledNaN_hi_hi_2 = 5'h1F; // @[FPU.scala:336:26] wire _fpu_out_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42] wire _fpu_out_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56] wire _fpu_out_data_T = 1'h1; // @[package.scala:39:86] wire _fpu_out_data_opts_bigger_swizzledNaN_T_4 = 1'h1; // @[FPU.scala:338:42] wire _fpu_out_data_opts_bigger_T_1 = 1'h1; // @[FPU.scala:249:56] wire _fpu_out_data_opts_bigger_swizzledNaN_T_8 = 1'h1; // @[FPU.scala:338:42] wire _fpu_out_data_opts_bigger_T_2 = 1'h1; // @[FPU.scala:249:56] wire [63:0] io_resp_bits_uop_exc_cause = 64'h0; // @[fpu.scala:170:7] wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[fpu.scala:170:7] wire [11:0] io_resp_bits_uop_csr_addr = 12'h0; // @[fpu.scala:170:7] wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[fpu.scala:170:7] wire [19:0] io_resp_bits_uop_imm_packed = 20'h0; // @[fpu.scala:170:7] wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_uop_pc_lob = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_uop_ldst = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_uop_lrs1 = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_uop_lrs2 = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_uop_lrs3 = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_fflags_bits_uop_ldst = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[fpu.scala:170:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[fpu.scala:170:7] wire [15:0] io_resp_bits_uop_br_mask = 16'h0; // @[fpu.scala:170:7] wire [15:0] io_resp_bits_fflags_bits_uop_br_mask = 16'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_uop_ftq_idx = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_uop_ldq_idx = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_uop_stq_idx = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_uop_ppred = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_uop_mem_cmd = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_fflags_bits_uop_ppred = 5'h0; // @[fpu.scala:170:7] wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_iw_state = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_rxq_idx = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_mem_size = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_dst_rtype = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_lrs1_rtype = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_lrs2_rtype = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_debug_fsrc = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_uop_debug_tsrc = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_iw_state = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_mem_size = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[fpu.scala:170:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[fpu.scala:170:7] wire [3:0] io_resp_bits_uop_ctrl_br_type = 4'h0; // @[fpu.scala:170:7] wire [3:0] io_resp_bits_uop_br_tag = 4'h0; // @[fpu.scala:170:7] wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[fpu.scala:170:7] wire [3:0] io_resp_bits_fflags_bits_uop_br_tag = 4'h0; // @[fpu.scala:170:7] wire [9:0] io_resp_bits_uop_fu_code = 10'h0; // @[fpu.scala:170:7] wire [9:0] io_resp_bits_fflags_bits_uop_fu_code = 10'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_uop_iq_type = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_fflags_bits_uop_iq_type = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[fpu.scala:170:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[fpu.scala:170:7] wire [39:0] io_resp_bits_uop_debug_pc = 40'h0; // @[fpu.scala:170:7] wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[fpu.scala:170:7] wire [31:0] io_resp_bits_uop_inst = 32'h0; // @[fpu.scala:170:7] wire [31:0] io_resp_bits_uop_debug_inst = 32'h0; // @[fpu.scala:170:7] wire [31:0] io_resp_bits_fflags_bits_uop_inst = 32'h0; // @[fpu.scala:170:7] wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_uopc = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_rob_idx = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_pdst = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_prs1 = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_prs2 = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_prs3 = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_uop_stale_pdst = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_uopc = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_pdst = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs1 = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs2 = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs3 = 7'h0; // @[fpu.scala:170:7] wire [6:0] io_resp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_rvc = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ctrl_fcn_dw = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ctrl_is_load = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ctrl_is_sta = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ctrl_is_std = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_iw_p1_poisoned = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_iw_p2_poisoned = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_br = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_jalr = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_jal = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_sfb = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_edge_inst = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_taken = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_prs1_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_prs2_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_prs3_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ppred_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_exception = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_bypassable = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_mem_signed = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_fence = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_fencei = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_amo = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_uses_ldq = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_uses_stq = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_sys_pc2epc = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_is_unique = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_flush_on_commit = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ldst_is_rs1 = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_ldst_val = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_frs3_en = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_fp_val = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_fp_single = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_xcpt_pf_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_xcpt_ae_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_xcpt_ma_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_bp_debug_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_uop_bp_xcpt_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_predicated = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_br = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_jal = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_taken = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_exception = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_bypassable = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_fence = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_amo = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_is_unique = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_fp_val = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_fp_single = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[fpu.scala:170:7] wire io_resp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[fpu.scala:170:7] wire dfma_io_in_bits_req_vec = 1'h0; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_vec = 1'h0; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_vec = 1'h0; // @[fpu.scala:188:19] wire _fpu_out_data_T_2 = 1'h0; // @[package.scala:39:86] wire [64:0] _dfma_io_in_bits_req_in1_T_1 = io_req_bits_rs1_data_0; // @[FPU.scala:372:26] wire [64:0] _dfma_io_in_bits_req_in2_T_1 = io_req_bits_rs2_data_0; // @[FPU.scala:372:26] wire [64:0] _dfma_io_in_bits_req_in3_T_1 = io_req_bits_rs3_data_0; // @[FPU.scala:372:26] wire _io_resp_valid_T_2; // @[fpu.scala:234:38] wire io_resp_bits_fflags_valid_0 = io_resp_valid; // @[fpu.scala:170:7] wire [64:0] fpu_out_data; // @[fpu.scala:237:8] wire [4:0] fpu_out_exc; // @[fpu.scala:243:8] wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[fpu.scala:170:7] wire [64:0] io_resp_bits_data_0; // @[fpu.scala:170:7] wire [2:0] _fp_rm_T = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire [2:0] _fp_rm_T_2 = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire _fp_rm_T_1 = &_fp_rm_T; // @[util.scala:289:58] wire [2:0] fp_rm = _fp_rm_T_1 ? io_req_bits_fcsr_rm_0 : _fp_rm_T_2; // @[util.scala:289:58] wire [2:0] dfma_io_in_bits_req_rm = fp_rm; // @[fpu.scala:185:18, :188:19] wire [2:0] sfma_io_in_bits_req_rm = fp_rm; // @[fpu.scala:185:18, :188:19] wire [2:0] fpiu_io_in_bits_req_rm = fp_rm; // @[fpu.scala:185:18, :188:19] wire _GEN = io_req_valid_0 & _fp_decoder_io_sigs_fma; // @[fpu.scala:170:7, :182:26, :209:36] wire _dfma_io_in_valid_T; // @[fpu.scala:209:36] assign _dfma_io_in_valid_T = _GEN; // @[fpu.scala:209:36] wire _sfma_io_in_valid_T; // @[fpu.scala:213:36] assign _sfma_io_in_valid_T = _GEN; // @[fpu.scala:209:36, :213:36] wire _GEN_0 = _fp_decoder_io_sigs_typeTagOut == 2'h1; // @[fpu.scala:182:26, :209:74] wire _dfma_io_in_valid_T_1; // @[fpu.scala:209:74] assign _dfma_io_in_valid_T_1 = _GEN_0; // @[fpu.scala:209:74] wire _fpmu_double_T_1; // @[fpu.scala:229:79] assign _fpmu_double_T_1 = _GEN_0; // @[fpu.scala:209:74, :229:79] wire _dfma_io_in_valid_T_2 = _dfma_io_in_valid_T & _dfma_io_in_valid_T_1; // @[fpu.scala:209:{36,51,74}] wire [1:0] _dfma_io_in_bits_req_typ_T; // @[util.scala:295:59] wire dfma_io_in_bits_req_ldst; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_wen; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_ren1; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_ren2; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_ren3; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_swap12; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_swap23; // @[fpu.scala:188:19] wire [1:0] dfma_io_in_bits_req_typeTagIn; // @[fpu.scala:188:19] wire [1:0] dfma_io_in_bits_req_typeTagOut; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_fromint; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_toint; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_fastpipe; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_fma; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_div; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_sqrt; // @[fpu.scala:188:19] wire dfma_io_in_bits_req_wflags; // @[fpu.scala:188:19] wire [1:0] dfma_io_in_bits_req_fmaCmd; // @[fpu.scala:188:19] wire [1:0] dfma_io_in_bits_req_typ; // @[fpu.scala:188:19] wire [1:0] dfma_io_in_bits_req_fmt; // @[fpu.scala:188:19] wire [64:0] dfma_io_in_bits_req_in1; // @[fpu.scala:188:19] wire [64:0] dfma_io_in_bits_req_in2; // @[fpu.scala:188:19] wire [64:0] dfma_io_in_bits_req_in3; // @[fpu.scala:188:19] wire _dfma_io_in_bits_req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _sfma_io_in_bits_req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] dfma_io_in_bits_req_in1_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in1_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in1_prev_prev_sign = dfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in1_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in1_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in1_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_expOut_T | _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in1_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in1_floats_0 = {dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _sfma_io_in_bits_req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _fpiu_io_in_bits_req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire dfma_io_in_bits_req_in1_prev_isbox = &_dfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in1_oks_0 = dfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in1 = _dfma_io_in_bits_req_in1_T_1; // @[FPU.scala:372:26] wire _dfma_io_in_bits_req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _sfma_io_in_bits_req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] dfma_io_in_bits_req_in2_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in2_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in2_prev_prev_sign = dfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in2_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in2_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in2_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_expOut_T | _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in2_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in2_floats_0 = {dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _sfma_io_in_bits_req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _fpiu_io_in_bits_req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire dfma_io_in_bits_req_in2_prev_isbox = &_dfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in2_oks_0 = dfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in2 = _dfma_io_in_bits_req_in2_T_1; // @[FPU.scala:372:26] wire _dfma_io_in_bits_req_in3_prev_unswizzled_T = io_req_bits_rs3_data_0[31]; // @[FPU.scala:357:14] wire _sfma_io_in_bits_req_in3_prev_unswizzled_T = io_req_bits_rs3_data_0[31]; // @[FPU.scala:357:14] wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T = io_req_bits_rs3_data_0[31]; // @[FPU.scala:357:14] wire _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = io_req_bits_rs3_data_0[52]; // @[FPU.scala:358:14] wire _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = io_req_bits_rs3_data_0[52]; // @[FPU.scala:358:14] wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = io_req_bits_rs3_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = io_req_bits_rs3_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = io_req_bits_rs3_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = io_req_bits_rs3_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] dfma_io_in_bits_req_in3_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in3_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in3_prev_prev_sign = dfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in3_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in3_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in3_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_expOut_T | _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in3_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in3_floats_0 = {dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in3_prev_isbox_T = io_req_bits_rs3_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _sfma_io_in_bits_req_in3_prev_isbox_T = io_req_bits_rs3_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _fpiu_io_in_bits_req_in3_prev_isbox_T = io_req_bits_rs3_data_0[64:60]; // @[FPU.scala:332:49] wire dfma_io_in_bits_req_in3_prev_isbox = &_dfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in3_oks_0 = dfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in3 = _fp_decoder_io_sigs_swap23 ? dfma_io_in_bits_req_in2 : _dfma_io_in_bits_req_in3_T_1; // @[FPU.scala:372:26] assign _dfma_io_in_bits_req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59] wire [1:0] _sfma_io_in_bits_req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59] wire [1:0] _fpiu_io_in_bits_req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59] assign dfma_io_in_bits_req_typ = _dfma_io_in_bits_req_typ_T; // @[util.scala:295:59] wire _GEN_1 = _fp_decoder_io_sigs_typeTagIn == 2'h0; // @[fpu.scala:182:26, :197:24] wire _dfma_io_in_bits_req_fmt_T; // @[fpu.scala:197:24] assign _dfma_io_in_bits_req_fmt_T = _GEN_1; // @[fpu.scala:197:24] wire _sfma_io_in_bits_req_fmt_T; // @[fpu.scala:197:24] assign _sfma_io_in_bits_req_fmt_T = _GEN_1; // @[fpu.scala:197:24] wire _fpiu_io_in_bits_req_fmt_T; // @[fpu.scala:197:24] assign _fpiu_io_in_bits_req_fmt_T = _GEN_1; // @[fpu.scala:197:24] wire _dfma_io_in_bits_req_fmt_T_1 = ~_dfma_io_in_bits_req_fmt_T; // @[fpu.scala:197:{19,24}] wire _GEN_2 = io_req_bits_uop_uopc_0 == 7'h46; // @[fpu.scala:170:7, :198:27] wire _dfma_io_in_bits_T; // @[fpu.scala:198:27] assign _dfma_io_in_bits_T = _GEN_2; // @[fpu.scala:198:27] wire _sfma_io_in_bits_T; // @[fpu.scala:198:27] assign _sfma_io_in_bits_T = _GEN_2; // @[fpu.scala:198:27] wire _fpiu_io_in_bits_T; // @[fpu.scala:198:27] assign _fpiu_io_in_bits_T = _GEN_2; // @[fpu.scala:198:27] assign dfma_io_in_bits_req_fmt = _dfma_io_in_bits_T ? 2'h0 : {1'h0, _dfma_io_in_bits_req_fmt_T_1}; // @[fpu.scala:188:19, :197:{13,19}, :198:{27,43}, :199:15] wire _sfma_io_in_valid_T_1 = _fp_decoder_io_sigs_typeTagOut == 2'h0; // @[fpu.scala:182:26, :213:74] wire _sfma_io_in_valid_T_2 = _sfma_io_in_valid_T & _sfma_io_in_valid_T_1; // @[fpu.scala:213:{36,51,74}] wire sfma_io_in_bits_req_ldst; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_wen; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_ren1; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_ren2; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_ren3; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_swap12; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_swap23; // @[fpu.scala:188:19] wire [1:0] sfma_io_in_bits_req_typeTagIn; // @[fpu.scala:188:19] wire [1:0] sfma_io_in_bits_req_typeTagOut; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_fromint; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_toint; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_fastpipe; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_fma; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_div; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_sqrt; // @[fpu.scala:188:19] wire sfma_io_in_bits_req_wflags; // @[fpu.scala:188:19] wire [1:0] sfma_io_in_bits_req_fmaCmd; // @[fpu.scala:188:19] wire [1:0] sfma_io_in_bits_req_typ; // @[fpu.scala:188:19] wire [1:0] sfma_io_in_bits_req_fmt; // @[fpu.scala:188:19] wire [64:0] sfma_io_in_bits_req_in1; // @[fpu.scala:188:19] wire [64:0] sfma_io_in_bits_req_in2; // @[fpu.scala:188:19] wire [64:0] sfma_io_in_bits_req_in3; // @[fpu.scala:188:19] wire [1:0] sfma_io_in_bits_req_in1_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in1_floats_0 = {sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in1_prev_isbox = &_sfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in1_oks_0 = sfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in1_sign = io_req_bits_rs1_data_0[64]; // @[FPU.scala:274:17] wire [51:0] sfma_io_in_bits_req_in1_fractIn = io_req_bits_rs1_data_0[51:0]; // @[FPU.scala:275:20] wire [11:0] sfma_io_in_bits_req_in1_expIn = io_req_bits_rs1_data_0[63:52]; // @[FPU.scala:276:18] wire [75:0] _sfma_io_in_bits_req_in1_fractOut_T = {sfma_io_in_bits_req_in1_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in1_fractOut = _sfma_io_in_bits_req_in1_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in1_expOut_expCode = sfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in1_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in1_expOut_commonCase = _sfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in1_expOut_T = sfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in1_expOut_T_1 = sfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in1_expOut_T_2 = _sfma_io_in_bits_req_in1_expOut_T | _sfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in1_expOut_T_3 = sfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_4 = {sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_5 = sfma_io_in_bits_req_in1_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in1_expOut = _sfma_io_in_bits_req_in1_expOut_T_2 ? _sfma_io_in_bits_req_in1_expOut_T_4 : _sfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in1_hi = {sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in1_floats_1 = {sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in1_T = sfma_io_in_bits_req_in1_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in1_T_1 = sfma_io_in_bits_req_in1_floats_0 | _sfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in1 = {32'h0, _sfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:372:26] wire [1:0] sfma_io_in_bits_req_in2_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in2_floats_0 = {sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in2_prev_isbox = &_sfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in2_oks_0 = sfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in2_sign = io_req_bits_rs2_data_0[64]; // @[FPU.scala:274:17] wire [51:0] sfma_io_in_bits_req_in2_fractIn = io_req_bits_rs2_data_0[51:0]; // @[FPU.scala:275:20] wire [11:0] sfma_io_in_bits_req_in2_expIn = io_req_bits_rs2_data_0[63:52]; // @[FPU.scala:276:18] wire [75:0] _sfma_io_in_bits_req_in2_fractOut_T = {sfma_io_in_bits_req_in2_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in2_fractOut = _sfma_io_in_bits_req_in2_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in2_expOut_expCode = sfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in2_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in2_expOut_commonCase = _sfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in2_expOut_T = sfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in2_expOut_T_1 = sfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in2_expOut_T_2 = _sfma_io_in_bits_req_in2_expOut_T | _sfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in2_expOut_T_3 = sfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_4 = {sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_5 = sfma_io_in_bits_req_in2_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in2_expOut = _sfma_io_in_bits_req_in2_expOut_T_2 ? _sfma_io_in_bits_req_in2_expOut_T_4 : _sfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in2_hi = {sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in2_floats_1 = {sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in2_T = sfma_io_in_bits_req_in2_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in2_T_1 = sfma_io_in_bits_req_in2_floats_0 | _sfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in2 = {32'h0, _sfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:372:26] wire [1:0] sfma_io_in_bits_req_in3_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in3_floats_0 = {sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in3_prev_isbox = &_sfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in3_oks_0 = sfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in3_sign = io_req_bits_rs3_data_0[64]; // @[FPU.scala:274:17] wire [51:0] sfma_io_in_bits_req_in3_fractIn = io_req_bits_rs3_data_0[51:0]; // @[FPU.scala:275:20] wire [11:0] sfma_io_in_bits_req_in3_expIn = io_req_bits_rs3_data_0[63:52]; // @[FPU.scala:276:18] wire [75:0] _sfma_io_in_bits_req_in3_fractOut_T = {sfma_io_in_bits_req_in3_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in3_fractOut = _sfma_io_in_bits_req_in3_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in3_expOut_expCode = sfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in3_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in3_expOut_commonCase = _sfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in3_expOut_T = sfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in3_expOut_T_1 = sfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in3_expOut_T_2 = _sfma_io_in_bits_req_in3_expOut_T | _sfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in3_expOut_T_3 = sfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_4 = {sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_5 = sfma_io_in_bits_req_in3_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in3_expOut = _sfma_io_in_bits_req_in3_expOut_T_2 ? _sfma_io_in_bits_req_in3_expOut_T_4 : _sfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in3_hi = {sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in3_floats_1 = {sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in3_T = sfma_io_in_bits_req_in3_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in3_T_1 = sfma_io_in_bits_req_in3_floats_0 | _sfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in3 = _fp_decoder_io_sigs_swap23 ? sfma_io_in_bits_req_in2 : {32'h0, _sfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:372:26] assign sfma_io_in_bits_req_typ = _sfma_io_in_bits_req_typ_T; // @[util.scala:295:59] wire _sfma_io_in_bits_req_fmt_T_1 = ~_sfma_io_in_bits_req_fmt_T; // @[fpu.scala:197:{19,24}] assign sfma_io_in_bits_req_fmt = _sfma_io_in_bits_T ? 2'h0 : {1'h0, _sfma_io_in_bits_req_fmt_T_1}; // @[fpu.scala:188:19, :197:{13,19}, :198:{27,43}, :199:15] wire _fpiu_io_in_valid_T = _fp_decoder_io_sigs_fastpipe & _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26, :217:75] wire _fpiu_io_in_valid_T_1 = _fp_decoder_io_sigs_toint | _fpiu_io_in_valid_T; // @[fpu.scala:182:26, :217:{54,75}] wire _fpiu_io_in_valid_T_2 = io_req_valid_0 & _fpiu_io_in_valid_T_1; // @[fpu.scala:170:7, :217:{36,54}] wire [64:0] _fpiu_io_in_bits_req_in1_T_4; // @[FPU.scala:369:10] wire [64:0] _fpiu_io_in_bits_req_in2_T_4; // @[FPU.scala:369:10] wire fpiu_io_in_bits_req_ldst; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_wen; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_ren1; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_ren2; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_ren3; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_swap12; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_swap23; // @[fpu.scala:188:19] wire [1:0] fpiu_io_in_bits_req_typeTagIn; // @[fpu.scala:188:19] wire [1:0] fpiu_io_in_bits_req_typeTagOut; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_fromint; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_toint; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_fastpipe; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_fma; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_div; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_sqrt; // @[fpu.scala:188:19] wire fpiu_io_in_bits_req_wflags; // @[fpu.scala:188:19] wire [1:0] fpiu_io_in_bits_req_fmaCmd; // @[fpu.scala:188:19] wire [1:0] fpiu_io_in_bits_req_typ; // @[fpu.scala:188:19] wire [1:0] fpiu_io_in_bits_req_fmt; // @[fpu.scala:188:19] wire [64:0] fpiu_io_in_bits_req_in1; // @[fpu.scala:188:19] wire [64:0] fpiu_io_in_bits_req_in2; // @[fpu.scala:188:19] wire [64:0] fpiu_io_in_bits_req_in3; // @[fpu.scala:188:19] wire [1:0] fpiu_io_in_bits_req_in1_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in1_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in1_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in1_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in1_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T | _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in1_floats_0 = {fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in1_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in1_oks_0 = fpiu_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _fpiu_io_in_bits_req_in1_truncIdx_T; // @[package.scala:38:21] wire fpiu_io_in_bits_req_in1_truncIdx = _fpiu_io_in_bits_req_in1_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in1_T = fpiu_io_in_bits_req_in1_truncIdx; // @[package.scala:38:47, :39:86] wire _fpiu_io_in_bits_req_in1_T_1 = _fpiu_io_in_bits_req_in1_T | fpiu_io_in_bits_req_in1_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _fpiu_io_in_bits_req_in1_truncIdx_T_1; // @[package.scala:38:21] wire fpiu_io_in_bits_req_in1_truncIdx_1 = _fpiu_io_in_bits_req_in1_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in1_T_2 = fpiu_io_in_bits_req_in1_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _fpiu_io_in_bits_req_in1_T_3 = _fpiu_io_in_bits_req_in1_T_2 ? io_req_bits_rs1_data_0 : fpiu_io_in_bits_req_in1_floats_0; // @[package.scala:39:{76,86}] assign _fpiu_io_in_bits_req_in1_T_4 = _fpiu_io_in_bits_req_in1_T_1 ? _fpiu_io_in_bits_req_in1_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in1 = _fpiu_io_in_bits_req_in1_T_4; // @[FPU.scala:369:10] wire [1:0] fpiu_io_in_bits_req_in2_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in2_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in2_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in2_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in2_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T | _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in2_floats_0 = {fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in2_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in2_oks_0 = fpiu_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _fpiu_io_in_bits_req_in2_truncIdx_T; // @[package.scala:38:21] wire fpiu_io_in_bits_req_in2_truncIdx = _fpiu_io_in_bits_req_in2_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in2_T = fpiu_io_in_bits_req_in2_truncIdx; // @[package.scala:38:47, :39:86] wire _fpiu_io_in_bits_req_in2_T_1 = _fpiu_io_in_bits_req_in2_T | fpiu_io_in_bits_req_in2_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _fpiu_io_in_bits_req_in2_truncIdx_T_1; // @[package.scala:38:21] wire fpiu_io_in_bits_req_in2_truncIdx_1 = _fpiu_io_in_bits_req_in2_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in2_T_2 = fpiu_io_in_bits_req_in2_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _fpiu_io_in_bits_req_in2_T_3 = _fpiu_io_in_bits_req_in2_T_2 ? io_req_bits_rs2_data_0 : fpiu_io_in_bits_req_in2_floats_0; // @[package.scala:39:{76,86}] assign _fpiu_io_in_bits_req_in2_T_4 = _fpiu_io_in_bits_req_in2_T_1 ? _fpiu_io_in_bits_req_in2_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in2 = _fpiu_io_in_bits_req_in2_T_4; // @[FPU.scala:369:10] wire [1:0] fpiu_io_in_bits_req_in3_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in3_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in3_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in3_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in3_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T | _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in3_floats_0 = {fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in3_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in3_oks_0 = fpiu_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _fpiu_io_in_bits_req_in3_truncIdx_T; // @[package.scala:38:21] wire fpiu_io_in_bits_req_in3_truncIdx = _fpiu_io_in_bits_req_in3_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in3_T = fpiu_io_in_bits_req_in3_truncIdx; // @[package.scala:38:47, :39:86] wire _fpiu_io_in_bits_req_in3_T_1 = _fpiu_io_in_bits_req_in3_T | fpiu_io_in_bits_req_in3_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _fpiu_io_in_bits_req_in3_truncIdx_T_1; // @[package.scala:38:21] wire fpiu_io_in_bits_req_in3_truncIdx_1 = _fpiu_io_in_bits_req_in3_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in3_T_2 = fpiu_io_in_bits_req_in3_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _fpiu_io_in_bits_req_in3_T_3 = _fpiu_io_in_bits_req_in3_T_2 ? io_req_bits_rs3_data_0 : fpiu_io_in_bits_req_in3_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in3_T_4 = _fpiu_io_in_bits_req_in3_T_1 ? _fpiu_io_in_bits_req_in3_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in3 = _fp_decoder_io_sigs_swap23 ? fpiu_io_in_bits_req_in2 : _fpiu_io_in_bits_req_in3_T_4; // @[FPU.scala:369:10] assign fpiu_io_in_bits_req_typ = _fpiu_io_in_bits_req_typ_T; // @[util.scala:295:59] wire _fpiu_io_in_bits_req_fmt_T_1 = ~_fpiu_io_in_bits_req_fmt_T; // @[fpu.scala:197:{19,24}] assign fpiu_io_in_bits_req_fmt = _fpiu_io_in_bits_T ? 2'h0 : {1'h0, _fpiu_io_in_bits_req_fmt_T_1}; // @[fpu.scala:188:19, :197:{13,19}, :198:{27,43}, :199:15] wire _fpiu_out_T = ~_fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26, :219:51] wire _fpiu_out_T_1 = _fpiu_io_in_valid_T_2 & _fpiu_out_T; // @[fpu.scala:217:36, :219:{48,51}] reg fpiu_out_REG; // @[fpu.scala:219:30] reg fpiu_out_pipe_v; // @[Valid.scala:141:24] reg fpiu_out_pipe_b_in_ldst; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_wen; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_ren1; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_ren2; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_ren3; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_swap12; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_swap23; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_fromint; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_toint; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_fastpipe; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_fma; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_div; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_sqrt; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_wflags; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_vec; // @[Valid.scala:142:26] reg [2:0] fpiu_out_pipe_b_in_rm; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_typ; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_fmt; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_b_in_in1; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_b_in_in2; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_b_in_in3; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_lt; // @[Valid.scala:142:26] reg [63:0] fpiu_out_pipe_b_store; // @[Valid.scala:142:26] reg [63:0] fpiu_out_pipe_b_toint; // @[Valid.scala:142:26] reg [4:0] fpiu_out_pipe_b_exc; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_v; // @[Valid.scala:141:24] reg fpiu_out_pipe_pipe_b_in_ldst; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_wen; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_ren1; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_ren2; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_ren3; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_swap12; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_swap23; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_fromint; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_toint; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_fastpipe; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_fma; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_div; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_sqrt; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_wflags; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_vec; // @[Valid.scala:142:26] reg [2:0] fpiu_out_pipe_pipe_b_in_rm; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_typ; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_fmt; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_pipe_b_in_in1; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_pipe_b_in_in2; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_pipe_b_in_in3; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_lt; // @[Valid.scala:142:26] reg [63:0] fpiu_out_pipe_pipe_b_store; // @[Valid.scala:142:26] reg [63:0] fpiu_out_pipe_pipe_b_toint; // @[Valid.scala:142:26] reg [4:0] fpiu_out_pipe_pipe_b_exc; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_pipe_v; // @[Valid.scala:141:24] wire fpiu_out_valid = fpiu_out_pipe_pipe_pipe_v; // @[Valid.scala:135:21, :141:24] reg fpiu_out_pipe_pipe_pipe_b_in_ldst; // @[Valid.scala:142:26] wire fpiu_out_bits_in_ldst = fpiu_out_pipe_pipe_pipe_b_in_ldst; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_wen; // @[Valid.scala:142:26] wire fpiu_out_bits_in_wen = fpiu_out_pipe_pipe_pipe_b_in_wen; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_ren1; // @[Valid.scala:142:26] wire fpiu_out_bits_in_ren1 = fpiu_out_pipe_pipe_pipe_b_in_ren1; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_ren2; // @[Valid.scala:142:26] wire fpiu_out_bits_in_ren2 = fpiu_out_pipe_pipe_pipe_b_in_ren2; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_ren3; // @[Valid.scala:142:26] wire fpiu_out_bits_in_ren3 = fpiu_out_pipe_pipe_pipe_b_in_ren3; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_swap12; // @[Valid.scala:142:26] wire fpiu_out_bits_in_swap12 = fpiu_out_pipe_pipe_pipe_b_in_swap12; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_swap23; // @[Valid.scala:142:26] wire fpiu_out_bits_in_swap23 = fpiu_out_pipe_pipe_pipe_b_in_swap23; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_typeTagIn = fpiu_out_pipe_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_typeTagOut = fpiu_out_pipe_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_fromint; // @[Valid.scala:142:26] wire fpiu_out_bits_in_fromint = fpiu_out_pipe_pipe_pipe_b_in_fromint; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_toint; // @[Valid.scala:142:26] wire fpiu_out_bits_in_toint = fpiu_out_pipe_pipe_pipe_b_in_toint; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_fastpipe; // @[Valid.scala:142:26] wire fpiu_out_bits_in_fastpipe = fpiu_out_pipe_pipe_pipe_b_in_fastpipe; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_fma; // @[Valid.scala:142:26] wire fpiu_out_bits_in_fma = fpiu_out_pipe_pipe_pipe_b_in_fma; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_div; // @[Valid.scala:142:26] wire fpiu_out_bits_in_div = fpiu_out_pipe_pipe_pipe_b_in_div; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_sqrt; // @[Valid.scala:142:26] wire fpiu_out_bits_in_sqrt = fpiu_out_pipe_pipe_pipe_b_in_sqrt; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_wflags; // @[Valid.scala:142:26] wire fpiu_out_bits_in_wflags = fpiu_out_pipe_pipe_pipe_b_in_wflags; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_vec; // @[Valid.scala:142:26] wire fpiu_out_bits_in_vec = fpiu_out_pipe_pipe_pipe_b_in_vec; // @[Valid.scala:135:21, :142:26] reg [2:0] fpiu_out_pipe_pipe_pipe_b_in_rm; // @[Valid.scala:142:26] wire [2:0] fpiu_out_bits_in_rm = fpiu_out_pipe_pipe_pipe_b_in_rm; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_fmaCmd = fpiu_out_pipe_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_typ; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_typ = fpiu_out_pipe_pipe_pipe_b_in_typ; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_fmt; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_fmt = fpiu_out_pipe_pipe_pipe_b_in_fmt; // @[Valid.scala:135:21, :142:26] reg [64:0] fpiu_out_pipe_pipe_pipe_b_in_in1; // @[Valid.scala:142:26] wire [64:0] fpiu_out_bits_in_in1 = fpiu_out_pipe_pipe_pipe_b_in_in1; // @[Valid.scala:135:21, :142:26] reg [64:0] fpiu_out_pipe_pipe_pipe_b_in_in2; // @[Valid.scala:142:26] wire [64:0] fpiu_out_bits_in_in2 = fpiu_out_pipe_pipe_pipe_b_in_in2; // @[Valid.scala:135:21, :142:26] reg [64:0] fpiu_out_pipe_pipe_pipe_b_in_in3; // @[Valid.scala:142:26] wire [64:0] fpiu_out_bits_in_in3 = fpiu_out_pipe_pipe_pipe_b_in_in3; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_lt; // @[Valid.scala:142:26] wire fpiu_out_bits_lt = fpiu_out_pipe_pipe_pipe_b_lt; // @[Valid.scala:135:21, :142:26] reg [63:0] fpiu_out_pipe_pipe_pipe_b_store; // @[Valid.scala:142:26] wire [63:0] fpiu_out_bits_store = fpiu_out_pipe_pipe_pipe_b_store; // @[Valid.scala:135:21, :142:26] reg [63:0] fpiu_out_pipe_pipe_pipe_b_toint; // @[Valid.scala:142:26] wire [63:0] fpiu_out_bits_toint = fpiu_out_pipe_pipe_pipe_b_toint; // @[Valid.scala:135:21, :142:26] reg [4:0] fpiu_out_pipe_pipe_pipe_b_exc; // @[Valid.scala:142:26] wire [4:0] fpiu_out_bits_exc = fpiu_out_pipe_pipe_pipe_b_exc; // @[Valid.scala:135:21, :142:26] wire [4:0] fpiu_result_exc = fpiu_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] fpiu_result_data; // @[fpu.scala:221:26] assign fpiu_result_data = {1'h0, fpiu_out_bits_toint}; // @[Valid.scala:135:21] wire _GEN_3 = io_req_valid_0 & _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:170:7, :182:26, :226:36] wire _fpmu_io_in_valid_T; // @[fpu.scala:226:36] assign _fpmu_io_in_valid_T = _GEN_3; // @[fpu.scala:226:36] wire _fpmu_double_T; // @[fpu.scala:229:39] assign _fpmu_double_T = _GEN_3; // @[fpu.scala:226:36, :229:39] reg fpmu_double_pipe_v; // @[Valid.scala:141:24] reg fpmu_double_pipe_b; // @[Valid.scala:142:26] reg fpmu_double_pipe_pipe_v; // @[Valid.scala:141:24] reg fpmu_double_pipe_pipe_b; // @[Valid.scala:142:26] reg fpmu_double_pipe_pipe_pipe_v; // @[Valid.scala:141:24] reg fpmu_double_pipe_pipe_pipe_b; // @[Valid.scala:142:26] reg fpmu_double_pipe_pipe_pipe_pipe_v; // @[Valid.scala:141:24] wire fpmu_double_pipe_pipe_pipe_pipe_out_valid = fpmu_double_pipe_pipe_pipe_pipe_v; // @[Valid.scala:135:21, :141:24] reg fpmu_double_pipe_pipe_pipe_pipe_b; // @[Valid.scala:142:26] wire fpmu_double_pipe_pipe_pipe_pipe_out_bits = fpmu_double_pipe_pipe_pipe_pipe_b; // @[Valid.scala:135:21, :142:26] wire _fpu_out_data_T_4 = fpmu_double_pipe_pipe_pipe_pipe_out_bits; // @[Valid.scala:135:21] wire _io_resp_valid_T = fpiu_out_valid | _fpmu_io_out_valid; // @[Valid.scala:135:21] wire _io_resp_valid_T_1 = _io_resp_valid_T | _sfma_io_out_valid; // @[fpu.scala:212:20, :232:35, :233:38] assign _io_resp_valid_T_2 = _io_resp_valid_T_1 | _dfma_io_out_valid; // @[fpu.scala:208:20, :233:38, :234:38] assign io_resp_valid = _io_resp_valid_T_2; // @[fpu.scala:170:7, :234:38] wire _fpu_out_data_opts_bigger_swizzledNaN_T_1 = _dfma_io_out_bits_data[31]; // @[FPU.scala:340:8] wire _fpu_out_data_opts_bigger_swizzledNaN_T_2 = _dfma_io_out_bits_data[32]; // @[FPU.scala:342:8] wire [30:0] _fpu_out_data_opts_bigger_swizzledNaN_T_3 = _dfma_io_out_bits_data[30:0]; // @[FPU.scala:343:8] wire [20:0] fpu_out_data_opts_bigger_swizzledNaN_lo_hi = {20'hFFFFF, _fpu_out_data_opts_bigger_swizzledNaN_T_2}; // @[FPU.scala:336:26, :342:8] wire [51:0] fpu_out_data_opts_bigger_swizzledNaN_lo = {fpu_out_data_opts_bigger_swizzledNaN_lo_hi, _fpu_out_data_opts_bigger_swizzledNaN_T_3}; // @[FPU.scala:336:26, :343:8] wire [7:0] fpu_out_data_opts_bigger_swizzledNaN_hi_lo = {7'h7F, _fpu_out_data_opts_bigger_swizzledNaN_T_1}; // @[FPU.scala:336:26, :340:8] wire [12:0] fpu_out_data_opts_bigger_swizzledNaN_hi = {5'h1F, fpu_out_data_opts_bigger_swizzledNaN_hi_lo}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_swizzledNaN = {fpu_out_data_opts_bigger_swizzledNaN_hi, fpu_out_data_opts_bigger_swizzledNaN_lo}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger = fpu_out_data_opts_bigger_swizzledNaN; // @[FPU.scala:336:26, :344:8] wire [64:0] fpu_out_data_opts_0 = fpu_out_data_opts_bigger; // @[FPU.scala:344:8, :398:14] wire _fpu_out_data_opts_bigger_swizzledNaN_T_5 = _sfma_io_out_bits_data[31]; // @[FPU.scala:340:8] wire _fpu_out_data_opts_bigger_swizzledNaN_T_6 = _sfma_io_out_bits_data[32]; // @[FPU.scala:342:8] wire [30:0] _fpu_out_data_opts_bigger_swizzledNaN_T_7 = _sfma_io_out_bits_data[30:0]; // @[FPU.scala:343:8] wire [20:0] fpu_out_data_opts_bigger_swizzledNaN_lo_hi_1 = {20'hFFFFF, _fpu_out_data_opts_bigger_swizzledNaN_T_6}; // @[FPU.scala:336:26, :342:8] wire [51:0] fpu_out_data_opts_bigger_swizzledNaN_lo_1 = {fpu_out_data_opts_bigger_swizzledNaN_lo_hi_1, _fpu_out_data_opts_bigger_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8] wire [7:0] fpu_out_data_opts_bigger_swizzledNaN_hi_lo_1 = {7'h7F, _fpu_out_data_opts_bigger_swizzledNaN_T_5}; // @[FPU.scala:336:26, :340:8] wire [12:0] fpu_out_data_opts_bigger_swizzledNaN_hi_1 = {5'h1F, fpu_out_data_opts_bigger_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_swizzledNaN_1 = {fpu_out_data_opts_bigger_swizzledNaN_hi_1, fpu_out_data_opts_bigger_swizzledNaN_lo_1}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_1 = fpu_out_data_opts_bigger_swizzledNaN_1; // @[FPU.scala:336:26, :344:8] wire [64:0] fpu_out_data_opts_0_1 = fpu_out_data_opts_bigger_1; // @[FPU.scala:344:8, :398:14] wire [64:0] _fpu_out_data_T_3 = fpu_out_data_opts_0_1; // @[package.scala:39:76] wire _fpu_out_data_opts_bigger_swizzledNaN_T_9 = _fpmu_io_out_bits_data[31]; // @[FPU.scala:340:8] wire _fpu_out_data_opts_bigger_swizzledNaN_T_10 = _fpmu_io_out_bits_data[32]; // @[FPU.scala:342:8] wire [30:0] _fpu_out_data_opts_bigger_swizzledNaN_T_11 = _fpmu_io_out_bits_data[30:0]; // @[FPU.scala:343:8] wire [20:0] fpu_out_data_opts_bigger_swizzledNaN_lo_hi_2 = {20'hFFFFF, _fpu_out_data_opts_bigger_swizzledNaN_T_10}; // @[FPU.scala:336:26, :342:8] wire [51:0] fpu_out_data_opts_bigger_swizzledNaN_lo_2 = {fpu_out_data_opts_bigger_swizzledNaN_lo_hi_2, _fpu_out_data_opts_bigger_swizzledNaN_T_11}; // @[FPU.scala:336:26, :343:8] wire [7:0] fpu_out_data_opts_bigger_swizzledNaN_hi_lo_2 = {7'h7F, _fpu_out_data_opts_bigger_swizzledNaN_T_9}; // @[FPU.scala:336:26, :340:8] wire [12:0] fpu_out_data_opts_bigger_swizzledNaN_hi_2 = {5'h1F, fpu_out_data_opts_bigger_swizzledNaN_hi_lo_2}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_swizzledNaN_2 = {fpu_out_data_opts_bigger_swizzledNaN_hi_2, fpu_out_data_opts_bigger_swizzledNaN_lo_2}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_2 = fpu_out_data_opts_bigger_swizzledNaN_2; // @[FPU.scala:336:26, :344:8] wire [64:0] fpu_out_data_opts_0_2 = fpu_out_data_opts_bigger_2; // @[FPU.scala:344:8, :398:14] wire [64:0] _fpu_out_data_T_5 = _fpu_out_data_T_4 ? _fpmu_io_out_bits_data : fpu_out_data_opts_0_2; // @[package.scala:39:{76,86}] wire [64:0] _fpu_out_data_T_6 = fpiu_out_valid ? fpiu_result_data : _fpu_out_data_T_5; // @[Valid.scala:135:21] wire [64:0] _fpu_out_data_T_7 = _sfma_io_out_valid ? _fpu_out_data_T_3 : _fpu_out_data_T_6; // @[package.scala:39:76] wire [64:0] _fpu_out_data_T_1; // @[package.scala:39:76] assign fpu_out_data = _dfma_io_out_valid ? _fpu_out_data_T_1 : _fpu_out_data_T_7; // @[package.scala:39:76] assign io_resp_bits_data_0 = fpu_out_data; // @[fpu.scala:170:7, :237:8] wire [4:0] _fpu_out_exc_T = fpiu_out_valid ? fpiu_result_exc : _fpmu_io_out_bits_exc; // @[Valid.scala:135:21] wire [4:0] _fpu_out_exc_T_1 = _sfma_io_out_valid ? _sfma_io_out_bits_exc : _fpu_out_exc_T; // @[fpu.scala:212:20, :244:8, :245:8] assign fpu_out_exc = _dfma_io_out_valid ? _dfma_io_out_bits_exc : _fpu_out_exc_T_1; // @[fpu.scala:208:20, :243:8, :244:8] assign io_resp_bits_fflags_bits_flags_0 = fpu_out_exc; // @[fpu.scala:170:7, :243:8] always @(posedge clock) begin // @[fpu.scala:170:7] fpiu_out_REG <= _fpiu_out_T_1; // @[fpu.scala:219:{30,48}] if (fpiu_out_REG) begin // @[fpu.scala:219:30] fpiu_out_pipe_b_in_ldst <= _fpiu_io_out_bits_in_ldst; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_wen <= _fpiu_io_out_bits_in_wen; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_ren1 <= _fpiu_io_out_bits_in_ren1; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_ren2 <= _fpiu_io_out_bits_in_ren2; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_ren3 <= _fpiu_io_out_bits_in_ren3; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_swap12 <= _fpiu_io_out_bits_in_swap12; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_swap23 <= _fpiu_io_out_bits_in_swap23; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_typeTagIn <= _fpiu_io_out_bits_in_typeTagIn; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_typeTagOut <= _fpiu_io_out_bits_in_typeTagOut; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fromint <= _fpiu_io_out_bits_in_fromint; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_toint <= _fpiu_io_out_bits_in_toint; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fastpipe <= _fpiu_io_out_bits_in_fastpipe; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fma <= _fpiu_io_out_bits_in_fma; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_div <= _fpiu_io_out_bits_in_div; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_sqrt <= _fpiu_io_out_bits_in_sqrt; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_wflags <= _fpiu_io_out_bits_in_wflags; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_rm <= _fpiu_io_out_bits_in_rm; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fmaCmd <= _fpiu_io_out_bits_in_fmaCmd; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_typ <= _fpiu_io_out_bits_in_typ; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fmt <= _fpiu_io_out_bits_in_fmt; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_in1 <= _fpiu_io_out_bits_in_in1; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_in2 <= _fpiu_io_out_bits_in_in2; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_in3 <= _fpiu_io_out_bits_in_in3; // @[Valid.scala:142:26] fpiu_out_pipe_b_lt <= _fpiu_io_out_bits_lt; // @[Valid.scala:142:26] fpiu_out_pipe_b_store <= _fpiu_io_out_bits_store; // @[Valid.scala:142:26] fpiu_out_pipe_b_toint <= _fpiu_io_out_bits_toint; // @[Valid.scala:142:26] fpiu_out_pipe_b_exc <= _fpiu_io_out_bits_exc; // @[Valid.scala:142:26] end fpiu_out_pipe_b_in_vec <= ~fpiu_out_REG & fpiu_out_pipe_b_in_vec; // @[Valid.scala:142:26] if (fpiu_out_pipe_v) begin // @[Valid.scala:141:24] fpiu_out_pipe_pipe_b_in_ldst <= fpiu_out_pipe_b_in_ldst; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_wen <= fpiu_out_pipe_b_in_wen; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_ren1 <= fpiu_out_pipe_b_in_ren1; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_ren2 <= fpiu_out_pipe_b_in_ren2; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_ren3 <= fpiu_out_pipe_b_in_ren3; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_swap12 <= fpiu_out_pipe_b_in_swap12; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_swap23 <= fpiu_out_pipe_b_in_swap23; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_typeTagIn <= fpiu_out_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_typeTagOut <= fpiu_out_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fromint <= fpiu_out_pipe_b_in_fromint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_toint <= fpiu_out_pipe_b_in_toint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fastpipe <= fpiu_out_pipe_b_in_fastpipe; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fma <= fpiu_out_pipe_b_in_fma; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_div <= fpiu_out_pipe_b_in_div; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_sqrt <= fpiu_out_pipe_b_in_sqrt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_wflags <= fpiu_out_pipe_b_in_wflags; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_vec <= fpiu_out_pipe_b_in_vec; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_rm <= fpiu_out_pipe_b_in_rm; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fmaCmd <= fpiu_out_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_typ <= fpiu_out_pipe_b_in_typ; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fmt <= fpiu_out_pipe_b_in_fmt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_in1 <= fpiu_out_pipe_b_in_in1; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_in2 <= fpiu_out_pipe_b_in_in2; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_in3 <= fpiu_out_pipe_b_in_in3; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_lt <= fpiu_out_pipe_b_lt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_store <= fpiu_out_pipe_b_store; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_toint <= fpiu_out_pipe_b_toint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_exc <= fpiu_out_pipe_b_exc; // @[Valid.scala:142:26] end if (fpiu_out_pipe_pipe_v) begin // @[Valid.scala:141:24] fpiu_out_pipe_pipe_pipe_b_in_ldst <= fpiu_out_pipe_pipe_b_in_ldst; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_wen <= fpiu_out_pipe_pipe_b_in_wen; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_ren1 <= fpiu_out_pipe_pipe_b_in_ren1; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_ren2 <= fpiu_out_pipe_pipe_b_in_ren2; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_ren3 <= fpiu_out_pipe_pipe_b_in_ren3; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_swap12 <= fpiu_out_pipe_pipe_b_in_swap12; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_swap23 <= fpiu_out_pipe_pipe_b_in_swap23; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_typeTagIn <= fpiu_out_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_typeTagOut <= fpiu_out_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fromint <= fpiu_out_pipe_pipe_b_in_fromint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_toint <= fpiu_out_pipe_pipe_b_in_toint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fastpipe <= fpiu_out_pipe_pipe_b_in_fastpipe; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fma <= fpiu_out_pipe_pipe_b_in_fma; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_div <= fpiu_out_pipe_pipe_b_in_div; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_sqrt <= fpiu_out_pipe_pipe_b_in_sqrt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_wflags <= fpiu_out_pipe_pipe_b_in_wflags; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_vec <= fpiu_out_pipe_pipe_b_in_vec; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_rm <= fpiu_out_pipe_pipe_b_in_rm; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fmaCmd <= fpiu_out_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_typ <= fpiu_out_pipe_pipe_b_in_typ; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fmt <= fpiu_out_pipe_pipe_b_in_fmt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_in1 <= fpiu_out_pipe_pipe_b_in_in1; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_in2 <= fpiu_out_pipe_pipe_b_in_in2; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_in3 <= fpiu_out_pipe_pipe_b_in_in3; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_lt <= fpiu_out_pipe_pipe_b_lt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_store <= fpiu_out_pipe_pipe_b_store; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_toint <= fpiu_out_pipe_pipe_b_toint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_exc <= fpiu_out_pipe_pipe_b_exc; // @[Valid.scala:142:26] end if (_fpmu_double_T) // @[fpu.scala:229:39] fpmu_double_pipe_b <= _fpmu_double_T_1; // @[Valid.scala:142:26] if (fpmu_double_pipe_v) // @[Valid.scala:141:24] fpmu_double_pipe_pipe_b <= fpmu_double_pipe_b; // @[Valid.scala:142:26] if (fpmu_double_pipe_pipe_v) // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_b <= fpmu_double_pipe_pipe_b; // @[Valid.scala:142:26] if (fpmu_double_pipe_pipe_pipe_v) // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_pipe_b <= fpmu_double_pipe_pipe_pipe_b; // @[Valid.scala:142:26] if (reset) begin // @[fpu.scala:170:7] fpiu_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpiu_out_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpiu_out_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpmu_double_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[fpu.scala:170:7] fpiu_out_pipe_v <= fpiu_out_REG; // @[Valid.scala:141:24] fpiu_out_pipe_pipe_v <= fpiu_out_pipe_v; // @[Valid.scala:141:24] fpiu_out_pipe_pipe_pipe_v <= fpiu_out_pipe_pipe_v; // @[Valid.scala:141:24] fpmu_double_pipe_v <= _fpmu_double_T; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_v <= fpmu_double_pipe_v; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_v <= fpmu_double_pipe_pipe_v; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_pipe_v <= fpmu_double_pipe_pipe_pipe_v; // @[Valid.scala:141:24] end always @(posedge) UOPCodeFPUDecoder_1 fp_decoder ( // @[fpu.scala:182:26] .clock (clock), .reset (reset), .io_uopc (io_req_bits_uop_uopc_0), // @[fpu.scala:170:7] .io_sigs_ldst (_fp_decoder_io_sigs_ldst), .io_sigs_wen (_fp_decoder_io_sigs_wen), .io_sigs_ren1 (_fp_decoder_io_sigs_ren1), .io_sigs_ren2 (_fp_decoder_io_sigs_ren2), .io_sigs_ren3 (_fp_decoder_io_sigs_ren3), .io_sigs_swap12 (_fp_decoder_io_sigs_swap12), .io_sigs_swap23 (_fp_decoder_io_sigs_swap23), .io_sigs_typeTagIn (_fp_decoder_io_sigs_typeTagIn), .io_sigs_typeTagOut (_fp_decoder_io_sigs_typeTagOut), .io_sigs_fromint (_fp_decoder_io_sigs_fromint), .io_sigs_toint (_fp_decoder_io_sigs_toint), .io_sigs_fastpipe (_fp_decoder_io_sigs_fastpipe), .io_sigs_fma (_fp_decoder_io_sigs_fma), .io_sigs_div (_fp_decoder_io_sigs_div), .io_sigs_sqrt (_fp_decoder_io_sigs_sqrt), .io_sigs_wflags (_fp_decoder_io_sigs_wflags) ); // @[fpu.scala:182:26] assign dfma_io_in_bits_req_ldst = _fp_decoder_io_sigs_ldst; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_wen = _fp_decoder_io_sigs_wen; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_ren1 = _fp_decoder_io_sigs_ren1; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_ren2 = _fp_decoder_io_sigs_ren2; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_ren3 = _fp_decoder_io_sigs_ren3; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_swap12 = _fp_decoder_io_sigs_swap12; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_swap23 = _fp_decoder_io_sigs_swap23; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_typeTagIn = _fp_decoder_io_sigs_typeTagIn; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_typeTagOut = _fp_decoder_io_sigs_typeTagOut; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_fromint = _fp_decoder_io_sigs_fromint; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_toint = _fp_decoder_io_sigs_toint; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_fastpipe = _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_fma = _fp_decoder_io_sigs_fma; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_div = _fp_decoder_io_sigs_div; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_sqrt = _fp_decoder_io_sigs_sqrt; // @[fpu.scala:182:26, :188:19] assign dfma_io_in_bits_req_wflags = _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_ldst = _fp_decoder_io_sigs_ldst; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_wen = _fp_decoder_io_sigs_wen; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_ren1 = _fp_decoder_io_sigs_ren1; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_ren2 = _fp_decoder_io_sigs_ren2; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_ren3 = _fp_decoder_io_sigs_ren3; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_swap12 = _fp_decoder_io_sigs_swap12; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_swap23 = _fp_decoder_io_sigs_swap23; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_typeTagIn = _fp_decoder_io_sigs_typeTagIn; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_typeTagOut = _fp_decoder_io_sigs_typeTagOut; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_fromint = _fp_decoder_io_sigs_fromint; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_toint = _fp_decoder_io_sigs_toint; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_fastpipe = _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_fma = _fp_decoder_io_sigs_fma; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_div = _fp_decoder_io_sigs_div; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_sqrt = _fp_decoder_io_sigs_sqrt; // @[fpu.scala:182:26, :188:19] assign sfma_io_in_bits_req_wflags = _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_ldst = _fp_decoder_io_sigs_ldst; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_wen = _fp_decoder_io_sigs_wen; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_ren1 = _fp_decoder_io_sigs_ren1; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_ren2 = _fp_decoder_io_sigs_ren2; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_ren3 = _fp_decoder_io_sigs_ren3; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_swap12 = _fp_decoder_io_sigs_swap12; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_swap23 = _fp_decoder_io_sigs_swap23; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_typeTagIn = _fp_decoder_io_sigs_typeTagIn; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_typeTagOut = _fp_decoder_io_sigs_typeTagOut; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_fromint = _fp_decoder_io_sigs_fromint; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_toint = _fp_decoder_io_sigs_toint; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_fastpipe = _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_fma = _fp_decoder_io_sigs_fma; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_div = _fp_decoder_io_sigs_div; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_sqrt = _fp_decoder_io_sigs_sqrt; // @[fpu.scala:182:26, :188:19] assign fpiu_io_in_bits_req_wflags = _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26, :188:19] assign _fpiu_io_in_bits_req_in1_truncIdx_T = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21] assign _fpiu_io_in_bits_req_in1_truncIdx_T_1 = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21] assign _fpiu_io_in_bits_req_in2_truncIdx_T = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21] assign _fpiu_io_in_bits_req_in2_truncIdx_T_1 = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21] assign _fpiu_io_in_bits_req_in3_truncIdx_T = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21] assign _fpiu_io_in_bits_req_in3_truncIdx_T_1 = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21] FPUFMAPipe_l4_f64 dfma ( // @[fpu.scala:208:20] .clock (clock), .reset (reset), .io_in_valid (_dfma_io_in_valid_T_2), // @[fpu.scala:209:51] .io_in_bits_ldst (dfma_io_in_bits_req_ldst), // @[fpu.scala:188:19] .io_in_bits_wen (dfma_io_in_bits_req_wen), // @[fpu.scala:188:19] .io_in_bits_ren1 (dfma_io_in_bits_req_ren1), // @[fpu.scala:188:19] .io_in_bits_ren2 (dfma_io_in_bits_req_ren2), // @[fpu.scala:188:19] .io_in_bits_ren3 (dfma_io_in_bits_req_ren3), // @[fpu.scala:188:19] .io_in_bits_swap12 (dfma_io_in_bits_req_swap12), // @[fpu.scala:188:19] .io_in_bits_swap23 (dfma_io_in_bits_req_swap23), // @[fpu.scala:188:19] .io_in_bits_typeTagIn (dfma_io_in_bits_req_typeTagIn), // @[fpu.scala:188:19] .io_in_bits_typeTagOut (dfma_io_in_bits_req_typeTagOut), // @[fpu.scala:188:19] .io_in_bits_fromint (dfma_io_in_bits_req_fromint), // @[fpu.scala:188:19] .io_in_bits_toint (dfma_io_in_bits_req_toint), // @[fpu.scala:188:19] .io_in_bits_fastpipe (dfma_io_in_bits_req_fastpipe), // @[fpu.scala:188:19] .io_in_bits_fma (dfma_io_in_bits_req_fma), // @[fpu.scala:188:19] .io_in_bits_div (dfma_io_in_bits_req_div), // @[fpu.scala:188:19] .io_in_bits_sqrt (dfma_io_in_bits_req_sqrt), // @[fpu.scala:188:19] .io_in_bits_wflags (dfma_io_in_bits_req_wflags), // @[fpu.scala:188:19] .io_in_bits_rm (dfma_io_in_bits_req_rm), // @[fpu.scala:188:19] .io_in_bits_fmaCmd (dfma_io_in_bits_req_fmaCmd), // @[fpu.scala:188:19] .io_in_bits_typ (dfma_io_in_bits_req_typ), // @[fpu.scala:188:19] .io_in_bits_fmt (dfma_io_in_bits_req_fmt), // @[fpu.scala:188:19] .io_in_bits_in1 (dfma_io_in_bits_req_in1), // @[fpu.scala:188:19] .io_in_bits_in2 (dfma_io_in_bits_req_in2), // @[fpu.scala:188:19] .io_in_bits_in3 (dfma_io_in_bits_req_in3), // @[fpu.scala:188:19] .io_out_valid (_dfma_io_out_valid), .io_out_bits_data (_dfma_io_out_bits_data), .io_out_bits_exc (_dfma_io_out_bits_exc) ); // @[fpu.scala:208:20] assign _fpu_out_data_T_1 = _dfma_io_out_bits_data; // @[package.scala:39:76] FMADecoder dfma_io_in_bits_fma_decoder ( // @[fpu.scala:202:29] .clock (clock), .reset (reset), .io_uopc (io_req_bits_uop_uopc_0), // @[fpu.scala:170:7] .io_cmd (dfma_io_in_bits_req_fmaCmd) ); // @[fpu.scala:202:29] FPUFMAPipe_l4_f32 sfma ( // @[fpu.scala:212:20] .clock (clock), .reset (reset), .io_in_valid (_sfma_io_in_valid_T_2), // @[fpu.scala:213:51] .io_in_bits_ldst (sfma_io_in_bits_req_ldst), // @[fpu.scala:188:19] .io_in_bits_wen (sfma_io_in_bits_req_wen), // @[fpu.scala:188:19] .io_in_bits_ren1 (sfma_io_in_bits_req_ren1), // @[fpu.scala:188:19] .io_in_bits_ren2 (sfma_io_in_bits_req_ren2), // @[fpu.scala:188:19] .io_in_bits_ren3 (sfma_io_in_bits_req_ren3), // @[fpu.scala:188:19] .io_in_bits_swap12 (sfma_io_in_bits_req_swap12), // @[fpu.scala:188:19] .io_in_bits_swap23 (sfma_io_in_bits_req_swap23), // @[fpu.scala:188:19] .io_in_bits_typeTagIn (sfma_io_in_bits_req_typeTagIn), // @[fpu.scala:188:19] .io_in_bits_typeTagOut (sfma_io_in_bits_req_typeTagOut), // @[fpu.scala:188:19] .io_in_bits_fromint (sfma_io_in_bits_req_fromint), // @[fpu.scala:188:19] .io_in_bits_toint (sfma_io_in_bits_req_toint), // @[fpu.scala:188:19] .io_in_bits_fastpipe (sfma_io_in_bits_req_fastpipe), // @[fpu.scala:188:19] .io_in_bits_fma (sfma_io_in_bits_req_fma), // @[fpu.scala:188:19] .io_in_bits_div (sfma_io_in_bits_req_div), // @[fpu.scala:188:19] .io_in_bits_sqrt (sfma_io_in_bits_req_sqrt), // @[fpu.scala:188:19] .io_in_bits_wflags (sfma_io_in_bits_req_wflags), // @[fpu.scala:188:19] .io_in_bits_rm (sfma_io_in_bits_req_rm), // @[fpu.scala:188:19] .io_in_bits_fmaCmd (sfma_io_in_bits_req_fmaCmd), // @[fpu.scala:188:19] .io_in_bits_typ (sfma_io_in_bits_req_typ), // @[fpu.scala:188:19] .io_in_bits_fmt (sfma_io_in_bits_req_fmt), // @[fpu.scala:188:19] .io_in_bits_in1 (sfma_io_in_bits_req_in1), // @[fpu.scala:188:19] .io_in_bits_in2 (sfma_io_in_bits_req_in2), // @[fpu.scala:188:19] .io_in_bits_in3 (sfma_io_in_bits_req_in3), // @[fpu.scala:188:19] .io_out_valid (_sfma_io_out_valid), .io_out_bits_data (_sfma_io_out_bits_data), .io_out_bits_exc (_sfma_io_out_bits_exc) ); // @[fpu.scala:212:20] FMADecoder_1 sfma_io_in_bits_fma_decoder ( // @[fpu.scala:202:29] .clock (clock), .reset (reset), .io_uopc (io_req_bits_uop_uopc_0), // @[fpu.scala:170:7] .io_cmd (sfma_io_in_bits_req_fmaCmd) ); // @[fpu.scala:202:29] FPToInt fpiu ( // @[fpu.scala:216:20] .clock (clock), .reset (reset), .io_in_valid (_fpiu_io_in_valid_T_2), // @[fpu.scala:217:36] .io_in_bits_ldst (fpiu_io_in_bits_req_ldst), // @[fpu.scala:188:19] .io_in_bits_wen (fpiu_io_in_bits_req_wen), // @[fpu.scala:188:19] .io_in_bits_ren1 (fpiu_io_in_bits_req_ren1), // @[fpu.scala:188:19] .io_in_bits_ren2 (fpiu_io_in_bits_req_ren2), // @[fpu.scala:188:19] .io_in_bits_ren3 (fpiu_io_in_bits_req_ren3), // @[fpu.scala:188:19] .io_in_bits_swap12 (fpiu_io_in_bits_req_swap12), // @[fpu.scala:188:19] .io_in_bits_swap23 (fpiu_io_in_bits_req_swap23), // @[fpu.scala:188:19] .io_in_bits_typeTagIn (fpiu_io_in_bits_req_typeTagIn), // @[fpu.scala:188:19] .io_in_bits_typeTagOut (fpiu_io_in_bits_req_typeTagOut), // @[fpu.scala:188:19] .io_in_bits_fromint (fpiu_io_in_bits_req_fromint), // @[fpu.scala:188:19] .io_in_bits_toint (fpiu_io_in_bits_req_toint), // @[fpu.scala:188:19] .io_in_bits_fastpipe (fpiu_io_in_bits_req_fastpipe), // @[fpu.scala:188:19] .io_in_bits_fma (fpiu_io_in_bits_req_fma), // @[fpu.scala:188:19] .io_in_bits_div (fpiu_io_in_bits_req_div), // @[fpu.scala:188:19] .io_in_bits_sqrt (fpiu_io_in_bits_req_sqrt), // @[fpu.scala:188:19] .io_in_bits_wflags (fpiu_io_in_bits_req_wflags), // @[fpu.scala:188:19] .io_in_bits_rm (fpiu_io_in_bits_req_rm), // @[fpu.scala:188:19] .io_in_bits_fmaCmd (fpiu_io_in_bits_req_fmaCmd), // @[fpu.scala:188:19] .io_in_bits_typ (fpiu_io_in_bits_req_typ), // @[fpu.scala:188:19] .io_in_bits_fmt (fpiu_io_in_bits_req_fmt), // @[fpu.scala:188:19] .io_in_bits_in1 (fpiu_io_in_bits_req_in1), // @[fpu.scala:188:19] .io_in_bits_in2 (fpiu_io_in_bits_req_in2), // @[fpu.scala:188:19] .io_in_bits_in3 (fpiu_io_in_bits_req_in3), // @[fpu.scala:188:19] .io_out_bits_in_ldst (_fpiu_io_out_bits_in_ldst), .io_out_bits_in_wen (_fpiu_io_out_bits_in_wen), .io_out_bits_in_ren1 (_fpiu_io_out_bits_in_ren1), .io_out_bits_in_ren2 (_fpiu_io_out_bits_in_ren2), .io_out_bits_in_ren3 (_fpiu_io_out_bits_in_ren3), .io_out_bits_in_swap12 (_fpiu_io_out_bits_in_swap12), .io_out_bits_in_swap23 (_fpiu_io_out_bits_in_swap23), .io_out_bits_in_typeTagIn (_fpiu_io_out_bits_in_typeTagIn), .io_out_bits_in_typeTagOut (_fpiu_io_out_bits_in_typeTagOut), .io_out_bits_in_fromint (_fpiu_io_out_bits_in_fromint), .io_out_bits_in_toint (_fpiu_io_out_bits_in_toint), .io_out_bits_in_fastpipe (_fpiu_io_out_bits_in_fastpipe), .io_out_bits_in_fma (_fpiu_io_out_bits_in_fma), .io_out_bits_in_div (_fpiu_io_out_bits_in_div), .io_out_bits_in_sqrt (_fpiu_io_out_bits_in_sqrt), .io_out_bits_in_wflags (_fpiu_io_out_bits_in_wflags), .io_out_bits_in_rm (_fpiu_io_out_bits_in_rm), .io_out_bits_in_fmaCmd (_fpiu_io_out_bits_in_fmaCmd), .io_out_bits_in_typ (_fpiu_io_out_bits_in_typ), .io_out_bits_in_fmt (_fpiu_io_out_bits_in_fmt), .io_out_bits_in_in1 (_fpiu_io_out_bits_in_in1), .io_out_bits_in_in2 (_fpiu_io_out_bits_in_in2), .io_out_bits_in_in3 (_fpiu_io_out_bits_in_in3), .io_out_bits_lt (_fpiu_io_out_bits_lt), .io_out_bits_store (_fpiu_io_out_bits_store), .io_out_bits_toint (_fpiu_io_out_bits_toint), .io_out_bits_exc (_fpiu_io_out_bits_exc) ); // @[fpu.scala:216:20] FMADecoder_2 fpiu_io_in_bits_fma_decoder ( // @[fpu.scala:202:29] .clock (clock), .reset (reset), .io_uopc (io_req_bits_uop_uopc_0), // @[fpu.scala:170:7] .io_cmd (fpiu_io_in_bits_req_fmaCmd) ); // @[fpu.scala:202:29] FPToFP fpmu ( // @[fpu.scala:225:20] .clock (clock), .reset (reset), .io_in_valid (_fpmu_io_in_valid_T), // @[fpu.scala:226:36] .io_in_bits_ldst (fpiu_io_in_bits_req_ldst), // @[fpu.scala:188:19] .io_in_bits_wen (fpiu_io_in_bits_req_wen), // @[fpu.scala:188:19] .io_in_bits_ren1 (fpiu_io_in_bits_req_ren1), // @[fpu.scala:188:19] .io_in_bits_ren2 (fpiu_io_in_bits_req_ren2), // @[fpu.scala:188:19] .io_in_bits_ren3 (fpiu_io_in_bits_req_ren3), // @[fpu.scala:188:19] .io_in_bits_swap12 (fpiu_io_in_bits_req_swap12), // @[fpu.scala:188:19] .io_in_bits_swap23 (fpiu_io_in_bits_req_swap23), // @[fpu.scala:188:19] .io_in_bits_typeTagIn (fpiu_io_in_bits_req_typeTagIn), // @[fpu.scala:188:19] .io_in_bits_typeTagOut (fpiu_io_in_bits_req_typeTagOut), // @[fpu.scala:188:19] .io_in_bits_fromint (fpiu_io_in_bits_req_fromint), // @[fpu.scala:188:19] .io_in_bits_toint (fpiu_io_in_bits_req_toint), // @[fpu.scala:188:19] .io_in_bits_fastpipe (fpiu_io_in_bits_req_fastpipe), // @[fpu.scala:188:19] .io_in_bits_fma (fpiu_io_in_bits_req_fma), // @[fpu.scala:188:19] .io_in_bits_div (fpiu_io_in_bits_req_div), // @[fpu.scala:188:19] .io_in_bits_sqrt (fpiu_io_in_bits_req_sqrt), // @[fpu.scala:188:19] .io_in_bits_wflags (fpiu_io_in_bits_req_wflags), // @[fpu.scala:188:19] .io_in_bits_rm (fpiu_io_in_bits_req_rm), // @[fpu.scala:188:19] .io_in_bits_fmaCmd (fpiu_io_in_bits_req_fmaCmd), // @[fpu.scala:188:19] .io_in_bits_typ (fpiu_io_in_bits_req_typ), // @[fpu.scala:188:19] .io_in_bits_fmt (fpiu_io_in_bits_req_fmt), // @[fpu.scala:188:19] .io_in_bits_in1 (fpiu_io_in_bits_req_in1), // @[fpu.scala:188:19] .io_in_bits_in2 (fpiu_io_in_bits_req_in2), // @[fpu.scala:188:19] .io_in_bits_in3 (fpiu_io_in_bits_req_in3), // @[fpu.scala:188:19] .io_out_valid (_fpmu_io_out_valid), .io_out_bits_data (_fpmu_io_out_bits_data), .io_out_bits_exc (_fpmu_io_out_bits_exc), .io_lt (_fpiu_io_out_bits_lt) // @[fpu.scala:216:20] ); // @[fpu.scala:225:20] assign io_resp_bits_data = io_resp_bits_data_0; // @[fpu.scala:170:7] assign io_resp_bits_fflags_valid = io_resp_bits_fflags_valid_0; // @[fpu.scala:170:7] assign io_resp_bits_fflags_bits_flags = io_resp_bits_fflags_bits_flags_0; // @[fpu.scala:170:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File DspBlock.scala: // SPDX-License-Identifier: Apache-2.0 package dspblocks import chisel3._ import freechips.rocketchip.amba.ahb._ import freechips.rocketchip.amba.apb._ import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.amba.axi4stream._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.tilelink._ /** * Base trait for basic unit of computation * @tparam D Down parameter type * @tparam U Up parameter type * @tparam EO Edge-out parameter type * @tparam EI Edge-in parameter type * @tparam B Bundle parameter type */ trait DspBlock[D, U, EO, EI, B <: Data] extends LazyModule { /** * Diplomatic node for AXI4-Stream interfaces */ val streamNode: AXI4StreamNodeHandle /** * Diplmatic node for memory interface * Some blocks might not need memory mapping, so this is an Option[] */ val mem: Option[MixedNode[D, U, EI, B, D, U, EO, B]] } /** * Mixin for DspBlock to make them standalone (i.e., you can build them as a top-level module). * This is especially important for testing. * * Adds BundleBridges to the input and output sides of the AXI4Stream node * @tparam D Down parameter type * @tparam U Up parameter type * @tparam EO Edge-out parameter type * @tparam EI Edge-in parameter type * @tparam B Bundle parameter type */ trait StandaloneBlock[D, U, EO, EI, B <: Data] extends DspBlock[D, U, EO, EI, B] { val ioInNode = BundleBridgeSource(() => new AXI4StreamBundle(AXI4StreamBundleParameters(n = 8))) val ioOutNode = BundleBridgeSink[AXI4StreamBundle]() ioOutNode := AXI4StreamToBundleBridge(AXI4StreamSlaveParameters()) := streamNode := BundleBridgeToAXI4Stream(AXI4StreamMasterParameters()) := ioInNode val in = InModuleBody { ioInNode.makeIO() } val out = InModuleBody { ioOutNode.makeIO() } } /** * AXI4-flavor of standalone block. Adds BundleBridge AXI4 interface. */ trait AXI4StandaloneBlock extends StandaloneBlock[ AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4EdgeParameters, AXI4Bundle ] { def standaloneParams = AXI4BundleParameters(addrBits = 64, dataBits = 64, idBits = 1) val ioMem = mem.map { m => { val ioMemNode = BundleBridgeSource(() => AXI4Bundle(standaloneParams)) m := BundleBridgeToAXI4(AXI4MasterPortParameters(Seq(AXI4MasterParameters("bundleBridgeToAXI4")))) := ioMemNode val ioMem = InModuleBody { ioMemNode.makeIO() } ioMem } } } /** * APB-flavor of standalone block. Adds BundleBridge APB interface. */ trait APBStandaloneBlock extends StandaloneBlock[ APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBEdgeParameters, APBBundle ] { def standaloneParams = APBBundleParameters(addrBits = 64, dataBits = 64) val ioMem = mem.map { m => { val ioMemNode = BundleBridgeSource(() => APBBundle(standaloneParams)) m := BundleBridgeToAPB(APBMasterPortParameters(Seq(APBMasterParameters("bundleBridgeToAPB")))) := ioMemNode val ioMem = InModuleBody { ioMemNode.makeIO() } ioMem } } } /** * TL-flavor of standalone block. Adds BundleBridge TL interface. */ trait TLStandaloneBlock extends StandaloneBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def standaloneParams = TLBundleParameters( addressBits = 64, dataBits = 64, sourceBits = 1, sinkBits = 1, sizeBits = 6, echoFields = Seq(), requestFields = Seq(), responseFields = Seq(), hasBCE = false ) val ioMem = mem.map { m => { val ioMemNode = BundleBridgeSource(() => TLBundle(standaloneParams)) m := BundleBridgeToTL(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1("bundleBridgeToTL")))) := ioMemNode val ioMem = InModuleBody { ioMemNode.makeIO() } ioMem } } } trait TLDspBlock extends DspBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle] trait TLDspBlockWithBus extends TLDspBlock { val bus = LazyModule(new TLXbar) val mem = Some(bus.node) } trait APBDspBlock extends DspBlock[APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBEdgeParameters, APBBundle] trait APBDspBlockWithBus extends APBDspBlock { val bus = LazyModule(new APBFanout) val mem = Some(bus.node) } object AXI4DspBlock { type AXI4Node = MixedNode[ AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4Bundle, AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4Bundle ] } trait AXI4DspBlock extends DspBlock[ AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4EdgeParameters, AXI4Bundle ] trait AXI4DspBlockWithBus extends AXI4DspBlock { val bus = LazyModule(new AXI4Xbar) val mem = Some(bus.node) } trait AHBSlaveDspBlock extends DspBlock[ AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBEdgeParameters, AHBSlaveBundle ] trait AHBSlaveDspBlockWithBus extends AHBSlaveDspBlock { val bus = LazyModule(new AHBFanout) val mem = Some(bus.node) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File StreamingPassthrough.scala: //// See LICENSE for license details. // package chipyard.example import chisel3._ import chisel3.{Bundle, Module} import chisel3.util._ import dspblocks._ import dsptools.numbers._ import freechips.rocketchip.amba.axi4stream._ import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ // Simple passthrough to use as testbed sanity check // StreamingPassthrough params case class StreamingPassthroughParams( writeAddress: BigInt = 0x2200, readAddress: BigInt = 0x2300, depth: Int ) // StreamingPassthrough key case object StreamingPassthroughKey extends Field[Option[StreamingPassthroughParams]](None) class StreamingPassthroughBundle[T<:Data:Ring](proto: T) extends Bundle { val data: T = proto.cloneType } object StreamingPassthroughBundle { def apply[T<:Data:Ring](proto: T): StreamingPassthroughBundle[T] = new StreamingPassthroughBundle(proto) } class StreamingPassthroughIO[T<:Data:Ring](proto: T) extends Bundle { val in = Flipped(Decoupled(StreamingPassthroughBundle(proto))) val out = Decoupled(StreamingPassthroughBundle(proto)) } object StreamingPassthroughIO { def apply[T<:Data:Ring](proto: T): StreamingPassthroughIO[T] = new StreamingPassthroughIO(proto) } class StreamingPassthrough[T<:Data:Ring](proto: T) extends Module { val io = IO(StreamingPassthroughIO(proto)) io.in.ready := io.out.ready io.out.bits.data := io.in.bits.data io.out.valid := io.in.valid } /** * Make DspBlock wrapper for StreamingPassthrough * @param cordicParams parameters for cordic * @param ev$1 * @param ev$2 * @param ev$3 * @param p * @tparam D * @tparam U * @tparam EO * @tparam EI * @tparam B * @tparam T Type parameter for passthrough, i.e. FixedPoint or DspReal */ abstract class StreamingPassthroughBlock[D, U, EO, EI, B<:Data, T<:Data:Ring] ( proto: T )(implicit p: Parameters) extends DspBlock[D, U, EO, EI, B] { val streamNode = AXI4StreamIdentityNode() val mem = None lazy val module = new LazyModuleImp(this) { require(streamNode.in.length == 1) require(streamNode.out.length == 1) val in = streamNode.in.head._1 val out = streamNode.out.head._1 // instantiate passthrough val passthrough = Module(new StreamingPassthrough(proto)) // Pass ready and valid from read queue to write queue in.ready := passthrough.io.in.ready passthrough.io.in.valid := in.valid // cast UInt to T passthrough.io.in.bits := in.bits.data.asTypeOf(StreamingPassthroughBundle(proto)) passthrough.io.out.ready := out.ready out.valid := passthrough.io.out.valid // cast T to UInt out.bits.data := passthrough.io.out.bits.asUInt } } /** * TLDspBlock specialization of StreamingPassthrough * @param cordicParams parameters for passthrough * @param ev$1 * @param ev$2 * @param ev$3 * @param p * @tparam T Type parameter for passthrough data type */ class TLStreamingPassthroughBlock[T<:Data:Ring] ( val proto: T )(implicit p: Parameters) extends StreamingPassthroughBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle, T](proto) with TLDspBlock /** * A chain of queues acting as our MMIOs with the passthrough module in between them. * @param depth depth of queues * @param ev$1 * @param ev$2 * @param ev$3 * @param p * @tparam T Type parameter for passthrough, i.e. FixedPoint or DspReal */ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughParams, proto: T)(implicit p: Parameters) extends TLChain(Seq( TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))(_), { implicit p: Parameters => { val streamingPassthrough = LazyModule(new TLStreamingPassthroughBlock(proto)) streamingPassthrough }}, TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))(_) )) trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem => val passthrough = p(StreamingPassthroughKey) match { case Some(params) => { val pbus = locateTLBusWrapper(PBUS) val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain") val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) } pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ } Some(streamingPassthroughChain) } case None => None } } /** * Mixin to add passthrough to rocket config */ class WithStreamingPassthrough extends Config((site, here, up) => { case StreamingPassthroughKey => Some(StreamingPassthroughParams(depth = 8)) }) File DspBlocks.scala: package chipyard.example import chisel3._ import chisel3.util._ import dspblocks._ import dsptools.numbers._ import freechips.rocketchip.amba.axi4stream._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ /** * The memory interface writes entries into the queue. * They stream out the streaming interface * @param depth number of entries in the queue * @param streamParameters parameters for the stream node * @param p */ abstract class WriteQueue[D, U, E, O, B <: Data] ( val depth: Int, val streamParameters: AXI4StreamMasterParameters = AXI4StreamMasterParameters() )(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR { // stream node, output only val streamNode = AXI4StreamMasterNode(streamParameters) lazy val module = new LazyModuleImp(this) { require(streamNode.out.length == 1) // get the output bundle associated with the AXI4Stream node val out = streamNode.out.head._1 // width (in bits) of the output interface val width = out.params.n * 8 // instantiate a queue val queue = Module(new Queue(UInt(out.params.dataBits.W), depth)) // connect queue output to streaming output out.valid := queue.io.deq.valid out.bits.data := queue.io.deq.bits // don't use last out.bits.last := false.B queue.io.deq.ready := out.ready regmap( // each write adds an entry to the queue 0x0 -> Seq(RegField.w(width, queue.io.enq)), // read the number of entries in the queue (width+7)/8 -> Seq(RegField.r(width, queue.io.count)), ) } } /** * TLDspBlock specialization of WriteQueue * @param depth number of entries in the queue * @param csrAddress address range for peripheral * @param beatBytes beatBytes of TL interface * @param p */ class TLWriteQueue (depth: Int, csrAddress: AddressSet, beatBytes: Int) (implicit p: Parameters) extends WriteQueue[ TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle ](depth) with TLHasCSR { val devname = "tlQueueIn" val devcompat = Seq("ucb-art", "dsptools") val device = new SimpleDevice(devname, devcompat) { override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) Description(name, mapping) } } // make diplomatic TL node for regmap override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) } object TLWriteQueue { def apply( depth: Int = 8, csrAddress: AddressSet = AddressSet(0x2000, 0xff), beatBytes: Int = 8, )(implicit p: Parameters) = { val writeQueue = LazyModule(new TLWriteQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes)) writeQueue } } /** * The streaming interface adds elements into the queue. * The memory interface can read elements out of the queue. * @param depth number of entries in the queue * @param streamParameters parameters for the stream node * @param p */ abstract class ReadQueue[D, U, E, O, B <: Data] ( val depth: Int, val streamParameters: AXI4StreamSlaveParameters = AXI4StreamSlaveParameters() )(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR { val streamNode = AXI4StreamSlaveNode(streamParameters) lazy val module = new LazyModuleImp(this) { require(streamNode.in.length == 1) // get the input associated with the stream node val in = streamNode.in.head._1 // make a Decoupled[UInt] that RegReadFn can do something with val out = Wire(Decoupled(UInt())) // get width of streaming input interface val width = in.params.n * 8 // instantiate a queue val queue = Module(new Queue(UInt(in.params.dataBits.W), depth)) // connect input to the streaming interface queue.io.enq.valid := in.valid queue.io.enq.bits := in.bits.data in.ready := queue.io.enq.ready // connect output to wire out.valid := queue.io.deq.valid out.bits := queue.io.deq.bits queue.io.deq.ready := out.ready regmap( // map the output of the queue 0x0 -> Seq(RegField.r(width, RegReadFn(out))), // read the number of elements in the queue (width+7)/8 -> Seq(RegField.r(width, queue.io.count)), ) } } /** * TLDspBlock specialization of ReadQueue * @param depth number of entries in the queue * @param csrAddress address range * @param beatBytes beatBytes of TL interface * @param p */ class TLReadQueue( depth: Int, csrAddress: AddressSet, beatBytes: Int) (implicit p: Parameters) extends ReadQueue[ TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle ](depth) with TLHasCSR { val devname = "tlQueueOut" val devcompat = Seq("ucb-art", "dsptools") val device = new SimpleDevice(devname, devcompat) { override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) Description(name, mapping) } } // make diplomatic TL node for regmap override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) } object TLReadQueue { def apply( depth: Int = 8, csrAddress: AddressSet = AddressSet(0x2100, 0xff), beatBytes: Int = 8)(implicit p: Parameters) = { val readQueue = LazyModule(new TLReadQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes)) readQueue } }

module TLStreamingPassthroughChain( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] output auto_bus_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_bus_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_bus_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_bus_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_bus_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_anon_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _bus_auto_anon_out_1_a_valid; // @[DspBlock.scala:146:23] wire [2:0] _bus_auto_anon_out_1_a_bits_opcode; // @[DspBlock.scala:146:23] wire [2:0] _bus_auto_anon_out_1_a_bits_param; // @[DspBlock.scala:146:23] wire [1:0] _bus_auto_anon_out_1_a_bits_size; // @[DspBlock.scala:146:23] wire [10:0] _bus_auto_anon_out_1_a_bits_source; // @[DspBlock.scala:146:23] wire [13:0] _bus_auto_anon_out_1_a_bits_address; // @[DspBlock.scala:146:23] wire [7:0] _bus_auto_anon_out_1_a_bits_mask; // @[DspBlock.scala:146:23] wire _bus_auto_anon_out_1_a_bits_corrupt; // @[DspBlock.scala:146:23] wire _bus_auto_anon_out_1_d_ready; // @[DspBlock.scala:146:23] wire _bus_auto_anon_out_0_a_valid; // @[DspBlock.scala:146:23] wire [2:0] _bus_auto_anon_out_0_a_bits_opcode; // @[DspBlock.scala:146:23] wire [2:0] _bus_auto_anon_out_0_a_bits_param; // @[DspBlock.scala:146:23] wire [1:0] _bus_auto_anon_out_0_a_bits_size; // @[DspBlock.scala:146:23] wire [10:0] _bus_auto_anon_out_0_a_bits_source; // @[DspBlock.scala:146:23] wire [13:0] _bus_auto_anon_out_0_a_bits_address; // @[DspBlock.scala:146:23] wire [7:0] _bus_auto_anon_out_0_a_bits_mask; // @[DspBlock.scala:146:23] wire [63:0] _bus_auto_anon_out_0_a_bits_data; // @[DspBlock.scala:146:23] wire _bus_auto_anon_out_0_a_bits_corrupt; // @[DspBlock.scala:146:23] wire _bus_auto_anon_out_0_d_ready; // @[DspBlock.scala:146:23] wire _readQueue_auto_mem_in_a_ready; // @[DspBlocks.scala:159:31] wire _readQueue_auto_mem_in_d_valid; // @[DspBlocks.scala:159:31] wire [2:0] _readQueue_auto_mem_in_d_bits_opcode; // @[DspBlocks.scala:159:31] wire [1:0] _readQueue_auto_mem_in_d_bits_size; // @[DspBlocks.scala:159:31] wire [10:0] _readQueue_auto_mem_in_d_bits_source; // @[DspBlocks.scala:159:31] wire [63:0] _readQueue_auto_mem_in_d_bits_data; // @[DspBlocks.scala:159:31] wire _readQueue_auto_stream_in_ready; // @[DspBlocks.scala:159:31] wire _streamingPassthrough_passthrough_io_in_ready; // @[StreamingPassthrough.scala:79:29] wire _streamingPassthrough_passthrough_io_out_valid; // @[StreamingPassthrough.scala:79:29] wire [31:0] _streamingPassthrough_passthrough_io_out_bits_data; // @[StreamingPassthrough.scala:79:29] wire _writeQueue_auto_mem_in_a_ready; // @[DspBlocks.scala:83:32] wire _writeQueue_auto_mem_in_d_valid; // @[DspBlocks.scala:83:32] wire [2:0] _writeQueue_auto_mem_in_d_bits_opcode; // @[DspBlocks.scala:83:32] wire [1:0] _writeQueue_auto_mem_in_d_bits_size; // @[DspBlocks.scala:83:32] wire [10:0] _writeQueue_auto_mem_in_d_bits_source; // @[DspBlocks.scala:83:32] wire [63:0] _writeQueue_auto_mem_in_d_bits_data; // @[DspBlocks.scala:83:32] wire _writeQueue_auto_stream_out_valid; // @[DspBlocks.scala:83:32] wire [63:0] _writeQueue_auto_stream_out_bits_data; // @[DspBlocks.scala:83:32] TLWriteQueue_1 writeQueue ( // @[DspBlocks.scala:83:32] .clock (clock), .reset (reset), .auto_mem_in_a_ready (_writeQueue_auto_mem_in_a_ready), .auto_mem_in_a_valid (_bus_auto_anon_out_0_a_valid), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_opcode (_bus_auto_anon_out_0_a_bits_opcode), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_param (_bus_auto_anon_out_0_a_bits_param), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_size (_bus_auto_anon_out_0_a_bits_size), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_source (_bus_auto_anon_out_0_a_bits_source), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_address (_bus_auto_anon_out_0_a_bits_address), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_mask (_bus_auto_anon_out_0_a_bits_mask), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_data (_bus_auto_anon_out_0_a_bits_data), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_corrupt (_bus_auto_anon_out_0_a_bits_corrupt), // @[DspBlock.scala:146:23] .auto_mem_in_d_ready (_bus_auto_anon_out_0_d_ready), // @[DspBlock.scala:146:23] .auto_mem_in_d_valid (_writeQueue_auto_mem_in_d_valid), .auto_mem_in_d_bits_opcode (_writeQueue_auto_mem_in_d_bits_opcode), .auto_mem_in_d_bits_size (_writeQueue_auto_mem_in_d_bits_size), .auto_mem_in_d_bits_source (_writeQueue_auto_mem_in_d_bits_source), .auto_mem_in_d_bits_data (_writeQueue_auto_mem_in_d_bits_data), .auto_stream_out_ready (_streamingPassthrough_passthrough_io_in_ready), // @[StreamingPassthrough.scala:79:29] .auto_stream_out_valid (_writeQueue_auto_stream_out_valid), .auto_stream_out_bits_data (_writeQueue_auto_stream_out_bits_data) ); // @[DspBlocks.scala:83:32] StreamingPassthrough streamingPassthrough_passthrough ( // @[StreamingPassthrough.scala:79:29] .io_in_ready (_streamingPassthrough_passthrough_io_in_ready), .io_in_valid (_writeQueue_auto_stream_out_valid), // @[DspBlocks.scala:83:32] .io_in_bits_data (_writeQueue_auto_stream_out_bits_data[31:0]), // @[StreamingPassthrough.scala:86:52] .io_out_ready (_readQueue_auto_stream_in_ready), // @[DspBlocks.scala:159:31] .io_out_valid (_streamingPassthrough_passthrough_io_out_valid), .io_out_bits_data (_streamingPassthrough_passthrough_io_out_bits_data) ); // @[StreamingPassthrough.scala:79:29] TLReadQueue_1 readQueue ( // @[DspBlocks.scala:159:31] .clock (clock), .reset (reset), .auto_mem_in_a_ready (_readQueue_auto_mem_in_a_ready), .auto_mem_in_a_valid (_bus_auto_anon_out_1_a_valid), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_opcode (_bus_auto_anon_out_1_a_bits_opcode), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_param (_bus_auto_anon_out_1_a_bits_param), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_size (_bus_auto_anon_out_1_a_bits_size), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_source (_bus_auto_anon_out_1_a_bits_source), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_address (_bus_auto_anon_out_1_a_bits_address), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_mask (_bus_auto_anon_out_1_a_bits_mask), // @[DspBlock.scala:146:23] .auto_mem_in_a_bits_corrupt (_bus_auto_anon_out_1_a_bits_corrupt), // @[DspBlock.scala:146:23] .auto_mem_in_d_ready (_bus_auto_anon_out_1_d_ready), // @[DspBlock.scala:146:23] .auto_mem_in_d_valid (_readQueue_auto_mem_in_d_valid), .auto_mem_in_d_bits_opcode (_readQueue_auto_mem_in_d_bits_opcode), .auto_mem_in_d_bits_size (_readQueue_auto_mem_in_d_bits_size), .auto_mem_in_d_bits_source (_readQueue_auto_mem_in_d_bits_source), .auto_mem_in_d_bits_data (_readQueue_auto_mem_in_d_bits_data), .auto_stream_in_ready (_readQueue_auto_stream_in_ready), .auto_stream_in_valid (_streamingPassthrough_passthrough_io_out_valid), // @[StreamingPassthrough.scala:79:29] .auto_stream_in_bits_data ({32'h0, _streamingPassthrough_passthrough_io_out_bits_data}) // @[StreamingPassthrough.scala:79:29, :92:19] ); // @[DspBlocks.scala:159:31] TLXbar_i1_o2_a14d64s11k1z2u_1 bus ( // @[DspBlock.scala:146:23] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_bus_anon_in_a_ready), .auto_anon_in_a_valid (auto_bus_anon_in_a_valid), .auto_anon_in_a_bits_opcode (auto_bus_anon_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_bus_anon_in_a_bits_param), .auto_anon_in_a_bits_size (auto_bus_anon_in_a_bits_size), .auto_anon_in_a_bits_source (auto_bus_anon_in_a_bits_source), .auto_anon_in_a_bits_address (auto_bus_anon_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_bus_anon_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_bus_anon_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_bus_anon_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_bus_anon_in_d_ready), .auto_anon_in_d_valid (auto_bus_anon_in_d_valid), .auto_anon_in_d_bits_opcode (auto_bus_anon_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_bus_anon_in_d_bits_size), .auto_anon_in_d_bits_source (auto_bus_anon_in_d_bits_source), .auto_anon_in_d_bits_data (auto_bus_anon_in_d_bits_data), .auto_anon_out_1_a_ready (_readQueue_auto_mem_in_a_ready), // @[DspBlocks.scala:159:31] .auto_anon_out_1_a_valid (_bus_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_bus_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_bus_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_bus_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_bus_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_bus_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_bus_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_corrupt (_bus_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_bus_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_readQueue_auto_mem_in_d_valid), // @[DspBlocks.scala:159:31] .auto_anon_out_1_d_bits_opcode (_readQueue_auto_mem_in_d_bits_opcode), // @[DspBlocks.scala:159:31] .auto_anon_out_1_d_bits_size (_readQueue_auto_mem_in_d_bits_size), // @[DspBlocks.scala:159:31] .auto_anon_out_1_d_bits_source (_readQueue_auto_mem_in_d_bits_source), // @[DspBlocks.scala:159:31] .auto_anon_out_1_d_bits_data (_readQueue_auto_mem_in_d_bits_data), // @[DspBlocks.scala:159:31] .auto_anon_out_0_a_ready (_writeQueue_auto_mem_in_a_ready), // @[DspBlocks.scala:83:32] .auto_anon_out_0_a_valid (_bus_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_bus_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_bus_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_bus_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_bus_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_bus_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_bus_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_bus_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_bus_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_bus_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_writeQueue_auto_mem_in_d_valid), // @[DspBlocks.scala:83:32] .auto_anon_out_0_d_bits_opcode (_writeQueue_auto_mem_in_d_bits_opcode), // @[DspBlocks.scala:83:32] .auto_anon_out_0_d_bits_size (_writeQueue_auto_mem_in_d_bits_size), // @[DspBlocks.scala:83:32] .auto_anon_out_0_d_bits_source (_writeQueue_auto_mem_in_d_bits_source), // @[DspBlocks.scala:83:32] .auto_anon_out_0_d_bits_data (_writeQueue_auto_mem_in_d_bits_data) // @[DspBlocks.scala:83:32] ); // @[DspBlock.scala:146:23] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_171( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_427 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File lsu.scala: //****************************************************************************** // Copyright (c) 2012 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Out-of-Order Load/Store Unit //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // Load/Store Unit is made up of the Load-Address Queue, the Store-Address // Queue, and the Store-Data queue (LAQ, SAQ, and SDQ). // // Stores are sent to memory at (well, after) commit, loads are executed // optimstically ASAP. If a misspeculation was discovered, the pipeline is // cleared. Loads put to sleep are retried. If a LoadAddr and StoreAddr match, // the Load can receive its data by forwarding data out of the Store-Data // Queue. // // Currently, loads are sent to memory immediately, and in parallel do an // associative search of the SAQ, on entering the LSU. If a hit on the SAQ // search, the memory request is killed on the next cycle, and if the SDQ entry // is valid, the store data is forwarded to the load (delayed to match the // load-use delay to delay with the write-port structural hazard). If the store // data is not present, or it's only a partial match (SB->LH), the load is put // to sleep in the LAQ. // // Memory ordering violations are detected by stores at their addr-gen time by // associatively searching the LAQ for newer loads that have been issued to // memory. // // The store queue contains both speculated and committed stores. // // Only one port to memory... loads and stores have to fight for it, West Side // Story style. // // TODO: // - Add predicting structure for ordering failures // - currently won't STD forward if DMEM is busy // - ability to turn off things if VM is disabled // - reconsider port count of the wakeup, retry stuff package boom.v4.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.Str import boom.v4.common._ import boom.v4.exu.{BrUpdateInfo, Exception, CommitSignals, MemGen, ExeUnitResp, Wakeup} import boom.v4.util._ class BoomDCacheReq(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = UInt(coreMaxAddrBits.W) val data = Bits(coreDataBits.W) val is_hella = Bool() // Is this the hellacache req? If so this is not tracked in LDQ or STQ } class BoomDCacheResp(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val data = Bits(coreDataBits.W) val is_hella = Bool() } class LSUDMemIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { // In LSU's dmem stage, send the request val req = new DecoupledIO(Vec(lsuWidth, Valid(new BoomDCacheReq))) // In LSU's LCAM search stage, kill if order fail (or forwarding possible) val s1_kill = Output(Vec(lsuWidth, Bool())) // The s1 inflight request will likely get nacked next cycle val s1_nack_advisory = Input(Vec(lsuWidth, Bool())) // Get a request any cycle val resp = Flipped(Vec(lsuWidth, new ValidIO(new BoomDCacheResp))) // The cache irrevocably accepted our store val store_ack = Flipped(Vec(lsuWidth, new ValidIO(new BoomDCacheReq))) // In our response stage, if we get a nack, we need to reexecute val nack = Flipped(Vec(lsuWidth, new ValidIO(new BoomDCacheReq))) val ll_resp = Flipped(new DecoupledIO(new BoomDCacheResp)) val brupdate = Output(new BrUpdateInfo) val exception = Output(Bool()) val rob_pnr_idx = Output(UInt(robAddrSz.W)) val rob_head_idx = Output(UInt(robAddrSz.W)) val release = Flipped(new DecoupledIO(new TLBundleC(edge.bundle))) // Clears prefetching MSHRs val force_order = Output(Bool()) val ordered = Input(Bool()) val perf = Input(new Bundle { val acquire = Bool() val release = Bool() }) } class LSUCoreIO(implicit p: Parameters) extends BoomBundle()(p) { val agen = Flipped(Vec(lsuWidth, Valid(new MemGen))) val dgen = Flipped(Vec(memWidth + 1, Valid(new MemGen))) val iwakeups = Vec(lsuWidth, Valid(new Wakeup)) val iresp = Vec(lsuWidth, Valid(new ExeUnitResp(xLen))) val fresp = Vec(lsuWidth, Valid(new ExeUnitResp(xLen))) val sfence = Flipped(Valid(new rocket.SFenceReq)) val dis_uops = Flipped(Vec(coreWidth, Valid(new MicroOp))) val dis_ldq_idx = Output(Vec(coreWidth, UInt(ldqAddrSz.W))) val dis_stq_idx = Output(Vec(coreWidth, UInt(stqAddrSz.W))) val ldq_full = Output(Vec(coreWidth, Bool())) val stq_full = Output(Vec(coreWidth, Bool())) val commit = Input(new CommitSignals) val commit_load_at_rob_head = Input(Bool()) // Stores clear busy bit when stdata is received // memWidth for incoming addr/datagen, +1 for fp dgen, +1 for clr_head pointer val clr_bsy = Output(Vec(coreWidth, Valid(UInt(robAddrSz.W)))) // Speculatively safe load (barring memory ordering failure) val clr_unsafe = Output(Vec(lsuWidth, Valid(UInt(robAddrSz.W)))) // Tell the DCache to clear prefetches/speculating misses val fence_dmem = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val exception = Input(Bool()) val fencei_rdy = Output(Bool()) val lxcpt = Output(Valid(new Exception)) val tsc_reg = Input(UInt()) val status = Input(new rocket.MStatus) val bp = Input(Vec(nBreakpoints, new rocket.BP)) val mcontext = Input(UInt()) val scontext = Input(UInt()) val perf = Output(new Bundle { val acquire = Bool() val release = Bool() val tlbMiss = Bool() }) } class LSUIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { val ptw = new rocket.TLBPTWIO val core = new LSUCoreIO val dmem = new LSUDMemIO val hellacache = Flipped(new freechips.rocketchip.rocket.HellaCacheIO) } class LDQEntry(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = Valid(UInt(coreMaxAddrBits.W)) val addr_is_virtual = Bool() // Virtual address, we got a TLB miss val addr_is_uncacheable = Bool() // Uncacheable, wait until head of ROB to execute val executed = Bool() // load sent to memory, reset by NACKs val succeeded = Bool() val order_fail = Bool() val observed = Bool() val st_dep_mask = UInt(numStqEntries.W) // list of stores older than us val ld_byte_mask = UInt(8.W) val forward_std_val = Bool() val forward_stq_idx = UInt(stqAddrSz.W) // Which store did we get the store-load forward from? val debug_wb_data = UInt(xLen.W) } class STQEntry(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = Valid(UInt(coreMaxAddrBits.W)) val addr_is_virtual = Bool() // Virtual address, we got a TLB miss val data = Valid(UInt(xLen.W)) val committed = Bool() // committed by ROB val succeeded = Bool() // D$ has ack'd this, we don't need to maintain this anymore val can_execute = Bool() val cleared = Bool() // we've cleared this entry in the ROB val debug_wb_data = UInt(xLen.W) } class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p) with rocket.HasL1HellaCacheParameters { val io = IO(new LSUIO) //val ldq = Reg(Vec(numLdqEntries, Valid(new LDQEntry))) val ldq_valid = Reg(Vec(numLdqEntries, Bool())) val ldq_uop = Reg(Vec(numLdqEntries, new MicroOp)) val ldq_addr = Reg(Vec(numLdqEntries, Valid(UInt(coreMaxAddrBits.W)))) val ldq_addr_is_virtual = Reg(Vec(numLdqEntries, Bool())) val ldq_addr_is_uncacheable = Reg(Vec(numLdqEntries, Bool())) val ldq_executed = Reg(Vec(numLdqEntries, Bool())) val ldq_succeeded = Reg(Vec(numLdqEntries, Bool())) val ldq_order_fail = Reg(Vec(numLdqEntries, Bool())) val ldq_observed = Reg(Vec(numLdqEntries, Bool())) val ldq_st_dep_mask = Reg(Vec(numLdqEntries, UInt(numStqEntries.W))) val ldq_ld_byte_mask = Reg(Vec(numLdqEntries, UInt(8.W))) val ldq_forward_std_val = Reg(Vec(numLdqEntries, Bool())) val ldq_forward_stq_idx = Reg(Vec(numLdqEntries, UInt(stqAddrSz.W))) val ldq_debug_wb_data = Reg(Vec(numLdqEntries, UInt(xLen.W))) def ldq_read(idx: UInt): Valid[LDQEntry] = { val e = Wire(Valid(new LDQEntry)) e.valid := ldq_valid (idx) e.bits.uop := ldq_uop (idx) e.bits.addr := ldq_addr (idx) e.bits.addr_is_virtual := ldq_addr_is_virtual (idx) e.bits.addr_is_uncacheable := ldq_addr_is_uncacheable(idx) e.bits.executed := ldq_executed (idx) e.bits.succeeded := ldq_succeeded (idx) e.bits.order_fail := ldq_order_fail (idx) e.bits.observed := ldq_observed (idx) e.bits.st_dep_mask := ldq_st_dep_mask (idx) e.bits.ld_byte_mask := ldq_ld_byte_mask (idx) e.bits.forward_std_val := ldq_forward_std_val (idx) e.bits.forward_stq_idx := ldq_forward_stq_idx (idx) e.bits.debug_wb_data := ldq_debug_wb_data (idx) e } //val stq = Reg(Vec(numStqEntries, Valid(new STQEntry))) val stq_valid = Reg(Vec(numStqEntries, Bool())) val stq_uop = Reg(Vec(numStqEntries, new MicroOp)) val stq_addr = Reg(Vec(numStqEntries, Valid(UInt(coreMaxAddrBits.W)))) val stq_addr_is_virtual = Reg(Vec(numStqEntries, Bool())) val stq_data = Reg(Vec(numStqEntries, Valid(UInt(xLen.W)))) val stq_committed = Reg(Vec(numStqEntries, Bool())) val stq_succeeded = Reg(Vec(numStqEntries, Bool())) val stq_can_execute = Reg(Vec(numStqEntries, Bool())) val stq_cleared = Reg(Vec(numStqEntries, Bool())) val stq_debug_wb_data = Reg(Vec(numStqEntries, UInt(xLen.W))) def stq_read(idx: UInt): Valid[STQEntry] = { val e = Wire(Valid(new STQEntry)) e.valid := stq_valid (idx) e.bits.uop := stq_uop (idx) e.bits.addr := stq_addr (idx) e.bits.addr_is_virtual := stq_addr_is_virtual (idx) e.bits.data := stq_data (idx) e.bits.committed := stq_committed (idx) e.bits.succeeded := stq_succeeded (idx) e.bits.can_execute := stq_can_execute (idx) e.bits.cleared := stq_cleared (idx) e.bits.debug_wb_data := stq_debug_wb_data (idx) e } val ldq_head = Reg(UInt(ldqAddrSz.W)) val ldq_tail = Reg(UInt(ldqAddrSz.W)) val stq_head = Reg(UInt(stqAddrSz.W)) // point to next store to clear from STQ (i.e., send to memory) val stq_tail = Reg(UInt(stqAddrSz.W)) val stq_commit_head = Reg(UInt(stqAddrSz.W)) // point to next store to commit val stq_execute_head = Reg(UInt(stqAddrSz.W)) // point to next store to execute val h_ready :: h_s1 :: h_s2 :: h_s2_nack :: h_wait :: h_replay :: h_dead :: Nil = Enum(7) // s1 : do TLB, if success and not killed, fire request go to h_s2 // store s1_data to register // if tlb miss, go to s2_nack // if don't get TLB, go to s2_nack // store tlb xcpt // s2 : If kill, go to dead // If tlb xcpt, send tlb xcpt, go to dead // s2_nack : send nack, go to dead // wait : wait for response, if nack, go to replay // replay : refire request, use already translated address // dead : wait for response, ignore it val hella_state = RegInit(h_ready) val hella_req = Reg(new rocket.HellaCacheReq) val hella_data = Reg(new rocket.HellaCacheWriteData) val hella_paddr = Reg(UInt(paddrBits.W)) val hella_xcpt = Reg(new rocket.HellaCacheExceptions) val dtlb = Module(new NBDTLB( instruction = false, lgMaxSize = log2Ceil(coreDataBytes), rocket.TLBConfig(dcacheParams.nTLBSets, dcacheParams.nTLBWays))) io.ptw <> dtlb.io.ptw io.core.perf.tlbMiss := io.ptw.req.fire io.core.perf.acquire := io.dmem.perf.acquire io.core.perf.release := io.dmem.perf.release val clear_store = WireInit(false.B) def widthMap[T <: Data](f: Int => T) = VecInit((0 until lsuWidth).map(f)) // default connection from flip flop to next state val ldq_will_succeed = WireDefault(ldq_succeeded) ldq_succeeded := ldq_will_succeed //------------------------------------------------------------- //------------------------------------------------------------- // Enqueue new entries //------------------------------------------------------------- //------------------------------------------------------------- // This is a newer store than existing loads, so clear the bit in all the store dependency masks for (i <- 0 until numLdqEntries) { when (clear_store) { ldq_st_dep_mask(i) := ldq_st_dep_mask(i) & ~(1.U << stq_head) } } // Decode stage var ld_enq_idx = ldq_tail var st_enq_idx = stq_tail val dis_ldq_oh = Reg(Vec(numLdqEntries, Bool())) val dis_stq_oh = Reg(Vec(numStqEntries, Bool())) dis_ldq_oh := 0.U(numLdqEntries.W).asBools dis_stq_oh := 0.U(numStqEntries.W).asBools val dis_uops = Reg(Vec(coreWidth, Valid(new MicroOp))) val live_store_mask = stq_valid.asUInt | dis_stq_oh.asUInt var next_live_store_mask = Mux(clear_store, live_store_mask & ~(1.U << stq_head), live_store_mask) var ldq_tail_oh = UIntToOH(ldq_tail)(numLdqEntries-1,0) val ldq_valids = ldq_valid.asUInt | dis_ldq_oh.asUInt var stq_tail_oh = UIntToOH(stq_tail)(numStqEntries-1,0) val stq_valids = stq_valid.asUInt | dis_stq_oh.asUInt val stq_nonempty = stq_valid.reduce(_||_) for (w <- 0 until coreWidth) { val ldq_full = (ldq_tail_oh & ldq_valids).orR io.core.ldq_full(w) := ldq_full io.core.dis_ldq_idx(w) := ld_enq_idx val stq_full = (stq_tail_oh & stq_valids).orR io.core.stq_full(w) := stq_full io.core.dis_stq_idx(w) := st_enq_idx val dis_ld_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_ldq && !io.core.dis_uops(w).bits.exception val dis_st_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_stq && !io.core.dis_uops(w).bits.exception dis_uops(w).valid := dis_ld_val || dis_st_val dis_uops(w).bits := io.core.dis_uops(w).bits when (dis_ld_val) { dis_ldq_oh(ld_enq_idx) := true.B ldq_st_dep_mask(ld_enq_idx) := next_live_store_mask assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, "[lsu] mismatch enq load tag.") assert (!ldq_valid(ld_enq_idx), "[lsu] Enqueuing uop is overwriting ldq entries") } when (dis_st_val) { dis_stq_oh(st_enq_idx) := true.B assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, "[lsu] mismatch enq store tag.") assert (!stq_valid(st_enq_idx), "[lsu] Enqueuing uop is overwriting stq entries") } when (dis_uops(w).valid && dis_uops(w).bits.uses_ldq) { val ldq_idx = dis_uops(w).bits.ldq_idx ldq_valid (ldq_idx) := !IsKilledByBranch(io.core.brupdate, io.core.exception, dis_uops(w).bits) ldq_uop (ldq_idx) := UpdateBrMask(io.core.brupdate, dis_uops(w).bits) ldq_addr (ldq_idx).valid := false.B ldq_executed (ldq_idx) := false.B ldq_will_succeed (ldq_idx) := false.B ldq_order_fail (ldq_idx) := false.B ldq_observed (ldq_idx) := false.B ldq_forward_std_val(ldq_idx) := false.B } when (dis_uops(w).valid && dis_uops(w).bits.uses_stq) { val stq_idx = dis_uops(w).bits.stq_idx stq_valid (stq_idx) := !IsKilledByBranch(io.core.brupdate, io.core.exception, dis_uops(w).bits) stq_uop (stq_idx) := UpdateBrMask(io.core.brupdate, dis_uops(w).bits) stq_addr (stq_idx).valid := false.B stq_data (stq_idx).valid := false.B stq_committed (stq_idx) := false.B stq_can_execute (stq_idx) := false.B stq_succeeded (stq_idx) := false.B stq_cleared (stq_idx) := false.B } ld_enq_idx = Mux(dis_ld_val, WrapInc(ld_enq_idx, numLdqEntries), ld_enq_idx) next_live_store_mask = Mux(dis_st_val, next_live_store_mask | (1.U << st_enq_idx), next_live_store_mask) st_enq_idx = Mux(dis_st_val, WrapInc(st_enq_idx, numStqEntries), st_enq_idx) assert(!(dis_ld_val && dis_st_val), "A UOP is trying to go into both the LDQ and the STQ") ldq_tail_oh = Mux((io.core.dis_uops(w).bits.uses_ldq && !io.core.dis_uops(w).bits.exception) || !enableCompactingLSUDuringDispatch.B, RotateL1(ldq_tail_oh), ldq_tail_oh) stq_tail_oh = Mux((io.core.dis_uops(w).bits.uses_stq && !io.core.dis_uops(w).bits.exception) || !enableCompactingLSUDuringDispatch.B, RotateL1(stq_tail_oh), stq_tail_oh) } ldq_tail := ld_enq_idx stq_tail := st_enq_idx // If we got a mispredict, the tail will be misaligned for 1 extra cycle assert (io.core.brupdate.b2.mispredict || stq_valid(stq_execute_head) || dis_stq_oh(stq_execute_head) || stq_head === stq_execute_head || stq_tail === stq_execute_head, "stq_execute_head got off track.") io.dmem.force_order := io.core.fence_dmem io.core.fencei_rdy := !stq_nonempty && io.dmem.ordered //------------------------------------------------------------- //------------------------------------------------------------- // Execute stage (access TLB, send requests to Memory) //------------------------------------------------------------- //------------------------------------------------------------- // We can only report 1 exception per cycle. // Just be sure to report the youngest one val mem_xcpt_valid = Wire(Bool()) val mem_xcpt_cause = Wire(UInt()) val mem_xcpt_uop = Wire(new MicroOp) val mem_xcpt_vaddr = Wire(UInt()) //--------------------------------------- // Can-fire logic and wakeup/retry select // // First we determine what operations are waiting to execute. // These are the "can_fire"/"will_fire" signals val will_fire_load_agen_exec = Wire(Vec(lsuWidth, Bool())) val will_fire_load_agen = Wire(Vec(lsuWidth, Bool())) val will_fire_store_agen = Wire(Vec(lsuWidth, Bool())) val will_fire_sfence = Wire(Vec(lsuWidth, Bool())) val will_fire_hella_incoming = Wire(Vec(lsuWidth, Bool())) val will_fire_hella_wakeup = Wire(Vec(lsuWidth, Bool())) val will_fire_release = Wire(Vec(lsuWidth, Bool())) val will_fire_load_retry = Wire(Vec(lsuWidth, Bool())) val will_fire_store_retry = Wire(Vec(lsuWidth, Bool())) val will_fire_store_commit_fast = Wire(Vec(lsuWidth, Bool())) val will_fire_store_commit_slow = Wire(Vec(lsuWidth, Bool())) val will_fire_load_wakeup = Wire(Vec(lsuWidth, Bool())) val agen = io.core.agen // ------------------------------- // Assorted signals for scheduling // Don't wakeup a load if we just sent it last cycle or two cycles ago // The block_load_mask may be wrong, but the executing_load mask must be accurate val block_load_mask = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) val p1_block_load_mask = RegNext(block_load_mask) val p2_block_load_mask = RegNext(p1_block_load_mask) // Prioritize emptying the store queue when it is almost full val stq_tail_plus = WrapAdd(stq_tail, (2*coreWidth).U, numStqEntries) val stq_almost_full = RegNext(IsOlder(stq_head, stq_tail_plus, stq_tail)) // The store at the commit head needs the DCache to appear ordered // Delay firing load wakeups and retries now val store_needs_order = WireInit(false.B) val ldq_incoming_idx = widthMap(i => agen(i).bits.uop.ldq_idx) val ldq_incoming_e = widthMap(i => WireInit(ldq_read(ldq_incoming_idx(i)))) val stq_incoming_idx = widthMap(i => agen(i).bits.uop.stq_idx) val stq_incoming_e = widthMap(i => WireInit(stq_read(stq_incoming_idx(i)))) val ldq_wakeup_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i=> { val block = block_load_mask(i) || p1_block_load_mask(i) ldq_addr(i).valid && !ldq_executed(i) && !ldq_succeeded(i) && !ldq_addr_is_virtual(i) && !block }), ldq_head)) val ldq_wakeup_e = WireInit(ldq_read(ldq_wakeup_idx)) // Enqueue into the retry queue val ldq_enq_retry_idx = Reg(UInt(ldqAddrSz.W)) ldq_enq_retry_idx := AgePriorityEncoder((0 until numLdqEntries).map(i => { ldq_addr(i).valid && ldq_addr_is_virtual(i) && (i.U =/= ldq_enq_retry_idx) }), ldq_head) val ldq_enq_retry_e = WireInit(ldq_read(ldq_enq_retry_idx)) val stq_enq_retry_idx = Reg(UInt(stqAddrSz.W)) stq_enq_retry_idx := AgePriorityEncoder((0 until numStqEntries).map(i => { stq_addr(i).valid && stq_addr_is_virtual(i) && (i.U =/= stq_enq_retry_idx) }), stq_commit_head) val stq_enq_retry_e = WireInit(stq_read(stq_enq_retry_idx)) val can_enq_load_retry = (ldq_enq_retry_e.valid && ldq_enq_retry_e.bits.addr.valid && ldq_enq_retry_e.bits.addr_is_virtual) val can_enq_store_retry = (stq_enq_retry_e.valid && stq_enq_retry_e.bits.addr.valid && stq_enq_retry_e.bits.addr_is_virtual) val retry_queue = Module(new BranchKillableQueue(new MemGen, 8)) retry_queue.io.brupdate := io.core.brupdate retry_queue.io.flush := io.core.exception retry_queue.io.enq.valid := can_enq_store_retry || can_enq_load_retry retry_queue.io.enq.bits := DontCare retry_queue.io.enq.bits.data := Mux(can_enq_store_retry, stq_enq_retry_e.bits.addr.bits, ldq_enq_retry_e.bits.addr.bits) retry_queue.io.enq.bits.uop := Mux(can_enq_store_retry, stq_enq_retry_e.bits.uop , ldq_enq_retry_e.bits.uop) retry_queue.io.enq.bits.uop.uses_ldq := can_enq_load_retry && !can_enq_store_retry retry_queue.io.enq.bits.uop.ldq_idx := ldq_enq_retry_idx retry_queue.io.enq.bits.uop.uses_stq := can_enq_store_retry retry_queue.io.enq.bits.uop.stq_idx := stq_enq_retry_idx when (can_enq_store_retry && retry_queue.io.enq.fire) { stq_addr(stq_enq_retry_idx).valid := false.B } .elsewhen (can_enq_load_retry && retry_queue.io.enq.fire) { ldq_addr(ldq_enq_retry_idx).valid := false.B } val ldq_retry_idx = retry_queue.io.deq.bits.uop.ldq_idx val stq_retry_idx = retry_queue.io.deq.bits.uop.stq_idx retry_queue.io.deq.ready := will_fire_load_retry.reduce(_||_) || will_fire_store_retry.reduce(_||_) val stq_execute_queue_flush = WireInit(false.B) val stq_execute_queue = withReset(reset.asBool || stq_execute_queue_flush) { Module(new Queue(new STQEntry, 4)) } val stq_commit_e = stq_execute_queue.io.deq val stq_enq_e = WireInit(stq_read(stq_execute_head)) stq_execute_queue.io.enq.bits := stq_enq_e.bits stq_execute_queue.io.enq.bits.uop.stq_idx := stq_execute_head stq_execute_queue.io.deq.ready := will_fire_store_commit_fast.reduce(_||_) || will_fire_store_commit_slow.reduce(_||_) val can_enq_store_execute = ( stq_enq_e.valid && stq_enq_e.bits.addr.valid && stq_enq_e.bits.data.valid && !stq_enq_e.bits.addr_is_virtual && !stq_enq_e.bits.uop.exception && !stq_enq_e.bits.uop.is_fence && (stq_enq_e.bits.committed || stq_enq_e.bits.uop.is_amo) ) stq_execute_queue.io.enq.valid := can_enq_store_execute when (can_enq_store_execute && stq_execute_queue.io.enq.fire) { stq_execute_head := WrapInc(stq_execute_head, numStqEntries) } // ----------------------- // Determine what can fire // Can we fire a incoming load val can_fire_load_agen_exec = widthMap(w => agen(w).valid && agen(w).bits.uop.uses_ldq) val can_fire_load_agen = can_fire_load_agen_exec // Can we fire an incoming store addrgen + store datagen val can_fire_store_agen = widthMap(w => agen(w).valid && agen(w).bits.uop.uses_stq) // Can we fire an incoming sfence val can_fire_sfence = widthMap(w => io.core.sfence.valid) // Can we fire a request from dcache to release a line // This needs to go through LDQ search to mark loads as dangerous val can_fire_release = widthMap(w => (w == lsuWidth-1).B && io.dmem.release.valid) io.dmem.release.ready := will_fire_release.reduce(_||_) // Can we retry a load that missed in the TLB val can_fire_load_retry = widthMap(w => ( retry_queue.io.deq.valid && retry_queue.io.deq.bits.uop.uses_ldq && !RegNext(store_needs_order) && (w == lsuWidth-1).B)) // Can we retry a store addrgen that missed in the TLB val can_fire_store_retry = widthMap(w => ( retry_queue.io.deq.valid && retry_queue.io.deq.bits.uop.uses_stq && (w == lsuWidth-1).B)) // Can we commit a store val can_fire_store_commit_slow = widthMap(w => ( stq_commit_e.valid && !mem_xcpt_valid && (w == 0).B)) val can_fire_store_commit_fast = widthMap(w => can_fire_store_commit_slow(w) && stq_almost_full) // Can we wakeup a load that was nack'd val block_load_wakeup = WireInit(false.B) val can_fire_load_wakeup = widthMap(w => ( ldq_wakeup_e.valid && ldq_wakeup_e.bits.addr.valid && !ldq_wakeup_e.bits.succeeded && !ldq_wakeup_e.bits.addr_is_virtual && !ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.order_fail && !p1_block_load_mask(ldq_wakeup_idx) && !p2_block_load_mask(ldq_wakeup_idx) && !RegNext(store_needs_order) && !block_load_wakeup && (w == lsuWidth-1).B && (!ldq_wakeup_e.bits.addr_is_uncacheable || (io.core.commit_load_at_rob_head && ldq_head === ldq_wakeup_idx && ldq_wakeup_e.bits.st_dep_mask.asUInt === 0.U)))) // Can we fire an incoming hellacache request val can_fire_hella_incoming = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim ocntroller // Can we fire a hellacache request that the dcache nack'd val can_fire_hella_wakeup = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim controller //--------------------------------------------------------- // Controller logic. Arbitrate which request actually fires val exe_tlb_valid = Wire(Vec(lsuWidth, Bool())) for (w <- 0 until lsuWidth) { var tlb_avail = true.B var dc_avail = true.B var lcam_avail = true.B def lsu_sched(can_fire: Bool, uses_tlb:Boolean, uses_dc:Boolean, uses_lcam: Boolean): Bool = { val will_fire = can_fire && !(uses_tlb.B && !tlb_avail) && !(uses_lcam.B && !lcam_avail) && !(uses_dc.B && !dc_avail) tlb_avail = tlb_avail && !(will_fire && uses_tlb.B) lcam_avail = lcam_avail && !(will_fire && uses_lcam.B) dc_avail = dc_avail && !(will_fire && uses_dc.B) dontTouch(will_fire) // dontTouch these so we can inspect the will_fire signals will_fire } // The order of these statements is the priority // Some restrictions // - Incoming ops must get precedence, can't backpresure memaddrgen // - Incoming hellacache ops must get precedence over retrying ops (PTW must get precedence over retrying translation) // Notes on performance // - Prioritize releases, this speeds up cache line writebacks and refills // - Store commits are lowest priority, since they don't "block" younger instructions unless stq fills up will_fire_sfence (w) := lsu_sched(can_fire_sfence (w) , true , false, false) // TLB , , will_fire_store_commit_fast(w) := lsu_sched(can_fire_store_commit_fast(w) , false, true , false) // , DC If store queue is filling up, prioritize draining it will_fire_load_agen_exec (w) := lsu_sched(can_fire_load_agen_exec (w) , true , true , true ) // TLB , DC , LCAM Normally fire loads as soon as translation completes will_fire_load_agen (w) := lsu_sched(can_fire_load_agen (w) , true , false, true ) // TLB , , LCAM If we are draining stores, still translate the loads will_fire_store_agen (w) := lsu_sched(can_fire_store_agen (w) , true , false, true ) // TLB , , LCAM will_fire_release (w) := lsu_sched(can_fire_release (w) , false, false, true ) // LCAM will_fire_hella_incoming (w) := lsu_sched(can_fire_hella_incoming (w) , true , true , false) // TLB , DC will_fire_hella_wakeup (w) := lsu_sched(can_fire_hella_wakeup (w) , false, true , false) // , DC will_fire_store_retry (w) := lsu_sched(can_fire_store_retry (w) , true , false, true ) // TLB , , LCAM will_fire_load_retry (w) := lsu_sched(can_fire_load_retry (w) , true , true , true ) // TLB , DC , LCAM will_fire_load_wakeup (w) := lsu_sched(can_fire_load_wakeup (w) , false, true , true ) // , DC , LCAM will_fire_store_commit_slow(w) := lsu_sched(can_fire_store_commit_slow(w) , false, true , false) // , DC assert(!(agen(w).valid && !(will_fire_load_agen_exec(w) || will_fire_load_agen(w) || will_fire_store_agen(w)))) when (will_fire_load_wakeup(w)) { block_load_mask(ldq_wakeup_idx) := true.B } .elsewhen (will_fire_load_agen(w) || will_fire_load_agen_exec(w)) { block_load_mask(agen(w).bits.uop.ldq_idx) := true.B } .elsewhen (will_fire_load_retry(w)) { block_load_mask(ldq_retry_idx) := true.B } exe_tlb_valid(w) := !tlb_avail } assert((lsuWidth == 1).B || (!will_fire_hella_incoming.reduce(_&&_) && !will_fire_hella_wakeup.reduce(_&&_) && !will_fire_load_retry.reduce(_&&_) && !will_fire_store_retry.reduce(_&&_) && !will_fire_store_commit_fast.reduce(_&&_) && !will_fire_store_commit_slow.reduce(_&&_) && !will_fire_load_wakeup.reduce(_&&_)), "Some operations is proceeding down multiple pipes") require(lsuWidth <= 2) //-------------------------------------------- // TLB Access assert(!(hella_state =/= h_ready && hella_req.cmd === rocket.M_SFENCE), "SFENCE through hella interface not supported") val exe_tlb_uop = widthMap(w => Mux(will_fire_load_agen_exec(w) || will_fire_load_agen (w) , ldq_incoming_e(w).bits.uop, Mux(will_fire_store_agen (w) , stq_incoming_e(w).bits.uop, Mux(will_fire_load_retry (w) || will_fire_store_retry (w) , retry_queue.io.deq.bits.uop, Mux(will_fire_hella_incoming(w) , 0.U.asTypeOf(new MicroOp), 0.U.asTypeOf(new MicroOp)))))) val exe_tlb_vaddr = widthMap(w => Mux(will_fire_load_agen_exec(w) || will_fire_load_agen (w) || will_fire_store_agen (w) , agen(w).bits.data, Mux(will_fire_sfence (w) , io.core.sfence.bits.addr, Mux(will_fire_load_retry (w) || will_fire_store_retry (w) , retry_queue.io.deq.bits.data, Mux(will_fire_hella_incoming(w) , hella_req.addr, 0.U))))) val exe_sfence = io.core.sfence val exe_size = widthMap(w => Mux(will_fire_load_agen_exec(w) || will_fire_load_agen (w) || will_fire_store_agen (w) || will_fire_load_retry (w) || will_fire_store_retry (w) , exe_tlb_uop(w).mem_size, Mux(will_fire_hella_incoming(w) , hella_req.size, 0.U))) val exe_cmd = widthMap(w => Mux(will_fire_load_agen_exec(w) || will_fire_load_agen (w) || will_fire_store_agen (w) || will_fire_load_retry (w) || will_fire_store_retry (w) , exe_tlb_uop(w).mem_cmd, Mux(will_fire_hella_incoming(w) , hella_req.cmd, Mux(will_fire_sfence (w) , rocket.M_SFENCE, 0.U)))) val exe_passthr= widthMap(w => Mux(will_fire_hella_incoming(w) , hella_req.phys, false.B)) val exe_kill = widthMap(w => Mux(will_fire_hella_incoming(w) , io.hellacache.s1_kill, false.B)) val bkptu = Seq.fill(lsuWidth) { Module(new rocket.BreakpointUnit(nBreakpoints)) } for (w <- 0 until lsuWidth) { dtlb.io.req(w).valid := exe_tlb_valid(w) dtlb.io.req(w).bits.vaddr := exe_tlb_vaddr(w) dtlb.io.req(w).bits.size := exe_size(w) dtlb.io.req(w).bits.cmd := exe_cmd(w) dtlb.io.req(w).bits.passthrough := exe_passthr(w) dtlb.io.req(w).bits.prv := io.ptw.status.prv dtlb.io.req(w).bits.v := io.ptw.status.v bkptu(w).io.status := io.core.status bkptu(w).io.bp := io.core.bp bkptu(w).io.pc := DontCare bkptu(w).io.ea := exe_tlb_vaddr(w) bkptu(w).io.mcontext := io.core.mcontext bkptu(w).io.scontext := io.core.scontext } dtlb.io.kill := exe_kill.reduce(_||_) dtlb.io.sfence := exe_sfence // exceptions val ma_ld = widthMap(w => dtlb.io.resp(w).ma.ld && exe_tlb_uop(w).uses_ldq) val ma_st = widthMap(w => dtlb.io.resp(w).ma.st && exe_tlb_uop(w).uses_stq && !exe_tlb_uop(w).is_fence) val pf_ld = widthMap(w => dtlb.io.resp(w).pf.ld && exe_tlb_uop(w).uses_ldq) val pf_st = widthMap(w => dtlb.io.resp(w).pf.st && exe_tlb_uop(w).uses_stq) val ae_ld = widthMap(w => dtlb.io.resp(w).ae.ld && exe_tlb_uop(w).uses_ldq) val ae_st = widthMap(w => dtlb.io.resp(w).ae.st && exe_tlb_uop(w).uses_stq) val dbg_bp = widthMap(w => bkptu(w).io.debug_st && ((exe_tlb_uop(w).uses_ldq && bkptu(w).io.debug_ld) || (exe_tlb_uop(w).uses_stq && bkptu(w).io.debug_st && !exe_tlb_uop(w).is_fence))) val bp = widthMap(w => bkptu(w).io.debug_st && ((exe_tlb_uop(w).uses_ldq && bkptu(w).io.xcpt_ld) || (exe_tlb_uop(w).uses_stq && bkptu(w).io.xcpt_st && !exe_tlb_uop(w).is_fence))) // TODO check for xcpt_if and verify that never happens on non-speculative instructions. val mem_xcpt_valids = RegNext(widthMap(w => exe_tlb_valid(w) && (pf_ld(w) || pf_st(w) || ae_ld(w) || ae_st(w) || ma_ld(w) || ma_st(w) || dbg_bp(w) || bp(w)) && !IsKilledByBranch(io.core.brupdate, io.core.exception, exe_tlb_uop(w)))) val mem_xcpt_uops = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_tlb_uop(w)))) val mem_xcpt_causes = RegNext(widthMap(w => Mux(dbg_bp(w), rocket.CSR.debugTriggerCause.U, Mux(bp (w), rocket.Causes.breakpoint.U, Mux(ma_st (w), rocket.Causes.misaligned_store.U, Mux(ma_ld (w), rocket.Causes.misaligned_load.U, Mux(pf_st (w), rocket.Causes.store_page_fault.U, Mux(pf_ld (w), rocket.Causes.load_page_fault.U, Mux(ae_st (w), rocket.Causes.store_access.U, Mux(ae_ld (w), rocket.Causes.load_access.U, 0.U)))))))))) val mem_xcpt_vaddrs = RegNext(exe_tlb_vaddr) for (w <- 0 until lsuWidth) { assert (!(dtlb.io.req(w).valid && exe_tlb_uop(w).is_fence), "Fence is pretending to talk to the TLB") } mem_xcpt_valid := mem_xcpt_valids.reduce(_||_) mem_xcpt_cause := mem_xcpt_causes(0) mem_xcpt_uop := mem_xcpt_uops(0) mem_xcpt_vaddr := mem_xcpt_vaddrs(0) var xcpt_found = mem_xcpt_valids(0) var oldest_xcpt_rob_idx = mem_xcpt_uops(0).rob_idx for (w <- 1 until lsuWidth) { val is_older = WireInit(false.B) when (mem_xcpt_valids(w) && (IsOlder(mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx, io.core.rob_head_idx) || !xcpt_found)) { is_older := true.B mem_xcpt_cause := mem_xcpt_causes(w) mem_xcpt_uop := mem_xcpt_uops(w) mem_xcpt_vaddr := mem_xcpt_vaddrs(w) } xcpt_found = xcpt_found || mem_xcpt_valids(w) oldest_xcpt_rob_idx = Mux(is_older, mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx) } val exe_tlb_miss = widthMap(w => dtlb.io.req(w).valid && (dtlb.io.resp(w).miss || !dtlb.io.req(w).ready)) val exe_tlb_paddr = widthMap(w => Cat(dtlb.io.resp(w).paddr(paddrBits-1,corePgIdxBits), exe_tlb_vaddr(w)(corePgIdxBits-1,0))) val exe_tlb_uncacheable = widthMap(w => !(dtlb.io.resp(w).cacheable)) for (w <- 0 until lsuWidth) { assert (exe_tlb_paddr(w) === dtlb.io.resp(w).paddr, "[lsu] paddrs should match.") when (mem_xcpt_valids(w)) { assert(RegNext(will_fire_load_agen_exec(w) || will_fire_load_agen(w) || will_fire_store_agen(w) || will_fire_load_retry(w) || will_fire_store_retry(w))) // Technically only faulting AMOs need this assert(mem_xcpt_uops(w).uses_ldq ^ mem_xcpt_uops(w).uses_stq) when (mem_xcpt_uops(w).uses_ldq) { ldq_uop(mem_xcpt_uops(w).ldq_idx).exception := true.B } .otherwise { stq_uop(mem_xcpt_uops(w).stq_idx).exception := true.B } } } val exe_agen_killed = widthMap(w => IsKilledByBranch(io.core.brupdate, io.core.exception, agen(w).bits.uop)) //------------------------------ // Issue Someting to Memory // // A memory op can come from many different places // The address either was freshly translated, or we are // reading a physical address from the LDQ,STQ, or the HellaCache adapter // defaults io.dmem.brupdate := io.core.brupdate io.dmem.exception := io.core.exception io.dmem.rob_head_idx := io.core.rob_head_idx io.dmem.rob_pnr_idx := io.core.rob_pnr_idx val dmem_req = Wire(Vec(lsuWidth, Valid(new BoomDCacheReq))) io.dmem.req.valid := dmem_req.map(_.valid).reduce(_||_) io.dmem.req.bits := dmem_req val dmem_req_fire = widthMap(w => dmem_req(w).valid && io.dmem.req.fire) val s0_executing_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) val s0_kills = Wire(Vec(lsuWidth, Bool())) for (w <- 0 until lsuWidth) { dmem_req(w).valid := false.B dmem_req(w).bits.uop := NullMicroOp dmem_req(w).bits.addr := 0.U dmem_req(w).bits.data := 0.U dmem_req(w).bits.is_hella := false.B s0_kills(w) := false.B io.dmem.s1_kill(w) := RegNext(s0_kills(w) && dmem_req_fire(w)) when (will_fire_load_agen_exec(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.uop := exe_tlb_uop(w) s0_kills(w) := exe_tlb_miss(w) || exe_tlb_uncacheable(w) || ma_ld(w) || ae_ld(w) || pf_ld(w) s0_executing_loads(ldq_incoming_idx(w)) := dmem_req_fire(w) && !s0_kills(w) assert(!ldq_incoming_e(w).bits.executed) } .elsewhen (will_fire_load_retry(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.uop := exe_tlb_uop(w) s0_kills(w) := exe_tlb_miss(w) || exe_tlb_uncacheable(w) || ma_ld(w) || ae_ld(w) || pf_ld(w) s0_executing_loads(ldq_retry_idx) := dmem_req_fire(w) && !s0_kills(w) } .elsewhen (will_fire_store_commit_slow(w) || will_fire_store_commit_fast(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := stq_commit_e.bits.addr.bits dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( stq_commit_e.bits.uop.mem_size, 0.U, stq_commit_e.bits.data.bits, coreDataBytes)).data dmem_req(w).bits.uop := stq_commit_e.bits.uop when (!dmem_req_fire(w)) { stq_execute_queue_flush := true.B stq_execute_head := stq_commit_e.bits.uop.stq_idx } stq_succeeded(stq_commit_e.bits.uop.stq_idx) := false.B } .elsewhen (will_fire_load_wakeup(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := ldq_wakeup_e.bits.addr.bits dmem_req(w).bits.uop := ldq_wakeup_e.bits.uop s0_executing_loads(ldq_wakeup_idx) := dmem_req_fire(w) assert(!ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.addr_is_virtual) } .elsewhen (will_fire_hella_incoming(w)) { assert(hella_state === h_s1) dmem_req(w).valid := !io.hellacache.s1_kill && (!exe_tlb_miss(w) || hella_req.phys) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( hella_req.size, 0.U, io.hellacache.s1_data.data, coreDataBytes)).data dmem_req(w).bits.uop.mem_cmd := hella_req.cmd dmem_req(w).bits.uop.mem_size := hella_req.size dmem_req(w).bits.uop.mem_signed := hella_req.signed dmem_req(w).bits.is_hella := true.B hella_paddr := exe_tlb_paddr(w) } .elsewhen (will_fire_hella_wakeup(w)) { assert(hella_state === h_replay) dmem_req(w).valid := true.B dmem_req(w).bits.addr := hella_paddr dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( hella_req.size, 0.U, hella_data.data, coreDataBytes)).data dmem_req(w).bits.uop.mem_cmd := hella_req.cmd dmem_req(w).bits.uop.mem_size := hella_req.size dmem_req(w).bits.uop.mem_signed := hella_req.signed dmem_req(w).bits.is_hella := true.B } //------------------------------------------------------------- // Write Addr into the LAQ/SAQ when (will_fire_load_agen(w) || will_fire_load_agen_exec(w) || will_fire_load_retry(w)) { val ldq_idx = Mux(will_fire_load_agen(w) || will_fire_load_agen_exec(w), ldq_incoming_idx(w), ldq_retry_idx) ldq_addr (ldq_idx).valid := !exe_agen_killed(w) || will_fire_load_retry(w) ldq_addr (ldq_idx).bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w)) ldq_ld_byte_mask (ldq_idx) := GenByteMask(exe_tlb_vaddr(w), exe_tlb_uop(w).mem_size) ldq_uop (ldq_idx).pdst := exe_tlb_uop(w).pdst ldq_addr_is_virtual (ldq_idx) := exe_tlb_miss(w) ldq_addr_is_uncacheable(ldq_idx) := exe_tlb_uncacheable(w) && !exe_tlb_miss(w) assert(!ldq_addr(ldq_idx).valid, "[lsu] Translating load is overwriting a valid address") } when (will_fire_store_agen(w) || will_fire_store_retry(w)) { val stq_idx = Mux(will_fire_store_agen(w), stq_incoming_idx(w), stq_retry_idx) stq_addr (stq_idx).valid := (!exe_agen_killed(w) || will_fire_store_retry(w)) && !pf_st(w) // Prevent AMOs from executing! stq_addr (stq_idx).bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w)) stq_uop (stq_idx).pdst := exe_tlb_uop(w).pdst // Needed for AMOs stq_addr_is_virtual(stq_idx) := exe_tlb_miss(w) assert(!stq_addr(stq_idx).valid, "[lsu] Translating store is overwriting a valid address") } } //------------------------------------------------------------- // Write data into the STQ for (dgen <- io.core.dgen) { when (dgen.valid) { val sidx = dgen.bits.uop.stq_idx //val stq_e = WireInit(stq(sidx)) stq_data(sidx).valid := true.B stq_data(sidx).bits := dgen.bits.data assert(!stq_data(sidx).valid || (stq_data(sidx).bits === dgen.bits.data)) } } require (xLen >= fLen) // for correct SDQ size //------------------------------------------------------------- // Speculative wakeup if loadUseDelay == 4 val wakeupArbs = Seq.fill(lsuWidth) { Module(new Arbiter(new Wakeup, 2)) } for (w <- 0 until lsuWidth) { wakeupArbs(w).io.out.ready := true.B wakeupArbs(w).io.in := DontCare io.core.iwakeups(w) := wakeupArbs(w).io.out if (enableFastLoadUse) { wakeupArbs(w).io.in(1).valid := (will_fire_load_agen_exec(w) && dmem_req_fire(w) && !agen(w).bits.uop.fp_val) wakeupArbs(w).io.in(1).bits.uop := agen(w).bits.uop wakeupArbs(w).io.in(1).bits.bypassable := true.B wakeupArbs(w).io.in(1).bits.speculative_mask := 0.U wakeupArbs(w).io.in(1).bits.rebusy := false.B } } //------------------------------------------------------------- //------------------------------------------------------------- // Cache Access Cycle (Mem) //------------------------------------------------------------- //------------------------------------------------------------- // Note the DCache may not have accepted our request val fired_load_agen_exec = widthMap(w => RegNext(will_fire_load_agen_exec(w) && !exe_agen_killed(w))) val fired_load_agen = widthMap(w => RegNext(will_fire_load_agen (w) && !exe_agen_killed(w))) val fired_store_agen = widthMap(w => RegNext(will_fire_store_agen (w) && !exe_agen_killed(w))) val fired_sfence = RegNext(will_fire_sfence) val fired_release = RegNext(will_fire_release) val fired_load_retry = widthMap(w => RegNext(will_fire_load_retry (w) && !IsKilledByBranch(io.core.brupdate, io.core.exception, retry_queue.io.deq.bits.uop))) val fired_store_retry = widthMap(w => RegNext(will_fire_store_retry (w) && !IsKilledByBranch(io.core.brupdate, io.core.exception, retry_queue.io.deq.bits.uop))) val fired_store_commit = widthMap(w => RegNext(will_fire_store_commit_slow(w) || will_fire_store_commit_fast(w))) val fired_load_wakeup = widthMap(w => RegNext(will_fire_load_wakeup (w) && !IsKilledByBranch(io.core.brupdate, io.core.exception, ldq_wakeup_e.bits.uop))) val fired_hella_incoming = RegNext(will_fire_hella_incoming) val fired_hella_wakeup = RegNext(will_fire_hella_wakeup) val mem_incoming_uop = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, agen(w).bits.uop))) val mem_ldq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, io.core.exception, ldq_incoming_e(w)))) val mem_stq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, io.core.exception, stq_incoming_e(w)))) val mem_ldq_wakeup_e = RegNext(UpdateBrMask(io.core.brupdate, io.core.exception, ldq_wakeup_e)) val mem_ldq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, io.core.exception, ldq_read(ldq_retry_idx))) val mem_stq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, io.core.exception, stq_read(stq_retry_idx))) val mem_ldq_e = widthMap(w => Mux(fired_load_agen (w) || fired_load_agen_exec(w), mem_ldq_incoming_e(w), Mux(fired_load_retry (w), mem_ldq_retry_e, Mux(fired_load_wakeup (w), mem_ldq_wakeup_e, (0.U).asTypeOf(Valid(new LDQEntry)))))) val mem_stq_e = widthMap(w => Mux(fired_store_agen (w), mem_stq_incoming_e(w), Mux(fired_store_retry(w), mem_stq_retry_e, (0.U).asTypeOf(Valid(new STQEntry))))) val mem_tlb_miss = RegNext(exe_tlb_miss) val mem_tlb_uncacheable = RegNext(exe_tlb_uncacheable) val mem_paddr = RegNext(widthMap(w => dmem_req(w).bits.addr)) // Task 1: Clr ROB busy bit val stq_clr_head_idx = RegNext(AgePriorityEncoder((0 until numStqEntries).map(i => { stq_valid(i) && !stq_cleared(i) }), stq_commit_head)) var clr_idx = stq_clr_head_idx for (i <- 0 until coreWidth) { // Delay store clearing 1 extra cycle, as the store clear can't occur // too quickly before an order fail caused by this store propagates to ROB val clr_valid = Reg(Bool()) clr_valid := false.B val clr_uop = Reg(new MicroOp) val clr_valid_1 = RegNext(clr_valid && !IsKilledByBranch(io.core.brupdate, io.core.exception, clr_uop)) val clr_uop_1 = RegNext(UpdateBrMask(io.core.brupdate, clr_uop)) //val stq_e = WireInit(stq(clr_idx)) val s_uop = WireInit(stq_uop(clr_idx)) when ( stq_valid (clr_idx) && stq_addr (clr_idx).valid && stq_data (clr_idx).valid && !stq_addr_is_virtual (clr_idx) && !s_uop.is_amo && !stq_cleared (clr_idx) && !IsKilledByBranch(io.core.brupdate, io.core.exception, s_uop)) { clr_valid := true.B clr_uop := UpdateBrMask(io.core.brupdate, s_uop) stq_cleared(clr_idx) := true.B } io.core.clr_bsy(i).valid := clr_valid_1 && !IsKilledByBranch(io.core.brupdate, io.core.exception, clr_uop_1) io.core.clr_bsy(i).bits := clr_uop_1.rob_idx clr_idx = WrapInc(clr_idx, numStqEntries) } // Task 2: Do LD-LD. ST-LD searches for ordering failures // Do LD-ST search for forwarding opportunities // We have the opportunity to kill a request we sent last cycle. Use it wisely! // We translated a store last cycle val do_st_search = widthMap(w => (fired_store_agen(w) || fired_store_retry(w)) && !mem_tlb_miss(w)) // We translated a load last cycle val do_ld_search = widthMap(w => ((fired_load_agen(w) || fired_load_agen_exec(w) || fired_load_retry(w)) && !mem_tlb_miss(w)) || fired_load_wakeup(w)) // We are making a local line visible to other harts val do_release_search = widthMap(w => fired_release(w)) // Store addrs don't go to memory yet, get it from the TLB response // Load wakeups don't go through TLB, get it through memory // Load incoming and load retries go through both val lcam_addr = widthMap(w => Mux(fired_store_agen(w) || fired_store_retry(w) || fired_load_agen(w) || fired_load_agen_exec(w), RegNext(exe_tlb_paddr(w)), Mux(fired_release(w), RegNext(io.dmem.release.bits.address), mem_paddr(w)))) val lcam_uop = widthMap(w => Mux(do_st_search(w), mem_stq_e(w).bits.uop, Mux(do_ld_search(w), mem_ldq_e(w).bits.uop, NullMicroOp))) val lcam_mask = widthMap(w => GenByteMask(lcam_addr(w), lcam_uop(w).mem_size)) val lcam_st_dep_mask = widthMap(w => mem_ldq_e(w).bits.st_dep_mask) val lcam_is_release = widthMap(w => fired_release(w)) val lcam_ldq_idx = widthMap(w => Mux(fired_load_agen (w) || fired_load_agen_exec(w) , mem_incoming_uop(w).ldq_idx, Mux(fired_load_wakeup (w), RegNext(ldq_wakeup_idx), Mux(fired_load_retry (w), RegNext(ldq_retry_idx), 0.U)))) val lcam_stq_idx = widthMap(w => Mux(fired_store_agen (w), mem_incoming_uop(w).stq_idx, Mux(fired_store_retry(w), RegNext(stq_retry_idx), 0.U))) val lcam_younger_load_mask = widthMap(w => IsYoungerMask(lcam_ldq_idx(w), ldq_head, numLdqEntries)) val can_forward = widthMap(w => Mux(fired_load_agen(w) || fired_load_agen_exec(w) || fired_load_retry(w), !mem_tlb_uncacheable(w), !mem_ldq_wakeup_e.bits.addr_is_uncacheable )) val kill_forward = WireInit(widthMap(w => false.B)) // Mask of stores which we conflict on address with val ldst_addr_matches = Wire(Vec(lsuWidth, UInt(numStqEntries.W))) // Mask of stores which we can forward from val ldst_forward_matches = Wire(Vec(lsuWidth, UInt(numStqEntries.W))) // Mask of stores we can forward to val stld_prs2_matches = Wire(Vec(lsuWidth, UInt(numStqEntries.W))) val s1_executing_loads = RegNext(s0_executing_loads) val s1_set_execute = WireInit(s1_executing_loads) val wb_ldst_forward_matches = RegNext(ldst_forward_matches) val wb_ldst_forward_valid = Wire(Vec(lsuWidth, Bool())) val wb_ldst_forward_e = widthMap(w => RegNext(UpdateBrMask(io.core.brupdate, ldq_read(lcam_ldq_idx(w)).bits))) val wb_ldst_forward_ldq_idx = RegNext(lcam_ldq_idx) val wb_ldst_forward_ld_addr = RegNext(lcam_addr) val wb_ldst_forward_stq_idx = Wire(Vec(lsuWidth, UInt(stqAddrSz.W))) val failed_load = WireInit(false.B) for (i <- 0 until numLdqEntries) { // val l_bits = ldq(i).bits val l_valid = ldq_valid(i) val l_addr = ldq_addr(i) val l_addr_is_virtual = ldq_addr_is_virtual(i) val l_executed = ldq_executed(i) val l_succeeded = ldq_succeeded(i) val l_will_succeed = ldq_will_succeed(i) val l_observed = ldq_observed(i) val l_mask = ldq_ld_byte_mask(i) val l_st_dep_mask = ldq_st_dep_mask(i) val l_uop = WireInit(ldq_uop(i)) val l_forward_std_val = ldq_forward_std_val(i) val l_forward_stq_idx = ldq_forward_stq_idx(i) val block_addr_matches = widthMap(w => lcam_addr(w) >> blockOffBits === l_addr.bits >> blockOffBits) val dword_addr_matches = widthMap(w => block_addr_matches(w) && lcam_addr(w)(blockOffBits-1,3) === l_addr.bits(blockOffBits-1,3)) val mask_match = widthMap(w => (l_mask & lcam_mask(w)) === l_mask) val mask_overlap = widthMap(w => (l_mask & lcam_mask(w)).orR) // Searcher is a store for (w <- 0 until lsuWidth) { when ( do_release_search(w) && l_valid && l_addr.valid && !l_addr_is_virtual && block_addr_matches(w)) { // This load has been observed, so if a younger load to the same address has not // executed yet, this load must be squashed ldq_observed(i) := true.B } when ( do_st_search(w) && l_valid && l_addr.valid && (l_executed || l_succeeded) && !l_addr_is_virtual && l_st_dep_mask(lcam_stq_idx(w)) && dword_addr_matches(w) && mask_overlap(w)) { val forwarded_is_older = IsOlder(l_forward_stq_idx, lcam_stq_idx(w), l_uop.stq_idx) // We are older than this load, which overlapped us. when (!l_forward_std_val || // If the load wasn't forwarded, it definitely failed ((l_forward_stq_idx =/= lcam_stq_idx(w)) && forwarded_is_older)) { // If the load forwarded from us, we might be ok ldq_order_fail(i) := true.B failed_load := true.B } } when ( do_ld_search(w) && l_valid && l_addr.valid && !l_addr_is_virtual && dword_addr_matches(w) && mask_overlap(w)) { val searcher_is_older = lcam_younger_load_mask(w)(i) assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older) when (searcher_is_older) { when ((l_executed || l_succeeded) && !s1_executing_loads(i) && // If the load is proceeding in parallel we don't need to kill it l_observed) { // Its only a ordering failure if the cache line was observed between the younger load and us //ldq_order_fail(i) := true.B // failed_load := true.B // this case is no longer possible where an older search gets replayed and found that a younger search has already been released. Note that this is stronger than rvwmo. assert(false.B) } } .elsewhen (lcam_ldq_idx(w) =/= i.U) { // The load is older, and it wasn't executed // we need to kill ourselves, and prevent forwarding // can also forward from the next cycle when (!(l_executed && (l_succeeded || l_will_succeed))) { s1_set_execute(lcam_ldq_idx(w)) := false.B when (RegNext(dmem_req_fire(w) && !s0_kills(w)) && !fired_load_agen(w)) { io.dmem.s1_kill(w) := true.B } kill_forward(w) := true.B } } } } } for (wi <- 0 until lsuWidth) { for (w <- 0 until lsuWidth) { // A younger load might find a older nacking load // this is not the full case, need also to account for the situation where the older load already went to sleep above val nack_dword_addr_matches = (lcam_addr(w) >> 3) === (io.dmem.nack(wi).bits.addr >> 3) val nack_mask = GenByteMask(io.dmem.nack(wi).bits.addr, io.dmem.nack(wi).bits.uop.mem_size) val nack_mask_overlap = (nack_mask & lcam_mask(w)) =/= 0.U when (do_ld_search(w) && io.dmem.nack(wi).valid && io.dmem.nack(wi).bits.uop.uses_ldq && nack_dword_addr_matches && nack_mask_overlap && IsOlder(io.dmem.nack(wi).bits.uop.ldq_idx, lcam_ldq_idx(w), ldq_head)) { s1_set_execute(lcam_ldq_idx(w)) := false.B when (RegNext(dmem_req_fire(w) && !s0_kills(w)) && !fired_load_agen(w)) { io.dmem.s1_kill(w) := true.B } kill_forward(w) := true.B } // A older load might find a younger forwarding load val forward_dword_addr_matches = (lcam_addr(w) >> 3 === wb_ldst_forward_ld_addr(wi) >> 3) val forward_mask = GenByteMask(wb_ldst_forward_ld_addr(wi), wb_ldst_forward_e(wi).uop.mem_size) val forward_mask_overlap = (forward_mask & lcam_mask(w)) =/= 0.U when (do_ld_search(w) && wb_ldst_forward_valid(wi) && forward_dword_addr_matches && forward_mask_overlap && wb_ldst_forward_e(wi).observed && IsOlder(lcam_ldq_idx(w), wb_ldst_forward_ldq_idx(wi), ldq_head)) { ldq_order_fail(wb_ldst_forward_ldq_idx(wi)) := true.B failed_load := true.B } // A older store might find a younger load which is forwarding from the wrong place val forwarded_is_older = IsOlder(wb_ldst_forward_stq_idx(wi), lcam_stq_idx(w), wb_ldst_forward_e(wi).uop.stq_idx) when (do_st_search(w) && wb_ldst_forward_valid(wi) && forward_dword_addr_matches && forward_mask_overlap && wb_ldst_forward_e(wi).st_dep_mask(lcam_stq_idx(w)) && forwarded_is_older) { ldq_order_fail(wb_ldst_forward_ldq_idx(wi)) := true.B failed_load := true.B } } } val addr_matches = Wire(Vec(lsuWidth, Vec(numStqEntries, Bool()))) val forward_matches = Wire(Vec(lsuWidth, Vec(numStqEntries, Bool()))) val prs2_matches = Wire(Vec(lsuWidth, Vec(numStqEntries, Bool()))) for (i <- 0 until numStqEntries) { //val s_e = WireInit(stq(i)) val s_addr = stq_addr(i) val s_data = stq_data(i) val s_addr_is_virtual = stq_addr_is_virtual(i) val s_uop = WireInit(stq_uop(i)) val write_mask = GenByteMask(s_addr.bits, s_uop.mem_size) for (w <- 0 until lsuWidth) { val dword_addr_matches = ( s_addr.valid && !s_uop.is_amo && !s_addr_is_virtual && (s_addr.bits(corePAddrBits-1,3) === lcam_addr(w)(corePAddrBits-1,3))) val mask_union = lcam_mask(w) & write_mask addr_matches(w)(i) := (mask_union =/= 0.U) && dword_addr_matches forward_matches(w)(i) := addr_matches(w)(i) && s_data.valid && (mask_union === lcam_mask(w)) prs2_matches(w)(i) := (s_uop.prs2 === lcam_uop(w).pdst && s_uop.lrs2_rtype === RT_FIX && enableLoadToStoreForwarding.B) } } val fast_stq_valids = stq_valid.asUInt for (w <- 0 until lsuWidth) { ldst_addr_matches(w) := (addr_matches(w).asUInt & lcam_st_dep_mask(w)) & fast_stq_valids ldst_forward_matches(w) := (forward_matches(w).asUInt & lcam_st_dep_mask(w)) & fast_stq_valids stld_prs2_matches(w) := (prs2_matches(w).asUInt & ~lcam_st_dep_mask(w)) & fast_stq_valids } val stq_amos = VecInit(stq_uop.map(u => u.is_fence || u.is_amo)) for (w <- 0 until lsuWidth) { val has_older_amo = (stq_amos.asUInt & lcam_st_dep_mask(w)) =/= 0.U when (do_ld_search(w) && (has_older_amo || (ldst_addr_matches(w) =/= 0.U))) { when (RegNext(dmem_req_fire(w) && !s0_kills(w)) && !fired_load_agen(w)) { io.dmem.s1_kill(w) := true.B } s1_set_execute(lcam_ldq_idx(w)) := false.B when (has_older_amo) { kill_forward(w) := true.B } } } // Set execute bit in LDQ for (i <- 0 until numLdqEntries) { when (s1_set_execute(i)) { ldq_executed(i) := true.B } } // Find the youngest store which the load is dependent on for (w <- 0 until lsuWidth) { val (youngest_matching, match_found) = ForwardingAgeLogic(numStqEntries, ldst_addr_matches(w), lcam_uop(w).stq_idx) val (youngest_forwarder, forwarder_found) = ForwardingAgeLogic(numStqEntries, ldst_forward_matches(w), lcam_uop(w).stq_idx) wb_ldst_forward_stq_idx(w) := youngest_forwarder // Forward if st-ld forwarding is possible from the writemask and loadmask wb_ldst_forward_valid(w) := (youngest_matching === youngest_forwarder && match_found && forwarder_found && RegNext(can_forward(w) && !kill_forward(w) && do_ld_search(w)) && !RegNext(IsKilledByBranch(io.core.brupdate, io.core.exception, lcam_uop(w)))) } // Avoid deadlock with a 1-w LSU prioritizing load wakeups > store commits // On a 2W machine, load wakeups and store commits occupy separate pipelines, // so only add this logic for 1-w LSU if (lsuWidth == 1) { // Wakeups may repeatedly find a st->ld addr conflict and fail to forward, // repeated wakeups may block the store from ever committing // Disallow load wakeups 1 cycle after this happens to allow the stores to drain when (RegNext(ldst_addr_matches(0) =/= 0.U) && !wb_ldst_forward_valid(0)) { block_load_wakeup := true.B } // If stores remain blocked for 15 cycles, block load wakeups to get a store through val store_blocked_counter = Reg(UInt(4.W)) when (will_fire_store_commit_fast(0) || will_fire_store_commit_slow(0) || !can_fire_store_commit_slow(0)) { store_blocked_counter := 0.U } .elsewhen (can_fire_store_commit_slow(0) && !(will_fire_store_commit_slow(0) || will_fire_store_commit_fast(0))) { store_blocked_counter := Mux(store_blocked_counter === 15.U, 15.U, store_blocked_counter + 1.U) } when (store_blocked_counter === 15.U) { block_load_wakeup := true.B } } // Forward this load to the youngest matching store val mem_stld_forward_stq_idx = widthMap(w => AgePriorityEncoder(stld_prs2_matches(w).asBools, lcam_uop(w).stq_idx)) val mem_stld_forward_valid = widthMap(w => do_ld_search(w) && stld_prs2_matches(w)(mem_stld_forward_stq_idx(w))) // Task 3: Clr unsafe bit in ROB for succesful t_ranslations // Delay this a cycle to avoid going ahead of the exception broadcast // The unsafe bit is cleared on the first translation, so no need to fire for load wakeups for (w <- 0 until lsuWidth) { io.core.clr_unsafe(w).valid := ( RegNext(do_st_search(w)) || (!io.dmem.nack(w).valid && RegNext(do_ld_search(w) && !fired_load_agen(w) && !io.dmem.s1_kill(w) && RegNext(dmem_req_fire(w)))) ) && !RegNext(failed_load) io.core.clr_unsafe(w).bits := RegNext(lcam_uop(w).rob_idx) } // detect which loads get marked as failures, but broadcast to the ROB the oldest failing load // TODO encapsulate this in an age-based priority-encoder val l_idx = AgePriorityEncoder((0 until numLdqEntries).map { i => ldq_valid(i) && ldq_order_fail(i) }, ldq_head) // one exception port, but multiple causes! // - 1) the incoming store-address finds a faulting load (it is by definition younger) // - 2) the incoming load or store address is excepting. It must be older and thus takes precedent. val r_xcpt_valid = RegInit(false.B) val r_xcpt = Reg(new Exception) val ld_xcpt_valid = (ldq_order_fail.asUInt & ldq_valid.asUInt) =/= 0.U val ld_xcpt_uop = WireInit(ldq_uop(Mux(l_idx >= numLdqEntries.U, l_idx - numLdqEntries.U, l_idx))) val use_mem_xcpt = (mem_xcpt_valid && IsOlder(mem_xcpt_uop.rob_idx, ld_xcpt_uop.rob_idx, io.core.rob_head_idx)) || !ld_xcpt_valid val xcpt_uop = Mux(use_mem_xcpt, mem_xcpt_uop, ld_xcpt_uop) r_xcpt_valid := (ld_xcpt_valid || mem_xcpt_valid) && !IsKilledByBranch(io.core.brupdate, io.core.exception, xcpt_uop) r_xcpt.uop := xcpt_uop r_xcpt.uop.br_mask := GetNewBrMask(io.core.brupdate, xcpt_uop) r_xcpt.cause := Mux(use_mem_xcpt, mem_xcpt_cause, MINI_EXCEPTION_MEM_ORDERING) r_xcpt.badvaddr := mem_xcpt_vaddr // TODO is there another register we can use instead? io.core.lxcpt.valid := r_xcpt_valid && !IsKilledByBranch(io.core.brupdate, io.core.exception, r_xcpt.uop) io.core.lxcpt.bits := r_xcpt // Task 4: Speculatively wakeup loads 1 cycle before they come back // if loadUseDelay == 5 for (w <- 0 until lsuWidth) { if (!enableFastLoadUse) { wakeupArbs(w).io.in(1).valid := (fired_load_agen_exec(w) && RegNext(dmem_req_fire(w)) && !io.dmem.s1_nack_advisory(w) && !mem_incoming_uop(w).fp_val) wakeupArbs(w).io.in(1).bits.uop := mem_incoming_uop(w) wakeupArbs(w).io.in(1).bits.bypassable := true.B wakeupArbs(w).io.in(1).bits.speculative_mask := 0.U wakeupArbs(w).io.in(1).bits.rebusy := false.B } } //------------------------------------------------------------- //------------------------------------------------------------- // Writeback Cycle (St->Ld Forwarding Path) //------------------------------------------------------------- //------------------------------------------------------------- // Handle Memory Responses and nacks //---------------------------------- val iresp = Wire(Vec(lsuWidth, Valid(new ExeUnitResp(xLen)))) val fresp = Wire(Vec(lsuWidth, Valid(new ExeUnitResp(xLen)))) for (w <- 0 until lsuWidth) { iresp(w).valid := false.B iresp(w).bits := DontCare fresp(w).valid := false.B fresp(w).bits := DontCare io.core.iresp(w) := (if (enableFastLoadUse) iresp(w) else RegNext( UpdateBrMask(io.core.brupdate, io.core.exception, iresp(w)))) io.core.fresp(w) := fresp(w) } // Initially assume the speculative load wakeup failed val wb_spec_wakeups = Wire(Vec(lsuWidth, Valid(new Wakeup))) val spec_wakeups = Wire(Vec(lsuWidth, Valid(new Wakeup))) val wb_slow_wakeups = Wire(Vec(lsuWidth, Valid(new Wakeup))) val slow_wakeups = Wire(Vec(lsuWidth, Valid(new Wakeup))) val dmem_resp_fired = WireInit(widthMap(w => false.B)) for (w <- 0 until lsuWidth) { val w1 = Reg(Valid(new Wakeup)) w1.valid := wakeupArbs(w).io.in(1).fire && !IsKilledByBranch(io.core.brupdate, io.core.exception, wakeupArbs(w).io.in(1).bits) w1.bits := UpdateBrMask(io.core.brupdate, wakeupArbs(w).io.in(1).bits) val w2 = Reg(Valid(new Wakeup)) w2.valid := w1.valid && !IsKilledByBranch(io.core.brupdate, io.core.exception, w1.bits) w2.bits := UpdateBrMask(io.core.brupdate, w1.bits) spec_wakeups(w).valid := w2.valid spec_wakeups(w).bits := w2.bits wb_spec_wakeups(w) := (if (enableFastLoadUse) w2 else w1) } for (w <- 0 until lsuWidth) { wb_slow_wakeups(w).valid := false.B wb_slow_wakeups(w).bits := DontCare // Handle nacks when (io.dmem.nack(w).valid) { when (io.dmem.nack(w).bits.is_hella) { assert(hella_state === h_wait || hella_state === h_dead) } .elsewhen (io.dmem.nack(w).bits.uop.uses_ldq) { assert(ldq_executed(io.dmem.nack(w).bits.uop.ldq_idx)) ldq_executed(io.dmem.nack(w).bits.uop.ldq_idx) := false.B } .otherwise { assert(io.dmem.nack(w).bits.uop.uses_stq) when (IsOlder(io.dmem.nack(w).bits.uop.stq_idx, stq_execute_head, stq_head)) { stq_execute_queue_flush := true.B stq_execute_head := io.dmem.nack(w).bits.uop.stq_idx } } } // Handle the response val resp = Mux(!io.dmem.resp(w).valid && (w == lsuWidth-1).B, io.dmem.ll_resp.bits, io.dmem.resp(w).bits) if (w == lsuWidth-1) { io.dmem.ll_resp.ready := !io.dmem.resp(w).valid && !wb_spec_wakeups(w).valid } when (io.dmem.resp(w).valid || ((w == lsuWidth-1).B && io.dmem.ll_resp.fire)) { when (resp.uop.uses_ldq) { assert(!resp.is_hella) val ldq_idx = resp.uop.ldq_idx val uop = WireInit(ldq_uop(ldq_idx)) val send_iresp = uop.dst_rtype === RT_FIX val send_fresp = uop.dst_rtype === RT_FLT iresp(w).bits.uop := uop fresp(w).bits.uop := uop iresp(w).valid := send_iresp iresp(w).bits.data := resp.data fresp(w).valid := send_fresp fresp(w).bits.data := resp.data assert(send_iresp ^ send_fresp) dmem_resp_fired(w) := true.B ldq_will_succeed (ldq_idx) := iresp(w).valid || fresp(w).valid ldq_debug_wb_data(ldq_idx) := resp.data wb_slow_wakeups(w).valid := send_iresp wb_slow_wakeups(w).bits.uop := uop wb_slow_wakeups(w).bits.speculative_mask := 0.U wb_slow_wakeups(w).bits.rebusy := false.B wb_slow_wakeups(w).bits.bypassable := false.B } when (resp.uop.uses_stq) { val uop = stq_uop(resp.uop.stq_idx) assert(!resp.is_hella && resp.uop.is_amo) dmem_resp_fired(w) := true.B iresp(w).valid := true.B iresp(w).bits.uop := uop iresp(w).bits.data := resp.data wb_slow_wakeups(w).valid := true.B wb_slow_wakeups(w).bits.uop := uop wb_slow_wakeups(w).bits.speculative_mask := 0.U wb_slow_wakeups(w).bits.rebusy := false.B wb_slow_wakeups(w).bits.bypassable := false.B stq_debug_wb_data(resp.uop.stq_idx) := resp.data } } // Handle store acks when (io.dmem.store_ack(w).valid) { stq_succeeded(io.dmem.store_ack(w).bits.uop.stq_idx) := true.B } when (dmem_resp_fired(w) && wb_ldst_forward_valid(w)) { // Twiddle thumbs. Can't forward because dcache response takes precedence } .elsewhen (!dmem_resp_fired(w) && wb_ldst_forward_valid(w)) { val f_idx = wb_ldst_forward_ldq_idx(w) val forward_uop = wb_ldst_forward_e(w).uop //val stq_e = WireInit(stq(wb_ldst_forward_stq_idx(w))) val s_idx = wb_ldst_forward_stq_idx(w) val storegen = new freechips.rocketchip.rocket.StoreGen( stq_uop(s_idx).mem_size, stq_addr(s_idx).bits, stq_data(s_idx).bits, coreDataBytes) val loadgen = new freechips.rocketchip.rocket.LoadGen( forward_uop.mem_size, forward_uop.mem_signed, wb_ldst_forward_ld_addr(w), storegen.data, false.B, coreDataBytes) wb_slow_wakeups(w).valid := forward_uop.dst_rtype === RT_FIX wb_slow_wakeups(w).bits.uop := forward_uop wb_slow_wakeups(w).bits.speculative_mask := 0.U wb_slow_wakeups(w).bits.rebusy := false.B wb_slow_wakeups(w).bits.bypassable := false.B iresp(w).valid := (forward_uop.dst_rtype === RT_FIX) fresp(w).valid := (forward_uop.dst_rtype === RT_FLT) iresp(w).bits.uop := forward_uop fresp(w).bits.uop := forward_uop iresp(w).bits.data := loadgen.data fresp(w).bits.data := loadgen.data ldq_will_succeed (f_idx) := true.B ldq_forward_std_val(f_idx) := true.B ldq_forward_stq_idx(f_idx) := wb_ldst_forward_stq_idx(w) ldq_debug_wb_data (f_idx) := loadgen.data } // Forward loads to store-data if (enableStLdForwarding) { when (iresp(w).valid && iresp(w).bits.uop.uses_ldq && iresp(w).bits.uop.ldq_idx === RegNext(lcam_ldq_idx(w)) && RegNext(mem_stld_forward_valid(w))) { assert(!stq_data(RegNext(mem_stld_forward_stq_idx(w))).valid) stq_data(RegNext(mem_stld_forward_stq_idx(w))).valid := true.B stq_data(RegNext(mem_stld_forward_stq_idx(w))).bits := iresp(w).bits.data } } // Do wakeups wakeupArbs(w).io.in(0).valid := false.B wakeupArbs(w).io.in(0).bits := DontCare slow_wakeups(w) := (if (enableFastLoadUse) wb_slow_wakeups(w) else RegNext(UpdateBrMask( io.core.brupdate, io.core.exception, wb_slow_wakeups(w)))) when (slow_wakeups(w).valid) { when (spec_wakeups(w).valid) { // Do nothing, since the slow wakeup matches a earlier speculative wakeup assert(slow_wakeups(w).bits.uop.ldq_idx === spec_wakeups(w).bits.uop.ldq_idx) } .otherwise { // This wasn't speculatively woken up, so end the late slow wakeup wakeupArbs(w).io.in(0).valid := slow_wakeups(w).valid wakeupArbs(w).io.in(0).bits := slow_wakeups(w).bits } } .otherwise { when (spec_wakeups(w).valid) { // This sent a speculative wakeup, now we need to undo it wakeupArbs(w).io.in(0).valid := spec_wakeups(w).valid wakeupArbs(w).io.in(0).bits := spec_wakeups(w).bits wakeupArbs(w).io.in(0).bits.rebusy := true.B } } } //------------------------------------------------------------- // Kill speculated entries on branch mispredict //------------------------------------------------------------- //------------------------------------------------------------- // Kill stores for (i <- 0 until numStqEntries) { when (stq_valid(i)) { val uop = WireInit(stq_uop(i)) stq_uop(i).br_mask := GetNewBrMask(io.core.brupdate, uop.br_mask) when (IsKilledByBranch(io.core.brupdate, false.B, uop)) { stq_valid(i) := false.B stq_addr (i).valid := false.B stq_data (i).valid := false.B } } assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)), "Branch is trying to clear a committed store.") } // Kill loads for (i <- 0 until numLdqEntries) { when (ldq_valid(i)) { val uop = WireInit(ldq_uop(i)) ldq_uop(i).br_mask := GetNewBrMask(io.core.brupdate, uop.br_mask) when (IsKilledByBranch(io.core.brupdate, io.core.exception, uop)) { ldq_valid(i) := false.B ldq_addr (i).valid := false.B } } } //------------------------------------------------------------- when (io.core.brupdate.b2.mispredict && !io.core.exception) { stq_tail := io.core.brupdate.b2.uop.stq_idx ldq_tail := io.core.brupdate.b2.uop.ldq_idx } //------------------------------------------------------------- //------------------------------------------------------------- // dequeue old entries on commit //------------------------------------------------------------- //------------------------------------------------------------- var temp_stq_commit_head = stq_commit_head var temp_ldq_head = ldq_head for (w <- 0 until coreWidth) { val commit_store = io.core.commit.valids(w) && io.core.commit.uops(w).uses_stq val commit_load = io.core.commit.valids(w) && io.core.commit.uops(w).uses_ldq // val stq_e = WireInit(stq(temp_stq_commit_head)) // val ldq_e = WireInit(ldq(temp_ldq_head)) val l_uop = WireInit(ldq_uop(temp_ldq_head)) val s_uop = WireInit(stq_uop(temp_stq_commit_head)) when (commit_store) { stq_committed (temp_stq_commit_head) := true.B stq_can_execute(temp_stq_commit_head) := true.B } .elsewhen (commit_load) { assert (ldq_valid(temp_ldq_head), "[lsu] trying to commit an un-allocated load entry.") assert ((ldq_executed(temp_ldq_head) || ldq_forward_std_val(temp_ldq_head)) && ldq_succeeded(temp_ldq_head), "[lsu] trying to commit an un-executed load entry.") ldq_valid(temp_ldq_head) := false.B } if (MEMTRACE_PRINTF) { when (commit_store || commit_load) { val uop = Mux(commit_store, s_uop, l_uop) val addr = Mux(commit_store, stq_addr(temp_stq_commit_head).bits , ldq_addr(temp_ldq_head).bits) val stdata = Mux(commit_store, stq_data(temp_stq_commit_head).bits , 0.U) val wbdata = Mux(commit_store, stq_debug_wb_data(temp_stq_commit_head), ldq_debug_wb_data(temp_ldq_head)) printf("MT %x %x %x %x %x %x %x\n", io.core.tsc_reg, 0.U, uop.mem_cmd, uop.mem_size, addr, stdata, wbdata) } } temp_stq_commit_head = Mux(commit_store, WrapInc(temp_stq_commit_head, numStqEntries), temp_stq_commit_head) temp_ldq_head = Mux(commit_load, WrapInc(temp_ldq_head, numLdqEntries), temp_ldq_head) } stq_commit_head := temp_stq_commit_head ldq_head := temp_ldq_head // store has been committed AND successfully sent data to memory val stq_head_is_fence = stq_uop(stq_head).is_fence when (stq_valid(stq_head) && stq_committed(stq_head)) { when (stq_head_is_fence && !io.dmem.ordered) { io.dmem.force_order := true.B store_needs_order := true.B } clear_store := Mux(stq_head_is_fence, io.dmem.ordered, stq_succeeded(stq_head)) } when (clear_store) { stq_valid(stq_head) := false.B stq_head := WrapInc(stq_head, numStqEntries) when (stq_head_is_fence) { stq_execute_head := WrapInc(stq_execute_head, numStqEntries) } } // ----------------------- // Hellacache interface // We need to time things like a HellaCache would io.hellacache.req.ready := false.B io.hellacache.s2_nack := false.B io.hellacache.s2_nack_cause_raw := false.B io.hellacache.s2_uncached := DontCare io.hellacache.s2_paddr := DontCare io.hellacache.s2_xcpt := (0.U).asTypeOf(new rocket.HellaCacheExceptions) io.hellacache.replay_next := false.B io.hellacache.s2_gpa := DontCare io.hellacache.s2_gpa_is_pte := DontCare io.hellacache.ordered := DontCare io.hellacache.perf := DontCare io.hellacache.clock_enabled := true.B io.hellacache.store_pending := stq_valid.reduce(_||_) io.hellacache.resp.valid := false.B io.hellacache.resp.bits.addr := hella_req.addr io.hellacache.resp.bits.tag := hella_req.tag io.hellacache.resp.bits.cmd := hella_req.cmd io.hellacache.resp.bits.signed := hella_req.signed io.hellacache.resp.bits.size := hella_req.size io.hellacache.resp.bits.mask := hella_req.mask io.hellacache.resp.bits.replay := false.B io.hellacache.resp.bits.has_data := true.B io.hellacache.resp.bits.data_word_bypass := io.dmem.ll_resp.bits.data io.hellacache.resp.bits.data_raw := io.dmem.ll_resp.bits.data io.hellacache.resp.bits.store_data := hella_req.data io.hellacache.resp.bits.dprv := io.ptw.status.prv io.hellacache.resp.bits.dv := io.ptw.status.v io.hellacache.resp.bits.data := io.dmem.ll_resp.bits.data when (hella_state === h_ready) { io.hellacache.req.ready := true.B when (io.hellacache.req.fire) { hella_req := io.hellacache.req.bits hella_state := h_s1 } } .elsewhen (hella_state === h_s1) { can_fire_hella_incoming(0) := true.B hella_data := io.hellacache.s1_data hella_xcpt := dtlb.io.resp(0) when (io.hellacache.s1_kill) { when (will_fire_hella_incoming(0) && dmem_req_fire(0)) { hella_state := h_dead } .otherwise { hella_state := h_ready } } .elsewhen (will_fire_hella_incoming(0) && dmem_req_fire(0)) { hella_state := h_s2 } .otherwise { hella_state := h_s2_nack } } .elsewhen (hella_state === h_s2_nack) { io.hellacache.s2_nack := true.B hella_state := h_ready } .elsewhen (hella_state === h_s2) { io.hellacache.s2_xcpt := hella_xcpt when (io.hellacache.s2_kill || hella_xcpt.asUInt =/= 0.U) { hella_state := h_dead } .otherwise { hella_state := h_wait } } .elsewhen (hella_state === h_wait) { when (io.dmem.ll_resp.fire && io.dmem.ll_resp.bits.is_hella) { hella_state := h_ready io.hellacache.resp.valid := true.B io.hellacache.resp.bits.addr := hella_req.addr io.hellacache.resp.bits.tag := hella_req.tag io.hellacache.resp.bits.cmd := hella_req.cmd io.hellacache.resp.bits.signed := hella_req.signed io.hellacache.resp.bits.size := hella_req.size io.hellacache.resp.bits.data := io.dmem.ll_resp.bits.data } for (w <- 0 until lsuWidth) { when ((io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) || (io.dmem.store_ack(w).valid && io.dmem.store_ack(w).bits.is_hella)) { hella_state := h_ready io.hellacache.resp.valid := true.B io.hellacache.resp.bits.addr := hella_req.addr io.hellacache.resp.bits.tag := hella_req.tag io.hellacache.resp.bits.cmd := hella_req.cmd io.hellacache.resp.bits.signed := hella_req.signed io.hellacache.resp.bits.size := hella_req.size io.hellacache.resp.bits.data := io.dmem.resp(w).bits.data } when (io.dmem.nack(w).valid && io.dmem.nack(w).bits.is_hella) { hella_state := h_replay } } } .elsewhen (hella_state === h_replay) { can_fire_hella_wakeup(0) := true.B when (will_fire_hella_wakeup(0) && dmem_req_fire(0)) { hella_state := h_wait } } .elsewhen (hella_state === h_dead) { when (io.dmem.ll_resp.fire && io.dmem.ll_resp.bits.is_hella) { hella_state := h_ready } for (w <- 0 until lsuWidth) { when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) { hella_state := h_ready } } } //------------------------------------------------------------- // Exception / Reset when (reset.asBool || io.core.exception) { ldq_head := 0.U ldq_tail := 0.U when (reset.asBool) { stq_head := 0.U stq_tail := 0.U stq_commit_head := 0.U stq_execute_head := 0.U for (i <- 0 until numStqEntries) { stq_valid(i) := false.B } } .otherwise // exception { stq_tail := stq_commit_head for (i <- 0 until numStqEntries) { when (!stq_committed(i) && !stq_succeeded(i)) { stq_valid(i) := false.B } } } for (i <- 0 until numLdqEntries) { ldq_valid(i) := false.B } } } /** * Object to take an address and generate an 8-bit mask of which bytes within a * double-word. */ object GenByteMask { def apply(addr: UInt, size: UInt): UInt = { val mask = Wire(UInt(8.W)) mask := MuxCase(255.U(8.W), Array( (size === 0.U) -> (1.U(8.W) << addr(2,0)), (size === 1.U) -> (3.U(8.W) << (addr(2,1) << 1.U)), (size === 2.U) -> Mux(addr(2), 240.U(8.W), 15.U(8.W)), (size === 3.U) -> 255.U(8.W))) mask } } object ForwardingAgeLogic { def apply(n: Int, matches: UInt, youngest: UInt): (UInt, Bool) = { val logic = Module(new ForwardingAgeLogic(n)) logic.io.matches := matches logic.io.youngest := youngest (logic.io.found_idx, logic.io.found) } } class ForwardingAgeLogic(n: Int) extends Module() { val io = IO(new Bundle { val matches = Input(UInt(n.W)) // bit vector of addresses that match // between the load and the SAQ val youngest = Input(UInt(log2Ceil(n).W)) // needed to get "age" val found = Output(Bool()) val found_idx = Output(UInt(log2Ceil(n).W)) }) // generating mask that zeroes out anything younger than tail val age_mask = Wire(Vec(n, Bool())) for (i <- 0 until n) { age_mask(i) := true.B when (i.U >= io.youngest) // currently the tail points PAST last store, so use >= { age_mask(i) := false.B } } // Priority encoder with moving tail: double length val matches = Wire(UInt((2*n).W)) matches := Cat(io.matches & age_mask.asUInt, io.matches) val found_match = Reg(Bool()) val found_idx = Reg(UInt(log2Ceil(n).W)) found_match := false.B found_idx := 0.U io.found_idx := found_idx io.found := found_match // look for youngest, approach from the oldest side, let the last one found stick for (i <- 0 until (2*n)) { when (matches(i)) { found_match := true.B found_idx := (i % n).U } } } File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 3 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_4 = 3.U(BSRC_SZ.W) // 4-cycle branch pred val BSRC_C = 4.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val B_N = 0.U(4.W) // Next val B_NE = 1.U(4.W) // Branch on NotEqual val B_EQ = 2.U(4.W) // Branch on Equal val B_GE = 3.U(4.W) // Branch on Greater/Equal val B_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val B_LT = 5.U(4.W) // Branch on Less Than val B_LTU = 6.U(4.W) // Branch on Less Than Unsigned val B_J = 7.U(4.W) // Jump val B_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_RS1SHL = 3.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_RS2OH = 5.U(3.W) val OP2_IMMOH = 6.U(3.W) val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_SH = 5.U(3.W) // short-type (sign extend from pimm to get imm) val IS_N = 6.U(3.W) // No immediate (zeros immediate) val IS_F3 = 7.U(3.W) // funct3 // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_X = 2.U(2.W) // not-a-register (prs1 = lrs1 special case) val RT_ZERO = 3.U(2.W) // IQT type val IQ_SZ = 4 val IQ_MEM = 0 val IQ_UNQ = 1 val IQ_ALU = 2 val IQ_FP = 3 // Functional unit select // bit mask, since a given execution pipeline may support multiple functional units val FC_SZ = 10 val FC_ALU = 0 val FC_AGEN = 1 val FC_DGEN = 2 val FC_MUL = 3 val FC_DIV = 4 val FC_CSR = 5 val FC_FPU = 6 val FC_FDV = 7 val FC_I2F = 8 val FC_F2I = 9 def NullMicroOp(implicit p: Parameters) = 0.U.asTypeOf(new boom.v4.common.MicroOp) } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v4.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize*8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) | Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and || logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out | ~wmask & io.lhs io.out_unmasked := out }

module LSU( // @[lsu.scala:211:7] input clock, // @[lsu.scala:211:7] input reset, // @[lsu.scala:211:7] input io_ptw_req_ready, // @[lsu.scala:214:14] output io_ptw_req_valid, // @[lsu.scala:214:14] output io_ptw_req_bits_valid, // @[lsu.scala:214:14] output [26:0] io_ptw_req_bits_bits_addr, // @[lsu.scala:214:14] input io_ptw_resp_valid, // @[lsu.scala:214:14] input io_ptw_resp_bits_ae_ptw, // @[lsu.scala:214:14] input io_ptw_resp_bits_ae_final, // @[lsu.scala:214:14] input io_ptw_resp_bits_pf, // @[lsu.scala:214:14] input io_ptw_resp_bits_gf, // @[lsu.scala:214:14] input io_ptw_resp_bits_hr, // @[lsu.scala:214:14] input io_ptw_resp_bits_hw, // @[lsu.scala:214:14] input io_ptw_resp_bits_hx, // @[lsu.scala:214:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[lsu.scala:214:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[lsu.scala:214:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_d, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_a, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_g, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_u, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_x, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_w, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_r, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_v, // @[lsu.scala:214:14] input [1:0] io_ptw_resp_bits_level, // @[lsu.scala:214:14] input io_ptw_resp_bits_homogeneous, // @[lsu.scala:214:14] input io_ptw_resp_bits_gpa_valid, // @[lsu.scala:214:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[lsu.scala:214:14] input io_ptw_resp_bits_gpa_is_pte, // @[lsu.scala:214:14] input [3:0] io_ptw_ptbr_mode, // @[lsu.scala:214:14] input [43:0] io_ptw_ptbr_ppn, // @[lsu.scala:214:14] input io_ptw_status_debug, // @[lsu.scala:214:14] input io_ptw_status_cease, // @[lsu.scala:214:14] input io_ptw_status_wfi, // @[lsu.scala:214:14] input [1:0] io_ptw_status_dprv, // @[lsu.scala:214:14] input io_ptw_status_dv, // @[lsu.scala:214:14] input [1:0] io_ptw_status_prv, // @[lsu.scala:214:14] input io_ptw_status_v, // @[lsu.scala:214:14] input io_ptw_status_sd, // @[lsu.scala:214:14] input io_ptw_status_mpv, // @[lsu.scala:214:14] input io_ptw_status_gva, // @[lsu.scala:214:14] input io_ptw_status_tsr, // @[lsu.scala:214:14] input io_ptw_status_tw, // @[lsu.scala:214:14] input io_ptw_status_tvm, // @[lsu.scala:214:14] input io_ptw_status_mxr, // @[lsu.scala:214:14] input io_ptw_status_sum, // @[lsu.scala:214:14] input io_ptw_status_mprv, // @[lsu.scala:214:14] input [1:0] io_ptw_status_fs, // @[lsu.scala:214:14] input [1:0] io_ptw_status_mpp, // @[lsu.scala:214:14] input io_ptw_status_spp, // @[lsu.scala:214:14] input io_ptw_status_mpie, // @[lsu.scala:214:14] input io_ptw_status_spie, // @[lsu.scala:214:14] input io_ptw_status_mie, // @[lsu.scala:214:14] input io_ptw_status_sie, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_0_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_0_mask, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_1_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_1_mask, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_2_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_2_mask, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_3_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_3_mask, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_4_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_4_mask, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_5_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_5_mask, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_6_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_6_mask, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_7_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_7_mask, // @[lsu.scala:214:14] input io_core_agen_0_valid, // @[lsu.scala:214:14] input [31:0] io_core_agen_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_agen_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_agen_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_agen_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_agen_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_agen_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_taken, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_agen_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_agen_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_agen_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_agen_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_agen_0_bits_data, // @[lsu.scala:214:14] input io_core_dgen_0_valid, // @[lsu.scala:214:14] input [31:0] io_core_dgen_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_dgen_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dgen_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_dgen_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dgen_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dgen_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_taken, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dgen_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_dgen_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_dgen_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_dgen_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_dgen_0_bits_data, // @[lsu.scala:214:14] input io_core_dgen_1_valid, // @[lsu.scala:214:14] input [31:0] io_core_dgen_1_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_dgen_1_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dgen_1_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_dgen_1_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dgen_1_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dgen_1_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_taken, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dgen_1_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_dgen_1_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_dgen_1_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_dgen_1_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_dgen_1_bits_data, // @[lsu.scala:214:14] input io_core_dgen_2_valid, // @[lsu.scala:214:14] input [31:0] io_core_dgen_2_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_dgen_2_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dgen_2_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_dgen_2_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dgen_2_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dgen_2_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_taken, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dgen_2_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_dgen_2_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_dgen_2_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_dgen_2_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_dgen_2_bits_data, // @[lsu.scala:214:14] output io_core_iwakeups_0_valid, // @[lsu.scala:214:14] output [31:0] io_core_iwakeups_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_iwakeups_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_iwakeups_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [11:0] io_core_iwakeups_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_iwakeups_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_iwakeups_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_taken, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_iwakeups_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [3:0] io_core_iwakeups_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [3:0] io_core_iwakeups_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_iwakeups_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_bypassable, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_speculative_mask, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_rebusy, // @[lsu.scala:214:14] output io_core_iresp_0_valid, // @[lsu.scala:214:14] output [31:0] io_core_iresp_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_iresp_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_iresp_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [11:0] io_core_iresp_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_iresp_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_iresp_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_taken, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_iresp_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [3:0] io_core_iresp_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [3:0] io_core_iresp_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_iresp_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [63:0] io_core_iresp_0_bits_data, // @[lsu.scala:214:14] output io_core_fresp_0_valid, // @[lsu.scala:214:14] output [31:0] io_core_fresp_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_fresp_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_fresp_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [11:0] io_core_fresp_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_fresp_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_fresp_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_taken, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_fresp_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [3:0] io_core_fresp_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [3:0] io_core_fresp_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_fresp_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [63:0] io_core_fresp_0_bits_data, // @[lsu.scala:214:14] input io_core_sfence_valid, // @[lsu.scala:214:14] input io_core_sfence_bits_rs1, // @[lsu.scala:214:14] input io_core_sfence_bits_rs2, // @[lsu.scala:214:14] input [38:0] io_core_sfence_bits_addr, // @[lsu.scala:214:14] input io_core_sfence_bits_asid, // @[lsu.scala:214:14] input io_core_sfence_bits_hv, // @[lsu.scala:214:14] input io_core_sfence_bits_hg, // @[lsu.scala:214:14] input io_core_dis_uops_0_valid, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_0_bits_inst, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_0_bits_debug_inst, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dis_uops_0_bits_debug_pc, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_0, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_1, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_2, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_3, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_0, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_1, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_2, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_3, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_4, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_5, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_6, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_7, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_8, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_9, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_issued, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_dis_uops_0_bits_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_0_bits_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_0_bits_br_type, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_sfb, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_fence, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_fencei, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_sfence, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_amo, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_eret, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_rocc, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_ftq_idx, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_pc_lob, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_taken, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dis_uops_0_bits_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_op2_sel, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_0_bits_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_0_bits_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_ppred, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_prs1_busy, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_prs2_busy, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_prs3_busy, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_stale_pdst, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_exception, // @[lsu.scala:214:14] input [63:0] io_core_dis_uops_0_bits_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_mem_size, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_mem_signed, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_uses_ldq, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_uses_stq, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_unique, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_csr_cmd, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_frs3_en, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_fcn_op, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_fp_typ, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_bp_debug_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_debug_tsrc, // @[lsu.scala:214:14] input io_core_dis_uops_1_valid, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_1_bits_inst, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_1_bits_debug_inst, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dis_uops_1_bits_debug_pc, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_0, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_1, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_2, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_3, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_0, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_1, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_2, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_3, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_4, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_5, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_6, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_7, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_8, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_9, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_issued, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_dis_uops_1_bits_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_1_bits_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_1_bits_br_type, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_sfb, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_fence, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_fencei, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_sfence, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_amo, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_eret, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_rocc, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_ftq_idx, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_pc_lob, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_taken, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dis_uops_1_bits_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_op2_sel, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_1_bits_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_1_bits_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_ppred, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_prs1_busy, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_prs2_busy, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_prs3_busy, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_stale_pdst, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_exception, // @[lsu.scala:214:14] input [63:0] io_core_dis_uops_1_bits_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_mem_size, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_mem_signed, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_uses_ldq, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_uses_stq, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_unique, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_csr_cmd, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_frs3_en, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_fcn_op, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_fp_typ, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_bp_debug_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_debug_tsrc, // @[lsu.scala:214:14] output [3:0] io_core_dis_ldq_idx_0, // @[lsu.scala:214:14] output [3:0] io_core_dis_ldq_idx_1, // @[lsu.scala:214:14] output [3:0] io_core_dis_stq_idx_0, // @[lsu.scala:214:14] output [3:0] io_core_dis_stq_idx_1, // @[lsu.scala:214:14] output io_core_ldq_full_0, // @[lsu.scala:214:14] output io_core_ldq_full_1, // @[lsu.scala:214:14] output io_core_stq_full_0, // @[lsu.scala:214:14] output io_core_stq_full_1, // @[lsu.scala:214:14] input io_core_commit_valids_0, // @[lsu.scala:214:14] input io_core_commit_valids_1, // @[lsu.scala:214:14] input io_core_commit_arch_valids_0, // @[lsu.scala:214:14] input io_core_commit_arch_valids_1, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_0_inst, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_0_debug_inst, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_commit_uops_0_debug_pc, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_0, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_1, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_2, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_3, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_0, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_1, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_2, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_3, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_4, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_5, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_6, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_7, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_8, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_9, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_issued, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_commit_uops_0_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_0_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_0_br_type, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_sfb, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_fence, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_fencei, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_sfence, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_amo, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_eret, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_rocc, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_ftq_idx, // @[lsu.scala:214:14] input io_core_commit_uops_0_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_pc_lob, // @[lsu.scala:214:14] input io_core_commit_uops_0_taken, // @[lsu.scala:214:14] input io_core_commit_uops_0_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_pimm, // @[lsu.scala:214:14] input [19:0] io_core_commit_uops_0_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_op2_sel, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_0_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_0_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_pdst, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_prs1, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_prs2, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_prs3, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_ppred, // @[lsu.scala:214:14] input io_core_commit_uops_0_prs1_busy, // @[lsu.scala:214:14] input io_core_commit_uops_0_prs2_busy, // @[lsu.scala:214:14] input io_core_commit_uops_0_prs3_busy, // @[lsu.scala:214:14] input io_core_commit_uops_0_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_stale_pdst, // @[lsu.scala:214:14] input io_core_commit_uops_0_exception, // @[lsu.scala:214:14] input [63:0] io_core_commit_uops_0_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_mem_size, // @[lsu.scala:214:14] input io_core_commit_uops_0_mem_signed, // @[lsu.scala:214:14] input io_core_commit_uops_0_uses_ldq, // @[lsu.scala:214:14] input io_core_commit_uops_0_uses_stq, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_unique, // @[lsu.scala:214:14] input io_core_commit_uops_0_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_csr_cmd, // @[lsu.scala:214:14] input io_core_commit_uops_0_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_ldst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_lrs2_rtype, // @[lsu.scala:214:14] input io_core_commit_uops_0_frs3_en, // @[lsu.scala:214:14] input io_core_commit_uops_0_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_fcn_op, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_fp_typ, // @[lsu.scala:214:14] input io_core_commit_uops_0_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_bp_debug_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_debug_tsrc, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_1_inst, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_1_debug_inst, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_commit_uops_1_debug_pc, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_0, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_1, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_2, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_3, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_0, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_1, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_2, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_3, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_4, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_5, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_6, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_7, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_8, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_9, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_issued, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_commit_uops_1_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_1_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_1_br_type, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_sfb, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_fence, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_fencei, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_sfence, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_amo, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_eret, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_rocc, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_ftq_idx, // @[lsu.scala:214:14] input io_core_commit_uops_1_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_pc_lob, // @[lsu.scala:214:14] input io_core_commit_uops_1_taken, // @[lsu.scala:214:14] input io_core_commit_uops_1_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_pimm, // @[lsu.scala:214:14] input [19:0] io_core_commit_uops_1_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_op2_sel, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_1_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_1_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_pdst, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_prs1, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_prs2, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_prs3, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_ppred, // @[lsu.scala:214:14] input io_core_commit_uops_1_prs1_busy, // @[lsu.scala:214:14] input io_core_commit_uops_1_prs2_busy, // @[lsu.scala:214:14] input io_core_commit_uops_1_prs3_busy, // @[lsu.scala:214:14] input io_core_commit_uops_1_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_stale_pdst, // @[lsu.scala:214:14] input io_core_commit_uops_1_exception, // @[lsu.scala:214:14] input [63:0] io_core_commit_uops_1_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_mem_size, // @[lsu.scala:214:14] input io_core_commit_uops_1_mem_signed, // @[lsu.scala:214:14] input io_core_commit_uops_1_uses_ldq, // @[lsu.scala:214:14] input io_core_commit_uops_1_uses_stq, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_unique, // @[lsu.scala:214:14] input io_core_commit_uops_1_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_csr_cmd, // @[lsu.scala:214:14] input io_core_commit_uops_1_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_ldst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_lrs2_rtype, // @[lsu.scala:214:14] input io_core_commit_uops_1_frs3_en, // @[lsu.scala:214:14] input io_core_commit_uops_1_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_fcn_op, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_fp_typ, // @[lsu.scala:214:14] input io_core_commit_uops_1_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_bp_debug_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_debug_tsrc, // @[lsu.scala:214:14] input io_core_commit_fflags_valid, // @[lsu.scala:214:14] input [4:0] io_core_commit_fflags_bits, // @[lsu.scala:214:14] input [63:0] io_core_commit_debug_wdata_0, // @[lsu.scala:214:14] input [63:0] io_core_commit_debug_wdata_1, // @[lsu.scala:214:14] input io_core_commit_load_at_rob_head, // @[lsu.scala:214:14] output io_core_clr_bsy_0_valid, // @[lsu.scala:214:14] output [5:0] io_core_clr_bsy_0_bits, // @[lsu.scala:214:14] output io_core_clr_bsy_1_valid, // @[lsu.scala:214:14] output [5:0] io_core_clr_bsy_1_bits, // @[lsu.scala:214:14] output io_core_clr_unsafe_0_valid, // @[lsu.scala:214:14] output [5:0] io_core_clr_unsafe_0_bits, // @[lsu.scala:214:14] input io_core_fence_dmem, // @[lsu.scala:214:14] input [11:0] io_core_brupdate_b1_resolve_mask, // @[lsu.scala:214:14] input [11:0] io_core_brupdate_b1_mispredict_mask, // @[lsu.scala:214:14] input [31:0] io_core_brupdate_b2_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_brupdate_b2_uop_debug_inst, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_brupdate_b2_uop_debug_pc, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_issued, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_core_brupdate_b2_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_brupdate_b2_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_brupdate_b2_uop_br_type, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_sfb, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_fence, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_fencei, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_sfence, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_amo, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_eret, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_rocc, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_pc_lob, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_taken, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_brupdate_b2_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_op2_sel, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_core_brupdate_b2_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_core_brupdate_b2_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_ppred, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_brupdate_b2_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_mem_size, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_mem_signed, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_uses_stq, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_unique, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_frs3_en, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_fcn_op, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_fp_typ, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:214:14] input io_core_brupdate_b2_mispredict, // @[lsu.scala:214:14] input io_core_brupdate_b2_taken, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_cfi_type, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_pc_sel, // @[lsu.scala:214:14] input [39:0] io_core_brupdate_b2_jalr_target, // @[lsu.scala:214:14] input [20:0] io_core_brupdate_b2_target_offset, // @[lsu.scala:214:14] input [5:0] io_core_rob_pnr_idx, // @[lsu.scala:214:14] input [5:0] io_core_rob_head_idx, // @[lsu.scala:214:14] input io_core_exception, // @[lsu.scala:214:14] output io_core_fencei_rdy, // @[lsu.scala:214:14] output io_core_lxcpt_valid, // @[lsu.scala:214:14] output [31:0] io_core_lxcpt_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_lxcpt_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_lxcpt_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [11:0] io_core_lxcpt_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_lxcpt_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_lxcpt_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_taken, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_lxcpt_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_rob_idx, // @[lsu.scala:214:14] output [3:0] io_core_lxcpt_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [3:0] io_core_lxcpt_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_lxcpt_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_cause, // @[lsu.scala:214:14] output [39:0] io_core_lxcpt_bits_badvaddr, // @[lsu.scala:214:14] input [63:0] io_core_tsc_reg, // @[lsu.scala:214:14] input io_core_status_debug, // @[lsu.scala:214:14] input io_core_status_cease, // @[lsu.scala:214:14] input io_core_status_wfi, // @[lsu.scala:214:14] input [1:0] io_core_status_dprv, // @[lsu.scala:214:14] input io_core_status_dv, // @[lsu.scala:214:14] input [1:0] io_core_status_prv, // @[lsu.scala:214:14] input io_core_status_v, // @[lsu.scala:214:14] input io_core_status_sd, // @[lsu.scala:214:14] input io_core_status_mpv, // @[lsu.scala:214:14] input io_core_status_gva, // @[lsu.scala:214:14] input io_core_status_tsr, // @[lsu.scala:214:14] input io_core_status_tw, // @[lsu.scala:214:14] input io_core_status_tvm, // @[lsu.scala:214:14] input io_core_status_mxr, // @[lsu.scala:214:14] input io_core_status_sum, // @[lsu.scala:214:14] input io_core_status_mprv, // @[lsu.scala:214:14] input [1:0] io_core_status_fs, // @[lsu.scala:214:14] input [1:0] io_core_status_mpp, // @[lsu.scala:214:14] input io_core_status_spp, // @[lsu.scala:214:14] input io_core_status_mpie, // @[lsu.scala:214:14] input io_core_status_spie, // @[lsu.scala:214:14] input io_core_status_mie, // @[lsu.scala:214:14] input io_core_status_sie, // @[lsu.scala:214:14] output io_core_perf_acquire, // @[lsu.scala:214:14] output io_core_perf_release, // @[lsu.scala:214:14] output io_core_perf_tlbMiss, // @[lsu.scala:214:14] input io_dmem_req_ready, // @[lsu.scala:214:14] output io_dmem_req_valid, // @[lsu.scala:214:14] output io_dmem_req_bits_0_valid, // @[lsu.scala:214:14] output [31:0] io_dmem_req_bits_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_dmem_req_bits_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_dmem_req_bits_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [11:0] io_dmem_req_bits_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_dmem_req_bits_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_dmem_req_bits_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_taken, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_dmem_req_bits_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [3:0] io_dmem_req_bits_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [3:0] io_dmem_req_bits_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_dmem_req_bits_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [39:0] io_dmem_req_bits_0_bits_addr, // @[lsu.scala:214:14] output [63:0] io_dmem_req_bits_0_bits_data, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_is_hella, // @[lsu.scala:214:14] output io_dmem_s1_kill_0, // @[lsu.scala:214:14] input io_dmem_resp_0_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_resp_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_resp_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_resp_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_dmem_resp_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_resp_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_resp_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_resp_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_resp_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_resp_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_resp_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_dmem_resp_0_bits_data, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_is_hella, // @[lsu.scala:214:14] input io_dmem_store_ack_0_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_store_ack_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_store_ack_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_store_ack_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_dmem_store_ack_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_store_ack_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_store_ack_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_store_ack_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_store_ack_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_store_ack_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_store_ack_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [39:0] io_dmem_store_ack_0_bits_addr, // @[lsu.scala:214:14] input [63:0] io_dmem_store_ack_0_bits_data, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_is_hella, // @[lsu.scala:214:14] input io_dmem_nack_0_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_nack_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_nack_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_nack_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_dmem_nack_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_nack_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_nack_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_nack_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_nack_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_nack_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_nack_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [39:0] io_dmem_nack_0_bits_addr, // @[lsu.scala:214:14] input [63:0] io_dmem_nack_0_bits_data, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_is_hella, // @[lsu.scala:214:14] output io_dmem_ll_resp_ready, // @[lsu.scala:214:14] input io_dmem_ll_resp_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_ll_resp_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_ll_resp_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_ll_resp_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [11:0] io_dmem_ll_resp_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_ll_resp_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_ll_resp_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_ll_resp_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_rob_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_ll_resp_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [3:0] io_dmem_ll_resp_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_ll_resp_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_dmem_ll_resp_bits_data, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_is_hella, // @[lsu.scala:214:14] output [11:0] io_dmem_brupdate_b1_resolve_mask, // @[lsu.scala:214:14] output [11:0] io_dmem_brupdate_b1_mispredict_mask, // @[lsu.scala:214:14] output [31:0] io_dmem_brupdate_b2_uop_inst, // @[lsu.scala:214:14] output [31:0] io_dmem_brupdate_b2_uop_debug_inst, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_dmem_brupdate_b2_uop_debug_pc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_0, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_1, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_2, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_3, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_0, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_1, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_2, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_3, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_4, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_5, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_6, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_7, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_8, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_9, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_issued, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_dis_col_sel, // @[lsu.scala:214:14] output [11:0] io_dmem_brupdate_b2_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_dmem_brupdate_b2_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_dmem_brupdate_b2_uop_br_type, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_sfb, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_fence, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_fencei, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_sfence, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_amo, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_eret, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_rocc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_ftq_idx, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_pc_lob, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_taken, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_dmem_brupdate_b2_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_op2_sel, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_rob_idx, // @[lsu.scala:214:14] output [3:0] io_dmem_brupdate_b2_uop_ldq_idx, // @[lsu.scala:214:14] output [3:0] io_dmem_brupdate_b2_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_ppred, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_prs1_busy, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_prs2_busy, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_prs3_busy, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_stale_pdst, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_exception, // @[lsu.scala:214:14] output [63:0] io_dmem_brupdate_b2_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_mem_size, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_mem_signed, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_uses_ldq, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_uses_stq, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_unique, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_csr_cmd, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_frs3_en, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_fcn_op, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_fp_typ, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_mispredict, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_taken, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_cfi_type, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_pc_sel, // @[lsu.scala:214:14] output [39:0] io_dmem_brupdate_b2_jalr_target, // @[lsu.scala:214:14] output [20:0] io_dmem_brupdate_b2_target_offset, // @[lsu.scala:214:14] output io_dmem_exception, // @[lsu.scala:214:14] output [5:0] io_dmem_rob_pnr_idx, // @[lsu.scala:214:14] output [5:0] io_dmem_rob_head_idx, // @[lsu.scala:214:14] output io_dmem_release_ready, // @[lsu.scala:214:14] input io_dmem_release_valid, // @[lsu.scala:214:14] input [2:0] io_dmem_release_bits_opcode, // @[lsu.scala:214:14] input [2:0] io_dmem_release_bits_param, // @[lsu.scala:214:14] input [3:0] io_dmem_release_bits_size, // @[lsu.scala:214:14] input [1:0] io_dmem_release_bits_source, // @[lsu.scala:214:14] input [31:0] io_dmem_release_bits_address, // @[lsu.scala:214:14] input [63:0] io_dmem_release_bits_data, // @[lsu.scala:214:14] output io_dmem_force_order, // @[lsu.scala:214:14] input io_dmem_ordered, // @[lsu.scala:214:14] input io_dmem_perf_acquire, // @[lsu.scala:214:14] input io_dmem_perf_release, // @[lsu.scala:214:14] output io_hellacache_req_ready, // @[lsu.scala:214:14] input io_hellacache_req_valid, // @[lsu.scala:214:14] input [39:0] io_hellacache_req_bits_addr, // @[lsu.scala:214:14] input io_hellacache_req_bits_dv, // @[lsu.scala:214:14] input io_hellacache_s1_kill, // @[lsu.scala:214:14] output io_hellacache_s2_nack, // @[lsu.scala:214:14] output io_hellacache_resp_valid, // @[lsu.scala:214:14] output [39:0] io_hellacache_resp_bits_addr, // @[lsu.scala:214:14] output [1:0] io_hellacache_resp_bits_dprv, // @[lsu.scala:214:14] output io_hellacache_resp_bits_dv, // @[lsu.scala:214:14] output [63:0] io_hellacache_resp_bits_data, // @[lsu.scala:214:14] output [63:0] io_hellacache_resp_bits_data_word_bypass, // @[lsu.scala:214:14] output [63:0] io_hellacache_resp_bits_data_raw, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ma_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ma_st, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_pf_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_pf_st, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_gf_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_gf_st, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ae_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ae_st, // @[lsu.scala:214:14] output io_hellacache_store_pending // @[lsu.scala:214:14] ); wire [2:0] wb_slow_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_ldst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1494:29] wire [63:0] wb_slow_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_exception; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_ppred; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_prs3; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_prs2; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_prs1; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_pdst; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1494:29] wire [3:0] wb_slow_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1494:29] wire [3:0] wb_slow_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1494:29] wire [19:0] wb_slow_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_pimm; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_taken; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1494:29] wire [3:0] wb_slow_wakeups_0_bits_uop_br_type; // @[lsu.scala:1494:29] wire [3:0] wb_slow_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1494:29] wire [39:0] wb_slow_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1494:29] wire [31:0] wb_slow_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1494:29] wire [31:0] wb_slow_wakeups_0_bits_uop_inst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1494:29] wire [63:0] iresp_0_bits_data; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_debug_tsrc; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_debug_fsrc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_bp_debug_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_fp_typ; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_fp_rm; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_val; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_fcn_op; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fcn_dw; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_frs3_en; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_lrs2_rtype; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_lrs1_rtype; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_dst_rtype; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_lrs3; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_lrs2; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_lrs1; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_ldst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_csr_cmd; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_flush_on_commit; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_unique; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_uses_stq; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_uses_ldq; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_mem_signed; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_mem_size; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_mem_cmd; // @[lsu.scala:1477:19] wire [63:0] iresp_0_bits_uop_exc_cause; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_exception; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_stale_pdst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_ppred_busy; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_prs3_busy; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_prs2_busy; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_prs1_busy; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_ppred; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_prs3; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_prs2; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_prs1; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_pdst; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_rxq_idx; // @[lsu.scala:1477:19] wire [3:0] iresp_0_bits_uop_stq_idx; // @[lsu.scala:1477:19] wire [3:0] iresp_0_bits_uop_ldq_idx; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_rob_idx; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_op2_sel; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_op1_sel; // @[lsu.scala:1477:19] wire [19:0] iresp_0_bits_uop_imm_packed; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_pimm; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_imm_sel; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_imm_rename; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_taken; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_pc_lob; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_edge_inst; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_ftq_idx; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_mov; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_rocc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_eret; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_amo; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_sfence; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_fencei; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_fence; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_sfb; // @[lsu.scala:1477:19] wire [3:0] iresp_0_bits_uop_br_type; // @[lsu.scala:1477:19] wire [3:0] iresp_0_bits_uop_br_tag; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_dis_col_sel; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_issued; // @[lsu.scala:1477:19] wire [39:0] iresp_0_bits_uop_debug_pc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_rvc; // @[lsu.scala:1477:19] wire [31:0] iresp_0_bits_uop_debug_inst; // @[lsu.scala:1477:19] wire [31:0] iresp_0_bits_uop_inst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_9; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_8; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_7; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_6; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_5; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_4; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_3; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_2; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_1; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_0; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_3; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_2; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_1; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_0; // @[lsu.scala:1477:19] wire [63:0] wb_ldst_forward_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] wb_ldst_forward_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [15:0] wb_ldst_forward_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_observed; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_order_fail; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_succeeded; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_executed; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] wb_ldst_forward_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] wb_ldst_forward_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] wb_ldst_forward_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] wb_ldst_forward_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] wb_ldst_forward_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] wb_ldst_forward_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire [2:0] s_uop_1_debug_tsrc; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_debug_fsrc; // @[lsu.scala:1093:25] wire s_uop_1_bp_xcpt_if; // @[lsu.scala:1093:25] wire s_uop_1_bp_debug_if; // @[lsu.scala:1093:25] wire s_uop_1_xcpt_ma_if; // @[lsu.scala:1093:25] wire s_uop_1_xcpt_ae_if; // @[lsu.scala:1093:25] wire s_uop_1_xcpt_pf_if; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_fp_typ; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_fp_rm; // @[lsu.scala:1093:25] wire s_uop_1_fp_val; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_fcn_op; // @[lsu.scala:1093:25] wire s_uop_1_fcn_dw; // @[lsu.scala:1093:25] wire s_uop_1_frs3_en; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_lrs2_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_lrs1_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_dst_rtype; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_lrs3; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_lrs2; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_lrs1; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_ldst; // @[lsu.scala:1093:25] wire s_uop_1_ldst_is_rs1; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_csr_cmd; // @[lsu.scala:1093:25] wire s_uop_1_flush_on_commit; // @[lsu.scala:1093:25] wire s_uop_1_is_unique; // @[lsu.scala:1093:25] wire s_uop_1_uses_stq; // @[lsu.scala:1093:25] wire s_uop_1_uses_ldq; // @[lsu.scala:1093:25] wire s_uop_1_mem_signed; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_mem_size; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_mem_cmd; // @[lsu.scala:1093:25] wire [63:0] s_uop_1_exc_cause; // @[lsu.scala:1093:25] wire s_uop_1_exception; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_stale_pdst; // @[lsu.scala:1093:25] wire s_uop_1_ppred_busy; // @[lsu.scala:1093:25] wire s_uop_1_prs3_busy; // @[lsu.scala:1093:25] wire s_uop_1_prs2_busy; // @[lsu.scala:1093:25] wire s_uop_1_prs1_busy; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_ppred; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_prs3; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_prs2; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_prs1; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_pdst; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_rxq_idx; // @[lsu.scala:1093:25] wire [3:0] s_uop_1_stq_idx; // @[lsu.scala:1093:25] wire [3:0] s_uop_1_ldq_idx; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_rob_idx; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_op2_sel; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_op1_sel; // @[lsu.scala:1093:25] wire [19:0] s_uop_1_imm_packed; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_pimm; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_imm_sel; // @[lsu.scala:1093:25] wire s_uop_1_imm_rename; // @[lsu.scala:1093:25] wire s_uop_1_taken; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_pc_lob; // @[lsu.scala:1093:25] wire s_uop_1_edge_inst; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_ftq_idx; // @[lsu.scala:1093:25] wire s_uop_1_is_mov; // @[lsu.scala:1093:25] wire s_uop_1_is_rocc; // @[lsu.scala:1093:25] wire s_uop_1_is_sys_pc2epc; // @[lsu.scala:1093:25] wire s_uop_1_is_eret; // @[lsu.scala:1093:25] wire s_uop_1_is_amo; // @[lsu.scala:1093:25] wire s_uop_1_is_sfence; // @[lsu.scala:1093:25] wire s_uop_1_is_fencei; // @[lsu.scala:1093:25] wire s_uop_1_is_fence; // @[lsu.scala:1093:25] wire s_uop_1_is_sfb; // @[lsu.scala:1093:25] wire [3:0] s_uop_1_br_type; // @[lsu.scala:1093:25] wire [3:0] s_uop_1_br_tag; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_dis_col_sel; // @[lsu.scala:1093:25] wire s_uop_1_iw_p3_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_1_iw_p2_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_1_iw_p1_bypass_hint; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_iw_p2_speculative_child; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_iw_p1_speculative_child; // @[lsu.scala:1093:25] wire s_uop_1_iw_issued_partial_dgen; // @[lsu.scala:1093:25] wire s_uop_1_iw_issued_partial_agen; // @[lsu.scala:1093:25] wire s_uop_1_iw_issued; // @[lsu.scala:1093:25] wire [39:0] s_uop_1_debug_pc; // @[lsu.scala:1093:25] wire s_uop_1_is_rvc; // @[lsu.scala:1093:25] wire [31:0] s_uop_1_debug_inst; // @[lsu.scala:1093:25] wire [31:0] s_uop_1_inst; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_vec; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_wflags; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_sqrt; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_div; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_fma; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_toint; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_fromint; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_swap23; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_swap12; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ren3; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ren2; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ren1; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_wen; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ldst; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_9; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_8; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_7; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_6; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_5; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_4; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_3; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_2; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_1; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_0; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_3; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_2; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_1; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_0; // @[lsu.scala:1093:25] wire [2:0] s_uop_debug_tsrc; // @[lsu.scala:1093:25] wire [2:0] s_uop_debug_fsrc; // @[lsu.scala:1093:25] wire s_uop_bp_xcpt_if; // @[lsu.scala:1093:25] wire s_uop_bp_debug_if; // @[lsu.scala:1093:25] wire s_uop_xcpt_ma_if; // @[lsu.scala:1093:25] wire s_uop_xcpt_ae_if; // @[lsu.scala:1093:25] wire s_uop_xcpt_pf_if; // @[lsu.scala:1093:25] wire [1:0] s_uop_fp_typ; // @[lsu.scala:1093:25] wire [2:0] s_uop_fp_rm; // @[lsu.scala:1093:25] wire s_uop_fp_val; // @[lsu.scala:1093:25] wire [4:0] s_uop_fcn_op; // @[lsu.scala:1093:25] wire s_uop_fcn_dw; // @[lsu.scala:1093:25] wire s_uop_frs3_en; // @[lsu.scala:1093:25] wire [1:0] s_uop_lrs2_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_lrs1_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_dst_rtype; // @[lsu.scala:1093:25] wire [5:0] s_uop_lrs3; // @[lsu.scala:1093:25] wire [5:0] s_uop_lrs2; // @[lsu.scala:1093:25] wire [5:0] s_uop_lrs1; // @[lsu.scala:1093:25] wire [5:0] s_uop_ldst; // @[lsu.scala:1093:25] wire s_uop_ldst_is_rs1; // @[lsu.scala:1093:25] wire [2:0] s_uop_csr_cmd; // @[lsu.scala:1093:25] wire s_uop_flush_on_commit; // @[lsu.scala:1093:25] wire s_uop_is_unique; // @[lsu.scala:1093:25] wire s_uop_uses_stq; // @[lsu.scala:1093:25] wire s_uop_uses_ldq; // @[lsu.scala:1093:25] wire s_uop_mem_signed; // @[lsu.scala:1093:25] wire [1:0] s_uop_mem_size; // @[lsu.scala:1093:25] wire [4:0] s_uop_mem_cmd; // @[lsu.scala:1093:25] wire [63:0] s_uop_exc_cause; // @[lsu.scala:1093:25] wire s_uop_exception; // @[lsu.scala:1093:25] wire [6:0] s_uop_stale_pdst; // @[lsu.scala:1093:25] wire s_uop_ppred_busy; // @[lsu.scala:1093:25] wire s_uop_prs3_busy; // @[lsu.scala:1093:25] wire s_uop_prs2_busy; // @[lsu.scala:1093:25] wire s_uop_prs1_busy; // @[lsu.scala:1093:25] wire [4:0] s_uop_ppred; // @[lsu.scala:1093:25] wire [6:0] s_uop_prs3; // @[lsu.scala:1093:25] wire [6:0] s_uop_prs2; // @[lsu.scala:1093:25] wire [6:0] s_uop_prs1; // @[lsu.scala:1093:25] wire [6:0] s_uop_pdst; // @[lsu.scala:1093:25] wire [1:0] s_uop_rxq_idx; // @[lsu.scala:1093:25] wire [3:0] s_uop_stq_idx; // @[lsu.scala:1093:25] wire [3:0] s_uop_ldq_idx; // @[lsu.scala:1093:25] wire [5:0] s_uop_rob_idx; // @[lsu.scala:1093:25] wire [2:0] s_uop_op2_sel; // @[lsu.scala:1093:25] wire [1:0] s_uop_op1_sel; // @[lsu.scala:1093:25] wire [19:0] s_uop_imm_packed; // @[lsu.scala:1093:25] wire [4:0] s_uop_pimm; // @[lsu.scala:1093:25] wire [2:0] s_uop_imm_sel; // @[lsu.scala:1093:25] wire s_uop_imm_rename; // @[lsu.scala:1093:25] wire s_uop_taken; // @[lsu.scala:1093:25] wire [5:0] s_uop_pc_lob; // @[lsu.scala:1093:25] wire s_uop_edge_inst; // @[lsu.scala:1093:25] wire [4:0] s_uop_ftq_idx; // @[lsu.scala:1093:25] wire s_uop_is_mov; // @[lsu.scala:1093:25] wire s_uop_is_rocc; // @[lsu.scala:1093:25] wire s_uop_is_sys_pc2epc; // @[lsu.scala:1093:25] wire s_uop_is_eret; // @[lsu.scala:1093:25] wire s_uop_is_amo; // @[lsu.scala:1093:25] wire s_uop_is_sfence; // @[lsu.scala:1093:25] wire s_uop_is_fencei; // @[lsu.scala:1093:25] wire s_uop_is_fence; // @[lsu.scala:1093:25] wire s_uop_is_sfb; // @[lsu.scala:1093:25] wire [3:0] s_uop_br_type; // @[lsu.scala:1093:25] wire [3:0] s_uop_br_tag; // @[lsu.scala:1093:25] wire [1:0] s_uop_dis_col_sel; // @[lsu.scala:1093:25] wire s_uop_iw_p3_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_iw_p2_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_iw_p1_bypass_hint; // @[lsu.scala:1093:25] wire [1:0] s_uop_iw_p2_speculative_child; // @[lsu.scala:1093:25] wire [1:0] s_uop_iw_p1_speculative_child; // @[lsu.scala:1093:25] wire s_uop_iw_issued_partial_dgen; // @[lsu.scala:1093:25] wire s_uop_iw_issued_partial_agen; // @[lsu.scala:1093:25] wire s_uop_iw_issued; // @[lsu.scala:1093:25] wire [39:0] s_uop_debug_pc; // @[lsu.scala:1093:25] wire s_uop_is_rvc; // @[lsu.scala:1093:25] wire [31:0] s_uop_debug_inst; // @[lsu.scala:1093:25] wire [31:0] s_uop_inst; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_vec; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_wflags; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_sqrt; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_div; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_fma; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_fastpipe; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_toint; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_fromint; // @[lsu.scala:1093:25] wire [1:0] s_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1093:25] wire [1:0] s_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_swap23; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_swap12; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ren3; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ren2; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ren1; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_wen; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ldst; // @[lsu.scala:1093:25] wire s_uop_fu_code_9; // @[lsu.scala:1093:25] wire s_uop_fu_code_8; // @[lsu.scala:1093:25] wire s_uop_fu_code_7; // @[lsu.scala:1093:25] wire s_uop_fu_code_6; // @[lsu.scala:1093:25] wire s_uop_fu_code_5; // @[lsu.scala:1093:25] wire s_uop_fu_code_4; // @[lsu.scala:1093:25] wire s_uop_fu_code_3; // @[lsu.scala:1093:25] wire s_uop_fu_code_2; // @[lsu.scala:1093:25] wire s_uop_fu_code_1; // @[lsu.scala:1093:25] wire s_uop_fu_code_0; // @[lsu.scala:1093:25] wire s_uop_iq_type_3; // @[lsu.scala:1093:25] wire s_uop_iq_type_2; // @[lsu.scala:1093:25] wire s_uop_iq_type_1; // @[lsu.scala:1093:25] wire s_uop_iq_type_0; // @[lsu.scala:1093:25] wire [63:0] mem_stq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_cleared; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_can_execute; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_succeeded; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_committed; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] mem_stq_retry_e_e_bits_data_bits; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] mem_stq_retry_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] mem_stq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [3:0] mem_stq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [3:0] mem_stq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] mem_stq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] mem_stq_retry_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] mem_stq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] mem_stq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] mem_stq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] mem_stq_retry_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire [63:0] mem_ldq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] mem_ldq_retry_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [15:0] mem_ldq_retry_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_observed; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_order_fail; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_succeeded; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_executed; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] mem_ldq_retry_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] mem_ldq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] mem_ldq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] mem_ldq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] mem_ldq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] mem_ldq_retry_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire mem_stq_incoming_e_out_valid; // @[util.scala:114:23] wire [11:0] mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_valid; // @[util.scala:114:23] wire [11:0] mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire [11:0] mem_incoming_uop_out_br_mask; // @[util.scala:104:23] wire [11:0] mem_xcpt_uops_out_br_mask; // @[util.scala:104:23] wire [63:0] stq_enq_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_cleared; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_can_execute; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_succeeded; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_committed; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] stq_enq_e_e_bits_data_bits; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] stq_enq_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] stq_enq_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [3:0] stq_enq_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [3:0] stq_enq_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] stq_enq_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] stq_enq_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] stq_enq_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [11:0] stq_enq_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] stq_enq_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] stq_enq_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] stq_enq_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_valid; // @[lsu.scala:262:17] wire [63:0] stq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_cleared; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_can_execute; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_committed; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] stq_enq_retry_e_e_bits_data_bits; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] stq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] stq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [3:0] stq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [3:0] stq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] stq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] stq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] stq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [11:0] stq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] stq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] stq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] stq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire ldq_enq_retry_e_e_valid; // @[lsu.scala:233:17] wire [63:0] ldq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] ldq_enq_retry_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [15:0] ldq_enq_retry_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_observed; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_order_fail; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_executed; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] ldq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] ldq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] ldq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [11:0] ldq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] ldq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] ldq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] ldq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_valid; // @[lsu.scala:233:17] wire [63:0] ldq_wakeup_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] ldq_wakeup_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [15:0] ldq_wakeup_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_observed; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_order_fail; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_succeeded; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_executed; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] ldq_wakeup_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] ldq_wakeup_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] ldq_wakeup_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [11:0] ldq_wakeup_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] ldq_wakeup_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] ldq_wakeup_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] ldq_wakeup_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire stq_incoming_e_e_valid; // @[lsu.scala:262:17] wire [63:0] stq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_cleared; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_can_execute; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_succeeded; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_committed; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] stq_incoming_e_e_bits_data_bits; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] stq_incoming_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] stq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [3:0] stq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [3:0] stq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] stq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] stq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] stq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [11:0] stq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] stq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] stq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] stq_incoming_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire ldq_incoming_e_e_valid; // @[lsu.scala:233:17] wire [63:0] ldq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] ldq_incoming_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [15:0] ldq_incoming_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_observed; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_order_fail; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_succeeded; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_executed; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] ldq_incoming_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] ldq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] ldq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [11:0] ldq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] ldq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] ldq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] ldq_incoming_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire _logic_1_io_found; // @[lsu.scala:1965:23] wire [3:0] _logic_1_io_found_idx; // @[lsu.scala:1965:23] wire _logic_io_found; // @[lsu.scala:1965:23] wire [3:0] _logic_io_found_idx; // @[lsu.scala:1965:23] wire _wakeupArbs_0_io_in_1_ready; // @[lsu.scala:1016:47] wire _stq_execute_queue_io_enq_ready; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_valid; // @[lsu.scala:558:11] wire [31:0] _stq_execute_queue_io_deq_bits_uop_inst; // @[lsu.scala:558:11] wire [31:0] _stq_execute_queue_io_deq_bits_uop_debug_inst; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_rvc; // @[lsu.scala:558:11] wire [39:0] _stq_execute_queue_io_deq_bits_uop_debug_pc; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_0; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_1; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_2; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_3; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_0; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_1; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_2; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_3; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_4; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_5; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_6; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_7; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_8; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_9; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_issued; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_agen; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_iw_p1_speculative_child; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_iw_p2_speculative_child; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_dis_col_sel; // @[lsu.scala:558:11] wire [11:0] _stq_execute_queue_io_deq_bits_uop_br_mask; // @[lsu.scala:558:11] wire [3:0] _stq_execute_queue_io_deq_bits_uop_br_tag; // @[lsu.scala:558:11] wire [3:0] _stq_execute_queue_io_deq_bits_uop_br_type; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_sfb; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_fence; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_fencei; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_sfence; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_amo; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_eret; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_sys_pc2epc; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_rocc; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_mov; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_ftq_idx; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_edge_inst; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_pc_lob; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_taken; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_imm_rename; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_imm_sel; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_pimm; // @[lsu.scala:558:11] wire [19:0] _stq_execute_queue_io_deq_bits_uop_imm_packed; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_op1_sel; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_op2_sel; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ldst; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wen; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren1; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren2; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren3; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap12; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap23; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fromint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_toint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fma; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_div; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wflags; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_vec; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_rob_idx; // @[lsu.scala:558:11] wire [3:0] _stq_execute_queue_io_deq_bits_uop_ldq_idx; // @[lsu.scala:558:11] wire [3:0] _stq_execute_queue_io_deq_bits_uop_stq_idx; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_rxq_idx; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_pdst; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_prs1; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_prs2; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_prs3; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_ppred; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_prs1_busy; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_prs2_busy; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_prs3_busy; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_ppred_busy; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_stale_pdst; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_exception; // @[lsu.scala:558:11] wire [63:0] _stq_execute_queue_io_deq_bits_uop_exc_cause; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_mem_cmd; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_mem_size; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_mem_signed; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_unique; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_flush_on_commit; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_csr_cmd; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_ldst_is_rs1; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_ldst; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_lrs1; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_lrs2; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_lrs3; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_dst_rtype; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_lrs1_rtype; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_lrs2_rtype; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_frs3_en; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fcn_dw; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_fcn_op; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_val; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_fp_rm; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_fp_typ; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_xcpt_pf_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_xcpt_ae_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_xcpt_ma_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_bp_debug_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_bp_xcpt_if; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_debug_fsrc; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_debug_tsrc; // @[lsu.scala:558:11] wire [39:0] _stq_execute_queue_io_deq_bits_addr_bits; // @[lsu.scala:558:11] wire [63:0] _stq_execute_queue_io_deq_bits_data_bits; // @[lsu.scala:558:11] wire _retry_queue_io_enq_ready; // @[lsu.scala:533:27] wire _retry_queue_io_deq_valid; // @[lsu.scala:533:27] wire [31:0] _retry_queue_io_deq_bits_uop_inst; // @[lsu.scala:533:27] wire [31:0] _retry_queue_io_deq_bits_uop_debug_inst; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_rvc; // @[lsu.scala:533:27] wire [39:0] _retry_queue_io_deq_bits_uop_debug_pc; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_0; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_1; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_2; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_3; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_0; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_1; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_2; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_3; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_4; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_5; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_6; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_7; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_8; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_9; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_issued; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_issued_partial_agen; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_iw_p1_speculative_child; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_iw_p2_speculative_child; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_dis_col_sel; // @[lsu.scala:533:27] wire [11:0] _retry_queue_io_deq_bits_uop_br_mask; // @[lsu.scala:533:27] wire [3:0] _retry_queue_io_deq_bits_uop_br_tag; // @[lsu.scala:533:27] wire [3:0] _retry_queue_io_deq_bits_uop_br_type; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_sfb; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_fence; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_fencei; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_sfence; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_amo; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_eret; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_sys_pc2epc; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_rocc; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_mov; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_ftq_idx; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_edge_inst; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_pc_lob; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_taken; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_imm_rename; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_imm_sel; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_pimm; // @[lsu.scala:533:27] wire [19:0] _retry_queue_io_deq_bits_uop_imm_packed; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_op1_sel; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_op2_sel; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ldst; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_wen; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ren1; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ren2; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ren3; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_swap12; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_swap23; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_fromint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_toint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_fma; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_div; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_wflags; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_vec; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_rob_idx; // @[lsu.scala:533:27] wire [3:0] _retry_queue_io_deq_bits_uop_ldq_idx; // @[lsu.scala:533:27] wire [3:0] _retry_queue_io_deq_bits_uop_stq_idx; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_rxq_idx; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_pdst; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_prs1; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_prs2; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_prs3; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_ppred; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_prs1_busy; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_prs2_busy; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_prs3_busy; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_ppred_busy; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_stale_pdst; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_exception; // @[lsu.scala:533:27] wire [63:0] _retry_queue_io_deq_bits_uop_exc_cause; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_mem_cmd; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_mem_size; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_mem_signed; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_unique; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_flush_on_commit; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_csr_cmd; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_ldst_is_rs1; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_ldst; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_lrs1; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_lrs2; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_lrs3; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_dst_rtype; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_lrs1_rtype; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_lrs2_rtype; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_frs3_en; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fcn_dw; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_fcn_op; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_val; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_fp_rm; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_fp_typ; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_xcpt_pf_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_xcpt_ae_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_xcpt_ma_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_bp_debug_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_bp_xcpt_if; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_debug_fsrc; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_debug_tsrc; // @[lsu.scala:533:27] wire [63:0] _retry_queue_io_deq_bits_data; // @[lsu.scala:533:27] wire [31:0] _dtlb_io_resp_0_paddr; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_pf_ld; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_pf_st; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ae_ld; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ae_st; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ma_ld; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ma_st; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_cacheable; // @[lsu.scala:308:20] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[lsu.scala:211:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[lsu.scala:211:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[lsu.scala:211:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[lsu.scala:211:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[lsu.scala:211:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[lsu.scala:211:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[lsu.scala:211:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[lsu.scala:211:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[lsu.scala:211:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[lsu.scala:211:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[lsu.scala:211:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[lsu.scala:211:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[lsu.scala:211:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[lsu.scala:211:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[lsu.scala:211:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[lsu.scala:211:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[lsu.scala:211:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[lsu.scala:211:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[lsu.scala:211:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[lsu.scala:211:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[lsu.scala:211:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[lsu.scala:211:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[lsu.scala:211:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[lsu.scala:211:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[lsu.scala:211:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[lsu.scala:211:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[lsu.scala:211:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[lsu.scala:211:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[lsu.scala:211:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[lsu.scala:211:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[lsu.scala:211:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[lsu.scala:211:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[lsu.scala:211:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[lsu.scala:211:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[lsu.scala:211:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[lsu.scala:211:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[lsu.scala:211:7] wire io_core_agen_0_valid_0 = io_core_agen_0_valid; // @[lsu.scala:211:7] wire [31:0] io_core_agen_0_bits_uop_inst_0 = io_core_agen_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_agen_0_bits_uop_debug_inst_0 = io_core_agen_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_rvc_0 = io_core_agen_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_agen_0_bits_uop_debug_pc_0 = io_core_agen_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_0_0 = io_core_agen_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_1_0 = io_core_agen_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_2_0 = io_core_agen_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_3_0 = io_core_agen_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_0_0 = io_core_agen_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_1_0 = io_core_agen_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_2_0 = io_core_agen_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_3_0 = io_core_agen_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_4_0 = io_core_agen_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_5_0 = io_core_agen_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_6_0 = io_core_agen_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_7_0 = io_core_agen_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_8_0 = io_core_agen_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_9_0 = io_core_agen_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_issued_0 = io_core_agen_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_issued_partial_agen_0 = io_core_agen_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_issued_partial_dgen_0 = io_core_agen_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_iw_p1_speculative_child_0 = io_core_agen_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_iw_p2_speculative_child_0 = io_core_agen_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_p1_bypass_hint_0 = io_core_agen_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_p2_bypass_hint_0 = io_core_agen_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_p3_bypass_hint_0 = io_core_agen_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_dis_col_sel_0 = io_core_agen_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_agen_0_bits_uop_br_mask_0 = io_core_agen_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_agen_0_bits_uop_br_tag_0 = io_core_agen_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_agen_0_bits_uop_br_type_0 = io_core_agen_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_sfb_0 = io_core_agen_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_fence_0 = io_core_agen_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_fencei_0 = io_core_agen_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_sfence_0 = io_core_agen_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_amo_0 = io_core_agen_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_eret_0 = io_core_agen_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_sys_pc2epc_0 = io_core_agen_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_rocc_0 = io_core_agen_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_mov_0 = io_core_agen_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_ftq_idx_0 = io_core_agen_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_edge_inst_0 = io_core_agen_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_pc_lob_0 = io_core_agen_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_taken_0 = io_core_agen_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_imm_rename_0 = io_core_agen_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_imm_sel_0 = io_core_agen_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_pimm_0 = io_core_agen_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_agen_0_bits_uop_imm_packed_0 = io_core_agen_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_op1_sel_0 = io_core_agen_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_op2_sel_0 = io_core_agen_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ldst_0 = io_core_agen_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_wen_0 = io_core_agen_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ren1_0 = io_core_agen_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ren2_0 = io_core_agen_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ren3_0 = io_core_agen_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_swap12_0 = io_core_agen_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_swap23_0 = io_core_agen_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagIn_0 = io_core_agen_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagOut_0 = io_core_agen_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_fromint_0 = io_core_agen_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_toint_0 = io_core_agen_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_fastpipe_0 = io_core_agen_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_fma_0 = io_core_agen_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_div_0 = io_core_agen_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_sqrt_0 = io_core_agen_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_wflags_0 = io_core_agen_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_vec_0 = io_core_agen_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_rob_idx_0 = io_core_agen_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_agen_0_bits_uop_ldq_idx_0 = io_core_agen_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_agen_0_bits_uop_stq_idx_0 = io_core_agen_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_rxq_idx_0 = io_core_agen_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_pdst_0 = io_core_agen_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_prs1_0 = io_core_agen_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_prs2_0 = io_core_agen_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_prs3_0 = io_core_agen_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_ppred_0 = io_core_agen_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_prs1_busy_0 = io_core_agen_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_prs2_busy_0 = io_core_agen_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_prs3_busy_0 = io_core_agen_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_ppred_busy_0 = io_core_agen_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_stale_pdst_0 = io_core_agen_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_exception_0 = io_core_agen_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_agen_0_bits_uop_exc_cause_0 = io_core_agen_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_mem_cmd_0 = io_core_agen_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_mem_size_0 = io_core_agen_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_mem_signed_0 = io_core_agen_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_uses_ldq_0 = io_core_agen_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_uses_stq_0 = io_core_agen_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_unique_0 = io_core_agen_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_flush_on_commit_0 = io_core_agen_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_csr_cmd_0 = io_core_agen_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_ldst_is_rs1_0 = io_core_agen_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_ldst_0 = io_core_agen_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_lrs1_0 = io_core_agen_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_lrs2_0 = io_core_agen_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_lrs3_0 = io_core_agen_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_dst_rtype_0 = io_core_agen_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_lrs1_rtype_0 = io_core_agen_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_lrs2_rtype_0 = io_core_agen_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_frs3_en_0 = io_core_agen_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fcn_dw_0 = io_core_agen_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_fcn_op_0 = io_core_agen_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_val_0 = io_core_agen_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_fp_rm_0 = io_core_agen_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_fp_typ_0 = io_core_agen_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_xcpt_pf_if_0 = io_core_agen_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_xcpt_ae_if_0 = io_core_agen_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_xcpt_ma_if_0 = io_core_agen_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_bp_debug_if_0 = io_core_agen_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_bp_xcpt_if_0 = io_core_agen_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_debug_fsrc_0 = io_core_agen_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_debug_tsrc_0 = io_core_agen_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_agen_0_bits_data_0 = io_core_agen_0_bits_data; // @[lsu.scala:211:7] wire io_core_dgen_0_valid_0 = io_core_dgen_0_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_0_bits_uop_inst_0 = io_core_dgen_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_0_bits_uop_debug_inst_0 = io_core_dgen_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_rvc_0 = io_core_dgen_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dgen_0_bits_uop_debug_pc_0 = io_core_dgen_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_0_0 = io_core_dgen_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_1_0 = io_core_dgen_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_2_0 = io_core_dgen_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_3_0 = io_core_dgen_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_0_0 = io_core_dgen_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_1_0 = io_core_dgen_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_2_0 = io_core_dgen_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_3_0 = io_core_dgen_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_4_0 = io_core_dgen_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_5_0 = io_core_dgen_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_6_0 = io_core_dgen_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_7_0 = io_core_dgen_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_8_0 = io_core_dgen_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_9_0 = io_core_dgen_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_issued_0 = io_core_dgen_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_issued_partial_agen_0 = io_core_dgen_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_issued_partial_dgen_0 = io_core_dgen_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_iw_p1_speculative_child_0 = io_core_dgen_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_iw_p2_speculative_child_0 = io_core_dgen_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_p1_bypass_hint_0 = io_core_dgen_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_p2_bypass_hint_0 = io_core_dgen_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_p3_bypass_hint_0 = io_core_dgen_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_dis_col_sel_0 = io_core_dgen_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_dgen_0_bits_uop_br_mask_0 = io_core_dgen_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_0_bits_uop_br_tag_0 = io_core_dgen_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_0_bits_uop_br_type_0 = io_core_dgen_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_sfb_0 = io_core_dgen_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_fence_0 = io_core_dgen_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_fencei_0 = io_core_dgen_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_sfence_0 = io_core_dgen_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_amo_0 = io_core_dgen_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_eret_0 = io_core_dgen_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_sys_pc2epc_0 = io_core_dgen_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_rocc_0 = io_core_dgen_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_mov_0 = io_core_dgen_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_ftq_idx_0 = io_core_dgen_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_edge_inst_0 = io_core_dgen_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_pc_lob_0 = io_core_dgen_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_taken_0 = io_core_dgen_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_imm_rename_0 = io_core_dgen_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_imm_sel_0 = io_core_dgen_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_pimm_0 = io_core_dgen_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dgen_0_bits_uop_imm_packed_0 = io_core_dgen_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_op1_sel_0 = io_core_dgen_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_op2_sel_0 = io_core_dgen_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ldst_0 = io_core_dgen_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_wen_0 = io_core_dgen_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ren1_0 = io_core_dgen_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ren2_0 = io_core_dgen_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ren3_0 = io_core_dgen_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_swap12_0 = io_core_dgen_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_swap23_0 = io_core_dgen_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn_0 = io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut_0 = io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_fromint_0 = io_core_dgen_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_toint_0 = io_core_dgen_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_fastpipe_0 = io_core_dgen_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_fma_0 = io_core_dgen_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_div_0 = io_core_dgen_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_sqrt_0 = io_core_dgen_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_wflags_0 = io_core_dgen_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_vec_0 = io_core_dgen_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_rob_idx_0 = io_core_dgen_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_0_bits_uop_ldq_idx_0 = io_core_dgen_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_0_bits_uop_stq_idx_0 = io_core_dgen_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_rxq_idx_0 = io_core_dgen_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_pdst_0 = io_core_dgen_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_prs1_0 = io_core_dgen_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_prs2_0 = io_core_dgen_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_prs3_0 = io_core_dgen_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_ppred_0 = io_core_dgen_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_prs1_busy_0 = io_core_dgen_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_prs2_busy_0 = io_core_dgen_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_prs3_busy_0 = io_core_dgen_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_ppred_busy_0 = io_core_dgen_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_stale_pdst_0 = io_core_dgen_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_exception_0 = io_core_dgen_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_0_bits_uop_exc_cause_0 = io_core_dgen_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_mem_cmd_0 = io_core_dgen_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_mem_size_0 = io_core_dgen_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_mem_signed_0 = io_core_dgen_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_uses_ldq_0 = io_core_dgen_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_uses_stq_0 = io_core_dgen_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_unique_0 = io_core_dgen_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_flush_on_commit_0 = io_core_dgen_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_csr_cmd_0 = io_core_dgen_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_ldst_is_rs1_0 = io_core_dgen_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_ldst_0 = io_core_dgen_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_lrs1_0 = io_core_dgen_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_lrs2_0 = io_core_dgen_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_lrs3_0 = io_core_dgen_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_dst_rtype_0 = io_core_dgen_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_lrs1_rtype_0 = io_core_dgen_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_lrs2_rtype_0 = io_core_dgen_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_frs3_en_0 = io_core_dgen_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fcn_dw_0 = io_core_dgen_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_fcn_op_0 = io_core_dgen_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_val_0 = io_core_dgen_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_fp_rm_0 = io_core_dgen_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_fp_typ_0 = io_core_dgen_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_xcpt_pf_if_0 = io_core_dgen_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_xcpt_ae_if_0 = io_core_dgen_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_xcpt_ma_if_0 = io_core_dgen_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_bp_debug_if_0 = io_core_dgen_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_bp_xcpt_if_0 = io_core_dgen_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_debug_fsrc_0 = io_core_dgen_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_debug_tsrc_0 = io_core_dgen_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_0_bits_data_0 = io_core_dgen_0_bits_data; // @[lsu.scala:211:7] wire io_core_dgen_1_valid_0 = io_core_dgen_1_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_1_bits_uop_inst_0 = io_core_dgen_1_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_1_bits_uop_debug_inst_0 = io_core_dgen_1_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_rvc_0 = io_core_dgen_1_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dgen_1_bits_uop_debug_pc_0 = io_core_dgen_1_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_0_0 = io_core_dgen_1_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_1_0 = io_core_dgen_1_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_2_0 = io_core_dgen_1_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_3_0 = io_core_dgen_1_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_0_0 = io_core_dgen_1_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_1_0 = io_core_dgen_1_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_2_0 = io_core_dgen_1_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_3_0 = io_core_dgen_1_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_4_0 = io_core_dgen_1_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_5_0 = io_core_dgen_1_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_6_0 = io_core_dgen_1_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_7_0 = io_core_dgen_1_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_8_0 = io_core_dgen_1_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_9_0 = io_core_dgen_1_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_issued_0 = io_core_dgen_1_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_issued_partial_agen_0 = io_core_dgen_1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_issued_partial_dgen_0 = io_core_dgen_1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_iw_p1_speculative_child_0 = io_core_dgen_1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_iw_p2_speculative_child_0 = io_core_dgen_1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_p1_bypass_hint_0 = io_core_dgen_1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_p2_bypass_hint_0 = io_core_dgen_1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_p3_bypass_hint_0 = io_core_dgen_1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_dis_col_sel_0 = io_core_dgen_1_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_dgen_1_bits_uop_br_mask_0 = io_core_dgen_1_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_1_bits_uop_br_tag_0 = io_core_dgen_1_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_1_bits_uop_br_type_0 = io_core_dgen_1_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_sfb_0 = io_core_dgen_1_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_fence_0 = io_core_dgen_1_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_fencei_0 = io_core_dgen_1_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_sfence_0 = io_core_dgen_1_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_amo_0 = io_core_dgen_1_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_eret_0 = io_core_dgen_1_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_sys_pc2epc_0 = io_core_dgen_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_rocc_0 = io_core_dgen_1_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_mov_0 = io_core_dgen_1_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_ftq_idx_0 = io_core_dgen_1_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_edge_inst_0 = io_core_dgen_1_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_pc_lob_0 = io_core_dgen_1_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_taken_0 = io_core_dgen_1_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_imm_rename_0 = io_core_dgen_1_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_imm_sel_0 = io_core_dgen_1_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_pimm_0 = io_core_dgen_1_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dgen_1_bits_uop_imm_packed_0 = io_core_dgen_1_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_op1_sel_0 = io_core_dgen_1_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_op2_sel_0 = io_core_dgen_1_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ldst_0 = io_core_dgen_1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_wen_0 = io_core_dgen_1_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ren1_0 = io_core_dgen_1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ren2_0 = io_core_dgen_1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ren3_0 = io_core_dgen_1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_swap12_0 = io_core_dgen_1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_swap23_0 = io_core_dgen_1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn_0 = io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut_0 = io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_fromint_0 = io_core_dgen_1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_toint_0 = io_core_dgen_1_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_fastpipe_0 = io_core_dgen_1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_fma_0 = io_core_dgen_1_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_div_0 = io_core_dgen_1_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_sqrt_0 = io_core_dgen_1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_wflags_0 = io_core_dgen_1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_vec_0 = io_core_dgen_1_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_rob_idx_0 = io_core_dgen_1_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_1_bits_uop_ldq_idx_0 = io_core_dgen_1_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_1_bits_uop_stq_idx_0 = io_core_dgen_1_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_rxq_idx_0 = io_core_dgen_1_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_pdst_0 = io_core_dgen_1_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_prs1_0 = io_core_dgen_1_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_prs2_0 = io_core_dgen_1_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_prs3_0 = io_core_dgen_1_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_ppred_0 = io_core_dgen_1_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_prs1_busy_0 = io_core_dgen_1_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_prs2_busy_0 = io_core_dgen_1_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_prs3_busy_0 = io_core_dgen_1_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_ppred_busy_0 = io_core_dgen_1_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_stale_pdst_0 = io_core_dgen_1_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_exception_0 = io_core_dgen_1_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_1_bits_uop_exc_cause_0 = io_core_dgen_1_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_mem_cmd_0 = io_core_dgen_1_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_mem_size_0 = io_core_dgen_1_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_mem_signed_0 = io_core_dgen_1_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_uses_ldq_0 = io_core_dgen_1_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_uses_stq_0 = io_core_dgen_1_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_unique_0 = io_core_dgen_1_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_flush_on_commit_0 = io_core_dgen_1_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_csr_cmd_0 = io_core_dgen_1_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_ldst_is_rs1_0 = io_core_dgen_1_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_ldst_0 = io_core_dgen_1_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_lrs1_0 = io_core_dgen_1_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_lrs2_0 = io_core_dgen_1_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_lrs3_0 = io_core_dgen_1_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_dst_rtype_0 = io_core_dgen_1_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_lrs1_rtype_0 = io_core_dgen_1_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_lrs2_rtype_0 = io_core_dgen_1_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_frs3_en_0 = io_core_dgen_1_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fcn_dw_0 = io_core_dgen_1_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_fcn_op_0 = io_core_dgen_1_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_val_0 = io_core_dgen_1_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_fp_rm_0 = io_core_dgen_1_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_fp_typ_0 = io_core_dgen_1_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_xcpt_pf_if_0 = io_core_dgen_1_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_xcpt_ae_if_0 = io_core_dgen_1_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_xcpt_ma_if_0 = io_core_dgen_1_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_bp_debug_if_0 = io_core_dgen_1_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_bp_xcpt_if_0 = io_core_dgen_1_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_debug_fsrc_0 = io_core_dgen_1_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_debug_tsrc_0 = io_core_dgen_1_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_1_bits_data_0 = io_core_dgen_1_bits_data; // @[lsu.scala:211:7] wire io_core_dgen_2_valid_0 = io_core_dgen_2_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_2_bits_uop_inst_0 = io_core_dgen_2_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_2_bits_uop_debug_inst_0 = io_core_dgen_2_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_rvc_0 = io_core_dgen_2_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dgen_2_bits_uop_debug_pc_0 = io_core_dgen_2_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_0_0 = io_core_dgen_2_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_1_0 = io_core_dgen_2_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_2_0 = io_core_dgen_2_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_3_0 = io_core_dgen_2_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_0_0 = io_core_dgen_2_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_1_0 = io_core_dgen_2_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_2_0 = io_core_dgen_2_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_3_0 = io_core_dgen_2_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_4_0 = io_core_dgen_2_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_5_0 = io_core_dgen_2_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_6_0 = io_core_dgen_2_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_7_0 = io_core_dgen_2_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_8_0 = io_core_dgen_2_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_9_0 = io_core_dgen_2_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_issued_0 = io_core_dgen_2_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_issued_partial_agen_0 = io_core_dgen_2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_issued_partial_dgen_0 = io_core_dgen_2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_iw_p1_speculative_child_0 = io_core_dgen_2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_iw_p2_speculative_child_0 = io_core_dgen_2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_p1_bypass_hint_0 = io_core_dgen_2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_p2_bypass_hint_0 = io_core_dgen_2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_p3_bypass_hint_0 = io_core_dgen_2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_dis_col_sel_0 = io_core_dgen_2_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_dgen_2_bits_uop_br_mask_0 = io_core_dgen_2_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_2_bits_uop_br_tag_0 = io_core_dgen_2_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_2_bits_uop_br_type_0 = io_core_dgen_2_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_sfb_0 = io_core_dgen_2_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_fence_0 = io_core_dgen_2_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_fencei_0 = io_core_dgen_2_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_sfence_0 = io_core_dgen_2_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_amo_0 = io_core_dgen_2_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_eret_0 = io_core_dgen_2_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_sys_pc2epc_0 = io_core_dgen_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_rocc_0 = io_core_dgen_2_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_mov_0 = io_core_dgen_2_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_ftq_idx_0 = io_core_dgen_2_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_edge_inst_0 = io_core_dgen_2_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_pc_lob_0 = io_core_dgen_2_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_taken_0 = io_core_dgen_2_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_imm_rename_0 = io_core_dgen_2_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_imm_sel_0 = io_core_dgen_2_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_pimm_0 = io_core_dgen_2_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dgen_2_bits_uop_imm_packed_0 = io_core_dgen_2_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_op1_sel_0 = io_core_dgen_2_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_op2_sel_0 = io_core_dgen_2_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ldst_0 = io_core_dgen_2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_wen_0 = io_core_dgen_2_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ren1_0 = io_core_dgen_2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ren2_0 = io_core_dgen_2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ren3_0 = io_core_dgen_2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_swap12_0 = io_core_dgen_2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_swap23_0 = io_core_dgen_2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn_0 = io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut_0 = io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_fromint_0 = io_core_dgen_2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_toint_0 = io_core_dgen_2_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_fastpipe_0 = io_core_dgen_2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_fma_0 = io_core_dgen_2_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_div_0 = io_core_dgen_2_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_sqrt_0 = io_core_dgen_2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_wflags_0 = io_core_dgen_2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_vec_0 = io_core_dgen_2_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_rob_idx_0 = io_core_dgen_2_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_2_bits_uop_ldq_idx_0 = io_core_dgen_2_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_2_bits_uop_stq_idx_0 = io_core_dgen_2_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_rxq_idx_0 = io_core_dgen_2_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_pdst_0 = io_core_dgen_2_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_prs1_0 = io_core_dgen_2_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_prs2_0 = io_core_dgen_2_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_prs3_0 = io_core_dgen_2_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_ppred_0 = io_core_dgen_2_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_prs1_busy_0 = io_core_dgen_2_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_prs2_busy_0 = io_core_dgen_2_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_prs3_busy_0 = io_core_dgen_2_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_ppred_busy_0 = io_core_dgen_2_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_stale_pdst_0 = io_core_dgen_2_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_exception_0 = io_core_dgen_2_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_2_bits_uop_exc_cause_0 = io_core_dgen_2_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_mem_cmd_0 = io_core_dgen_2_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_mem_size_0 = io_core_dgen_2_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_mem_signed_0 = io_core_dgen_2_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_uses_ldq_0 = io_core_dgen_2_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_uses_stq_0 = io_core_dgen_2_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_unique_0 = io_core_dgen_2_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_flush_on_commit_0 = io_core_dgen_2_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_csr_cmd_0 = io_core_dgen_2_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_ldst_is_rs1_0 = io_core_dgen_2_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_ldst_0 = io_core_dgen_2_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_lrs1_0 = io_core_dgen_2_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_lrs2_0 = io_core_dgen_2_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_lrs3_0 = io_core_dgen_2_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_dst_rtype_0 = io_core_dgen_2_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_lrs1_rtype_0 = io_core_dgen_2_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_lrs2_rtype_0 = io_core_dgen_2_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_frs3_en_0 = io_core_dgen_2_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fcn_dw_0 = io_core_dgen_2_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_fcn_op_0 = io_core_dgen_2_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_val_0 = io_core_dgen_2_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_fp_rm_0 = io_core_dgen_2_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_fp_typ_0 = io_core_dgen_2_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_xcpt_pf_if_0 = io_core_dgen_2_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_xcpt_ae_if_0 = io_core_dgen_2_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_xcpt_ma_if_0 = io_core_dgen_2_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_bp_debug_if_0 = io_core_dgen_2_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_bp_xcpt_if_0 = io_core_dgen_2_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_debug_fsrc_0 = io_core_dgen_2_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_debug_tsrc_0 = io_core_dgen_2_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_2_bits_data_0 = io_core_dgen_2_bits_data; // @[lsu.scala:211:7] wire io_core_sfence_valid_0 = io_core_sfence_valid; // @[lsu.scala:211:7] wire io_core_sfence_bits_rs1_0 = io_core_sfence_bits_rs1; // @[lsu.scala:211:7] wire io_core_sfence_bits_rs2_0 = io_core_sfence_bits_rs2; // @[lsu.scala:211:7] wire [38:0] io_core_sfence_bits_addr_0 = io_core_sfence_bits_addr; // @[lsu.scala:211:7] wire io_core_sfence_bits_asid_0 = io_core_sfence_bits_asid; // @[lsu.scala:211:7] wire io_core_sfence_bits_hv_0 = io_core_sfence_bits_hv; // @[lsu.scala:211:7] wire io_core_sfence_bits_hg_0 = io_core_sfence_bits_hg; // @[lsu.scala:211:7] wire io_core_dis_uops_0_valid_0 = io_core_dis_uops_0_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_0_bits_inst_0 = io_core_dis_uops_0_bits_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_0_bits_debug_inst_0 = io_core_dis_uops_0_bits_debug_inst; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_rvc_0 = io_core_dis_uops_0_bits_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dis_uops_0_bits_debug_pc_0 = io_core_dis_uops_0_bits_debug_pc; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_0_0 = io_core_dis_uops_0_bits_iq_type_0; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_1_0 = io_core_dis_uops_0_bits_iq_type_1; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_2_0 = io_core_dis_uops_0_bits_iq_type_2; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_3_0 = io_core_dis_uops_0_bits_iq_type_3; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_0_0 = io_core_dis_uops_0_bits_fu_code_0; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_1_0 = io_core_dis_uops_0_bits_fu_code_1; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_2_0 = io_core_dis_uops_0_bits_fu_code_2; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_3_0 = io_core_dis_uops_0_bits_fu_code_3; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_4_0 = io_core_dis_uops_0_bits_fu_code_4; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_5_0 = io_core_dis_uops_0_bits_fu_code_5; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_6_0 = io_core_dis_uops_0_bits_fu_code_6; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_7_0 = io_core_dis_uops_0_bits_fu_code_7; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_8_0 = io_core_dis_uops_0_bits_fu_code_8; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_9_0 = io_core_dis_uops_0_bits_fu_code_9; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_issued_0 = io_core_dis_uops_0_bits_iw_issued; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_issued_partial_agen_0 = io_core_dis_uops_0_bits_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_core_dis_uops_0_bits_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_iw_p1_speculative_child_0 = io_core_dis_uops_0_bits_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_iw_p2_speculative_child_0 = io_core_dis_uops_0_bits_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_core_dis_uops_0_bits_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_core_dis_uops_0_bits_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_core_dis_uops_0_bits_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_dis_col_sel_0 = io_core_dis_uops_0_bits_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_dis_uops_0_bits_br_mask_0 = io_core_dis_uops_0_bits_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_0_bits_br_tag_0 = io_core_dis_uops_0_bits_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_0_bits_br_type_0 = io_core_dis_uops_0_bits_br_type; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_sfb_0 = io_core_dis_uops_0_bits_is_sfb; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_fence_0 = io_core_dis_uops_0_bits_is_fence; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_fencei_0 = io_core_dis_uops_0_bits_is_fencei; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_sfence_0 = io_core_dis_uops_0_bits_is_sfence; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_amo_0 = io_core_dis_uops_0_bits_is_amo; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_eret_0 = io_core_dis_uops_0_bits_is_eret; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_sys_pc2epc_0 = io_core_dis_uops_0_bits_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_rocc_0 = io_core_dis_uops_0_bits_is_rocc; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_mov_0 = io_core_dis_uops_0_bits_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_ftq_idx_0 = io_core_dis_uops_0_bits_ftq_idx; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_edge_inst_0 = io_core_dis_uops_0_bits_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_pc_lob_0 = io_core_dis_uops_0_bits_pc_lob; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_taken_0 = io_core_dis_uops_0_bits_taken; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_imm_rename_0 = io_core_dis_uops_0_bits_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_imm_sel_0 = io_core_dis_uops_0_bits_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_pimm_0 = io_core_dis_uops_0_bits_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dis_uops_0_bits_imm_packed_0 = io_core_dis_uops_0_bits_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_op1_sel_0 = io_core_dis_uops_0_bits_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_op2_sel_0 = io_core_dis_uops_0_bits_op2_sel; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ldst_0 = io_core_dis_uops_0_bits_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_wen_0 = io_core_dis_uops_0_bits_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ren1_0 = io_core_dis_uops_0_bits_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ren2_0 = io_core_dis_uops_0_bits_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ren3_0 = io_core_dis_uops_0_bits_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_swap12_0 = io_core_dis_uops_0_bits_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_swap23_0 = io_core_dis_uops_0_bits_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_core_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_core_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_fromint_0 = io_core_dis_uops_0_bits_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_toint_0 = io_core_dis_uops_0_bits_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_core_dis_uops_0_bits_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_fma_0 = io_core_dis_uops_0_bits_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_div_0 = io_core_dis_uops_0_bits_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_core_dis_uops_0_bits_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_wflags_0 = io_core_dis_uops_0_bits_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_vec_0 = io_core_dis_uops_0_bits_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_rob_idx_0 = io_core_dis_uops_0_bits_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_0_bits_ldq_idx_0 = io_core_dis_uops_0_bits_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_0_bits_stq_idx_0 = io_core_dis_uops_0_bits_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_rxq_idx_0 = io_core_dis_uops_0_bits_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_pdst_0 = io_core_dis_uops_0_bits_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_prs1_0 = io_core_dis_uops_0_bits_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_prs2_0 = io_core_dis_uops_0_bits_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_prs3_0 = io_core_dis_uops_0_bits_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_ppred_0 = io_core_dis_uops_0_bits_ppred; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_prs1_busy_0 = io_core_dis_uops_0_bits_prs1_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_prs2_busy_0 = io_core_dis_uops_0_bits_prs2_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_prs3_busy_0 = io_core_dis_uops_0_bits_prs3_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_ppred_busy_0 = io_core_dis_uops_0_bits_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_stale_pdst_0 = io_core_dis_uops_0_bits_stale_pdst; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_exception_0 = io_core_dis_uops_0_bits_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dis_uops_0_bits_exc_cause_0 = io_core_dis_uops_0_bits_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_mem_cmd_0 = io_core_dis_uops_0_bits_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_mem_size_0 = io_core_dis_uops_0_bits_mem_size; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_mem_signed_0 = io_core_dis_uops_0_bits_mem_signed; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_uses_ldq_0 = io_core_dis_uops_0_bits_uses_ldq; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_uses_stq_0 = io_core_dis_uops_0_bits_uses_stq; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_unique_0 = io_core_dis_uops_0_bits_is_unique; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_flush_on_commit_0 = io_core_dis_uops_0_bits_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_csr_cmd_0 = io_core_dis_uops_0_bits_csr_cmd; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_ldst_is_rs1_0 = io_core_dis_uops_0_bits_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_ldst_0 = io_core_dis_uops_0_bits_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_lrs1_0 = io_core_dis_uops_0_bits_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_lrs2_0 = io_core_dis_uops_0_bits_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_lrs3_0 = io_core_dis_uops_0_bits_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_dst_rtype_0 = io_core_dis_uops_0_bits_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_lrs1_rtype_0 = io_core_dis_uops_0_bits_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_lrs2_rtype_0 = io_core_dis_uops_0_bits_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_frs3_en_0 = io_core_dis_uops_0_bits_frs3_en; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fcn_dw_0 = io_core_dis_uops_0_bits_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_fcn_op_0 = io_core_dis_uops_0_bits_fcn_op; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_val_0 = io_core_dis_uops_0_bits_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_fp_rm_0 = io_core_dis_uops_0_bits_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_fp_typ_0 = io_core_dis_uops_0_bits_fp_typ; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_xcpt_pf_if_0 = io_core_dis_uops_0_bits_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_xcpt_ae_if_0 = io_core_dis_uops_0_bits_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_xcpt_ma_if_0 = io_core_dis_uops_0_bits_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_bp_debug_if_0 = io_core_dis_uops_0_bits_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_bp_xcpt_if_0 = io_core_dis_uops_0_bits_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_debug_fsrc_0 = io_core_dis_uops_0_bits_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_debug_tsrc_0 = io_core_dis_uops_0_bits_debug_tsrc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_valid_0 = io_core_dis_uops_1_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_1_bits_inst_0 = io_core_dis_uops_1_bits_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_1_bits_debug_inst_0 = io_core_dis_uops_1_bits_debug_inst; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_rvc_0 = io_core_dis_uops_1_bits_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dis_uops_1_bits_debug_pc_0 = io_core_dis_uops_1_bits_debug_pc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_0_0 = io_core_dis_uops_1_bits_iq_type_0; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_1_0 = io_core_dis_uops_1_bits_iq_type_1; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_2_0 = io_core_dis_uops_1_bits_iq_type_2; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_3_0 = io_core_dis_uops_1_bits_iq_type_3; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_0_0 = io_core_dis_uops_1_bits_fu_code_0; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_1_0 = io_core_dis_uops_1_bits_fu_code_1; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_2_0 = io_core_dis_uops_1_bits_fu_code_2; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_3_0 = io_core_dis_uops_1_bits_fu_code_3; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_4_0 = io_core_dis_uops_1_bits_fu_code_4; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_5_0 = io_core_dis_uops_1_bits_fu_code_5; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_6_0 = io_core_dis_uops_1_bits_fu_code_6; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_7_0 = io_core_dis_uops_1_bits_fu_code_7; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_8_0 = io_core_dis_uops_1_bits_fu_code_8; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_9_0 = io_core_dis_uops_1_bits_fu_code_9; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_issued_0 = io_core_dis_uops_1_bits_iw_issued; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_issued_partial_agen_0 = io_core_dis_uops_1_bits_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_core_dis_uops_1_bits_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_iw_p1_speculative_child_0 = io_core_dis_uops_1_bits_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_iw_p2_speculative_child_0 = io_core_dis_uops_1_bits_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_core_dis_uops_1_bits_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_core_dis_uops_1_bits_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_core_dis_uops_1_bits_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_dis_col_sel_0 = io_core_dis_uops_1_bits_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_dis_uops_1_bits_br_mask_0 = io_core_dis_uops_1_bits_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_1_bits_br_tag_0 = io_core_dis_uops_1_bits_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_1_bits_br_type_0 = io_core_dis_uops_1_bits_br_type; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_sfb_0 = io_core_dis_uops_1_bits_is_sfb; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_fence_0 = io_core_dis_uops_1_bits_is_fence; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_fencei_0 = io_core_dis_uops_1_bits_is_fencei; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_sfence_0 = io_core_dis_uops_1_bits_is_sfence; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_amo_0 = io_core_dis_uops_1_bits_is_amo; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_eret_0 = io_core_dis_uops_1_bits_is_eret; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_sys_pc2epc_0 = io_core_dis_uops_1_bits_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_rocc_0 = io_core_dis_uops_1_bits_is_rocc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_mov_0 = io_core_dis_uops_1_bits_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_ftq_idx_0 = io_core_dis_uops_1_bits_ftq_idx; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_edge_inst_0 = io_core_dis_uops_1_bits_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_pc_lob_0 = io_core_dis_uops_1_bits_pc_lob; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_taken_0 = io_core_dis_uops_1_bits_taken; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_imm_rename_0 = io_core_dis_uops_1_bits_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_imm_sel_0 = io_core_dis_uops_1_bits_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_pimm_0 = io_core_dis_uops_1_bits_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dis_uops_1_bits_imm_packed_0 = io_core_dis_uops_1_bits_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_op1_sel_0 = io_core_dis_uops_1_bits_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_op2_sel_0 = io_core_dis_uops_1_bits_op2_sel; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ldst_0 = io_core_dis_uops_1_bits_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_wen_0 = io_core_dis_uops_1_bits_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ren1_0 = io_core_dis_uops_1_bits_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ren2_0 = io_core_dis_uops_1_bits_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ren3_0 = io_core_dis_uops_1_bits_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_swap12_0 = io_core_dis_uops_1_bits_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_swap23_0 = io_core_dis_uops_1_bits_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_core_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_core_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_fromint_0 = io_core_dis_uops_1_bits_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_toint_0 = io_core_dis_uops_1_bits_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_core_dis_uops_1_bits_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_fma_0 = io_core_dis_uops_1_bits_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_div_0 = io_core_dis_uops_1_bits_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_core_dis_uops_1_bits_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_wflags_0 = io_core_dis_uops_1_bits_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_vec_0 = io_core_dis_uops_1_bits_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_rob_idx_0 = io_core_dis_uops_1_bits_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_1_bits_ldq_idx_0 = io_core_dis_uops_1_bits_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_1_bits_stq_idx_0 = io_core_dis_uops_1_bits_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_rxq_idx_0 = io_core_dis_uops_1_bits_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_pdst_0 = io_core_dis_uops_1_bits_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_prs1_0 = io_core_dis_uops_1_bits_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_prs2_0 = io_core_dis_uops_1_bits_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_prs3_0 = io_core_dis_uops_1_bits_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_ppred_0 = io_core_dis_uops_1_bits_ppred; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_prs1_busy_0 = io_core_dis_uops_1_bits_prs1_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_prs2_busy_0 = io_core_dis_uops_1_bits_prs2_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_prs3_busy_0 = io_core_dis_uops_1_bits_prs3_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_ppred_busy_0 = io_core_dis_uops_1_bits_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_stale_pdst_0 = io_core_dis_uops_1_bits_stale_pdst; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_exception_0 = io_core_dis_uops_1_bits_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dis_uops_1_bits_exc_cause_0 = io_core_dis_uops_1_bits_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_mem_cmd_0 = io_core_dis_uops_1_bits_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_mem_size_0 = io_core_dis_uops_1_bits_mem_size; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_mem_signed_0 = io_core_dis_uops_1_bits_mem_signed; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_uses_ldq_0 = io_core_dis_uops_1_bits_uses_ldq; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_uses_stq_0 = io_core_dis_uops_1_bits_uses_stq; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_unique_0 = io_core_dis_uops_1_bits_is_unique; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_flush_on_commit_0 = io_core_dis_uops_1_bits_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_csr_cmd_0 = io_core_dis_uops_1_bits_csr_cmd; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_ldst_is_rs1_0 = io_core_dis_uops_1_bits_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_ldst_0 = io_core_dis_uops_1_bits_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_lrs1_0 = io_core_dis_uops_1_bits_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_lrs2_0 = io_core_dis_uops_1_bits_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_lrs3_0 = io_core_dis_uops_1_bits_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_dst_rtype_0 = io_core_dis_uops_1_bits_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_lrs1_rtype_0 = io_core_dis_uops_1_bits_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_lrs2_rtype_0 = io_core_dis_uops_1_bits_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_frs3_en_0 = io_core_dis_uops_1_bits_frs3_en; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fcn_dw_0 = io_core_dis_uops_1_bits_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_fcn_op_0 = io_core_dis_uops_1_bits_fcn_op; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_val_0 = io_core_dis_uops_1_bits_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_fp_rm_0 = io_core_dis_uops_1_bits_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_fp_typ_0 = io_core_dis_uops_1_bits_fp_typ; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_xcpt_pf_if_0 = io_core_dis_uops_1_bits_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_xcpt_ae_if_0 = io_core_dis_uops_1_bits_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_xcpt_ma_if_0 = io_core_dis_uops_1_bits_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_bp_debug_if_0 = io_core_dis_uops_1_bits_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_bp_xcpt_if_0 = io_core_dis_uops_1_bits_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_debug_fsrc_0 = io_core_dis_uops_1_bits_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_debug_tsrc_0 = io_core_dis_uops_1_bits_debug_tsrc; // @[lsu.scala:211:7] wire io_core_commit_valids_0_0 = io_core_commit_valids_0; // @[lsu.scala:211:7] wire io_core_commit_valids_1_0 = io_core_commit_valids_1; // @[lsu.scala:211:7] wire io_core_commit_arch_valids_0_0 = io_core_commit_arch_valids_0; // @[lsu.scala:211:7] wire io_core_commit_arch_valids_1_0 = io_core_commit_arch_valids_1; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_0_inst_0 = io_core_commit_uops_0_inst; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_0_debug_inst_0 = io_core_commit_uops_0_debug_inst; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_rvc_0 = io_core_commit_uops_0_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_commit_uops_0_debug_pc_0 = io_core_commit_uops_0_debug_pc; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_0_0 = io_core_commit_uops_0_iq_type_0; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_1_0 = io_core_commit_uops_0_iq_type_1; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_2_0 = io_core_commit_uops_0_iq_type_2; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_3_0 = io_core_commit_uops_0_iq_type_3; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_0_0 = io_core_commit_uops_0_fu_code_0; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_1_0 = io_core_commit_uops_0_fu_code_1; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_2_0 = io_core_commit_uops_0_fu_code_2; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_3_0 = io_core_commit_uops_0_fu_code_3; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_4_0 = io_core_commit_uops_0_fu_code_4; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_5_0 = io_core_commit_uops_0_fu_code_5; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_6_0 = io_core_commit_uops_0_fu_code_6; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_7_0 = io_core_commit_uops_0_fu_code_7; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_8_0 = io_core_commit_uops_0_fu_code_8; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_9_0 = io_core_commit_uops_0_fu_code_9; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_issued_0 = io_core_commit_uops_0_iw_issued; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_issued_partial_agen_0 = io_core_commit_uops_0_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_issued_partial_dgen_0 = io_core_commit_uops_0_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_iw_p1_speculative_child_0 = io_core_commit_uops_0_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_iw_p2_speculative_child_0 = io_core_commit_uops_0_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_p1_bypass_hint_0 = io_core_commit_uops_0_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_p2_bypass_hint_0 = io_core_commit_uops_0_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_p3_bypass_hint_0 = io_core_commit_uops_0_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_dis_col_sel_0 = io_core_commit_uops_0_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_commit_uops_0_br_mask_0 = io_core_commit_uops_0_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_0_br_tag_0 = io_core_commit_uops_0_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_0_br_type_0 = io_core_commit_uops_0_br_type; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_sfb_0 = io_core_commit_uops_0_is_sfb; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_fence_0 = io_core_commit_uops_0_is_fence; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_fencei_0 = io_core_commit_uops_0_is_fencei; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_sfence_0 = io_core_commit_uops_0_is_sfence; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_amo_0 = io_core_commit_uops_0_is_amo; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_eret_0 = io_core_commit_uops_0_is_eret; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_sys_pc2epc_0 = io_core_commit_uops_0_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_rocc_0 = io_core_commit_uops_0_is_rocc; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_mov_0 = io_core_commit_uops_0_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_ftq_idx_0 = io_core_commit_uops_0_ftq_idx; // @[lsu.scala:211:7] wire io_core_commit_uops_0_edge_inst_0 = io_core_commit_uops_0_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_pc_lob_0 = io_core_commit_uops_0_pc_lob; // @[lsu.scala:211:7] wire io_core_commit_uops_0_taken_0 = io_core_commit_uops_0_taken; // @[lsu.scala:211:7] wire io_core_commit_uops_0_imm_rename_0 = io_core_commit_uops_0_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_imm_sel_0 = io_core_commit_uops_0_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_pimm_0 = io_core_commit_uops_0_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_commit_uops_0_imm_packed_0 = io_core_commit_uops_0_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_op1_sel_0 = io_core_commit_uops_0_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_op2_sel_0 = io_core_commit_uops_0_op2_sel; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ldst_0 = io_core_commit_uops_0_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_wen_0 = io_core_commit_uops_0_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ren1_0 = io_core_commit_uops_0_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ren2_0 = io_core_commit_uops_0_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ren3_0 = io_core_commit_uops_0_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_swap12_0 = io_core_commit_uops_0_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_swap23_0 = io_core_commit_uops_0_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_fp_ctrl_typeTagIn_0 = io_core_commit_uops_0_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_fp_ctrl_typeTagOut_0 = io_core_commit_uops_0_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_fromint_0 = io_core_commit_uops_0_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_toint_0 = io_core_commit_uops_0_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_fastpipe_0 = io_core_commit_uops_0_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_fma_0 = io_core_commit_uops_0_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_div_0 = io_core_commit_uops_0_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_sqrt_0 = io_core_commit_uops_0_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_wflags_0 = io_core_commit_uops_0_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_vec_0 = io_core_commit_uops_0_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_rob_idx_0 = io_core_commit_uops_0_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_0_ldq_idx_0 = io_core_commit_uops_0_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_0_stq_idx_0 = io_core_commit_uops_0_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_rxq_idx_0 = io_core_commit_uops_0_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_pdst_0 = io_core_commit_uops_0_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_prs1_0 = io_core_commit_uops_0_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_prs2_0 = io_core_commit_uops_0_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_prs3_0 = io_core_commit_uops_0_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_ppred_0 = io_core_commit_uops_0_ppred; // @[lsu.scala:211:7] wire io_core_commit_uops_0_prs1_busy_0 = io_core_commit_uops_0_prs1_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_0_prs2_busy_0 = io_core_commit_uops_0_prs2_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_0_prs3_busy_0 = io_core_commit_uops_0_prs3_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_0_ppred_busy_0 = io_core_commit_uops_0_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_stale_pdst_0 = io_core_commit_uops_0_stale_pdst; // @[lsu.scala:211:7] wire io_core_commit_uops_0_exception_0 = io_core_commit_uops_0_exception; // @[lsu.scala:211:7] wire [63:0] io_core_commit_uops_0_exc_cause_0 = io_core_commit_uops_0_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_mem_cmd_0 = io_core_commit_uops_0_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_mem_size_0 = io_core_commit_uops_0_mem_size; // @[lsu.scala:211:7] wire io_core_commit_uops_0_mem_signed_0 = io_core_commit_uops_0_mem_signed; // @[lsu.scala:211:7] wire io_core_commit_uops_0_uses_ldq_0 = io_core_commit_uops_0_uses_ldq; // @[lsu.scala:211:7] wire io_core_commit_uops_0_uses_stq_0 = io_core_commit_uops_0_uses_stq; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_unique_0 = io_core_commit_uops_0_is_unique; // @[lsu.scala:211:7] wire io_core_commit_uops_0_flush_on_commit_0 = io_core_commit_uops_0_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_csr_cmd_0 = io_core_commit_uops_0_csr_cmd; // @[lsu.scala:211:7] wire io_core_commit_uops_0_ldst_is_rs1_0 = io_core_commit_uops_0_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_ldst_0 = io_core_commit_uops_0_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_lrs1_0 = io_core_commit_uops_0_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_lrs2_0 = io_core_commit_uops_0_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_lrs3_0 = io_core_commit_uops_0_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_dst_rtype_0 = io_core_commit_uops_0_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_lrs1_rtype_0 = io_core_commit_uops_0_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_lrs2_rtype_0 = io_core_commit_uops_0_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_commit_uops_0_frs3_en_0 = io_core_commit_uops_0_frs3_en; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fcn_dw_0 = io_core_commit_uops_0_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_fcn_op_0 = io_core_commit_uops_0_fcn_op; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_val_0 = io_core_commit_uops_0_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_fp_rm_0 = io_core_commit_uops_0_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_fp_typ_0 = io_core_commit_uops_0_fp_typ; // @[lsu.scala:211:7] wire io_core_commit_uops_0_xcpt_pf_if_0 = io_core_commit_uops_0_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_xcpt_ae_if_0 = io_core_commit_uops_0_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_xcpt_ma_if_0 = io_core_commit_uops_0_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_bp_debug_if_0 = io_core_commit_uops_0_bp_debug_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_bp_xcpt_if_0 = io_core_commit_uops_0_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_debug_fsrc_0 = io_core_commit_uops_0_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_debug_tsrc_0 = io_core_commit_uops_0_debug_tsrc; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_1_inst_0 = io_core_commit_uops_1_inst; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_1_debug_inst_0 = io_core_commit_uops_1_debug_inst; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_rvc_0 = io_core_commit_uops_1_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_commit_uops_1_debug_pc_0 = io_core_commit_uops_1_debug_pc; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_0_0 = io_core_commit_uops_1_iq_type_0; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_1_0 = io_core_commit_uops_1_iq_type_1; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_2_0 = io_core_commit_uops_1_iq_type_2; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_3_0 = io_core_commit_uops_1_iq_type_3; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_0_0 = io_core_commit_uops_1_fu_code_0; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_1_0 = io_core_commit_uops_1_fu_code_1; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_2_0 = io_core_commit_uops_1_fu_code_2; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_3_0 = io_core_commit_uops_1_fu_code_3; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_4_0 = io_core_commit_uops_1_fu_code_4; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_5_0 = io_core_commit_uops_1_fu_code_5; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_6_0 = io_core_commit_uops_1_fu_code_6; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_7_0 = io_core_commit_uops_1_fu_code_7; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_8_0 = io_core_commit_uops_1_fu_code_8; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_9_0 = io_core_commit_uops_1_fu_code_9; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_issued_0 = io_core_commit_uops_1_iw_issued; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_issued_partial_agen_0 = io_core_commit_uops_1_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_issued_partial_dgen_0 = io_core_commit_uops_1_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_iw_p1_speculative_child_0 = io_core_commit_uops_1_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_iw_p2_speculative_child_0 = io_core_commit_uops_1_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_p1_bypass_hint_0 = io_core_commit_uops_1_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_p2_bypass_hint_0 = io_core_commit_uops_1_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_p3_bypass_hint_0 = io_core_commit_uops_1_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_dis_col_sel_0 = io_core_commit_uops_1_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_commit_uops_1_br_mask_0 = io_core_commit_uops_1_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_1_br_tag_0 = io_core_commit_uops_1_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_1_br_type_0 = io_core_commit_uops_1_br_type; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_sfb_0 = io_core_commit_uops_1_is_sfb; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_fence_0 = io_core_commit_uops_1_is_fence; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_fencei_0 = io_core_commit_uops_1_is_fencei; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_sfence_0 = io_core_commit_uops_1_is_sfence; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_amo_0 = io_core_commit_uops_1_is_amo; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_eret_0 = io_core_commit_uops_1_is_eret; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_sys_pc2epc_0 = io_core_commit_uops_1_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_rocc_0 = io_core_commit_uops_1_is_rocc; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_mov_0 = io_core_commit_uops_1_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_ftq_idx_0 = io_core_commit_uops_1_ftq_idx; // @[lsu.scala:211:7] wire io_core_commit_uops_1_edge_inst_0 = io_core_commit_uops_1_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_pc_lob_0 = io_core_commit_uops_1_pc_lob; // @[lsu.scala:211:7] wire io_core_commit_uops_1_taken_0 = io_core_commit_uops_1_taken; // @[lsu.scala:211:7] wire io_core_commit_uops_1_imm_rename_0 = io_core_commit_uops_1_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_imm_sel_0 = io_core_commit_uops_1_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_pimm_0 = io_core_commit_uops_1_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_commit_uops_1_imm_packed_0 = io_core_commit_uops_1_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_op1_sel_0 = io_core_commit_uops_1_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_op2_sel_0 = io_core_commit_uops_1_op2_sel; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ldst_0 = io_core_commit_uops_1_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_wen_0 = io_core_commit_uops_1_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ren1_0 = io_core_commit_uops_1_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ren2_0 = io_core_commit_uops_1_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ren3_0 = io_core_commit_uops_1_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_swap12_0 = io_core_commit_uops_1_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_swap23_0 = io_core_commit_uops_1_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_fp_ctrl_typeTagIn_0 = io_core_commit_uops_1_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_fp_ctrl_typeTagOut_0 = io_core_commit_uops_1_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_fromint_0 = io_core_commit_uops_1_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_toint_0 = io_core_commit_uops_1_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_fastpipe_0 = io_core_commit_uops_1_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_fma_0 = io_core_commit_uops_1_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_div_0 = io_core_commit_uops_1_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_sqrt_0 = io_core_commit_uops_1_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_wflags_0 = io_core_commit_uops_1_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_vec_0 = io_core_commit_uops_1_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_rob_idx_0 = io_core_commit_uops_1_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_1_ldq_idx_0 = io_core_commit_uops_1_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_1_stq_idx_0 = io_core_commit_uops_1_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_rxq_idx_0 = io_core_commit_uops_1_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_pdst_0 = io_core_commit_uops_1_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_prs1_0 = io_core_commit_uops_1_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_prs2_0 = io_core_commit_uops_1_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_prs3_0 = io_core_commit_uops_1_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_ppred_0 = io_core_commit_uops_1_ppred; // @[lsu.scala:211:7] wire io_core_commit_uops_1_prs1_busy_0 = io_core_commit_uops_1_prs1_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_1_prs2_busy_0 = io_core_commit_uops_1_prs2_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_1_prs3_busy_0 = io_core_commit_uops_1_prs3_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_1_ppred_busy_0 = io_core_commit_uops_1_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_stale_pdst_0 = io_core_commit_uops_1_stale_pdst; // @[lsu.scala:211:7] wire io_core_commit_uops_1_exception_0 = io_core_commit_uops_1_exception; // @[lsu.scala:211:7] wire [63:0] io_core_commit_uops_1_exc_cause_0 = io_core_commit_uops_1_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_mem_cmd_0 = io_core_commit_uops_1_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_mem_size_0 = io_core_commit_uops_1_mem_size; // @[lsu.scala:211:7] wire io_core_commit_uops_1_mem_signed_0 = io_core_commit_uops_1_mem_signed; // @[lsu.scala:211:7] wire io_core_commit_uops_1_uses_ldq_0 = io_core_commit_uops_1_uses_ldq; // @[lsu.scala:211:7] wire io_core_commit_uops_1_uses_stq_0 = io_core_commit_uops_1_uses_stq; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_unique_0 = io_core_commit_uops_1_is_unique; // @[lsu.scala:211:7] wire io_core_commit_uops_1_flush_on_commit_0 = io_core_commit_uops_1_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_csr_cmd_0 = io_core_commit_uops_1_csr_cmd; // @[lsu.scala:211:7] wire io_core_commit_uops_1_ldst_is_rs1_0 = io_core_commit_uops_1_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_ldst_0 = io_core_commit_uops_1_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_lrs1_0 = io_core_commit_uops_1_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_lrs2_0 = io_core_commit_uops_1_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_lrs3_0 = io_core_commit_uops_1_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_dst_rtype_0 = io_core_commit_uops_1_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_lrs1_rtype_0 = io_core_commit_uops_1_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_lrs2_rtype_0 = io_core_commit_uops_1_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_commit_uops_1_frs3_en_0 = io_core_commit_uops_1_frs3_en; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fcn_dw_0 = io_core_commit_uops_1_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_fcn_op_0 = io_core_commit_uops_1_fcn_op; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_val_0 = io_core_commit_uops_1_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_fp_rm_0 = io_core_commit_uops_1_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_fp_typ_0 = io_core_commit_uops_1_fp_typ; // @[lsu.scala:211:7] wire io_core_commit_uops_1_xcpt_pf_if_0 = io_core_commit_uops_1_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_xcpt_ae_if_0 = io_core_commit_uops_1_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_xcpt_ma_if_0 = io_core_commit_uops_1_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_bp_debug_if_0 = io_core_commit_uops_1_bp_debug_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_bp_xcpt_if_0 = io_core_commit_uops_1_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_debug_fsrc_0 = io_core_commit_uops_1_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_debug_tsrc_0 = io_core_commit_uops_1_debug_tsrc; // @[lsu.scala:211:7] wire io_core_commit_fflags_valid_0 = io_core_commit_fflags_valid; // @[lsu.scala:211:7] wire [4:0] io_core_commit_fflags_bits_0 = io_core_commit_fflags_bits; // @[lsu.scala:211:7] wire [63:0] io_core_commit_debug_wdata_0_0 = io_core_commit_debug_wdata_0; // @[lsu.scala:211:7] wire [63:0] io_core_commit_debug_wdata_1_0 = io_core_commit_debug_wdata_1; // @[lsu.scala:211:7] wire io_core_commit_load_at_rob_head_0 = io_core_commit_load_at_rob_head; // @[lsu.scala:211:7] wire io_core_fence_dmem_0 = io_core_fence_dmem; // @[lsu.scala:211:7] wire [11:0] io_core_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask; // @[lsu.scala:211:7] wire [11:0] io_core_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask; // @[lsu.scala:211:7] wire [31:0] io_core_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_0_0 = io_core_brupdate_b2_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_1_0 = io_core_brupdate_b2_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_2_0 = io_core_brupdate_b2_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_3_0 = io_core_brupdate_b2_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_0_0 = io_core_brupdate_b2_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_1_0 = io_core_brupdate_b2_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_2_0 = io_core_brupdate_b2_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_3_0 = io_core_brupdate_b2_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_4_0 = io_core_brupdate_b2_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_5_0 = io_core_brupdate_b2_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_6_0 = io_core_brupdate_b2_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_7_0 = io_core_brupdate_b2_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_8_0 = io_core_brupdate_b2_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_9_0 = io_core_brupdate_b2_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_issued_0 = io_core_brupdate_b2_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_issued_partial_agen_0 = io_core_brupdate_b2_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_core_brupdate_b2_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_iw_p1_speculative_child_0 = io_core_brupdate_b2_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_iw_p2_speculative_child_0 = io_core_brupdate_b2_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_dis_col_sel_0 = io_core_brupdate_b2_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_core_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_brupdate_b2_uop_br_type_0 = io_core_brupdate_b2_uop_br_type; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_sfence_0 = io_core_brupdate_b2_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_eret_0 = io_core_brupdate_b2_uop_is_eret; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_rocc_0 = io_core_brupdate_b2_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_mov_0 = io_core_brupdate_b2_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_imm_rename_0 = io_core_brupdate_b2_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_imm_sel_0 = io_core_brupdate_b2_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_pimm_0 = io_core_brupdate_b2_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_op1_sel_0 = io_core_brupdate_b2_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_op2_sel_0 = io_core_brupdate_b2_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ldst_0 = io_core_brupdate_b2_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_wen_0 = io_core_brupdate_b2_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ren1_0 = io_core_brupdate_b2_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ren2_0 = io_core_brupdate_b2_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ren3_0 = io_core_brupdate_b2_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_swap12_0 = io_core_brupdate_b2_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_swap23_0 = io_core_brupdate_b2_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_fromint_0 = io_core_brupdate_b2_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_toint_0 = io_core_brupdate_b2_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_core_brupdate_b2_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_fma_0 = io_core_brupdate_b2_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_div_0 = io_core_brupdate_b2_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_core_brupdate_b2_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_wflags_0 = io_core_brupdate_b2_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_vec_0 = io_core_brupdate_b2_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_core_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_core_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_csr_cmd_0 = io_core_brupdate_b2_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fcn_dw_0 = io_core_brupdate_b2_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_fcn_op_0 = io_core_brupdate_b2_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_fp_rm_0 = io_core_brupdate_b2_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_fp_typ_0 = io_core_brupdate_b2_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict; // @[lsu.scala:211:7] wire io_core_brupdate_b2_taken_0 = io_core_brupdate_b2_taken; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel; // @[lsu.scala:211:7] wire [39:0] io_core_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target; // @[lsu.scala:211:7] wire [20:0] io_core_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset; // @[lsu.scala:211:7] wire [5:0] io_core_rob_pnr_idx_0 = io_core_rob_pnr_idx; // @[lsu.scala:211:7] wire [5:0] io_core_rob_head_idx_0 = io_core_rob_head_idx; // @[lsu.scala:211:7] wire io_core_exception_0 = io_core_exception; // @[lsu.scala:211:7] wire [63:0] io_core_tsc_reg_0 = io_core_tsc_reg; // @[lsu.scala:211:7] wire io_core_status_debug_0 = io_core_status_debug; // @[lsu.scala:211:7] wire io_core_status_cease_0 = io_core_status_cease; // @[lsu.scala:211:7] wire io_core_status_wfi_0 = io_core_status_wfi; // @[lsu.scala:211:7] wire [1:0] io_core_status_dprv_0 = io_core_status_dprv; // @[lsu.scala:211:7] wire io_core_status_dv_0 = io_core_status_dv; // @[lsu.scala:211:7] wire [1:0] io_core_status_prv_0 = io_core_status_prv; // @[lsu.scala:211:7] wire io_core_status_v_0 = io_core_status_v; // @[lsu.scala:211:7] wire io_core_status_sd_0 = io_core_status_sd; // @[lsu.scala:211:7] wire io_core_status_mpv_0 = io_core_status_mpv; // @[lsu.scala:211:7] wire io_core_status_gva_0 = io_core_status_gva; // @[lsu.scala:211:7] wire io_core_status_tsr_0 = io_core_status_tsr; // @[lsu.scala:211:7] wire io_core_status_tw_0 = io_core_status_tw; // @[lsu.scala:211:7] wire io_core_status_tvm_0 = io_core_status_tvm; // @[lsu.scala:211:7] wire io_core_status_mxr_0 = io_core_status_mxr; // @[lsu.scala:211:7] wire io_core_status_sum_0 = io_core_status_sum; // @[lsu.scala:211:7] wire io_core_status_mprv_0 = io_core_status_mprv; // @[lsu.scala:211:7] wire [1:0] io_core_status_fs_0 = io_core_status_fs; // @[lsu.scala:211:7] wire [1:0] io_core_status_mpp_0 = io_core_status_mpp; // @[lsu.scala:211:7] wire io_core_status_spp_0 = io_core_status_spp; // @[lsu.scala:211:7] wire io_core_status_mpie_0 = io_core_status_mpie; // @[lsu.scala:211:7] wire io_core_status_spie_0 = io_core_status_spie; // @[lsu.scala:211:7] wire io_core_status_mie_0 = io_core_status_mie; // @[lsu.scala:211:7] wire io_core_status_sie_0 = io_core_status_sie; // @[lsu.scala:211:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[lsu.scala:211:7] wire io_dmem_resp_0_valid_0 = io_dmem_resp_0_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_resp_0_bits_uop_inst_0 = io_dmem_resp_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_resp_0_bits_uop_debug_inst_0 = io_dmem_resp_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_rvc_0 = io_dmem_resp_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_resp_0_bits_uop_debug_pc_0 = io_dmem_resp_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_0_0 = io_dmem_resp_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_1_0 = io_dmem_resp_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_2_0 = io_dmem_resp_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_3_0 = io_dmem_resp_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_0_0 = io_dmem_resp_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_1_0 = io_dmem_resp_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_2_0 = io_dmem_resp_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_3_0 = io_dmem_resp_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_4_0 = io_dmem_resp_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_5_0 = io_dmem_resp_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_6_0 = io_dmem_resp_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_7_0 = io_dmem_resp_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_8_0 = io_dmem_resp_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_9_0 = io_dmem_resp_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_issued_0 = io_dmem_resp_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_issued_partial_agen_0 = io_dmem_resp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_issued_partial_dgen_0 = io_dmem_resp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_iw_p1_speculative_child_0 = io_dmem_resp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_iw_p2_speculative_child_0 = io_dmem_resp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_p1_bypass_hint_0 = io_dmem_resp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_p2_bypass_hint_0 = io_dmem_resp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_p3_bypass_hint_0 = io_dmem_resp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_dis_col_sel_0 = io_dmem_resp_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_dmem_resp_0_bits_uop_br_mask_0 = io_dmem_resp_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_resp_0_bits_uop_br_tag_0 = io_dmem_resp_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_resp_0_bits_uop_br_type_0 = io_dmem_resp_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_sfb_0 = io_dmem_resp_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_fence_0 = io_dmem_resp_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_fencei_0 = io_dmem_resp_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_sfence_0 = io_dmem_resp_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_amo_0 = io_dmem_resp_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_eret_0 = io_dmem_resp_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_sys_pc2epc_0 = io_dmem_resp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_rocc_0 = io_dmem_resp_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_mov_0 = io_dmem_resp_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_ftq_idx_0 = io_dmem_resp_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_edge_inst_0 = io_dmem_resp_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_pc_lob_0 = io_dmem_resp_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_taken_0 = io_dmem_resp_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_imm_rename_0 = io_dmem_resp_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_imm_sel_0 = io_dmem_resp_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_pimm_0 = io_dmem_resp_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_resp_0_bits_uop_imm_packed_0 = io_dmem_resp_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_op1_sel_0 = io_dmem_resp_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_op2_sel_0 = io_dmem_resp_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ldst_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_wen_0 = io_dmem_resp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ren1_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ren2_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ren3_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_swap12_0 = io_dmem_resp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_swap23_0 = io_dmem_resp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_fromint_0 = io_dmem_resp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_toint_0 = io_dmem_resp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_fma_0 = io_dmem_resp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_div_0 = io_dmem_resp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_sqrt_0 = io_dmem_resp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_wflags_0 = io_dmem_resp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_vec_0 = io_dmem_resp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_rob_idx_0 = io_dmem_resp_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_resp_0_bits_uop_ldq_idx_0 = io_dmem_resp_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_resp_0_bits_uop_stq_idx_0 = io_dmem_resp_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_rxq_idx_0 = io_dmem_resp_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_pdst_0 = io_dmem_resp_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_prs1_0 = io_dmem_resp_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_prs2_0 = io_dmem_resp_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_prs3_0 = io_dmem_resp_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_ppred_0 = io_dmem_resp_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_prs1_busy_0 = io_dmem_resp_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_prs2_busy_0 = io_dmem_resp_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_prs3_busy_0 = io_dmem_resp_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_ppred_busy_0 = io_dmem_resp_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_stale_pdst_0 = io_dmem_resp_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_exception_0 = io_dmem_resp_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_resp_0_bits_uop_exc_cause_0 = io_dmem_resp_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_mem_cmd_0 = io_dmem_resp_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_mem_size_0 = io_dmem_resp_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_mem_signed_0 = io_dmem_resp_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_uses_ldq_0 = io_dmem_resp_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_uses_stq_0 = io_dmem_resp_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_unique_0 = io_dmem_resp_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_flush_on_commit_0 = io_dmem_resp_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_csr_cmd_0 = io_dmem_resp_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_ldst_is_rs1_0 = io_dmem_resp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_ldst_0 = io_dmem_resp_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs1_0 = io_dmem_resp_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs2_0 = io_dmem_resp_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs3_0 = io_dmem_resp_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_dst_rtype_0 = io_dmem_resp_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype_0 = io_dmem_resp_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype_0 = io_dmem_resp_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_frs3_en_0 = io_dmem_resp_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fcn_dw_0 = io_dmem_resp_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_fcn_op_0 = io_dmem_resp_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_val_0 = io_dmem_resp_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_fp_rm_0 = io_dmem_resp_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_fp_typ_0 = io_dmem_resp_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_xcpt_pf_if_0 = io_dmem_resp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_xcpt_ae_if_0 = io_dmem_resp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_xcpt_ma_if_0 = io_dmem_resp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_bp_debug_if_0 = io_dmem_resp_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_bp_xcpt_if_0 = io_dmem_resp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_debug_fsrc_0 = io_dmem_resp_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_debug_tsrc_0 = io_dmem_resp_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_dmem_resp_0_bits_data_0 = io_dmem_resp_0_bits_data; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_is_hella_0 = io_dmem_resp_0_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_valid_0 = io_dmem_store_ack_0_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_store_ack_0_bits_uop_inst_0 = io_dmem_store_ack_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_store_ack_0_bits_uop_debug_inst_0 = io_dmem_store_ack_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_rvc_0 = io_dmem_store_ack_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_store_ack_0_bits_uop_debug_pc_0 = io_dmem_store_ack_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_0_0 = io_dmem_store_ack_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_1_0 = io_dmem_store_ack_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_2_0 = io_dmem_store_ack_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_3_0 = io_dmem_store_ack_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_0_0 = io_dmem_store_ack_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_1_0 = io_dmem_store_ack_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_2_0 = io_dmem_store_ack_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_3_0 = io_dmem_store_ack_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_4_0 = io_dmem_store_ack_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_5_0 = io_dmem_store_ack_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_6_0 = io_dmem_store_ack_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_7_0 = io_dmem_store_ack_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_8_0 = io_dmem_store_ack_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_9_0 = io_dmem_store_ack_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_issued_0 = io_dmem_store_ack_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen_0 = io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen_0 = io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child_0 = io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child_0 = io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint_0 = io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint_0 = io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint_0 = io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_dis_col_sel_0 = io_dmem_store_ack_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_dmem_store_ack_0_bits_uop_br_mask_0 = io_dmem_store_ack_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_store_ack_0_bits_uop_br_tag_0 = io_dmem_store_ack_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_store_ack_0_bits_uop_br_type_0 = io_dmem_store_ack_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_sfb_0 = io_dmem_store_ack_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_fence_0 = io_dmem_store_ack_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_fencei_0 = io_dmem_store_ack_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_sfence_0 = io_dmem_store_ack_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_amo_0 = io_dmem_store_ack_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_eret_0 = io_dmem_store_ack_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_sys_pc2epc_0 = io_dmem_store_ack_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_rocc_0 = io_dmem_store_ack_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_mov_0 = io_dmem_store_ack_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_ftq_idx_0 = io_dmem_store_ack_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_edge_inst_0 = io_dmem_store_ack_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_pc_lob_0 = io_dmem_store_ack_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_taken_0 = io_dmem_store_ack_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_imm_rename_0 = io_dmem_store_ack_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_imm_sel_0 = io_dmem_store_ack_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_pimm_0 = io_dmem_store_ack_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_store_ack_0_bits_uop_imm_packed_0 = io_dmem_store_ack_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_op1_sel_0 = io_dmem_store_ack_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_op2_sel_0 = io_dmem_store_ack_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_wen_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_toint_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_fma_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_div_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_vec_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_rob_idx_0 = io_dmem_store_ack_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_store_ack_0_bits_uop_ldq_idx_0 = io_dmem_store_ack_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_store_ack_0_bits_uop_stq_idx_0 = io_dmem_store_ack_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_rxq_idx_0 = io_dmem_store_ack_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_pdst_0 = io_dmem_store_ack_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_prs1_0 = io_dmem_store_ack_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_prs2_0 = io_dmem_store_ack_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_prs3_0 = io_dmem_store_ack_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_ppred_0 = io_dmem_store_ack_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_prs1_busy_0 = io_dmem_store_ack_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_prs2_busy_0 = io_dmem_store_ack_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_prs3_busy_0 = io_dmem_store_ack_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_ppred_busy_0 = io_dmem_store_ack_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_stale_pdst_0 = io_dmem_store_ack_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_exception_0 = io_dmem_store_ack_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_store_ack_0_bits_uop_exc_cause_0 = io_dmem_store_ack_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_mem_cmd_0 = io_dmem_store_ack_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_mem_size_0 = io_dmem_store_ack_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_mem_signed_0 = io_dmem_store_ack_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_uses_ldq_0 = io_dmem_store_ack_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_uses_stq_0 = io_dmem_store_ack_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_unique_0 = io_dmem_store_ack_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_flush_on_commit_0 = io_dmem_store_ack_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_csr_cmd_0 = io_dmem_store_ack_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_ldst_is_rs1_0 = io_dmem_store_ack_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_ldst_0 = io_dmem_store_ack_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_lrs1_0 = io_dmem_store_ack_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_lrs2_0 = io_dmem_store_ack_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_lrs3_0 = io_dmem_store_ack_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_dst_rtype_0 = io_dmem_store_ack_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_lrs1_rtype_0 = io_dmem_store_ack_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_lrs2_rtype_0 = io_dmem_store_ack_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_frs3_en_0 = io_dmem_store_ack_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fcn_dw_0 = io_dmem_store_ack_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_fcn_op_0 = io_dmem_store_ack_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_val_0 = io_dmem_store_ack_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_fp_rm_0 = io_dmem_store_ack_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_fp_typ_0 = io_dmem_store_ack_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_xcpt_pf_if_0 = io_dmem_store_ack_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_xcpt_ae_if_0 = io_dmem_store_ack_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_xcpt_ma_if_0 = io_dmem_store_ack_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_bp_debug_if_0 = io_dmem_store_ack_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_bp_xcpt_if_0 = io_dmem_store_ack_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_debug_fsrc_0 = io_dmem_store_ack_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_debug_tsrc_0 = io_dmem_store_ack_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [39:0] io_dmem_store_ack_0_bits_addr_0 = io_dmem_store_ack_0_bits_addr; // @[lsu.scala:211:7] wire [63:0] io_dmem_store_ack_0_bits_data_0 = io_dmem_store_ack_0_bits_data; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_is_hella_0 = io_dmem_store_ack_0_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_nack_0_valid_0 = io_dmem_nack_0_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_nack_0_bits_uop_inst_0 = io_dmem_nack_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_nack_0_bits_uop_debug_inst_0 = io_dmem_nack_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_rvc_0 = io_dmem_nack_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_nack_0_bits_uop_debug_pc_0 = io_dmem_nack_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_0_0 = io_dmem_nack_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_1_0 = io_dmem_nack_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_2_0 = io_dmem_nack_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_3_0 = io_dmem_nack_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_0_0 = io_dmem_nack_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_1_0 = io_dmem_nack_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_2_0 = io_dmem_nack_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_3_0 = io_dmem_nack_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_4_0 = io_dmem_nack_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_5_0 = io_dmem_nack_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_6_0 = io_dmem_nack_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_7_0 = io_dmem_nack_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_8_0 = io_dmem_nack_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_9_0 = io_dmem_nack_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_issued_0 = io_dmem_nack_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_issued_partial_agen_0 = io_dmem_nack_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_issued_partial_dgen_0 = io_dmem_nack_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_iw_p1_speculative_child_0 = io_dmem_nack_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_iw_p2_speculative_child_0 = io_dmem_nack_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_p1_bypass_hint_0 = io_dmem_nack_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_p2_bypass_hint_0 = io_dmem_nack_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_p3_bypass_hint_0 = io_dmem_nack_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_dis_col_sel_0 = io_dmem_nack_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_dmem_nack_0_bits_uop_br_mask_0 = io_dmem_nack_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_nack_0_bits_uop_br_tag_0 = io_dmem_nack_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_nack_0_bits_uop_br_type_0 = io_dmem_nack_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_sfb_0 = io_dmem_nack_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_fence_0 = io_dmem_nack_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_fencei_0 = io_dmem_nack_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_sfence_0 = io_dmem_nack_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_amo_0 = io_dmem_nack_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_eret_0 = io_dmem_nack_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_sys_pc2epc_0 = io_dmem_nack_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_rocc_0 = io_dmem_nack_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_mov_0 = io_dmem_nack_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_ftq_idx_0 = io_dmem_nack_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_edge_inst_0 = io_dmem_nack_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_pc_lob_0 = io_dmem_nack_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_taken_0 = io_dmem_nack_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_imm_rename_0 = io_dmem_nack_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_imm_sel_0 = io_dmem_nack_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_pimm_0 = io_dmem_nack_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_nack_0_bits_uop_imm_packed_0 = io_dmem_nack_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_op1_sel_0 = io_dmem_nack_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_op2_sel_0 = io_dmem_nack_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ldst_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_wen_0 = io_dmem_nack_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ren1_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ren2_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ren3_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_swap12_0 = io_dmem_nack_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_swap23_0 = io_dmem_nack_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_fromint_0 = io_dmem_nack_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_toint_0 = io_dmem_nack_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_fma_0 = io_dmem_nack_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_div_0 = io_dmem_nack_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_sqrt_0 = io_dmem_nack_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_wflags_0 = io_dmem_nack_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_vec_0 = io_dmem_nack_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_rob_idx_0 = io_dmem_nack_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_nack_0_bits_uop_ldq_idx_0 = io_dmem_nack_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_nack_0_bits_uop_stq_idx_0 = io_dmem_nack_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_rxq_idx_0 = io_dmem_nack_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_pdst_0 = io_dmem_nack_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_prs1_0 = io_dmem_nack_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_prs2_0 = io_dmem_nack_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_prs3_0 = io_dmem_nack_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_ppred_0 = io_dmem_nack_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_prs1_busy_0 = io_dmem_nack_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_prs2_busy_0 = io_dmem_nack_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_prs3_busy_0 = io_dmem_nack_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_ppred_busy_0 = io_dmem_nack_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_stale_pdst_0 = io_dmem_nack_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_exception_0 = io_dmem_nack_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_nack_0_bits_uop_exc_cause_0 = io_dmem_nack_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_mem_cmd_0 = io_dmem_nack_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_mem_size_0 = io_dmem_nack_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_mem_signed_0 = io_dmem_nack_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_uses_ldq_0 = io_dmem_nack_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_uses_stq_0 = io_dmem_nack_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_unique_0 = io_dmem_nack_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_flush_on_commit_0 = io_dmem_nack_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_csr_cmd_0 = io_dmem_nack_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_ldst_is_rs1_0 = io_dmem_nack_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_ldst_0 = io_dmem_nack_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs1_0 = io_dmem_nack_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs2_0 = io_dmem_nack_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs3_0 = io_dmem_nack_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_dst_rtype_0 = io_dmem_nack_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype_0 = io_dmem_nack_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype_0 = io_dmem_nack_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_frs3_en_0 = io_dmem_nack_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fcn_dw_0 = io_dmem_nack_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_fcn_op_0 = io_dmem_nack_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_val_0 = io_dmem_nack_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_fp_rm_0 = io_dmem_nack_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_fp_typ_0 = io_dmem_nack_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_xcpt_pf_if_0 = io_dmem_nack_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_xcpt_ae_if_0 = io_dmem_nack_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_xcpt_ma_if_0 = io_dmem_nack_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_bp_debug_if_0 = io_dmem_nack_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_bp_xcpt_if_0 = io_dmem_nack_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_debug_fsrc_0 = io_dmem_nack_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_debug_tsrc_0 = io_dmem_nack_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [39:0] io_dmem_nack_0_bits_addr_0 = io_dmem_nack_0_bits_addr; // @[lsu.scala:211:7] wire [63:0] io_dmem_nack_0_bits_data_0 = io_dmem_nack_0_bits_data; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_is_hella_0 = io_dmem_nack_0_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_ll_resp_valid_0 = io_dmem_ll_resp_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_ll_resp_bits_uop_inst_0 = io_dmem_ll_resp_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_ll_resp_bits_uop_debug_inst_0 = io_dmem_ll_resp_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_rvc_0 = io_dmem_ll_resp_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_ll_resp_bits_uop_debug_pc_0 = io_dmem_ll_resp_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_0_0 = io_dmem_ll_resp_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_1_0 = io_dmem_ll_resp_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_2_0 = io_dmem_ll_resp_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_3_0 = io_dmem_ll_resp_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_0_0 = io_dmem_ll_resp_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_1_0 = io_dmem_ll_resp_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_2_0 = io_dmem_ll_resp_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_3_0 = io_dmem_ll_resp_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_4_0 = io_dmem_ll_resp_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_5_0 = io_dmem_ll_resp_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_6_0 = io_dmem_ll_resp_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_7_0 = io_dmem_ll_resp_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_8_0 = io_dmem_ll_resp_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_9_0 = io_dmem_ll_resp_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_issued_0 = io_dmem_ll_resp_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_issued_partial_agen_0 = io_dmem_ll_resp_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen_0 = io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_iw_p1_speculative_child_0 = io_dmem_ll_resp_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_iw_p2_speculative_child_0 = io_dmem_ll_resp_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint_0 = io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint_0 = io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint_0 = io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_dis_col_sel_0 = io_dmem_ll_resp_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [11:0] io_dmem_ll_resp_bits_uop_br_mask_0 = io_dmem_ll_resp_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_ll_resp_bits_uop_br_tag_0 = io_dmem_ll_resp_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_ll_resp_bits_uop_br_type_0 = io_dmem_ll_resp_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_sfb_0 = io_dmem_ll_resp_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_fence_0 = io_dmem_ll_resp_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_fencei_0 = io_dmem_ll_resp_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_sfence_0 = io_dmem_ll_resp_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_amo_0 = io_dmem_ll_resp_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_eret_0 = io_dmem_ll_resp_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_sys_pc2epc_0 = io_dmem_ll_resp_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_rocc_0 = io_dmem_ll_resp_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_mov_0 = io_dmem_ll_resp_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_ftq_idx_0 = io_dmem_ll_resp_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_edge_inst_0 = io_dmem_ll_resp_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_pc_lob_0 = io_dmem_ll_resp_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_taken_0 = io_dmem_ll_resp_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_imm_rename_0 = io_dmem_ll_resp_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_imm_sel_0 = io_dmem_ll_resp_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_pimm_0 = io_dmem_ll_resp_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_ll_resp_bits_uop_imm_packed_0 = io_dmem_ll_resp_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_op1_sel_0 = io_dmem_ll_resp_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_op2_sel_0 = io_dmem_ll_resp_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ldst_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_wen_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ren1_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ren2_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ren3_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_swap12_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_swap23_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_fromint_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_toint_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_fma_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_div_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_wflags_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_vec_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_rob_idx_0 = io_dmem_ll_resp_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_ll_resp_bits_uop_ldq_idx_0 = io_dmem_ll_resp_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [3:0] io_dmem_ll_resp_bits_uop_stq_idx_0 = io_dmem_ll_resp_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_rxq_idx_0 = io_dmem_ll_resp_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_pdst_0 = io_dmem_ll_resp_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_prs1_0 = io_dmem_ll_resp_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_prs2_0 = io_dmem_ll_resp_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_prs3_0 = io_dmem_ll_resp_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_ppred_0 = io_dmem_ll_resp_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_prs1_busy_0 = io_dmem_ll_resp_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_prs2_busy_0 = io_dmem_ll_resp_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_prs3_busy_0 = io_dmem_ll_resp_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_ppred_busy_0 = io_dmem_ll_resp_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_stale_pdst_0 = io_dmem_ll_resp_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_exception_0 = io_dmem_ll_resp_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_ll_resp_bits_uop_exc_cause_0 = io_dmem_ll_resp_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_mem_cmd_0 = io_dmem_ll_resp_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_mem_size_0 = io_dmem_ll_resp_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_mem_signed_0 = io_dmem_ll_resp_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_uses_ldq_0 = io_dmem_ll_resp_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_uses_stq_0 = io_dmem_ll_resp_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_unique_0 = io_dmem_ll_resp_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_flush_on_commit_0 = io_dmem_ll_resp_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_csr_cmd_0 = io_dmem_ll_resp_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_ldst_is_rs1_0 = io_dmem_ll_resp_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_ldst_0 = io_dmem_ll_resp_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_lrs1_0 = io_dmem_ll_resp_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_lrs2_0 = io_dmem_ll_resp_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_lrs3_0 = io_dmem_ll_resp_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_dst_rtype_0 = io_dmem_ll_resp_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_lrs1_rtype_0 = io_dmem_ll_resp_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_lrs2_rtype_0 = io_dmem_ll_resp_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_frs3_en_0 = io_dmem_ll_resp_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fcn_dw_0 = io_dmem_ll_resp_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_fcn_op_0 = io_dmem_ll_resp_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_val_0 = io_dmem_ll_resp_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_fp_rm_0 = io_dmem_ll_resp_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_fp_typ_0 = io_dmem_ll_resp_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_xcpt_pf_if_0 = io_dmem_ll_resp_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_xcpt_ae_if_0 = io_dmem_ll_resp_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_xcpt_ma_if_0 = io_dmem_ll_resp_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_bp_debug_if_0 = io_dmem_ll_resp_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_bp_xcpt_if_0 = io_dmem_ll_resp_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_debug_fsrc_0 = io_dmem_ll_resp_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_debug_tsrc_0 = io_dmem_ll_resp_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_dmem_ll_resp_bits_data_0 = io_dmem_ll_resp_bits_data; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_is_hella_0 = io_dmem_ll_resp_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_release_valid_0 = io_dmem_release_valid; // @[lsu.scala:211:7] wire [2:0] io_dmem_release_bits_opcode_0 = io_dmem_release_bits_opcode; // @[lsu.scala:211:7] wire [2:0] io_dmem_release_bits_param_0 = io_dmem_release_bits_param; // @[lsu.scala:211:7] wire [3:0] io_dmem_release_bits_size_0 = io_dmem_release_bits_size; // @[lsu.scala:211:7] wire [1:0] io_dmem_release_bits_source_0 = io_dmem_release_bits_source; // @[lsu.scala:211:7] wire [31:0] io_dmem_release_bits_address_0 = io_dmem_release_bits_address; // @[lsu.scala:211:7] wire [63:0] io_dmem_release_bits_data_0 = io_dmem_release_bits_data; // @[lsu.scala:211:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[lsu.scala:211:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[lsu.scala:211:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[lsu.scala:211:7] wire io_hellacache_req_valid_0 = io_hellacache_req_valid; // @[lsu.scala:211:7] wire [39:0] io_hellacache_req_bits_addr_0 = io_hellacache_req_bits_addr; // @[lsu.scala:211:7] wire io_hellacache_req_bits_dv_0 = io_hellacache_req_bits_dv; // @[lsu.scala:211:7] wire io_hellacache_s1_kill_0 = io_hellacache_s1_kill; // @[lsu.scala:211:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[lsu.scala:211:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[lsu.scala:211:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[lsu.scala:211:7] wire [15:0] _dmem_req_0_bits_data_T_17 = 16'h0; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_21 = 16'h0; // @[AMOALU.scala:29:69] wire [15:0] _mem_ldq_e_WIRE_bits_st_dep_mask = 16'h0; // @[lsu.scala:1064:73] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[lsu.scala:211:7] wire [31:0] io_core_status_isa = 32'h14112D; // @[lsu.scala:211:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[lsu.scala:211:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[lsu.scala:211:7] wire [22:0] io_core_status_zero2 = 23'h0; // @[lsu.scala:211:7] wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[lsu.scala:211:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_mbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_sbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_ube = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_upie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_hie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_uie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vtw = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_hu = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_spvp = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_spv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_gva = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_debug = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_cease = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_wfi = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_dv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_v = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sd = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mpv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_gva = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_tsr = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_tw = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_tvm = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mxr = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sum = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mprv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_spp = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mpie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_ube = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_spie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_upie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_hie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_uie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_predicated = 1'h0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_predicated = 1'h0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:211:7] wire io_core_status_mbe = 1'h0; // @[lsu.scala:211:7] wire io_core_status_sbe = 1'h0; // @[lsu.scala:211:7] wire io_core_status_sd_rv32 = 1'h0; // @[lsu.scala:211:7] wire io_core_status_ube = 1'h0; // @[lsu.scala:211:7] wire io_core_status_upie = 1'h0; // @[lsu.scala:211:7] wire io_core_status_hie = 1'h0; // @[lsu.scala:211:7] wire io_core_status_uie = 1'h0; // @[lsu.scala:211:7] wire io_dmem_s1_nack_advisory_0 = 1'h0; // @[lsu.scala:211:7] wire io_dmem_release_bits_corrupt = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_signed = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_no_resp = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_no_alloc = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_no_xcpt = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_nack_cause_raw = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_kill = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_uncached = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_signed = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_replay = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_replay_next = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_gpa_is_pte = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_ordered = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_acquire = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_release = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_grant = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_tlbMiss = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_blocked = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_canAcceptStoreThenLoad = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_canAcceptStoreThenRMW = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_canAcceptLoadThenLoad = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_storeBufferEmptyAfterLoad = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_storeBufferEmptyAfterStore = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_keep_clock_enabled = 1'h0; // @[lsu.scala:211:7] wire _block_load_mask_WIRE_0 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_1 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_2 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_3 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_4 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_5 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_6 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_7 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_8 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_9 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_10 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_11 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_12 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_13 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_14 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_15 = 1'h0; // @[lsu.scala:488:44] wire _can_fire_hella_incoming_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire _can_fire_hella_wakeup_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire _will_fire_sfence_0_will_fire_T = 1'h0; // @[lsu.scala:656:51] wire _will_fire_sfence_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_sfence_0_will_fire_T_4 = 1'h0; // @[lsu.scala:657:52] wire _will_fire_sfence_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_sfence_0_will_fire_T_8 = 1'h0; // @[lsu.scala:658:50] wire _will_fire_sfence_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_sfence_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_sfence_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_store_commit_fast_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_store_commit_fast_0_will_fire_T_4 = 1'h0; // @[lsu.scala:657:52] wire _will_fire_store_commit_fast_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_store_commit_fast_0_will_fire_T_8 = 1'h0; // @[lsu.scala:658:50] wire _will_fire_store_commit_fast_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_store_commit_fast_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_store_commit_fast_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_load_agen_exec_0_will_fire_T_4 = 1'h0; // @[lsu.scala:657:52] wire _will_fire_load_agen_exec_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_load_agen_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_load_agen_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_store_agen_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_store_agen_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_release_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_release_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_release_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_release_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_hella_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_hella_incoming_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_hella_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_hella_wakeup_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_hella_wakeup_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_hella_wakeup_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_store_retry_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_store_retry_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_load_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_load_wakeup_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_store_commit_slow_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_store_commit_slow_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_store_commit_slow_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_store_commit_slow_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _exe_tlb_uop_WIRE_is_rvc = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_0 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_2 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_3 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_0 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_2 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_3 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_4 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_5 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_6 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_7 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_8 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_9 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_issued = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_sfb = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_fence = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_fencei = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_sfence = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_amo = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_eret = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_sys_pc2epc = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_rocc = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_mov = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_edge_inst = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_taken = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_imm_rename = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_wen = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_toint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_fma = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_div = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_vec = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_prs1_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_prs2_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_prs3_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_ppred_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_exception = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_mem_signed = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_uses_ldq = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_uses_stq = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_unique = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_flush_on_commit = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_ldst_is_rs1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_frs3_en = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fcn_dw = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_val = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_xcpt_pf_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_xcpt_ae_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_xcpt_ma_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_bp_debug_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_bp_xcpt_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_1_is_rvc = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_0 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_2 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_3 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_0 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_2 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_3 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_4 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_5 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_6 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_7 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_8 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_9 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_issued = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_issued_partial_agen = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_sfb = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_fence = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_fencei = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_sfence = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_amo = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_eret = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_sys_pc2epc = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_rocc = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_mov = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_edge_inst = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_taken = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_imm_rename = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ldst = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_wen = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_fromint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_toint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_fma = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_div = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_wflags = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_vec = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_prs1_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_prs2_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_prs3_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_ppred_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_exception = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_mem_signed = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_uses_ldq = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_uses_stq = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_unique = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_flush_on_commit = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_ldst_is_rs1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_frs3_en = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fcn_dw = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_val = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_xcpt_pf_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_xcpt_ae_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_xcpt_ma_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_bp_debug_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_bp_xcpt_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_T_2_is_rvc = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_0 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_2 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_3 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_0 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_2 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_3 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_4 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_5 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_6 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_7 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_8 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_9 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_issued = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_issued_partial_agen = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_sfb = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_fence = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_fencei = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_sfence = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_amo = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_eret = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_sys_pc2epc = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_rocc = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_mov = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_edge_inst = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_taken = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_imm_rename = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ldst = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_wen = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_fromint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_toint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_fma = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_div = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_wflags = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_vec = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_prs1_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_prs2_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_prs3_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_ppred_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_exception = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_mem_signed = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_uses_ldq = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_uses_stq = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_unique = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_flush_on_commit = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_ldst_is_rs1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_frs3_en = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fcn_dw = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_val = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_xcpt_pf_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_xcpt_ae_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_xcpt_ma_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_bp_debug_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_bp_xcpt_if = 1'h0; // @[lsu.scala:722:24] wire _dbg_bp_T = 1'h0; // @[lsu.scala:788:80] wire _dbg_bp_T_1 = 1'h0; // @[lsu.scala:789:80] wire _dbg_bp_T_3 = 1'h0; // @[lsu.scala:789:104] wire _dbg_bp_T_4 = 1'h0; // @[lsu.scala:788:105] wire _dbg_bp_T_5 = 1'h0; // @[lsu.scala:788:51] wire dbg_bp_0 = 1'h0; // @[lsu.scala:321:49] wire _bp_T = 1'h0; // @[lsu.scala:790:80] wire _bp_T_1 = 1'h0; // @[lsu.scala:791:80] wire _bp_T_3 = 1'h0; // @[lsu.scala:791:103] wire _bp_T_4 = 1'h0; // @[lsu.scala:790:104] wire _bp_T_5 = 1'h0; // @[lsu.scala:790:51] wire bp_0 = 1'h0; // @[lsu.scala:321:49] wire _exe_tlb_miss_T = 1'h0; // @[lsu.scala:835:86] wire _s0_executing_loads_WIRE_0 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_1 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_2 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_3 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_4 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_5 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_6 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_7 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_8 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_9 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_10 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_11 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_12 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_13 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_14 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_15 = 1'h0; // @[lsu.scala:882:44] wire _dmem_req_0_bits_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_data_T_15 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_20 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_24 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_30 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_35 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_39 = 1'h0; // @[AMOALU.scala:29:19] wire _mem_ldq_e_WIRE_valid = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_0 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_2 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_3 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_0 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_2 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_3 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_4 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_5 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_6 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_7 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_8 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_9 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_issued = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_issued_partial_agen = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_sfence = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_eret = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_rocc = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_mov = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_imm_rename = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ldst = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_wen = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_fromint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_toint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_fma = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_div = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_wflags = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_vec = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fcn_dw = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_addr_is_uncacheable = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_executed = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_order_fail = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_observed = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_forward_std_val = 1'h0; // @[lsu.scala:1064:73] wire _mem_stq_e_WIRE_valid = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_0 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_2 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_3 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_0 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_2 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_3 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_4 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_5 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_6 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_7 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_8 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_9 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_issued = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_issued_partial_agen = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_sfence = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_eret = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_rocc = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_mov = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_imm_rename = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ldst = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_wen = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_fromint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_toint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_fma = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_div = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_wflags = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_vec = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fcn_dw = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_data_valid = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_committed = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_can_execute = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_cleared = 1'h0; // @[lsu.scala:1067:87] wire _lcam_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57] wire _kill_forward_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire _ld_xcpt_uop_T = 1'h0; // @[lsu.scala:1438:50] wire iresp_0_bits_predicated = 1'h0; // @[lsu.scala:1477:19] wire iresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:1477:19] wire fresp_0_bits_predicated = 1'h0; // @[lsu.scala:1478:19] wire fresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:1478:19] wire io_core_iresp_0_out_bits_predicated = 1'h0; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_fflags_valid = 1'h0; // @[util.scala:114:23] wire wb_spec_wakeups_0_bits_rebusy = 1'h0; // @[lsu.scala:1491:29] wire wb_slow_wakeups_0_bits_bypassable = 1'h0; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_rebusy = 1'h0; // @[lsu.scala:1494:29] wire slow_wakeups_0_bits_bypassable = 1'h0; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_rebusy = 1'h0; // @[lsu.scala:1495:26] wire _dmem_resp_fired_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire w1_bits_out_rebusy = 1'h0; // @[util.scala:109:23] wire w2_bits_out_rebusy = 1'h0; // @[util.scala:109:23] wire iresp_0_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire iresp_0_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire iresp_0_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire fresp_0_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire fresp_0_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire fresp_0_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_debug_wb_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire ldq_debug_wb_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_debug_wb_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire slow_wakeups_0_out_bits_bypassable = 1'h0; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_rebusy = 1'h0; // @[util.scala:114:23] wire _io_hellacache_s2_xcpt_WIRE_ma_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_ma_st = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_pf_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_pf_st = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_gf_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_gf_st = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_ae_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_ae_st = 1'h0; // @[lsu.scala:1797:44] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_core_status_zero1 = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_hellacache_req_bits_mask = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_hellacache_s1_data_mask = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_hellacache_resp_bits_mask = 8'h0; // @[lsu.scala:211:7] wire [7:0] _dmem_req_0_bits_data_T_16 = 8'h0; // @[AMOALU.scala:29:69] wire [7:0] _mem_ldq_e_WIRE_bits_ld_byte_mask = 8'h0; // @[lsu.scala:1064:73] wire [1:0] io_ptw_status_xs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_core_status_xs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_core_status_vs = 2'h0; // @[lsu.scala:211:7] wire [1:0] _exe_tlb_uop_WIRE_iw_p1_speculative_child = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_iw_p2_speculative_child = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_dis_col_sel = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_op1_sel = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_rxq_idx = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_mem_size = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_dst_rtype = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_lrs1_rtype = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_lrs2_rtype = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_fp_typ = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_1_iw_p1_speculative_child = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_iw_p2_speculative_child = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_dis_col_sel = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_op1_sel = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_rxq_idx = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_mem_size = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_dst_rtype = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_lrs1_rtype = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_lrs2_rtype = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_fp_typ = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_T_2_iw_p1_speculative_child = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_iw_p2_speculative_child = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_dis_col_sel = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_op1_sel = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_rxq_idx = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_mem_size = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_dst_rtype = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_lrs1_rtype = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_lrs2_rtype = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_fp_typ = 2'h0; // @[lsu.scala:722:24] wire [1:0] _dmem_req_0_bits_uop_WIRE_iw_p1_speculative_child = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_iw_p2_speculative_child = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_dis_col_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57] wire [1:0] _mem_ldq_e_WIRE_bits_uop_iw_p1_speculative_child = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_iw_p2_speculative_child = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_dis_col_sel = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_op1_sel = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_fp_typ = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_stq_e_WIRE_bits_uop_iw_p1_speculative_child = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_iw_p2_speculative_child = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_dis_col_sel = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_op1_sel = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_fp_typ = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _lcam_uop_WIRE_iw_p1_speculative_child = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_iw_p2_speculative_child = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_dis_col_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57] wire [1:0] wb_spec_wakeups_0_bits_speculative_mask = 2'h0; // @[lsu.scala:1491:29] wire [1:0] wb_slow_wakeups_0_bits_speculative_mask = 2'h0; // @[lsu.scala:1494:29] wire [1:0] slow_wakeups_0_bits_speculative_mask = 2'h0; // @[lsu.scala:1495:26] wire [1:0] w1_bits_out_speculative_mask = 2'h0; // @[util.scala:109:23] wire [1:0] w2_bits_out_speculative_mask = 2'h0; // @[util.scala:109:23] wire [1:0] slow_wakeups_0_out_bits_speculative_mask = 2'h0; // @[util.scala:114:23] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_hellacache_req_bits_cmd = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_hellacache_resp_bits_cmd = 5'h0; // @[lsu.scala:211:7] wire [4:0] _exe_tlb_uop_WIRE_ftq_idx = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_pimm = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_ppred = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_mem_cmd = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_fcn_op = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_1_ftq_idx = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_pimm = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_ppred = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_mem_cmd = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_fcn_op = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_T_2_ftq_idx = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_pimm = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_ppred = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_mem_cmd = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_fcn_op = 5'h0; // @[lsu.scala:722:24] wire [4:0] _dmem_req_0_bits_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_pimm = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ppred = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_fcn_op = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_stq_e_WIRE_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_pimm = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_ppred = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_fcn_op = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _lcam_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57] wire [4:0] iresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:1477:19] wire [4:0] fresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:1478:19] wire [4:0] io_core_iresp_0_out_bits_fflags_bits = 5'h0; // @[util.scala:114:23] wire [6:0] io_hellacache_req_bits_tag = 7'h0; // @[lsu.scala:211:7] wire [6:0] io_hellacache_resp_bits_tag = 7'h0; // @[lsu.scala:211:7] wire [6:0] _exe_tlb_uop_WIRE_pdst = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_prs1 = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_prs2 = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_prs3 = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_stale_pdst = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_1_pdst = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_prs1 = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_prs2 = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_prs3 = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_stale_pdst = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_T_2_pdst = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_prs1 = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_prs2 = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_prs3 = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_stale_pdst = 7'h0; // @[lsu.scala:722:24] wire [6:0] _dmem_req_0_bits_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _mem_ldq_e_WIRE_bits_uop_pdst = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs1 = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs2 = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs3 = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_stq_e_WIRE_bits_uop_pdst = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs1 = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs2 = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs3 = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _lcam_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57] wire [1:0] io_hellacache_req_bits_size = 2'h3; // @[lsu.scala:211:7] wire [1:0] io_hellacache_resp_bits_size = 2'h3; // @[lsu.scala:211:7] wire [1:0] dmem_req_0_bits_data_size_1 = 2'h3; // @[AMOALU.scala:11:18] wire [1:0] dmem_req_0_bits_data_size_2 = 2'h3; // @[AMOALU.scala:11:18] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_2_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_3_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_req_bits_data = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_s1_data_data = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_resp_bits_store_data = 64'h0; // @[lsu.scala:211:7] wire [63:0] _exe_tlb_uop_WIRE_exc_cause = 64'h0; // @[lsu.scala:722:68] wire [63:0] _exe_tlb_uop_WIRE_1_exc_cause = 64'h0; // @[lsu.scala:723:68] wire [63:0] _exe_tlb_uop_T_2_exc_cause = 64'h0; // @[lsu.scala:722:24] wire [63:0] _dmem_req_0_bits_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57] wire [63:0] _dmem_req_0_bits_data_T_19 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_23 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_26 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_27 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_28 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_29 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _mem_ldq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:1064:73] wire [63:0] _mem_ldq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:1064:73] wire [63:0] _mem_stq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:1067:87] wire [63:0] _mem_stq_e_WIRE_bits_data_bits = 64'h0; // @[lsu.scala:1067:87] wire [63:0] _mem_stq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:1067:87] wire [63:0] _lcam_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57] wire io_hellacache_req_bits_phys = 1'h1; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_has_data = 1'h1; // @[lsu.scala:211:7] wire io_hellacache_clock_enabled = 1'h1; // @[lsu.scala:211:7] wire _ldq_wakeup_idx_temp_vec_T_15 = 1'h1; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_15 = 1'h1; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_15 = 1'h1; // @[util.scala:352:72] wire _will_fire_sfence_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_sfence_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_sfence_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_sfence_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_sfence_0_T_5 = 1'h1; // @[lsu.scala:660:31] wire _will_fire_sfence_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_sfence_0_T_8 = 1'h1; // @[lsu.scala:661:31] wire _will_fire_store_commit_fast_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_store_commit_fast_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_store_commit_fast_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_store_commit_fast_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_store_commit_fast_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_store_commit_fast_0_T_5 = 1'h1; // @[lsu.scala:660:31] wire _will_fire_load_agen_exec_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_load_agen_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_load_agen_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_store_agen_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_store_agen_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_release_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_release_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_release_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_release_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_hella_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_hella_incoming_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_hella_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_hella_wakeup_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_hella_wakeup_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_hella_wakeup_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_store_retry_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_store_retry_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_load_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_load_wakeup_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_store_commit_slow_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_store_commit_slow_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_store_commit_slow_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_store_commit_slow_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _dmem_req_0_valid_T_2 = 1'h1; // @[lsu.scala:937:86] wire _stq_clr_head_idx_temp_vec_T_15 = 1'h1; // @[util.scala:352:72] wire _mem_stld_forward_stq_idx_temp_vec_T_15 = 1'h1; // @[util.scala:352:72] wire _l_idx_temp_vec_T_15 = 1'h1; // @[util.scala:352:72] wire _wakeupArbs_0_io_in_1_valid_T_1 = 1'h1; // @[lsu.scala:1459:40] wire wb_spec_wakeups_0_bits_bypassable = 1'h1; // @[lsu.scala:1491:29] wire w1_bits_out_bypassable = 1'h1; // @[util.scala:109:23] wire w2_bits_out_bypassable = 1'h1; // @[util.scala:109:23] wire [1:0] io_hellacache_req_bits_dprv = 2'h1; // @[lsu.scala:211:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[lsu.scala:211:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[lsu.scala:211:7] wire [3:0] _exe_tlb_uop_WIRE_br_tag = 4'h0; // @[lsu.scala:722:68] wire [3:0] _exe_tlb_uop_WIRE_br_type = 4'h0; // @[lsu.scala:722:68] wire [3:0] _exe_tlb_uop_WIRE_ldq_idx = 4'h0; // @[lsu.scala:722:68] wire [3:0] _exe_tlb_uop_WIRE_stq_idx = 4'h0; // @[lsu.scala:722:68] wire [3:0] _exe_tlb_uop_WIRE_1_br_tag = 4'h0; // @[lsu.scala:723:68] wire [3:0] _exe_tlb_uop_WIRE_1_br_type = 4'h0; // @[lsu.scala:723:68] wire [3:0] _exe_tlb_uop_WIRE_1_ldq_idx = 4'h0; // @[lsu.scala:723:68] wire [3:0] _exe_tlb_uop_WIRE_1_stq_idx = 4'h0; // @[lsu.scala:723:68] wire [3:0] _exe_tlb_uop_T_2_br_tag = 4'h0; // @[lsu.scala:722:24] wire [3:0] _exe_tlb_uop_T_2_br_type = 4'h0; // @[lsu.scala:722:24] wire [3:0] _exe_tlb_uop_T_2_ldq_idx = 4'h0; // @[lsu.scala:722:24] wire [3:0] _exe_tlb_uop_T_2_stq_idx = 4'h0; // @[lsu.scala:722:24] wire [3:0] _dmem_req_0_bits_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57] wire [3:0] _dmem_req_0_bits_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57] wire [3:0] _dmem_req_0_bits_uop_WIRE_ldq_idx = 4'h0; // @[consts.scala:141:57] wire [3:0] _dmem_req_0_bits_uop_WIRE_stq_idx = 4'h0; // @[consts.scala:141:57] wire [3:0] _mem_ldq_e_WIRE_bits_uop_br_tag = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_ldq_e_WIRE_bits_uop_br_type = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_ldq_e_WIRE_bits_uop_ldq_idx = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_ldq_e_WIRE_bits_uop_stq_idx = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_ldq_e_WIRE_bits_forward_stq_idx = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_stq_e_WIRE_bits_uop_br_tag = 4'h0; // @[lsu.scala:1067:87] wire [3:0] _mem_stq_e_WIRE_bits_uop_br_type = 4'h0; // @[lsu.scala:1067:87] wire [3:0] _mem_stq_e_WIRE_bits_uop_ldq_idx = 4'h0; // @[lsu.scala:1067:87] wire [3:0] _mem_stq_e_WIRE_bits_uop_stq_idx = 4'h0; // @[lsu.scala:1067:87] wire [3:0] _lcam_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57] wire [3:0] _lcam_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57] wire [3:0] _lcam_uop_WIRE_ldq_idx = 4'h0; // @[consts.scala:141:57] wire [3:0] _lcam_uop_WIRE_stq_idx = 4'h0; // @[consts.scala:141:57] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[lsu.scala:211:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[lsu.scala:211:7] wire [1:0] io_core_status_sxl = 2'h2; // @[lsu.scala:211:7] wire [1:0] io_core_status_uxl = 2'h2; // @[lsu.scala:211:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[lsu.scala:211:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[lsu.scala:211:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[lsu.scala:211:7] wire [5:0] _exe_tlb_uop_WIRE_pc_lob = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_rob_idx = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_ldst = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_lrs1 = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_lrs2 = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_lrs3 = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_1_pc_lob = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_rob_idx = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_ldst = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_lrs1 = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_lrs2 = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_lrs3 = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_T_2_pc_lob = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_rob_idx = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_ldst = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_lrs1 = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_lrs2 = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_lrs3 = 6'h0; // @[lsu.scala:722:24] wire [5:0] _dmem_req_0_bits_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_rob_idx = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57] wire [5:0] _mem_ldq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_rob_idx = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_stq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_rob_idx = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _lcam_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_rob_idx = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_core_commit_debug_insts_0 = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_core_commit_debug_insts_1 = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_hellacache_s2_paddr = 32'h0; // @[lsu.scala:211:7] wire [31:0] _exe_tlb_uop_WIRE_inst = 32'h0; // @[lsu.scala:722:68] wire [31:0] _exe_tlb_uop_WIRE_debug_inst = 32'h0; // @[lsu.scala:722:68] wire [31:0] _exe_tlb_uop_WIRE_1_inst = 32'h0; // @[lsu.scala:723:68] wire [31:0] _exe_tlb_uop_WIRE_1_debug_inst = 32'h0; // @[lsu.scala:723:68] wire [31:0] _exe_tlb_uop_T_2_inst = 32'h0; // @[lsu.scala:722:24] wire [31:0] _exe_tlb_uop_T_2_debug_inst = 32'h0; // @[lsu.scala:722:24] wire [31:0] _dmem_req_0_bits_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _dmem_req_0_bits_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _dmem_req_0_bits_data_T_18 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_22 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_25 = 32'h0; // @[AMOALU.scala:29:69] wire [31:0] _mem_ldq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:1064:73] wire [31:0] _mem_ldq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:1064:73] wire [31:0] _mem_stq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:1067:87] wire [31:0] _mem_stq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:1067:87] wire [31:0] _lcam_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _lcam_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57] wire [39:0] io_hellacache_s2_gpa = 40'h0; // @[lsu.scala:211:7] wire [39:0] _exe_tlb_uop_WIRE_debug_pc = 40'h0; // @[lsu.scala:722:68] wire [39:0] _exe_tlb_uop_WIRE_1_debug_pc = 40'h0; // @[lsu.scala:723:68] wire [39:0] _exe_tlb_uop_T_2_debug_pc = 40'h0; // @[lsu.scala:722:24] wire [39:0] _dmem_req_0_bits_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57] wire [39:0] _mem_ldq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:1064:73] wire [39:0] _mem_ldq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:1064:73] wire [39:0] _mem_stq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:1067:87] wire [39:0] _mem_stq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:1067:87] wire [39:0] _lcam_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57] wire [7:0] _ldq_ld_byte_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _lcam_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _nack_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _forward_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_26 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_41 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_56 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_71 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_86 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_101 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_116 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_131 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_146 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_161 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_176 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_191 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_206 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_221 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_236 = 8'hFF; // @[Mux.scala:126:16] wire [2:0] _exe_tlb_uop_WIRE_imm_sel = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_op2_sel = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_csr_cmd = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_fp_rm = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_debug_fsrc = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_debug_tsrc = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_1_imm_sel = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_op2_sel = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_csr_cmd = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_fp_rm = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_debug_fsrc = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_debug_tsrc = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_T_2_imm_sel = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_op2_sel = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_csr_cmd = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_fp_rm = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_debug_fsrc = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_debug_tsrc = 3'h0; // @[lsu.scala:722:24] wire [2:0] _dmem_req_0_bits_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _mem_ldq_e_WIRE_bits_uop_imm_sel = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_op2_sel = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_csr_cmd = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_fp_rm = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_debug_fsrc = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_debug_tsrc = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_stq_e_WIRE_bits_uop_imm_sel = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_op2_sel = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_csr_cmd = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_fp_rm = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_debug_fsrc = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_debug_tsrc = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _lcam_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57] wire [19:0] _exe_tlb_uop_WIRE_imm_packed = 20'h0; // @[lsu.scala:722:68] wire [19:0] _exe_tlb_uop_WIRE_1_imm_packed = 20'h0; // @[lsu.scala:723:68] wire [19:0] _exe_tlb_uop_T_2_imm_packed = 20'h0; // @[lsu.scala:722:24] wire [19:0] _dmem_req_0_bits_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57] wire [19:0] _mem_ldq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:1064:73] wire [19:0] _mem_stq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:1067:87] wire [19:0] _lcam_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57] wire [11:0] _exe_tlb_uop_WIRE_br_mask = 12'h0; // @[lsu.scala:722:68] wire [11:0] _exe_tlb_uop_WIRE_1_br_mask = 12'h0; // @[lsu.scala:723:68] wire [11:0] _exe_tlb_uop_T_2_br_mask = 12'h0; // @[lsu.scala:722:24] wire [11:0] _dmem_req_0_bits_uop_WIRE_br_mask = 12'h0; // @[consts.scala:141:57] wire [11:0] _mem_ldq_e_WIRE_bits_uop_br_mask = 12'h0; // @[lsu.scala:1064:73] wire [11:0] _mem_stq_e_WIRE_bits_uop_br_mask = 12'h0; // @[lsu.scala:1067:87] wire [11:0] _lcam_uop_WIRE_br_mask = 12'h0; // @[consts.scala:141:57] wire [1:0] io_hellacache_resp_bits_dprv_0 = io_ptw_status_prv_0; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_dv_0 = io_ptw_status_v_0; // @[lsu.scala:211:7] wire [31:0] mem_incoming_uop_out_inst = io_core_agen_0_bits_uop_inst_0; // @[util.scala:104:23] wire [31:0] mem_incoming_uop_out_debug_inst = io_core_agen_0_bits_uop_debug_inst_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_rvc = io_core_agen_0_bits_uop_is_rvc_0; // @[util.scala:104:23] wire [39:0] mem_incoming_uop_out_debug_pc = io_core_agen_0_bits_uop_debug_pc_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_0 = io_core_agen_0_bits_uop_iq_type_0_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_1 = io_core_agen_0_bits_uop_iq_type_1_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_2 = io_core_agen_0_bits_uop_iq_type_2_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_3 = io_core_agen_0_bits_uop_iq_type_3_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_0 = io_core_agen_0_bits_uop_fu_code_0_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_1 = io_core_agen_0_bits_uop_fu_code_1_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_2 = io_core_agen_0_bits_uop_fu_code_2_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_3 = io_core_agen_0_bits_uop_fu_code_3_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_4 = io_core_agen_0_bits_uop_fu_code_4_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_5 = io_core_agen_0_bits_uop_fu_code_5_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_6 = io_core_agen_0_bits_uop_fu_code_6_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_7 = io_core_agen_0_bits_uop_fu_code_7_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_8 = io_core_agen_0_bits_uop_fu_code_8_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_9 = io_core_agen_0_bits_uop_fu_code_9_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_issued = io_core_agen_0_bits_uop_iw_issued_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_issued_partial_agen = io_core_agen_0_bits_uop_iw_issued_partial_agen_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_issued_partial_dgen = io_core_agen_0_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_iw_p1_speculative_child = io_core_agen_0_bits_uop_iw_p1_speculative_child_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_iw_p2_speculative_child = io_core_agen_0_bits_uop_iw_p2_speculative_child_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_p1_bypass_hint = io_core_agen_0_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_p2_bypass_hint = io_core_agen_0_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_p3_bypass_hint = io_core_agen_0_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_dis_col_sel = io_core_agen_0_bits_uop_dis_col_sel_0; // @[util.scala:104:23] wire [3:0] mem_incoming_uop_out_br_tag = io_core_agen_0_bits_uop_br_tag_0; // @[util.scala:104:23] wire [3:0] mem_incoming_uop_out_br_type = io_core_agen_0_bits_uop_br_type_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_sfb = io_core_agen_0_bits_uop_is_sfb_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_fence = io_core_agen_0_bits_uop_is_fence_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_fencei = io_core_agen_0_bits_uop_is_fencei_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_sfence = io_core_agen_0_bits_uop_is_sfence_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_amo = io_core_agen_0_bits_uop_is_amo_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_eret = io_core_agen_0_bits_uop_is_eret_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_sys_pc2epc = io_core_agen_0_bits_uop_is_sys_pc2epc_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_rocc = io_core_agen_0_bits_uop_is_rocc_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_mov = io_core_agen_0_bits_uop_is_mov_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_ftq_idx = io_core_agen_0_bits_uop_ftq_idx_0; // @[util.scala:104:23] wire mem_incoming_uop_out_edge_inst = io_core_agen_0_bits_uop_edge_inst_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_pc_lob = io_core_agen_0_bits_uop_pc_lob_0; // @[util.scala:104:23] wire mem_incoming_uop_out_taken = io_core_agen_0_bits_uop_taken_0; // @[util.scala:104:23] wire mem_incoming_uop_out_imm_rename = io_core_agen_0_bits_uop_imm_rename_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_imm_sel = io_core_agen_0_bits_uop_imm_sel_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_pimm = io_core_agen_0_bits_uop_pimm_0; // @[util.scala:104:23] wire [19:0] mem_incoming_uop_out_imm_packed = io_core_agen_0_bits_uop_imm_packed_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_op1_sel = io_core_agen_0_bits_uop_op1_sel_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_op2_sel = io_core_agen_0_bits_uop_op2_sel_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ldst = io_core_agen_0_bits_uop_fp_ctrl_ldst_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_wen = io_core_agen_0_bits_uop_fp_ctrl_wen_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ren1 = io_core_agen_0_bits_uop_fp_ctrl_ren1_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ren2 = io_core_agen_0_bits_uop_fp_ctrl_ren2_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ren3 = io_core_agen_0_bits_uop_fp_ctrl_ren3_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_swap12 = io_core_agen_0_bits_uop_fp_ctrl_swap12_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_swap23 = io_core_agen_0_bits_uop_fp_ctrl_swap23_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_fp_ctrl_typeTagIn = io_core_agen_0_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_fp_ctrl_typeTagOut = io_core_agen_0_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_fromint = io_core_agen_0_bits_uop_fp_ctrl_fromint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_toint = io_core_agen_0_bits_uop_fp_ctrl_toint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_fastpipe = io_core_agen_0_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_fma = io_core_agen_0_bits_uop_fp_ctrl_fma_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_div = io_core_agen_0_bits_uop_fp_ctrl_div_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_sqrt = io_core_agen_0_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_wflags = io_core_agen_0_bits_uop_fp_ctrl_wflags_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_vec = io_core_agen_0_bits_uop_fp_ctrl_vec_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_rob_idx = io_core_agen_0_bits_uop_rob_idx_0; // @[util.scala:104:23] wire [3:0] ldq_incoming_idx_0 = io_core_agen_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7, :321:49] wire [3:0] mem_incoming_uop_out_ldq_idx = io_core_agen_0_bits_uop_ldq_idx_0; // @[util.scala:104:23] wire [3:0] stq_incoming_idx_0 = io_core_agen_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7, :321:49] wire [3:0] mem_incoming_uop_out_stq_idx = io_core_agen_0_bits_uop_stq_idx_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_rxq_idx = io_core_agen_0_bits_uop_rxq_idx_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_pdst = io_core_agen_0_bits_uop_pdst_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_prs1 = io_core_agen_0_bits_uop_prs1_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_prs2 = io_core_agen_0_bits_uop_prs2_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_prs3 = io_core_agen_0_bits_uop_prs3_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_ppred = io_core_agen_0_bits_uop_ppred_0; // @[util.scala:104:23] wire mem_incoming_uop_out_prs1_busy = io_core_agen_0_bits_uop_prs1_busy_0; // @[util.scala:104:23] wire mem_incoming_uop_out_prs2_busy = io_core_agen_0_bits_uop_prs2_busy_0; // @[util.scala:104:23] wire mem_incoming_uop_out_prs3_busy = io_core_agen_0_bits_uop_prs3_busy_0; // @[util.scala:104:23] wire mem_incoming_uop_out_ppred_busy = io_core_agen_0_bits_uop_ppred_busy_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_stale_pdst = io_core_agen_0_bits_uop_stale_pdst_0; // @[util.scala:104:23] wire mem_incoming_uop_out_exception = io_core_agen_0_bits_uop_exception_0; // @[util.scala:104:23] wire [63:0] mem_incoming_uop_out_exc_cause = io_core_agen_0_bits_uop_exc_cause_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_mem_cmd = io_core_agen_0_bits_uop_mem_cmd_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_mem_size = io_core_agen_0_bits_uop_mem_size_0; // @[util.scala:104:23] wire mem_incoming_uop_out_mem_signed = io_core_agen_0_bits_uop_mem_signed_0; // @[util.scala:104:23] wire mem_incoming_uop_out_uses_ldq = io_core_agen_0_bits_uop_uses_ldq_0; // @[util.scala:104:23] wire mem_incoming_uop_out_uses_stq = io_core_agen_0_bits_uop_uses_stq_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_unique = io_core_agen_0_bits_uop_is_unique_0; // @[util.scala:104:23] wire mem_incoming_uop_out_flush_on_commit = io_core_agen_0_bits_uop_flush_on_commit_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_csr_cmd = io_core_agen_0_bits_uop_csr_cmd_0; // @[util.scala:104:23] wire mem_incoming_uop_out_ldst_is_rs1 = io_core_agen_0_bits_uop_ldst_is_rs1_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_ldst = io_core_agen_0_bits_uop_ldst_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_lrs1 = io_core_agen_0_bits_uop_lrs1_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_lrs2 = io_core_agen_0_bits_uop_lrs2_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_lrs3 = io_core_agen_0_bits_uop_lrs3_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_dst_rtype = io_core_agen_0_bits_uop_dst_rtype_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_lrs1_rtype = io_core_agen_0_bits_uop_lrs1_rtype_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_lrs2_rtype = io_core_agen_0_bits_uop_lrs2_rtype_0; // @[util.scala:104:23] wire mem_incoming_uop_out_frs3_en = io_core_agen_0_bits_uop_frs3_en_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fcn_dw = io_core_agen_0_bits_uop_fcn_dw_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_fcn_op = io_core_agen_0_bits_uop_fcn_op_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_val = io_core_agen_0_bits_uop_fp_val_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_fp_rm = io_core_agen_0_bits_uop_fp_rm_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_fp_typ = io_core_agen_0_bits_uop_fp_typ_0; // @[util.scala:104:23] wire mem_incoming_uop_out_xcpt_pf_if = io_core_agen_0_bits_uop_xcpt_pf_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_xcpt_ae_if = io_core_agen_0_bits_uop_xcpt_ae_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_xcpt_ma_if = io_core_agen_0_bits_uop_xcpt_ma_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_bp_debug_if = io_core_agen_0_bits_uop_bp_debug_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_bp_xcpt_if = io_core_agen_0_bits_uop_bp_xcpt_if_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_debug_fsrc = io_core_agen_0_bits_uop_debug_fsrc_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_debug_tsrc = io_core_agen_0_bits_uop_debug_tsrc_0; // @[util.scala:104:23] wire fresp_0_valid; // @[lsu.scala:1478:19] wire [31:0] fresp_0_bits_uop_inst; // @[lsu.scala:1478:19] wire [31:0] fresp_0_bits_uop_debug_inst; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_rvc; // @[lsu.scala:1478:19] wire [39:0] fresp_0_bits_uop_debug_pc; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_0; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_1; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_2; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_3; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_0; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_1; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_2; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_3; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_4; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_5; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_6; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_7; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_8; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_9; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_issued; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_dis_col_sel; // @[lsu.scala:1478:19] wire [11:0] fresp_0_bits_uop_br_mask; // @[lsu.scala:1478:19] wire [3:0] fresp_0_bits_uop_br_tag; // @[lsu.scala:1478:19] wire [3:0] fresp_0_bits_uop_br_type; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_sfb; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_fence; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_fencei; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_sfence; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_amo; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_eret; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_rocc; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_mov; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_ftq_idx; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_edge_inst; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_pc_lob; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_taken; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_imm_rename; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_imm_sel; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_pimm; // @[lsu.scala:1478:19] wire [19:0] fresp_0_bits_uop_imm_packed; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_op1_sel; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_op2_sel; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_rob_idx; // @[lsu.scala:1478:19] wire [3:0] fresp_0_bits_uop_ldq_idx; // @[lsu.scala:1478:19] wire [3:0] fresp_0_bits_uop_stq_idx; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_rxq_idx; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_pdst; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_prs1; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_prs2; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_prs3; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_ppred; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_prs1_busy; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_prs2_busy; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_prs3_busy; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_ppred_busy; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_stale_pdst; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_exception; // @[lsu.scala:1478:19] wire [63:0] fresp_0_bits_uop_exc_cause; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_mem_cmd; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_mem_size; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_mem_signed; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_uses_ldq; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_uses_stq; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_unique; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_flush_on_commit; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_csr_cmd; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_ldst; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_lrs1; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_lrs2; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_lrs3; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_dst_rtype; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_lrs1_rtype; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_lrs2_rtype; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_frs3_en; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fcn_dw; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_fcn_op; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_val; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_fp_rm; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_fp_typ; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_bp_debug_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_debug_fsrc; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_debug_tsrc; // @[lsu.scala:1478:19] wire [63:0] fresp_0_bits_data; // @[lsu.scala:1478:19] wire can_fire_sfence_0 = io_core_sfence_valid_0; // @[lsu.scala:211:7, :321:49] wire ldq_full; // @[lsu.scala:369:47] wire ldq_full_1; // @[lsu.scala:369:47] wire stq_full; // @[lsu.scala:373:47] wire stq_full_1; // @[lsu.scala:373:47] wire _io_core_clr_bsy_0_valid_T_4; // @[lsu.scala:1107:45] wire _io_core_clr_bsy_1_valid_T_4; // @[lsu.scala:1107:45] wire _io_core_clr_unsafe_0_valid_T_9; // @[lsu.scala:1423:7] wire [11:0] io_dmem_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask_0; // @[lsu.scala:211:7] wire [11:0] io_dmem_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_0_0 = io_core_brupdate_b2_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_1_0 = io_core_brupdate_b2_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_2_0 = io_core_brupdate_b2_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_3_0 = io_core_brupdate_b2_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_0_0 = io_core_brupdate_b2_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_1_0 = io_core_brupdate_b2_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_2_0 = io_core_brupdate_b2_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_3_0 = io_core_brupdate_b2_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_4_0 = io_core_brupdate_b2_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_5_0 = io_core_brupdate_b2_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_6_0 = io_core_brupdate_b2_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_7_0 = io_core_brupdate_b2_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_8_0 = io_core_brupdate_b2_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_9_0 = io_core_brupdate_b2_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_issued_0 = io_core_brupdate_b2_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_issued_partial_agen_0 = io_core_brupdate_b2_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_core_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_iw_p1_speculative_child_0 = io_core_brupdate_b2_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_iw_p2_speculative_child_0 = io_core_brupdate_b2_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_dis_col_sel_0 = io_core_brupdate_b2_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [11:0] io_dmem_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_brupdate_b2_uop_br_type_0 = io_core_brupdate_b2_uop_br_type_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_sfence_0 = io_core_brupdate_b2_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_eret_0 = io_core_brupdate_b2_uop_is_eret_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_rocc_0 = io_core_brupdate_b2_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_mov_0 = io_core_brupdate_b2_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_imm_rename_0 = io_core_brupdate_b2_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_imm_sel_0 = io_core_brupdate_b2_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_pimm_0 = io_core_brupdate_b2_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_dmem_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_op1_sel_0 = io_core_brupdate_b2_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_op2_sel_0 = io_core_brupdate_b2_uop_op2_sel_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ldst_0 = io_core_brupdate_b2_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_wen_0 = io_core_brupdate_b2_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ren1_0 = io_core_brupdate_b2_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ren2_0 = io_core_brupdate_b2_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ren3_0 = io_core_brupdate_b2_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_swap12_0 = io_core_brupdate_b2_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_swap23_0 = io_core_brupdate_b2_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_fromint_0 = io_core_brupdate_b2_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_toint_0 = io_core_brupdate_b2_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_core_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_fma_0 = io_core_brupdate_b2_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_div_0 = io_core_brupdate_b2_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_core_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_wflags_0 = io_core_brupdate_b2_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_vec_0 = io_core_brupdate_b2_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_dmem_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_csr_cmd_0 = io_core_brupdate_b2_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fcn_dw_0 = io_core_brupdate_b2_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_fcn_op_0 = io_core_brupdate_b2_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_fp_rm_0 = io_core_brupdate_b2_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_fp_typ_0 = io_core_brupdate_b2_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_taken_0 = io_core_brupdate_b2_taken_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target_0; // @[lsu.scala:211:7] wire [20:0] io_dmem_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_rob_pnr_idx_0 = io_core_rob_pnr_idx_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_rob_head_idx_0 = io_core_rob_head_idx_0; // @[lsu.scala:211:7] wire io_dmem_exception_0 = io_core_exception_0; // @[lsu.scala:211:7] wire _io_core_fencei_rdy_T_1; // @[lsu.scala:446:42] wire _io_core_lxcpt_valid_T_4; // @[lsu.scala:1450:39] wire _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire dmem_req_0_valid; // @[lsu.scala:877:22] wire [31:0] dmem_req_0_bits_uop_inst; // @[lsu.scala:877:22] wire [31:0] dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:877:22] wire [39:0] dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_0; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_1; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_2; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_3; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_0; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_1; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_2; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_3; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_4; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_5; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_6; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_7; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_8; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_9; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_issued; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_dis_col_sel; // @[lsu.scala:877:22] wire [11:0] dmem_req_0_bits_uop_br_mask; // @[lsu.scala:877:22] wire [3:0] dmem_req_0_bits_uop_br_tag; // @[lsu.scala:877:22] wire [3:0] dmem_req_0_bits_uop_br_type; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_fence; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_sfence; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_amo; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_eret; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_rocc; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_mov; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_taken; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_imm_rename; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_imm_sel; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_pimm; // @[lsu.scala:877:22] wire [19:0] dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_op1_sel; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_op2_sel; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_div; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:877:22] wire [3:0] dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:877:22] wire [3:0] dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_pdst; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_prs1; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_prs2; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_prs3; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_ppred; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_exception; // @[lsu.scala:877:22] wire [63:0] dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_mem_size; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_unique; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_csr_cmd; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_ldst; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_lrs1; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_lrs2; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_lrs3; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fcn_dw; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_fcn_op; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_val; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_fp_rm; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_fp_typ; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:877:22] wire [39:0] dmem_req_0_bits_addr; // @[lsu.scala:877:22] wire [63:0] dmem_req_0_bits_data; // @[lsu.scala:877:22] wire dmem_req_0_bits_is_hella; // @[lsu.scala:877:22] wire _io_dmem_ll_resp_ready_T_2; // @[lsu.scala:1537:55] wire [63:0] io_hellacache_resp_bits_data_word_bypass_0 = io_dmem_ll_resp_bits_data_0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_resp_bits_data_raw_0 = io_dmem_ll_resp_bits_data_0; // @[lsu.scala:211:7] wire will_fire_release_0; // @[lsu.scala:475:41] wire _can_fire_release_T = io_dmem_release_valid_0; // @[lsu.scala:211:7, :598:66] wire io_core_perf_acquire_0 = io_dmem_perf_acquire_0; // @[lsu.scala:211:7] wire io_core_perf_release_0 = io_dmem_perf_release_0; // @[lsu.scala:211:7] wire _io_hellacache_store_pending_T_14; // @[lsu.scala:1804:52] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[lsu.scala:211:7] wire io_ptw_req_bits_valid_0; // @[lsu.scala:211:7] wire io_ptw_req_valid_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_iwakeups_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_iwakeups_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_iwakeups_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [11:0] io_core_iwakeups_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_iwakeups_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_iwakeups_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_iwakeups_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_iwakeups_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_iwakeups_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_iwakeups_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_bypassable_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_speculative_mask_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_rebusy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_valid_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_iresp_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_iresp_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_iresp_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [11:0] io_core_iresp_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_iresp_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_iresp_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_iresp_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_iresp_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_iresp_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_iresp_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [63:0] io_core_iresp_0_bits_data_0; // @[lsu.scala:211:7] wire io_core_iresp_0_valid_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_fresp_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_fresp_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_fresp_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [11:0] io_core_fresp_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_fresp_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_fresp_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_fresp_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_fresp_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_fresp_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_fresp_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [63:0] io_core_fresp_0_bits_data_0; // @[lsu.scala:211:7] wire io_core_fresp_0_valid_0; // @[lsu.scala:211:7] wire [3:0] io_core_dis_ldq_idx_0_0; // @[lsu.scala:211:7] wire [3:0] io_core_dis_ldq_idx_1_0; // @[lsu.scala:211:7] wire [3:0] io_core_dis_stq_idx_0_0; // @[lsu.scala:211:7] wire [3:0] io_core_dis_stq_idx_1_0; // @[lsu.scala:211:7] wire io_core_ldq_full_0_0; // @[lsu.scala:211:7] wire io_core_ldq_full_1_0; // @[lsu.scala:211:7] wire io_core_stq_full_0_0; // @[lsu.scala:211:7] wire io_core_stq_full_1_0; // @[lsu.scala:211:7] wire io_core_clr_bsy_0_valid_0; // @[lsu.scala:211:7] wire [5:0] io_core_clr_bsy_0_bits_0; // @[lsu.scala:211:7] wire io_core_clr_bsy_1_valid_0; // @[lsu.scala:211:7] wire [5:0] io_core_clr_bsy_1_bits_0; // @[lsu.scala:211:7] wire io_core_clr_unsafe_0_valid_0; // @[lsu.scala:211:7] wire [5:0] io_core_clr_unsafe_0_bits_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_lxcpt_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_lxcpt_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_lxcpt_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [11:0] io_core_lxcpt_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_lxcpt_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_lxcpt_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_lxcpt_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_lxcpt_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [3:0] io_core_lxcpt_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_lxcpt_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_cause_0; // @[lsu.scala:211:7] wire [39:0] io_core_lxcpt_bits_badvaddr_0; // @[lsu.scala:211:7] wire io_core_lxcpt_valid_0; // @[lsu.scala:211:7] wire io_core_perf_tlbMiss_0; // @[lsu.scala:211:7] wire io_core_fencei_rdy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_req_bits_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_req_bits_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_req_bits_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [11:0] io_dmem_req_bits_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_req_bits_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_req_bits_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_dmem_req_bits_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_req_bits_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_req_bits_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_dmem_req_bits_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_req_bits_0_bits_addr_0; // @[lsu.scala:211:7] wire [63:0] io_dmem_req_bits_0_bits_data_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_is_hella_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_valid_0; // @[lsu.scala:211:7] wire io_dmem_req_valid_0; // @[lsu.scala:211:7] wire io_dmem_s1_kill_0_0; // @[lsu.scala:211:7] wire io_dmem_ll_resp_ready_0; // @[lsu.scala:211:7] wire io_dmem_release_ready_0; // @[lsu.scala:211:7] wire io_dmem_force_order_0; // @[lsu.scala:211:7] wire io_hellacache_req_ready_0; // @[lsu.scala:211:7] wire [39:0] io_hellacache_resp_bits_addr_0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_resp_bits_data_0; // @[lsu.scala:211:7] wire io_hellacache_resp_valid_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ma_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ma_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_pf_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_pf_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_gf_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_gf_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ae_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ae_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_nack_0; // @[lsu.scala:211:7] wire io_hellacache_store_pending_0; // @[lsu.scala:211:7] reg ldq_valid_0; // @[lsu.scala:218:36] reg ldq_valid_1; // @[lsu.scala:218:36] reg ldq_valid_2; // @[lsu.scala:218:36] reg ldq_valid_3; // @[lsu.scala:218:36] reg ldq_valid_4; // @[lsu.scala:218:36] reg ldq_valid_5; // @[lsu.scala:218:36] reg ldq_valid_6; // @[lsu.scala:218:36] reg ldq_valid_7; // @[lsu.scala:218:36] reg ldq_valid_8; // @[lsu.scala:218:36] reg ldq_valid_9; // @[lsu.scala:218:36] reg ldq_valid_10; // @[lsu.scala:218:36] reg ldq_valid_11; // @[lsu.scala:218:36] reg ldq_valid_12; // @[lsu.scala:218:36] reg ldq_valid_13; // @[lsu.scala:218:36] reg ldq_valid_14; // @[lsu.scala:218:36] reg ldq_valid_15; // @[lsu.scala:218:36] reg [31:0] ldq_uop_0_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_inst = ldq_uop_0_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_17_inst = ldq_uop_0_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_0_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_debug_inst = ldq_uop_0_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_17_debug_inst = ldq_uop_0_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_rvc; // @[lsu.scala:219:36] wire l_uop_is_rvc = ldq_uop_0_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_rvc = ldq_uop_0_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_0_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_debug_pc = ldq_uop_0_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_17_debug_pc = ldq_uop_0_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_0; // @[lsu.scala:219:36] wire l_uop_iq_type_0 = ldq_uop_0_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_17_iq_type_0 = ldq_uop_0_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_1; // @[lsu.scala:219:36] wire l_uop_iq_type_1 = ldq_uop_0_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_17_iq_type_1 = ldq_uop_0_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_2; // @[lsu.scala:219:36] wire l_uop_iq_type_2 = ldq_uop_0_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_17_iq_type_2 = ldq_uop_0_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_3; // @[lsu.scala:219:36] wire l_uop_iq_type_3 = ldq_uop_0_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_17_iq_type_3 = ldq_uop_0_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_0; // @[lsu.scala:219:36] wire l_uop_fu_code_0 = ldq_uop_0_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_0 = ldq_uop_0_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_1; // @[lsu.scala:219:36] wire l_uop_fu_code_1 = ldq_uop_0_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_1 = ldq_uop_0_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_2; // @[lsu.scala:219:36] wire l_uop_fu_code_2 = ldq_uop_0_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_2 = ldq_uop_0_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_3; // @[lsu.scala:219:36] wire l_uop_fu_code_3 = ldq_uop_0_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_3 = ldq_uop_0_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_4; // @[lsu.scala:219:36] wire l_uop_fu_code_4 = ldq_uop_0_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_4 = ldq_uop_0_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_5; // @[lsu.scala:219:36] wire l_uop_fu_code_5 = ldq_uop_0_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_5 = ldq_uop_0_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_6; // @[lsu.scala:219:36] wire l_uop_fu_code_6 = ldq_uop_0_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_6 = ldq_uop_0_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_7; // @[lsu.scala:219:36] wire l_uop_fu_code_7 = ldq_uop_0_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_7 = ldq_uop_0_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_8; // @[lsu.scala:219:36] wire l_uop_fu_code_8 = ldq_uop_0_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_8 = ldq_uop_0_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_9; // @[lsu.scala:219:36] wire l_uop_fu_code_9 = ldq_uop_0_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_17_fu_code_9 = ldq_uop_0_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_issued; // @[lsu.scala:219:36] wire l_uop_iw_issued = ldq_uop_0_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_17_iw_issued = ldq_uop_0_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_iw_issued_partial_agen = ldq_uop_0_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_17_iw_issued_partial_agen = ldq_uop_0_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_iw_issued_partial_dgen = ldq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_17_iw_issued_partial_dgen = ldq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_iw_p1_speculative_child = ldq_uop_0_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_iw_p1_speculative_child = ldq_uop_0_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_iw_p2_speculative_child = ldq_uop_0_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_iw_p2_speculative_child = ldq_uop_0_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_iw_p1_bypass_hint = ldq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_17_iw_p1_bypass_hint = ldq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_iw_p2_bypass_hint = ldq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_17_iw_p2_bypass_hint = ldq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_iw_p3_bypass_hint = ldq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_17_iw_p3_bypass_hint = ldq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_dis_col_sel = ldq_uop_0_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_dis_col_sel = ldq_uop_0_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_0_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_br_mask = ldq_uop_0_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_17_br_mask = ldq_uop_0_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_0_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_br_tag = ldq_uop_0_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_17_br_tag = ldq_uop_0_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_0_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_br_type = ldq_uop_0_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_17_br_type = ldq_uop_0_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_sfb; // @[lsu.scala:219:36] wire l_uop_is_sfb = ldq_uop_0_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_sfb = ldq_uop_0_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_fence; // @[lsu.scala:219:36] wire l_uop_is_fence = ldq_uop_0_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_fence = ldq_uop_0_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_fencei; // @[lsu.scala:219:36] wire l_uop_is_fencei = ldq_uop_0_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_fencei = ldq_uop_0_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_sfence; // @[lsu.scala:219:36] wire l_uop_is_sfence = ldq_uop_0_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_sfence = ldq_uop_0_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_amo; // @[lsu.scala:219:36] wire l_uop_is_amo = ldq_uop_0_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_amo = ldq_uop_0_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_eret; // @[lsu.scala:219:36] wire l_uop_is_eret = ldq_uop_0_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_eret = ldq_uop_0_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_is_sys_pc2epc = ldq_uop_0_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_sys_pc2epc = ldq_uop_0_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_rocc; // @[lsu.scala:219:36] wire l_uop_is_rocc = ldq_uop_0_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_rocc = ldq_uop_0_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_mov; // @[lsu.scala:219:36] wire l_uop_is_mov = ldq_uop_0_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_mov = ldq_uop_0_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_ftq_idx = ldq_uop_0_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_17_ftq_idx = ldq_uop_0_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_edge_inst; // @[lsu.scala:219:36] wire l_uop_edge_inst = ldq_uop_0_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_17_edge_inst = ldq_uop_0_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_pc_lob = ldq_uop_0_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_17_pc_lob = ldq_uop_0_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_taken; // @[lsu.scala:219:36] wire l_uop_taken = ldq_uop_0_taken; // @[lsu.scala:219:36, :1191:37] wire uop_17_taken = ldq_uop_0_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_imm_rename; // @[lsu.scala:219:36] wire l_uop_imm_rename = ldq_uop_0_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_17_imm_rename = ldq_uop_0_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_imm_sel = ldq_uop_0_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_17_imm_sel = ldq_uop_0_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_pimm = ldq_uop_0_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_17_pimm = ldq_uop_0_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_0_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_imm_packed = ldq_uop_0_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_17_imm_packed = ldq_uop_0_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_op1_sel = ldq_uop_0_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_op1_sel = ldq_uop_0_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_op2_sel = ldq_uop_0_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_17_op2_sel = ldq_uop_0_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ldst = ldq_uop_0_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_ldst = ldq_uop_0_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_wen = ldq_uop_0_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_wen = ldq_uop_0_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ren1 = ldq_uop_0_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_ren1 = ldq_uop_0_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ren2 = ldq_uop_0_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_ren2 = ldq_uop_0_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ren3 = ldq_uop_0_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_ren3 = ldq_uop_0_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_swap12 = ldq_uop_0_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_swap12 = ldq_uop_0_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_swap23 = ldq_uop_0_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_swap23 = ldq_uop_0_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_fp_ctrl_typeTagIn = ldq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_fp_ctrl_typeTagIn = ldq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_fp_ctrl_typeTagOut = ldq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_fp_ctrl_typeTagOut = ldq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_fromint = ldq_uop_0_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_fromint = ldq_uop_0_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_toint = ldq_uop_0_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_toint = ldq_uop_0_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_fastpipe = ldq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_fastpipe = ldq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_fma = ldq_uop_0_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_fma = ldq_uop_0_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_div = ldq_uop_0_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_div = ldq_uop_0_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_sqrt = ldq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_sqrt = ldq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_wflags = ldq_uop_0_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_wflags = ldq_uop_0_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_vec = ldq_uop_0_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_ctrl_vec = ldq_uop_0_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_rob_idx = ldq_uop_0_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_17_rob_idx = ldq_uop_0_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_0_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_ldq_idx = ldq_uop_0_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_17_ldq_idx = ldq_uop_0_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_0_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_stq_idx = ldq_uop_0_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_17_stq_idx = ldq_uop_0_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_rxq_idx = ldq_uop_0_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_rxq_idx = ldq_uop_0_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_pdst = ldq_uop_0_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_17_pdst = ldq_uop_0_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_prs1 = ldq_uop_0_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_17_prs1 = ldq_uop_0_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_prs2 = ldq_uop_0_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_17_prs2 = ldq_uop_0_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_prs3 = ldq_uop_0_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_17_prs3 = ldq_uop_0_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_ppred = ldq_uop_0_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_17_ppred = ldq_uop_0_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_prs1_busy; // @[lsu.scala:219:36] wire l_uop_prs1_busy = ldq_uop_0_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_17_prs1_busy = ldq_uop_0_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_prs2_busy; // @[lsu.scala:219:36] wire l_uop_prs2_busy = ldq_uop_0_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_17_prs2_busy = ldq_uop_0_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_prs3_busy; // @[lsu.scala:219:36] wire l_uop_prs3_busy = ldq_uop_0_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_17_prs3_busy = ldq_uop_0_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_ppred_busy; // @[lsu.scala:219:36] wire l_uop_ppred_busy = ldq_uop_0_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_17_ppred_busy = ldq_uop_0_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_stale_pdst = ldq_uop_0_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_17_stale_pdst = ldq_uop_0_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_exception; // @[lsu.scala:219:36] wire l_uop_exception = ldq_uop_0_exception; // @[lsu.scala:219:36, :1191:37] wire uop_17_exception = ldq_uop_0_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_0_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_exc_cause = ldq_uop_0_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_17_exc_cause = ldq_uop_0_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_mem_cmd = ldq_uop_0_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_17_mem_cmd = ldq_uop_0_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_mem_size = ldq_uop_0_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_mem_size = ldq_uop_0_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_mem_signed; // @[lsu.scala:219:36] wire l_uop_mem_signed = ldq_uop_0_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_17_mem_signed = ldq_uop_0_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_uses_ldq; // @[lsu.scala:219:36] wire l_uop_uses_ldq = ldq_uop_0_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_17_uses_ldq = ldq_uop_0_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_uses_stq; // @[lsu.scala:219:36] wire l_uop_uses_stq = ldq_uop_0_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_17_uses_stq = ldq_uop_0_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_unique; // @[lsu.scala:219:36] wire l_uop_is_unique = ldq_uop_0_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_17_is_unique = ldq_uop_0_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_flush_on_commit = ldq_uop_0_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_17_flush_on_commit = ldq_uop_0_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_csr_cmd = ldq_uop_0_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_17_csr_cmd = ldq_uop_0_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_ldst_is_rs1 = ldq_uop_0_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_17_ldst_is_rs1 = ldq_uop_0_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_ldst = ldq_uop_0_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_17_ldst = ldq_uop_0_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_lrs1 = ldq_uop_0_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_17_lrs1 = ldq_uop_0_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_lrs2 = ldq_uop_0_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_17_lrs2 = ldq_uop_0_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_lrs3 = ldq_uop_0_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_17_lrs3 = ldq_uop_0_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_dst_rtype = ldq_uop_0_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_dst_rtype = ldq_uop_0_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_lrs1_rtype = ldq_uop_0_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_lrs1_rtype = ldq_uop_0_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_lrs2_rtype = ldq_uop_0_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_lrs2_rtype = ldq_uop_0_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_frs3_en; // @[lsu.scala:219:36] wire l_uop_frs3_en = ldq_uop_0_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_17_frs3_en = ldq_uop_0_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fcn_dw; // @[lsu.scala:219:36] wire l_uop_fcn_dw = ldq_uop_0_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_17_fcn_dw = ldq_uop_0_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_fcn_op = ldq_uop_0_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_17_fcn_op = ldq_uop_0_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_val; // @[lsu.scala:219:36] wire l_uop_fp_val = ldq_uop_0_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_17_fp_val = ldq_uop_0_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_fp_rm = ldq_uop_0_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_17_fp_rm = ldq_uop_0_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_fp_typ = ldq_uop_0_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_17_fp_typ = ldq_uop_0_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_xcpt_pf_if = ldq_uop_0_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_17_xcpt_pf_if = ldq_uop_0_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_xcpt_ae_if = ldq_uop_0_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_17_xcpt_ae_if = ldq_uop_0_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_xcpt_ma_if = ldq_uop_0_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_17_xcpt_ma_if = ldq_uop_0_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_bp_debug_if = ldq_uop_0_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_17_bp_debug_if = ldq_uop_0_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_bp_xcpt_if = ldq_uop_0_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_17_bp_xcpt_if = ldq_uop_0_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_debug_fsrc = ldq_uop_0_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_17_debug_fsrc = ldq_uop_0_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_debug_tsrc = ldq_uop_0_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_17_debug_tsrc = ldq_uop_0_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_1_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_1_inst = ldq_uop_1_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_18_inst = ldq_uop_1_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_1_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_1_debug_inst = ldq_uop_1_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_18_debug_inst = ldq_uop_1_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_rvc; // @[lsu.scala:219:36] wire l_uop_1_is_rvc = ldq_uop_1_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_rvc = ldq_uop_1_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_1_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_1_debug_pc = ldq_uop_1_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_18_debug_pc = ldq_uop_1_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_0; // @[lsu.scala:219:36] wire l_uop_1_iq_type_0 = ldq_uop_1_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_18_iq_type_0 = ldq_uop_1_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_1; // @[lsu.scala:219:36] wire l_uop_1_iq_type_1 = ldq_uop_1_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_18_iq_type_1 = ldq_uop_1_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_2; // @[lsu.scala:219:36] wire l_uop_1_iq_type_2 = ldq_uop_1_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_18_iq_type_2 = ldq_uop_1_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_3; // @[lsu.scala:219:36] wire l_uop_1_iq_type_3 = ldq_uop_1_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_18_iq_type_3 = ldq_uop_1_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_0; // @[lsu.scala:219:36] wire l_uop_1_fu_code_0 = ldq_uop_1_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_0 = ldq_uop_1_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_1; // @[lsu.scala:219:36] wire l_uop_1_fu_code_1 = ldq_uop_1_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_1 = ldq_uop_1_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_2; // @[lsu.scala:219:36] wire l_uop_1_fu_code_2 = ldq_uop_1_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_2 = ldq_uop_1_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_3; // @[lsu.scala:219:36] wire l_uop_1_fu_code_3 = ldq_uop_1_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_3 = ldq_uop_1_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_4; // @[lsu.scala:219:36] wire l_uop_1_fu_code_4 = ldq_uop_1_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_4 = ldq_uop_1_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_5; // @[lsu.scala:219:36] wire l_uop_1_fu_code_5 = ldq_uop_1_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_5 = ldq_uop_1_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_6; // @[lsu.scala:219:36] wire l_uop_1_fu_code_6 = ldq_uop_1_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_6 = ldq_uop_1_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_7; // @[lsu.scala:219:36] wire l_uop_1_fu_code_7 = ldq_uop_1_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_7 = ldq_uop_1_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_8; // @[lsu.scala:219:36] wire l_uop_1_fu_code_8 = ldq_uop_1_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_8 = ldq_uop_1_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_9; // @[lsu.scala:219:36] wire l_uop_1_fu_code_9 = ldq_uop_1_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_18_fu_code_9 = ldq_uop_1_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_issued; // @[lsu.scala:219:36] wire l_uop_1_iw_issued = ldq_uop_1_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_18_iw_issued = ldq_uop_1_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_1_iw_issued_partial_agen = ldq_uop_1_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_18_iw_issued_partial_agen = ldq_uop_1_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_1_iw_issued_partial_dgen = ldq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_18_iw_issued_partial_dgen = ldq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_1_iw_p1_speculative_child = ldq_uop_1_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_iw_p1_speculative_child = ldq_uop_1_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_1_iw_p2_speculative_child = ldq_uop_1_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_iw_p2_speculative_child = ldq_uop_1_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_1_iw_p1_bypass_hint = ldq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_18_iw_p1_bypass_hint = ldq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_1_iw_p2_bypass_hint = ldq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_18_iw_p2_bypass_hint = ldq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_1_iw_p3_bypass_hint = ldq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_18_iw_p3_bypass_hint = ldq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_1_dis_col_sel = ldq_uop_1_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_dis_col_sel = ldq_uop_1_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_1_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_1_br_mask = ldq_uop_1_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_18_br_mask = ldq_uop_1_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_1_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_1_br_tag = ldq_uop_1_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_18_br_tag = ldq_uop_1_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_1_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_1_br_type = ldq_uop_1_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_18_br_type = ldq_uop_1_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_sfb; // @[lsu.scala:219:36] wire l_uop_1_is_sfb = ldq_uop_1_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_sfb = ldq_uop_1_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_fence; // @[lsu.scala:219:36] wire l_uop_1_is_fence = ldq_uop_1_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_fence = ldq_uop_1_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_fencei; // @[lsu.scala:219:36] wire l_uop_1_is_fencei = ldq_uop_1_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_fencei = ldq_uop_1_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_sfence; // @[lsu.scala:219:36] wire l_uop_1_is_sfence = ldq_uop_1_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_sfence = ldq_uop_1_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_amo; // @[lsu.scala:219:36] wire l_uop_1_is_amo = ldq_uop_1_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_amo = ldq_uop_1_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_eret; // @[lsu.scala:219:36] wire l_uop_1_is_eret = ldq_uop_1_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_eret = ldq_uop_1_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_1_is_sys_pc2epc = ldq_uop_1_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_sys_pc2epc = ldq_uop_1_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_rocc; // @[lsu.scala:219:36] wire l_uop_1_is_rocc = ldq_uop_1_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_rocc = ldq_uop_1_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_mov; // @[lsu.scala:219:36] wire l_uop_1_is_mov = ldq_uop_1_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_mov = ldq_uop_1_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_1_ftq_idx = ldq_uop_1_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_18_ftq_idx = ldq_uop_1_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_edge_inst; // @[lsu.scala:219:36] wire l_uop_1_edge_inst = ldq_uop_1_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_18_edge_inst = ldq_uop_1_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_1_pc_lob = ldq_uop_1_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_18_pc_lob = ldq_uop_1_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_taken; // @[lsu.scala:219:36] wire l_uop_1_taken = ldq_uop_1_taken; // @[lsu.scala:219:36, :1191:37] wire uop_18_taken = ldq_uop_1_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_imm_rename; // @[lsu.scala:219:36] wire l_uop_1_imm_rename = ldq_uop_1_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_18_imm_rename = ldq_uop_1_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_1_imm_sel = ldq_uop_1_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_18_imm_sel = ldq_uop_1_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_1_pimm = ldq_uop_1_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_18_pimm = ldq_uop_1_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_1_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_1_imm_packed = ldq_uop_1_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_18_imm_packed = ldq_uop_1_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_1_op1_sel = ldq_uop_1_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_op1_sel = ldq_uop_1_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_1_op2_sel = ldq_uop_1_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_18_op2_sel = ldq_uop_1_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ldst = ldq_uop_1_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_ldst = ldq_uop_1_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_wen = ldq_uop_1_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_wen = ldq_uop_1_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ren1 = ldq_uop_1_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_ren1 = ldq_uop_1_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ren2 = ldq_uop_1_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_ren2 = ldq_uop_1_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ren3 = ldq_uop_1_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_ren3 = ldq_uop_1_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_swap12 = ldq_uop_1_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_swap12 = ldq_uop_1_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_swap23 = ldq_uop_1_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_swap23 = ldq_uop_1_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_1_fp_ctrl_typeTagIn = ldq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_fp_ctrl_typeTagIn = ldq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_1_fp_ctrl_typeTagOut = ldq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_fp_ctrl_typeTagOut = ldq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_fromint = ldq_uop_1_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_fromint = ldq_uop_1_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_toint = ldq_uop_1_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_toint = ldq_uop_1_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_fastpipe = ldq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_fastpipe = ldq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_fma = ldq_uop_1_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_fma = ldq_uop_1_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_div = ldq_uop_1_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_div = ldq_uop_1_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_sqrt = ldq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_sqrt = ldq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_wflags = ldq_uop_1_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_wflags = ldq_uop_1_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_vec = ldq_uop_1_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_ctrl_vec = ldq_uop_1_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_1_rob_idx = ldq_uop_1_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_18_rob_idx = ldq_uop_1_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_1_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_1_ldq_idx = ldq_uop_1_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_18_ldq_idx = ldq_uop_1_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_1_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_1_stq_idx = ldq_uop_1_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_18_stq_idx = ldq_uop_1_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_1_rxq_idx = ldq_uop_1_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_rxq_idx = ldq_uop_1_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_1_pdst = ldq_uop_1_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_18_pdst = ldq_uop_1_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_1_prs1 = ldq_uop_1_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_18_prs1 = ldq_uop_1_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_1_prs2 = ldq_uop_1_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_18_prs2 = ldq_uop_1_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_1_prs3 = ldq_uop_1_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_18_prs3 = ldq_uop_1_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_1_ppred = ldq_uop_1_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_18_ppred = ldq_uop_1_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_prs1_busy; // @[lsu.scala:219:36] wire l_uop_1_prs1_busy = ldq_uop_1_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_18_prs1_busy = ldq_uop_1_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_prs2_busy; // @[lsu.scala:219:36] wire l_uop_1_prs2_busy = ldq_uop_1_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_18_prs2_busy = ldq_uop_1_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_prs3_busy; // @[lsu.scala:219:36] wire l_uop_1_prs3_busy = ldq_uop_1_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_18_prs3_busy = ldq_uop_1_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_ppred_busy; // @[lsu.scala:219:36] wire l_uop_1_ppred_busy = ldq_uop_1_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_18_ppred_busy = ldq_uop_1_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_1_stale_pdst = ldq_uop_1_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_18_stale_pdst = ldq_uop_1_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_exception; // @[lsu.scala:219:36] wire l_uop_1_exception = ldq_uop_1_exception; // @[lsu.scala:219:36, :1191:37] wire uop_18_exception = ldq_uop_1_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_1_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_1_exc_cause = ldq_uop_1_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_18_exc_cause = ldq_uop_1_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_1_mem_cmd = ldq_uop_1_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_18_mem_cmd = ldq_uop_1_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_1_mem_size = ldq_uop_1_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_mem_size = ldq_uop_1_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_mem_signed; // @[lsu.scala:219:36] wire l_uop_1_mem_signed = ldq_uop_1_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_18_mem_signed = ldq_uop_1_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_uses_ldq; // @[lsu.scala:219:36] wire l_uop_1_uses_ldq = ldq_uop_1_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_18_uses_ldq = ldq_uop_1_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_uses_stq; // @[lsu.scala:219:36] wire l_uop_1_uses_stq = ldq_uop_1_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_18_uses_stq = ldq_uop_1_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_unique; // @[lsu.scala:219:36] wire l_uop_1_is_unique = ldq_uop_1_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_18_is_unique = ldq_uop_1_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_1_flush_on_commit = ldq_uop_1_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_18_flush_on_commit = ldq_uop_1_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_1_csr_cmd = ldq_uop_1_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_18_csr_cmd = ldq_uop_1_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_1_ldst_is_rs1 = ldq_uop_1_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_18_ldst_is_rs1 = ldq_uop_1_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_1_ldst = ldq_uop_1_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_18_ldst = ldq_uop_1_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_1_lrs1 = ldq_uop_1_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_18_lrs1 = ldq_uop_1_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_1_lrs2 = ldq_uop_1_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_18_lrs2 = ldq_uop_1_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_1_lrs3 = ldq_uop_1_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_18_lrs3 = ldq_uop_1_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_1_dst_rtype = ldq_uop_1_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_dst_rtype = ldq_uop_1_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_1_lrs1_rtype = ldq_uop_1_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_lrs1_rtype = ldq_uop_1_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_1_lrs2_rtype = ldq_uop_1_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_lrs2_rtype = ldq_uop_1_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_frs3_en; // @[lsu.scala:219:36] wire l_uop_1_frs3_en = ldq_uop_1_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_18_frs3_en = ldq_uop_1_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fcn_dw; // @[lsu.scala:219:36] wire l_uop_1_fcn_dw = ldq_uop_1_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_18_fcn_dw = ldq_uop_1_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_1_fcn_op = ldq_uop_1_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_18_fcn_op = ldq_uop_1_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_val; // @[lsu.scala:219:36] wire l_uop_1_fp_val = ldq_uop_1_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_18_fp_val = ldq_uop_1_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_1_fp_rm = ldq_uop_1_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_18_fp_rm = ldq_uop_1_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_1_fp_typ = ldq_uop_1_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_18_fp_typ = ldq_uop_1_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_1_xcpt_pf_if = ldq_uop_1_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_18_xcpt_pf_if = ldq_uop_1_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_1_xcpt_ae_if = ldq_uop_1_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_18_xcpt_ae_if = ldq_uop_1_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_1_xcpt_ma_if = ldq_uop_1_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_18_xcpt_ma_if = ldq_uop_1_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_1_bp_debug_if = ldq_uop_1_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_18_bp_debug_if = ldq_uop_1_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_1_bp_xcpt_if = ldq_uop_1_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_18_bp_xcpt_if = ldq_uop_1_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_1_debug_fsrc = ldq_uop_1_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_18_debug_fsrc = ldq_uop_1_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_1_debug_tsrc = ldq_uop_1_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_18_debug_tsrc = ldq_uop_1_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_2_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_2_inst = ldq_uop_2_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_19_inst = ldq_uop_2_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_2_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_2_debug_inst = ldq_uop_2_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_19_debug_inst = ldq_uop_2_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_rvc; // @[lsu.scala:219:36] wire l_uop_2_is_rvc = ldq_uop_2_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_rvc = ldq_uop_2_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_2_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_2_debug_pc = ldq_uop_2_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_19_debug_pc = ldq_uop_2_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_0; // @[lsu.scala:219:36] wire l_uop_2_iq_type_0 = ldq_uop_2_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_19_iq_type_0 = ldq_uop_2_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_1; // @[lsu.scala:219:36] wire l_uop_2_iq_type_1 = ldq_uop_2_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_19_iq_type_1 = ldq_uop_2_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_2; // @[lsu.scala:219:36] wire l_uop_2_iq_type_2 = ldq_uop_2_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_19_iq_type_2 = ldq_uop_2_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_3; // @[lsu.scala:219:36] wire l_uop_2_iq_type_3 = ldq_uop_2_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_19_iq_type_3 = ldq_uop_2_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_0; // @[lsu.scala:219:36] wire l_uop_2_fu_code_0 = ldq_uop_2_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_0 = ldq_uop_2_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_1; // @[lsu.scala:219:36] wire l_uop_2_fu_code_1 = ldq_uop_2_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_1 = ldq_uop_2_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_2; // @[lsu.scala:219:36] wire l_uop_2_fu_code_2 = ldq_uop_2_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_2 = ldq_uop_2_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_3; // @[lsu.scala:219:36] wire l_uop_2_fu_code_3 = ldq_uop_2_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_3 = ldq_uop_2_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_4; // @[lsu.scala:219:36] wire l_uop_2_fu_code_4 = ldq_uop_2_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_4 = ldq_uop_2_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_5; // @[lsu.scala:219:36] wire l_uop_2_fu_code_5 = ldq_uop_2_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_5 = ldq_uop_2_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_6; // @[lsu.scala:219:36] wire l_uop_2_fu_code_6 = ldq_uop_2_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_6 = ldq_uop_2_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_7; // @[lsu.scala:219:36] wire l_uop_2_fu_code_7 = ldq_uop_2_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_7 = ldq_uop_2_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_8; // @[lsu.scala:219:36] wire l_uop_2_fu_code_8 = ldq_uop_2_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_8 = ldq_uop_2_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_9; // @[lsu.scala:219:36] wire l_uop_2_fu_code_9 = ldq_uop_2_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_19_fu_code_9 = ldq_uop_2_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_issued; // @[lsu.scala:219:36] wire l_uop_2_iw_issued = ldq_uop_2_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_19_iw_issued = ldq_uop_2_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_2_iw_issued_partial_agen = ldq_uop_2_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_19_iw_issued_partial_agen = ldq_uop_2_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_2_iw_issued_partial_dgen = ldq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_19_iw_issued_partial_dgen = ldq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_2_iw_p1_speculative_child = ldq_uop_2_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_iw_p1_speculative_child = ldq_uop_2_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_2_iw_p2_speculative_child = ldq_uop_2_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_iw_p2_speculative_child = ldq_uop_2_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_2_iw_p1_bypass_hint = ldq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_19_iw_p1_bypass_hint = ldq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_2_iw_p2_bypass_hint = ldq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_19_iw_p2_bypass_hint = ldq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_2_iw_p3_bypass_hint = ldq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_19_iw_p3_bypass_hint = ldq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_2_dis_col_sel = ldq_uop_2_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_dis_col_sel = ldq_uop_2_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_2_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_2_br_mask = ldq_uop_2_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_19_br_mask = ldq_uop_2_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_2_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_2_br_tag = ldq_uop_2_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_19_br_tag = ldq_uop_2_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_2_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_2_br_type = ldq_uop_2_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_19_br_type = ldq_uop_2_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_sfb; // @[lsu.scala:219:36] wire l_uop_2_is_sfb = ldq_uop_2_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_sfb = ldq_uop_2_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_fence; // @[lsu.scala:219:36] wire l_uop_2_is_fence = ldq_uop_2_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_fence = ldq_uop_2_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_fencei; // @[lsu.scala:219:36] wire l_uop_2_is_fencei = ldq_uop_2_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_fencei = ldq_uop_2_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_sfence; // @[lsu.scala:219:36] wire l_uop_2_is_sfence = ldq_uop_2_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_sfence = ldq_uop_2_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_amo; // @[lsu.scala:219:36] wire l_uop_2_is_amo = ldq_uop_2_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_amo = ldq_uop_2_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_eret; // @[lsu.scala:219:36] wire l_uop_2_is_eret = ldq_uop_2_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_eret = ldq_uop_2_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_2_is_sys_pc2epc = ldq_uop_2_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_sys_pc2epc = ldq_uop_2_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_rocc; // @[lsu.scala:219:36] wire l_uop_2_is_rocc = ldq_uop_2_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_rocc = ldq_uop_2_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_mov; // @[lsu.scala:219:36] wire l_uop_2_is_mov = ldq_uop_2_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_mov = ldq_uop_2_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_2_ftq_idx = ldq_uop_2_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_19_ftq_idx = ldq_uop_2_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_edge_inst; // @[lsu.scala:219:36] wire l_uop_2_edge_inst = ldq_uop_2_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_19_edge_inst = ldq_uop_2_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_2_pc_lob = ldq_uop_2_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_19_pc_lob = ldq_uop_2_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_taken; // @[lsu.scala:219:36] wire l_uop_2_taken = ldq_uop_2_taken; // @[lsu.scala:219:36, :1191:37] wire uop_19_taken = ldq_uop_2_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_imm_rename; // @[lsu.scala:219:36] wire l_uop_2_imm_rename = ldq_uop_2_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_19_imm_rename = ldq_uop_2_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_2_imm_sel = ldq_uop_2_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_19_imm_sel = ldq_uop_2_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_2_pimm = ldq_uop_2_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_19_pimm = ldq_uop_2_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_2_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_2_imm_packed = ldq_uop_2_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_19_imm_packed = ldq_uop_2_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_2_op1_sel = ldq_uop_2_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_op1_sel = ldq_uop_2_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_2_op2_sel = ldq_uop_2_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_19_op2_sel = ldq_uop_2_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ldst = ldq_uop_2_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_ldst = ldq_uop_2_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_wen = ldq_uop_2_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_wen = ldq_uop_2_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ren1 = ldq_uop_2_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_ren1 = ldq_uop_2_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ren2 = ldq_uop_2_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_ren2 = ldq_uop_2_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ren3 = ldq_uop_2_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_ren3 = ldq_uop_2_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_swap12 = ldq_uop_2_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_swap12 = ldq_uop_2_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_swap23 = ldq_uop_2_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_swap23 = ldq_uop_2_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_2_fp_ctrl_typeTagIn = ldq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_fp_ctrl_typeTagIn = ldq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_2_fp_ctrl_typeTagOut = ldq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_fp_ctrl_typeTagOut = ldq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_fromint = ldq_uop_2_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_fromint = ldq_uop_2_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_toint = ldq_uop_2_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_toint = ldq_uop_2_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_fastpipe = ldq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_fastpipe = ldq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_fma = ldq_uop_2_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_fma = ldq_uop_2_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_div = ldq_uop_2_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_div = ldq_uop_2_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_sqrt = ldq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_sqrt = ldq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_wflags = ldq_uop_2_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_wflags = ldq_uop_2_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_vec = ldq_uop_2_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_ctrl_vec = ldq_uop_2_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_2_rob_idx = ldq_uop_2_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_19_rob_idx = ldq_uop_2_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_2_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_2_ldq_idx = ldq_uop_2_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_19_ldq_idx = ldq_uop_2_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_2_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_2_stq_idx = ldq_uop_2_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_19_stq_idx = ldq_uop_2_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_2_rxq_idx = ldq_uop_2_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_rxq_idx = ldq_uop_2_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_2_pdst = ldq_uop_2_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_19_pdst = ldq_uop_2_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_2_prs1 = ldq_uop_2_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_19_prs1 = ldq_uop_2_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_2_prs2 = ldq_uop_2_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_19_prs2 = ldq_uop_2_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_2_prs3 = ldq_uop_2_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_19_prs3 = ldq_uop_2_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_2_ppred = ldq_uop_2_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_19_ppred = ldq_uop_2_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_prs1_busy; // @[lsu.scala:219:36] wire l_uop_2_prs1_busy = ldq_uop_2_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_19_prs1_busy = ldq_uop_2_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_prs2_busy; // @[lsu.scala:219:36] wire l_uop_2_prs2_busy = ldq_uop_2_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_19_prs2_busy = ldq_uop_2_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_prs3_busy; // @[lsu.scala:219:36] wire l_uop_2_prs3_busy = ldq_uop_2_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_19_prs3_busy = ldq_uop_2_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_ppred_busy; // @[lsu.scala:219:36] wire l_uop_2_ppred_busy = ldq_uop_2_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_19_ppred_busy = ldq_uop_2_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_2_stale_pdst = ldq_uop_2_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_19_stale_pdst = ldq_uop_2_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_exception; // @[lsu.scala:219:36] wire l_uop_2_exception = ldq_uop_2_exception; // @[lsu.scala:219:36, :1191:37] wire uop_19_exception = ldq_uop_2_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_2_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_2_exc_cause = ldq_uop_2_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_19_exc_cause = ldq_uop_2_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_2_mem_cmd = ldq_uop_2_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_19_mem_cmd = ldq_uop_2_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_2_mem_size = ldq_uop_2_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_mem_size = ldq_uop_2_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_mem_signed; // @[lsu.scala:219:36] wire l_uop_2_mem_signed = ldq_uop_2_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_19_mem_signed = ldq_uop_2_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_uses_ldq; // @[lsu.scala:219:36] wire l_uop_2_uses_ldq = ldq_uop_2_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_19_uses_ldq = ldq_uop_2_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_uses_stq; // @[lsu.scala:219:36] wire l_uop_2_uses_stq = ldq_uop_2_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_19_uses_stq = ldq_uop_2_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_unique; // @[lsu.scala:219:36] wire l_uop_2_is_unique = ldq_uop_2_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_19_is_unique = ldq_uop_2_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_2_flush_on_commit = ldq_uop_2_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_19_flush_on_commit = ldq_uop_2_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_2_csr_cmd = ldq_uop_2_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_19_csr_cmd = ldq_uop_2_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_2_ldst_is_rs1 = ldq_uop_2_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_19_ldst_is_rs1 = ldq_uop_2_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_2_ldst = ldq_uop_2_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_19_ldst = ldq_uop_2_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_2_lrs1 = ldq_uop_2_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_19_lrs1 = ldq_uop_2_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_2_lrs2 = ldq_uop_2_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_19_lrs2 = ldq_uop_2_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_2_lrs3 = ldq_uop_2_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_19_lrs3 = ldq_uop_2_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_2_dst_rtype = ldq_uop_2_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_dst_rtype = ldq_uop_2_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_2_lrs1_rtype = ldq_uop_2_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_lrs1_rtype = ldq_uop_2_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_2_lrs2_rtype = ldq_uop_2_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_lrs2_rtype = ldq_uop_2_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_frs3_en; // @[lsu.scala:219:36] wire l_uop_2_frs3_en = ldq_uop_2_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_19_frs3_en = ldq_uop_2_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fcn_dw; // @[lsu.scala:219:36] wire l_uop_2_fcn_dw = ldq_uop_2_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_19_fcn_dw = ldq_uop_2_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_2_fcn_op = ldq_uop_2_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_19_fcn_op = ldq_uop_2_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_val; // @[lsu.scala:219:36] wire l_uop_2_fp_val = ldq_uop_2_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_19_fp_val = ldq_uop_2_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_2_fp_rm = ldq_uop_2_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_19_fp_rm = ldq_uop_2_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_2_fp_typ = ldq_uop_2_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_19_fp_typ = ldq_uop_2_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_2_xcpt_pf_if = ldq_uop_2_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_19_xcpt_pf_if = ldq_uop_2_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_2_xcpt_ae_if = ldq_uop_2_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_19_xcpt_ae_if = ldq_uop_2_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_2_xcpt_ma_if = ldq_uop_2_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_19_xcpt_ma_if = ldq_uop_2_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_2_bp_debug_if = ldq_uop_2_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_19_bp_debug_if = ldq_uop_2_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_2_bp_xcpt_if = ldq_uop_2_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_19_bp_xcpt_if = ldq_uop_2_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_2_debug_fsrc = ldq_uop_2_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_19_debug_fsrc = ldq_uop_2_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_2_debug_tsrc = ldq_uop_2_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_19_debug_tsrc = ldq_uop_2_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_3_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_3_inst = ldq_uop_3_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_20_inst = ldq_uop_3_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_3_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_3_debug_inst = ldq_uop_3_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_20_debug_inst = ldq_uop_3_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_rvc; // @[lsu.scala:219:36] wire l_uop_3_is_rvc = ldq_uop_3_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_rvc = ldq_uop_3_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_3_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_3_debug_pc = ldq_uop_3_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_20_debug_pc = ldq_uop_3_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_0; // @[lsu.scala:219:36] wire l_uop_3_iq_type_0 = ldq_uop_3_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_20_iq_type_0 = ldq_uop_3_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_1; // @[lsu.scala:219:36] wire l_uop_3_iq_type_1 = ldq_uop_3_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_20_iq_type_1 = ldq_uop_3_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_2; // @[lsu.scala:219:36] wire l_uop_3_iq_type_2 = ldq_uop_3_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_20_iq_type_2 = ldq_uop_3_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_3; // @[lsu.scala:219:36] wire l_uop_3_iq_type_3 = ldq_uop_3_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_20_iq_type_3 = ldq_uop_3_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_0; // @[lsu.scala:219:36] wire l_uop_3_fu_code_0 = ldq_uop_3_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_0 = ldq_uop_3_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_1; // @[lsu.scala:219:36] wire l_uop_3_fu_code_1 = ldq_uop_3_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_1 = ldq_uop_3_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_2; // @[lsu.scala:219:36] wire l_uop_3_fu_code_2 = ldq_uop_3_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_2 = ldq_uop_3_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_3; // @[lsu.scala:219:36] wire l_uop_3_fu_code_3 = ldq_uop_3_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_3 = ldq_uop_3_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_4; // @[lsu.scala:219:36] wire l_uop_3_fu_code_4 = ldq_uop_3_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_4 = ldq_uop_3_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_5; // @[lsu.scala:219:36] wire l_uop_3_fu_code_5 = ldq_uop_3_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_5 = ldq_uop_3_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_6; // @[lsu.scala:219:36] wire l_uop_3_fu_code_6 = ldq_uop_3_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_6 = ldq_uop_3_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_7; // @[lsu.scala:219:36] wire l_uop_3_fu_code_7 = ldq_uop_3_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_7 = ldq_uop_3_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_8; // @[lsu.scala:219:36] wire l_uop_3_fu_code_8 = ldq_uop_3_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_8 = ldq_uop_3_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_9; // @[lsu.scala:219:36] wire l_uop_3_fu_code_9 = ldq_uop_3_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_20_fu_code_9 = ldq_uop_3_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_issued; // @[lsu.scala:219:36] wire l_uop_3_iw_issued = ldq_uop_3_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_20_iw_issued = ldq_uop_3_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_3_iw_issued_partial_agen = ldq_uop_3_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_20_iw_issued_partial_agen = ldq_uop_3_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_3_iw_issued_partial_dgen = ldq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_20_iw_issued_partial_dgen = ldq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_3_iw_p1_speculative_child = ldq_uop_3_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_iw_p1_speculative_child = ldq_uop_3_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_3_iw_p2_speculative_child = ldq_uop_3_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_iw_p2_speculative_child = ldq_uop_3_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_3_iw_p1_bypass_hint = ldq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_20_iw_p1_bypass_hint = ldq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_3_iw_p2_bypass_hint = ldq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_20_iw_p2_bypass_hint = ldq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_3_iw_p3_bypass_hint = ldq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_20_iw_p3_bypass_hint = ldq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_3_dis_col_sel = ldq_uop_3_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_dis_col_sel = ldq_uop_3_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_3_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_3_br_mask = ldq_uop_3_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_20_br_mask = ldq_uop_3_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_3_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_3_br_tag = ldq_uop_3_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_20_br_tag = ldq_uop_3_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_3_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_3_br_type = ldq_uop_3_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_20_br_type = ldq_uop_3_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_sfb; // @[lsu.scala:219:36] wire l_uop_3_is_sfb = ldq_uop_3_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_sfb = ldq_uop_3_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_fence; // @[lsu.scala:219:36] wire l_uop_3_is_fence = ldq_uop_3_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_fence = ldq_uop_3_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_fencei; // @[lsu.scala:219:36] wire l_uop_3_is_fencei = ldq_uop_3_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_fencei = ldq_uop_3_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_sfence; // @[lsu.scala:219:36] wire l_uop_3_is_sfence = ldq_uop_3_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_sfence = ldq_uop_3_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_amo; // @[lsu.scala:219:36] wire l_uop_3_is_amo = ldq_uop_3_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_amo = ldq_uop_3_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_eret; // @[lsu.scala:219:36] wire l_uop_3_is_eret = ldq_uop_3_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_eret = ldq_uop_3_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_3_is_sys_pc2epc = ldq_uop_3_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_sys_pc2epc = ldq_uop_3_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_rocc; // @[lsu.scala:219:36] wire l_uop_3_is_rocc = ldq_uop_3_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_rocc = ldq_uop_3_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_mov; // @[lsu.scala:219:36] wire l_uop_3_is_mov = ldq_uop_3_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_mov = ldq_uop_3_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_3_ftq_idx = ldq_uop_3_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_20_ftq_idx = ldq_uop_3_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_edge_inst; // @[lsu.scala:219:36] wire l_uop_3_edge_inst = ldq_uop_3_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_20_edge_inst = ldq_uop_3_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_3_pc_lob = ldq_uop_3_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_20_pc_lob = ldq_uop_3_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_taken; // @[lsu.scala:219:36] wire l_uop_3_taken = ldq_uop_3_taken; // @[lsu.scala:219:36, :1191:37] wire uop_20_taken = ldq_uop_3_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_imm_rename; // @[lsu.scala:219:36] wire l_uop_3_imm_rename = ldq_uop_3_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_20_imm_rename = ldq_uop_3_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_3_imm_sel = ldq_uop_3_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_20_imm_sel = ldq_uop_3_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_3_pimm = ldq_uop_3_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_20_pimm = ldq_uop_3_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_3_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_3_imm_packed = ldq_uop_3_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_20_imm_packed = ldq_uop_3_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_3_op1_sel = ldq_uop_3_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_op1_sel = ldq_uop_3_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_3_op2_sel = ldq_uop_3_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_20_op2_sel = ldq_uop_3_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ldst = ldq_uop_3_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_ldst = ldq_uop_3_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_wen = ldq_uop_3_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_wen = ldq_uop_3_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ren1 = ldq_uop_3_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_ren1 = ldq_uop_3_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ren2 = ldq_uop_3_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_ren2 = ldq_uop_3_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ren3 = ldq_uop_3_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_ren3 = ldq_uop_3_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_swap12 = ldq_uop_3_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_swap12 = ldq_uop_3_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_swap23 = ldq_uop_3_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_swap23 = ldq_uop_3_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_3_fp_ctrl_typeTagIn = ldq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_fp_ctrl_typeTagIn = ldq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_3_fp_ctrl_typeTagOut = ldq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_fp_ctrl_typeTagOut = ldq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_fromint = ldq_uop_3_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_fromint = ldq_uop_3_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_toint = ldq_uop_3_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_toint = ldq_uop_3_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_fastpipe = ldq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_fastpipe = ldq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_fma = ldq_uop_3_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_fma = ldq_uop_3_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_div = ldq_uop_3_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_div = ldq_uop_3_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_sqrt = ldq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_sqrt = ldq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_wflags = ldq_uop_3_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_wflags = ldq_uop_3_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_vec = ldq_uop_3_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_ctrl_vec = ldq_uop_3_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_3_rob_idx = ldq_uop_3_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_20_rob_idx = ldq_uop_3_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_3_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_3_ldq_idx = ldq_uop_3_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_20_ldq_idx = ldq_uop_3_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_3_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_3_stq_idx = ldq_uop_3_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_20_stq_idx = ldq_uop_3_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_3_rxq_idx = ldq_uop_3_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_rxq_idx = ldq_uop_3_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_3_pdst = ldq_uop_3_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_20_pdst = ldq_uop_3_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_3_prs1 = ldq_uop_3_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_20_prs1 = ldq_uop_3_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_3_prs2 = ldq_uop_3_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_20_prs2 = ldq_uop_3_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_3_prs3 = ldq_uop_3_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_20_prs3 = ldq_uop_3_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_3_ppred = ldq_uop_3_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_20_ppred = ldq_uop_3_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_prs1_busy; // @[lsu.scala:219:36] wire l_uop_3_prs1_busy = ldq_uop_3_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_20_prs1_busy = ldq_uop_3_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_prs2_busy; // @[lsu.scala:219:36] wire l_uop_3_prs2_busy = ldq_uop_3_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_20_prs2_busy = ldq_uop_3_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_prs3_busy; // @[lsu.scala:219:36] wire l_uop_3_prs3_busy = ldq_uop_3_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_20_prs3_busy = ldq_uop_3_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_ppred_busy; // @[lsu.scala:219:36] wire l_uop_3_ppred_busy = ldq_uop_3_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_20_ppred_busy = ldq_uop_3_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_3_stale_pdst = ldq_uop_3_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_20_stale_pdst = ldq_uop_3_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_exception; // @[lsu.scala:219:36] wire l_uop_3_exception = ldq_uop_3_exception; // @[lsu.scala:219:36, :1191:37] wire uop_20_exception = ldq_uop_3_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_3_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_3_exc_cause = ldq_uop_3_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_20_exc_cause = ldq_uop_3_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_3_mem_cmd = ldq_uop_3_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_20_mem_cmd = ldq_uop_3_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_3_mem_size = ldq_uop_3_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_mem_size = ldq_uop_3_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_mem_signed; // @[lsu.scala:219:36] wire l_uop_3_mem_signed = ldq_uop_3_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_20_mem_signed = ldq_uop_3_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_uses_ldq; // @[lsu.scala:219:36] wire l_uop_3_uses_ldq = ldq_uop_3_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_20_uses_ldq = ldq_uop_3_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_uses_stq; // @[lsu.scala:219:36] wire l_uop_3_uses_stq = ldq_uop_3_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_20_uses_stq = ldq_uop_3_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_unique; // @[lsu.scala:219:36] wire l_uop_3_is_unique = ldq_uop_3_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_20_is_unique = ldq_uop_3_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_3_flush_on_commit = ldq_uop_3_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_20_flush_on_commit = ldq_uop_3_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_3_csr_cmd = ldq_uop_3_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_20_csr_cmd = ldq_uop_3_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_3_ldst_is_rs1 = ldq_uop_3_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_20_ldst_is_rs1 = ldq_uop_3_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_3_ldst = ldq_uop_3_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_20_ldst = ldq_uop_3_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_3_lrs1 = ldq_uop_3_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_20_lrs1 = ldq_uop_3_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_3_lrs2 = ldq_uop_3_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_20_lrs2 = ldq_uop_3_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_3_lrs3 = ldq_uop_3_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_20_lrs3 = ldq_uop_3_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_3_dst_rtype = ldq_uop_3_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_dst_rtype = ldq_uop_3_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_3_lrs1_rtype = ldq_uop_3_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_lrs1_rtype = ldq_uop_3_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_3_lrs2_rtype = ldq_uop_3_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_lrs2_rtype = ldq_uop_3_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_frs3_en; // @[lsu.scala:219:36] wire l_uop_3_frs3_en = ldq_uop_3_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_20_frs3_en = ldq_uop_3_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fcn_dw; // @[lsu.scala:219:36] wire l_uop_3_fcn_dw = ldq_uop_3_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_20_fcn_dw = ldq_uop_3_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_3_fcn_op = ldq_uop_3_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_20_fcn_op = ldq_uop_3_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_val; // @[lsu.scala:219:36] wire l_uop_3_fp_val = ldq_uop_3_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_20_fp_val = ldq_uop_3_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_3_fp_rm = ldq_uop_3_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_20_fp_rm = ldq_uop_3_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_3_fp_typ = ldq_uop_3_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_20_fp_typ = ldq_uop_3_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_3_xcpt_pf_if = ldq_uop_3_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_20_xcpt_pf_if = ldq_uop_3_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_3_xcpt_ae_if = ldq_uop_3_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_20_xcpt_ae_if = ldq_uop_3_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_3_xcpt_ma_if = ldq_uop_3_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_20_xcpt_ma_if = ldq_uop_3_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_3_bp_debug_if = ldq_uop_3_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_20_bp_debug_if = ldq_uop_3_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_3_bp_xcpt_if = ldq_uop_3_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_20_bp_xcpt_if = ldq_uop_3_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_3_debug_fsrc = ldq_uop_3_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_20_debug_fsrc = ldq_uop_3_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_3_debug_tsrc = ldq_uop_3_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_20_debug_tsrc = ldq_uop_3_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_4_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_4_inst = ldq_uop_4_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_21_inst = ldq_uop_4_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_4_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_4_debug_inst = ldq_uop_4_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_21_debug_inst = ldq_uop_4_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_rvc; // @[lsu.scala:219:36] wire l_uop_4_is_rvc = ldq_uop_4_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_rvc = ldq_uop_4_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_4_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_4_debug_pc = ldq_uop_4_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_21_debug_pc = ldq_uop_4_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_0; // @[lsu.scala:219:36] wire l_uop_4_iq_type_0 = ldq_uop_4_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_21_iq_type_0 = ldq_uop_4_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_1; // @[lsu.scala:219:36] wire l_uop_4_iq_type_1 = ldq_uop_4_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_21_iq_type_1 = ldq_uop_4_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_2; // @[lsu.scala:219:36] wire l_uop_4_iq_type_2 = ldq_uop_4_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_21_iq_type_2 = ldq_uop_4_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_3; // @[lsu.scala:219:36] wire l_uop_4_iq_type_3 = ldq_uop_4_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_21_iq_type_3 = ldq_uop_4_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_0; // @[lsu.scala:219:36] wire l_uop_4_fu_code_0 = ldq_uop_4_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_0 = ldq_uop_4_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_1; // @[lsu.scala:219:36] wire l_uop_4_fu_code_1 = ldq_uop_4_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_1 = ldq_uop_4_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_2; // @[lsu.scala:219:36] wire l_uop_4_fu_code_2 = ldq_uop_4_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_2 = ldq_uop_4_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_3; // @[lsu.scala:219:36] wire l_uop_4_fu_code_3 = ldq_uop_4_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_3 = ldq_uop_4_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_4; // @[lsu.scala:219:36] wire l_uop_4_fu_code_4 = ldq_uop_4_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_4 = ldq_uop_4_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_5; // @[lsu.scala:219:36] wire l_uop_4_fu_code_5 = ldq_uop_4_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_5 = ldq_uop_4_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_6; // @[lsu.scala:219:36] wire l_uop_4_fu_code_6 = ldq_uop_4_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_6 = ldq_uop_4_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_7; // @[lsu.scala:219:36] wire l_uop_4_fu_code_7 = ldq_uop_4_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_7 = ldq_uop_4_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_8; // @[lsu.scala:219:36] wire l_uop_4_fu_code_8 = ldq_uop_4_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_8 = ldq_uop_4_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_9; // @[lsu.scala:219:36] wire l_uop_4_fu_code_9 = ldq_uop_4_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_21_fu_code_9 = ldq_uop_4_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_issued; // @[lsu.scala:219:36] wire l_uop_4_iw_issued = ldq_uop_4_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_21_iw_issued = ldq_uop_4_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_4_iw_issued_partial_agen = ldq_uop_4_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_21_iw_issued_partial_agen = ldq_uop_4_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_4_iw_issued_partial_dgen = ldq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_21_iw_issued_partial_dgen = ldq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_4_iw_p1_speculative_child = ldq_uop_4_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_iw_p1_speculative_child = ldq_uop_4_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_4_iw_p2_speculative_child = ldq_uop_4_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_iw_p2_speculative_child = ldq_uop_4_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_4_iw_p1_bypass_hint = ldq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_21_iw_p1_bypass_hint = ldq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_4_iw_p2_bypass_hint = ldq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_21_iw_p2_bypass_hint = ldq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_4_iw_p3_bypass_hint = ldq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_21_iw_p3_bypass_hint = ldq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_4_dis_col_sel = ldq_uop_4_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_dis_col_sel = ldq_uop_4_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_4_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_4_br_mask = ldq_uop_4_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_21_br_mask = ldq_uop_4_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_4_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_4_br_tag = ldq_uop_4_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_21_br_tag = ldq_uop_4_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_4_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_4_br_type = ldq_uop_4_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_21_br_type = ldq_uop_4_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_sfb; // @[lsu.scala:219:36] wire l_uop_4_is_sfb = ldq_uop_4_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_sfb = ldq_uop_4_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_fence; // @[lsu.scala:219:36] wire l_uop_4_is_fence = ldq_uop_4_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_fence = ldq_uop_4_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_fencei; // @[lsu.scala:219:36] wire l_uop_4_is_fencei = ldq_uop_4_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_fencei = ldq_uop_4_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_sfence; // @[lsu.scala:219:36] wire l_uop_4_is_sfence = ldq_uop_4_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_sfence = ldq_uop_4_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_amo; // @[lsu.scala:219:36] wire l_uop_4_is_amo = ldq_uop_4_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_amo = ldq_uop_4_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_eret; // @[lsu.scala:219:36] wire l_uop_4_is_eret = ldq_uop_4_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_eret = ldq_uop_4_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_4_is_sys_pc2epc = ldq_uop_4_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_sys_pc2epc = ldq_uop_4_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_rocc; // @[lsu.scala:219:36] wire l_uop_4_is_rocc = ldq_uop_4_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_rocc = ldq_uop_4_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_mov; // @[lsu.scala:219:36] wire l_uop_4_is_mov = ldq_uop_4_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_mov = ldq_uop_4_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_4_ftq_idx = ldq_uop_4_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_21_ftq_idx = ldq_uop_4_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_edge_inst; // @[lsu.scala:219:36] wire l_uop_4_edge_inst = ldq_uop_4_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_21_edge_inst = ldq_uop_4_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_4_pc_lob = ldq_uop_4_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_21_pc_lob = ldq_uop_4_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_taken; // @[lsu.scala:219:36] wire l_uop_4_taken = ldq_uop_4_taken; // @[lsu.scala:219:36, :1191:37] wire uop_21_taken = ldq_uop_4_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_imm_rename; // @[lsu.scala:219:36] wire l_uop_4_imm_rename = ldq_uop_4_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_21_imm_rename = ldq_uop_4_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_4_imm_sel = ldq_uop_4_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_21_imm_sel = ldq_uop_4_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_4_pimm = ldq_uop_4_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_21_pimm = ldq_uop_4_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_4_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_4_imm_packed = ldq_uop_4_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_21_imm_packed = ldq_uop_4_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_4_op1_sel = ldq_uop_4_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_op1_sel = ldq_uop_4_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_4_op2_sel = ldq_uop_4_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_21_op2_sel = ldq_uop_4_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ldst = ldq_uop_4_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_ldst = ldq_uop_4_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_wen = ldq_uop_4_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_wen = ldq_uop_4_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ren1 = ldq_uop_4_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_ren1 = ldq_uop_4_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ren2 = ldq_uop_4_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_ren2 = ldq_uop_4_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ren3 = ldq_uop_4_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_ren3 = ldq_uop_4_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_swap12 = ldq_uop_4_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_swap12 = ldq_uop_4_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_swap23 = ldq_uop_4_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_swap23 = ldq_uop_4_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_4_fp_ctrl_typeTagIn = ldq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_fp_ctrl_typeTagIn = ldq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_4_fp_ctrl_typeTagOut = ldq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_fp_ctrl_typeTagOut = ldq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_fromint = ldq_uop_4_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_fromint = ldq_uop_4_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_toint = ldq_uop_4_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_toint = ldq_uop_4_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_fastpipe = ldq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_fastpipe = ldq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_fma = ldq_uop_4_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_fma = ldq_uop_4_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_div = ldq_uop_4_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_div = ldq_uop_4_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_sqrt = ldq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_sqrt = ldq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_wflags = ldq_uop_4_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_wflags = ldq_uop_4_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_vec = ldq_uop_4_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_ctrl_vec = ldq_uop_4_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_4_rob_idx = ldq_uop_4_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_21_rob_idx = ldq_uop_4_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_4_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_4_ldq_idx = ldq_uop_4_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_21_ldq_idx = ldq_uop_4_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_4_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_4_stq_idx = ldq_uop_4_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_21_stq_idx = ldq_uop_4_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_4_rxq_idx = ldq_uop_4_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_rxq_idx = ldq_uop_4_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_4_pdst = ldq_uop_4_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_21_pdst = ldq_uop_4_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_4_prs1 = ldq_uop_4_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_21_prs1 = ldq_uop_4_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_4_prs2 = ldq_uop_4_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_21_prs2 = ldq_uop_4_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_4_prs3 = ldq_uop_4_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_21_prs3 = ldq_uop_4_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_4_ppred = ldq_uop_4_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_21_ppred = ldq_uop_4_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_prs1_busy; // @[lsu.scala:219:36] wire l_uop_4_prs1_busy = ldq_uop_4_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_21_prs1_busy = ldq_uop_4_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_prs2_busy; // @[lsu.scala:219:36] wire l_uop_4_prs2_busy = ldq_uop_4_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_21_prs2_busy = ldq_uop_4_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_prs3_busy; // @[lsu.scala:219:36] wire l_uop_4_prs3_busy = ldq_uop_4_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_21_prs3_busy = ldq_uop_4_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_ppred_busy; // @[lsu.scala:219:36] wire l_uop_4_ppred_busy = ldq_uop_4_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_21_ppred_busy = ldq_uop_4_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_4_stale_pdst = ldq_uop_4_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_21_stale_pdst = ldq_uop_4_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_exception; // @[lsu.scala:219:36] wire l_uop_4_exception = ldq_uop_4_exception; // @[lsu.scala:219:36, :1191:37] wire uop_21_exception = ldq_uop_4_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_4_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_4_exc_cause = ldq_uop_4_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_21_exc_cause = ldq_uop_4_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_4_mem_cmd = ldq_uop_4_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_21_mem_cmd = ldq_uop_4_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_4_mem_size = ldq_uop_4_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_mem_size = ldq_uop_4_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_mem_signed; // @[lsu.scala:219:36] wire l_uop_4_mem_signed = ldq_uop_4_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_21_mem_signed = ldq_uop_4_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_uses_ldq; // @[lsu.scala:219:36] wire l_uop_4_uses_ldq = ldq_uop_4_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_21_uses_ldq = ldq_uop_4_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_uses_stq; // @[lsu.scala:219:36] wire l_uop_4_uses_stq = ldq_uop_4_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_21_uses_stq = ldq_uop_4_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_unique; // @[lsu.scala:219:36] wire l_uop_4_is_unique = ldq_uop_4_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_21_is_unique = ldq_uop_4_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_4_flush_on_commit = ldq_uop_4_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_21_flush_on_commit = ldq_uop_4_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_4_csr_cmd = ldq_uop_4_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_21_csr_cmd = ldq_uop_4_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_4_ldst_is_rs1 = ldq_uop_4_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_21_ldst_is_rs1 = ldq_uop_4_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_4_ldst = ldq_uop_4_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_21_ldst = ldq_uop_4_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_4_lrs1 = ldq_uop_4_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_21_lrs1 = ldq_uop_4_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_4_lrs2 = ldq_uop_4_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_21_lrs2 = ldq_uop_4_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_4_lrs3 = ldq_uop_4_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_21_lrs3 = ldq_uop_4_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_4_dst_rtype = ldq_uop_4_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_dst_rtype = ldq_uop_4_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_4_lrs1_rtype = ldq_uop_4_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_lrs1_rtype = ldq_uop_4_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_4_lrs2_rtype = ldq_uop_4_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_lrs2_rtype = ldq_uop_4_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_frs3_en; // @[lsu.scala:219:36] wire l_uop_4_frs3_en = ldq_uop_4_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_21_frs3_en = ldq_uop_4_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fcn_dw; // @[lsu.scala:219:36] wire l_uop_4_fcn_dw = ldq_uop_4_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_21_fcn_dw = ldq_uop_4_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_4_fcn_op = ldq_uop_4_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_21_fcn_op = ldq_uop_4_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_val; // @[lsu.scala:219:36] wire l_uop_4_fp_val = ldq_uop_4_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_21_fp_val = ldq_uop_4_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_4_fp_rm = ldq_uop_4_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_21_fp_rm = ldq_uop_4_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_4_fp_typ = ldq_uop_4_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_21_fp_typ = ldq_uop_4_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_4_xcpt_pf_if = ldq_uop_4_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_21_xcpt_pf_if = ldq_uop_4_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_4_xcpt_ae_if = ldq_uop_4_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_21_xcpt_ae_if = ldq_uop_4_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_4_xcpt_ma_if = ldq_uop_4_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_21_xcpt_ma_if = ldq_uop_4_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_4_bp_debug_if = ldq_uop_4_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_21_bp_debug_if = ldq_uop_4_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_4_bp_xcpt_if = ldq_uop_4_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_21_bp_xcpt_if = ldq_uop_4_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_4_debug_fsrc = ldq_uop_4_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_21_debug_fsrc = ldq_uop_4_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_4_debug_tsrc = ldq_uop_4_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_21_debug_tsrc = ldq_uop_4_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_5_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_5_inst = ldq_uop_5_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_22_inst = ldq_uop_5_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_5_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_5_debug_inst = ldq_uop_5_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_22_debug_inst = ldq_uop_5_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_rvc; // @[lsu.scala:219:36] wire l_uop_5_is_rvc = ldq_uop_5_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_rvc = ldq_uop_5_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_5_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_5_debug_pc = ldq_uop_5_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_22_debug_pc = ldq_uop_5_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_0; // @[lsu.scala:219:36] wire l_uop_5_iq_type_0 = ldq_uop_5_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_22_iq_type_0 = ldq_uop_5_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_1; // @[lsu.scala:219:36] wire l_uop_5_iq_type_1 = ldq_uop_5_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_22_iq_type_1 = ldq_uop_5_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_2; // @[lsu.scala:219:36] wire l_uop_5_iq_type_2 = ldq_uop_5_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_22_iq_type_2 = ldq_uop_5_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_3; // @[lsu.scala:219:36] wire l_uop_5_iq_type_3 = ldq_uop_5_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_22_iq_type_3 = ldq_uop_5_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_0; // @[lsu.scala:219:36] wire l_uop_5_fu_code_0 = ldq_uop_5_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_0 = ldq_uop_5_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_1; // @[lsu.scala:219:36] wire l_uop_5_fu_code_1 = ldq_uop_5_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_1 = ldq_uop_5_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_2; // @[lsu.scala:219:36] wire l_uop_5_fu_code_2 = ldq_uop_5_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_2 = ldq_uop_5_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_3; // @[lsu.scala:219:36] wire l_uop_5_fu_code_3 = ldq_uop_5_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_3 = ldq_uop_5_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_4; // @[lsu.scala:219:36] wire l_uop_5_fu_code_4 = ldq_uop_5_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_4 = ldq_uop_5_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_5; // @[lsu.scala:219:36] wire l_uop_5_fu_code_5 = ldq_uop_5_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_5 = ldq_uop_5_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_6; // @[lsu.scala:219:36] wire l_uop_5_fu_code_6 = ldq_uop_5_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_6 = ldq_uop_5_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_7; // @[lsu.scala:219:36] wire l_uop_5_fu_code_7 = ldq_uop_5_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_7 = ldq_uop_5_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_8; // @[lsu.scala:219:36] wire l_uop_5_fu_code_8 = ldq_uop_5_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_8 = ldq_uop_5_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_9; // @[lsu.scala:219:36] wire l_uop_5_fu_code_9 = ldq_uop_5_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_22_fu_code_9 = ldq_uop_5_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_issued; // @[lsu.scala:219:36] wire l_uop_5_iw_issued = ldq_uop_5_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_22_iw_issued = ldq_uop_5_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_5_iw_issued_partial_agen = ldq_uop_5_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_22_iw_issued_partial_agen = ldq_uop_5_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_5_iw_issued_partial_dgen = ldq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_22_iw_issued_partial_dgen = ldq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_5_iw_p1_speculative_child = ldq_uop_5_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_iw_p1_speculative_child = ldq_uop_5_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_5_iw_p2_speculative_child = ldq_uop_5_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_iw_p2_speculative_child = ldq_uop_5_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_5_iw_p1_bypass_hint = ldq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_22_iw_p1_bypass_hint = ldq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_5_iw_p2_bypass_hint = ldq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_22_iw_p2_bypass_hint = ldq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_5_iw_p3_bypass_hint = ldq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_22_iw_p3_bypass_hint = ldq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_5_dis_col_sel = ldq_uop_5_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_dis_col_sel = ldq_uop_5_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_5_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_5_br_mask = ldq_uop_5_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_22_br_mask = ldq_uop_5_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_5_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_5_br_tag = ldq_uop_5_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_22_br_tag = ldq_uop_5_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_5_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_5_br_type = ldq_uop_5_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_22_br_type = ldq_uop_5_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_sfb; // @[lsu.scala:219:36] wire l_uop_5_is_sfb = ldq_uop_5_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_sfb = ldq_uop_5_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_fence; // @[lsu.scala:219:36] wire l_uop_5_is_fence = ldq_uop_5_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_fence = ldq_uop_5_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_fencei; // @[lsu.scala:219:36] wire l_uop_5_is_fencei = ldq_uop_5_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_fencei = ldq_uop_5_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_sfence; // @[lsu.scala:219:36] wire l_uop_5_is_sfence = ldq_uop_5_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_sfence = ldq_uop_5_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_amo; // @[lsu.scala:219:36] wire l_uop_5_is_amo = ldq_uop_5_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_amo = ldq_uop_5_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_eret; // @[lsu.scala:219:36] wire l_uop_5_is_eret = ldq_uop_5_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_eret = ldq_uop_5_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_5_is_sys_pc2epc = ldq_uop_5_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_sys_pc2epc = ldq_uop_5_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_rocc; // @[lsu.scala:219:36] wire l_uop_5_is_rocc = ldq_uop_5_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_rocc = ldq_uop_5_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_mov; // @[lsu.scala:219:36] wire l_uop_5_is_mov = ldq_uop_5_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_mov = ldq_uop_5_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_5_ftq_idx = ldq_uop_5_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_22_ftq_idx = ldq_uop_5_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_edge_inst; // @[lsu.scala:219:36] wire l_uop_5_edge_inst = ldq_uop_5_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_22_edge_inst = ldq_uop_5_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_5_pc_lob = ldq_uop_5_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_22_pc_lob = ldq_uop_5_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_taken; // @[lsu.scala:219:36] wire l_uop_5_taken = ldq_uop_5_taken; // @[lsu.scala:219:36, :1191:37] wire uop_22_taken = ldq_uop_5_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_imm_rename; // @[lsu.scala:219:36] wire l_uop_5_imm_rename = ldq_uop_5_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_22_imm_rename = ldq_uop_5_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_5_imm_sel = ldq_uop_5_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_22_imm_sel = ldq_uop_5_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_5_pimm = ldq_uop_5_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_22_pimm = ldq_uop_5_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_5_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_5_imm_packed = ldq_uop_5_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_22_imm_packed = ldq_uop_5_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_5_op1_sel = ldq_uop_5_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_op1_sel = ldq_uop_5_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_5_op2_sel = ldq_uop_5_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_22_op2_sel = ldq_uop_5_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ldst = ldq_uop_5_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_ldst = ldq_uop_5_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_wen = ldq_uop_5_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_wen = ldq_uop_5_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ren1 = ldq_uop_5_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_ren1 = ldq_uop_5_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ren2 = ldq_uop_5_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_ren2 = ldq_uop_5_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ren3 = ldq_uop_5_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_ren3 = ldq_uop_5_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_swap12 = ldq_uop_5_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_swap12 = ldq_uop_5_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_swap23 = ldq_uop_5_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_swap23 = ldq_uop_5_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_5_fp_ctrl_typeTagIn = ldq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_fp_ctrl_typeTagIn = ldq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_5_fp_ctrl_typeTagOut = ldq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_fp_ctrl_typeTagOut = ldq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_fromint = ldq_uop_5_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_fromint = ldq_uop_5_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_toint = ldq_uop_5_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_toint = ldq_uop_5_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_fastpipe = ldq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_fastpipe = ldq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_fma = ldq_uop_5_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_fma = ldq_uop_5_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_div = ldq_uop_5_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_div = ldq_uop_5_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_sqrt = ldq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_sqrt = ldq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_wflags = ldq_uop_5_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_wflags = ldq_uop_5_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_vec = ldq_uop_5_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_ctrl_vec = ldq_uop_5_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_5_rob_idx = ldq_uop_5_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_22_rob_idx = ldq_uop_5_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_5_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_5_ldq_idx = ldq_uop_5_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_22_ldq_idx = ldq_uop_5_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_5_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_5_stq_idx = ldq_uop_5_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_22_stq_idx = ldq_uop_5_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_5_rxq_idx = ldq_uop_5_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_rxq_idx = ldq_uop_5_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_5_pdst = ldq_uop_5_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_22_pdst = ldq_uop_5_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_5_prs1 = ldq_uop_5_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_22_prs1 = ldq_uop_5_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_5_prs2 = ldq_uop_5_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_22_prs2 = ldq_uop_5_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_5_prs3 = ldq_uop_5_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_22_prs3 = ldq_uop_5_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_5_ppred = ldq_uop_5_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_22_ppred = ldq_uop_5_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_prs1_busy; // @[lsu.scala:219:36] wire l_uop_5_prs1_busy = ldq_uop_5_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_22_prs1_busy = ldq_uop_5_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_prs2_busy; // @[lsu.scala:219:36] wire l_uop_5_prs2_busy = ldq_uop_5_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_22_prs2_busy = ldq_uop_5_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_prs3_busy; // @[lsu.scala:219:36] wire l_uop_5_prs3_busy = ldq_uop_5_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_22_prs3_busy = ldq_uop_5_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_ppred_busy; // @[lsu.scala:219:36] wire l_uop_5_ppred_busy = ldq_uop_5_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_22_ppred_busy = ldq_uop_5_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_5_stale_pdst = ldq_uop_5_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_22_stale_pdst = ldq_uop_5_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_exception; // @[lsu.scala:219:36] wire l_uop_5_exception = ldq_uop_5_exception; // @[lsu.scala:219:36, :1191:37] wire uop_22_exception = ldq_uop_5_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_5_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_5_exc_cause = ldq_uop_5_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_22_exc_cause = ldq_uop_5_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_5_mem_cmd = ldq_uop_5_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_22_mem_cmd = ldq_uop_5_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_5_mem_size = ldq_uop_5_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_mem_size = ldq_uop_5_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_mem_signed; // @[lsu.scala:219:36] wire l_uop_5_mem_signed = ldq_uop_5_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_22_mem_signed = ldq_uop_5_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_uses_ldq; // @[lsu.scala:219:36] wire l_uop_5_uses_ldq = ldq_uop_5_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_22_uses_ldq = ldq_uop_5_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_uses_stq; // @[lsu.scala:219:36] wire l_uop_5_uses_stq = ldq_uop_5_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_22_uses_stq = ldq_uop_5_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_unique; // @[lsu.scala:219:36] wire l_uop_5_is_unique = ldq_uop_5_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_22_is_unique = ldq_uop_5_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_5_flush_on_commit = ldq_uop_5_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_22_flush_on_commit = ldq_uop_5_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_5_csr_cmd = ldq_uop_5_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_22_csr_cmd = ldq_uop_5_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_5_ldst_is_rs1 = ldq_uop_5_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_22_ldst_is_rs1 = ldq_uop_5_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_5_ldst = ldq_uop_5_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_22_ldst = ldq_uop_5_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_5_lrs1 = ldq_uop_5_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_22_lrs1 = ldq_uop_5_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_5_lrs2 = ldq_uop_5_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_22_lrs2 = ldq_uop_5_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_5_lrs3 = ldq_uop_5_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_22_lrs3 = ldq_uop_5_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_5_dst_rtype = ldq_uop_5_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_dst_rtype = ldq_uop_5_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_5_lrs1_rtype = ldq_uop_5_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_lrs1_rtype = ldq_uop_5_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_5_lrs2_rtype = ldq_uop_5_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_lrs2_rtype = ldq_uop_5_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_frs3_en; // @[lsu.scala:219:36] wire l_uop_5_frs3_en = ldq_uop_5_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_22_frs3_en = ldq_uop_5_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fcn_dw; // @[lsu.scala:219:36] wire l_uop_5_fcn_dw = ldq_uop_5_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_22_fcn_dw = ldq_uop_5_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_5_fcn_op = ldq_uop_5_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_22_fcn_op = ldq_uop_5_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_val; // @[lsu.scala:219:36] wire l_uop_5_fp_val = ldq_uop_5_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_22_fp_val = ldq_uop_5_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_5_fp_rm = ldq_uop_5_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_22_fp_rm = ldq_uop_5_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_5_fp_typ = ldq_uop_5_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_22_fp_typ = ldq_uop_5_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_5_xcpt_pf_if = ldq_uop_5_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_22_xcpt_pf_if = ldq_uop_5_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_5_xcpt_ae_if = ldq_uop_5_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_22_xcpt_ae_if = ldq_uop_5_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_5_xcpt_ma_if = ldq_uop_5_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_22_xcpt_ma_if = ldq_uop_5_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_5_bp_debug_if = ldq_uop_5_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_22_bp_debug_if = ldq_uop_5_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_5_bp_xcpt_if = ldq_uop_5_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_22_bp_xcpt_if = ldq_uop_5_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_5_debug_fsrc = ldq_uop_5_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_22_debug_fsrc = ldq_uop_5_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_5_debug_tsrc = ldq_uop_5_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_22_debug_tsrc = ldq_uop_5_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_6_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_6_inst = ldq_uop_6_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_23_inst = ldq_uop_6_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_6_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_6_debug_inst = ldq_uop_6_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_23_debug_inst = ldq_uop_6_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_rvc; // @[lsu.scala:219:36] wire l_uop_6_is_rvc = ldq_uop_6_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_rvc = ldq_uop_6_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_6_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_6_debug_pc = ldq_uop_6_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_23_debug_pc = ldq_uop_6_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_0; // @[lsu.scala:219:36] wire l_uop_6_iq_type_0 = ldq_uop_6_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_23_iq_type_0 = ldq_uop_6_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_1; // @[lsu.scala:219:36] wire l_uop_6_iq_type_1 = ldq_uop_6_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_23_iq_type_1 = ldq_uop_6_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_2; // @[lsu.scala:219:36] wire l_uop_6_iq_type_2 = ldq_uop_6_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_23_iq_type_2 = ldq_uop_6_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_3; // @[lsu.scala:219:36] wire l_uop_6_iq_type_3 = ldq_uop_6_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_23_iq_type_3 = ldq_uop_6_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_0; // @[lsu.scala:219:36] wire l_uop_6_fu_code_0 = ldq_uop_6_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_0 = ldq_uop_6_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_1; // @[lsu.scala:219:36] wire l_uop_6_fu_code_1 = ldq_uop_6_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_1 = ldq_uop_6_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_2; // @[lsu.scala:219:36] wire l_uop_6_fu_code_2 = ldq_uop_6_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_2 = ldq_uop_6_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_3; // @[lsu.scala:219:36] wire l_uop_6_fu_code_3 = ldq_uop_6_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_3 = ldq_uop_6_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_4; // @[lsu.scala:219:36] wire l_uop_6_fu_code_4 = ldq_uop_6_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_4 = ldq_uop_6_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_5; // @[lsu.scala:219:36] wire l_uop_6_fu_code_5 = ldq_uop_6_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_5 = ldq_uop_6_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_6; // @[lsu.scala:219:36] wire l_uop_6_fu_code_6 = ldq_uop_6_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_6 = ldq_uop_6_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_7; // @[lsu.scala:219:36] wire l_uop_6_fu_code_7 = ldq_uop_6_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_7 = ldq_uop_6_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_8; // @[lsu.scala:219:36] wire l_uop_6_fu_code_8 = ldq_uop_6_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_8 = ldq_uop_6_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_9; // @[lsu.scala:219:36] wire l_uop_6_fu_code_9 = ldq_uop_6_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_23_fu_code_9 = ldq_uop_6_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_issued; // @[lsu.scala:219:36] wire l_uop_6_iw_issued = ldq_uop_6_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_23_iw_issued = ldq_uop_6_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_6_iw_issued_partial_agen = ldq_uop_6_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_23_iw_issued_partial_agen = ldq_uop_6_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_6_iw_issued_partial_dgen = ldq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_23_iw_issued_partial_dgen = ldq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_6_iw_p1_speculative_child = ldq_uop_6_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_iw_p1_speculative_child = ldq_uop_6_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_6_iw_p2_speculative_child = ldq_uop_6_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_iw_p2_speculative_child = ldq_uop_6_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_6_iw_p1_bypass_hint = ldq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_23_iw_p1_bypass_hint = ldq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_6_iw_p2_bypass_hint = ldq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_23_iw_p2_bypass_hint = ldq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_6_iw_p3_bypass_hint = ldq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_23_iw_p3_bypass_hint = ldq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_6_dis_col_sel = ldq_uop_6_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_dis_col_sel = ldq_uop_6_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_6_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_6_br_mask = ldq_uop_6_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_23_br_mask = ldq_uop_6_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_6_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_6_br_tag = ldq_uop_6_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_23_br_tag = ldq_uop_6_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_6_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_6_br_type = ldq_uop_6_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_23_br_type = ldq_uop_6_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_sfb; // @[lsu.scala:219:36] wire l_uop_6_is_sfb = ldq_uop_6_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_sfb = ldq_uop_6_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_fence; // @[lsu.scala:219:36] wire l_uop_6_is_fence = ldq_uop_6_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_fence = ldq_uop_6_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_fencei; // @[lsu.scala:219:36] wire l_uop_6_is_fencei = ldq_uop_6_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_fencei = ldq_uop_6_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_sfence; // @[lsu.scala:219:36] wire l_uop_6_is_sfence = ldq_uop_6_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_sfence = ldq_uop_6_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_amo; // @[lsu.scala:219:36] wire l_uop_6_is_amo = ldq_uop_6_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_amo = ldq_uop_6_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_eret; // @[lsu.scala:219:36] wire l_uop_6_is_eret = ldq_uop_6_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_eret = ldq_uop_6_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_6_is_sys_pc2epc = ldq_uop_6_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_sys_pc2epc = ldq_uop_6_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_rocc; // @[lsu.scala:219:36] wire l_uop_6_is_rocc = ldq_uop_6_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_rocc = ldq_uop_6_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_mov; // @[lsu.scala:219:36] wire l_uop_6_is_mov = ldq_uop_6_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_mov = ldq_uop_6_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_6_ftq_idx = ldq_uop_6_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_23_ftq_idx = ldq_uop_6_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_edge_inst; // @[lsu.scala:219:36] wire l_uop_6_edge_inst = ldq_uop_6_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_23_edge_inst = ldq_uop_6_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_6_pc_lob = ldq_uop_6_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_23_pc_lob = ldq_uop_6_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_taken; // @[lsu.scala:219:36] wire l_uop_6_taken = ldq_uop_6_taken; // @[lsu.scala:219:36, :1191:37] wire uop_23_taken = ldq_uop_6_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_imm_rename; // @[lsu.scala:219:36] wire l_uop_6_imm_rename = ldq_uop_6_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_23_imm_rename = ldq_uop_6_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_6_imm_sel = ldq_uop_6_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_23_imm_sel = ldq_uop_6_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_6_pimm = ldq_uop_6_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_23_pimm = ldq_uop_6_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_6_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_6_imm_packed = ldq_uop_6_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_23_imm_packed = ldq_uop_6_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_6_op1_sel = ldq_uop_6_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_op1_sel = ldq_uop_6_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_6_op2_sel = ldq_uop_6_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_23_op2_sel = ldq_uop_6_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ldst = ldq_uop_6_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_ldst = ldq_uop_6_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_wen = ldq_uop_6_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_wen = ldq_uop_6_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ren1 = ldq_uop_6_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_ren1 = ldq_uop_6_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ren2 = ldq_uop_6_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_ren2 = ldq_uop_6_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ren3 = ldq_uop_6_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_ren3 = ldq_uop_6_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_swap12 = ldq_uop_6_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_swap12 = ldq_uop_6_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_swap23 = ldq_uop_6_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_swap23 = ldq_uop_6_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_6_fp_ctrl_typeTagIn = ldq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_fp_ctrl_typeTagIn = ldq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_6_fp_ctrl_typeTagOut = ldq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_fp_ctrl_typeTagOut = ldq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_fromint = ldq_uop_6_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_fromint = ldq_uop_6_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_toint = ldq_uop_6_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_toint = ldq_uop_6_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_fastpipe = ldq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_fastpipe = ldq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_fma = ldq_uop_6_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_fma = ldq_uop_6_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_div = ldq_uop_6_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_div = ldq_uop_6_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_sqrt = ldq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_sqrt = ldq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_wflags = ldq_uop_6_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_wflags = ldq_uop_6_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_vec = ldq_uop_6_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_ctrl_vec = ldq_uop_6_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_6_rob_idx = ldq_uop_6_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_23_rob_idx = ldq_uop_6_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_6_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_6_ldq_idx = ldq_uop_6_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_23_ldq_idx = ldq_uop_6_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_6_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_6_stq_idx = ldq_uop_6_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_23_stq_idx = ldq_uop_6_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_6_rxq_idx = ldq_uop_6_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_rxq_idx = ldq_uop_6_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_6_pdst = ldq_uop_6_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_23_pdst = ldq_uop_6_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_6_prs1 = ldq_uop_6_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_23_prs1 = ldq_uop_6_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_6_prs2 = ldq_uop_6_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_23_prs2 = ldq_uop_6_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_6_prs3 = ldq_uop_6_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_23_prs3 = ldq_uop_6_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_6_ppred = ldq_uop_6_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_23_ppred = ldq_uop_6_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_prs1_busy; // @[lsu.scala:219:36] wire l_uop_6_prs1_busy = ldq_uop_6_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_23_prs1_busy = ldq_uop_6_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_prs2_busy; // @[lsu.scala:219:36] wire l_uop_6_prs2_busy = ldq_uop_6_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_23_prs2_busy = ldq_uop_6_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_prs3_busy; // @[lsu.scala:219:36] wire l_uop_6_prs3_busy = ldq_uop_6_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_23_prs3_busy = ldq_uop_6_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_ppred_busy; // @[lsu.scala:219:36] wire l_uop_6_ppred_busy = ldq_uop_6_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_23_ppred_busy = ldq_uop_6_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_6_stale_pdst = ldq_uop_6_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_23_stale_pdst = ldq_uop_6_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_exception; // @[lsu.scala:219:36] wire l_uop_6_exception = ldq_uop_6_exception; // @[lsu.scala:219:36, :1191:37] wire uop_23_exception = ldq_uop_6_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_6_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_6_exc_cause = ldq_uop_6_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_23_exc_cause = ldq_uop_6_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_6_mem_cmd = ldq_uop_6_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_23_mem_cmd = ldq_uop_6_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_6_mem_size = ldq_uop_6_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_mem_size = ldq_uop_6_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_mem_signed; // @[lsu.scala:219:36] wire l_uop_6_mem_signed = ldq_uop_6_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_23_mem_signed = ldq_uop_6_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_uses_ldq; // @[lsu.scala:219:36] wire l_uop_6_uses_ldq = ldq_uop_6_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_23_uses_ldq = ldq_uop_6_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_uses_stq; // @[lsu.scala:219:36] wire l_uop_6_uses_stq = ldq_uop_6_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_23_uses_stq = ldq_uop_6_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_unique; // @[lsu.scala:219:36] wire l_uop_6_is_unique = ldq_uop_6_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_23_is_unique = ldq_uop_6_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_6_flush_on_commit = ldq_uop_6_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_23_flush_on_commit = ldq_uop_6_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_6_csr_cmd = ldq_uop_6_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_23_csr_cmd = ldq_uop_6_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_6_ldst_is_rs1 = ldq_uop_6_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_23_ldst_is_rs1 = ldq_uop_6_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_6_ldst = ldq_uop_6_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_23_ldst = ldq_uop_6_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_6_lrs1 = ldq_uop_6_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_23_lrs1 = ldq_uop_6_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_6_lrs2 = ldq_uop_6_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_23_lrs2 = ldq_uop_6_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_6_lrs3 = ldq_uop_6_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_23_lrs3 = ldq_uop_6_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_6_dst_rtype = ldq_uop_6_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_dst_rtype = ldq_uop_6_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_6_lrs1_rtype = ldq_uop_6_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_lrs1_rtype = ldq_uop_6_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_6_lrs2_rtype = ldq_uop_6_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_lrs2_rtype = ldq_uop_6_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_frs3_en; // @[lsu.scala:219:36] wire l_uop_6_frs3_en = ldq_uop_6_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_23_frs3_en = ldq_uop_6_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fcn_dw; // @[lsu.scala:219:36] wire l_uop_6_fcn_dw = ldq_uop_6_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_23_fcn_dw = ldq_uop_6_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_6_fcn_op = ldq_uop_6_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_23_fcn_op = ldq_uop_6_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_val; // @[lsu.scala:219:36] wire l_uop_6_fp_val = ldq_uop_6_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_23_fp_val = ldq_uop_6_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_6_fp_rm = ldq_uop_6_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_23_fp_rm = ldq_uop_6_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_6_fp_typ = ldq_uop_6_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_23_fp_typ = ldq_uop_6_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_6_xcpt_pf_if = ldq_uop_6_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_23_xcpt_pf_if = ldq_uop_6_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_6_xcpt_ae_if = ldq_uop_6_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_23_xcpt_ae_if = ldq_uop_6_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_6_xcpt_ma_if = ldq_uop_6_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_23_xcpt_ma_if = ldq_uop_6_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_6_bp_debug_if = ldq_uop_6_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_23_bp_debug_if = ldq_uop_6_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_6_bp_xcpt_if = ldq_uop_6_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_23_bp_xcpt_if = ldq_uop_6_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_6_debug_fsrc = ldq_uop_6_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_23_debug_fsrc = ldq_uop_6_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_6_debug_tsrc = ldq_uop_6_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_23_debug_tsrc = ldq_uop_6_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_7_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_7_inst = ldq_uop_7_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_24_inst = ldq_uop_7_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_7_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_7_debug_inst = ldq_uop_7_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_24_debug_inst = ldq_uop_7_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_rvc; // @[lsu.scala:219:36] wire l_uop_7_is_rvc = ldq_uop_7_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_rvc = ldq_uop_7_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_7_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_7_debug_pc = ldq_uop_7_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_24_debug_pc = ldq_uop_7_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_0; // @[lsu.scala:219:36] wire l_uop_7_iq_type_0 = ldq_uop_7_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_24_iq_type_0 = ldq_uop_7_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_1; // @[lsu.scala:219:36] wire l_uop_7_iq_type_1 = ldq_uop_7_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_24_iq_type_1 = ldq_uop_7_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_2; // @[lsu.scala:219:36] wire l_uop_7_iq_type_2 = ldq_uop_7_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_24_iq_type_2 = ldq_uop_7_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_3; // @[lsu.scala:219:36] wire l_uop_7_iq_type_3 = ldq_uop_7_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_24_iq_type_3 = ldq_uop_7_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_0; // @[lsu.scala:219:36] wire l_uop_7_fu_code_0 = ldq_uop_7_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_0 = ldq_uop_7_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_1; // @[lsu.scala:219:36] wire l_uop_7_fu_code_1 = ldq_uop_7_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_1 = ldq_uop_7_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_2; // @[lsu.scala:219:36] wire l_uop_7_fu_code_2 = ldq_uop_7_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_2 = ldq_uop_7_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_3; // @[lsu.scala:219:36] wire l_uop_7_fu_code_3 = ldq_uop_7_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_3 = ldq_uop_7_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_4; // @[lsu.scala:219:36] wire l_uop_7_fu_code_4 = ldq_uop_7_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_4 = ldq_uop_7_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_5; // @[lsu.scala:219:36] wire l_uop_7_fu_code_5 = ldq_uop_7_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_5 = ldq_uop_7_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_6; // @[lsu.scala:219:36] wire l_uop_7_fu_code_6 = ldq_uop_7_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_6 = ldq_uop_7_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_7; // @[lsu.scala:219:36] wire l_uop_7_fu_code_7 = ldq_uop_7_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_7 = ldq_uop_7_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_8; // @[lsu.scala:219:36] wire l_uop_7_fu_code_8 = ldq_uop_7_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_8 = ldq_uop_7_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_9; // @[lsu.scala:219:36] wire l_uop_7_fu_code_9 = ldq_uop_7_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_24_fu_code_9 = ldq_uop_7_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_issued; // @[lsu.scala:219:36] wire l_uop_7_iw_issued = ldq_uop_7_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_24_iw_issued = ldq_uop_7_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_7_iw_issued_partial_agen = ldq_uop_7_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_24_iw_issued_partial_agen = ldq_uop_7_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_7_iw_issued_partial_dgen = ldq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_24_iw_issued_partial_dgen = ldq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_7_iw_p1_speculative_child = ldq_uop_7_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_iw_p1_speculative_child = ldq_uop_7_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_7_iw_p2_speculative_child = ldq_uop_7_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_iw_p2_speculative_child = ldq_uop_7_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_7_iw_p1_bypass_hint = ldq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_24_iw_p1_bypass_hint = ldq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_7_iw_p2_bypass_hint = ldq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_24_iw_p2_bypass_hint = ldq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_7_iw_p3_bypass_hint = ldq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_24_iw_p3_bypass_hint = ldq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_7_dis_col_sel = ldq_uop_7_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_dis_col_sel = ldq_uop_7_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_7_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_7_br_mask = ldq_uop_7_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_24_br_mask = ldq_uop_7_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_7_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_7_br_tag = ldq_uop_7_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_24_br_tag = ldq_uop_7_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_7_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_7_br_type = ldq_uop_7_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_24_br_type = ldq_uop_7_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_sfb; // @[lsu.scala:219:36] wire l_uop_7_is_sfb = ldq_uop_7_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_sfb = ldq_uop_7_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_fence; // @[lsu.scala:219:36] wire l_uop_7_is_fence = ldq_uop_7_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_fence = ldq_uop_7_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_fencei; // @[lsu.scala:219:36] wire l_uop_7_is_fencei = ldq_uop_7_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_fencei = ldq_uop_7_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_sfence; // @[lsu.scala:219:36] wire l_uop_7_is_sfence = ldq_uop_7_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_sfence = ldq_uop_7_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_amo; // @[lsu.scala:219:36] wire l_uop_7_is_amo = ldq_uop_7_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_amo = ldq_uop_7_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_eret; // @[lsu.scala:219:36] wire l_uop_7_is_eret = ldq_uop_7_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_eret = ldq_uop_7_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_7_is_sys_pc2epc = ldq_uop_7_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_sys_pc2epc = ldq_uop_7_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_rocc; // @[lsu.scala:219:36] wire l_uop_7_is_rocc = ldq_uop_7_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_rocc = ldq_uop_7_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_mov; // @[lsu.scala:219:36] wire l_uop_7_is_mov = ldq_uop_7_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_mov = ldq_uop_7_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_7_ftq_idx = ldq_uop_7_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_24_ftq_idx = ldq_uop_7_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_edge_inst; // @[lsu.scala:219:36] wire l_uop_7_edge_inst = ldq_uop_7_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_24_edge_inst = ldq_uop_7_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_7_pc_lob = ldq_uop_7_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_24_pc_lob = ldq_uop_7_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_taken; // @[lsu.scala:219:36] wire l_uop_7_taken = ldq_uop_7_taken; // @[lsu.scala:219:36, :1191:37] wire uop_24_taken = ldq_uop_7_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_imm_rename; // @[lsu.scala:219:36] wire l_uop_7_imm_rename = ldq_uop_7_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_24_imm_rename = ldq_uop_7_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_7_imm_sel = ldq_uop_7_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_24_imm_sel = ldq_uop_7_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_7_pimm = ldq_uop_7_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_24_pimm = ldq_uop_7_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_7_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_7_imm_packed = ldq_uop_7_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_24_imm_packed = ldq_uop_7_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_7_op1_sel = ldq_uop_7_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_op1_sel = ldq_uop_7_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_7_op2_sel = ldq_uop_7_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_24_op2_sel = ldq_uop_7_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ldst = ldq_uop_7_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_ldst = ldq_uop_7_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_wen = ldq_uop_7_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_wen = ldq_uop_7_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ren1 = ldq_uop_7_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_ren1 = ldq_uop_7_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ren2 = ldq_uop_7_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_ren2 = ldq_uop_7_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ren3 = ldq_uop_7_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_ren3 = ldq_uop_7_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_swap12 = ldq_uop_7_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_swap12 = ldq_uop_7_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_swap23 = ldq_uop_7_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_swap23 = ldq_uop_7_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_7_fp_ctrl_typeTagIn = ldq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_fp_ctrl_typeTagIn = ldq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_7_fp_ctrl_typeTagOut = ldq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_fp_ctrl_typeTagOut = ldq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_fromint = ldq_uop_7_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_fromint = ldq_uop_7_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_toint = ldq_uop_7_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_toint = ldq_uop_7_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_fastpipe = ldq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_fastpipe = ldq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_fma = ldq_uop_7_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_fma = ldq_uop_7_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_div = ldq_uop_7_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_div = ldq_uop_7_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_sqrt = ldq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_sqrt = ldq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_wflags = ldq_uop_7_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_wflags = ldq_uop_7_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_vec = ldq_uop_7_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_ctrl_vec = ldq_uop_7_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_7_rob_idx = ldq_uop_7_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_24_rob_idx = ldq_uop_7_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_7_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_7_ldq_idx = ldq_uop_7_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_24_ldq_idx = ldq_uop_7_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_7_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_7_stq_idx = ldq_uop_7_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_24_stq_idx = ldq_uop_7_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_7_rxq_idx = ldq_uop_7_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_rxq_idx = ldq_uop_7_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_7_pdst = ldq_uop_7_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_24_pdst = ldq_uop_7_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_7_prs1 = ldq_uop_7_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_24_prs1 = ldq_uop_7_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_7_prs2 = ldq_uop_7_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_24_prs2 = ldq_uop_7_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_7_prs3 = ldq_uop_7_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_24_prs3 = ldq_uop_7_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_7_ppred = ldq_uop_7_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_24_ppred = ldq_uop_7_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_prs1_busy; // @[lsu.scala:219:36] wire l_uop_7_prs1_busy = ldq_uop_7_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_24_prs1_busy = ldq_uop_7_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_prs2_busy; // @[lsu.scala:219:36] wire l_uop_7_prs2_busy = ldq_uop_7_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_24_prs2_busy = ldq_uop_7_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_prs3_busy; // @[lsu.scala:219:36] wire l_uop_7_prs3_busy = ldq_uop_7_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_24_prs3_busy = ldq_uop_7_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_ppred_busy; // @[lsu.scala:219:36] wire l_uop_7_ppred_busy = ldq_uop_7_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_24_ppred_busy = ldq_uop_7_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_7_stale_pdst = ldq_uop_7_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_24_stale_pdst = ldq_uop_7_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_exception; // @[lsu.scala:219:36] wire l_uop_7_exception = ldq_uop_7_exception; // @[lsu.scala:219:36, :1191:37] wire uop_24_exception = ldq_uop_7_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_7_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_7_exc_cause = ldq_uop_7_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_24_exc_cause = ldq_uop_7_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_7_mem_cmd = ldq_uop_7_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_24_mem_cmd = ldq_uop_7_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_7_mem_size = ldq_uop_7_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_mem_size = ldq_uop_7_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_mem_signed; // @[lsu.scala:219:36] wire l_uop_7_mem_signed = ldq_uop_7_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_24_mem_signed = ldq_uop_7_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_uses_ldq; // @[lsu.scala:219:36] wire l_uop_7_uses_ldq = ldq_uop_7_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_24_uses_ldq = ldq_uop_7_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_uses_stq; // @[lsu.scala:219:36] wire l_uop_7_uses_stq = ldq_uop_7_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_24_uses_stq = ldq_uop_7_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_unique; // @[lsu.scala:219:36] wire l_uop_7_is_unique = ldq_uop_7_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_24_is_unique = ldq_uop_7_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_7_flush_on_commit = ldq_uop_7_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_24_flush_on_commit = ldq_uop_7_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_7_csr_cmd = ldq_uop_7_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_24_csr_cmd = ldq_uop_7_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_7_ldst_is_rs1 = ldq_uop_7_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_24_ldst_is_rs1 = ldq_uop_7_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_7_ldst = ldq_uop_7_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_24_ldst = ldq_uop_7_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_7_lrs1 = ldq_uop_7_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_24_lrs1 = ldq_uop_7_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_7_lrs2 = ldq_uop_7_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_24_lrs2 = ldq_uop_7_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_7_lrs3 = ldq_uop_7_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_24_lrs3 = ldq_uop_7_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_7_dst_rtype = ldq_uop_7_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_dst_rtype = ldq_uop_7_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_7_lrs1_rtype = ldq_uop_7_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_lrs1_rtype = ldq_uop_7_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_7_lrs2_rtype = ldq_uop_7_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_lrs2_rtype = ldq_uop_7_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_frs3_en; // @[lsu.scala:219:36] wire l_uop_7_frs3_en = ldq_uop_7_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_24_frs3_en = ldq_uop_7_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fcn_dw; // @[lsu.scala:219:36] wire l_uop_7_fcn_dw = ldq_uop_7_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_24_fcn_dw = ldq_uop_7_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_7_fcn_op = ldq_uop_7_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_24_fcn_op = ldq_uop_7_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_val; // @[lsu.scala:219:36] wire l_uop_7_fp_val = ldq_uop_7_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_24_fp_val = ldq_uop_7_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_7_fp_rm = ldq_uop_7_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_24_fp_rm = ldq_uop_7_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_7_fp_typ = ldq_uop_7_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_24_fp_typ = ldq_uop_7_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_7_xcpt_pf_if = ldq_uop_7_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_24_xcpt_pf_if = ldq_uop_7_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_7_xcpt_ae_if = ldq_uop_7_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_24_xcpt_ae_if = ldq_uop_7_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_7_xcpt_ma_if = ldq_uop_7_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_24_xcpt_ma_if = ldq_uop_7_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_7_bp_debug_if = ldq_uop_7_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_24_bp_debug_if = ldq_uop_7_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_7_bp_xcpt_if = ldq_uop_7_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_24_bp_xcpt_if = ldq_uop_7_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_7_debug_fsrc = ldq_uop_7_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_24_debug_fsrc = ldq_uop_7_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_7_debug_tsrc = ldq_uop_7_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_24_debug_tsrc = ldq_uop_7_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_8_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_8_inst = ldq_uop_8_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_25_inst = ldq_uop_8_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_8_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_8_debug_inst = ldq_uop_8_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_25_debug_inst = ldq_uop_8_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_rvc; // @[lsu.scala:219:36] wire l_uop_8_is_rvc = ldq_uop_8_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_rvc = ldq_uop_8_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_8_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_8_debug_pc = ldq_uop_8_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_25_debug_pc = ldq_uop_8_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_0; // @[lsu.scala:219:36] wire l_uop_8_iq_type_0 = ldq_uop_8_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_0 = ldq_uop_8_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_1; // @[lsu.scala:219:36] wire l_uop_8_iq_type_1 = ldq_uop_8_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_1 = ldq_uop_8_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_2; // @[lsu.scala:219:36] wire l_uop_8_iq_type_2 = ldq_uop_8_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_2 = ldq_uop_8_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_3; // @[lsu.scala:219:36] wire l_uop_8_iq_type_3 = ldq_uop_8_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_3 = ldq_uop_8_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_0; // @[lsu.scala:219:36] wire l_uop_8_fu_code_0 = ldq_uop_8_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_0 = ldq_uop_8_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_1; // @[lsu.scala:219:36] wire l_uop_8_fu_code_1 = ldq_uop_8_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_1 = ldq_uop_8_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_2; // @[lsu.scala:219:36] wire l_uop_8_fu_code_2 = ldq_uop_8_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_2 = ldq_uop_8_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_3; // @[lsu.scala:219:36] wire l_uop_8_fu_code_3 = ldq_uop_8_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_3 = ldq_uop_8_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_4; // @[lsu.scala:219:36] wire l_uop_8_fu_code_4 = ldq_uop_8_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_4 = ldq_uop_8_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_5; // @[lsu.scala:219:36] wire l_uop_8_fu_code_5 = ldq_uop_8_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_5 = ldq_uop_8_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_6; // @[lsu.scala:219:36] wire l_uop_8_fu_code_6 = ldq_uop_8_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_6 = ldq_uop_8_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_7; // @[lsu.scala:219:36] wire l_uop_8_fu_code_7 = ldq_uop_8_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_7 = ldq_uop_8_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_8; // @[lsu.scala:219:36] wire l_uop_8_fu_code_8 = ldq_uop_8_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_8 = ldq_uop_8_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_9; // @[lsu.scala:219:36] wire l_uop_8_fu_code_9 = ldq_uop_8_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_9 = ldq_uop_8_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_issued; // @[lsu.scala:219:36] wire l_uop_8_iw_issued = ldq_uop_8_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_issued = ldq_uop_8_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_8_iw_issued_partial_agen = ldq_uop_8_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_issued_partial_agen = ldq_uop_8_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_8_iw_issued_partial_dgen = ldq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_issued_partial_dgen = ldq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_8_iw_p1_speculative_child = ldq_uop_8_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_iw_p1_speculative_child = ldq_uop_8_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_8_iw_p2_speculative_child = ldq_uop_8_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_iw_p2_speculative_child = ldq_uop_8_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_8_iw_p1_bypass_hint = ldq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_p1_bypass_hint = ldq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_8_iw_p2_bypass_hint = ldq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_p2_bypass_hint = ldq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_8_iw_p3_bypass_hint = ldq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_p3_bypass_hint = ldq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_8_dis_col_sel = ldq_uop_8_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_dis_col_sel = ldq_uop_8_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_8_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_8_br_mask = ldq_uop_8_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_25_br_mask = ldq_uop_8_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_8_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_8_br_tag = ldq_uop_8_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_25_br_tag = ldq_uop_8_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_8_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_8_br_type = ldq_uop_8_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_25_br_type = ldq_uop_8_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_sfb; // @[lsu.scala:219:36] wire l_uop_8_is_sfb = ldq_uop_8_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_sfb = ldq_uop_8_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_fence; // @[lsu.scala:219:36] wire l_uop_8_is_fence = ldq_uop_8_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_fence = ldq_uop_8_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_fencei; // @[lsu.scala:219:36] wire l_uop_8_is_fencei = ldq_uop_8_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_fencei = ldq_uop_8_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_sfence; // @[lsu.scala:219:36] wire l_uop_8_is_sfence = ldq_uop_8_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_sfence = ldq_uop_8_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_amo; // @[lsu.scala:219:36] wire l_uop_8_is_amo = ldq_uop_8_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_amo = ldq_uop_8_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_eret; // @[lsu.scala:219:36] wire l_uop_8_is_eret = ldq_uop_8_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_eret = ldq_uop_8_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_8_is_sys_pc2epc = ldq_uop_8_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_sys_pc2epc = ldq_uop_8_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_rocc; // @[lsu.scala:219:36] wire l_uop_8_is_rocc = ldq_uop_8_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_rocc = ldq_uop_8_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_mov; // @[lsu.scala:219:36] wire l_uop_8_is_mov = ldq_uop_8_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_mov = ldq_uop_8_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_8_ftq_idx = ldq_uop_8_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_ftq_idx = ldq_uop_8_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_edge_inst; // @[lsu.scala:219:36] wire l_uop_8_edge_inst = ldq_uop_8_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_25_edge_inst = ldq_uop_8_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_8_pc_lob = ldq_uop_8_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_pc_lob = ldq_uop_8_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_taken; // @[lsu.scala:219:36] wire l_uop_8_taken = ldq_uop_8_taken; // @[lsu.scala:219:36, :1191:37] wire uop_25_taken = ldq_uop_8_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_imm_rename; // @[lsu.scala:219:36] wire l_uop_8_imm_rename = ldq_uop_8_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_25_imm_rename = ldq_uop_8_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_8_imm_sel = ldq_uop_8_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_imm_sel = ldq_uop_8_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_8_pimm = ldq_uop_8_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_pimm = ldq_uop_8_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_8_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_8_imm_packed = ldq_uop_8_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_25_imm_packed = ldq_uop_8_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_8_op1_sel = ldq_uop_8_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_op1_sel = ldq_uop_8_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_8_op2_sel = ldq_uop_8_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_op2_sel = ldq_uop_8_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ldst = ldq_uop_8_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ldst = ldq_uop_8_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_wen = ldq_uop_8_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_wen = ldq_uop_8_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ren1 = ldq_uop_8_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ren1 = ldq_uop_8_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ren2 = ldq_uop_8_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ren2 = ldq_uop_8_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ren3 = ldq_uop_8_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ren3 = ldq_uop_8_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_swap12 = ldq_uop_8_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_swap12 = ldq_uop_8_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_swap23 = ldq_uop_8_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_swap23 = ldq_uop_8_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_8_fp_ctrl_typeTagIn = ldq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_fp_ctrl_typeTagIn = ldq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_8_fp_ctrl_typeTagOut = ldq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_fp_ctrl_typeTagOut = ldq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_fromint = ldq_uop_8_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_fromint = ldq_uop_8_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_toint = ldq_uop_8_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_toint = ldq_uop_8_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_fastpipe = ldq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_fastpipe = ldq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_fma = ldq_uop_8_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_fma = ldq_uop_8_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_div = ldq_uop_8_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_div = ldq_uop_8_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_sqrt = ldq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_sqrt = ldq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_wflags = ldq_uop_8_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_wflags = ldq_uop_8_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_vec = ldq_uop_8_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_vec = ldq_uop_8_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_8_rob_idx = ldq_uop_8_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_rob_idx = ldq_uop_8_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_8_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_8_ldq_idx = ldq_uop_8_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_25_ldq_idx = ldq_uop_8_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_8_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_8_stq_idx = ldq_uop_8_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_25_stq_idx = ldq_uop_8_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_8_rxq_idx = ldq_uop_8_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_rxq_idx = ldq_uop_8_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_8_pdst = ldq_uop_8_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_pdst = ldq_uop_8_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_8_prs1 = ldq_uop_8_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_prs1 = ldq_uop_8_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_8_prs2 = ldq_uop_8_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_prs2 = ldq_uop_8_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_8_prs3 = ldq_uop_8_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_prs3 = ldq_uop_8_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_8_ppred = ldq_uop_8_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_ppred = ldq_uop_8_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_prs1_busy; // @[lsu.scala:219:36] wire l_uop_8_prs1_busy = ldq_uop_8_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_prs1_busy = ldq_uop_8_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_prs2_busy; // @[lsu.scala:219:36] wire l_uop_8_prs2_busy = ldq_uop_8_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_prs2_busy = ldq_uop_8_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_prs3_busy; // @[lsu.scala:219:36] wire l_uop_8_prs3_busy = ldq_uop_8_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_prs3_busy = ldq_uop_8_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_ppred_busy; // @[lsu.scala:219:36] wire l_uop_8_ppred_busy = ldq_uop_8_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_ppred_busy = ldq_uop_8_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_8_stale_pdst = ldq_uop_8_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_stale_pdst = ldq_uop_8_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_exception; // @[lsu.scala:219:36] wire l_uop_8_exception = ldq_uop_8_exception; // @[lsu.scala:219:36, :1191:37] wire uop_25_exception = ldq_uop_8_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_8_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_8_exc_cause = ldq_uop_8_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_25_exc_cause = ldq_uop_8_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_8_mem_cmd = ldq_uop_8_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_mem_cmd = ldq_uop_8_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_8_mem_size = ldq_uop_8_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_mem_size = ldq_uop_8_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_mem_signed; // @[lsu.scala:219:36] wire l_uop_8_mem_signed = ldq_uop_8_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_25_mem_signed = ldq_uop_8_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_uses_ldq; // @[lsu.scala:219:36] wire l_uop_8_uses_ldq = ldq_uop_8_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_25_uses_ldq = ldq_uop_8_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_uses_stq; // @[lsu.scala:219:36] wire l_uop_8_uses_stq = ldq_uop_8_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_25_uses_stq = ldq_uop_8_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_unique; // @[lsu.scala:219:36] wire l_uop_8_is_unique = ldq_uop_8_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_unique = ldq_uop_8_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_8_flush_on_commit = ldq_uop_8_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_25_flush_on_commit = ldq_uop_8_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_8_csr_cmd = ldq_uop_8_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_csr_cmd = ldq_uop_8_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_8_ldst_is_rs1 = ldq_uop_8_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_25_ldst_is_rs1 = ldq_uop_8_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_8_ldst = ldq_uop_8_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_ldst = ldq_uop_8_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_8_lrs1 = ldq_uop_8_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_lrs1 = ldq_uop_8_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_8_lrs2 = ldq_uop_8_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_lrs2 = ldq_uop_8_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_8_lrs3 = ldq_uop_8_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_lrs3 = ldq_uop_8_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_8_dst_rtype = ldq_uop_8_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_dst_rtype = ldq_uop_8_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_8_lrs1_rtype = ldq_uop_8_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_lrs1_rtype = ldq_uop_8_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_8_lrs2_rtype = ldq_uop_8_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_lrs2_rtype = ldq_uop_8_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_frs3_en; // @[lsu.scala:219:36] wire l_uop_8_frs3_en = ldq_uop_8_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_25_frs3_en = ldq_uop_8_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fcn_dw; // @[lsu.scala:219:36] wire l_uop_8_fcn_dw = ldq_uop_8_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_25_fcn_dw = ldq_uop_8_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_8_fcn_op = ldq_uop_8_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_fcn_op = ldq_uop_8_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_val; // @[lsu.scala:219:36] wire l_uop_8_fp_val = ldq_uop_8_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_val = ldq_uop_8_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_8_fp_rm = ldq_uop_8_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_fp_rm = ldq_uop_8_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_8_fp_typ = ldq_uop_8_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_fp_typ = ldq_uop_8_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_8_xcpt_pf_if = ldq_uop_8_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_xcpt_pf_if = ldq_uop_8_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_8_xcpt_ae_if = ldq_uop_8_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_xcpt_ae_if = ldq_uop_8_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_8_xcpt_ma_if = ldq_uop_8_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_xcpt_ma_if = ldq_uop_8_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_8_bp_debug_if = ldq_uop_8_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_bp_debug_if = ldq_uop_8_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_8_bp_xcpt_if = ldq_uop_8_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_bp_xcpt_if = ldq_uop_8_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_8_debug_fsrc = ldq_uop_8_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_debug_fsrc = ldq_uop_8_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_8_debug_tsrc = ldq_uop_8_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_debug_tsrc = ldq_uop_8_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_9_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_9_inst = ldq_uop_9_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_26_inst = ldq_uop_9_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_9_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_9_debug_inst = ldq_uop_9_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_26_debug_inst = ldq_uop_9_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_rvc; // @[lsu.scala:219:36] wire l_uop_9_is_rvc = ldq_uop_9_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_rvc = ldq_uop_9_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_9_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_9_debug_pc = ldq_uop_9_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_26_debug_pc = ldq_uop_9_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_0; // @[lsu.scala:219:36] wire l_uop_9_iq_type_0 = ldq_uop_9_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_0 = ldq_uop_9_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_1; // @[lsu.scala:219:36] wire l_uop_9_iq_type_1 = ldq_uop_9_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_1 = ldq_uop_9_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_2; // @[lsu.scala:219:36] wire l_uop_9_iq_type_2 = ldq_uop_9_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_2 = ldq_uop_9_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_3; // @[lsu.scala:219:36] wire l_uop_9_iq_type_3 = ldq_uop_9_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_3 = ldq_uop_9_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_0; // @[lsu.scala:219:36] wire l_uop_9_fu_code_0 = ldq_uop_9_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_0 = ldq_uop_9_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_1; // @[lsu.scala:219:36] wire l_uop_9_fu_code_1 = ldq_uop_9_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_1 = ldq_uop_9_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_2; // @[lsu.scala:219:36] wire l_uop_9_fu_code_2 = ldq_uop_9_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_2 = ldq_uop_9_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_3; // @[lsu.scala:219:36] wire l_uop_9_fu_code_3 = ldq_uop_9_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_3 = ldq_uop_9_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_4; // @[lsu.scala:219:36] wire l_uop_9_fu_code_4 = ldq_uop_9_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_4 = ldq_uop_9_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_5; // @[lsu.scala:219:36] wire l_uop_9_fu_code_5 = ldq_uop_9_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_5 = ldq_uop_9_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_6; // @[lsu.scala:219:36] wire l_uop_9_fu_code_6 = ldq_uop_9_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_6 = ldq_uop_9_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_7; // @[lsu.scala:219:36] wire l_uop_9_fu_code_7 = ldq_uop_9_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_7 = ldq_uop_9_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_8; // @[lsu.scala:219:36] wire l_uop_9_fu_code_8 = ldq_uop_9_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_8 = ldq_uop_9_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_9; // @[lsu.scala:219:36] wire l_uop_9_fu_code_9 = ldq_uop_9_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_9 = ldq_uop_9_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_issued; // @[lsu.scala:219:36] wire l_uop_9_iw_issued = ldq_uop_9_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_issued = ldq_uop_9_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_9_iw_issued_partial_agen = ldq_uop_9_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_issued_partial_agen = ldq_uop_9_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_9_iw_issued_partial_dgen = ldq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_issued_partial_dgen = ldq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_9_iw_p1_speculative_child = ldq_uop_9_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_iw_p1_speculative_child = ldq_uop_9_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_9_iw_p2_speculative_child = ldq_uop_9_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_iw_p2_speculative_child = ldq_uop_9_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_9_iw_p1_bypass_hint = ldq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_p1_bypass_hint = ldq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_9_iw_p2_bypass_hint = ldq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_p2_bypass_hint = ldq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_9_iw_p3_bypass_hint = ldq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_p3_bypass_hint = ldq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_9_dis_col_sel = ldq_uop_9_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_dis_col_sel = ldq_uop_9_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_9_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_9_br_mask = ldq_uop_9_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_26_br_mask = ldq_uop_9_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_9_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_9_br_tag = ldq_uop_9_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_26_br_tag = ldq_uop_9_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_9_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_9_br_type = ldq_uop_9_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_26_br_type = ldq_uop_9_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_sfb; // @[lsu.scala:219:36] wire l_uop_9_is_sfb = ldq_uop_9_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_sfb = ldq_uop_9_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_fence; // @[lsu.scala:219:36] wire l_uop_9_is_fence = ldq_uop_9_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_fence = ldq_uop_9_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_fencei; // @[lsu.scala:219:36] wire l_uop_9_is_fencei = ldq_uop_9_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_fencei = ldq_uop_9_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_sfence; // @[lsu.scala:219:36] wire l_uop_9_is_sfence = ldq_uop_9_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_sfence = ldq_uop_9_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_amo; // @[lsu.scala:219:36] wire l_uop_9_is_amo = ldq_uop_9_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_amo = ldq_uop_9_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_eret; // @[lsu.scala:219:36] wire l_uop_9_is_eret = ldq_uop_9_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_eret = ldq_uop_9_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_9_is_sys_pc2epc = ldq_uop_9_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_sys_pc2epc = ldq_uop_9_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_rocc; // @[lsu.scala:219:36] wire l_uop_9_is_rocc = ldq_uop_9_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_rocc = ldq_uop_9_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_mov; // @[lsu.scala:219:36] wire l_uop_9_is_mov = ldq_uop_9_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_mov = ldq_uop_9_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_9_ftq_idx = ldq_uop_9_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_ftq_idx = ldq_uop_9_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_edge_inst; // @[lsu.scala:219:36] wire l_uop_9_edge_inst = ldq_uop_9_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_26_edge_inst = ldq_uop_9_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_9_pc_lob = ldq_uop_9_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_pc_lob = ldq_uop_9_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_taken; // @[lsu.scala:219:36] wire l_uop_9_taken = ldq_uop_9_taken; // @[lsu.scala:219:36, :1191:37] wire uop_26_taken = ldq_uop_9_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_imm_rename; // @[lsu.scala:219:36] wire l_uop_9_imm_rename = ldq_uop_9_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_26_imm_rename = ldq_uop_9_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_9_imm_sel = ldq_uop_9_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_imm_sel = ldq_uop_9_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_9_pimm = ldq_uop_9_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_pimm = ldq_uop_9_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_9_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_9_imm_packed = ldq_uop_9_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_26_imm_packed = ldq_uop_9_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_9_op1_sel = ldq_uop_9_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_op1_sel = ldq_uop_9_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_9_op2_sel = ldq_uop_9_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_op2_sel = ldq_uop_9_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ldst = ldq_uop_9_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ldst = ldq_uop_9_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_wen = ldq_uop_9_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_wen = ldq_uop_9_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ren1 = ldq_uop_9_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ren1 = ldq_uop_9_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ren2 = ldq_uop_9_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ren2 = ldq_uop_9_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ren3 = ldq_uop_9_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ren3 = ldq_uop_9_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_swap12 = ldq_uop_9_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_swap12 = ldq_uop_9_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_swap23 = ldq_uop_9_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_swap23 = ldq_uop_9_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_9_fp_ctrl_typeTagIn = ldq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_fp_ctrl_typeTagIn = ldq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_9_fp_ctrl_typeTagOut = ldq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_fp_ctrl_typeTagOut = ldq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_fromint = ldq_uop_9_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_fromint = ldq_uop_9_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_toint = ldq_uop_9_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_toint = ldq_uop_9_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_fastpipe = ldq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_fastpipe = ldq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_fma = ldq_uop_9_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_fma = ldq_uop_9_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_div = ldq_uop_9_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_div = ldq_uop_9_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_sqrt = ldq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_sqrt = ldq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_wflags = ldq_uop_9_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_wflags = ldq_uop_9_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_vec = ldq_uop_9_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_vec = ldq_uop_9_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_9_rob_idx = ldq_uop_9_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_rob_idx = ldq_uop_9_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_9_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_9_ldq_idx = ldq_uop_9_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_26_ldq_idx = ldq_uop_9_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_9_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_9_stq_idx = ldq_uop_9_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_26_stq_idx = ldq_uop_9_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_9_rxq_idx = ldq_uop_9_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_rxq_idx = ldq_uop_9_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_9_pdst = ldq_uop_9_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_pdst = ldq_uop_9_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_9_prs1 = ldq_uop_9_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_prs1 = ldq_uop_9_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_9_prs2 = ldq_uop_9_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_prs2 = ldq_uop_9_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_9_prs3 = ldq_uop_9_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_prs3 = ldq_uop_9_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_9_ppred = ldq_uop_9_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_ppred = ldq_uop_9_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_prs1_busy; // @[lsu.scala:219:36] wire l_uop_9_prs1_busy = ldq_uop_9_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_prs1_busy = ldq_uop_9_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_prs2_busy; // @[lsu.scala:219:36] wire l_uop_9_prs2_busy = ldq_uop_9_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_prs2_busy = ldq_uop_9_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_prs3_busy; // @[lsu.scala:219:36] wire l_uop_9_prs3_busy = ldq_uop_9_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_prs3_busy = ldq_uop_9_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_ppred_busy; // @[lsu.scala:219:36] wire l_uop_9_ppred_busy = ldq_uop_9_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_ppred_busy = ldq_uop_9_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_9_stale_pdst = ldq_uop_9_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_stale_pdst = ldq_uop_9_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_exception; // @[lsu.scala:219:36] wire l_uop_9_exception = ldq_uop_9_exception; // @[lsu.scala:219:36, :1191:37] wire uop_26_exception = ldq_uop_9_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_9_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_9_exc_cause = ldq_uop_9_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_26_exc_cause = ldq_uop_9_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_9_mem_cmd = ldq_uop_9_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_mem_cmd = ldq_uop_9_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_9_mem_size = ldq_uop_9_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_mem_size = ldq_uop_9_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_mem_signed; // @[lsu.scala:219:36] wire l_uop_9_mem_signed = ldq_uop_9_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_26_mem_signed = ldq_uop_9_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_uses_ldq; // @[lsu.scala:219:36] wire l_uop_9_uses_ldq = ldq_uop_9_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_26_uses_ldq = ldq_uop_9_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_uses_stq; // @[lsu.scala:219:36] wire l_uop_9_uses_stq = ldq_uop_9_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_26_uses_stq = ldq_uop_9_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_unique; // @[lsu.scala:219:36] wire l_uop_9_is_unique = ldq_uop_9_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_unique = ldq_uop_9_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_9_flush_on_commit = ldq_uop_9_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_26_flush_on_commit = ldq_uop_9_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_9_csr_cmd = ldq_uop_9_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_csr_cmd = ldq_uop_9_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_9_ldst_is_rs1 = ldq_uop_9_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_26_ldst_is_rs1 = ldq_uop_9_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_9_ldst = ldq_uop_9_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_ldst = ldq_uop_9_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_9_lrs1 = ldq_uop_9_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_lrs1 = ldq_uop_9_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_9_lrs2 = ldq_uop_9_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_lrs2 = ldq_uop_9_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_9_lrs3 = ldq_uop_9_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_lrs3 = ldq_uop_9_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_9_dst_rtype = ldq_uop_9_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_dst_rtype = ldq_uop_9_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_9_lrs1_rtype = ldq_uop_9_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_lrs1_rtype = ldq_uop_9_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_9_lrs2_rtype = ldq_uop_9_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_lrs2_rtype = ldq_uop_9_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_frs3_en; // @[lsu.scala:219:36] wire l_uop_9_frs3_en = ldq_uop_9_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_26_frs3_en = ldq_uop_9_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fcn_dw; // @[lsu.scala:219:36] wire l_uop_9_fcn_dw = ldq_uop_9_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_26_fcn_dw = ldq_uop_9_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_9_fcn_op = ldq_uop_9_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_fcn_op = ldq_uop_9_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_val; // @[lsu.scala:219:36] wire l_uop_9_fp_val = ldq_uop_9_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_val = ldq_uop_9_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_9_fp_rm = ldq_uop_9_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_fp_rm = ldq_uop_9_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_9_fp_typ = ldq_uop_9_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_fp_typ = ldq_uop_9_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_9_xcpt_pf_if = ldq_uop_9_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_xcpt_pf_if = ldq_uop_9_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_9_xcpt_ae_if = ldq_uop_9_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_xcpt_ae_if = ldq_uop_9_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_9_xcpt_ma_if = ldq_uop_9_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_xcpt_ma_if = ldq_uop_9_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_9_bp_debug_if = ldq_uop_9_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_bp_debug_if = ldq_uop_9_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_9_bp_xcpt_if = ldq_uop_9_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_bp_xcpt_if = ldq_uop_9_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_9_debug_fsrc = ldq_uop_9_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_debug_fsrc = ldq_uop_9_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_9_debug_tsrc = ldq_uop_9_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_debug_tsrc = ldq_uop_9_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_10_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_10_inst = ldq_uop_10_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_27_inst = ldq_uop_10_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_10_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_10_debug_inst = ldq_uop_10_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_27_debug_inst = ldq_uop_10_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_rvc; // @[lsu.scala:219:36] wire l_uop_10_is_rvc = ldq_uop_10_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_rvc = ldq_uop_10_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_10_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_10_debug_pc = ldq_uop_10_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_27_debug_pc = ldq_uop_10_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_0; // @[lsu.scala:219:36] wire l_uop_10_iq_type_0 = ldq_uop_10_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_0 = ldq_uop_10_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_1; // @[lsu.scala:219:36] wire l_uop_10_iq_type_1 = ldq_uop_10_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_1 = ldq_uop_10_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_2; // @[lsu.scala:219:36] wire l_uop_10_iq_type_2 = ldq_uop_10_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_2 = ldq_uop_10_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_3; // @[lsu.scala:219:36] wire l_uop_10_iq_type_3 = ldq_uop_10_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_3 = ldq_uop_10_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_0; // @[lsu.scala:219:36] wire l_uop_10_fu_code_0 = ldq_uop_10_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_0 = ldq_uop_10_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_1; // @[lsu.scala:219:36] wire l_uop_10_fu_code_1 = ldq_uop_10_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_1 = ldq_uop_10_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_2; // @[lsu.scala:219:36] wire l_uop_10_fu_code_2 = ldq_uop_10_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_2 = ldq_uop_10_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_3; // @[lsu.scala:219:36] wire l_uop_10_fu_code_3 = ldq_uop_10_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_3 = ldq_uop_10_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_4; // @[lsu.scala:219:36] wire l_uop_10_fu_code_4 = ldq_uop_10_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_4 = ldq_uop_10_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_5; // @[lsu.scala:219:36] wire l_uop_10_fu_code_5 = ldq_uop_10_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_5 = ldq_uop_10_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_6; // @[lsu.scala:219:36] wire l_uop_10_fu_code_6 = ldq_uop_10_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_6 = ldq_uop_10_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_7; // @[lsu.scala:219:36] wire l_uop_10_fu_code_7 = ldq_uop_10_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_7 = ldq_uop_10_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_8; // @[lsu.scala:219:36] wire l_uop_10_fu_code_8 = ldq_uop_10_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_8 = ldq_uop_10_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_9; // @[lsu.scala:219:36] wire l_uop_10_fu_code_9 = ldq_uop_10_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_9 = ldq_uop_10_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_issued; // @[lsu.scala:219:36] wire l_uop_10_iw_issued = ldq_uop_10_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_issued = ldq_uop_10_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_10_iw_issued_partial_agen = ldq_uop_10_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_issued_partial_agen = ldq_uop_10_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_10_iw_issued_partial_dgen = ldq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_issued_partial_dgen = ldq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_10_iw_p1_speculative_child = ldq_uop_10_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_iw_p1_speculative_child = ldq_uop_10_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_10_iw_p2_speculative_child = ldq_uop_10_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_iw_p2_speculative_child = ldq_uop_10_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_10_iw_p1_bypass_hint = ldq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_p1_bypass_hint = ldq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_10_iw_p2_bypass_hint = ldq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_p2_bypass_hint = ldq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_10_iw_p3_bypass_hint = ldq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_p3_bypass_hint = ldq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_10_dis_col_sel = ldq_uop_10_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_dis_col_sel = ldq_uop_10_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_10_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_10_br_mask = ldq_uop_10_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_27_br_mask = ldq_uop_10_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_10_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_10_br_tag = ldq_uop_10_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_27_br_tag = ldq_uop_10_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_10_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_10_br_type = ldq_uop_10_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_27_br_type = ldq_uop_10_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_sfb; // @[lsu.scala:219:36] wire l_uop_10_is_sfb = ldq_uop_10_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_sfb = ldq_uop_10_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_fence; // @[lsu.scala:219:36] wire l_uop_10_is_fence = ldq_uop_10_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_fence = ldq_uop_10_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_fencei; // @[lsu.scala:219:36] wire l_uop_10_is_fencei = ldq_uop_10_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_fencei = ldq_uop_10_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_sfence; // @[lsu.scala:219:36] wire l_uop_10_is_sfence = ldq_uop_10_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_sfence = ldq_uop_10_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_amo; // @[lsu.scala:219:36] wire l_uop_10_is_amo = ldq_uop_10_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_amo = ldq_uop_10_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_eret; // @[lsu.scala:219:36] wire l_uop_10_is_eret = ldq_uop_10_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_eret = ldq_uop_10_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_10_is_sys_pc2epc = ldq_uop_10_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_sys_pc2epc = ldq_uop_10_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_rocc; // @[lsu.scala:219:36] wire l_uop_10_is_rocc = ldq_uop_10_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_rocc = ldq_uop_10_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_mov; // @[lsu.scala:219:36] wire l_uop_10_is_mov = ldq_uop_10_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_mov = ldq_uop_10_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_10_ftq_idx = ldq_uop_10_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_ftq_idx = ldq_uop_10_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_edge_inst; // @[lsu.scala:219:36] wire l_uop_10_edge_inst = ldq_uop_10_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_27_edge_inst = ldq_uop_10_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_10_pc_lob = ldq_uop_10_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_pc_lob = ldq_uop_10_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_taken; // @[lsu.scala:219:36] wire l_uop_10_taken = ldq_uop_10_taken; // @[lsu.scala:219:36, :1191:37] wire uop_27_taken = ldq_uop_10_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_imm_rename; // @[lsu.scala:219:36] wire l_uop_10_imm_rename = ldq_uop_10_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_27_imm_rename = ldq_uop_10_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_10_imm_sel = ldq_uop_10_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_imm_sel = ldq_uop_10_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_10_pimm = ldq_uop_10_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_pimm = ldq_uop_10_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_10_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_10_imm_packed = ldq_uop_10_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_27_imm_packed = ldq_uop_10_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_10_op1_sel = ldq_uop_10_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_op1_sel = ldq_uop_10_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_10_op2_sel = ldq_uop_10_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_op2_sel = ldq_uop_10_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ldst = ldq_uop_10_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ldst = ldq_uop_10_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_wen = ldq_uop_10_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_wen = ldq_uop_10_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ren1 = ldq_uop_10_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ren1 = ldq_uop_10_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ren2 = ldq_uop_10_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ren2 = ldq_uop_10_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ren3 = ldq_uop_10_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ren3 = ldq_uop_10_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_swap12 = ldq_uop_10_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_swap12 = ldq_uop_10_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_swap23 = ldq_uop_10_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_swap23 = ldq_uop_10_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_10_fp_ctrl_typeTagIn = ldq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_fp_ctrl_typeTagIn = ldq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_10_fp_ctrl_typeTagOut = ldq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_fp_ctrl_typeTagOut = ldq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_fromint = ldq_uop_10_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_fromint = ldq_uop_10_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_toint = ldq_uop_10_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_toint = ldq_uop_10_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_fastpipe = ldq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_fastpipe = ldq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_fma = ldq_uop_10_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_fma = ldq_uop_10_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_div = ldq_uop_10_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_div = ldq_uop_10_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_sqrt = ldq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_sqrt = ldq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_wflags = ldq_uop_10_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_wflags = ldq_uop_10_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_vec = ldq_uop_10_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_vec = ldq_uop_10_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_10_rob_idx = ldq_uop_10_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_rob_idx = ldq_uop_10_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_10_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_10_ldq_idx = ldq_uop_10_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_27_ldq_idx = ldq_uop_10_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_10_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_10_stq_idx = ldq_uop_10_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_27_stq_idx = ldq_uop_10_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_10_rxq_idx = ldq_uop_10_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_rxq_idx = ldq_uop_10_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_10_pdst = ldq_uop_10_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_pdst = ldq_uop_10_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_10_prs1 = ldq_uop_10_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_prs1 = ldq_uop_10_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_10_prs2 = ldq_uop_10_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_prs2 = ldq_uop_10_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_10_prs3 = ldq_uop_10_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_prs3 = ldq_uop_10_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_10_ppred = ldq_uop_10_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_ppred = ldq_uop_10_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_prs1_busy; // @[lsu.scala:219:36] wire l_uop_10_prs1_busy = ldq_uop_10_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_prs1_busy = ldq_uop_10_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_prs2_busy; // @[lsu.scala:219:36] wire l_uop_10_prs2_busy = ldq_uop_10_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_prs2_busy = ldq_uop_10_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_prs3_busy; // @[lsu.scala:219:36] wire l_uop_10_prs3_busy = ldq_uop_10_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_prs3_busy = ldq_uop_10_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_ppred_busy; // @[lsu.scala:219:36] wire l_uop_10_ppred_busy = ldq_uop_10_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_ppred_busy = ldq_uop_10_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_10_stale_pdst = ldq_uop_10_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_stale_pdst = ldq_uop_10_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_exception; // @[lsu.scala:219:36] wire l_uop_10_exception = ldq_uop_10_exception; // @[lsu.scala:219:36, :1191:37] wire uop_27_exception = ldq_uop_10_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_10_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_10_exc_cause = ldq_uop_10_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_27_exc_cause = ldq_uop_10_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_10_mem_cmd = ldq_uop_10_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_mem_cmd = ldq_uop_10_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_10_mem_size = ldq_uop_10_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_mem_size = ldq_uop_10_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_mem_signed; // @[lsu.scala:219:36] wire l_uop_10_mem_signed = ldq_uop_10_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_27_mem_signed = ldq_uop_10_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_uses_ldq; // @[lsu.scala:219:36] wire l_uop_10_uses_ldq = ldq_uop_10_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_27_uses_ldq = ldq_uop_10_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_uses_stq; // @[lsu.scala:219:36] wire l_uop_10_uses_stq = ldq_uop_10_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_27_uses_stq = ldq_uop_10_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_unique; // @[lsu.scala:219:36] wire l_uop_10_is_unique = ldq_uop_10_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_unique = ldq_uop_10_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_10_flush_on_commit = ldq_uop_10_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_27_flush_on_commit = ldq_uop_10_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_10_csr_cmd = ldq_uop_10_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_csr_cmd = ldq_uop_10_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_10_ldst_is_rs1 = ldq_uop_10_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_27_ldst_is_rs1 = ldq_uop_10_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_10_ldst = ldq_uop_10_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_ldst = ldq_uop_10_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_10_lrs1 = ldq_uop_10_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_lrs1 = ldq_uop_10_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_10_lrs2 = ldq_uop_10_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_lrs2 = ldq_uop_10_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_10_lrs3 = ldq_uop_10_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_lrs3 = ldq_uop_10_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_10_dst_rtype = ldq_uop_10_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_dst_rtype = ldq_uop_10_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_10_lrs1_rtype = ldq_uop_10_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_lrs1_rtype = ldq_uop_10_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_10_lrs2_rtype = ldq_uop_10_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_lrs2_rtype = ldq_uop_10_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_frs3_en; // @[lsu.scala:219:36] wire l_uop_10_frs3_en = ldq_uop_10_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_27_frs3_en = ldq_uop_10_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fcn_dw; // @[lsu.scala:219:36] wire l_uop_10_fcn_dw = ldq_uop_10_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_27_fcn_dw = ldq_uop_10_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_10_fcn_op = ldq_uop_10_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_fcn_op = ldq_uop_10_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_val; // @[lsu.scala:219:36] wire l_uop_10_fp_val = ldq_uop_10_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_val = ldq_uop_10_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_10_fp_rm = ldq_uop_10_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_fp_rm = ldq_uop_10_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_10_fp_typ = ldq_uop_10_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_fp_typ = ldq_uop_10_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_10_xcpt_pf_if = ldq_uop_10_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_xcpt_pf_if = ldq_uop_10_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_10_xcpt_ae_if = ldq_uop_10_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_xcpt_ae_if = ldq_uop_10_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_10_xcpt_ma_if = ldq_uop_10_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_xcpt_ma_if = ldq_uop_10_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_10_bp_debug_if = ldq_uop_10_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_bp_debug_if = ldq_uop_10_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_10_bp_xcpt_if = ldq_uop_10_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_bp_xcpt_if = ldq_uop_10_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_10_debug_fsrc = ldq_uop_10_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_debug_fsrc = ldq_uop_10_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_10_debug_tsrc = ldq_uop_10_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_debug_tsrc = ldq_uop_10_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_11_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_11_inst = ldq_uop_11_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_28_inst = ldq_uop_11_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_11_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_11_debug_inst = ldq_uop_11_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_28_debug_inst = ldq_uop_11_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_rvc; // @[lsu.scala:219:36] wire l_uop_11_is_rvc = ldq_uop_11_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_rvc = ldq_uop_11_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_11_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_11_debug_pc = ldq_uop_11_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_28_debug_pc = ldq_uop_11_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_0; // @[lsu.scala:219:36] wire l_uop_11_iq_type_0 = ldq_uop_11_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_0 = ldq_uop_11_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_1; // @[lsu.scala:219:36] wire l_uop_11_iq_type_1 = ldq_uop_11_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_1 = ldq_uop_11_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_2; // @[lsu.scala:219:36] wire l_uop_11_iq_type_2 = ldq_uop_11_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_2 = ldq_uop_11_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_3; // @[lsu.scala:219:36] wire l_uop_11_iq_type_3 = ldq_uop_11_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_3 = ldq_uop_11_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_0; // @[lsu.scala:219:36] wire l_uop_11_fu_code_0 = ldq_uop_11_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_0 = ldq_uop_11_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_1; // @[lsu.scala:219:36] wire l_uop_11_fu_code_1 = ldq_uop_11_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_1 = ldq_uop_11_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_2; // @[lsu.scala:219:36] wire l_uop_11_fu_code_2 = ldq_uop_11_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_2 = ldq_uop_11_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_3; // @[lsu.scala:219:36] wire l_uop_11_fu_code_3 = ldq_uop_11_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_3 = ldq_uop_11_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_4; // @[lsu.scala:219:36] wire l_uop_11_fu_code_4 = ldq_uop_11_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_4 = ldq_uop_11_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_5; // @[lsu.scala:219:36] wire l_uop_11_fu_code_5 = ldq_uop_11_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_5 = ldq_uop_11_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_6; // @[lsu.scala:219:36] wire l_uop_11_fu_code_6 = ldq_uop_11_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_6 = ldq_uop_11_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_7; // @[lsu.scala:219:36] wire l_uop_11_fu_code_7 = ldq_uop_11_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_7 = ldq_uop_11_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_8; // @[lsu.scala:219:36] wire l_uop_11_fu_code_8 = ldq_uop_11_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_8 = ldq_uop_11_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_9; // @[lsu.scala:219:36] wire l_uop_11_fu_code_9 = ldq_uop_11_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_9 = ldq_uop_11_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_issued; // @[lsu.scala:219:36] wire l_uop_11_iw_issued = ldq_uop_11_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_issued = ldq_uop_11_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_11_iw_issued_partial_agen = ldq_uop_11_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_issued_partial_agen = ldq_uop_11_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_11_iw_issued_partial_dgen = ldq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_issued_partial_dgen = ldq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_11_iw_p1_speculative_child = ldq_uop_11_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_iw_p1_speculative_child = ldq_uop_11_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_11_iw_p2_speculative_child = ldq_uop_11_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_iw_p2_speculative_child = ldq_uop_11_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_11_iw_p1_bypass_hint = ldq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_p1_bypass_hint = ldq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_11_iw_p2_bypass_hint = ldq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_p2_bypass_hint = ldq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_11_iw_p3_bypass_hint = ldq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_p3_bypass_hint = ldq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_11_dis_col_sel = ldq_uop_11_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_dis_col_sel = ldq_uop_11_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_11_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_11_br_mask = ldq_uop_11_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_28_br_mask = ldq_uop_11_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_11_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_11_br_tag = ldq_uop_11_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_28_br_tag = ldq_uop_11_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_11_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_11_br_type = ldq_uop_11_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_28_br_type = ldq_uop_11_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_sfb; // @[lsu.scala:219:36] wire l_uop_11_is_sfb = ldq_uop_11_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_sfb = ldq_uop_11_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_fence; // @[lsu.scala:219:36] wire l_uop_11_is_fence = ldq_uop_11_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_fence = ldq_uop_11_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_fencei; // @[lsu.scala:219:36] wire l_uop_11_is_fencei = ldq_uop_11_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_fencei = ldq_uop_11_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_sfence; // @[lsu.scala:219:36] wire l_uop_11_is_sfence = ldq_uop_11_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_sfence = ldq_uop_11_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_amo; // @[lsu.scala:219:36] wire l_uop_11_is_amo = ldq_uop_11_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_amo = ldq_uop_11_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_eret; // @[lsu.scala:219:36] wire l_uop_11_is_eret = ldq_uop_11_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_eret = ldq_uop_11_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_11_is_sys_pc2epc = ldq_uop_11_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_sys_pc2epc = ldq_uop_11_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_rocc; // @[lsu.scala:219:36] wire l_uop_11_is_rocc = ldq_uop_11_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_rocc = ldq_uop_11_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_mov; // @[lsu.scala:219:36] wire l_uop_11_is_mov = ldq_uop_11_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_mov = ldq_uop_11_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_11_ftq_idx = ldq_uop_11_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_ftq_idx = ldq_uop_11_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_edge_inst; // @[lsu.scala:219:36] wire l_uop_11_edge_inst = ldq_uop_11_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_28_edge_inst = ldq_uop_11_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_11_pc_lob = ldq_uop_11_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_pc_lob = ldq_uop_11_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_taken; // @[lsu.scala:219:36] wire l_uop_11_taken = ldq_uop_11_taken; // @[lsu.scala:219:36, :1191:37] wire uop_28_taken = ldq_uop_11_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_imm_rename; // @[lsu.scala:219:36] wire l_uop_11_imm_rename = ldq_uop_11_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_28_imm_rename = ldq_uop_11_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_11_imm_sel = ldq_uop_11_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_imm_sel = ldq_uop_11_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_11_pimm = ldq_uop_11_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_pimm = ldq_uop_11_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_11_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_11_imm_packed = ldq_uop_11_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_28_imm_packed = ldq_uop_11_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_11_op1_sel = ldq_uop_11_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_op1_sel = ldq_uop_11_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_11_op2_sel = ldq_uop_11_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_op2_sel = ldq_uop_11_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ldst = ldq_uop_11_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ldst = ldq_uop_11_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_wen = ldq_uop_11_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_wen = ldq_uop_11_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ren1 = ldq_uop_11_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ren1 = ldq_uop_11_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ren2 = ldq_uop_11_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ren2 = ldq_uop_11_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ren3 = ldq_uop_11_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ren3 = ldq_uop_11_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_swap12 = ldq_uop_11_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_swap12 = ldq_uop_11_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_swap23 = ldq_uop_11_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_swap23 = ldq_uop_11_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_11_fp_ctrl_typeTagIn = ldq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_fp_ctrl_typeTagIn = ldq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_11_fp_ctrl_typeTagOut = ldq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_fp_ctrl_typeTagOut = ldq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_fromint = ldq_uop_11_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_fromint = ldq_uop_11_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_toint = ldq_uop_11_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_toint = ldq_uop_11_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_fastpipe = ldq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_fastpipe = ldq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_fma = ldq_uop_11_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_fma = ldq_uop_11_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_div = ldq_uop_11_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_div = ldq_uop_11_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_sqrt = ldq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_sqrt = ldq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_wflags = ldq_uop_11_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_wflags = ldq_uop_11_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_vec = ldq_uop_11_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_vec = ldq_uop_11_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_11_rob_idx = ldq_uop_11_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_rob_idx = ldq_uop_11_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_11_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_11_ldq_idx = ldq_uop_11_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_28_ldq_idx = ldq_uop_11_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_11_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_11_stq_idx = ldq_uop_11_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_28_stq_idx = ldq_uop_11_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_11_rxq_idx = ldq_uop_11_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_rxq_idx = ldq_uop_11_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_11_pdst = ldq_uop_11_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_pdst = ldq_uop_11_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_11_prs1 = ldq_uop_11_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_prs1 = ldq_uop_11_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_11_prs2 = ldq_uop_11_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_prs2 = ldq_uop_11_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_11_prs3 = ldq_uop_11_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_prs3 = ldq_uop_11_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_11_ppred = ldq_uop_11_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_ppred = ldq_uop_11_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_prs1_busy; // @[lsu.scala:219:36] wire l_uop_11_prs1_busy = ldq_uop_11_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_prs1_busy = ldq_uop_11_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_prs2_busy; // @[lsu.scala:219:36] wire l_uop_11_prs2_busy = ldq_uop_11_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_prs2_busy = ldq_uop_11_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_prs3_busy; // @[lsu.scala:219:36] wire l_uop_11_prs3_busy = ldq_uop_11_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_prs3_busy = ldq_uop_11_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_ppred_busy; // @[lsu.scala:219:36] wire l_uop_11_ppred_busy = ldq_uop_11_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_ppred_busy = ldq_uop_11_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_11_stale_pdst = ldq_uop_11_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_stale_pdst = ldq_uop_11_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_exception; // @[lsu.scala:219:36] wire l_uop_11_exception = ldq_uop_11_exception; // @[lsu.scala:219:36, :1191:37] wire uop_28_exception = ldq_uop_11_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_11_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_11_exc_cause = ldq_uop_11_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_28_exc_cause = ldq_uop_11_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_11_mem_cmd = ldq_uop_11_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_mem_cmd = ldq_uop_11_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_11_mem_size = ldq_uop_11_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_mem_size = ldq_uop_11_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_mem_signed; // @[lsu.scala:219:36] wire l_uop_11_mem_signed = ldq_uop_11_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_28_mem_signed = ldq_uop_11_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_uses_ldq; // @[lsu.scala:219:36] wire l_uop_11_uses_ldq = ldq_uop_11_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_28_uses_ldq = ldq_uop_11_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_uses_stq; // @[lsu.scala:219:36] wire l_uop_11_uses_stq = ldq_uop_11_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_28_uses_stq = ldq_uop_11_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_unique; // @[lsu.scala:219:36] wire l_uop_11_is_unique = ldq_uop_11_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_unique = ldq_uop_11_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_11_flush_on_commit = ldq_uop_11_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_28_flush_on_commit = ldq_uop_11_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_11_csr_cmd = ldq_uop_11_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_csr_cmd = ldq_uop_11_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_11_ldst_is_rs1 = ldq_uop_11_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_28_ldst_is_rs1 = ldq_uop_11_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_11_ldst = ldq_uop_11_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_ldst = ldq_uop_11_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_11_lrs1 = ldq_uop_11_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_lrs1 = ldq_uop_11_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_11_lrs2 = ldq_uop_11_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_lrs2 = ldq_uop_11_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_11_lrs3 = ldq_uop_11_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_lrs3 = ldq_uop_11_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_11_dst_rtype = ldq_uop_11_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_dst_rtype = ldq_uop_11_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_11_lrs1_rtype = ldq_uop_11_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_lrs1_rtype = ldq_uop_11_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_11_lrs2_rtype = ldq_uop_11_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_lrs2_rtype = ldq_uop_11_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_frs3_en; // @[lsu.scala:219:36] wire l_uop_11_frs3_en = ldq_uop_11_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_28_frs3_en = ldq_uop_11_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fcn_dw; // @[lsu.scala:219:36] wire l_uop_11_fcn_dw = ldq_uop_11_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_28_fcn_dw = ldq_uop_11_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_11_fcn_op = ldq_uop_11_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_fcn_op = ldq_uop_11_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_val; // @[lsu.scala:219:36] wire l_uop_11_fp_val = ldq_uop_11_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_val = ldq_uop_11_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_11_fp_rm = ldq_uop_11_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_fp_rm = ldq_uop_11_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_11_fp_typ = ldq_uop_11_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_fp_typ = ldq_uop_11_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_11_xcpt_pf_if = ldq_uop_11_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_xcpt_pf_if = ldq_uop_11_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_11_xcpt_ae_if = ldq_uop_11_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_xcpt_ae_if = ldq_uop_11_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_11_xcpt_ma_if = ldq_uop_11_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_xcpt_ma_if = ldq_uop_11_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_11_bp_debug_if = ldq_uop_11_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_bp_debug_if = ldq_uop_11_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_11_bp_xcpt_if = ldq_uop_11_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_bp_xcpt_if = ldq_uop_11_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_11_debug_fsrc = ldq_uop_11_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_debug_fsrc = ldq_uop_11_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_11_debug_tsrc = ldq_uop_11_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_debug_tsrc = ldq_uop_11_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_12_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_12_inst = ldq_uop_12_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_29_inst = ldq_uop_12_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_12_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_12_debug_inst = ldq_uop_12_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_29_debug_inst = ldq_uop_12_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_rvc; // @[lsu.scala:219:36] wire l_uop_12_is_rvc = ldq_uop_12_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_rvc = ldq_uop_12_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_12_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_12_debug_pc = ldq_uop_12_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_29_debug_pc = ldq_uop_12_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_0; // @[lsu.scala:219:36] wire l_uop_12_iq_type_0 = ldq_uop_12_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_0 = ldq_uop_12_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_1; // @[lsu.scala:219:36] wire l_uop_12_iq_type_1 = ldq_uop_12_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_1 = ldq_uop_12_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_2; // @[lsu.scala:219:36] wire l_uop_12_iq_type_2 = ldq_uop_12_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_2 = ldq_uop_12_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_3; // @[lsu.scala:219:36] wire l_uop_12_iq_type_3 = ldq_uop_12_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_3 = ldq_uop_12_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_0; // @[lsu.scala:219:36] wire l_uop_12_fu_code_0 = ldq_uop_12_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_0 = ldq_uop_12_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_1; // @[lsu.scala:219:36] wire l_uop_12_fu_code_1 = ldq_uop_12_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_1 = ldq_uop_12_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_2; // @[lsu.scala:219:36] wire l_uop_12_fu_code_2 = ldq_uop_12_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_2 = ldq_uop_12_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_3; // @[lsu.scala:219:36] wire l_uop_12_fu_code_3 = ldq_uop_12_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_3 = ldq_uop_12_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_4; // @[lsu.scala:219:36] wire l_uop_12_fu_code_4 = ldq_uop_12_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_4 = ldq_uop_12_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_5; // @[lsu.scala:219:36] wire l_uop_12_fu_code_5 = ldq_uop_12_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_5 = ldq_uop_12_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_6; // @[lsu.scala:219:36] wire l_uop_12_fu_code_6 = ldq_uop_12_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_6 = ldq_uop_12_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_7; // @[lsu.scala:219:36] wire l_uop_12_fu_code_7 = ldq_uop_12_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_7 = ldq_uop_12_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_8; // @[lsu.scala:219:36] wire l_uop_12_fu_code_8 = ldq_uop_12_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_8 = ldq_uop_12_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_9; // @[lsu.scala:219:36] wire l_uop_12_fu_code_9 = ldq_uop_12_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_9 = ldq_uop_12_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_issued; // @[lsu.scala:219:36] wire l_uop_12_iw_issued = ldq_uop_12_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_issued = ldq_uop_12_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_12_iw_issued_partial_agen = ldq_uop_12_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_issued_partial_agen = ldq_uop_12_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_12_iw_issued_partial_dgen = ldq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_issued_partial_dgen = ldq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_12_iw_p1_speculative_child = ldq_uop_12_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_iw_p1_speculative_child = ldq_uop_12_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_12_iw_p2_speculative_child = ldq_uop_12_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_iw_p2_speculative_child = ldq_uop_12_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_12_iw_p1_bypass_hint = ldq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_p1_bypass_hint = ldq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_12_iw_p2_bypass_hint = ldq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_p2_bypass_hint = ldq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_12_iw_p3_bypass_hint = ldq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_p3_bypass_hint = ldq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_12_dis_col_sel = ldq_uop_12_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_dis_col_sel = ldq_uop_12_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_12_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_12_br_mask = ldq_uop_12_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_29_br_mask = ldq_uop_12_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_12_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_12_br_tag = ldq_uop_12_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_29_br_tag = ldq_uop_12_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_12_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_12_br_type = ldq_uop_12_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_29_br_type = ldq_uop_12_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_sfb; // @[lsu.scala:219:36] wire l_uop_12_is_sfb = ldq_uop_12_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_sfb = ldq_uop_12_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_fence; // @[lsu.scala:219:36] wire l_uop_12_is_fence = ldq_uop_12_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_fence = ldq_uop_12_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_fencei; // @[lsu.scala:219:36] wire l_uop_12_is_fencei = ldq_uop_12_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_fencei = ldq_uop_12_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_sfence; // @[lsu.scala:219:36] wire l_uop_12_is_sfence = ldq_uop_12_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_sfence = ldq_uop_12_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_amo; // @[lsu.scala:219:36] wire l_uop_12_is_amo = ldq_uop_12_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_amo = ldq_uop_12_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_eret; // @[lsu.scala:219:36] wire l_uop_12_is_eret = ldq_uop_12_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_eret = ldq_uop_12_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_12_is_sys_pc2epc = ldq_uop_12_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_sys_pc2epc = ldq_uop_12_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_rocc; // @[lsu.scala:219:36] wire l_uop_12_is_rocc = ldq_uop_12_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_rocc = ldq_uop_12_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_mov; // @[lsu.scala:219:36] wire l_uop_12_is_mov = ldq_uop_12_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_mov = ldq_uop_12_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_12_ftq_idx = ldq_uop_12_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_ftq_idx = ldq_uop_12_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_edge_inst; // @[lsu.scala:219:36] wire l_uop_12_edge_inst = ldq_uop_12_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_29_edge_inst = ldq_uop_12_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_12_pc_lob = ldq_uop_12_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_pc_lob = ldq_uop_12_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_taken; // @[lsu.scala:219:36] wire l_uop_12_taken = ldq_uop_12_taken; // @[lsu.scala:219:36, :1191:37] wire uop_29_taken = ldq_uop_12_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_imm_rename; // @[lsu.scala:219:36] wire l_uop_12_imm_rename = ldq_uop_12_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_29_imm_rename = ldq_uop_12_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_12_imm_sel = ldq_uop_12_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_imm_sel = ldq_uop_12_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_12_pimm = ldq_uop_12_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_pimm = ldq_uop_12_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_12_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_12_imm_packed = ldq_uop_12_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_29_imm_packed = ldq_uop_12_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_12_op1_sel = ldq_uop_12_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_op1_sel = ldq_uop_12_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_12_op2_sel = ldq_uop_12_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_op2_sel = ldq_uop_12_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ldst = ldq_uop_12_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ldst = ldq_uop_12_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_wen = ldq_uop_12_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_wen = ldq_uop_12_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ren1 = ldq_uop_12_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ren1 = ldq_uop_12_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ren2 = ldq_uop_12_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ren2 = ldq_uop_12_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ren3 = ldq_uop_12_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ren3 = ldq_uop_12_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_swap12 = ldq_uop_12_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_swap12 = ldq_uop_12_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_swap23 = ldq_uop_12_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_swap23 = ldq_uop_12_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_12_fp_ctrl_typeTagIn = ldq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_fp_ctrl_typeTagIn = ldq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_12_fp_ctrl_typeTagOut = ldq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_fp_ctrl_typeTagOut = ldq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_fromint = ldq_uop_12_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_fromint = ldq_uop_12_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_toint = ldq_uop_12_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_toint = ldq_uop_12_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_fastpipe = ldq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_fastpipe = ldq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_fma = ldq_uop_12_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_fma = ldq_uop_12_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_div = ldq_uop_12_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_div = ldq_uop_12_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_sqrt = ldq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_sqrt = ldq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_wflags = ldq_uop_12_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_wflags = ldq_uop_12_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_vec = ldq_uop_12_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_vec = ldq_uop_12_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_12_rob_idx = ldq_uop_12_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_rob_idx = ldq_uop_12_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_12_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_12_ldq_idx = ldq_uop_12_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_29_ldq_idx = ldq_uop_12_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_12_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_12_stq_idx = ldq_uop_12_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_29_stq_idx = ldq_uop_12_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_12_rxq_idx = ldq_uop_12_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_rxq_idx = ldq_uop_12_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_12_pdst = ldq_uop_12_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_pdst = ldq_uop_12_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_12_prs1 = ldq_uop_12_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_prs1 = ldq_uop_12_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_12_prs2 = ldq_uop_12_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_prs2 = ldq_uop_12_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_12_prs3 = ldq_uop_12_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_prs3 = ldq_uop_12_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_12_ppred = ldq_uop_12_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_ppred = ldq_uop_12_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_prs1_busy; // @[lsu.scala:219:36] wire l_uop_12_prs1_busy = ldq_uop_12_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_prs1_busy = ldq_uop_12_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_prs2_busy; // @[lsu.scala:219:36] wire l_uop_12_prs2_busy = ldq_uop_12_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_prs2_busy = ldq_uop_12_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_prs3_busy; // @[lsu.scala:219:36] wire l_uop_12_prs3_busy = ldq_uop_12_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_prs3_busy = ldq_uop_12_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_ppred_busy; // @[lsu.scala:219:36] wire l_uop_12_ppred_busy = ldq_uop_12_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_ppred_busy = ldq_uop_12_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_12_stale_pdst = ldq_uop_12_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_stale_pdst = ldq_uop_12_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_exception; // @[lsu.scala:219:36] wire l_uop_12_exception = ldq_uop_12_exception; // @[lsu.scala:219:36, :1191:37] wire uop_29_exception = ldq_uop_12_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_12_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_12_exc_cause = ldq_uop_12_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_29_exc_cause = ldq_uop_12_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_12_mem_cmd = ldq_uop_12_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_mem_cmd = ldq_uop_12_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_12_mem_size = ldq_uop_12_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_mem_size = ldq_uop_12_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_mem_signed; // @[lsu.scala:219:36] wire l_uop_12_mem_signed = ldq_uop_12_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_29_mem_signed = ldq_uop_12_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_uses_ldq; // @[lsu.scala:219:36] wire l_uop_12_uses_ldq = ldq_uop_12_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_29_uses_ldq = ldq_uop_12_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_uses_stq; // @[lsu.scala:219:36] wire l_uop_12_uses_stq = ldq_uop_12_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_29_uses_stq = ldq_uop_12_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_unique; // @[lsu.scala:219:36] wire l_uop_12_is_unique = ldq_uop_12_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_unique = ldq_uop_12_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_12_flush_on_commit = ldq_uop_12_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_29_flush_on_commit = ldq_uop_12_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_12_csr_cmd = ldq_uop_12_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_csr_cmd = ldq_uop_12_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_12_ldst_is_rs1 = ldq_uop_12_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_29_ldst_is_rs1 = ldq_uop_12_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_12_ldst = ldq_uop_12_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_ldst = ldq_uop_12_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_12_lrs1 = ldq_uop_12_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_lrs1 = ldq_uop_12_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_12_lrs2 = ldq_uop_12_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_lrs2 = ldq_uop_12_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_12_lrs3 = ldq_uop_12_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_lrs3 = ldq_uop_12_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_12_dst_rtype = ldq_uop_12_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_dst_rtype = ldq_uop_12_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_12_lrs1_rtype = ldq_uop_12_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_lrs1_rtype = ldq_uop_12_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_12_lrs2_rtype = ldq_uop_12_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_lrs2_rtype = ldq_uop_12_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_frs3_en; // @[lsu.scala:219:36] wire l_uop_12_frs3_en = ldq_uop_12_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_29_frs3_en = ldq_uop_12_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fcn_dw; // @[lsu.scala:219:36] wire l_uop_12_fcn_dw = ldq_uop_12_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_29_fcn_dw = ldq_uop_12_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_12_fcn_op = ldq_uop_12_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_fcn_op = ldq_uop_12_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_val; // @[lsu.scala:219:36] wire l_uop_12_fp_val = ldq_uop_12_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_val = ldq_uop_12_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_12_fp_rm = ldq_uop_12_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_fp_rm = ldq_uop_12_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_12_fp_typ = ldq_uop_12_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_fp_typ = ldq_uop_12_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_12_xcpt_pf_if = ldq_uop_12_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_xcpt_pf_if = ldq_uop_12_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_12_xcpt_ae_if = ldq_uop_12_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_xcpt_ae_if = ldq_uop_12_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_12_xcpt_ma_if = ldq_uop_12_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_xcpt_ma_if = ldq_uop_12_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_12_bp_debug_if = ldq_uop_12_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_bp_debug_if = ldq_uop_12_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_12_bp_xcpt_if = ldq_uop_12_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_bp_xcpt_if = ldq_uop_12_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_12_debug_fsrc = ldq_uop_12_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_debug_fsrc = ldq_uop_12_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_12_debug_tsrc = ldq_uop_12_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_debug_tsrc = ldq_uop_12_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_13_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_13_inst = ldq_uop_13_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_30_inst = ldq_uop_13_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_13_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_13_debug_inst = ldq_uop_13_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_30_debug_inst = ldq_uop_13_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_rvc; // @[lsu.scala:219:36] wire l_uop_13_is_rvc = ldq_uop_13_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_rvc = ldq_uop_13_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_13_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_13_debug_pc = ldq_uop_13_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_30_debug_pc = ldq_uop_13_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_0; // @[lsu.scala:219:36] wire l_uop_13_iq_type_0 = ldq_uop_13_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_0 = ldq_uop_13_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_1; // @[lsu.scala:219:36] wire l_uop_13_iq_type_1 = ldq_uop_13_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_1 = ldq_uop_13_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_2; // @[lsu.scala:219:36] wire l_uop_13_iq_type_2 = ldq_uop_13_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_2 = ldq_uop_13_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_3; // @[lsu.scala:219:36] wire l_uop_13_iq_type_3 = ldq_uop_13_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_3 = ldq_uop_13_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_0; // @[lsu.scala:219:36] wire l_uop_13_fu_code_0 = ldq_uop_13_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_0 = ldq_uop_13_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_1; // @[lsu.scala:219:36] wire l_uop_13_fu_code_1 = ldq_uop_13_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_1 = ldq_uop_13_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_2; // @[lsu.scala:219:36] wire l_uop_13_fu_code_2 = ldq_uop_13_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_2 = ldq_uop_13_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_3; // @[lsu.scala:219:36] wire l_uop_13_fu_code_3 = ldq_uop_13_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_3 = ldq_uop_13_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_4; // @[lsu.scala:219:36] wire l_uop_13_fu_code_4 = ldq_uop_13_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_4 = ldq_uop_13_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_5; // @[lsu.scala:219:36] wire l_uop_13_fu_code_5 = ldq_uop_13_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_5 = ldq_uop_13_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_6; // @[lsu.scala:219:36] wire l_uop_13_fu_code_6 = ldq_uop_13_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_6 = ldq_uop_13_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_7; // @[lsu.scala:219:36] wire l_uop_13_fu_code_7 = ldq_uop_13_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_7 = ldq_uop_13_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_8; // @[lsu.scala:219:36] wire l_uop_13_fu_code_8 = ldq_uop_13_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_8 = ldq_uop_13_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_9; // @[lsu.scala:219:36] wire l_uop_13_fu_code_9 = ldq_uop_13_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_9 = ldq_uop_13_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_issued; // @[lsu.scala:219:36] wire l_uop_13_iw_issued = ldq_uop_13_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_issued = ldq_uop_13_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_13_iw_issued_partial_agen = ldq_uop_13_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_issued_partial_agen = ldq_uop_13_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_13_iw_issued_partial_dgen = ldq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_issued_partial_dgen = ldq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_13_iw_p1_speculative_child = ldq_uop_13_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_iw_p1_speculative_child = ldq_uop_13_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_13_iw_p2_speculative_child = ldq_uop_13_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_iw_p2_speculative_child = ldq_uop_13_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_13_iw_p1_bypass_hint = ldq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_p1_bypass_hint = ldq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_13_iw_p2_bypass_hint = ldq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_p2_bypass_hint = ldq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_13_iw_p3_bypass_hint = ldq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_p3_bypass_hint = ldq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_13_dis_col_sel = ldq_uop_13_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_dis_col_sel = ldq_uop_13_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_13_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_13_br_mask = ldq_uop_13_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_30_br_mask = ldq_uop_13_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_13_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_13_br_tag = ldq_uop_13_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_30_br_tag = ldq_uop_13_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_13_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_13_br_type = ldq_uop_13_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_30_br_type = ldq_uop_13_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_sfb; // @[lsu.scala:219:36] wire l_uop_13_is_sfb = ldq_uop_13_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_sfb = ldq_uop_13_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_fence; // @[lsu.scala:219:36] wire l_uop_13_is_fence = ldq_uop_13_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_fence = ldq_uop_13_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_fencei; // @[lsu.scala:219:36] wire l_uop_13_is_fencei = ldq_uop_13_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_fencei = ldq_uop_13_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_sfence; // @[lsu.scala:219:36] wire l_uop_13_is_sfence = ldq_uop_13_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_sfence = ldq_uop_13_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_amo; // @[lsu.scala:219:36] wire l_uop_13_is_amo = ldq_uop_13_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_amo = ldq_uop_13_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_eret; // @[lsu.scala:219:36] wire l_uop_13_is_eret = ldq_uop_13_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_eret = ldq_uop_13_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_13_is_sys_pc2epc = ldq_uop_13_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_sys_pc2epc = ldq_uop_13_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_rocc; // @[lsu.scala:219:36] wire l_uop_13_is_rocc = ldq_uop_13_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_rocc = ldq_uop_13_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_mov; // @[lsu.scala:219:36] wire l_uop_13_is_mov = ldq_uop_13_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_mov = ldq_uop_13_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_13_ftq_idx = ldq_uop_13_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_ftq_idx = ldq_uop_13_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_edge_inst; // @[lsu.scala:219:36] wire l_uop_13_edge_inst = ldq_uop_13_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_30_edge_inst = ldq_uop_13_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_13_pc_lob = ldq_uop_13_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_pc_lob = ldq_uop_13_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_taken; // @[lsu.scala:219:36] wire l_uop_13_taken = ldq_uop_13_taken; // @[lsu.scala:219:36, :1191:37] wire uop_30_taken = ldq_uop_13_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_imm_rename; // @[lsu.scala:219:36] wire l_uop_13_imm_rename = ldq_uop_13_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_30_imm_rename = ldq_uop_13_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_13_imm_sel = ldq_uop_13_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_imm_sel = ldq_uop_13_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_13_pimm = ldq_uop_13_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_pimm = ldq_uop_13_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_13_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_13_imm_packed = ldq_uop_13_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_30_imm_packed = ldq_uop_13_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_13_op1_sel = ldq_uop_13_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_op1_sel = ldq_uop_13_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_13_op2_sel = ldq_uop_13_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_op2_sel = ldq_uop_13_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ldst = ldq_uop_13_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ldst = ldq_uop_13_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_wen = ldq_uop_13_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_wen = ldq_uop_13_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ren1 = ldq_uop_13_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ren1 = ldq_uop_13_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ren2 = ldq_uop_13_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ren2 = ldq_uop_13_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ren3 = ldq_uop_13_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ren3 = ldq_uop_13_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_swap12 = ldq_uop_13_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_swap12 = ldq_uop_13_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_swap23 = ldq_uop_13_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_swap23 = ldq_uop_13_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_13_fp_ctrl_typeTagIn = ldq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_fp_ctrl_typeTagIn = ldq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_13_fp_ctrl_typeTagOut = ldq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_fp_ctrl_typeTagOut = ldq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_fromint = ldq_uop_13_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_fromint = ldq_uop_13_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_toint = ldq_uop_13_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_toint = ldq_uop_13_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_fastpipe = ldq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_fastpipe = ldq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_fma = ldq_uop_13_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_fma = ldq_uop_13_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_div = ldq_uop_13_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_div = ldq_uop_13_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_sqrt = ldq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_sqrt = ldq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_wflags = ldq_uop_13_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_wflags = ldq_uop_13_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_vec = ldq_uop_13_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_vec = ldq_uop_13_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_13_rob_idx = ldq_uop_13_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_rob_idx = ldq_uop_13_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_13_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_13_ldq_idx = ldq_uop_13_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_30_ldq_idx = ldq_uop_13_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_13_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_13_stq_idx = ldq_uop_13_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_30_stq_idx = ldq_uop_13_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_13_rxq_idx = ldq_uop_13_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_rxq_idx = ldq_uop_13_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_13_pdst = ldq_uop_13_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_pdst = ldq_uop_13_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_13_prs1 = ldq_uop_13_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_prs1 = ldq_uop_13_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_13_prs2 = ldq_uop_13_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_prs2 = ldq_uop_13_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_13_prs3 = ldq_uop_13_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_prs3 = ldq_uop_13_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_13_ppred = ldq_uop_13_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_ppred = ldq_uop_13_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_prs1_busy; // @[lsu.scala:219:36] wire l_uop_13_prs1_busy = ldq_uop_13_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_prs1_busy = ldq_uop_13_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_prs2_busy; // @[lsu.scala:219:36] wire l_uop_13_prs2_busy = ldq_uop_13_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_prs2_busy = ldq_uop_13_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_prs3_busy; // @[lsu.scala:219:36] wire l_uop_13_prs3_busy = ldq_uop_13_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_prs3_busy = ldq_uop_13_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_ppred_busy; // @[lsu.scala:219:36] wire l_uop_13_ppred_busy = ldq_uop_13_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_ppred_busy = ldq_uop_13_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_13_stale_pdst = ldq_uop_13_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_stale_pdst = ldq_uop_13_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_exception; // @[lsu.scala:219:36] wire l_uop_13_exception = ldq_uop_13_exception; // @[lsu.scala:219:36, :1191:37] wire uop_30_exception = ldq_uop_13_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_13_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_13_exc_cause = ldq_uop_13_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_30_exc_cause = ldq_uop_13_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_13_mem_cmd = ldq_uop_13_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_mem_cmd = ldq_uop_13_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_13_mem_size = ldq_uop_13_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_mem_size = ldq_uop_13_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_mem_signed; // @[lsu.scala:219:36] wire l_uop_13_mem_signed = ldq_uop_13_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_30_mem_signed = ldq_uop_13_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_uses_ldq; // @[lsu.scala:219:36] wire l_uop_13_uses_ldq = ldq_uop_13_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_30_uses_ldq = ldq_uop_13_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_uses_stq; // @[lsu.scala:219:36] wire l_uop_13_uses_stq = ldq_uop_13_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_30_uses_stq = ldq_uop_13_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_unique; // @[lsu.scala:219:36] wire l_uop_13_is_unique = ldq_uop_13_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_unique = ldq_uop_13_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_13_flush_on_commit = ldq_uop_13_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_30_flush_on_commit = ldq_uop_13_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_13_csr_cmd = ldq_uop_13_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_csr_cmd = ldq_uop_13_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_13_ldst_is_rs1 = ldq_uop_13_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_30_ldst_is_rs1 = ldq_uop_13_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_13_ldst = ldq_uop_13_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_ldst = ldq_uop_13_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_13_lrs1 = ldq_uop_13_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_lrs1 = ldq_uop_13_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_13_lrs2 = ldq_uop_13_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_lrs2 = ldq_uop_13_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_13_lrs3 = ldq_uop_13_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_lrs3 = ldq_uop_13_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_13_dst_rtype = ldq_uop_13_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_dst_rtype = ldq_uop_13_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_13_lrs1_rtype = ldq_uop_13_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_lrs1_rtype = ldq_uop_13_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_13_lrs2_rtype = ldq_uop_13_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_lrs2_rtype = ldq_uop_13_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_frs3_en; // @[lsu.scala:219:36] wire l_uop_13_frs3_en = ldq_uop_13_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_30_frs3_en = ldq_uop_13_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fcn_dw; // @[lsu.scala:219:36] wire l_uop_13_fcn_dw = ldq_uop_13_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_30_fcn_dw = ldq_uop_13_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_13_fcn_op = ldq_uop_13_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_fcn_op = ldq_uop_13_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_val; // @[lsu.scala:219:36] wire l_uop_13_fp_val = ldq_uop_13_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_val = ldq_uop_13_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_13_fp_rm = ldq_uop_13_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_fp_rm = ldq_uop_13_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_13_fp_typ = ldq_uop_13_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_fp_typ = ldq_uop_13_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_13_xcpt_pf_if = ldq_uop_13_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_xcpt_pf_if = ldq_uop_13_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_13_xcpt_ae_if = ldq_uop_13_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_xcpt_ae_if = ldq_uop_13_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_13_xcpt_ma_if = ldq_uop_13_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_xcpt_ma_if = ldq_uop_13_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_13_bp_debug_if = ldq_uop_13_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_bp_debug_if = ldq_uop_13_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_13_bp_xcpt_if = ldq_uop_13_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_bp_xcpt_if = ldq_uop_13_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_13_debug_fsrc = ldq_uop_13_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_debug_fsrc = ldq_uop_13_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_13_debug_tsrc = ldq_uop_13_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_debug_tsrc = ldq_uop_13_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_14_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_14_inst = ldq_uop_14_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_31_inst = ldq_uop_14_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_14_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_14_debug_inst = ldq_uop_14_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_31_debug_inst = ldq_uop_14_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_rvc; // @[lsu.scala:219:36] wire l_uop_14_is_rvc = ldq_uop_14_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_rvc = ldq_uop_14_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_14_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_14_debug_pc = ldq_uop_14_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_31_debug_pc = ldq_uop_14_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_0; // @[lsu.scala:219:36] wire l_uop_14_iq_type_0 = ldq_uop_14_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_0 = ldq_uop_14_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_1; // @[lsu.scala:219:36] wire l_uop_14_iq_type_1 = ldq_uop_14_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_1 = ldq_uop_14_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_2; // @[lsu.scala:219:36] wire l_uop_14_iq_type_2 = ldq_uop_14_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_2 = ldq_uop_14_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_3; // @[lsu.scala:219:36] wire l_uop_14_iq_type_3 = ldq_uop_14_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_3 = ldq_uop_14_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_0; // @[lsu.scala:219:36] wire l_uop_14_fu_code_0 = ldq_uop_14_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_0 = ldq_uop_14_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_1; // @[lsu.scala:219:36] wire l_uop_14_fu_code_1 = ldq_uop_14_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_1 = ldq_uop_14_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_2; // @[lsu.scala:219:36] wire l_uop_14_fu_code_2 = ldq_uop_14_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_2 = ldq_uop_14_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_3; // @[lsu.scala:219:36] wire l_uop_14_fu_code_3 = ldq_uop_14_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_3 = ldq_uop_14_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_4; // @[lsu.scala:219:36] wire l_uop_14_fu_code_4 = ldq_uop_14_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_4 = ldq_uop_14_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_5; // @[lsu.scala:219:36] wire l_uop_14_fu_code_5 = ldq_uop_14_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_5 = ldq_uop_14_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_6; // @[lsu.scala:219:36] wire l_uop_14_fu_code_6 = ldq_uop_14_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_6 = ldq_uop_14_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_7; // @[lsu.scala:219:36] wire l_uop_14_fu_code_7 = ldq_uop_14_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_7 = ldq_uop_14_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_8; // @[lsu.scala:219:36] wire l_uop_14_fu_code_8 = ldq_uop_14_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_8 = ldq_uop_14_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_9; // @[lsu.scala:219:36] wire l_uop_14_fu_code_9 = ldq_uop_14_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_9 = ldq_uop_14_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_issued; // @[lsu.scala:219:36] wire l_uop_14_iw_issued = ldq_uop_14_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_issued = ldq_uop_14_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_14_iw_issued_partial_agen = ldq_uop_14_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_issued_partial_agen = ldq_uop_14_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_14_iw_issued_partial_dgen = ldq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_issued_partial_dgen = ldq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_14_iw_p1_speculative_child = ldq_uop_14_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_iw_p1_speculative_child = ldq_uop_14_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_14_iw_p2_speculative_child = ldq_uop_14_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_iw_p2_speculative_child = ldq_uop_14_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_14_iw_p1_bypass_hint = ldq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_p1_bypass_hint = ldq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_14_iw_p2_bypass_hint = ldq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_p2_bypass_hint = ldq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_14_iw_p3_bypass_hint = ldq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_p3_bypass_hint = ldq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_14_dis_col_sel = ldq_uop_14_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_dis_col_sel = ldq_uop_14_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_14_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_14_br_mask = ldq_uop_14_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_31_br_mask = ldq_uop_14_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_14_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_14_br_tag = ldq_uop_14_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_31_br_tag = ldq_uop_14_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_14_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_14_br_type = ldq_uop_14_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_31_br_type = ldq_uop_14_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_sfb; // @[lsu.scala:219:36] wire l_uop_14_is_sfb = ldq_uop_14_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_sfb = ldq_uop_14_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_fence; // @[lsu.scala:219:36] wire l_uop_14_is_fence = ldq_uop_14_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_fence = ldq_uop_14_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_fencei; // @[lsu.scala:219:36] wire l_uop_14_is_fencei = ldq_uop_14_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_fencei = ldq_uop_14_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_sfence; // @[lsu.scala:219:36] wire l_uop_14_is_sfence = ldq_uop_14_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_sfence = ldq_uop_14_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_amo; // @[lsu.scala:219:36] wire l_uop_14_is_amo = ldq_uop_14_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_amo = ldq_uop_14_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_eret; // @[lsu.scala:219:36] wire l_uop_14_is_eret = ldq_uop_14_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_eret = ldq_uop_14_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_14_is_sys_pc2epc = ldq_uop_14_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_sys_pc2epc = ldq_uop_14_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_rocc; // @[lsu.scala:219:36] wire l_uop_14_is_rocc = ldq_uop_14_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_rocc = ldq_uop_14_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_mov; // @[lsu.scala:219:36] wire l_uop_14_is_mov = ldq_uop_14_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_mov = ldq_uop_14_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_14_ftq_idx = ldq_uop_14_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_ftq_idx = ldq_uop_14_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_edge_inst; // @[lsu.scala:219:36] wire l_uop_14_edge_inst = ldq_uop_14_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_31_edge_inst = ldq_uop_14_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_14_pc_lob = ldq_uop_14_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_pc_lob = ldq_uop_14_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_taken; // @[lsu.scala:219:36] wire l_uop_14_taken = ldq_uop_14_taken; // @[lsu.scala:219:36, :1191:37] wire uop_31_taken = ldq_uop_14_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_imm_rename; // @[lsu.scala:219:36] wire l_uop_14_imm_rename = ldq_uop_14_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_31_imm_rename = ldq_uop_14_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_14_imm_sel = ldq_uop_14_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_imm_sel = ldq_uop_14_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_14_pimm = ldq_uop_14_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_pimm = ldq_uop_14_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_14_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_14_imm_packed = ldq_uop_14_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_31_imm_packed = ldq_uop_14_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_14_op1_sel = ldq_uop_14_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_op1_sel = ldq_uop_14_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_14_op2_sel = ldq_uop_14_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_op2_sel = ldq_uop_14_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ldst = ldq_uop_14_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ldst = ldq_uop_14_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_wen = ldq_uop_14_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_wen = ldq_uop_14_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ren1 = ldq_uop_14_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ren1 = ldq_uop_14_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ren2 = ldq_uop_14_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ren2 = ldq_uop_14_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ren3 = ldq_uop_14_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ren3 = ldq_uop_14_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_swap12 = ldq_uop_14_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_swap12 = ldq_uop_14_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_swap23 = ldq_uop_14_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_swap23 = ldq_uop_14_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_14_fp_ctrl_typeTagIn = ldq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_fp_ctrl_typeTagIn = ldq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_14_fp_ctrl_typeTagOut = ldq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_fp_ctrl_typeTagOut = ldq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_fromint = ldq_uop_14_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_fromint = ldq_uop_14_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_toint = ldq_uop_14_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_toint = ldq_uop_14_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_fastpipe = ldq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_fastpipe = ldq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_fma = ldq_uop_14_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_fma = ldq_uop_14_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_div = ldq_uop_14_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_div = ldq_uop_14_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_sqrt = ldq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_sqrt = ldq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_wflags = ldq_uop_14_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_wflags = ldq_uop_14_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_vec = ldq_uop_14_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_vec = ldq_uop_14_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_14_rob_idx = ldq_uop_14_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_rob_idx = ldq_uop_14_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_14_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_14_ldq_idx = ldq_uop_14_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_31_ldq_idx = ldq_uop_14_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_14_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_14_stq_idx = ldq_uop_14_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_31_stq_idx = ldq_uop_14_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_14_rxq_idx = ldq_uop_14_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_rxq_idx = ldq_uop_14_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_14_pdst = ldq_uop_14_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_pdst = ldq_uop_14_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_14_prs1 = ldq_uop_14_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_prs1 = ldq_uop_14_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_14_prs2 = ldq_uop_14_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_prs2 = ldq_uop_14_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_14_prs3 = ldq_uop_14_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_prs3 = ldq_uop_14_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_14_ppred = ldq_uop_14_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_ppred = ldq_uop_14_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_prs1_busy; // @[lsu.scala:219:36] wire l_uop_14_prs1_busy = ldq_uop_14_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_prs1_busy = ldq_uop_14_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_prs2_busy; // @[lsu.scala:219:36] wire l_uop_14_prs2_busy = ldq_uop_14_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_prs2_busy = ldq_uop_14_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_prs3_busy; // @[lsu.scala:219:36] wire l_uop_14_prs3_busy = ldq_uop_14_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_prs3_busy = ldq_uop_14_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_ppred_busy; // @[lsu.scala:219:36] wire l_uop_14_ppred_busy = ldq_uop_14_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_ppred_busy = ldq_uop_14_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_14_stale_pdst = ldq_uop_14_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_stale_pdst = ldq_uop_14_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_exception; // @[lsu.scala:219:36] wire l_uop_14_exception = ldq_uop_14_exception; // @[lsu.scala:219:36, :1191:37] wire uop_31_exception = ldq_uop_14_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_14_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_14_exc_cause = ldq_uop_14_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_31_exc_cause = ldq_uop_14_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_14_mem_cmd = ldq_uop_14_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_mem_cmd = ldq_uop_14_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_14_mem_size = ldq_uop_14_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_mem_size = ldq_uop_14_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_mem_signed; // @[lsu.scala:219:36] wire l_uop_14_mem_signed = ldq_uop_14_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_31_mem_signed = ldq_uop_14_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_uses_ldq; // @[lsu.scala:219:36] wire l_uop_14_uses_ldq = ldq_uop_14_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_31_uses_ldq = ldq_uop_14_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_uses_stq; // @[lsu.scala:219:36] wire l_uop_14_uses_stq = ldq_uop_14_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_31_uses_stq = ldq_uop_14_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_unique; // @[lsu.scala:219:36] wire l_uop_14_is_unique = ldq_uop_14_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_unique = ldq_uop_14_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_14_flush_on_commit = ldq_uop_14_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_31_flush_on_commit = ldq_uop_14_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_14_csr_cmd = ldq_uop_14_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_csr_cmd = ldq_uop_14_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_14_ldst_is_rs1 = ldq_uop_14_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_31_ldst_is_rs1 = ldq_uop_14_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_14_ldst = ldq_uop_14_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_ldst = ldq_uop_14_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_14_lrs1 = ldq_uop_14_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_lrs1 = ldq_uop_14_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_14_lrs2 = ldq_uop_14_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_lrs2 = ldq_uop_14_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_14_lrs3 = ldq_uop_14_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_lrs3 = ldq_uop_14_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_14_dst_rtype = ldq_uop_14_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_dst_rtype = ldq_uop_14_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_14_lrs1_rtype = ldq_uop_14_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_lrs1_rtype = ldq_uop_14_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_14_lrs2_rtype = ldq_uop_14_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_lrs2_rtype = ldq_uop_14_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_frs3_en; // @[lsu.scala:219:36] wire l_uop_14_frs3_en = ldq_uop_14_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_31_frs3_en = ldq_uop_14_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fcn_dw; // @[lsu.scala:219:36] wire l_uop_14_fcn_dw = ldq_uop_14_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_31_fcn_dw = ldq_uop_14_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_14_fcn_op = ldq_uop_14_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_fcn_op = ldq_uop_14_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_val; // @[lsu.scala:219:36] wire l_uop_14_fp_val = ldq_uop_14_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_val = ldq_uop_14_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_14_fp_rm = ldq_uop_14_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_fp_rm = ldq_uop_14_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_14_fp_typ = ldq_uop_14_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_fp_typ = ldq_uop_14_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_14_xcpt_pf_if = ldq_uop_14_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_xcpt_pf_if = ldq_uop_14_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_14_xcpt_ae_if = ldq_uop_14_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_xcpt_ae_if = ldq_uop_14_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_14_xcpt_ma_if = ldq_uop_14_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_xcpt_ma_if = ldq_uop_14_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_14_bp_debug_if = ldq_uop_14_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_bp_debug_if = ldq_uop_14_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_14_bp_xcpt_if = ldq_uop_14_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_bp_xcpt_if = ldq_uop_14_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_14_debug_fsrc = ldq_uop_14_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_debug_fsrc = ldq_uop_14_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_14_debug_tsrc = ldq_uop_14_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_debug_tsrc = ldq_uop_14_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_15_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_15_inst = ldq_uop_15_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_32_inst = ldq_uop_15_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_15_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_15_debug_inst = ldq_uop_15_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_32_debug_inst = ldq_uop_15_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_rvc; // @[lsu.scala:219:36] wire l_uop_15_is_rvc = ldq_uop_15_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_rvc = ldq_uop_15_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_15_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_15_debug_pc = ldq_uop_15_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_32_debug_pc = ldq_uop_15_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_0; // @[lsu.scala:219:36] wire l_uop_15_iq_type_0 = ldq_uop_15_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_0 = ldq_uop_15_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_1; // @[lsu.scala:219:36] wire l_uop_15_iq_type_1 = ldq_uop_15_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_1 = ldq_uop_15_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_2; // @[lsu.scala:219:36] wire l_uop_15_iq_type_2 = ldq_uop_15_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_2 = ldq_uop_15_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_3; // @[lsu.scala:219:36] wire l_uop_15_iq_type_3 = ldq_uop_15_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_3 = ldq_uop_15_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_0; // @[lsu.scala:219:36] wire l_uop_15_fu_code_0 = ldq_uop_15_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_0 = ldq_uop_15_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_1; // @[lsu.scala:219:36] wire l_uop_15_fu_code_1 = ldq_uop_15_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_1 = ldq_uop_15_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_2; // @[lsu.scala:219:36] wire l_uop_15_fu_code_2 = ldq_uop_15_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_2 = ldq_uop_15_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_3; // @[lsu.scala:219:36] wire l_uop_15_fu_code_3 = ldq_uop_15_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_3 = ldq_uop_15_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_4; // @[lsu.scala:219:36] wire l_uop_15_fu_code_4 = ldq_uop_15_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_4 = ldq_uop_15_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_5; // @[lsu.scala:219:36] wire l_uop_15_fu_code_5 = ldq_uop_15_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_5 = ldq_uop_15_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_6; // @[lsu.scala:219:36] wire l_uop_15_fu_code_6 = ldq_uop_15_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_6 = ldq_uop_15_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_7; // @[lsu.scala:219:36] wire l_uop_15_fu_code_7 = ldq_uop_15_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_7 = ldq_uop_15_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_8; // @[lsu.scala:219:36] wire l_uop_15_fu_code_8 = ldq_uop_15_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_8 = ldq_uop_15_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_9; // @[lsu.scala:219:36] wire l_uop_15_fu_code_9 = ldq_uop_15_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_9 = ldq_uop_15_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_issued; // @[lsu.scala:219:36] wire l_uop_15_iw_issued = ldq_uop_15_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_issued = ldq_uop_15_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_15_iw_issued_partial_agen = ldq_uop_15_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_issued_partial_agen = ldq_uop_15_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_15_iw_issued_partial_dgen = ldq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_issued_partial_dgen = ldq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_15_iw_p1_speculative_child = ldq_uop_15_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_iw_p1_speculative_child = ldq_uop_15_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [1:0] l_uop_15_iw_p2_speculative_child = ldq_uop_15_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_iw_p2_speculative_child = ldq_uop_15_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_15_iw_p1_bypass_hint = ldq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_p1_bypass_hint = ldq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_15_iw_p2_bypass_hint = ldq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_p2_bypass_hint = ldq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_15_iw_p3_bypass_hint = ldq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_p3_bypass_hint = ldq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_dis_col_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_15_dis_col_sel = ldq_uop_15_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_dis_col_sel = ldq_uop_15_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [11:0] ldq_uop_15_br_mask; // @[lsu.scala:219:36] wire [11:0] l_uop_15_br_mask = ldq_uop_15_br_mask; // @[lsu.scala:219:36, :1191:37] wire [11:0] uop_32_br_mask = ldq_uop_15_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_15_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_15_br_tag = ldq_uop_15_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_32_br_tag = ldq_uop_15_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_15_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_15_br_type = ldq_uop_15_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_32_br_type = ldq_uop_15_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_sfb; // @[lsu.scala:219:36] wire l_uop_15_is_sfb = ldq_uop_15_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_sfb = ldq_uop_15_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_fence; // @[lsu.scala:219:36] wire l_uop_15_is_fence = ldq_uop_15_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_fence = ldq_uop_15_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_fencei; // @[lsu.scala:219:36] wire l_uop_15_is_fencei = ldq_uop_15_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_fencei = ldq_uop_15_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_sfence; // @[lsu.scala:219:36] wire l_uop_15_is_sfence = ldq_uop_15_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_sfence = ldq_uop_15_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_amo; // @[lsu.scala:219:36] wire l_uop_15_is_amo = ldq_uop_15_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_amo = ldq_uop_15_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_eret; // @[lsu.scala:219:36] wire l_uop_15_is_eret = ldq_uop_15_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_eret = ldq_uop_15_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_15_is_sys_pc2epc = ldq_uop_15_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_sys_pc2epc = ldq_uop_15_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_rocc; // @[lsu.scala:219:36] wire l_uop_15_is_rocc = ldq_uop_15_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_rocc = ldq_uop_15_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_mov; // @[lsu.scala:219:36] wire l_uop_15_is_mov = ldq_uop_15_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_mov = ldq_uop_15_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_15_ftq_idx = ldq_uop_15_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_ftq_idx = ldq_uop_15_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_edge_inst; // @[lsu.scala:219:36] wire l_uop_15_edge_inst = ldq_uop_15_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_32_edge_inst = ldq_uop_15_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_15_pc_lob = ldq_uop_15_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_pc_lob = ldq_uop_15_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_taken; // @[lsu.scala:219:36] wire l_uop_15_taken = ldq_uop_15_taken; // @[lsu.scala:219:36, :1191:37] wire uop_32_taken = ldq_uop_15_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_imm_rename; // @[lsu.scala:219:36] wire l_uop_15_imm_rename = ldq_uop_15_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_32_imm_rename = ldq_uop_15_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_15_imm_sel = ldq_uop_15_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_imm_sel = ldq_uop_15_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_15_pimm = ldq_uop_15_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_pimm = ldq_uop_15_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_15_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_15_imm_packed = ldq_uop_15_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_32_imm_packed = ldq_uop_15_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_15_op1_sel = ldq_uop_15_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_op1_sel = ldq_uop_15_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_15_op2_sel = ldq_uop_15_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_op2_sel = ldq_uop_15_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ldst = ldq_uop_15_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ldst = ldq_uop_15_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_wen = ldq_uop_15_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_wen = ldq_uop_15_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ren1 = ldq_uop_15_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ren1 = ldq_uop_15_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ren2 = ldq_uop_15_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ren2 = ldq_uop_15_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ren3 = ldq_uop_15_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ren3 = ldq_uop_15_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_swap12 = ldq_uop_15_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_swap12 = ldq_uop_15_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_swap23 = ldq_uop_15_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_swap23 = ldq_uop_15_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_15_fp_ctrl_typeTagIn = ldq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_fp_ctrl_typeTagIn = ldq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_15_fp_ctrl_typeTagOut = ldq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_fp_ctrl_typeTagOut = ldq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_fromint = ldq_uop_15_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_fromint = ldq_uop_15_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_toint = ldq_uop_15_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_toint = ldq_uop_15_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_fastpipe = ldq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_fastpipe = ldq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_fma = ldq_uop_15_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_fma = ldq_uop_15_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_div = ldq_uop_15_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_div = ldq_uop_15_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_sqrt = ldq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_sqrt = ldq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_wflags = ldq_uop_15_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_wflags = ldq_uop_15_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_vec = ldq_uop_15_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_vec = ldq_uop_15_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_rob_idx; // @[lsu.scala:219:36] wire [5:0] l_uop_15_rob_idx = ldq_uop_15_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_rob_idx = ldq_uop_15_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_15_ldq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_15_ldq_idx = ldq_uop_15_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_32_ldq_idx = ldq_uop_15_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_15_stq_idx; // @[lsu.scala:219:36] wire [3:0] l_uop_15_stq_idx = ldq_uop_15_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_32_stq_idx = ldq_uop_15_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_15_rxq_idx = ldq_uop_15_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_rxq_idx = ldq_uop_15_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_15_pdst = ldq_uop_15_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_pdst = ldq_uop_15_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_15_prs1 = ldq_uop_15_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_prs1 = ldq_uop_15_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_15_prs2 = ldq_uop_15_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_prs2 = ldq_uop_15_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_15_prs3 = ldq_uop_15_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_prs3 = ldq_uop_15_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_15_ppred = ldq_uop_15_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_ppred = ldq_uop_15_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_prs1_busy; // @[lsu.scala:219:36] wire l_uop_15_prs1_busy = ldq_uop_15_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_prs1_busy = ldq_uop_15_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_prs2_busy; // @[lsu.scala:219:36] wire l_uop_15_prs2_busy = ldq_uop_15_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_prs2_busy = ldq_uop_15_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_prs3_busy; // @[lsu.scala:219:36] wire l_uop_15_prs3_busy = ldq_uop_15_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_prs3_busy = ldq_uop_15_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_ppred_busy; // @[lsu.scala:219:36] wire l_uop_15_ppred_busy = ldq_uop_15_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_ppred_busy = ldq_uop_15_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_15_stale_pdst = ldq_uop_15_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_stale_pdst = ldq_uop_15_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_exception; // @[lsu.scala:219:36] wire l_uop_15_exception = ldq_uop_15_exception; // @[lsu.scala:219:36, :1191:37] wire uop_32_exception = ldq_uop_15_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_15_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_15_exc_cause = ldq_uop_15_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_32_exc_cause = ldq_uop_15_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_15_mem_cmd = ldq_uop_15_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_mem_cmd = ldq_uop_15_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_15_mem_size = ldq_uop_15_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_mem_size = ldq_uop_15_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_mem_signed; // @[lsu.scala:219:36] wire l_uop_15_mem_signed = ldq_uop_15_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_32_mem_signed = ldq_uop_15_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_uses_ldq; // @[lsu.scala:219:36] wire l_uop_15_uses_ldq = ldq_uop_15_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_32_uses_ldq = ldq_uop_15_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_uses_stq; // @[lsu.scala:219:36] wire l_uop_15_uses_stq = ldq_uop_15_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_32_uses_stq = ldq_uop_15_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_unique; // @[lsu.scala:219:36] wire l_uop_15_is_unique = ldq_uop_15_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_unique = ldq_uop_15_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_15_flush_on_commit = ldq_uop_15_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_32_flush_on_commit = ldq_uop_15_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_15_csr_cmd = ldq_uop_15_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_csr_cmd = ldq_uop_15_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_15_ldst_is_rs1 = ldq_uop_15_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_32_ldst_is_rs1 = ldq_uop_15_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_15_ldst = ldq_uop_15_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_ldst = ldq_uop_15_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_15_lrs1 = ldq_uop_15_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_lrs1 = ldq_uop_15_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_15_lrs2 = ldq_uop_15_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_lrs2 = ldq_uop_15_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_15_lrs3 = ldq_uop_15_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_lrs3 = ldq_uop_15_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_15_dst_rtype = ldq_uop_15_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_dst_rtype = ldq_uop_15_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_15_lrs1_rtype = ldq_uop_15_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_lrs1_rtype = ldq_uop_15_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_15_lrs2_rtype = ldq_uop_15_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_lrs2_rtype = ldq_uop_15_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_frs3_en; // @[lsu.scala:219:36] wire l_uop_15_frs3_en = ldq_uop_15_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_32_frs3_en = ldq_uop_15_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fcn_dw; // @[lsu.scala:219:36] wire l_uop_15_fcn_dw = ldq_uop_15_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_32_fcn_dw = ldq_uop_15_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_15_fcn_op = ldq_uop_15_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_fcn_op = ldq_uop_15_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_val; // @[lsu.scala:219:36] wire l_uop_15_fp_val = ldq_uop_15_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_val = ldq_uop_15_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_15_fp_rm = ldq_uop_15_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_fp_rm = ldq_uop_15_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_15_fp_typ = ldq_uop_15_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_fp_typ = ldq_uop_15_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_15_xcpt_pf_if = ldq_uop_15_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_xcpt_pf_if = ldq_uop_15_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_15_xcpt_ae_if = ldq_uop_15_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_xcpt_ae_if = ldq_uop_15_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_15_xcpt_ma_if = ldq_uop_15_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_xcpt_ma_if = ldq_uop_15_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_15_bp_debug_if = ldq_uop_15_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_bp_debug_if = ldq_uop_15_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_15_bp_xcpt_if = ldq_uop_15_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_bp_xcpt_if = ldq_uop_15_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_15_debug_fsrc = ldq_uop_15_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_debug_fsrc = ldq_uop_15_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_15_debug_tsrc = ldq_uop_15_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_debug_tsrc = ldq_uop_15_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg ldq_addr_0_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_0_bits; // @[lsu.scala:220:36] reg ldq_addr_1_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_1_bits; // @[lsu.scala:220:36] reg ldq_addr_2_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_2_bits; // @[lsu.scala:220:36] reg ldq_addr_3_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_3_bits; // @[lsu.scala:220:36] reg ldq_addr_4_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_4_bits; // @[lsu.scala:220:36] reg ldq_addr_5_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_5_bits; // @[lsu.scala:220:36] reg ldq_addr_6_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_6_bits; // @[lsu.scala:220:36] reg ldq_addr_7_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_7_bits; // @[lsu.scala:220:36] reg ldq_addr_8_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_8_bits; // @[lsu.scala:220:36] reg ldq_addr_9_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_9_bits; // @[lsu.scala:220:36] reg ldq_addr_10_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_10_bits; // @[lsu.scala:220:36] reg ldq_addr_11_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_11_bits; // @[lsu.scala:220:36] reg ldq_addr_12_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_12_bits; // @[lsu.scala:220:36] reg ldq_addr_13_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_13_bits; // @[lsu.scala:220:36] reg ldq_addr_14_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_14_bits; // @[lsu.scala:220:36] reg ldq_addr_15_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_15_bits; // @[lsu.scala:220:36] reg ldq_addr_is_virtual_0; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_1; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_2; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_3; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_4; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_5; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_6; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_7; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_8; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_9; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_10; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_11; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_12; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_13; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_14; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_15; // @[lsu.scala:221:36] reg ldq_addr_is_uncacheable_0; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_1; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_2; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_3; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_4; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_5; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_6; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_7; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_8; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_9; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_10; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_11; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_12; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_13; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_14; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_15; // @[lsu.scala:222:36] reg ldq_executed_0; // @[lsu.scala:223:36] reg ldq_executed_1; // @[lsu.scala:223:36] reg ldq_executed_2; // @[lsu.scala:223:36] reg ldq_executed_3; // @[lsu.scala:223:36] reg ldq_executed_4; // @[lsu.scala:223:36] reg ldq_executed_5; // @[lsu.scala:223:36] reg ldq_executed_6; // @[lsu.scala:223:36] reg ldq_executed_7; // @[lsu.scala:223:36] reg ldq_executed_8; // @[lsu.scala:223:36] reg ldq_executed_9; // @[lsu.scala:223:36] reg ldq_executed_10; // @[lsu.scala:223:36] reg ldq_executed_11; // @[lsu.scala:223:36] reg ldq_executed_12; // @[lsu.scala:223:36] reg ldq_executed_13; // @[lsu.scala:223:36] reg ldq_executed_14; // @[lsu.scala:223:36] reg ldq_executed_15; // @[lsu.scala:223:36] reg ldq_succeeded_0; // @[lsu.scala:224:36] reg ldq_succeeded_1; // @[lsu.scala:224:36] reg ldq_succeeded_2; // @[lsu.scala:224:36] reg ldq_succeeded_3; // @[lsu.scala:224:36] reg ldq_succeeded_4; // @[lsu.scala:224:36] reg ldq_succeeded_5; // @[lsu.scala:224:36] reg ldq_succeeded_6; // @[lsu.scala:224:36] reg ldq_succeeded_7; // @[lsu.scala:224:36] reg ldq_succeeded_8; // @[lsu.scala:224:36] reg ldq_succeeded_9; // @[lsu.scala:224:36] reg ldq_succeeded_10; // @[lsu.scala:224:36] reg ldq_succeeded_11; // @[lsu.scala:224:36] reg ldq_succeeded_12; // @[lsu.scala:224:36] reg ldq_succeeded_13; // @[lsu.scala:224:36] reg ldq_succeeded_14; // @[lsu.scala:224:36] reg ldq_succeeded_15; // @[lsu.scala:224:36] reg ldq_order_fail_0; // @[lsu.scala:225:36] reg ldq_order_fail_1; // @[lsu.scala:225:36] reg ldq_order_fail_2; // @[lsu.scala:225:36] reg ldq_order_fail_3; // @[lsu.scala:225:36] reg ldq_order_fail_4; // @[lsu.scala:225:36] reg ldq_order_fail_5; // @[lsu.scala:225:36] reg ldq_order_fail_6; // @[lsu.scala:225:36] reg ldq_order_fail_7; // @[lsu.scala:225:36] reg ldq_order_fail_8; // @[lsu.scala:225:36] reg ldq_order_fail_9; // @[lsu.scala:225:36] reg ldq_order_fail_10; // @[lsu.scala:225:36] reg ldq_order_fail_11; // @[lsu.scala:225:36] reg ldq_order_fail_12; // @[lsu.scala:225:36] reg ldq_order_fail_13; // @[lsu.scala:225:36] reg ldq_order_fail_14; // @[lsu.scala:225:36] reg ldq_order_fail_15; // @[lsu.scala:225:36] reg ldq_observed_0; // @[lsu.scala:226:36] reg ldq_observed_1; // @[lsu.scala:226:36] reg ldq_observed_2; // @[lsu.scala:226:36] reg ldq_observed_3; // @[lsu.scala:226:36] reg ldq_observed_4; // @[lsu.scala:226:36] reg ldq_observed_5; // @[lsu.scala:226:36] reg ldq_observed_6; // @[lsu.scala:226:36] reg ldq_observed_7; // @[lsu.scala:226:36] reg ldq_observed_8; // @[lsu.scala:226:36] reg ldq_observed_9; // @[lsu.scala:226:36] reg ldq_observed_10; // @[lsu.scala:226:36] reg ldq_observed_11; // @[lsu.scala:226:36] reg ldq_observed_12; // @[lsu.scala:226:36] reg ldq_observed_13; // @[lsu.scala:226:36] reg ldq_observed_14; // @[lsu.scala:226:36] reg ldq_observed_15; // @[lsu.scala:226:36] reg [15:0] ldq_st_dep_mask_0; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_1; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_2; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_3; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_4; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_5; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_6; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_7; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_8; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_9; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_10; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_11; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_12; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_13; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_14; // @[lsu.scala:227:36] reg [15:0] ldq_st_dep_mask_15; // @[lsu.scala:227:36] reg [7:0] ldq_ld_byte_mask_0; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_1; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_2; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_3; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_4; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_5; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_6; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_7; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_8; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_9; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_10; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_11; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_12; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_13; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_14; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_15; // @[lsu.scala:228:36] reg ldq_forward_std_val_0; // @[lsu.scala:229:36] reg ldq_forward_std_val_1; // @[lsu.scala:229:36] reg ldq_forward_std_val_2; // @[lsu.scala:229:36] reg ldq_forward_std_val_3; // @[lsu.scala:229:36] reg ldq_forward_std_val_4; // @[lsu.scala:229:36] reg ldq_forward_std_val_5; // @[lsu.scala:229:36] reg ldq_forward_std_val_6; // @[lsu.scala:229:36] reg ldq_forward_std_val_7; // @[lsu.scala:229:36] reg ldq_forward_std_val_8; // @[lsu.scala:229:36] reg ldq_forward_std_val_9; // @[lsu.scala:229:36] reg ldq_forward_std_val_10; // @[lsu.scala:229:36] reg ldq_forward_std_val_11; // @[lsu.scala:229:36] reg ldq_forward_std_val_12; // @[lsu.scala:229:36] reg ldq_forward_std_val_13; // @[lsu.scala:229:36] reg ldq_forward_std_val_14; // @[lsu.scala:229:36] reg ldq_forward_std_val_15; // @[lsu.scala:229:36] reg [3:0] ldq_forward_stq_idx_0; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_1; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_2; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_3; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_4; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_5; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_6; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_7; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_8; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_9; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_10; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_11; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_12; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_13; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_14; // @[lsu.scala:230:36] reg [3:0] ldq_forward_stq_idx_15; // @[lsu.scala:230:36] reg [63:0] ldq_debug_wb_data_0; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_1; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_2; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_3; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_4; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_5; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_6; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_7; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_8; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_9; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_10; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_11; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_12; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_13; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_14; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_15; // @[lsu.scala:231:36] reg stq_valid_0; // @[lsu.scala:251:32] reg stq_valid_1; // @[lsu.scala:251:32] reg stq_valid_2; // @[lsu.scala:251:32] reg stq_valid_3; // @[lsu.scala:251:32] reg stq_valid_4; // @[lsu.scala:251:32] reg stq_valid_5; // @[lsu.scala:251:32] reg stq_valid_6; // @[lsu.scala:251:32] reg stq_valid_7; // @[lsu.scala:251:32] reg stq_valid_8; // @[lsu.scala:251:32] reg stq_valid_9; // @[lsu.scala:251:32] reg stq_valid_10; // @[lsu.scala:251:32] reg stq_valid_11; // @[lsu.scala:251:32] reg stq_valid_12; // @[lsu.scala:251:32] reg stq_valid_13; // @[lsu.scala:251:32] reg stq_valid_14; // @[lsu.scala:251:32] reg stq_valid_15; // @[lsu.scala:251:32] reg [31:0] stq_uop_0_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_2_inst = stq_uop_0_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_1_inst = stq_uop_0_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_0_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_2_debug_inst = stq_uop_0_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_1_debug_inst = stq_uop_0_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_rvc; // @[lsu.scala:252:32] wire s_uop_2_is_rvc = stq_uop_0_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_rvc = stq_uop_0_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_0_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_2_debug_pc = stq_uop_0_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_1_debug_pc = stq_uop_0_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_0; // @[lsu.scala:252:32] wire s_uop_2_iq_type_0 = stq_uop_0_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_0 = stq_uop_0_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_1; // @[lsu.scala:252:32] wire s_uop_2_iq_type_1 = stq_uop_0_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_1 = stq_uop_0_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_2; // @[lsu.scala:252:32] wire s_uop_2_iq_type_2 = stq_uop_0_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_2 = stq_uop_0_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_3; // @[lsu.scala:252:32] wire s_uop_2_iq_type_3 = stq_uop_0_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_3 = stq_uop_0_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_0; // @[lsu.scala:252:32] wire s_uop_2_fu_code_0 = stq_uop_0_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_0 = stq_uop_0_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_1; // @[lsu.scala:252:32] wire s_uop_2_fu_code_1 = stq_uop_0_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_1 = stq_uop_0_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_2; // @[lsu.scala:252:32] wire s_uop_2_fu_code_2 = stq_uop_0_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_2 = stq_uop_0_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_3; // @[lsu.scala:252:32] wire s_uop_2_fu_code_3 = stq_uop_0_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_3 = stq_uop_0_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_4; // @[lsu.scala:252:32] wire s_uop_2_fu_code_4 = stq_uop_0_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_4 = stq_uop_0_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_5; // @[lsu.scala:252:32] wire s_uop_2_fu_code_5 = stq_uop_0_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_5 = stq_uop_0_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_6; // @[lsu.scala:252:32] wire s_uop_2_fu_code_6 = stq_uop_0_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_6 = stq_uop_0_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_7; // @[lsu.scala:252:32] wire s_uop_2_fu_code_7 = stq_uop_0_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_7 = stq_uop_0_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_8; // @[lsu.scala:252:32] wire s_uop_2_fu_code_8 = stq_uop_0_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_8 = stq_uop_0_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_9; // @[lsu.scala:252:32] wire s_uop_2_fu_code_9 = stq_uop_0_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_9 = stq_uop_0_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_issued; // @[lsu.scala:252:32] wire s_uop_2_iw_issued = stq_uop_0_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_issued = stq_uop_0_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_2_iw_issued_partial_agen = stq_uop_0_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_issued_partial_agen = stq_uop_0_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_2_iw_issued_partial_dgen = stq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_issued_partial_dgen = stq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_2_iw_p1_speculative_child = stq_uop_0_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_iw_p1_speculative_child = stq_uop_0_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_2_iw_p2_speculative_child = stq_uop_0_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_iw_p2_speculative_child = stq_uop_0_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_2_iw_p1_bypass_hint = stq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_p1_bypass_hint = stq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_2_iw_p2_bypass_hint = stq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_p2_bypass_hint = stq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_2_iw_p3_bypass_hint = stq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_p3_bypass_hint = stq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_2_dis_col_sel = stq_uop_0_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_dis_col_sel = stq_uop_0_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_0_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_2_br_mask = stq_uop_0_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_1_br_mask = stq_uop_0_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_0_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_2_br_tag = stq_uop_0_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_1_br_tag = stq_uop_0_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_0_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_2_br_type = stq_uop_0_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_1_br_type = stq_uop_0_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_sfb; // @[lsu.scala:252:32] wire s_uop_2_is_sfb = stq_uop_0_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_sfb = stq_uop_0_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_fence; // @[lsu.scala:252:32] wire s_uop_2_is_fence = stq_uop_0_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_fence = stq_uop_0_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_fencei; // @[lsu.scala:252:32] wire s_uop_2_is_fencei = stq_uop_0_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_fencei = stq_uop_0_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_sfence; // @[lsu.scala:252:32] wire s_uop_2_is_sfence = stq_uop_0_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_sfence = stq_uop_0_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_amo; // @[lsu.scala:252:32] wire s_uop_2_is_amo = stq_uop_0_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_amo = stq_uop_0_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_eret; // @[lsu.scala:252:32] wire s_uop_2_is_eret = stq_uop_0_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_eret = stq_uop_0_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_2_is_sys_pc2epc = stq_uop_0_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_sys_pc2epc = stq_uop_0_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_rocc; // @[lsu.scala:252:32] wire s_uop_2_is_rocc = stq_uop_0_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_rocc = stq_uop_0_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_mov; // @[lsu.scala:252:32] wire s_uop_2_is_mov = stq_uop_0_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_mov = stq_uop_0_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_2_ftq_idx = stq_uop_0_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_ftq_idx = stq_uop_0_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_edge_inst; // @[lsu.scala:252:32] wire s_uop_2_edge_inst = stq_uop_0_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_1_edge_inst = stq_uop_0_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_2_pc_lob = stq_uop_0_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_pc_lob = stq_uop_0_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_taken; // @[lsu.scala:252:32] wire s_uop_2_taken = stq_uop_0_taken; // @[lsu.scala:252:32, :1324:37] wire uop_1_taken = stq_uop_0_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_imm_rename; // @[lsu.scala:252:32] wire s_uop_2_imm_rename = stq_uop_0_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_1_imm_rename = stq_uop_0_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_2_imm_sel = stq_uop_0_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_imm_sel = stq_uop_0_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_2_pimm = stq_uop_0_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_pimm = stq_uop_0_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_0_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_2_imm_packed = stq_uop_0_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_1_imm_packed = stq_uop_0_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_2_op1_sel = stq_uop_0_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_op1_sel = stq_uop_0_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_2_op2_sel = stq_uop_0_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_op2_sel = stq_uop_0_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_ldst = stq_uop_0_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ldst = stq_uop_0_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_wen = stq_uop_0_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_wen = stq_uop_0_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_ren1 = stq_uop_0_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ren1 = stq_uop_0_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_ren2 = stq_uop_0_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ren2 = stq_uop_0_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_ren3 = stq_uop_0_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ren3 = stq_uop_0_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_swap12 = stq_uop_0_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_swap12 = stq_uop_0_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_swap23 = stq_uop_0_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_swap23 = stq_uop_0_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_2_fp_ctrl_typeTagIn = stq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_fp_ctrl_typeTagIn = stq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_2_fp_ctrl_typeTagOut = stq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_fp_ctrl_typeTagOut = stq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_fromint = stq_uop_0_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_fromint = stq_uop_0_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_toint = stq_uop_0_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_toint = stq_uop_0_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_fastpipe = stq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_fastpipe = stq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_fma = stq_uop_0_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_fma = stq_uop_0_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_div = stq_uop_0_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_div = stq_uop_0_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_sqrt = stq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_sqrt = stq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_wflags = stq_uop_0_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_wflags = stq_uop_0_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_2_fp_ctrl_vec = stq_uop_0_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_vec = stq_uop_0_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_2_rob_idx = stq_uop_0_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_rob_idx = stq_uop_0_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_0_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_2_ldq_idx = stq_uop_0_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_1_ldq_idx = stq_uop_0_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_0_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_2_stq_idx = stq_uop_0_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_1_stq_idx = stq_uop_0_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_2_rxq_idx = stq_uop_0_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_rxq_idx = stq_uop_0_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_2_pdst = stq_uop_0_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_pdst = stq_uop_0_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_2_prs1 = stq_uop_0_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_prs1 = stq_uop_0_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_2_prs2 = stq_uop_0_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_prs2 = stq_uop_0_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_2_prs3 = stq_uop_0_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_prs3 = stq_uop_0_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_2_ppred = stq_uop_0_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_ppred = stq_uop_0_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_prs1_busy; // @[lsu.scala:252:32] wire s_uop_2_prs1_busy = stq_uop_0_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_prs1_busy = stq_uop_0_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_prs2_busy; // @[lsu.scala:252:32] wire s_uop_2_prs2_busy = stq_uop_0_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_prs2_busy = stq_uop_0_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_prs3_busy; // @[lsu.scala:252:32] wire s_uop_2_prs3_busy = stq_uop_0_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_prs3_busy = stq_uop_0_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_ppred_busy; // @[lsu.scala:252:32] wire s_uop_2_ppred_busy = stq_uop_0_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_ppred_busy = stq_uop_0_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_2_stale_pdst = stq_uop_0_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_stale_pdst = stq_uop_0_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_exception; // @[lsu.scala:252:32] wire s_uop_2_exception = stq_uop_0_exception; // @[lsu.scala:252:32, :1324:37] wire uop_1_exception = stq_uop_0_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_0_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_2_exc_cause = stq_uop_0_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_1_exc_cause = stq_uop_0_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_2_mem_cmd = stq_uop_0_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_mem_cmd = stq_uop_0_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_2_mem_size = stq_uop_0_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_mem_size = stq_uop_0_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_mem_signed; // @[lsu.scala:252:32] wire s_uop_2_mem_signed = stq_uop_0_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_1_mem_signed = stq_uop_0_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_uses_ldq; // @[lsu.scala:252:32] wire s_uop_2_uses_ldq = stq_uop_0_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_1_uses_ldq = stq_uop_0_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_uses_stq; // @[lsu.scala:252:32] wire s_uop_2_uses_stq = stq_uop_0_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_1_uses_stq = stq_uop_0_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_unique; // @[lsu.scala:252:32] wire s_uop_2_is_unique = stq_uop_0_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_unique = stq_uop_0_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_2_flush_on_commit = stq_uop_0_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_1_flush_on_commit = stq_uop_0_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_2_csr_cmd = stq_uop_0_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_csr_cmd = stq_uop_0_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_2_ldst_is_rs1 = stq_uop_0_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_1_ldst_is_rs1 = stq_uop_0_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_2_ldst = stq_uop_0_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_ldst = stq_uop_0_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_2_lrs1 = stq_uop_0_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_lrs1 = stq_uop_0_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_2_lrs2 = stq_uop_0_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_lrs2 = stq_uop_0_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_2_lrs3 = stq_uop_0_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_lrs3 = stq_uop_0_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_2_dst_rtype = stq_uop_0_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_dst_rtype = stq_uop_0_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_2_lrs1_rtype = stq_uop_0_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_lrs1_rtype = stq_uop_0_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_2_lrs2_rtype = stq_uop_0_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_lrs2_rtype = stq_uop_0_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_frs3_en; // @[lsu.scala:252:32] wire s_uop_2_frs3_en = stq_uop_0_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_1_frs3_en = stq_uop_0_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fcn_dw; // @[lsu.scala:252:32] wire s_uop_2_fcn_dw = stq_uop_0_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_1_fcn_dw = stq_uop_0_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_2_fcn_op = stq_uop_0_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_fcn_op = stq_uop_0_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_val; // @[lsu.scala:252:32] wire s_uop_2_fp_val = stq_uop_0_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_val = stq_uop_0_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_2_fp_rm = stq_uop_0_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_fp_rm = stq_uop_0_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_2_fp_typ = stq_uop_0_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_fp_typ = stq_uop_0_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_2_xcpt_pf_if = stq_uop_0_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_xcpt_pf_if = stq_uop_0_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_2_xcpt_ae_if = stq_uop_0_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_xcpt_ae_if = stq_uop_0_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_2_xcpt_ma_if = stq_uop_0_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_xcpt_ma_if = stq_uop_0_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_2_bp_debug_if = stq_uop_0_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_bp_debug_if = stq_uop_0_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_2_bp_xcpt_if = stq_uop_0_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_bp_xcpt_if = stq_uop_0_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_2_debug_fsrc = stq_uop_0_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_debug_fsrc = stq_uop_0_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_2_debug_tsrc = stq_uop_0_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_debug_tsrc = stq_uop_0_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_1_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_3_inst = stq_uop_1_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_2_inst = stq_uop_1_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_1_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_3_debug_inst = stq_uop_1_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_2_debug_inst = stq_uop_1_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_rvc; // @[lsu.scala:252:32] wire s_uop_3_is_rvc = stq_uop_1_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_rvc = stq_uop_1_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_1_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_3_debug_pc = stq_uop_1_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_2_debug_pc = stq_uop_1_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_0; // @[lsu.scala:252:32] wire s_uop_3_iq_type_0 = stq_uop_1_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_0 = stq_uop_1_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_1; // @[lsu.scala:252:32] wire s_uop_3_iq_type_1 = stq_uop_1_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_1 = stq_uop_1_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_2; // @[lsu.scala:252:32] wire s_uop_3_iq_type_2 = stq_uop_1_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_2 = stq_uop_1_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_3; // @[lsu.scala:252:32] wire s_uop_3_iq_type_3 = stq_uop_1_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_3 = stq_uop_1_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_0; // @[lsu.scala:252:32] wire s_uop_3_fu_code_0 = stq_uop_1_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_0 = stq_uop_1_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_1; // @[lsu.scala:252:32] wire s_uop_3_fu_code_1 = stq_uop_1_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_1 = stq_uop_1_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_2; // @[lsu.scala:252:32] wire s_uop_3_fu_code_2 = stq_uop_1_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_2 = stq_uop_1_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_3; // @[lsu.scala:252:32] wire s_uop_3_fu_code_3 = stq_uop_1_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_3 = stq_uop_1_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_4; // @[lsu.scala:252:32] wire s_uop_3_fu_code_4 = stq_uop_1_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_4 = stq_uop_1_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_5; // @[lsu.scala:252:32] wire s_uop_3_fu_code_5 = stq_uop_1_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_5 = stq_uop_1_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_6; // @[lsu.scala:252:32] wire s_uop_3_fu_code_6 = stq_uop_1_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_6 = stq_uop_1_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_7; // @[lsu.scala:252:32] wire s_uop_3_fu_code_7 = stq_uop_1_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_7 = stq_uop_1_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_8; // @[lsu.scala:252:32] wire s_uop_3_fu_code_8 = stq_uop_1_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_8 = stq_uop_1_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_9; // @[lsu.scala:252:32] wire s_uop_3_fu_code_9 = stq_uop_1_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_9 = stq_uop_1_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_issued; // @[lsu.scala:252:32] wire s_uop_3_iw_issued = stq_uop_1_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_issued = stq_uop_1_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_3_iw_issued_partial_agen = stq_uop_1_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_issued_partial_agen = stq_uop_1_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_3_iw_issued_partial_dgen = stq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_issued_partial_dgen = stq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_3_iw_p1_speculative_child = stq_uop_1_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_iw_p1_speculative_child = stq_uop_1_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_3_iw_p2_speculative_child = stq_uop_1_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_iw_p2_speculative_child = stq_uop_1_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_3_iw_p1_bypass_hint = stq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_p1_bypass_hint = stq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_3_iw_p2_bypass_hint = stq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_p2_bypass_hint = stq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_3_iw_p3_bypass_hint = stq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_p3_bypass_hint = stq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_3_dis_col_sel = stq_uop_1_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_dis_col_sel = stq_uop_1_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_1_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_3_br_mask = stq_uop_1_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_2_br_mask = stq_uop_1_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_1_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_3_br_tag = stq_uop_1_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_2_br_tag = stq_uop_1_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_1_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_3_br_type = stq_uop_1_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_2_br_type = stq_uop_1_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_sfb; // @[lsu.scala:252:32] wire s_uop_3_is_sfb = stq_uop_1_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_sfb = stq_uop_1_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_fence; // @[lsu.scala:252:32] wire s_uop_3_is_fence = stq_uop_1_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_fence = stq_uop_1_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_fencei; // @[lsu.scala:252:32] wire s_uop_3_is_fencei = stq_uop_1_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_fencei = stq_uop_1_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_sfence; // @[lsu.scala:252:32] wire s_uop_3_is_sfence = stq_uop_1_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_sfence = stq_uop_1_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_amo; // @[lsu.scala:252:32] wire s_uop_3_is_amo = stq_uop_1_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_amo = stq_uop_1_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_eret; // @[lsu.scala:252:32] wire s_uop_3_is_eret = stq_uop_1_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_eret = stq_uop_1_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_3_is_sys_pc2epc = stq_uop_1_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_sys_pc2epc = stq_uop_1_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_rocc; // @[lsu.scala:252:32] wire s_uop_3_is_rocc = stq_uop_1_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_rocc = stq_uop_1_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_mov; // @[lsu.scala:252:32] wire s_uop_3_is_mov = stq_uop_1_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_mov = stq_uop_1_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_3_ftq_idx = stq_uop_1_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_ftq_idx = stq_uop_1_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_edge_inst; // @[lsu.scala:252:32] wire s_uop_3_edge_inst = stq_uop_1_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_2_edge_inst = stq_uop_1_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_3_pc_lob = stq_uop_1_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_pc_lob = stq_uop_1_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_taken; // @[lsu.scala:252:32] wire s_uop_3_taken = stq_uop_1_taken; // @[lsu.scala:252:32, :1324:37] wire uop_2_taken = stq_uop_1_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_imm_rename; // @[lsu.scala:252:32] wire s_uop_3_imm_rename = stq_uop_1_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_2_imm_rename = stq_uop_1_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_3_imm_sel = stq_uop_1_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_imm_sel = stq_uop_1_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_3_pimm = stq_uop_1_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_pimm = stq_uop_1_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_1_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_3_imm_packed = stq_uop_1_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_2_imm_packed = stq_uop_1_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_3_op1_sel = stq_uop_1_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_op1_sel = stq_uop_1_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_3_op2_sel = stq_uop_1_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_op2_sel = stq_uop_1_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ldst = stq_uop_1_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ldst = stq_uop_1_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_wen = stq_uop_1_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_wen = stq_uop_1_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ren1 = stq_uop_1_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ren1 = stq_uop_1_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ren2 = stq_uop_1_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ren2 = stq_uop_1_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ren3 = stq_uop_1_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ren3 = stq_uop_1_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_swap12 = stq_uop_1_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_swap12 = stq_uop_1_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_swap23 = stq_uop_1_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_swap23 = stq_uop_1_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_3_fp_ctrl_typeTagIn = stq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_fp_ctrl_typeTagIn = stq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_3_fp_ctrl_typeTagOut = stq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_fp_ctrl_typeTagOut = stq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_fromint = stq_uop_1_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_fromint = stq_uop_1_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_toint = stq_uop_1_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_toint = stq_uop_1_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_fastpipe = stq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_fastpipe = stq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_fma = stq_uop_1_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_fma = stq_uop_1_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_div = stq_uop_1_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_div = stq_uop_1_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_sqrt = stq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_sqrt = stq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_wflags = stq_uop_1_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_wflags = stq_uop_1_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_vec = stq_uop_1_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_vec = stq_uop_1_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_3_rob_idx = stq_uop_1_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_rob_idx = stq_uop_1_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_1_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_3_ldq_idx = stq_uop_1_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_2_ldq_idx = stq_uop_1_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_1_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_3_stq_idx = stq_uop_1_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_2_stq_idx = stq_uop_1_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_3_rxq_idx = stq_uop_1_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_rxq_idx = stq_uop_1_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_3_pdst = stq_uop_1_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_pdst = stq_uop_1_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_3_prs1 = stq_uop_1_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_prs1 = stq_uop_1_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_3_prs2 = stq_uop_1_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_prs2 = stq_uop_1_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_3_prs3 = stq_uop_1_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_prs3 = stq_uop_1_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_3_ppred = stq_uop_1_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_ppred = stq_uop_1_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_prs1_busy; // @[lsu.scala:252:32] wire s_uop_3_prs1_busy = stq_uop_1_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_prs1_busy = stq_uop_1_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_prs2_busy; // @[lsu.scala:252:32] wire s_uop_3_prs2_busy = stq_uop_1_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_prs2_busy = stq_uop_1_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_prs3_busy; // @[lsu.scala:252:32] wire s_uop_3_prs3_busy = stq_uop_1_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_prs3_busy = stq_uop_1_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_ppred_busy; // @[lsu.scala:252:32] wire s_uop_3_ppred_busy = stq_uop_1_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_ppred_busy = stq_uop_1_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_3_stale_pdst = stq_uop_1_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_stale_pdst = stq_uop_1_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_exception; // @[lsu.scala:252:32] wire s_uop_3_exception = stq_uop_1_exception; // @[lsu.scala:252:32, :1324:37] wire uop_2_exception = stq_uop_1_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_1_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_3_exc_cause = stq_uop_1_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_2_exc_cause = stq_uop_1_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_3_mem_cmd = stq_uop_1_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_mem_cmd = stq_uop_1_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_3_mem_size = stq_uop_1_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_mem_size = stq_uop_1_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_mem_signed; // @[lsu.scala:252:32] wire s_uop_3_mem_signed = stq_uop_1_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_2_mem_signed = stq_uop_1_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_uses_ldq; // @[lsu.scala:252:32] wire s_uop_3_uses_ldq = stq_uop_1_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_2_uses_ldq = stq_uop_1_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_uses_stq; // @[lsu.scala:252:32] wire s_uop_3_uses_stq = stq_uop_1_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_2_uses_stq = stq_uop_1_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_unique; // @[lsu.scala:252:32] wire s_uop_3_is_unique = stq_uop_1_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_unique = stq_uop_1_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_3_flush_on_commit = stq_uop_1_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_2_flush_on_commit = stq_uop_1_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_3_csr_cmd = stq_uop_1_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_csr_cmd = stq_uop_1_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_3_ldst_is_rs1 = stq_uop_1_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_2_ldst_is_rs1 = stq_uop_1_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_3_ldst = stq_uop_1_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_ldst = stq_uop_1_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_3_lrs1 = stq_uop_1_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_lrs1 = stq_uop_1_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_3_lrs2 = stq_uop_1_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_lrs2 = stq_uop_1_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_3_lrs3 = stq_uop_1_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_lrs3 = stq_uop_1_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_3_dst_rtype = stq_uop_1_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_dst_rtype = stq_uop_1_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_3_lrs1_rtype = stq_uop_1_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_lrs1_rtype = stq_uop_1_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_3_lrs2_rtype = stq_uop_1_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_lrs2_rtype = stq_uop_1_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_frs3_en; // @[lsu.scala:252:32] wire s_uop_3_frs3_en = stq_uop_1_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_2_frs3_en = stq_uop_1_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fcn_dw; // @[lsu.scala:252:32] wire s_uop_3_fcn_dw = stq_uop_1_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_2_fcn_dw = stq_uop_1_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_3_fcn_op = stq_uop_1_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_fcn_op = stq_uop_1_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_val; // @[lsu.scala:252:32] wire s_uop_3_fp_val = stq_uop_1_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_val = stq_uop_1_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_3_fp_rm = stq_uop_1_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_fp_rm = stq_uop_1_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_3_fp_typ = stq_uop_1_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_fp_typ = stq_uop_1_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_3_xcpt_pf_if = stq_uop_1_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_xcpt_pf_if = stq_uop_1_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_3_xcpt_ae_if = stq_uop_1_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_xcpt_ae_if = stq_uop_1_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_3_xcpt_ma_if = stq_uop_1_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_xcpt_ma_if = stq_uop_1_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_3_bp_debug_if = stq_uop_1_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_bp_debug_if = stq_uop_1_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_3_bp_xcpt_if = stq_uop_1_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_bp_xcpt_if = stq_uop_1_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_3_debug_fsrc = stq_uop_1_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_debug_fsrc = stq_uop_1_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_3_debug_tsrc = stq_uop_1_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_debug_tsrc = stq_uop_1_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_2_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_4_inst = stq_uop_2_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_3_inst = stq_uop_2_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_2_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_4_debug_inst = stq_uop_2_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_3_debug_inst = stq_uop_2_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_rvc; // @[lsu.scala:252:32] wire s_uop_4_is_rvc = stq_uop_2_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_rvc = stq_uop_2_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_2_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_4_debug_pc = stq_uop_2_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_3_debug_pc = stq_uop_2_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_0; // @[lsu.scala:252:32] wire s_uop_4_iq_type_0 = stq_uop_2_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_0 = stq_uop_2_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_1; // @[lsu.scala:252:32] wire s_uop_4_iq_type_1 = stq_uop_2_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_1 = stq_uop_2_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_2; // @[lsu.scala:252:32] wire s_uop_4_iq_type_2 = stq_uop_2_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_2 = stq_uop_2_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_3; // @[lsu.scala:252:32] wire s_uop_4_iq_type_3 = stq_uop_2_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_3 = stq_uop_2_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_0; // @[lsu.scala:252:32] wire s_uop_4_fu_code_0 = stq_uop_2_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_0 = stq_uop_2_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_1; // @[lsu.scala:252:32] wire s_uop_4_fu_code_1 = stq_uop_2_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_1 = stq_uop_2_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_2; // @[lsu.scala:252:32] wire s_uop_4_fu_code_2 = stq_uop_2_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_2 = stq_uop_2_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_3; // @[lsu.scala:252:32] wire s_uop_4_fu_code_3 = stq_uop_2_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_3 = stq_uop_2_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_4; // @[lsu.scala:252:32] wire s_uop_4_fu_code_4 = stq_uop_2_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_4 = stq_uop_2_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_5; // @[lsu.scala:252:32] wire s_uop_4_fu_code_5 = stq_uop_2_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_5 = stq_uop_2_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_6; // @[lsu.scala:252:32] wire s_uop_4_fu_code_6 = stq_uop_2_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_6 = stq_uop_2_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_7; // @[lsu.scala:252:32] wire s_uop_4_fu_code_7 = stq_uop_2_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_7 = stq_uop_2_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_8; // @[lsu.scala:252:32] wire s_uop_4_fu_code_8 = stq_uop_2_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_8 = stq_uop_2_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_9; // @[lsu.scala:252:32] wire s_uop_4_fu_code_9 = stq_uop_2_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_9 = stq_uop_2_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_issued; // @[lsu.scala:252:32] wire s_uop_4_iw_issued = stq_uop_2_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_issued = stq_uop_2_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_4_iw_issued_partial_agen = stq_uop_2_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_issued_partial_agen = stq_uop_2_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_4_iw_issued_partial_dgen = stq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_issued_partial_dgen = stq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_4_iw_p1_speculative_child = stq_uop_2_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_iw_p1_speculative_child = stq_uop_2_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_4_iw_p2_speculative_child = stq_uop_2_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_iw_p2_speculative_child = stq_uop_2_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_4_iw_p1_bypass_hint = stq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_p1_bypass_hint = stq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_4_iw_p2_bypass_hint = stq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_p2_bypass_hint = stq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_4_iw_p3_bypass_hint = stq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_p3_bypass_hint = stq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_4_dis_col_sel = stq_uop_2_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_dis_col_sel = stq_uop_2_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_2_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_4_br_mask = stq_uop_2_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_3_br_mask = stq_uop_2_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_2_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_4_br_tag = stq_uop_2_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_3_br_tag = stq_uop_2_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_2_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_4_br_type = stq_uop_2_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_3_br_type = stq_uop_2_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_sfb; // @[lsu.scala:252:32] wire s_uop_4_is_sfb = stq_uop_2_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_sfb = stq_uop_2_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_fence; // @[lsu.scala:252:32] wire s_uop_4_is_fence = stq_uop_2_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_fence = stq_uop_2_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_fencei; // @[lsu.scala:252:32] wire s_uop_4_is_fencei = stq_uop_2_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_fencei = stq_uop_2_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_sfence; // @[lsu.scala:252:32] wire s_uop_4_is_sfence = stq_uop_2_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_sfence = stq_uop_2_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_amo; // @[lsu.scala:252:32] wire s_uop_4_is_amo = stq_uop_2_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_amo = stq_uop_2_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_eret; // @[lsu.scala:252:32] wire s_uop_4_is_eret = stq_uop_2_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_eret = stq_uop_2_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_4_is_sys_pc2epc = stq_uop_2_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_sys_pc2epc = stq_uop_2_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_rocc; // @[lsu.scala:252:32] wire s_uop_4_is_rocc = stq_uop_2_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_rocc = stq_uop_2_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_mov; // @[lsu.scala:252:32] wire s_uop_4_is_mov = stq_uop_2_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_mov = stq_uop_2_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_4_ftq_idx = stq_uop_2_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_ftq_idx = stq_uop_2_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_edge_inst; // @[lsu.scala:252:32] wire s_uop_4_edge_inst = stq_uop_2_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_3_edge_inst = stq_uop_2_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_4_pc_lob = stq_uop_2_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_pc_lob = stq_uop_2_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_taken; // @[lsu.scala:252:32] wire s_uop_4_taken = stq_uop_2_taken; // @[lsu.scala:252:32, :1324:37] wire uop_3_taken = stq_uop_2_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_imm_rename; // @[lsu.scala:252:32] wire s_uop_4_imm_rename = stq_uop_2_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_3_imm_rename = stq_uop_2_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_4_imm_sel = stq_uop_2_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_imm_sel = stq_uop_2_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_4_pimm = stq_uop_2_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_pimm = stq_uop_2_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_2_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_4_imm_packed = stq_uop_2_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_3_imm_packed = stq_uop_2_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_4_op1_sel = stq_uop_2_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_op1_sel = stq_uop_2_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_4_op2_sel = stq_uop_2_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_op2_sel = stq_uop_2_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ldst = stq_uop_2_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ldst = stq_uop_2_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_wen = stq_uop_2_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_wen = stq_uop_2_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ren1 = stq_uop_2_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ren1 = stq_uop_2_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ren2 = stq_uop_2_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ren2 = stq_uop_2_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ren3 = stq_uop_2_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ren3 = stq_uop_2_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_swap12 = stq_uop_2_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_swap12 = stq_uop_2_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_swap23 = stq_uop_2_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_swap23 = stq_uop_2_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_4_fp_ctrl_typeTagIn = stq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_fp_ctrl_typeTagIn = stq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_4_fp_ctrl_typeTagOut = stq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_fp_ctrl_typeTagOut = stq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_fromint = stq_uop_2_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_fromint = stq_uop_2_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_toint = stq_uop_2_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_toint = stq_uop_2_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_fastpipe = stq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_fastpipe = stq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_fma = stq_uop_2_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_fma = stq_uop_2_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_div = stq_uop_2_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_div = stq_uop_2_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_sqrt = stq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_sqrt = stq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_wflags = stq_uop_2_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_wflags = stq_uop_2_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_vec = stq_uop_2_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_vec = stq_uop_2_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_4_rob_idx = stq_uop_2_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_rob_idx = stq_uop_2_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_2_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_4_ldq_idx = stq_uop_2_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_3_ldq_idx = stq_uop_2_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_2_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_4_stq_idx = stq_uop_2_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_3_stq_idx = stq_uop_2_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_4_rxq_idx = stq_uop_2_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_rxq_idx = stq_uop_2_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_4_pdst = stq_uop_2_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_pdst = stq_uop_2_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_4_prs1 = stq_uop_2_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_prs1 = stq_uop_2_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_4_prs2 = stq_uop_2_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_prs2 = stq_uop_2_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_4_prs3 = stq_uop_2_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_prs3 = stq_uop_2_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_4_ppred = stq_uop_2_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_ppred = stq_uop_2_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_prs1_busy; // @[lsu.scala:252:32] wire s_uop_4_prs1_busy = stq_uop_2_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_prs1_busy = stq_uop_2_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_prs2_busy; // @[lsu.scala:252:32] wire s_uop_4_prs2_busy = stq_uop_2_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_prs2_busy = stq_uop_2_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_prs3_busy; // @[lsu.scala:252:32] wire s_uop_4_prs3_busy = stq_uop_2_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_prs3_busy = stq_uop_2_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_ppred_busy; // @[lsu.scala:252:32] wire s_uop_4_ppred_busy = stq_uop_2_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_ppred_busy = stq_uop_2_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_4_stale_pdst = stq_uop_2_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_stale_pdst = stq_uop_2_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_exception; // @[lsu.scala:252:32] wire s_uop_4_exception = stq_uop_2_exception; // @[lsu.scala:252:32, :1324:37] wire uop_3_exception = stq_uop_2_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_2_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_4_exc_cause = stq_uop_2_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_3_exc_cause = stq_uop_2_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_4_mem_cmd = stq_uop_2_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_mem_cmd = stq_uop_2_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_4_mem_size = stq_uop_2_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_mem_size = stq_uop_2_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_mem_signed; // @[lsu.scala:252:32] wire s_uop_4_mem_signed = stq_uop_2_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_3_mem_signed = stq_uop_2_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_uses_ldq; // @[lsu.scala:252:32] wire s_uop_4_uses_ldq = stq_uop_2_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_3_uses_ldq = stq_uop_2_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_uses_stq; // @[lsu.scala:252:32] wire s_uop_4_uses_stq = stq_uop_2_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_3_uses_stq = stq_uop_2_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_unique; // @[lsu.scala:252:32] wire s_uop_4_is_unique = stq_uop_2_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_unique = stq_uop_2_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_4_flush_on_commit = stq_uop_2_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_3_flush_on_commit = stq_uop_2_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_4_csr_cmd = stq_uop_2_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_csr_cmd = stq_uop_2_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_4_ldst_is_rs1 = stq_uop_2_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_3_ldst_is_rs1 = stq_uop_2_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_4_ldst = stq_uop_2_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_ldst = stq_uop_2_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_4_lrs1 = stq_uop_2_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_lrs1 = stq_uop_2_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_4_lrs2 = stq_uop_2_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_lrs2 = stq_uop_2_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_4_lrs3 = stq_uop_2_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_lrs3 = stq_uop_2_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_4_dst_rtype = stq_uop_2_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_dst_rtype = stq_uop_2_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_4_lrs1_rtype = stq_uop_2_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_lrs1_rtype = stq_uop_2_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_4_lrs2_rtype = stq_uop_2_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_lrs2_rtype = stq_uop_2_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_frs3_en; // @[lsu.scala:252:32] wire s_uop_4_frs3_en = stq_uop_2_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_3_frs3_en = stq_uop_2_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fcn_dw; // @[lsu.scala:252:32] wire s_uop_4_fcn_dw = stq_uop_2_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_3_fcn_dw = stq_uop_2_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_4_fcn_op = stq_uop_2_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_fcn_op = stq_uop_2_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_val; // @[lsu.scala:252:32] wire s_uop_4_fp_val = stq_uop_2_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_val = stq_uop_2_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_4_fp_rm = stq_uop_2_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_fp_rm = stq_uop_2_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_4_fp_typ = stq_uop_2_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_fp_typ = stq_uop_2_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_4_xcpt_pf_if = stq_uop_2_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_xcpt_pf_if = stq_uop_2_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_4_xcpt_ae_if = stq_uop_2_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_xcpt_ae_if = stq_uop_2_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_4_xcpt_ma_if = stq_uop_2_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_xcpt_ma_if = stq_uop_2_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_4_bp_debug_if = stq_uop_2_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_bp_debug_if = stq_uop_2_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_4_bp_xcpt_if = stq_uop_2_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_bp_xcpt_if = stq_uop_2_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_4_debug_fsrc = stq_uop_2_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_debug_fsrc = stq_uop_2_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_4_debug_tsrc = stq_uop_2_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_debug_tsrc = stq_uop_2_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_3_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_5_inst = stq_uop_3_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_4_inst = stq_uop_3_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_3_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_5_debug_inst = stq_uop_3_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_4_debug_inst = stq_uop_3_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_rvc; // @[lsu.scala:252:32] wire s_uop_5_is_rvc = stq_uop_3_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_rvc = stq_uop_3_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_3_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_5_debug_pc = stq_uop_3_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_4_debug_pc = stq_uop_3_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_0; // @[lsu.scala:252:32] wire s_uop_5_iq_type_0 = stq_uop_3_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_0 = stq_uop_3_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_1; // @[lsu.scala:252:32] wire s_uop_5_iq_type_1 = stq_uop_3_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_1 = stq_uop_3_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_2; // @[lsu.scala:252:32] wire s_uop_5_iq_type_2 = stq_uop_3_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_2 = stq_uop_3_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_3; // @[lsu.scala:252:32] wire s_uop_5_iq_type_3 = stq_uop_3_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_3 = stq_uop_3_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_0; // @[lsu.scala:252:32] wire s_uop_5_fu_code_0 = stq_uop_3_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_0 = stq_uop_3_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_1; // @[lsu.scala:252:32] wire s_uop_5_fu_code_1 = stq_uop_3_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_1 = stq_uop_3_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_2; // @[lsu.scala:252:32] wire s_uop_5_fu_code_2 = stq_uop_3_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_2 = stq_uop_3_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_3; // @[lsu.scala:252:32] wire s_uop_5_fu_code_3 = stq_uop_3_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_3 = stq_uop_3_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_4; // @[lsu.scala:252:32] wire s_uop_5_fu_code_4 = stq_uop_3_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_4 = stq_uop_3_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_5; // @[lsu.scala:252:32] wire s_uop_5_fu_code_5 = stq_uop_3_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_5 = stq_uop_3_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_6; // @[lsu.scala:252:32] wire s_uop_5_fu_code_6 = stq_uop_3_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_6 = stq_uop_3_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_7; // @[lsu.scala:252:32] wire s_uop_5_fu_code_7 = stq_uop_3_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_7 = stq_uop_3_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_8; // @[lsu.scala:252:32] wire s_uop_5_fu_code_8 = stq_uop_3_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_8 = stq_uop_3_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_9; // @[lsu.scala:252:32] wire s_uop_5_fu_code_9 = stq_uop_3_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_9 = stq_uop_3_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_issued; // @[lsu.scala:252:32] wire s_uop_5_iw_issued = stq_uop_3_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_issued = stq_uop_3_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_5_iw_issued_partial_agen = stq_uop_3_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_issued_partial_agen = stq_uop_3_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_5_iw_issued_partial_dgen = stq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_issued_partial_dgen = stq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_5_iw_p1_speculative_child = stq_uop_3_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_iw_p1_speculative_child = stq_uop_3_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_5_iw_p2_speculative_child = stq_uop_3_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_iw_p2_speculative_child = stq_uop_3_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_5_iw_p1_bypass_hint = stq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_p1_bypass_hint = stq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_5_iw_p2_bypass_hint = stq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_p2_bypass_hint = stq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_5_iw_p3_bypass_hint = stq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_p3_bypass_hint = stq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_5_dis_col_sel = stq_uop_3_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_dis_col_sel = stq_uop_3_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_3_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_5_br_mask = stq_uop_3_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_4_br_mask = stq_uop_3_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_3_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_5_br_tag = stq_uop_3_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_4_br_tag = stq_uop_3_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_3_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_5_br_type = stq_uop_3_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_4_br_type = stq_uop_3_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_sfb; // @[lsu.scala:252:32] wire s_uop_5_is_sfb = stq_uop_3_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_sfb = stq_uop_3_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_fence; // @[lsu.scala:252:32] wire s_uop_5_is_fence = stq_uop_3_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_fence = stq_uop_3_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_fencei; // @[lsu.scala:252:32] wire s_uop_5_is_fencei = stq_uop_3_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_fencei = stq_uop_3_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_sfence; // @[lsu.scala:252:32] wire s_uop_5_is_sfence = stq_uop_3_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_sfence = stq_uop_3_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_amo; // @[lsu.scala:252:32] wire s_uop_5_is_amo = stq_uop_3_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_amo = stq_uop_3_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_eret; // @[lsu.scala:252:32] wire s_uop_5_is_eret = stq_uop_3_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_eret = stq_uop_3_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_5_is_sys_pc2epc = stq_uop_3_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_sys_pc2epc = stq_uop_3_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_rocc; // @[lsu.scala:252:32] wire s_uop_5_is_rocc = stq_uop_3_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_rocc = stq_uop_3_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_mov; // @[lsu.scala:252:32] wire s_uop_5_is_mov = stq_uop_3_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_mov = stq_uop_3_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_5_ftq_idx = stq_uop_3_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_ftq_idx = stq_uop_3_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_edge_inst; // @[lsu.scala:252:32] wire s_uop_5_edge_inst = stq_uop_3_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_4_edge_inst = stq_uop_3_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_5_pc_lob = stq_uop_3_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_pc_lob = stq_uop_3_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_taken; // @[lsu.scala:252:32] wire s_uop_5_taken = stq_uop_3_taken; // @[lsu.scala:252:32, :1324:37] wire uop_4_taken = stq_uop_3_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_imm_rename; // @[lsu.scala:252:32] wire s_uop_5_imm_rename = stq_uop_3_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_4_imm_rename = stq_uop_3_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_5_imm_sel = stq_uop_3_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_imm_sel = stq_uop_3_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_5_pimm = stq_uop_3_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_pimm = stq_uop_3_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_3_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_5_imm_packed = stq_uop_3_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_4_imm_packed = stq_uop_3_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_5_op1_sel = stq_uop_3_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_op1_sel = stq_uop_3_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_5_op2_sel = stq_uop_3_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_op2_sel = stq_uop_3_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ldst = stq_uop_3_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ldst = stq_uop_3_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_wen = stq_uop_3_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_wen = stq_uop_3_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ren1 = stq_uop_3_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ren1 = stq_uop_3_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ren2 = stq_uop_3_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ren2 = stq_uop_3_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ren3 = stq_uop_3_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ren3 = stq_uop_3_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_swap12 = stq_uop_3_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_swap12 = stq_uop_3_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_swap23 = stq_uop_3_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_swap23 = stq_uop_3_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_5_fp_ctrl_typeTagIn = stq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_fp_ctrl_typeTagIn = stq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_5_fp_ctrl_typeTagOut = stq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_fp_ctrl_typeTagOut = stq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_fromint = stq_uop_3_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_fromint = stq_uop_3_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_toint = stq_uop_3_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_toint = stq_uop_3_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_fastpipe = stq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_fastpipe = stq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_fma = stq_uop_3_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_fma = stq_uop_3_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_div = stq_uop_3_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_div = stq_uop_3_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_sqrt = stq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_sqrt = stq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_wflags = stq_uop_3_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_wflags = stq_uop_3_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_vec = stq_uop_3_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_vec = stq_uop_3_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_5_rob_idx = stq_uop_3_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_rob_idx = stq_uop_3_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_3_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_5_ldq_idx = stq_uop_3_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_4_ldq_idx = stq_uop_3_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_3_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_5_stq_idx = stq_uop_3_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_4_stq_idx = stq_uop_3_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_5_rxq_idx = stq_uop_3_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_rxq_idx = stq_uop_3_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_5_pdst = stq_uop_3_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_pdst = stq_uop_3_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_5_prs1 = stq_uop_3_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_prs1 = stq_uop_3_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_5_prs2 = stq_uop_3_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_prs2 = stq_uop_3_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_5_prs3 = stq_uop_3_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_prs3 = stq_uop_3_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_5_ppred = stq_uop_3_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_ppred = stq_uop_3_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_prs1_busy; // @[lsu.scala:252:32] wire s_uop_5_prs1_busy = stq_uop_3_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_prs1_busy = stq_uop_3_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_prs2_busy; // @[lsu.scala:252:32] wire s_uop_5_prs2_busy = stq_uop_3_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_prs2_busy = stq_uop_3_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_prs3_busy; // @[lsu.scala:252:32] wire s_uop_5_prs3_busy = stq_uop_3_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_prs3_busy = stq_uop_3_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_ppred_busy; // @[lsu.scala:252:32] wire s_uop_5_ppred_busy = stq_uop_3_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_ppred_busy = stq_uop_3_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_5_stale_pdst = stq_uop_3_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_stale_pdst = stq_uop_3_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_exception; // @[lsu.scala:252:32] wire s_uop_5_exception = stq_uop_3_exception; // @[lsu.scala:252:32, :1324:37] wire uop_4_exception = stq_uop_3_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_3_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_5_exc_cause = stq_uop_3_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_4_exc_cause = stq_uop_3_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_5_mem_cmd = stq_uop_3_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_mem_cmd = stq_uop_3_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_5_mem_size = stq_uop_3_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_mem_size = stq_uop_3_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_mem_signed; // @[lsu.scala:252:32] wire s_uop_5_mem_signed = stq_uop_3_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_4_mem_signed = stq_uop_3_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_uses_ldq; // @[lsu.scala:252:32] wire s_uop_5_uses_ldq = stq_uop_3_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_4_uses_ldq = stq_uop_3_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_uses_stq; // @[lsu.scala:252:32] wire s_uop_5_uses_stq = stq_uop_3_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_4_uses_stq = stq_uop_3_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_unique; // @[lsu.scala:252:32] wire s_uop_5_is_unique = stq_uop_3_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_unique = stq_uop_3_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_5_flush_on_commit = stq_uop_3_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_4_flush_on_commit = stq_uop_3_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_5_csr_cmd = stq_uop_3_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_csr_cmd = stq_uop_3_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_5_ldst_is_rs1 = stq_uop_3_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_4_ldst_is_rs1 = stq_uop_3_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_5_ldst = stq_uop_3_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_ldst = stq_uop_3_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_5_lrs1 = stq_uop_3_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_lrs1 = stq_uop_3_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_5_lrs2 = stq_uop_3_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_lrs2 = stq_uop_3_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_5_lrs3 = stq_uop_3_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_lrs3 = stq_uop_3_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_5_dst_rtype = stq_uop_3_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_dst_rtype = stq_uop_3_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_5_lrs1_rtype = stq_uop_3_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_lrs1_rtype = stq_uop_3_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_5_lrs2_rtype = stq_uop_3_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_lrs2_rtype = stq_uop_3_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_frs3_en; // @[lsu.scala:252:32] wire s_uop_5_frs3_en = stq_uop_3_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_4_frs3_en = stq_uop_3_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fcn_dw; // @[lsu.scala:252:32] wire s_uop_5_fcn_dw = stq_uop_3_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_4_fcn_dw = stq_uop_3_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_5_fcn_op = stq_uop_3_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_fcn_op = stq_uop_3_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_val; // @[lsu.scala:252:32] wire s_uop_5_fp_val = stq_uop_3_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_val = stq_uop_3_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_5_fp_rm = stq_uop_3_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_fp_rm = stq_uop_3_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_5_fp_typ = stq_uop_3_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_fp_typ = stq_uop_3_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_5_xcpt_pf_if = stq_uop_3_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_xcpt_pf_if = stq_uop_3_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_5_xcpt_ae_if = stq_uop_3_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_xcpt_ae_if = stq_uop_3_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_5_xcpt_ma_if = stq_uop_3_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_xcpt_ma_if = stq_uop_3_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_5_bp_debug_if = stq_uop_3_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_bp_debug_if = stq_uop_3_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_5_bp_xcpt_if = stq_uop_3_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_bp_xcpt_if = stq_uop_3_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_5_debug_fsrc = stq_uop_3_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_debug_fsrc = stq_uop_3_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_5_debug_tsrc = stq_uop_3_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_debug_tsrc = stq_uop_3_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_4_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_6_inst = stq_uop_4_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_5_inst = stq_uop_4_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_4_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_6_debug_inst = stq_uop_4_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_5_debug_inst = stq_uop_4_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_rvc; // @[lsu.scala:252:32] wire s_uop_6_is_rvc = stq_uop_4_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_rvc = stq_uop_4_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_4_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_6_debug_pc = stq_uop_4_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_5_debug_pc = stq_uop_4_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_0; // @[lsu.scala:252:32] wire s_uop_6_iq_type_0 = stq_uop_4_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_0 = stq_uop_4_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_1; // @[lsu.scala:252:32] wire s_uop_6_iq_type_1 = stq_uop_4_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_1 = stq_uop_4_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_2; // @[lsu.scala:252:32] wire s_uop_6_iq_type_2 = stq_uop_4_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_2 = stq_uop_4_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_3; // @[lsu.scala:252:32] wire s_uop_6_iq_type_3 = stq_uop_4_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_3 = stq_uop_4_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_0; // @[lsu.scala:252:32] wire s_uop_6_fu_code_0 = stq_uop_4_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_0 = stq_uop_4_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_1; // @[lsu.scala:252:32] wire s_uop_6_fu_code_1 = stq_uop_4_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_1 = stq_uop_4_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_2; // @[lsu.scala:252:32] wire s_uop_6_fu_code_2 = stq_uop_4_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_2 = stq_uop_4_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_3; // @[lsu.scala:252:32] wire s_uop_6_fu_code_3 = stq_uop_4_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_3 = stq_uop_4_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_4; // @[lsu.scala:252:32] wire s_uop_6_fu_code_4 = stq_uop_4_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_4 = stq_uop_4_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_5; // @[lsu.scala:252:32] wire s_uop_6_fu_code_5 = stq_uop_4_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_5 = stq_uop_4_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_6; // @[lsu.scala:252:32] wire s_uop_6_fu_code_6 = stq_uop_4_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_6 = stq_uop_4_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_7; // @[lsu.scala:252:32] wire s_uop_6_fu_code_7 = stq_uop_4_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_7 = stq_uop_4_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_8; // @[lsu.scala:252:32] wire s_uop_6_fu_code_8 = stq_uop_4_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_8 = stq_uop_4_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_9; // @[lsu.scala:252:32] wire s_uop_6_fu_code_9 = stq_uop_4_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_9 = stq_uop_4_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_issued; // @[lsu.scala:252:32] wire s_uop_6_iw_issued = stq_uop_4_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_issued = stq_uop_4_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_6_iw_issued_partial_agen = stq_uop_4_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_issued_partial_agen = stq_uop_4_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_6_iw_issued_partial_dgen = stq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_issued_partial_dgen = stq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_6_iw_p1_speculative_child = stq_uop_4_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_iw_p1_speculative_child = stq_uop_4_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_6_iw_p2_speculative_child = stq_uop_4_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_iw_p2_speculative_child = stq_uop_4_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_6_iw_p1_bypass_hint = stq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_p1_bypass_hint = stq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_6_iw_p2_bypass_hint = stq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_p2_bypass_hint = stq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_6_iw_p3_bypass_hint = stq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_p3_bypass_hint = stq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_6_dis_col_sel = stq_uop_4_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_dis_col_sel = stq_uop_4_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_4_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_6_br_mask = stq_uop_4_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_5_br_mask = stq_uop_4_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_4_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_6_br_tag = stq_uop_4_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_5_br_tag = stq_uop_4_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_4_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_6_br_type = stq_uop_4_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_5_br_type = stq_uop_4_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_sfb; // @[lsu.scala:252:32] wire s_uop_6_is_sfb = stq_uop_4_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_sfb = stq_uop_4_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_fence; // @[lsu.scala:252:32] wire s_uop_6_is_fence = stq_uop_4_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_fence = stq_uop_4_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_fencei; // @[lsu.scala:252:32] wire s_uop_6_is_fencei = stq_uop_4_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_fencei = stq_uop_4_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_sfence; // @[lsu.scala:252:32] wire s_uop_6_is_sfence = stq_uop_4_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_sfence = stq_uop_4_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_amo; // @[lsu.scala:252:32] wire s_uop_6_is_amo = stq_uop_4_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_amo = stq_uop_4_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_eret; // @[lsu.scala:252:32] wire s_uop_6_is_eret = stq_uop_4_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_eret = stq_uop_4_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_6_is_sys_pc2epc = stq_uop_4_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_sys_pc2epc = stq_uop_4_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_rocc; // @[lsu.scala:252:32] wire s_uop_6_is_rocc = stq_uop_4_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_rocc = stq_uop_4_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_mov; // @[lsu.scala:252:32] wire s_uop_6_is_mov = stq_uop_4_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_mov = stq_uop_4_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_6_ftq_idx = stq_uop_4_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_ftq_idx = stq_uop_4_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_edge_inst; // @[lsu.scala:252:32] wire s_uop_6_edge_inst = stq_uop_4_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_5_edge_inst = stq_uop_4_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_6_pc_lob = stq_uop_4_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_pc_lob = stq_uop_4_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_taken; // @[lsu.scala:252:32] wire s_uop_6_taken = stq_uop_4_taken; // @[lsu.scala:252:32, :1324:37] wire uop_5_taken = stq_uop_4_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_imm_rename; // @[lsu.scala:252:32] wire s_uop_6_imm_rename = stq_uop_4_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_5_imm_rename = stq_uop_4_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_6_imm_sel = stq_uop_4_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_imm_sel = stq_uop_4_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_6_pimm = stq_uop_4_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_pimm = stq_uop_4_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_4_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_6_imm_packed = stq_uop_4_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_5_imm_packed = stq_uop_4_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_6_op1_sel = stq_uop_4_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_op1_sel = stq_uop_4_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_6_op2_sel = stq_uop_4_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_op2_sel = stq_uop_4_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ldst = stq_uop_4_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ldst = stq_uop_4_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_wen = stq_uop_4_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_wen = stq_uop_4_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ren1 = stq_uop_4_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ren1 = stq_uop_4_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ren2 = stq_uop_4_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ren2 = stq_uop_4_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ren3 = stq_uop_4_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ren3 = stq_uop_4_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_swap12 = stq_uop_4_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_swap12 = stq_uop_4_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_swap23 = stq_uop_4_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_swap23 = stq_uop_4_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_6_fp_ctrl_typeTagIn = stq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_fp_ctrl_typeTagIn = stq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_6_fp_ctrl_typeTagOut = stq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_fp_ctrl_typeTagOut = stq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_fromint = stq_uop_4_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_fromint = stq_uop_4_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_toint = stq_uop_4_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_toint = stq_uop_4_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_fastpipe = stq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_fastpipe = stq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_fma = stq_uop_4_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_fma = stq_uop_4_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_div = stq_uop_4_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_div = stq_uop_4_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_sqrt = stq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_sqrt = stq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_wflags = stq_uop_4_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_wflags = stq_uop_4_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_vec = stq_uop_4_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_vec = stq_uop_4_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_6_rob_idx = stq_uop_4_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_rob_idx = stq_uop_4_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_4_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_6_ldq_idx = stq_uop_4_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_5_ldq_idx = stq_uop_4_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_4_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_6_stq_idx = stq_uop_4_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_5_stq_idx = stq_uop_4_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_6_rxq_idx = stq_uop_4_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_rxq_idx = stq_uop_4_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_6_pdst = stq_uop_4_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_pdst = stq_uop_4_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_6_prs1 = stq_uop_4_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_prs1 = stq_uop_4_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_6_prs2 = stq_uop_4_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_prs2 = stq_uop_4_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_6_prs3 = stq_uop_4_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_prs3 = stq_uop_4_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_6_ppred = stq_uop_4_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_ppred = stq_uop_4_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_prs1_busy; // @[lsu.scala:252:32] wire s_uop_6_prs1_busy = stq_uop_4_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_prs1_busy = stq_uop_4_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_prs2_busy; // @[lsu.scala:252:32] wire s_uop_6_prs2_busy = stq_uop_4_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_prs2_busy = stq_uop_4_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_prs3_busy; // @[lsu.scala:252:32] wire s_uop_6_prs3_busy = stq_uop_4_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_prs3_busy = stq_uop_4_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_ppred_busy; // @[lsu.scala:252:32] wire s_uop_6_ppred_busy = stq_uop_4_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_ppred_busy = stq_uop_4_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_6_stale_pdst = stq_uop_4_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_stale_pdst = stq_uop_4_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_exception; // @[lsu.scala:252:32] wire s_uop_6_exception = stq_uop_4_exception; // @[lsu.scala:252:32, :1324:37] wire uop_5_exception = stq_uop_4_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_4_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_6_exc_cause = stq_uop_4_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_5_exc_cause = stq_uop_4_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_6_mem_cmd = stq_uop_4_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_mem_cmd = stq_uop_4_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_6_mem_size = stq_uop_4_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_mem_size = stq_uop_4_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_mem_signed; // @[lsu.scala:252:32] wire s_uop_6_mem_signed = stq_uop_4_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_5_mem_signed = stq_uop_4_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_uses_ldq; // @[lsu.scala:252:32] wire s_uop_6_uses_ldq = stq_uop_4_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_5_uses_ldq = stq_uop_4_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_uses_stq; // @[lsu.scala:252:32] wire s_uop_6_uses_stq = stq_uop_4_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_5_uses_stq = stq_uop_4_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_unique; // @[lsu.scala:252:32] wire s_uop_6_is_unique = stq_uop_4_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_unique = stq_uop_4_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_6_flush_on_commit = stq_uop_4_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_5_flush_on_commit = stq_uop_4_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_6_csr_cmd = stq_uop_4_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_csr_cmd = stq_uop_4_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_6_ldst_is_rs1 = stq_uop_4_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_5_ldst_is_rs1 = stq_uop_4_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_6_ldst = stq_uop_4_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_ldst = stq_uop_4_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_6_lrs1 = stq_uop_4_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_lrs1 = stq_uop_4_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_6_lrs2 = stq_uop_4_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_lrs2 = stq_uop_4_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_6_lrs3 = stq_uop_4_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_lrs3 = stq_uop_4_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_6_dst_rtype = stq_uop_4_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_dst_rtype = stq_uop_4_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_6_lrs1_rtype = stq_uop_4_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_lrs1_rtype = stq_uop_4_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_6_lrs2_rtype = stq_uop_4_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_lrs2_rtype = stq_uop_4_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_frs3_en; // @[lsu.scala:252:32] wire s_uop_6_frs3_en = stq_uop_4_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_5_frs3_en = stq_uop_4_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fcn_dw; // @[lsu.scala:252:32] wire s_uop_6_fcn_dw = stq_uop_4_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_5_fcn_dw = stq_uop_4_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_6_fcn_op = stq_uop_4_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_fcn_op = stq_uop_4_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_val; // @[lsu.scala:252:32] wire s_uop_6_fp_val = stq_uop_4_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_val = stq_uop_4_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_6_fp_rm = stq_uop_4_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_fp_rm = stq_uop_4_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_6_fp_typ = stq_uop_4_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_fp_typ = stq_uop_4_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_6_xcpt_pf_if = stq_uop_4_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_xcpt_pf_if = stq_uop_4_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_6_xcpt_ae_if = stq_uop_4_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_xcpt_ae_if = stq_uop_4_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_6_xcpt_ma_if = stq_uop_4_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_xcpt_ma_if = stq_uop_4_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_6_bp_debug_if = stq_uop_4_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_bp_debug_if = stq_uop_4_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_6_bp_xcpt_if = stq_uop_4_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_bp_xcpt_if = stq_uop_4_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_6_debug_fsrc = stq_uop_4_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_debug_fsrc = stq_uop_4_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_6_debug_tsrc = stq_uop_4_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_debug_tsrc = stq_uop_4_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_5_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_7_inst = stq_uop_5_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_6_inst = stq_uop_5_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_5_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_7_debug_inst = stq_uop_5_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_6_debug_inst = stq_uop_5_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_rvc; // @[lsu.scala:252:32] wire s_uop_7_is_rvc = stq_uop_5_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_rvc = stq_uop_5_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_5_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_7_debug_pc = stq_uop_5_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_6_debug_pc = stq_uop_5_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_0; // @[lsu.scala:252:32] wire s_uop_7_iq_type_0 = stq_uop_5_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_0 = stq_uop_5_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_1; // @[lsu.scala:252:32] wire s_uop_7_iq_type_1 = stq_uop_5_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_1 = stq_uop_5_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_2; // @[lsu.scala:252:32] wire s_uop_7_iq_type_2 = stq_uop_5_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_2 = stq_uop_5_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_3; // @[lsu.scala:252:32] wire s_uop_7_iq_type_3 = stq_uop_5_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_3 = stq_uop_5_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_0; // @[lsu.scala:252:32] wire s_uop_7_fu_code_0 = stq_uop_5_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_0 = stq_uop_5_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_1; // @[lsu.scala:252:32] wire s_uop_7_fu_code_1 = stq_uop_5_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_1 = stq_uop_5_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_2; // @[lsu.scala:252:32] wire s_uop_7_fu_code_2 = stq_uop_5_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_2 = stq_uop_5_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_3; // @[lsu.scala:252:32] wire s_uop_7_fu_code_3 = stq_uop_5_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_3 = stq_uop_5_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_4; // @[lsu.scala:252:32] wire s_uop_7_fu_code_4 = stq_uop_5_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_4 = stq_uop_5_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_5; // @[lsu.scala:252:32] wire s_uop_7_fu_code_5 = stq_uop_5_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_5 = stq_uop_5_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_6; // @[lsu.scala:252:32] wire s_uop_7_fu_code_6 = stq_uop_5_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_6 = stq_uop_5_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_7; // @[lsu.scala:252:32] wire s_uop_7_fu_code_7 = stq_uop_5_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_7 = stq_uop_5_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_8; // @[lsu.scala:252:32] wire s_uop_7_fu_code_8 = stq_uop_5_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_8 = stq_uop_5_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_9; // @[lsu.scala:252:32] wire s_uop_7_fu_code_9 = stq_uop_5_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_9 = stq_uop_5_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_issued; // @[lsu.scala:252:32] wire s_uop_7_iw_issued = stq_uop_5_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_issued = stq_uop_5_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_7_iw_issued_partial_agen = stq_uop_5_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_issued_partial_agen = stq_uop_5_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_7_iw_issued_partial_dgen = stq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_issued_partial_dgen = stq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_7_iw_p1_speculative_child = stq_uop_5_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_iw_p1_speculative_child = stq_uop_5_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_7_iw_p2_speculative_child = stq_uop_5_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_iw_p2_speculative_child = stq_uop_5_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_7_iw_p1_bypass_hint = stq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_p1_bypass_hint = stq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_7_iw_p2_bypass_hint = stq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_p2_bypass_hint = stq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_7_iw_p3_bypass_hint = stq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_p3_bypass_hint = stq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_7_dis_col_sel = stq_uop_5_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_dis_col_sel = stq_uop_5_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_5_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_7_br_mask = stq_uop_5_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_6_br_mask = stq_uop_5_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_5_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_7_br_tag = stq_uop_5_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_6_br_tag = stq_uop_5_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_5_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_7_br_type = stq_uop_5_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_6_br_type = stq_uop_5_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_sfb; // @[lsu.scala:252:32] wire s_uop_7_is_sfb = stq_uop_5_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_sfb = stq_uop_5_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_fence; // @[lsu.scala:252:32] wire s_uop_7_is_fence = stq_uop_5_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_fence = stq_uop_5_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_fencei; // @[lsu.scala:252:32] wire s_uop_7_is_fencei = stq_uop_5_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_fencei = stq_uop_5_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_sfence; // @[lsu.scala:252:32] wire s_uop_7_is_sfence = stq_uop_5_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_sfence = stq_uop_5_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_amo; // @[lsu.scala:252:32] wire s_uop_7_is_amo = stq_uop_5_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_amo = stq_uop_5_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_eret; // @[lsu.scala:252:32] wire s_uop_7_is_eret = stq_uop_5_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_eret = stq_uop_5_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_7_is_sys_pc2epc = stq_uop_5_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_sys_pc2epc = stq_uop_5_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_rocc; // @[lsu.scala:252:32] wire s_uop_7_is_rocc = stq_uop_5_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_rocc = stq_uop_5_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_mov; // @[lsu.scala:252:32] wire s_uop_7_is_mov = stq_uop_5_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_mov = stq_uop_5_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_7_ftq_idx = stq_uop_5_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_ftq_idx = stq_uop_5_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_edge_inst; // @[lsu.scala:252:32] wire s_uop_7_edge_inst = stq_uop_5_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_6_edge_inst = stq_uop_5_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_7_pc_lob = stq_uop_5_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_pc_lob = stq_uop_5_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_taken; // @[lsu.scala:252:32] wire s_uop_7_taken = stq_uop_5_taken; // @[lsu.scala:252:32, :1324:37] wire uop_6_taken = stq_uop_5_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_imm_rename; // @[lsu.scala:252:32] wire s_uop_7_imm_rename = stq_uop_5_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_6_imm_rename = stq_uop_5_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_7_imm_sel = stq_uop_5_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_imm_sel = stq_uop_5_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_7_pimm = stq_uop_5_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_pimm = stq_uop_5_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_5_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_7_imm_packed = stq_uop_5_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_6_imm_packed = stq_uop_5_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_7_op1_sel = stq_uop_5_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_op1_sel = stq_uop_5_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_7_op2_sel = stq_uop_5_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_op2_sel = stq_uop_5_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ldst = stq_uop_5_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ldst = stq_uop_5_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_wen = stq_uop_5_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_wen = stq_uop_5_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ren1 = stq_uop_5_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ren1 = stq_uop_5_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ren2 = stq_uop_5_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ren2 = stq_uop_5_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ren3 = stq_uop_5_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ren3 = stq_uop_5_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_swap12 = stq_uop_5_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_swap12 = stq_uop_5_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_swap23 = stq_uop_5_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_swap23 = stq_uop_5_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_7_fp_ctrl_typeTagIn = stq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_fp_ctrl_typeTagIn = stq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_7_fp_ctrl_typeTagOut = stq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_fp_ctrl_typeTagOut = stq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_fromint = stq_uop_5_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_fromint = stq_uop_5_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_toint = stq_uop_5_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_toint = stq_uop_5_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_fastpipe = stq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_fastpipe = stq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_fma = stq_uop_5_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_fma = stq_uop_5_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_div = stq_uop_5_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_div = stq_uop_5_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_sqrt = stq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_sqrt = stq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_wflags = stq_uop_5_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_wflags = stq_uop_5_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_vec = stq_uop_5_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_vec = stq_uop_5_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_7_rob_idx = stq_uop_5_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_rob_idx = stq_uop_5_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_5_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_7_ldq_idx = stq_uop_5_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_6_ldq_idx = stq_uop_5_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_5_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_7_stq_idx = stq_uop_5_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_6_stq_idx = stq_uop_5_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_7_rxq_idx = stq_uop_5_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_rxq_idx = stq_uop_5_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_7_pdst = stq_uop_5_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_pdst = stq_uop_5_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_7_prs1 = stq_uop_5_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_prs1 = stq_uop_5_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_7_prs2 = stq_uop_5_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_prs2 = stq_uop_5_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_7_prs3 = stq_uop_5_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_prs3 = stq_uop_5_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_7_ppred = stq_uop_5_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_ppred = stq_uop_5_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_prs1_busy; // @[lsu.scala:252:32] wire s_uop_7_prs1_busy = stq_uop_5_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_prs1_busy = stq_uop_5_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_prs2_busy; // @[lsu.scala:252:32] wire s_uop_7_prs2_busy = stq_uop_5_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_prs2_busy = stq_uop_5_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_prs3_busy; // @[lsu.scala:252:32] wire s_uop_7_prs3_busy = stq_uop_5_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_prs3_busy = stq_uop_5_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_ppred_busy; // @[lsu.scala:252:32] wire s_uop_7_ppred_busy = stq_uop_5_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_ppred_busy = stq_uop_5_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_7_stale_pdst = stq_uop_5_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_stale_pdst = stq_uop_5_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_exception; // @[lsu.scala:252:32] wire s_uop_7_exception = stq_uop_5_exception; // @[lsu.scala:252:32, :1324:37] wire uop_6_exception = stq_uop_5_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_5_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_7_exc_cause = stq_uop_5_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_6_exc_cause = stq_uop_5_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_7_mem_cmd = stq_uop_5_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_mem_cmd = stq_uop_5_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_7_mem_size = stq_uop_5_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_mem_size = stq_uop_5_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_mem_signed; // @[lsu.scala:252:32] wire s_uop_7_mem_signed = stq_uop_5_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_6_mem_signed = stq_uop_5_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_uses_ldq; // @[lsu.scala:252:32] wire s_uop_7_uses_ldq = stq_uop_5_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_6_uses_ldq = stq_uop_5_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_uses_stq; // @[lsu.scala:252:32] wire s_uop_7_uses_stq = stq_uop_5_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_6_uses_stq = stq_uop_5_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_unique; // @[lsu.scala:252:32] wire s_uop_7_is_unique = stq_uop_5_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_unique = stq_uop_5_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_7_flush_on_commit = stq_uop_5_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_6_flush_on_commit = stq_uop_5_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_7_csr_cmd = stq_uop_5_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_csr_cmd = stq_uop_5_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_7_ldst_is_rs1 = stq_uop_5_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_6_ldst_is_rs1 = stq_uop_5_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_7_ldst = stq_uop_5_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_ldst = stq_uop_5_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_7_lrs1 = stq_uop_5_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_lrs1 = stq_uop_5_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_7_lrs2 = stq_uop_5_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_lrs2 = stq_uop_5_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_7_lrs3 = stq_uop_5_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_lrs3 = stq_uop_5_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_7_dst_rtype = stq_uop_5_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_dst_rtype = stq_uop_5_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_7_lrs1_rtype = stq_uop_5_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_lrs1_rtype = stq_uop_5_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_7_lrs2_rtype = stq_uop_5_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_lrs2_rtype = stq_uop_5_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_frs3_en; // @[lsu.scala:252:32] wire s_uop_7_frs3_en = stq_uop_5_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_6_frs3_en = stq_uop_5_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fcn_dw; // @[lsu.scala:252:32] wire s_uop_7_fcn_dw = stq_uop_5_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_6_fcn_dw = stq_uop_5_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_7_fcn_op = stq_uop_5_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_fcn_op = stq_uop_5_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_val; // @[lsu.scala:252:32] wire s_uop_7_fp_val = stq_uop_5_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_val = stq_uop_5_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_7_fp_rm = stq_uop_5_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_fp_rm = stq_uop_5_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_7_fp_typ = stq_uop_5_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_fp_typ = stq_uop_5_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_7_xcpt_pf_if = stq_uop_5_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_xcpt_pf_if = stq_uop_5_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_7_xcpt_ae_if = stq_uop_5_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_xcpt_ae_if = stq_uop_5_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_7_xcpt_ma_if = stq_uop_5_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_xcpt_ma_if = stq_uop_5_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_7_bp_debug_if = stq_uop_5_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_bp_debug_if = stq_uop_5_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_7_bp_xcpt_if = stq_uop_5_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_bp_xcpt_if = stq_uop_5_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_7_debug_fsrc = stq_uop_5_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_debug_fsrc = stq_uop_5_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_7_debug_tsrc = stq_uop_5_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_debug_tsrc = stq_uop_5_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_6_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_8_inst = stq_uop_6_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_7_inst = stq_uop_6_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_6_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_8_debug_inst = stq_uop_6_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_7_debug_inst = stq_uop_6_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_rvc; // @[lsu.scala:252:32] wire s_uop_8_is_rvc = stq_uop_6_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_rvc = stq_uop_6_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_6_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_8_debug_pc = stq_uop_6_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_7_debug_pc = stq_uop_6_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_0; // @[lsu.scala:252:32] wire s_uop_8_iq_type_0 = stq_uop_6_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_0 = stq_uop_6_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_1; // @[lsu.scala:252:32] wire s_uop_8_iq_type_1 = stq_uop_6_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_1 = stq_uop_6_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_2; // @[lsu.scala:252:32] wire s_uop_8_iq_type_2 = stq_uop_6_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_2 = stq_uop_6_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_3; // @[lsu.scala:252:32] wire s_uop_8_iq_type_3 = stq_uop_6_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_3 = stq_uop_6_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_0; // @[lsu.scala:252:32] wire s_uop_8_fu_code_0 = stq_uop_6_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_0 = stq_uop_6_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_1; // @[lsu.scala:252:32] wire s_uop_8_fu_code_1 = stq_uop_6_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_1 = stq_uop_6_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_2; // @[lsu.scala:252:32] wire s_uop_8_fu_code_2 = stq_uop_6_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_2 = stq_uop_6_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_3; // @[lsu.scala:252:32] wire s_uop_8_fu_code_3 = stq_uop_6_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_3 = stq_uop_6_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_4; // @[lsu.scala:252:32] wire s_uop_8_fu_code_4 = stq_uop_6_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_4 = stq_uop_6_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_5; // @[lsu.scala:252:32] wire s_uop_8_fu_code_5 = stq_uop_6_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_5 = stq_uop_6_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_6; // @[lsu.scala:252:32] wire s_uop_8_fu_code_6 = stq_uop_6_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_6 = stq_uop_6_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_7; // @[lsu.scala:252:32] wire s_uop_8_fu_code_7 = stq_uop_6_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_7 = stq_uop_6_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_8; // @[lsu.scala:252:32] wire s_uop_8_fu_code_8 = stq_uop_6_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_8 = stq_uop_6_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_9; // @[lsu.scala:252:32] wire s_uop_8_fu_code_9 = stq_uop_6_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_9 = stq_uop_6_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_issued; // @[lsu.scala:252:32] wire s_uop_8_iw_issued = stq_uop_6_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_issued = stq_uop_6_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_8_iw_issued_partial_agen = stq_uop_6_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_issued_partial_agen = stq_uop_6_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_8_iw_issued_partial_dgen = stq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_issued_partial_dgen = stq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_8_iw_p1_speculative_child = stq_uop_6_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_iw_p1_speculative_child = stq_uop_6_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_8_iw_p2_speculative_child = stq_uop_6_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_iw_p2_speculative_child = stq_uop_6_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_8_iw_p1_bypass_hint = stq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_p1_bypass_hint = stq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_8_iw_p2_bypass_hint = stq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_p2_bypass_hint = stq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_8_iw_p3_bypass_hint = stq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_p3_bypass_hint = stq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_8_dis_col_sel = stq_uop_6_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_dis_col_sel = stq_uop_6_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_6_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_8_br_mask = stq_uop_6_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_7_br_mask = stq_uop_6_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_6_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_8_br_tag = stq_uop_6_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_7_br_tag = stq_uop_6_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_6_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_8_br_type = stq_uop_6_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_7_br_type = stq_uop_6_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_sfb; // @[lsu.scala:252:32] wire s_uop_8_is_sfb = stq_uop_6_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_sfb = stq_uop_6_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_fence; // @[lsu.scala:252:32] wire s_uop_8_is_fence = stq_uop_6_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_fence = stq_uop_6_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_fencei; // @[lsu.scala:252:32] wire s_uop_8_is_fencei = stq_uop_6_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_fencei = stq_uop_6_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_sfence; // @[lsu.scala:252:32] wire s_uop_8_is_sfence = stq_uop_6_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_sfence = stq_uop_6_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_amo; // @[lsu.scala:252:32] wire s_uop_8_is_amo = stq_uop_6_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_amo = stq_uop_6_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_eret; // @[lsu.scala:252:32] wire s_uop_8_is_eret = stq_uop_6_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_eret = stq_uop_6_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_8_is_sys_pc2epc = stq_uop_6_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_sys_pc2epc = stq_uop_6_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_rocc; // @[lsu.scala:252:32] wire s_uop_8_is_rocc = stq_uop_6_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_rocc = stq_uop_6_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_mov; // @[lsu.scala:252:32] wire s_uop_8_is_mov = stq_uop_6_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_mov = stq_uop_6_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_8_ftq_idx = stq_uop_6_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_ftq_idx = stq_uop_6_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_edge_inst; // @[lsu.scala:252:32] wire s_uop_8_edge_inst = stq_uop_6_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_7_edge_inst = stq_uop_6_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_8_pc_lob = stq_uop_6_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_pc_lob = stq_uop_6_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_taken; // @[lsu.scala:252:32] wire s_uop_8_taken = stq_uop_6_taken; // @[lsu.scala:252:32, :1324:37] wire uop_7_taken = stq_uop_6_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_imm_rename; // @[lsu.scala:252:32] wire s_uop_8_imm_rename = stq_uop_6_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_7_imm_rename = stq_uop_6_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_8_imm_sel = stq_uop_6_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_imm_sel = stq_uop_6_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_8_pimm = stq_uop_6_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_pimm = stq_uop_6_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_6_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_8_imm_packed = stq_uop_6_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_7_imm_packed = stq_uop_6_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_8_op1_sel = stq_uop_6_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_op1_sel = stq_uop_6_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_8_op2_sel = stq_uop_6_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_op2_sel = stq_uop_6_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ldst = stq_uop_6_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ldst = stq_uop_6_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_wen = stq_uop_6_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_wen = stq_uop_6_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ren1 = stq_uop_6_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ren1 = stq_uop_6_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ren2 = stq_uop_6_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ren2 = stq_uop_6_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ren3 = stq_uop_6_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ren3 = stq_uop_6_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_swap12 = stq_uop_6_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_swap12 = stq_uop_6_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_swap23 = stq_uop_6_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_swap23 = stq_uop_6_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_8_fp_ctrl_typeTagIn = stq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_fp_ctrl_typeTagIn = stq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_8_fp_ctrl_typeTagOut = stq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_fp_ctrl_typeTagOut = stq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_fromint = stq_uop_6_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_fromint = stq_uop_6_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_toint = stq_uop_6_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_toint = stq_uop_6_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_fastpipe = stq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_fastpipe = stq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_fma = stq_uop_6_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_fma = stq_uop_6_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_div = stq_uop_6_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_div = stq_uop_6_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_sqrt = stq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_sqrt = stq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_wflags = stq_uop_6_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_wflags = stq_uop_6_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_vec = stq_uop_6_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_vec = stq_uop_6_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_8_rob_idx = stq_uop_6_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_rob_idx = stq_uop_6_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_6_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_8_ldq_idx = stq_uop_6_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_7_ldq_idx = stq_uop_6_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_6_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_8_stq_idx = stq_uop_6_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_7_stq_idx = stq_uop_6_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_8_rxq_idx = stq_uop_6_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_rxq_idx = stq_uop_6_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_8_pdst = stq_uop_6_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_pdst = stq_uop_6_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_8_prs1 = stq_uop_6_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_prs1 = stq_uop_6_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_8_prs2 = stq_uop_6_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_prs2 = stq_uop_6_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_8_prs3 = stq_uop_6_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_prs3 = stq_uop_6_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_8_ppred = stq_uop_6_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_ppred = stq_uop_6_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_prs1_busy; // @[lsu.scala:252:32] wire s_uop_8_prs1_busy = stq_uop_6_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_prs1_busy = stq_uop_6_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_prs2_busy; // @[lsu.scala:252:32] wire s_uop_8_prs2_busy = stq_uop_6_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_prs2_busy = stq_uop_6_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_prs3_busy; // @[lsu.scala:252:32] wire s_uop_8_prs3_busy = stq_uop_6_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_prs3_busy = stq_uop_6_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_ppred_busy; // @[lsu.scala:252:32] wire s_uop_8_ppred_busy = stq_uop_6_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_ppred_busy = stq_uop_6_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_8_stale_pdst = stq_uop_6_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_stale_pdst = stq_uop_6_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_exception; // @[lsu.scala:252:32] wire s_uop_8_exception = stq_uop_6_exception; // @[lsu.scala:252:32, :1324:37] wire uop_7_exception = stq_uop_6_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_6_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_8_exc_cause = stq_uop_6_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_7_exc_cause = stq_uop_6_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_8_mem_cmd = stq_uop_6_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_mem_cmd = stq_uop_6_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_8_mem_size = stq_uop_6_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_mem_size = stq_uop_6_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_mem_signed; // @[lsu.scala:252:32] wire s_uop_8_mem_signed = stq_uop_6_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_7_mem_signed = stq_uop_6_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_uses_ldq; // @[lsu.scala:252:32] wire s_uop_8_uses_ldq = stq_uop_6_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_7_uses_ldq = stq_uop_6_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_uses_stq; // @[lsu.scala:252:32] wire s_uop_8_uses_stq = stq_uop_6_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_7_uses_stq = stq_uop_6_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_unique; // @[lsu.scala:252:32] wire s_uop_8_is_unique = stq_uop_6_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_unique = stq_uop_6_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_8_flush_on_commit = stq_uop_6_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_7_flush_on_commit = stq_uop_6_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_8_csr_cmd = stq_uop_6_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_csr_cmd = stq_uop_6_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_8_ldst_is_rs1 = stq_uop_6_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_7_ldst_is_rs1 = stq_uop_6_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_8_ldst = stq_uop_6_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_ldst = stq_uop_6_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_8_lrs1 = stq_uop_6_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_lrs1 = stq_uop_6_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_8_lrs2 = stq_uop_6_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_lrs2 = stq_uop_6_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_8_lrs3 = stq_uop_6_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_lrs3 = stq_uop_6_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_8_dst_rtype = stq_uop_6_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_dst_rtype = stq_uop_6_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_8_lrs1_rtype = stq_uop_6_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_lrs1_rtype = stq_uop_6_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_8_lrs2_rtype = stq_uop_6_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_lrs2_rtype = stq_uop_6_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_frs3_en; // @[lsu.scala:252:32] wire s_uop_8_frs3_en = stq_uop_6_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_7_frs3_en = stq_uop_6_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fcn_dw; // @[lsu.scala:252:32] wire s_uop_8_fcn_dw = stq_uop_6_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_7_fcn_dw = stq_uop_6_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_8_fcn_op = stq_uop_6_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_fcn_op = stq_uop_6_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_val; // @[lsu.scala:252:32] wire s_uop_8_fp_val = stq_uop_6_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_val = stq_uop_6_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_8_fp_rm = stq_uop_6_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_fp_rm = stq_uop_6_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_8_fp_typ = stq_uop_6_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_fp_typ = stq_uop_6_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_8_xcpt_pf_if = stq_uop_6_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_xcpt_pf_if = stq_uop_6_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_8_xcpt_ae_if = stq_uop_6_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_xcpt_ae_if = stq_uop_6_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_8_xcpt_ma_if = stq_uop_6_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_xcpt_ma_if = stq_uop_6_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_8_bp_debug_if = stq_uop_6_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_bp_debug_if = stq_uop_6_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_8_bp_xcpt_if = stq_uop_6_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_bp_xcpt_if = stq_uop_6_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_8_debug_fsrc = stq_uop_6_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_debug_fsrc = stq_uop_6_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_8_debug_tsrc = stq_uop_6_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_debug_tsrc = stq_uop_6_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_7_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_9_inst = stq_uop_7_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_8_inst = stq_uop_7_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_7_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_9_debug_inst = stq_uop_7_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_8_debug_inst = stq_uop_7_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_rvc; // @[lsu.scala:252:32] wire s_uop_9_is_rvc = stq_uop_7_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_rvc = stq_uop_7_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_7_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_9_debug_pc = stq_uop_7_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_8_debug_pc = stq_uop_7_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_0; // @[lsu.scala:252:32] wire s_uop_9_iq_type_0 = stq_uop_7_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_0 = stq_uop_7_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_1; // @[lsu.scala:252:32] wire s_uop_9_iq_type_1 = stq_uop_7_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_1 = stq_uop_7_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_2; // @[lsu.scala:252:32] wire s_uop_9_iq_type_2 = stq_uop_7_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_2 = stq_uop_7_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_3; // @[lsu.scala:252:32] wire s_uop_9_iq_type_3 = stq_uop_7_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_3 = stq_uop_7_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_0; // @[lsu.scala:252:32] wire s_uop_9_fu_code_0 = stq_uop_7_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_0 = stq_uop_7_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_1; // @[lsu.scala:252:32] wire s_uop_9_fu_code_1 = stq_uop_7_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_1 = stq_uop_7_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_2; // @[lsu.scala:252:32] wire s_uop_9_fu_code_2 = stq_uop_7_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_2 = stq_uop_7_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_3; // @[lsu.scala:252:32] wire s_uop_9_fu_code_3 = stq_uop_7_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_3 = stq_uop_7_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_4; // @[lsu.scala:252:32] wire s_uop_9_fu_code_4 = stq_uop_7_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_4 = stq_uop_7_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_5; // @[lsu.scala:252:32] wire s_uop_9_fu_code_5 = stq_uop_7_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_5 = stq_uop_7_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_6; // @[lsu.scala:252:32] wire s_uop_9_fu_code_6 = stq_uop_7_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_6 = stq_uop_7_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_7; // @[lsu.scala:252:32] wire s_uop_9_fu_code_7 = stq_uop_7_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_7 = stq_uop_7_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_8; // @[lsu.scala:252:32] wire s_uop_9_fu_code_8 = stq_uop_7_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_8 = stq_uop_7_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_9; // @[lsu.scala:252:32] wire s_uop_9_fu_code_9 = stq_uop_7_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_9 = stq_uop_7_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_issued; // @[lsu.scala:252:32] wire s_uop_9_iw_issued = stq_uop_7_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_issued = stq_uop_7_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_9_iw_issued_partial_agen = stq_uop_7_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_issued_partial_agen = stq_uop_7_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_9_iw_issued_partial_dgen = stq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_issued_partial_dgen = stq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_9_iw_p1_speculative_child = stq_uop_7_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_iw_p1_speculative_child = stq_uop_7_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_9_iw_p2_speculative_child = stq_uop_7_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_iw_p2_speculative_child = stq_uop_7_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_9_iw_p1_bypass_hint = stq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_p1_bypass_hint = stq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_9_iw_p2_bypass_hint = stq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_p2_bypass_hint = stq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_9_iw_p3_bypass_hint = stq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_p3_bypass_hint = stq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_9_dis_col_sel = stq_uop_7_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_dis_col_sel = stq_uop_7_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_7_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_9_br_mask = stq_uop_7_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_8_br_mask = stq_uop_7_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_7_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_9_br_tag = stq_uop_7_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_8_br_tag = stq_uop_7_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_7_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_9_br_type = stq_uop_7_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_8_br_type = stq_uop_7_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_sfb; // @[lsu.scala:252:32] wire s_uop_9_is_sfb = stq_uop_7_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_sfb = stq_uop_7_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_fence; // @[lsu.scala:252:32] wire s_uop_9_is_fence = stq_uop_7_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_fence = stq_uop_7_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_fencei; // @[lsu.scala:252:32] wire s_uop_9_is_fencei = stq_uop_7_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_fencei = stq_uop_7_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_sfence; // @[lsu.scala:252:32] wire s_uop_9_is_sfence = stq_uop_7_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_sfence = stq_uop_7_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_amo; // @[lsu.scala:252:32] wire s_uop_9_is_amo = stq_uop_7_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_amo = stq_uop_7_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_eret; // @[lsu.scala:252:32] wire s_uop_9_is_eret = stq_uop_7_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_eret = stq_uop_7_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_9_is_sys_pc2epc = stq_uop_7_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_sys_pc2epc = stq_uop_7_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_rocc; // @[lsu.scala:252:32] wire s_uop_9_is_rocc = stq_uop_7_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_rocc = stq_uop_7_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_mov; // @[lsu.scala:252:32] wire s_uop_9_is_mov = stq_uop_7_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_mov = stq_uop_7_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_9_ftq_idx = stq_uop_7_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_ftq_idx = stq_uop_7_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_edge_inst; // @[lsu.scala:252:32] wire s_uop_9_edge_inst = stq_uop_7_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_8_edge_inst = stq_uop_7_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_9_pc_lob = stq_uop_7_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_pc_lob = stq_uop_7_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_taken; // @[lsu.scala:252:32] wire s_uop_9_taken = stq_uop_7_taken; // @[lsu.scala:252:32, :1324:37] wire uop_8_taken = stq_uop_7_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_imm_rename; // @[lsu.scala:252:32] wire s_uop_9_imm_rename = stq_uop_7_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_8_imm_rename = stq_uop_7_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_9_imm_sel = stq_uop_7_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_imm_sel = stq_uop_7_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_9_pimm = stq_uop_7_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_pimm = stq_uop_7_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_7_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_9_imm_packed = stq_uop_7_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_8_imm_packed = stq_uop_7_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_9_op1_sel = stq_uop_7_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_op1_sel = stq_uop_7_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_9_op2_sel = stq_uop_7_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_op2_sel = stq_uop_7_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ldst = stq_uop_7_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ldst = stq_uop_7_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_wen = stq_uop_7_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_wen = stq_uop_7_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ren1 = stq_uop_7_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ren1 = stq_uop_7_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ren2 = stq_uop_7_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ren2 = stq_uop_7_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ren3 = stq_uop_7_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ren3 = stq_uop_7_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_swap12 = stq_uop_7_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_swap12 = stq_uop_7_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_swap23 = stq_uop_7_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_swap23 = stq_uop_7_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_9_fp_ctrl_typeTagIn = stq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_fp_ctrl_typeTagIn = stq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_9_fp_ctrl_typeTagOut = stq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_fp_ctrl_typeTagOut = stq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_fromint = stq_uop_7_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_fromint = stq_uop_7_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_toint = stq_uop_7_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_toint = stq_uop_7_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_fastpipe = stq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_fastpipe = stq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_fma = stq_uop_7_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_fma = stq_uop_7_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_div = stq_uop_7_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_div = stq_uop_7_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_sqrt = stq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_sqrt = stq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_wflags = stq_uop_7_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_wflags = stq_uop_7_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_vec = stq_uop_7_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_vec = stq_uop_7_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_9_rob_idx = stq_uop_7_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_rob_idx = stq_uop_7_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_7_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_9_ldq_idx = stq_uop_7_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_8_ldq_idx = stq_uop_7_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_7_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_9_stq_idx = stq_uop_7_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_8_stq_idx = stq_uop_7_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_9_rxq_idx = stq_uop_7_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_rxq_idx = stq_uop_7_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_9_pdst = stq_uop_7_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_pdst = stq_uop_7_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_9_prs1 = stq_uop_7_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_prs1 = stq_uop_7_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_9_prs2 = stq_uop_7_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_prs2 = stq_uop_7_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_9_prs3 = stq_uop_7_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_prs3 = stq_uop_7_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_9_ppred = stq_uop_7_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_ppred = stq_uop_7_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_prs1_busy; // @[lsu.scala:252:32] wire s_uop_9_prs1_busy = stq_uop_7_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_prs1_busy = stq_uop_7_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_prs2_busy; // @[lsu.scala:252:32] wire s_uop_9_prs2_busy = stq_uop_7_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_prs2_busy = stq_uop_7_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_prs3_busy; // @[lsu.scala:252:32] wire s_uop_9_prs3_busy = stq_uop_7_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_prs3_busy = stq_uop_7_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_ppred_busy; // @[lsu.scala:252:32] wire s_uop_9_ppred_busy = stq_uop_7_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_ppred_busy = stq_uop_7_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_9_stale_pdst = stq_uop_7_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_stale_pdst = stq_uop_7_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_exception; // @[lsu.scala:252:32] wire s_uop_9_exception = stq_uop_7_exception; // @[lsu.scala:252:32, :1324:37] wire uop_8_exception = stq_uop_7_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_7_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_9_exc_cause = stq_uop_7_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_8_exc_cause = stq_uop_7_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_9_mem_cmd = stq_uop_7_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_mem_cmd = stq_uop_7_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_9_mem_size = stq_uop_7_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_mem_size = stq_uop_7_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_mem_signed; // @[lsu.scala:252:32] wire s_uop_9_mem_signed = stq_uop_7_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_8_mem_signed = stq_uop_7_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_uses_ldq; // @[lsu.scala:252:32] wire s_uop_9_uses_ldq = stq_uop_7_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_8_uses_ldq = stq_uop_7_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_uses_stq; // @[lsu.scala:252:32] wire s_uop_9_uses_stq = stq_uop_7_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_8_uses_stq = stq_uop_7_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_unique; // @[lsu.scala:252:32] wire s_uop_9_is_unique = stq_uop_7_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_unique = stq_uop_7_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_9_flush_on_commit = stq_uop_7_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_8_flush_on_commit = stq_uop_7_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_9_csr_cmd = stq_uop_7_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_csr_cmd = stq_uop_7_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_9_ldst_is_rs1 = stq_uop_7_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_8_ldst_is_rs1 = stq_uop_7_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_9_ldst = stq_uop_7_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_ldst = stq_uop_7_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_9_lrs1 = stq_uop_7_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_lrs1 = stq_uop_7_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_9_lrs2 = stq_uop_7_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_lrs2 = stq_uop_7_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_9_lrs3 = stq_uop_7_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_lrs3 = stq_uop_7_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_9_dst_rtype = stq_uop_7_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_dst_rtype = stq_uop_7_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_9_lrs1_rtype = stq_uop_7_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_lrs1_rtype = stq_uop_7_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_9_lrs2_rtype = stq_uop_7_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_lrs2_rtype = stq_uop_7_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_frs3_en; // @[lsu.scala:252:32] wire s_uop_9_frs3_en = stq_uop_7_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_8_frs3_en = stq_uop_7_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fcn_dw; // @[lsu.scala:252:32] wire s_uop_9_fcn_dw = stq_uop_7_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_8_fcn_dw = stq_uop_7_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_9_fcn_op = stq_uop_7_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_fcn_op = stq_uop_7_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_val; // @[lsu.scala:252:32] wire s_uop_9_fp_val = stq_uop_7_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_val = stq_uop_7_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_9_fp_rm = stq_uop_7_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_fp_rm = stq_uop_7_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_9_fp_typ = stq_uop_7_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_fp_typ = stq_uop_7_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_9_xcpt_pf_if = stq_uop_7_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_xcpt_pf_if = stq_uop_7_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_9_xcpt_ae_if = stq_uop_7_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_xcpt_ae_if = stq_uop_7_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_9_xcpt_ma_if = stq_uop_7_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_xcpt_ma_if = stq_uop_7_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_9_bp_debug_if = stq_uop_7_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_bp_debug_if = stq_uop_7_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_9_bp_xcpt_if = stq_uop_7_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_bp_xcpt_if = stq_uop_7_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_9_debug_fsrc = stq_uop_7_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_debug_fsrc = stq_uop_7_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_9_debug_tsrc = stq_uop_7_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_debug_tsrc = stq_uop_7_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_8_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_10_inst = stq_uop_8_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_9_inst = stq_uop_8_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_8_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_10_debug_inst = stq_uop_8_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_9_debug_inst = stq_uop_8_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_rvc; // @[lsu.scala:252:32] wire s_uop_10_is_rvc = stq_uop_8_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_rvc = stq_uop_8_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_8_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_10_debug_pc = stq_uop_8_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_9_debug_pc = stq_uop_8_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_0; // @[lsu.scala:252:32] wire s_uop_10_iq_type_0 = stq_uop_8_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_0 = stq_uop_8_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_1; // @[lsu.scala:252:32] wire s_uop_10_iq_type_1 = stq_uop_8_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_1 = stq_uop_8_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_2; // @[lsu.scala:252:32] wire s_uop_10_iq_type_2 = stq_uop_8_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_2 = stq_uop_8_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_3; // @[lsu.scala:252:32] wire s_uop_10_iq_type_3 = stq_uop_8_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_3 = stq_uop_8_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_0; // @[lsu.scala:252:32] wire s_uop_10_fu_code_0 = stq_uop_8_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_0 = stq_uop_8_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_1; // @[lsu.scala:252:32] wire s_uop_10_fu_code_1 = stq_uop_8_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_1 = stq_uop_8_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_2; // @[lsu.scala:252:32] wire s_uop_10_fu_code_2 = stq_uop_8_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_2 = stq_uop_8_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_3; // @[lsu.scala:252:32] wire s_uop_10_fu_code_3 = stq_uop_8_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_3 = stq_uop_8_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_4; // @[lsu.scala:252:32] wire s_uop_10_fu_code_4 = stq_uop_8_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_4 = stq_uop_8_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_5; // @[lsu.scala:252:32] wire s_uop_10_fu_code_5 = stq_uop_8_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_5 = stq_uop_8_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_6; // @[lsu.scala:252:32] wire s_uop_10_fu_code_6 = stq_uop_8_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_6 = stq_uop_8_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_7; // @[lsu.scala:252:32] wire s_uop_10_fu_code_7 = stq_uop_8_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_7 = stq_uop_8_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_8; // @[lsu.scala:252:32] wire s_uop_10_fu_code_8 = stq_uop_8_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_8 = stq_uop_8_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_9; // @[lsu.scala:252:32] wire s_uop_10_fu_code_9 = stq_uop_8_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_9 = stq_uop_8_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_issued; // @[lsu.scala:252:32] wire s_uop_10_iw_issued = stq_uop_8_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_issued = stq_uop_8_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_10_iw_issued_partial_agen = stq_uop_8_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_issued_partial_agen = stq_uop_8_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_10_iw_issued_partial_dgen = stq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_issued_partial_dgen = stq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_10_iw_p1_speculative_child = stq_uop_8_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_iw_p1_speculative_child = stq_uop_8_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_10_iw_p2_speculative_child = stq_uop_8_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_iw_p2_speculative_child = stq_uop_8_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_10_iw_p1_bypass_hint = stq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_p1_bypass_hint = stq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_10_iw_p2_bypass_hint = stq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_p2_bypass_hint = stq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_10_iw_p3_bypass_hint = stq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_p3_bypass_hint = stq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_10_dis_col_sel = stq_uop_8_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_dis_col_sel = stq_uop_8_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_8_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_10_br_mask = stq_uop_8_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_9_br_mask = stq_uop_8_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_8_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_10_br_tag = stq_uop_8_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_9_br_tag = stq_uop_8_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_8_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_10_br_type = stq_uop_8_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_9_br_type = stq_uop_8_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_sfb; // @[lsu.scala:252:32] wire s_uop_10_is_sfb = stq_uop_8_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_sfb = stq_uop_8_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_fence; // @[lsu.scala:252:32] wire s_uop_10_is_fence = stq_uop_8_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_fence = stq_uop_8_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_fencei; // @[lsu.scala:252:32] wire s_uop_10_is_fencei = stq_uop_8_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_fencei = stq_uop_8_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_sfence; // @[lsu.scala:252:32] wire s_uop_10_is_sfence = stq_uop_8_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_sfence = stq_uop_8_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_amo; // @[lsu.scala:252:32] wire s_uop_10_is_amo = stq_uop_8_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_amo = stq_uop_8_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_eret; // @[lsu.scala:252:32] wire s_uop_10_is_eret = stq_uop_8_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_eret = stq_uop_8_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_10_is_sys_pc2epc = stq_uop_8_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_sys_pc2epc = stq_uop_8_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_rocc; // @[lsu.scala:252:32] wire s_uop_10_is_rocc = stq_uop_8_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_rocc = stq_uop_8_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_mov; // @[lsu.scala:252:32] wire s_uop_10_is_mov = stq_uop_8_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_mov = stq_uop_8_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_10_ftq_idx = stq_uop_8_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_ftq_idx = stq_uop_8_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_edge_inst; // @[lsu.scala:252:32] wire s_uop_10_edge_inst = stq_uop_8_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_9_edge_inst = stq_uop_8_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_10_pc_lob = stq_uop_8_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_pc_lob = stq_uop_8_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_taken; // @[lsu.scala:252:32] wire s_uop_10_taken = stq_uop_8_taken; // @[lsu.scala:252:32, :1324:37] wire uop_9_taken = stq_uop_8_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_imm_rename; // @[lsu.scala:252:32] wire s_uop_10_imm_rename = stq_uop_8_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_9_imm_rename = stq_uop_8_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_10_imm_sel = stq_uop_8_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_imm_sel = stq_uop_8_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_10_pimm = stq_uop_8_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_pimm = stq_uop_8_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_8_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_10_imm_packed = stq_uop_8_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_9_imm_packed = stq_uop_8_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_10_op1_sel = stq_uop_8_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_op1_sel = stq_uop_8_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_10_op2_sel = stq_uop_8_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_op2_sel = stq_uop_8_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ldst = stq_uop_8_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ldst = stq_uop_8_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_wen = stq_uop_8_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_wen = stq_uop_8_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ren1 = stq_uop_8_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ren1 = stq_uop_8_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ren2 = stq_uop_8_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ren2 = stq_uop_8_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ren3 = stq_uop_8_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ren3 = stq_uop_8_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_swap12 = stq_uop_8_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_swap12 = stq_uop_8_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_swap23 = stq_uop_8_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_swap23 = stq_uop_8_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_10_fp_ctrl_typeTagIn = stq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_fp_ctrl_typeTagIn = stq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_10_fp_ctrl_typeTagOut = stq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_fp_ctrl_typeTagOut = stq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_fromint = stq_uop_8_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_fromint = stq_uop_8_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_toint = stq_uop_8_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_toint = stq_uop_8_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_fastpipe = stq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_fastpipe = stq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_fma = stq_uop_8_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_fma = stq_uop_8_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_div = stq_uop_8_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_div = stq_uop_8_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_sqrt = stq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_sqrt = stq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_wflags = stq_uop_8_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_wflags = stq_uop_8_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_vec = stq_uop_8_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_vec = stq_uop_8_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_10_rob_idx = stq_uop_8_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_rob_idx = stq_uop_8_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_8_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_10_ldq_idx = stq_uop_8_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_9_ldq_idx = stq_uop_8_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_8_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_10_stq_idx = stq_uop_8_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_9_stq_idx = stq_uop_8_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_10_rxq_idx = stq_uop_8_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_rxq_idx = stq_uop_8_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_10_pdst = stq_uop_8_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_pdst = stq_uop_8_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_10_prs1 = stq_uop_8_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_prs1 = stq_uop_8_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_10_prs2 = stq_uop_8_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_prs2 = stq_uop_8_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_10_prs3 = stq_uop_8_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_prs3 = stq_uop_8_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_10_ppred = stq_uop_8_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_ppred = stq_uop_8_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_prs1_busy; // @[lsu.scala:252:32] wire s_uop_10_prs1_busy = stq_uop_8_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_prs1_busy = stq_uop_8_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_prs2_busy; // @[lsu.scala:252:32] wire s_uop_10_prs2_busy = stq_uop_8_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_prs2_busy = stq_uop_8_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_prs3_busy; // @[lsu.scala:252:32] wire s_uop_10_prs3_busy = stq_uop_8_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_prs3_busy = stq_uop_8_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_ppred_busy; // @[lsu.scala:252:32] wire s_uop_10_ppred_busy = stq_uop_8_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_ppred_busy = stq_uop_8_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_10_stale_pdst = stq_uop_8_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_stale_pdst = stq_uop_8_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_exception; // @[lsu.scala:252:32] wire s_uop_10_exception = stq_uop_8_exception; // @[lsu.scala:252:32, :1324:37] wire uop_9_exception = stq_uop_8_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_8_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_10_exc_cause = stq_uop_8_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_9_exc_cause = stq_uop_8_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_10_mem_cmd = stq_uop_8_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_mem_cmd = stq_uop_8_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_10_mem_size = stq_uop_8_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_mem_size = stq_uop_8_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_mem_signed; // @[lsu.scala:252:32] wire s_uop_10_mem_signed = stq_uop_8_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_9_mem_signed = stq_uop_8_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_uses_ldq; // @[lsu.scala:252:32] wire s_uop_10_uses_ldq = stq_uop_8_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_9_uses_ldq = stq_uop_8_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_uses_stq; // @[lsu.scala:252:32] wire s_uop_10_uses_stq = stq_uop_8_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_9_uses_stq = stq_uop_8_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_unique; // @[lsu.scala:252:32] wire s_uop_10_is_unique = stq_uop_8_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_unique = stq_uop_8_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_10_flush_on_commit = stq_uop_8_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_9_flush_on_commit = stq_uop_8_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_10_csr_cmd = stq_uop_8_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_csr_cmd = stq_uop_8_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_10_ldst_is_rs1 = stq_uop_8_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_9_ldst_is_rs1 = stq_uop_8_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_10_ldst = stq_uop_8_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_ldst = stq_uop_8_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_10_lrs1 = stq_uop_8_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_lrs1 = stq_uop_8_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_10_lrs2 = stq_uop_8_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_lrs2 = stq_uop_8_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_10_lrs3 = stq_uop_8_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_lrs3 = stq_uop_8_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_10_dst_rtype = stq_uop_8_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_dst_rtype = stq_uop_8_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_10_lrs1_rtype = stq_uop_8_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_lrs1_rtype = stq_uop_8_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_10_lrs2_rtype = stq_uop_8_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_lrs2_rtype = stq_uop_8_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_frs3_en; // @[lsu.scala:252:32] wire s_uop_10_frs3_en = stq_uop_8_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_9_frs3_en = stq_uop_8_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fcn_dw; // @[lsu.scala:252:32] wire s_uop_10_fcn_dw = stq_uop_8_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_9_fcn_dw = stq_uop_8_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_10_fcn_op = stq_uop_8_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_fcn_op = stq_uop_8_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_val; // @[lsu.scala:252:32] wire s_uop_10_fp_val = stq_uop_8_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_val = stq_uop_8_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_10_fp_rm = stq_uop_8_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_fp_rm = stq_uop_8_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_10_fp_typ = stq_uop_8_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_fp_typ = stq_uop_8_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_10_xcpt_pf_if = stq_uop_8_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_xcpt_pf_if = stq_uop_8_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_10_xcpt_ae_if = stq_uop_8_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_xcpt_ae_if = stq_uop_8_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_10_xcpt_ma_if = stq_uop_8_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_xcpt_ma_if = stq_uop_8_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_10_bp_debug_if = stq_uop_8_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_bp_debug_if = stq_uop_8_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_10_bp_xcpt_if = stq_uop_8_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_bp_xcpt_if = stq_uop_8_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_10_debug_fsrc = stq_uop_8_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_debug_fsrc = stq_uop_8_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_10_debug_tsrc = stq_uop_8_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_debug_tsrc = stq_uop_8_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_9_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_11_inst = stq_uop_9_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_10_inst = stq_uop_9_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_9_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_11_debug_inst = stq_uop_9_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_10_debug_inst = stq_uop_9_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_rvc; // @[lsu.scala:252:32] wire s_uop_11_is_rvc = stq_uop_9_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_rvc = stq_uop_9_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_9_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_11_debug_pc = stq_uop_9_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_10_debug_pc = stq_uop_9_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_0; // @[lsu.scala:252:32] wire s_uop_11_iq_type_0 = stq_uop_9_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_0 = stq_uop_9_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_1; // @[lsu.scala:252:32] wire s_uop_11_iq_type_1 = stq_uop_9_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_1 = stq_uop_9_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_2; // @[lsu.scala:252:32] wire s_uop_11_iq_type_2 = stq_uop_9_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_2 = stq_uop_9_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_3; // @[lsu.scala:252:32] wire s_uop_11_iq_type_3 = stq_uop_9_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_3 = stq_uop_9_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_0; // @[lsu.scala:252:32] wire s_uop_11_fu_code_0 = stq_uop_9_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_0 = stq_uop_9_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_1; // @[lsu.scala:252:32] wire s_uop_11_fu_code_1 = stq_uop_9_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_1 = stq_uop_9_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_2; // @[lsu.scala:252:32] wire s_uop_11_fu_code_2 = stq_uop_9_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_2 = stq_uop_9_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_3; // @[lsu.scala:252:32] wire s_uop_11_fu_code_3 = stq_uop_9_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_3 = stq_uop_9_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_4; // @[lsu.scala:252:32] wire s_uop_11_fu_code_4 = stq_uop_9_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_4 = stq_uop_9_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_5; // @[lsu.scala:252:32] wire s_uop_11_fu_code_5 = stq_uop_9_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_5 = stq_uop_9_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_6; // @[lsu.scala:252:32] wire s_uop_11_fu_code_6 = stq_uop_9_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_6 = stq_uop_9_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_7; // @[lsu.scala:252:32] wire s_uop_11_fu_code_7 = stq_uop_9_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_7 = stq_uop_9_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_8; // @[lsu.scala:252:32] wire s_uop_11_fu_code_8 = stq_uop_9_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_8 = stq_uop_9_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_9; // @[lsu.scala:252:32] wire s_uop_11_fu_code_9 = stq_uop_9_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_9 = stq_uop_9_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_issued; // @[lsu.scala:252:32] wire s_uop_11_iw_issued = stq_uop_9_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_issued = stq_uop_9_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_11_iw_issued_partial_agen = stq_uop_9_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_issued_partial_agen = stq_uop_9_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_11_iw_issued_partial_dgen = stq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_issued_partial_dgen = stq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_11_iw_p1_speculative_child = stq_uop_9_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_iw_p1_speculative_child = stq_uop_9_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_11_iw_p2_speculative_child = stq_uop_9_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_iw_p2_speculative_child = stq_uop_9_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_11_iw_p1_bypass_hint = stq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_p1_bypass_hint = stq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_11_iw_p2_bypass_hint = stq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_p2_bypass_hint = stq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_11_iw_p3_bypass_hint = stq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_p3_bypass_hint = stq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_11_dis_col_sel = stq_uop_9_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_dis_col_sel = stq_uop_9_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_9_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_11_br_mask = stq_uop_9_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_10_br_mask = stq_uop_9_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_9_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_11_br_tag = stq_uop_9_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_10_br_tag = stq_uop_9_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_9_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_11_br_type = stq_uop_9_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_10_br_type = stq_uop_9_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_sfb; // @[lsu.scala:252:32] wire s_uop_11_is_sfb = stq_uop_9_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_sfb = stq_uop_9_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_fence; // @[lsu.scala:252:32] wire s_uop_11_is_fence = stq_uop_9_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_fence = stq_uop_9_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_fencei; // @[lsu.scala:252:32] wire s_uop_11_is_fencei = stq_uop_9_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_fencei = stq_uop_9_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_sfence; // @[lsu.scala:252:32] wire s_uop_11_is_sfence = stq_uop_9_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_sfence = stq_uop_9_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_amo; // @[lsu.scala:252:32] wire s_uop_11_is_amo = stq_uop_9_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_amo = stq_uop_9_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_eret; // @[lsu.scala:252:32] wire s_uop_11_is_eret = stq_uop_9_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_eret = stq_uop_9_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_11_is_sys_pc2epc = stq_uop_9_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_sys_pc2epc = stq_uop_9_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_rocc; // @[lsu.scala:252:32] wire s_uop_11_is_rocc = stq_uop_9_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_rocc = stq_uop_9_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_mov; // @[lsu.scala:252:32] wire s_uop_11_is_mov = stq_uop_9_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_mov = stq_uop_9_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_11_ftq_idx = stq_uop_9_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_ftq_idx = stq_uop_9_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_edge_inst; // @[lsu.scala:252:32] wire s_uop_11_edge_inst = stq_uop_9_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_10_edge_inst = stq_uop_9_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_11_pc_lob = stq_uop_9_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_pc_lob = stq_uop_9_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_taken; // @[lsu.scala:252:32] wire s_uop_11_taken = stq_uop_9_taken; // @[lsu.scala:252:32, :1324:37] wire uop_10_taken = stq_uop_9_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_imm_rename; // @[lsu.scala:252:32] wire s_uop_11_imm_rename = stq_uop_9_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_10_imm_rename = stq_uop_9_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_11_imm_sel = stq_uop_9_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_imm_sel = stq_uop_9_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_11_pimm = stq_uop_9_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_pimm = stq_uop_9_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_9_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_11_imm_packed = stq_uop_9_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_10_imm_packed = stq_uop_9_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_11_op1_sel = stq_uop_9_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_op1_sel = stq_uop_9_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_11_op2_sel = stq_uop_9_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_op2_sel = stq_uop_9_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ldst = stq_uop_9_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ldst = stq_uop_9_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_wen = stq_uop_9_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_wen = stq_uop_9_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ren1 = stq_uop_9_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ren1 = stq_uop_9_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ren2 = stq_uop_9_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ren2 = stq_uop_9_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ren3 = stq_uop_9_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ren3 = stq_uop_9_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_swap12 = stq_uop_9_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_swap12 = stq_uop_9_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_swap23 = stq_uop_9_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_swap23 = stq_uop_9_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_11_fp_ctrl_typeTagIn = stq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_fp_ctrl_typeTagIn = stq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_11_fp_ctrl_typeTagOut = stq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_fp_ctrl_typeTagOut = stq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_fromint = stq_uop_9_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_fromint = stq_uop_9_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_toint = stq_uop_9_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_toint = stq_uop_9_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_fastpipe = stq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_fastpipe = stq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_fma = stq_uop_9_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_fma = stq_uop_9_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_div = stq_uop_9_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_div = stq_uop_9_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_sqrt = stq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_sqrt = stq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_wflags = stq_uop_9_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_wflags = stq_uop_9_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_vec = stq_uop_9_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_vec = stq_uop_9_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_11_rob_idx = stq_uop_9_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_rob_idx = stq_uop_9_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_9_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_11_ldq_idx = stq_uop_9_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_10_ldq_idx = stq_uop_9_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_9_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_11_stq_idx = stq_uop_9_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_10_stq_idx = stq_uop_9_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_11_rxq_idx = stq_uop_9_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_rxq_idx = stq_uop_9_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_11_pdst = stq_uop_9_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_pdst = stq_uop_9_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_11_prs1 = stq_uop_9_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_prs1 = stq_uop_9_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_11_prs2 = stq_uop_9_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_prs2 = stq_uop_9_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_11_prs3 = stq_uop_9_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_prs3 = stq_uop_9_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_11_ppred = stq_uop_9_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_ppred = stq_uop_9_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_prs1_busy; // @[lsu.scala:252:32] wire s_uop_11_prs1_busy = stq_uop_9_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_prs1_busy = stq_uop_9_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_prs2_busy; // @[lsu.scala:252:32] wire s_uop_11_prs2_busy = stq_uop_9_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_prs2_busy = stq_uop_9_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_prs3_busy; // @[lsu.scala:252:32] wire s_uop_11_prs3_busy = stq_uop_9_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_prs3_busy = stq_uop_9_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_ppred_busy; // @[lsu.scala:252:32] wire s_uop_11_ppred_busy = stq_uop_9_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_ppred_busy = stq_uop_9_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_11_stale_pdst = stq_uop_9_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_stale_pdst = stq_uop_9_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_exception; // @[lsu.scala:252:32] wire s_uop_11_exception = stq_uop_9_exception; // @[lsu.scala:252:32, :1324:37] wire uop_10_exception = stq_uop_9_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_9_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_11_exc_cause = stq_uop_9_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_10_exc_cause = stq_uop_9_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_11_mem_cmd = stq_uop_9_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_mem_cmd = stq_uop_9_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_11_mem_size = stq_uop_9_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_mem_size = stq_uop_9_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_mem_signed; // @[lsu.scala:252:32] wire s_uop_11_mem_signed = stq_uop_9_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_10_mem_signed = stq_uop_9_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_uses_ldq; // @[lsu.scala:252:32] wire s_uop_11_uses_ldq = stq_uop_9_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_10_uses_ldq = stq_uop_9_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_uses_stq; // @[lsu.scala:252:32] wire s_uop_11_uses_stq = stq_uop_9_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_10_uses_stq = stq_uop_9_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_unique; // @[lsu.scala:252:32] wire s_uop_11_is_unique = stq_uop_9_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_unique = stq_uop_9_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_11_flush_on_commit = stq_uop_9_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_10_flush_on_commit = stq_uop_9_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_11_csr_cmd = stq_uop_9_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_csr_cmd = stq_uop_9_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_11_ldst_is_rs1 = stq_uop_9_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_10_ldst_is_rs1 = stq_uop_9_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_11_ldst = stq_uop_9_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_ldst = stq_uop_9_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_11_lrs1 = stq_uop_9_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_lrs1 = stq_uop_9_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_11_lrs2 = stq_uop_9_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_lrs2 = stq_uop_9_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_11_lrs3 = stq_uop_9_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_lrs3 = stq_uop_9_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_11_dst_rtype = stq_uop_9_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_dst_rtype = stq_uop_9_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_11_lrs1_rtype = stq_uop_9_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_lrs1_rtype = stq_uop_9_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_11_lrs2_rtype = stq_uop_9_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_lrs2_rtype = stq_uop_9_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_frs3_en; // @[lsu.scala:252:32] wire s_uop_11_frs3_en = stq_uop_9_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_10_frs3_en = stq_uop_9_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fcn_dw; // @[lsu.scala:252:32] wire s_uop_11_fcn_dw = stq_uop_9_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_10_fcn_dw = stq_uop_9_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_11_fcn_op = stq_uop_9_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_fcn_op = stq_uop_9_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_val; // @[lsu.scala:252:32] wire s_uop_11_fp_val = stq_uop_9_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_val = stq_uop_9_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_11_fp_rm = stq_uop_9_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_fp_rm = stq_uop_9_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_11_fp_typ = stq_uop_9_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_fp_typ = stq_uop_9_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_11_xcpt_pf_if = stq_uop_9_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_xcpt_pf_if = stq_uop_9_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_11_xcpt_ae_if = stq_uop_9_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_xcpt_ae_if = stq_uop_9_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_11_xcpt_ma_if = stq_uop_9_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_xcpt_ma_if = stq_uop_9_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_11_bp_debug_if = stq_uop_9_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_bp_debug_if = stq_uop_9_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_11_bp_xcpt_if = stq_uop_9_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_bp_xcpt_if = stq_uop_9_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_11_debug_fsrc = stq_uop_9_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_debug_fsrc = stq_uop_9_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_11_debug_tsrc = stq_uop_9_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_debug_tsrc = stq_uop_9_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_10_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_12_inst = stq_uop_10_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_11_inst = stq_uop_10_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_10_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_12_debug_inst = stq_uop_10_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_11_debug_inst = stq_uop_10_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_rvc; // @[lsu.scala:252:32] wire s_uop_12_is_rvc = stq_uop_10_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_rvc = stq_uop_10_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_10_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_12_debug_pc = stq_uop_10_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_11_debug_pc = stq_uop_10_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_0; // @[lsu.scala:252:32] wire s_uop_12_iq_type_0 = stq_uop_10_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_0 = stq_uop_10_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_1; // @[lsu.scala:252:32] wire s_uop_12_iq_type_1 = stq_uop_10_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_1 = stq_uop_10_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_2; // @[lsu.scala:252:32] wire s_uop_12_iq_type_2 = stq_uop_10_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_2 = stq_uop_10_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_3; // @[lsu.scala:252:32] wire s_uop_12_iq_type_3 = stq_uop_10_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_3 = stq_uop_10_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_0; // @[lsu.scala:252:32] wire s_uop_12_fu_code_0 = stq_uop_10_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_0 = stq_uop_10_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_1; // @[lsu.scala:252:32] wire s_uop_12_fu_code_1 = stq_uop_10_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_1 = stq_uop_10_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_2; // @[lsu.scala:252:32] wire s_uop_12_fu_code_2 = stq_uop_10_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_2 = stq_uop_10_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_3; // @[lsu.scala:252:32] wire s_uop_12_fu_code_3 = stq_uop_10_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_3 = stq_uop_10_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_4; // @[lsu.scala:252:32] wire s_uop_12_fu_code_4 = stq_uop_10_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_4 = stq_uop_10_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_5; // @[lsu.scala:252:32] wire s_uop_12_fu_code_5 = stq_uop_10_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_5 = stq_uop_10_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_6; // @[lsu.scala:252:32] wire s_uop_12_fu_code_6 = stq_uop_10_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_6 = stq_uop_10_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_7; // @[lsu.scala:252:32] wire s_uop_12_fu_code_7 = stq_uop_10_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_7 = stq_uop_10_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_8; // @[lsu.scala:252:32] wire s_uop_12_fu_code_8 = stq_uop_10_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_8 = stq_uop_10_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_9; // @[lsu.scala:252:32] wire s_uop_12_fu_code_9 = stq_uop_10_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_9 = stq_uop_10_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_issued; // @[lsu.scala:252:32] wire s_uop_12_iw_issued = stq_uop_10_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_issued = stq_uop_10_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_12_iw_issued_partial_agen = stq_uop_10_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_issued_partial_agen = stq_uop_10_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_12_iw_issued_partial_dgen = stq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_issued_partial_dgen = stq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_12_iw_p1_speculative_child = stq_uop_10_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_iw_p1_speculative_child = stq_uop_10_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_12_iw_p2_speculative_child = stq_uop_10_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_iw_p2_speculative_child = stq_uop_10_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_12_iw_p1_bypass_hint = stq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_p1_bypass_hint = stq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_12_iw_p2_bypass_hint = stq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_p2_bypass_hint = stq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_12_iw_p3_bypass_hint = stq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_p3_bypass_hint = stq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_12_dis_col_sel = stq_uop_10_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_dis_col_sel = stq_uop_10_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_10_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_12_br_mask = stq_uop_10_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_11_br_mask = stq_uop_10_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_10_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_12_br_tag = stq_uop_10_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_11_br_tag = stq_uop_10_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_10_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_12_br_type = stq_uop_10_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_11_br_type = stq_uop_10_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_sfb; // @[lsu.scala:252:32] wire s_uop_12_is_sfb = stq_uop_10_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_sfb = stq_uop_10_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_fence; // @[lsu.scala:252:32] wire s_uop_12_is_fence = stq_uop_10_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_fence = stq_uop_10_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_fencei; // @[lsu.scala:252:32] wire s_uop_12_is_fencei = stq_uop_10_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_fencei = stq_uop_10_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_sfence; // @[lsu.scala:252:32] wire s_uop_12_is_sfence = stq_uop_10_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_sfence = stq_uop_10_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_amo; // @[lsu.scala:252:32] wire s_uop_12_is_amo = stq_uop_10_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_amo = stq_uop_10_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_eret; // @[lsu.scala:252:32] wire s_uop_12_is_eret = stq_uop_10_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_eret = stq_uop_10_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_12_is_sys_pc2epc = stq_uop_10_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_sys_pc2epc = stq_uop_10_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_rocc; // @[lsu.scala:252:32] wire s_uop_12_is_rocc = stq_uop_10_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_rocc = stq_uop_10_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_mov; // @[lsu.scala:252:32] wire s_uop_12_is_mov = stq_uop_10_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_mov = stq_uop_10_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_12_ftq_idx = stq_uop_10_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_ftq_idx = stq_uop_10_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_edge_inst; // @[lsu.scala:252:32] wire s_uop_12_edge_inst = stq_uop_10_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_11_edge_inst = stq_uop_10_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_12_pc_lob = stq_uop_10_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_pc_lob = stq_uop_10_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_taken; // @[lsu.scala:252:32] wire s_uop_12_taken = stq_uop_10_taken; // @[lsu.scala:252:32, :1324:37] wire uop_11_taken = stq_uop_10_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_imm_rename; // @[lsu.scala:252:32] wire s_uop_12_imm_rename = stq_uop_10_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_11_imm_rename = stq_uop_10_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_12_imm_sel = stq_uop_10_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_imm_sel = stq_uop_10_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_12_pimm = stq_uop_10_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_pimm = stq_uop_10_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_10_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_12_imm_packed = stq_uop_10_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_11_imm_packed = stq_uop_10_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_12_op1_sel = stq_uop_10_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_op1_sel = stq_uop_10_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_12_op2_sel = stq_uop_10_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_op2_sel = stq_uop_10_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ldst = stq_uop_10_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ldst = stq_uop_10_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_wen = stq_uop_10_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_wen = stq_uop_10_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ren1 = stq_uop_10_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ren1 = stq_uop_10_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ren2 = stq_uop_10_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ren2 = stq_uop_10_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ren3 = stq_uop_10_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ren3 = stq_uop_10_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_swap12 = stq_uop_10_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_swap12 = stq_uop_10_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_swap23 = stq_uop_10_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_swap23 = stq_uop_10_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_12_fp_ctrl_typeTagIn = stq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_fp_ctrl_typeTagIn = stq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_12_fp_ctrl_typeTagOut = stq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_fp_ctrl_typeTagOut = stq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_fromint = stq_uop_10_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_fromint = stq_uop_10_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_toint = stq_uop_10_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_toint = stq_uop_10_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_fastpipe = stq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_fastpipe = stq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_fma = stq_uop_10_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_fma = stq_uop_10_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_div = stq_uop_10_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_div = stq_uop_10_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_sqrt = stq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_sqrt = stq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_wflags = stq_uop_10_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_wflags = stq_uop_10_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_vec = stq_uop_10_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_vec = stq_uop_10_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_12_rob_idx = stq_uop_10_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_rob_idx = stq_uop_10_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_10_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_12_ldq_idx = stq_uop_10_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_11_ldq_idx = stq_uop_10_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_10_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_12_stq_idx = stq_uop_10_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_11_stq_idx = stq_uop_10_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_12_rxq_idx = stq_uop_10_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_rxq_idx = stq_uop_10_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_12_pdst = stq_uop_10_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_pdst = stq_uop_10_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_12_prs1 = stq_uop_10_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_prs1 = stq_uop_10_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_12_prs2 = stq_uop_10_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_prs2 = stq_uop_10_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_12_prs3 = stq_uop_10_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_prs3 = stq_uop_10_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_12_ppred = stq_uop_10_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_ppred = stq_uop_10_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_prs1_busy; // @[lsu.scala:252:32] wire s_uop_12_prs1_busy = stq_uop_10_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_prs1_busy = stq_uop_10_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_prs2_busy; // @[lsu.scala:252:32] wire s_uop_12_prs2_busy = stq_uop_10_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_prs2_busy = stq_uop_10_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_prs3_busy; // @[lsu.scala:252:32] wire s_uop_12_prs3_busy = stq_uop_10_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_prs3_busy = stq_uop_10_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_ppred_busy; // @[lsu.scala:252:32] wire s_uop_12_ppred_busy = stq_uop_10_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_ppred_busy = stq_uop_10_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_12_stale_pdst = stq_uop_10_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_stale_pdst = stq_uop_10_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_exception; // @[lsu.scala:252:32] wire s_uop_12_exception = stq_uop_10_exception; // @[lsu.scala:252:32, :1324:37] wire uop_11_exception = stq_uop_10_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_10_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_12_exc_cause = stq_uop_10_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_11_exc_cause = stq_uop_10_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_12_mem_cmd = stq_uop_10_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_mem_cmd = stq_uop_10_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_12_mem_size = stq_uop_10_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_mem_size = stq_uop_10_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_mem_signed; // @[lsu.scala:252:32] wire s_uop_12_mem_signed = stq_uop_10_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_11_mem_signed = stq_uop_10_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_uses_ldq; // @[lsu.scala:252:32] wire s_uop_12_uses_ldq = stq_uop_10_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_11_uses_ldq = stq_uop_10_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_uses_stq; // @[lsu.scala:252:32] wire s_uop_12_uses_stq = stq_uop_10_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_11_uses_stq = stq_uop_10_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_unique; // @[lsu.scala:252:32] wire s_uop_12_is_unique = stq_uop_10_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_unique = stq_uop_10_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_12_flush_on_commit = stq_uop_10_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_11_flush_on_commit = stq_uop_10_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_12_csr_cmd = stq_uop_10_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_csr_cmd = stq_uop_10_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_12_ldst_is_rs1 = stq_uop_10_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_11_ldst_is_rs1 = stq_uop_10_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_12_ldst = stq_uop_10_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_ldst = stq_uop_10_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_12_lrs1 = stq_uop_10_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_lrs1 = stq_uop_10_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_12_lrs2 = stq_uop_10_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_lrs2 = stq_uop_10_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_12_lrs3 = stq_uop_10_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_lrs3 = stq_uop_10_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_12_dst_rtype = stq_uop_10_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_dst_rtype = stq_uop_10_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_12_lrs1_rtype = stq_uop_10_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_lrs1_rtype = stq_uop_10_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_12_lrs2_rtype = stq_uop_10_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_lrs2_rtype = stq_uop_10_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_frs3_en; // @[lsu.scala:252:32] wire s_uop_12_frs3_en = stq_uop_10_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_11_frs3_en = stq_uop_10_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fcn_dw; // @[lsu.scala:252:32] wire s_uop_12_fcn_dw = stq_uop_10_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_11_fcn_dw = stq_uop_10_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_12_fcn_op = stq_uop_10_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_fcn_op = stq_uop_10_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_val; // @[lsu.scala:252:32] wire s_uop_12_fp_val = stq_uop_10_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_val = stq_uop_10_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_12_fp_rm = stq_uop_10_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_fp_rm = stq_uop_10_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_12_fp_typ = stq_uop_10_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_fp_typ = stq_uop_10_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_12_xcpt_pf_if = stq_uop_10_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_xcpt_pf_if = stq_uop_10_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_12_xcpt_ae_if = stq_uop_10_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_xcpt_ae_if = stq_uop_10_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_12_xcpt_ma_if = stq_uop_10_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_xcpt_ma_if = stq_uop_10_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_12_bp_debug_if = stq_uop_10_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_bp_debug_if = stq_uop_10_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_12_bp_xcpt_if = stq_uop_10_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_bp_xcpt_if = stq_uop_10_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_12_debug_fsrc = stq_uop_10_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_debug_fsrc = stq_uop_10_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_12_debug_tsrc = stq_uop_10_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_debug_tsrc = stq_uop_10_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_11_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_13_inst = stq_uop_11_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_12_inst = stq_uop_11_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_11_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_13_debug_inst = stq_uop_11_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_12_debug_inst = stq_uop_11_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_rvc; // @[lsu.scala:252:32] wire s_uop_13_is_rvc = stq_uop_11_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_rvc = stq_uop_11_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_11_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_13_debug_pc = stq_uop_11_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_12_debug_pc = stq_uop_11_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_0; // @[lsu.scala:252:32] wire s_uop_13_iq_type_0 = stq_uop_11_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_0 = stq_uop_11_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_1; // @[lsu.scala:252:32] wire s_uop_13_iq_type_1 = stq_uop_11_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_1 = stq_uop_11_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_2; // @[lsu.scala:252:32] wire s_uop_13_iq_type_2 = stq_uop_11_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_2 = stq_uop_11_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_3; // @[lsu.scala:252:32] wire s_uop_13_iq_type_3 = stq_uop_11_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_3 = stq_uop_11_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_0; // @[lsu.scala:252:32] wire s_uop_13_fu_code_0 = stq_uop_11_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_0 = stq_uop_11_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_1; // @[lsu.scala:252:32] wire s_uop_13_fu_code_1 = stq_uop_11_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_1 = stq_uop_11_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_2; // @[lsu.scala:252:32] wire s_uop_13_fu_code_2 = stq_uop_11_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_2 = stq_uop_11_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_3; // @[lsu.scala:252:32] wire s_uop_13_fu_code_3 = stq_uop_11_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_3 = stq_uop_11_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_4; // @[lsu.scala:252:32] wire s_uop_13_fu_code_4 = stq_uop_11_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_4 = stq_uop_11_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_5; // @[lsu.scala:252:32] wire s_uop_13_fu_code_5 = stq_uop_11_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_5 = stq_uop_11_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_6; // @[lsu.scala:252:32] wire s_uop_13_fu_code_6 = stq_uop_11_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_6 = stq_uop_11_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_7; // @[lsu.scala:252:32] wire s_uop_13_fu_code_7 = stq_uop_11_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_7 = stq_uop_11_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_8; // @[lsu.scala:252:32] wire s_uop_13_fu_code_8 = stq_uop_11_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_8 = stq_uop_11_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_9; // @[lsu.scala:252:32] wire s_uop_13_fu_code_9 = stq_uop_11_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_9 = stq_uop_11_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_issued; // @[lsu.scala:252:32] wire s_uop_13_iw_issued = stq_uop_11_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_issued = stq_uop_11_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_13_iw_issued_partial_agen = stq_uop_11_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_issued_partial_agen = stq_uop_11_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_13_iw_issued_partial_dgen = stq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_issued_partial_dgen = stq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_13_iw_p1_speculative_child = stq_uop_11_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_iw_p1_speculative_child = stq_uop_11_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_13_iw_p2_speculative_child = stq_uop_11_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_iw_p2_speculative_child = stq_uop_11_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_13_iw_p1_bypass_hint = stq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_p1_bypass_hint = stq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_13_iw_p2_bypass_hint = stq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_p2_bypass_hint = stq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_13_iw_p3_bypass_hint = stq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_p3_bypass_hint = stq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_13_dis_col_sel = stq_uop_11_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_dis_col_sel = stq_uop_11_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_11_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_13_br_mask = stq_uop_11_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_12_br_mask = stq_uop_11_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_11_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_13_br_tag = stq_uop_11_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_12_br_tag = stq_uop_11_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_11_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_13_br_type = stq_uop_11_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_12_br_type = stq_uop_11_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_sfb; // @[lsu.scala:252:32] wire s_uop_13_is_sfb = stq_uop_11_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_sfb = stq_uop_11_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_fence; // @[lsu.scala:252:32] wire s_uop_13_is_fence = stq_uop_11_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_fence = stq_uop_11_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_fencei; // @[lsu.scala:252:32] wire s_uop_13_is_fencei = stq_uop_11_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_fencei = stq_uop_11_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_sfence; // @[lsu.scala:252:32] wire s_uop_13_is_sfence = stq_uop_11_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_sfence = stq_uop_11_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_amo; // @[lsu.scala:252:32] wire s_uop_13_is_amo = stq_uop_11_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_amo = stq_uop_11_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_eret; // @[lsu.scala:252:32] wire s_uop_13_is_eret = stq_uop_11_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_eret = stq_uop_11_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_13_is_sys_pc2epc = stq_uop_11_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_sys_pc2epc = stq_uop_11_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_rocc; // @[lsu.scala:252:32] wire s_uop_13_is_rocc = stq_uop_11_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_rocc = stq_uop_11_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_mov; // @[lsu.scala:252:32] wire s_uop_13_is_mov = stq_uop_11_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_mov = stq_uop_11_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_13_ftq_idx = stq_uop_11_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_ftq_idx = stq_uop_11_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_edge_inst; // @[lsu.scala:252:32] wire s_uop_13_edge_inst = stq_uop_11_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_12_edge_inst = stq_uop_11_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_13_pc_lob = stq_uop_11_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_pc_lob = stq_uop_11_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_taken; // @[lsu.scala:252:32] wire s_uop_13_taken = stq_uop_11_taken; // @[lsu.scala:252:32, :1324:37] wire uop_12_taken = stq_uop_11_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_imm_rename; // @[lsu.scala:252:32] wire s_uop_13_imm_rename = stq_uop_11_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_12_imm_rename = stq_uop_11_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_13_imm_sel = stq_uop_11_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_imm_sel = stq_uop_11_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_13_pimm = stq_uop_11_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_pimm = stq_uop_11_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_11_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_13_imm_packed = stq_uop_11_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_12_imm_packed = stq_uop_11_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_13_op1_sel = stq_uop_11_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_op1_sel = stq_uop_11_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_13_op2_sel = stq_uop_11_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_op2_sel = stq_uop_11_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ldst = stq_uop_11_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ldst = stq_uop_11_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_wen = stq_uop_11_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_wen = stq_uop_11_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ren1 = stq_uop_11_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ren1 = stq_uop_11_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ren2 = stq_uop_11_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ren2 = stq_uop_11_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ren3 = stq_uop_11_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ren3 = stq_uop_11_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_swap12 = stq_uop_11_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_swap12 = stq_uop_11_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_swap23 = stq_uop_11_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_swap23 = stq_uop_11_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_13_fp_ctrl_typeTagIn = stq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_fp_ctrl_typeTagIn = stq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_13_fp_ctrl_typeTagOut = stq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_fp_ctrl_typeTagOut = stq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_fromint = stq_uop_11_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_fromint = stq_uop_11_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_toint = stq_uop_11_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_toint = stq_uop_11_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_fastpipe = stq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_fastpipe = stq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_fma = stq_uop_11_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_fma = stq_uop_11_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_div = stq_uop_11_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_div = stq_uop_11_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_sqrt = stq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_sqrt = stq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_wflags = stq_uop_11_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_wflags = stq_uop_11_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_vec = stq_uop_11_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_vec = stq_uop_11_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_13_rob_idx = stq_uop_11_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_rob_idx = stq_uop_11_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_11_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_13_ldq_idx = stq_uop_11_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_12_ldq_idx = stq_uop_11_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_11_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_13_stq_idx = stq_uop_11_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_12_stq_idx = stq_uop_11_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_13_rxq_idx = stq_uop_11_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_rxq_idx = stq_uop_11_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_13_pdst = stq_uop_11_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_pdst = stq_uop_11_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_13_prs1 = stq_uop_11_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_prs1 = stq_uop_11_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_13_prs2 = stq_uop_11_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_prs2 = stq_uop_11_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_13_prs3 = stq_uop_11_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_prs3 = stq_uop_11_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_13_ppred = stq_uop_11_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_ppred = stq_uop_11_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_prs1_busy; // @[lsu.scala:252:32] wire s_uop_13_prs1_busy = stq_uop_11_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_prs1_busy = stq_uop_11_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_prs2_busy; // @[lsu.scala:252:32] wire s_uop_13_prs2_busy = stq_uop_11_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_prs2_busy = stq_uop_11_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_prs3_busy; // @[lsu.scala:252:32] wire s_uop_13_prs3_busy = stq_uop_11_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_prs3_busy = stq_uop_11_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_ppred_busy; // @[lsu.scala:252:32] wire s_uop_13_ppred_busy = stq_uop_11_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_ppred_busy = stq_uop_11_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_13_stale_pdst = stq_uop_11_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_stale_pdst = stq_uop_11_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_exception; // @[lsu.scala:252:32] wire s_uop_13_exception = stq_uop_11_exception; // @[lsu.scala:252:32, :1324:37] wire uop_12_exception = stq_uop_11_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_11_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_13_exc_cause = stq_uop_11_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_12_exc_cause = stq_uop_11_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_13_mem_cmd = stq_uop_11_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_mem_cmd = stq_uop_11_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_13_mem_size = stq_uop_11_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_mem_size = stq_uop_11_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_mem_signed; // @[lsu.scala:252:32] wire s_uop_13_mem_signed = stq_uop_11_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_12_mem_signed = stq_uop_11_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_uses_ldq; // @[lsu.scala:252:32] wire s_uop_13_uses_ldq = stq_uop_11_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_12_uses_ldq = stq_uop_11_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_uses_stq; // @[lsu.scala:252:32] wire s_uop_13_uses_stq = stq_uop_11_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_12_uses_stq = stq_uop_11_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_unique; // @[lsu.scala:252:32] wire s_uop_13_is_unique = stq_uop_11_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_unique = stq_uop_11_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_13_flush_on_commit = stq_uop_11_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_12_flush_on_commit = stq_uop_11_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_13_csr_cmd = stq_uop_11_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_csr_cmd = stq_uop_11_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_13_ldst_is_rs1 = stq_uop_11_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_12_ldst_is_rs1 = stq_uop_11_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_13_ldst = stq_uop_11_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_ldst = stq_uop_11_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_13_lrs1 = stq_uop_11_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_lrs1 = stq_uop_11_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_13_lrs2 = stq_uop_11_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_lrs2 = stq_uop_11_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_13_lrs3 = stq_uop_11_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_lrs3 = stq_uop_11_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_13_dst_rtype = stq_uop_11_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_dst_rtype = stq_uop_11_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_13_lrs1_rtype = stq_uop_11_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_lrs1_rtype = stq_uop_11_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_13_lrs2_rtype = stq_uop_11_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_lrs2_rtype = stq_uop_11_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_frs3_en; // @[lsu.scala:252:32] wire s_uop_13_frs3_en = stq_uop_11_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_12_frs3_en = stq_uop_11_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fcn_dw; // @[lsu.scala:252:32] wire s_uop_13_fcn_dw = stq_uop_11_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_12_fcn_dw = stq_uop_11_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_13_fcn_op = stq_uop_11_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_fcn_op = stq_uop_11_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_val; // @[lsu.scala:252:32] wire s_uop_13_fp_val = stq_uop_11_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_val = stq_uop_11_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_13_fp_rm = stq_uop_11_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_fp_rm = stq_uop_11_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_13_fp_typ = stq_uop_11_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_fp_typ = stq_uop_11_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_13_xcpt_pf_if = stq_uop_11_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_xcpt_pf_if = stq_uop_11_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_13_xcpt_ae_if = stq_uop_11_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_xcpt_ae_if = stq_uop_11_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_13_xcpt_ma_if = stq_uop_11_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_xcpt_ma_if = stq_uop_11_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_13_bp_debug_if = stq_uop_11_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_bp_debug_if = stq_uop_11_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_13_bp_xcpt_if = stq_uop_11_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_bp_xcpt_if = stq_uop_11_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_13_debug_fsrc = stq_uop_11_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_debug_fsrc = stq_uop_11_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_13_debug_tsrc = stq_uop_11_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_debug_tsrc = stq_uop_11_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_12_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_14_inst = stq_uop_12_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_13_inst = stq_uop_12_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_12_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_14_debug_inst = stq_uop_12_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_13_debug_inst = stq_uop_12_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_rvc; // @[lsu.scala:252:32] wire s_uop_14_is_rvc = stq_uop_12_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_rvc = stq_uop_12_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_12_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_14_debug_pc = stq_uop_12_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_13_debug_pc = stq_uop_12_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_0; // @[lsu.scala:252:32] wire s_uop_14_iq_type_0 = stq_uop_12_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_0 = stq_uop_12_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_1; // @[lsu.scala:252:32] wire s_uop_14_iq_type_1 = stq_uop_12_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_1 = stq_uop_12_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_2; // @[lsu.scala:252:32] wire s_uop_14_iq_type_2 = stq_uop_12_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_2 = stq_uop_12_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_3; // @[lsu.scala:252:32] wire s_uop_14_iq_type_3 = stq_uop_12_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_3 = stq_uop_12_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_0; // @[lsu.scala:252:32] wire s_uop_14_fu_code_0 = stq_uop_12_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_0 = stq_uop_12_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_1; // @[lsu.scala:252:32] wire s_uop_14_fu_code_1 = stq_uop_12_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_1 = stq_uop_12_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_2; // @[lsu.scala:252:32] wire s_uop_14_fu_code_2 = stq_uop_12_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_2 = stq_uop_12_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_3; // @[lsu.scala:252:32] wire s_uop_14_fu_code_3 = stq_uop_12_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_3 = stq_uop_12_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_4; // @[lsu.scala:252:32] wire s_uop_14_fu_code_4 = stq_uop_12_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_4 = stq_uop_12_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_5; // @[lsu.scala:252:32] wire s_uop_14_fu_code_5 = stq_uop_12_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_5 = stq_uop_12_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_6; // @[lsu.scala:252:32] wire s_uop_14_fu_code_6 = stq_uop_12_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_6 = stq_uop_12_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_7; // @[lsu.scala:252:32] wire s_uop_14_fu_code_7 = stq_uop_12_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_7 = stq_uop_12_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_8; // @[lsu.scala:252:32] wire s_uop_14_fu_code_8 = stq_uop_12_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_8 = stq_uop_12_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_9; // @[lsu.scala:252:32] wire s_uop_14_fu_code_9 = stq_uop_12_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_9 = stq_uop_12_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_issued; // @[lsu.scala:252:32] wire s_uop_14_iw_issued = stq_uop_12_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_issued = stq_uop_12_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_14_iw_issued_partial_agen = stq_uop_12_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_issued_partial_agen = stq_uop_12_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_14_iw_issued_partial_dgen = stq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_issued_partial_dgen = stq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_14_iw_p1_speculative_child = stq_uop_12_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_iw_p1_speculative_child = stq_uop_12_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_14_iw_p2_speculative_child = stq_uop_12_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_iw_p2_speculative_child = stq_uop_12_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_14_iw_p1_bypass_hint = stq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_p1_bypass_hint = stq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_14_iw_p2_bypass_hint = stq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_p2_bypass_hint = stq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_14_iw_p3_bypass_hint = stq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_p3_bypass_hint = stq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_14_dis_col_sel = stq_uop_12_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_dis_col_sel = stq_uop_12_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_12_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_14_br_mask = stq_uop_12_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_13_br_mask = stq_uop_12_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_12_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_14_br_tag = stq_uop_12_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_13_br_tag = stq_uop_12_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_12_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_14_br_type = stq_uop_12_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_13_br_type = stq_uop_12_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_sfb; // @[lsu.scala:252:32] wire s_uop_14_is_sfb = stq_uop_12_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_sfb = stq_uop_12_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_fence; // @[lsu.scala:252:32] wire s_uop_14_is_fence = stq_uop_12_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_fence = stq_uop_12_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_fencei; // @[lsu.scala:252:32] wire s_uop_14_is_fencei = stq_uop_12_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_fencei = stq_uop_12_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_sfence; // @[lsu.scala:252:32] wire s_uop_14_is_sfence = stq_uop_12_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_sfence = stq_uop_12_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_amo; // @[lsu.scala:252:32] wire s_uop_14_is_amo = stq_uop_12_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_amo = stq_uop_12_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_eret; // @[lsu.scala:252:32] wire s_uop_14_is_eret = stq_uop_12_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_eret = stq_uop_12_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_14_is_sys_pc2epc = stq_uop_12_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_sys_pc2epc = stq_uop_12_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_rocc; // @[lsu.scala:252:32] wire s_uop_14_is_rocc = stq_uop_12_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_rocc = stq_uop_12_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_mov; // @[lsu.scala:252:32] wire s_uop_14_is_mov = stq_uop_12_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_mov = stq_uop_12_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_14_ftq_idx = stq_uop_12_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_ftq_idx = stq_uop_12_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_edge_inst; // @[lsu.scala:252:32] wire s_uop_14_edge_inst = stq_uop_12_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_13_edge_inst = stq_uop_12_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_14_pc_lob = stq_uop_12_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_pc_lob = stq_uop_12_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_taken; // @[lsu.scala:252:32] wire s_uop_14_taken = stq_uop_12_taken; // @[lsu.scala:252:32, :1324:37] wire uop_13_taken = stq_uop_12_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_imm_rename; // @[lsu.scala:252:32] wire s_uop_14_imm_rename = stq_uop_12_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_13_imm_rename = stq_uop_12_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_14_imm_sel = stq_uop_12_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_imm_sel = stq_uop_12_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_14_pimm = stq_uop_12_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_pimm = stq_uop_12_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_12_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_14_imm_packed = stq_uop_12_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_13_imm_packed = stq_uop_12_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_14_op1_sel = stq_uop_12_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_op1_sel = stq_uop_12_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_14_op2_sel = stq_uop_12_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_op2_sel = stq_uop_12_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ldst = stq_uop_12_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ldst = stq_uop_12_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_wen = stq_uop_12_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_wen = stq_uop_12_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ren1 = stq_uop_12_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ren1 = stq_uop_12_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ren2 = stq_uop_12_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ren2 = stq_uop_12_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ren3 = stq_uop_12_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ren3 = stq_uop_12_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_swap12 = stq_uop_12_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_swap12 = stq_uop_12_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_swap23 = stq_uop_12_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_swap23 = stq_uop_12_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_14_fp_ctrl_typeTagIn = stq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_fp_ctrl_typeTagIn = stq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_14_fp_ctrl_typeTagOut = stq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_fp_ctrl_typeTagOut = stq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_fromint = stq_uop_12_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_fromint = stq_uop_12_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_toint = stq_uop_12_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_toint = stq_uop_12_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_fastpipe = stq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_fastpipe = stq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_fma = stq_uop_12_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_fma = stq_uop_12_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_div = stq_uop_12_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_div = stq_uop_12_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_sqrt = stq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_sqrt = stq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_wflags = stq_uop_12_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_wflags = stq_uop_12_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_vec = stq_uop_12_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_vec = stq_uop_12_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_14_rob_idx = stq_uop_12_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_rob_idx = stq_uop_12_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_12_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_14_ldq_idx = stq_uop_12_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_13_ldq_idx = stq_uop_12_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_12_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_14_stq_idx = stq_uop_12_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_13_stq_idx = stq_uop_12_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_14_rxq_idx = stq_uop_12_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_rxq_idx = stq_uop_12_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_14_pdst = stq_uop_12_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_pdst = stq_uop_12_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_14_prs1 = stq_uop_12_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_prs1 = stq_uop_12_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_14_prs2 = stq_uop_12_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_prs2 = stq_uop_12_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_14_prs3 = stq_uop_12_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_prs3 = stq_uop_12_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_14_ppred = stq_uop_12_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_ppred = stq_uop_12_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_prs1_busy; // @[lsu.scala:252:32] wire s_uop_14_prs1_busy = stq_uop_12_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_prs1_busy = stq_uop_12_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_prs2_busy; // @[lsu.scala:252:32] wire s_uop_14_prs2_busy = stq_uop_12_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_prs2_busy = stq_uop_12_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_prs3_busy; // @[lsu.scala:252:32] wire s_uop_14_prs3_busy = stq_uop_12_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_prs3_busy = stq_uop_12_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_ppred_busy; // @[lsu.scala:252:32] wire s_uop_14_ppred_busy = stq_uop_12_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_ppred_busy = stq_uop_12_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_14_stale_pdst = stq_uop_12_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_stale_pdst = stq_uop_12_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_exception; // @[lsu.scala:252:32] wire s_uop_14_exception = stq_uop_12_exception; // @[lsu.scala:252:32, :1324:37] wire uop_13_exception = stq_uop_12_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_12_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_14_exc_cause = stq_uop_12_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_13_exc_cause = stq_uop_12_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_14_mem_cmd = stq_uop_12_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_mem_cmd = stq_uop_12_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_14_mem_size = stq_uop_12_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_mem_size = stq_uop_12_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_mem_signed; // @[lsu.scala:252:32] wire s_uop_14_mem_signed = stq_uop_12_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_13_mem_signed = stq_uop_12_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_uses_ldq; // @[lsu.scala:252:32] wire s_uop_14_uses_ldq = stq_uop_12_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_13_uses_ldq = stq_uop_12_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_uses_stq; // @[lsu.scala:252:32] wire s_uop_14_uses_stq = stq_uop_12_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_13_uses_stq = stq_uop_12_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_unique; // @[lsu.scala:252:32] wire s_uop_14_is_unique = stq_uop_12_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_unique = stq_uop_12_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_14_flush_on_commit = stq_uop_12_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_13_flush_on_commit = stq_uop_12_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_14_csr_cmd = stq_uop_12_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_csr_cmd = stq_uop_12_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_14_ldst_is_rs1 = stq_uop_12_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_13_ldst_is_rs1 = stq_uop_12_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_14_ldst = stq_uop_12_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_ldst = stq_uop_12_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_14_lrs1 = stq_uop_12_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_lrs1 = stq_uop_12_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_14_lrs2 = stq_uop_12_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_lrs2 = stq_uop_12_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_14_lrs3 = stq_uop_12_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_lrs3 = stq_uop_12_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_14_dst_rtype = stq_uop_12_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_dst_rtype = stq_uop_12_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_14_lrs1_rtype = stq_uop_12_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_lrs1_rtype = stq_uop_12_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_14_lrs2_rtype = stq_uop_12_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_lrs2_rtype = stq_uop_12_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_frs3_en; // @[lsu.scala:252:32] wire s_uop_14_frs3_en = stq_uop_12_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_13_frs3_en = stq_uop_12_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fcn_dw; // @[lsu.scala:252:32] wire s_uop_14_fcn_dw = stq_uop_12_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_13_fcn_dw = stq_uop_12_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_14_fcn_op = stq_uop_12_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_fcn_op = stq_uop_12_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_val; // @[lsu.scala:252:32] wire s_uop_14_fp_val = stq_uop_12_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_val = stq_uop_12_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_14_fp_rm = stq_uop_12_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_fp_rm = stq_uop_12_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_14_fp_typ = stq_uop_12_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_fp_typ = stq_uop_12_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_14_xcpt_pf_if = stq_uop_12_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_xcpt_pf_if = stq_uop_12_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_14_xcpt_ae_if = stq_uop_12_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_xcpt_ae_if = stq_uop_12_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_14_xcpt_ma_if = stq_uop_12_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_xcpt_ma_if = stq_uop_12_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_14_bp_debug_if = stq_uop_12_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_bp_debug_if = stq_uop_12_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_14_bp_xcpt_if = stq_uop_12_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_bp_xcpt_if = stq_uop_12_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_14_debug_fsrc = stq_uop_12_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_debug_fsrc = stq_uop_12_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_14_debug_tsrc = stq_uop_12_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_debug_tsrc = stq_uop_12_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_13_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_15_inst = stq_uop_13_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_14_inst = stq_uop_13_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_13_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_15_debug_inst = stq_uop_13_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_14_debug_inst = stq_uop_13_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_rvc; // @[lsu.scala:252:32] wire s_uop_15_is_rvc = stq_uop_13_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_rvc = stq_uop_13_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_13_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_15_debug_pc = stq_uop_13_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_14_debug_pc = stq_uop_13_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_0; // @[lsu.scala:252:32] wire s_uop_15_iq_type_0 = stq_uop_13_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_0 = stq_uop_13_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_1; // @[lsu.scala:252:32] wire s_uop_15_iq_type_1 = stq_uop_13_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_1 = stq_uop_13_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_2; // @[lsu.scala:252:32] wire s_uop_15_iq_type_2 = stq_uop_13_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_2 = stq_uop_13_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_3; // @[lsu.scala:252:32] wire s_uop_15_iq_type_3 = stq_uop_13_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_3 = stq_uop_13_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_0; // @[lsu.scala:252:32] wire s_uop_15_fu_code_0 = stq_uop_13_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_0 = stq_uop_13_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_1; // @[lsu.scala:252:32] wire s_uop_15_fu_code_1 = stq_uop_13_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_1 = stq_uop_13_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_2; // @[lsu.scala:252:32] wire s_uop_15_fu_code_2 = stq_uop_13_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_2 = stq_uop_13_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_3; // @[lsu.scala:252:32] wire s_uop_15_fu_code_3 = stq_uop_13_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_3 = stq_uop_13_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_4; // @[lsu.scala:252:32] wire s_uop_15_fu_code_4 = stq_uop_13_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_4 = stq_uop_13_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_5; // @[lsu.scala:252:32] wire s_uop_15_fu_code_5 = stq_uop_13_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_5 = stq_uop_13_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_6; // @[lsu.scala:252:32] wire s_uop_15_fu_code_6 = stq_uop_13_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_6 = stq_uop_13_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_7; // @[lsu.scala:252:32] wire s_uop_15_fu_code_7 = stq_uop_13_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_7 = stq_uop_13_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_8; // @[lsu.scala:252:32] wire s_uop_15_fu_code_8 = stq_uop_13_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_8 = stq_uop_13_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_9; // @[lsu.scala:252:32] wire s_uop_15_fu_code_9 = stq_uop_13_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_9 = stq_uop_13_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_issued; // @[lsu.scala:252:32] wire s_uop_15_iw_issued = stq_uop_13_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_issued = stq_uop_13_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_15_iw_issued_partial_agen = stq_uop_13_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_issued_partial_agen = stq_uop_13_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_15_iw_issued_partial_dgen = stq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_issued_partial_dgen = stq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_15_iw_p1_speculative_child = stq_uop_13_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_iw_p1_speculative_child = stq_uop_13_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_15_iw_p2_speculative_child = stq_uop_13_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_iw_p2_speculative_child = stq_uop_13_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_15_iw_p1_bypass_hint = stq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_p1_bypass_hint = stq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_15_iw_p2_bypass_hint = stq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_p2_bypass_hint = stq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_15_iw_p3_bypass_hint = stq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_p3_bypass_hint = stq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_15_dis_col_sel = stq_uop_13_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_dis_col_sel = stq_uop_13_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_13_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_15_br_mask = stq_uop_13_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_14_br_mask = stq_uop_13_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_13_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_15_br_tag = stq_uop_13_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_14_br_tag = stq_uop_13_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_13_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_15_br_type = stq_uop_13_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_14_br_type = stq_uop_13_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_sfb; // @[lsu.scala:252:32] wire s_uop_15_is_sfb = stq_uop_13_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_sfb = stq_uop_13_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_fence; // @[lsu.scala:252:32] wire s_uop_15_is_fence = stq_uop_13_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_fence = stq_uop_13_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_fencei; // @[lsu.scala:252:32] wire s_uop_15_is_fencei = stq_uop_13_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_fencei = stq_uop_13_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_sfence; // @[lsu.scala:252:32] wire s_uop_15_is_sfence = stq_uop_13_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_sfence = stq_uop_13_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_amo; // @[lsu.scala:252:32] wire s_uop_15_is_amo = stq_uop_13_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_amo = stq_uop_13_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_eret; // @[lsu.scala:252:32] wire s_uop_15_is_eret = stq_uop_13_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_eret = stq_uop_13_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_15_is_sys_pc2epc = stq_uop_13_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_sys_pc2epc = stq_uop_13_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_rocc; // @[lsu.scala:252:32] wire s_uop_15_is_rocc = stq_uop_13_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_rocc = stq_uop_13_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_mov; // @[lsu.scala:252:32] wire s_uop_15_is_mov = stq_uop_13_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_mov = stq_uop_13_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_15_ftq_idx = stq_uop_13_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_ftq_idx = stq_uop_13_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_edge_inst; // @[lsu.scala:252:32] wire s_uop_15_edge_inst = stq_uop_13_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_14_edge_inst = stq_uop_13_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_15_pc_lob = stq_uop_13_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_pc_lob = stq_uop_13_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_taken; // @[lsu.scala:252:32] wire s_uop_15_taken = stq_uop_13_taken; // @[lsu.scala:252:32, :1324:37] wire uop_14_taken = stq_uop_13_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_imm_rename; // @[lsu.scala:252:32] wire s_uop_15_imm_rename = stq_uop_13_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_14_imm_rename = stq_uop_13_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_15_imm_sel = stq_uop_13_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_imm_sel = stq_uop_13_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_15_pimm = stq_uop_13_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_pimm = stq_uop_13_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_13_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_15_imm_packed = stq_uop_13_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_14_imm_packed = stq_uop_13_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_15_op1_sel = stq_uop_13_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_op1_sel = stq_uop_13_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_15_op2_sel = stq_uop_13_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_op2_sel = stq_uop_13_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ldst = stq_uop_13_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ldst = stq_uop_13_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_wen = stq_uop_13_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_wen = stq_uop_13_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ren1 = stq_uop_13_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ren1 = stq_uop_13_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ren2 = stq_uop_13_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ren2 = stq_uop_13_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ren3 = stq_uop_13_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ren3 = stq_uop_13_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_swap12 = stq_uop_13_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_swap12 = stq_uop_13_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_swap23 = stq_uop_13_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_swap23 = stq_uop_13_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_15_fp_ctrl_typeTagIn = stq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_fp_ctrl_typeTagIn = stq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_15_fp_ctrl_typeTagOut = stq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_fp_ctrl_typeTagOut = stq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_fromint = stq_uop_13_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_fromint = stq_uop_13_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_toint = stq_uop_13_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_toint = stq_uop_13_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_fastpipe = stq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_fastpipe = stq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_fma = stq_uop_13_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_fma = stq_uop_13_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_div = stq_uop_13_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_div = stq_uop_13_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_sqrt = stq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_sqrt = stq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_wflags = stq_uop_13_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_wflags = stq_uop_13_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_vec = stq_uop_13_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_vec = stq_uop_13_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_15_rob_idx = stq_uop_13_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_rob_idx = stq_uop_13_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_13_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_15_ldq_idx = stq_uop_13_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_14_ldq_idx = stq_uop_13_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_13_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_15_stq_idx = stq_uop_13_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_14_stq_idx = stq_uop_13_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_15_rxq_idx = stq_uop_13_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_rxq_idx = stq_uop_13_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_15_pdst = stq_uop_13_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_pdst = stq_uop_13_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_15_prs1 = stq_uop_13_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_prs1 = stq_uop_13_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_15_prs2 = stq_uop_13_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_prs2 = stq_uop_13_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_15_prs3 = stq_uop_13_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_prs3 = stq_uop_13_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_15_ppred = stq_uop_13_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_ppred = stq_uop_13_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_prs1_busy; // @[lsu.scala:252:32] wire s_uop_15_prs1_busy = stq_uop_13_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_prs1_busy = stq_uop_13_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_prs2_busy; // @[lsu.scala:252:32] wire s_uop_15_prs2_busy = stq_uop_13_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_prs2_busy = stq_uop_13_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_prs3_busy; // @[lsu.scala:252:32] wire s_uop_15_prs3_busy = stq_uop_13_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_prs3_busy = stq_uop_13_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_ppred_busy; // @[lsu.scala:252:32] wire s_uop_15_ppred_busy = stq_uop_13_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_ppred_busy = stq_uop_13_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_15_stale_pdst = stq_uop_13_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_stale_pdst = stq_uop_13_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_exception; // @[lsu.scala:252:32] wire s_uop_15_exception = stq_uop_13_exception; // @[lsu.scala:252:32, :1324:37] wire uop_14_exception = stq_uop_13_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_13_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_15_exc_cause = stq_uop_13_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_14_exc_cause = stq_uop_13_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_15_mem_cmd = stq_uop_13_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_mem_cmd = stq_uop_13_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_15_mem_size = stq_uop_13_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_mem_size = stq_uop_13_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_mem_signed; // @[lsu.scala:252:32] wire s_uop_15_mem_signed = stq_uop_13_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_14_mem_signed = stq_uop_13_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_uses_ldq; // @[lsu.scala:252:32] wire s_uop_15_uses_ldq = stq_uop_13_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_14_uses_ldq = stq_uop_13_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_uses_stq; // @[lsu.scala:252:32] wire s_uop_15_uses_stq = stq_uop_13_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_14_uses_stq = stq_uop_13_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_unique; // @[lsu.scala:252:32] wire s_uop_15_is_unique = stq_uop_13_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_unique = stq_uop_13_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_15_flush_on_commit = stq_uop_13_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_14_flush_on_commit = stq_uop_13_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_15_csr_cmd = stq_uop_13_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_csr_cmd = stq_uop_13_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_15_ldst_is_rs1 = stq_uop_13_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_14_ldst_is_rs1 = stq_uop_13_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_15_ldst = stq_uop_13_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_ldst = stq_uop_13_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_15_lrs1 = stq_uop_13_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_lrs1 = stq_uop_13_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_15_lrs2 = stq_uop_13_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_lrs2 = stq_uop_13_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_15_lrs3 = stq_uop_13_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_lrs3 = stq_uop_13_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_15_dst_rtype = stq_uop_13_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_dst_rtype = stq_uop_13_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_15_lrs1_rtype = stq_uop_13_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_lrs1_rtype = stq_uop_13_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_15_lrs2_rtype = stq_uop_13_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_lrs2_rtype = stq_uop_13_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_frs3_en; // @[lsu.scala:252:32] wire s_uop_15_frs3_en = stq_uop_13_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_14_frs3_en = stq_uop_13_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fcn_dw; // @[lsu.scala:252:32] wire s_uop_15_fcn_dw = stq_uop_13_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_14_fcn_dw = stq_uop_13_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_15_fcn_op = stq_uop_13_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_fcn_op = stq_uop_13_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_val; // @[lsu.scala:252:32] wire s_uop_15_fp_val = stq_uop_13_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_val = stq_uop_13_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_15_fp_rm = stq_uop_13_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_fp_rm = stq_uop_13_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_15_fp_typ = stq_uop_13_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_fp_typ = stq_uop_13_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_15_xcpt_pf_if = stq_uop_13_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_xcpt_pf_if = stq_uop_13_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_15_xcpt_ae_if = stq_uop_13_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_xcpt_ae_if = stq_uop_13_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_15_xcpt_ma_if = stq_uop_13_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_xcpt_ma_if = stq_uop_13_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_15_bp_debug_if = stq_uop_13_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_bp_debug_if = stq_uop_13_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_15_bp_xcpt_if = stq_uop_13_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_bp_xcpt_if = stq_uop_13_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_15_debug_fsrc = stq_uop_13_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_debug_fsrc = stq_uop_13_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_15_debug_tsrc = stq_uop_13_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_debug_tsrc = stq_uop_13_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_14_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_16_inst = stq_uop_14_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_15_inst = stq_uop_14_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_14_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_16_debug_inst = stq_uop_14_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_15_debug_inst = stq_uop_14_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_rvc; // @[lsu.scala:252:32] wire s_uop_16_is_rvc = stq_uop_14_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_rvc = stq_uop_14_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_14_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_16_debug_pc = stq_uop_14_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_15_debug_pc = stq_uop_14_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_0; // @[lsu.scala:252:32] wire s_uop_16_iq_type_0 = stq_uop_14_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_0 = stq_uop_14_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_1; // @[lsu.scala:252:32] wire s_uop_16_iq_type_1 = stq_uop_14_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_1 = stq_uop_14_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_2; // @[lsu.scala:252:32] wire s_uop_16_iq_type_2 = stq_uop_14_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_2 = stq_uop_14_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_3; // @[lsu.scala:252:32] wire s_uop_16_iq_type_3 = stq_uop_14_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_3 = stq_uop_14_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_0; // @[lsu.scala:252:32] wire s_uop_16_fu_code_0 = stq_uop_14_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_0 = stq_uop_14_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_1; // @[lsu.scala:252:32] wire s_uop_16_fu_code_1 = stq_uop_14_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_1 = stq_uop_14_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_2; // @[lsu.scala:252:32] wire s_uop_16_fu_code_2 = stq_uop_14_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_2 = stq_uop_14_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_3; // @[lsu.scala:252:32] wire s_uop_16_fu_code_3 = stq_uop_14_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_3 = stq_uop_14_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_4; // @[lsu.scala:252:32] wire s_uop_16_fu_code_4 = stq_uop_14_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_4 = stq_uop_14_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_5; // @[lsu.scala:252:32] wire s_uop_16_fu_code_5 = stq_uop_14_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_5 = stq_uop_14_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_6; // @[lsu.scala:252:32] wire s_uop_16_fu_code_6 = stq_uop_14_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_6 = stq_uop_14_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_7; // @[lsu.scala:252:32] wire s_uop_16_fu_code_7 = stq_uop_14_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_7 = stq_uop_14_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_8; // @[lsu.scala:252:32] wire s_uop_16_fu_code_8 = stq_uop_14_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_8 = stq_uop_14_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_9; // @[lsu.scala:252:32] wire s_uop_16_fu_code_9 = stq_uop_14_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_9 = stq_uop_14_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_issued; // @[lsu.scala:252:32] wire s_uop_16_iw_issued = stq_uop_14_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_issued = stq_uop_14_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_16_iw_issued_partial_agen = stq_uop_14_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_issued_partial_agen = stq_uop_14_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_16_iw_issued_partial_dgen = stq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_issued_partial_dgen = stq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_16_iw_p1_speculative_child = stq_uop_14_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_iw_p1_speculative_child = stq_uop_14_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_16_iw_p2_speculative_child = stq_uop_14_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_iw_p2_speculative_child = stq_uop_14_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_16_iw_p1_bypass_hint = stq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_p1_bypass_hint = stq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_16_iw_p2_bypass_hint = stq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_p2_bypass_hint = stq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_16_iw_p3_bypass_hint = stq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_p3_bypass_hint = stq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_16_dis_col_sel = stq_uop_14_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_dis_col_sel = stq_uop_14_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_14_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_16_br_mask = stq_uop_14_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_15_br_mask = stq_uop_14_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_14_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_16_br_tag = stq_uop_14_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_15_br_tag = stq_uop_14_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_14_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_16_br_type = stq_uop_14_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_15_br_type = stq_uop_14_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_sfb; // @[lsu.scala:252:32] wire s_uop_16_is_sfb = stq_uop_14_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_sfb = stq_uop_14_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_fence; // @[lsu.scala:252:32] wire s_uop_16_is_fence = stq_uop_14_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_fence = stq_uop_14_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_fencei; // @[lsu.scala:252:32] wire s_uop_16_is_fencei = stq_uop_14_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_fencei = stq_uop_14_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_sfence; // @[lsu.scala:252:32] wire s_uop_16_is_sfence = stq_uop_14_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_sfence = stq_uop_14_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_amo; // @[lsu.scala:252:32] wire s_uop_16_is_amo = stq_uop_14_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_amo = stq_uop_14_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_eret; // @[lsu.scala:252:32] wire s_uop_16_is_eret = stq_uop_14_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_eret = stq_uop_14_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_16_is_sys_pc2epc = stq_uop_14_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_sys_pc2epc = stq_uop_14_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_rocc; // @[lsu.scala:252:32] wire s_uop_16_is_rocc = stq_uop_14_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_rocc = stq_uop_14_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_mov; // @[lsu.scala:252:32] wire s_uop_16_is_mov = stq_uop_14_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_mov = stq_uop_14_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_16_ftq_idx = stq_uop_14_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_ftq_idx = stq_uop_14_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_edge_inst; // @[lsu.scala:252:32] wire s_uop_16_edge_inst = stq_uop_14_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_15_edge_inst = stq_uop_14_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_16_pc_lob = stq_uop_14_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_pc_lob = stq_uop_14_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_taken; // @[lsu.scala:252:32] wire s_uop_16_taken = stq_uop_14_taken; // @[lsu.scala:252:32, :1324:37] wire uop_15_taken = stq_uop_14_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_imm_rename; // @[lsu.scala:252:32] wire s_uop_16_imm_rename = stq_uop_14_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_15_imm_rename = stq_uop_14_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_16_imm_sel = stq_uop_14_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_imm_sel = stq_uop_14_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_16_pimm = stq_uop_14_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_pimm = stq_uop_14_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_14_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_16_imm_packed = stq_uop_14_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_15_imm_packed = stq_uop_14_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_16_op1_sel = stq_uop_14_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_op1_sel = stq_uop_14_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_16_op2_sel = stq_uop_14_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_op2_sel = stq_uop_14_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ldst = stq_uop_14_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ldst = stq_uop_14_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_wen = stq_uop_14_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_wen = stq_uop_14_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ren1 = stq_uop_14_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ren1 = stq_uop_14_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ren2 = stq_uop_14_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ren2 = stq_uop_14_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ren3 = stq_uop_14_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ren3 = stq_uop_14_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_swap12 = stq_uop_14_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_swap12 = stq_uop_14_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_swap23 = stq_uop_14_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_swap23 = stq_uop_14_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_16_fp_ctrl_typeTagIn = stq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_fp_ctrl_typeTagIn = stq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_16_fp_ctrl_typeTagOut = stq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_fp_ctrl_typeTagOut = stq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_fromint = stq_uop_14_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_fromint = stq_uop_14_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_toint = stq_uop_14_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_toint = stq_uop_14_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_fastpipe = stq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_fastpipe = stq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_fma = stq_uop_14_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_fma = stq_uop_14_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_div = stq_uop_14_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_div = stq_uop_14_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_sqrt = stq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_sqrt = stq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_wflags = stq_uop_14_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_wflags = stq_uop_14_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_vec = stq_uop_14_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_vec = stq_uop_14_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_16_rob_idx = stq_uop_14_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_rob_idx = stq_uop_14_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_14_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_16_ldq_idx = stq_uop_14_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_15_ldq_idx = stq_uop_14_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_14_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_16_stq_idx = stq_uop_14_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_15_stq_idx = stq_uop_14_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_16_rxq_idx = stq_uop_14_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_rxq_idx = stq_uop_14_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_16_pdst = stq_uop_14_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_pdst = stq_uop_14_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_16_prs1 = stq_uop_14_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_prs1 = stq_uop_14_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_16_prs2 = stq_uop_14_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_prs2 = stq_uop_14_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_16_prs3 = stq_uop_14_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_prs3 = stq_uop_14_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_16_ppred = stq_uop_14_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_ppred = stq_uop_14_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_prs1_busy; // @[lsu.scala:252:32] wire s_uop_16_prs1_busy = stq_uop_14_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_prs1_busy = stq_uop_14_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_prs2_busy; // @[lsu.scala:252:32] wire s_uop_16_prs2_busy = stq_uop_14_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_prs2_busy = stq_uop_14_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_prs3_busy; // @[lsu.scala:252:32] wire s_uop_16_prs3_busy = stq_uop_14_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_prs3_busy = stq_uop_14_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_ppred_busy; // @[lsu.scala:252:32] wire s_uop_16_ppred_busy = stq_uop_14_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_ppred_busy = stq_uop_14_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_16_stale_pdst = stq_uop_14_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_stale_pdst = stq_uop_14_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_exception; // @[lsu.scala:252:32] wire s_uop_16_exception = stq_uop_14_exception; // @[lsu.scala:252:32, :1324:37] wire uop_15_exception = stq_uop_14_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_14_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_16_exc_cause = stq_uop_14_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_15_exc_cause = stq_uop_14_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_16_mem_cmd = stq_uop_14_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_mem_cmd = stq_uop_14_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_16_mem_size = stq_uop_14_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_mem_size = stq_uop_14_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_mem_signed; // @[lsu.scala:252:32] wire s_uop_16_mem_signed = stq_uop_14_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_15_mem_signed = stq_uop_14_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_uses_ldq; // @[lsu.scala:252:32] wire s_uop_16_uses_ldq = stq_uop_14_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_15_uses_ldq = stq_uop_14_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_uses_stq; // @[lsu.scala:252:32] wire s_uop_16_uses_stq = stq_uop_14_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_15_uses_stq = stq_uop_14_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_unique; // @[lsu.scala:252:32] wire s_uop_16_is_unique = stq_uop_14_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_unique = stq_uop_14_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_16_flush_on_commit = stq_uop_14_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_15_flush_on_commit = stq_uop_14_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_16_csr_cmd = stq_uop_14_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_csr_cmd = stq_uop_14_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_16_ldst_is_rs1 = stq_uop_14_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_15_ldst_is_rs1 = stq_uop_14_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_16_ldst = stq_uop_14_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_ldst = stq_uop_14_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_16_lrs1 = stq_uop_14_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_lrs1 = stq_uop_14_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_16_lrs2 = stq_uop_14_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_lrs2 = stq_uop_14_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_16_lrs3 = stq_uop_14_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_lrs3 = stq_uop_14_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_16_dst_rtype = stq_uop_14_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_dst_rtype = stq_uop_14_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_16_lrs1_rtype = stq_uop_14_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_lrs1_rtype = stq_uop_14_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_16_lrs2_rtype = stq_uop_14_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_lrs2_rtype = stq_uop_14_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_frs3_en; // @[lsu.scala:252:32] wire s_uop_16_frs3_en = stq_uop_14_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_15_frs3_en = stq_uop_14_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fcn_dw; // @[lsu.scala:252:32] wire s_uop_16_fcn_dw = stq_uop_14_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_15_fcn_dw = stq_uop_14_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_16_fcn_op = stq_uop_14_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_fcn_op = stq_uop_14_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_val; // @[lsu.scala:252:32] wire s_uop_16_fp_val = stq_uop_14_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_val = stq_uop_14_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_16_fp_rm = stq_uop_14_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_fp_rm = stq_uop_14_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_16_fp_typ = stq_uop_14_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_fp_typ = stq_uop_14_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_16_xcpt_pf_if = stq_uop_14_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_xcpt_pf_if = stq_uop_14_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_16_xcpt_ae_if = stq_uop_14_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_xcpt_ae_if = stq_uop_14_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_16_xcpt_ma_if = stq_uop_14_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_xcpt_ma_if = stq_uop_14_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_16_bp_debug_if = stq_uop_14_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_bp_debug_if = stq_uop_14_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_16_bp_xcpt_if = stq_uop_14_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_bp_xcpt_if = stq_uop_14_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_16_debug_fsrc = stq_uop_14_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_debug_fsrc = stq_uop_14_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_16_debug_tsrc = stq_uop_14_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_debug_tsrc = stq_uop_14_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_15_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_17_inst = stq_uop_15_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_16_inst = stq_uop_15_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_15_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_17_debug_inst = stq_uop_15_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_16_debug_inst = stq_uop_15_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_rvc; // @[lsu.scala:252:32] wire s_uop_17_is_rvc = stq_uop_15_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_rvc = stq_uop_15_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_15_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_17_debug_pc = stq_uop_15_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_16_debug_pc = stq_uop_15_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_0; // @[lsu.scala:252:32] wire s_uop_17_iq_type_0 = stq_uop_15_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_0 = stq_uop_15_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_1; // @[lsu.scala:252:32] wire s_uop_17_iq_type_1 = stq_uop_15_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_1 = stq_uop_15_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_2; // @[lsu.scala:252:32] wire s_uop_17_iq_type_2 = stq_uop_15_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_2 = stq_uop_15_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_3; // @[lsu.scala:252:32] wire s_uop_17_iq_type_3 = stq_uop_15_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_3 = stq_uop_15_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_0; // @[lsu.scala:252:32] wire s_uop_17_fu_code_0 = stq_uop_15_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_0 = stq_uop_15_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_1; // @[lsu.scala:252:32] wire s_uop_17_fu_code_1 = stq_uop_15_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_1 = stq_uop_15_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_2; // @[lsu.scala:252:32] wire s_uop_17_fu_code_2 = stq_uop_15_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_2 = stq_uop_15_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_3; // @[lsu.scala:252:32] wire s_uop_17_fu_code_3 = stq_uop_15_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_3 = stq_uop_15_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_4; // @[lsu.scala:252:32] wire s_uop_17_fu_code_4 = stq_uop_15_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_4 = stq_uop_15_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_5; // @[lsu.scala:252:32] wire s_uop_17_fu_code_5 = stq_uop_15_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_5 = stq_uop_15_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_6; // @[lsu.scala:252:32] wire s_uop_17_fu_code_6 = stq_uop_15_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_6 = stq_uop_15_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_7; // @[lsu.scala:252:32] wire s_uop_17_fu_code_7 = stq_uop_15_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_7 = stq_uop_15_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_8; // @[lsu.scala:252:32] wire s_uop_17_fu_code_8 = stq_uop_15_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_8 = stq_uop_15_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_9; // @[lsu.scala:252:32] wire s_uop_17_fu_code_9 = stq_uop_15_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_9 = stq_uop_15_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_issued; // @[lsu.scala:252:32] wire s_uop_17_iw_issued = stq_uop_15_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_issued = stq_uop_15_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_17_iw_issued_partial_agen = stq_uop_15_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_issued_partial_agen = stq_uop_15_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_17_iw_issued_partial_dgen = stq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_issued_partial_dgen = stq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_17_iw_p1_speculative_child = stq_uop_15_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_iw_p1_speculative_child = stq_uop_15_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [1:0] s_uop_17_iw_p2_speculative_child = stq_uop_15_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_iw_p2_speculative_child = stq_uop_15_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_17_iw_p1_bypass_hint = stq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_p1_bypass_hint = stq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_17_iw_p2_bypass_hint = stq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_p2_bypass_hint = stq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_17_iw_p3_bypass_hint = stq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_p3_bypass_hint = stq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_dis_col_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_17_dis_col_sel = stq_uop_15_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_dis_col_sel = stq_uop_15_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [11:0] stq_uop_15_br_mask; // @[lsu.scala:252:32] wire [11:0] s_uop_17_br_mask = stq_uop_15_br_mask; // @[lsu.scala:252:32, :1324:37] wire [11:0] uop_16_br_mask = stq_uop_15_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_15_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_17_br_tag = stq_uop_15_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_16_br_tag = stq_uop_15_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_15_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_17_br_type = stq_uop_15_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_16_br_type = stq_uop_15_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_sfb; // @[lsu.scala:252:32] wire s_uop_17_is_sfb = stq_uop_15_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_sfb = stq_uop_15_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_fence; // @[lsu.scala:252:32] wire s_uop_17_is_fence = stq_uop_15_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_fence = stq_uop_15_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_fencei; // @[lsu.scala:252:32] wire s_uop_17_is_fencei = stq_uop_15_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_fencei = stq_uop_15_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_sfence; // @[lsu.scala:252:32] wire s_uop_17_is_sfence = stq_uop_15_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_sfence = stq_uop_15_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_amo; // @[lsu.scala:252:32] wire s_uop_17_is_amo = stq_uop_15_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_amo = stq_uop_15_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_eret; // @[lsu.scala:252:32] wire s_uop_17_is_eret = stq_uop_15_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_eret = stq_uop_15_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_17_is_sys_pc2epc = stq_uop_15_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_sys_pc2epc = stq_uop_15_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_rocc; // @[lsu.scala:252:32] wire s_uop_17_is_rocc = stq_uop_15_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_rocc = stq_uop_15_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_mov; // @[lsu.scala:252:32] wire s_uop_17_is_mov = stq_uop_15_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_mov = stq_uop_15_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_17_ftq_idx = stq_uop_15_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_ftq_idx = stq_uop_15_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_edge_inst; // @[lsu.scala:252:32] wire s_uop_17_edge_inst = stq_uop_15_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_16_edge_inst = stq_uop_15_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_17_pc_lob = stq_uop_15_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_pc_lob = stq_uop_15_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_taken; // @[lsu.scala:252:32] wire s_uop_17_taken = stq_uop_15_taken; // @[lsu.scala:252:32, :1324:37] wire uop_16_taken = stq_uop_15_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_imm_rename; // @[lsu.scala:252:32] wire s_uop_17_imm_rename = stq_uop_15_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_16_imm_rename = stq_uop_15_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_17_imm_sel = stq_uop_15_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_imm_sel = stq_uop_15_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_17_pimm = stq_uop_15_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_pimm = stq_uop_15_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_15_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_17_imm_packed = stq_uop_15_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_16_imm_packed = stq_uop_15_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_17_op1_sel = stq_uop_15_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_op1_sel = stq_uop_15_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_17_op2_sel = stq_uop_15_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_op2_sel = stq_uop_15_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ldst = stq_uop_15_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ldst = stq_uop_15_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_wen = stq_uop_15_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_wen = stq_uop_15_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ren1 = stq_uop_15_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ren1 = stq_uop_15_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ren2 = stq_uop_15_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ren2 = stq_uop_15_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ren3 = stq_uop_15_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ren3 = stq_uop_15_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_swap12 = stq_uop_15_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_swap12 = stq_uop_15_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_swap23 = stq_uop_15_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_swap23 = stq_uop_15_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_17_fp_ctrl_typeTagIn = stq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_fp_ctrl_typeTagIn = stq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_17_fp_ctrl_typeTagOut = stq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_fp_ctrl_typeTagOut = stq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_fromint = stq_uop_15_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_fromint = stq_uop_15_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_toint = stq_uop_15_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_toint = stq_uop_15_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_fastpipe = stq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_fastpipe = stq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_fma = stq_uop_15_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_fma = stq_uop_15_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_div = stq_uop_15_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_div = stq_uop_15_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_sqrt = stq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_sqrt = stq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_wflags = stq_uop_15_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_wflags = stq_uop_15_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_vec = stq_uop_15_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_vec = stq_uop_15_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_rob_idx; // @[lsu.scala:252:32] wire [5:0] s_uop_17_rob_idx = stq_uop_15_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_rob_idx = stq_uop_15_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_15_ldq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_17_ldq_idx = stq_uop_15_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_16_ldq_idx = stq_uop_15_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_15_stq_idx; // @[lsu.scala:252:32] wire [3:0] s_uop_17_stq_idx = stq_uop_15_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_16_stq_idx = stq_uop_15_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_17_rxq_idx = stq_uop_15_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_rxq_idx = stq_uop_15_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_17_pdst = stq_uop_15_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_pdst = stq_uop_15_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_17_prs1 = stq_uop_15_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_prs1 = stq_uop_15_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_17_prs2 = stq_uop_15_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_prs2 = stq_uop_15_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_17_prs3 = stq_uop_15_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_prs3 = stq_uop_15_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_17_ppred = stq_uop_15_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_ppred = stq_uop_15_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_prs1_busy; // @[lsu.scala:252:32] wire s_uop_17_prs1_busy = stq_uop_15_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_prs1_busy = stq_uop_15_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_prs2_busy; // @[lsu.scala:252:32] wire s_uop_17_prs2_busy = stq_uop_15_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_prs2_busy = stq_uop_15_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_prs3_busy; // @[lsu.scala:252:32] wire s_uop_17_prs3_busy = stq_uop_15_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_prs3_busy = stq_uop_15_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_ppred_busy; // @[lsu.scala:252:32] wire s_uop_17_ppred_busy = stq_uop_15_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_ppred_busy = stq_uop_15_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_17_stale_pdst = stq_uop_15_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_stale_pdst = stq_uop_15_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_exception; // @[lsu.scala:252:32] wire s_uop_17_exception = stq_uop_15_exception; // @[lsu.scala:252:32, :1324:37] wire uop_16_exception = stq_uop_15_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_15_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_17_exc_cause = stq_uop_15_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_16_exc_cause = stq_uop_15_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_17_mem_cmd = stq_uop_15_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_mem_cmd = stq_uop_15_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_17_mem_size = stq_uop_15_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_mem_size = stq_uop_15_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_mem_signed; // @[lsu.scala:252:32] wire s_uop_17_mem_signed = stq_uop_15_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_16_mem_signed = stq_uop_15_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_uses_ldq; // @[lsu.scala:252:32] wire s_uop_17_uses_ldq = stq_uop_15_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_16_uses_ldq = stq_uop_15_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_uses_stq; // @[lsu.scala:252:32] wire s_uop_17_uses_stq = stq_uop_15_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_16_uses_stq = stq_uop_15_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_unique; // @[lsu.scala:252:32] wire s_uop_17_is_unique = stq_uop_15_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_unique = stq_uop_15_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_17_flush_on_commit = stq_uop_15_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_16_flush_on_commit = stq_uop_15_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_17_csr_cmd = stq_uop_15_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_csr_cmd = stq_uop_15_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_17_ldst_is_rs1 = stq_uop_15_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_16_ldst_is_rs1 = stq_uop_15_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_17_ldst = stq_uop_15_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_ldst = stq_uop_15_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_17_lrs1 = stq_uop_15_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_lrs1 = stq_uop_15_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_17_lrs2 = stq_uop_15_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_lrs2 = stq_uop_15_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_17_lrs3 = stq_uop_15_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_lrs3 = stq_uop_15_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_17_dst_rtype = stq_uop_15_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_dst_rtype = stq_uop_15_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_17_lrs1_rtype = stq_uop_15_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_lrs1_rtype = stq_uop_15_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_17_lrs2_rtype = stq_uop_15_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_lrs2_rtype = stq_uop_15_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_frs3_en; // @[lsu.scala:252:32] wire s_uop_17_frs3_en = stq_uop_15_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_16_frs3_en = stq_uop_15_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fcn_dw; // @[lsu.scala:252:32] wire s_uop_17_fcn_dw = stq_uop_15_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_16_fcn_dw = stq_uop_15_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_17_fcn_op = stq_uop_15_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_fcn_op = stq_uop_15_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_val; // @[lsu.scala:252:32] wire s_uop_17_fp_val = stq_uop_15_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_val = stq_uop_15_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_17_fp_rm = stq_uop_15_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_fp_rm = stq_uop_15_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_17_fp_typ = stq_uop_15_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_fp_typ = stq_uop_15_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_17_xcpt_pf_if = stq_uop_15_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_xcpt_pf_if = stq_uop_15_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_17_xcpt_ae_if = stq_uop_15_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_xcpt_ae_if = stq_uop_15_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_17_xcpt_ma_if = stq_uop_15_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_xcpt_ma_if = stq_uop_15_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_17_bp_debug_if = stq_uop_15_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_bp_debug_if = stq_uop_15_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_17_bp_xcpt_if = stq_uop_15_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_bp_xcpt_if = stq_uop_15_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_17_debug_fsrc = stq_uop_15_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_debug_fsrc = stq_uop_15_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_17_debug_tsrc = stq_uop_15_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_debug_tsrc = stq_uop_15_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg stq_addr_0_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_0_bits; // @[lsu.scala:253:32] reg stq_addr_1_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_1_bits; // @[lsu.scala:253:32] reg stq_addr_2_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_2_bits; // @[lsu.scala:253:32] reg stq_addr_3_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_3_bits; // @[lsu.scala:253:32] reg stq_addr_4_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_4_bits; // @[lsu.scala:253:32] reg stq_addr_5_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_5_bits; // @[lsu.scala:253:32] reg stq_addr_6_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_6_bits; // @[lsu.scala:253:32] reg stq_addr_7_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_7_bits; // @[lsu.scala:253:32] reg stq_addr_8_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_8_bits; // @[lsu.scala:253:32] reg stq_addr_9_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_9_bits; // @[lsu.scala:253:32] reg stq_addr_10_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_10_bits; // @[lsu.scala:253:32] reg stq_addr_11_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_11_bits; // @[lsu.scala:253:32] reg stq_addr_12_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_12_bits; // @[lsu.scala:253:32] reg stq_addr_13_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_13_bits; // @[lsu.scala:253:32] reg stq_addr_14_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_14_bits; // @[lsu.scala:253:32] reg stq_addr_15_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_15_bits; // @[lsu.scala:253:32] reg stq_addr_is_virtual_0; // @[lsu.scala:254:32] reg stq_addr_is_virtual_1; // @[lsu.scala:254:32] reg stq_addr_is_virtual_2; // @[lsu.scala:254:32] reg stq_addr_is_virtual_3; // @[lsu.scala:254:32] reg stq_addr_is_virtual_4; // @[lsu.scala:254:32] reg stq_addr_is_virtual_5; // @[lsu.scala:254:32] reg stq_addr_is_virtual_6; // @[lsu.scala:254:32] reg stq_addr_is_virtual_7; // @[lsu.scala:254:32] reg stq_addr_is_virtual_8; // @[lsu.scala:254:32] reg stq_addr_is_virtual_9; // @[lsu.scala:254:32] reg stq_addr_is_virtual_10; // @[lsu.scala:254:32] reg stq_addr_is_virtual_11; // @[lsu.scala:254:32] reg stq_addr_is_virtual_12; // @[lsu.scala:254:32] reg stq_addr_is_virtual_13; // @[lsu.scala:254:32] reg stq_addr_is_virtual_14; // @[lsu.scala:254:32] reg stq_addr_is_virtual_15; // @[lsu.scala:254:32] reg stq_data_0_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_0_bits; // @[lsu.scala:255:32] reg stq_data_1_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_1_bits; // @[lsu.scala:255:32] reg stq_data_2_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_2_bits; // @[lsu.scala:255:32] reg stq_data_3_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_3_bits; // @[lsu.scala:255:32] reg stq_data_4_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_4_bits; // @[lsu.scala:255:32] reg stq_data_5_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_5_bits; // @[lsu.scala:255:32] reg stq_data_6_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_6_bits; // @[lsu.scala:255:32] reg stq_data_7_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_7_bits; // @[lsu.scala:255:32] reg stq_data_8_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_8_bits; // @[lsu.scala:255:32] reg stq_data_9_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_9_bits; // @[lsu.scala:255:32] reg stq_data_10_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_10_bits; // @[lsu.scala:255:32] reg stq_data_11_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_11_bits; // @[lsu.scala:255:32] reg stq_data_12_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_12_bits; // @[lsu.scala:255:32] reg stq_data_13_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_13_bits; // @[lsu.scala:255:32] reg stq_data_14_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_14_bits; // @[lsu.scala:255:32] reg stq_data_15_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_15_bits; // @[lsu.scala:255:32] reg stq_committed_0; // @[lsu.scala:256:32] reg stq_committed_1; // @[lsu.scala:256:32] reg stq_committed_2; // @[lsu.scala:256:32] reg stq_committed_3; // @[lsu.scala:256:32] reg stq_committed_4; // @[lsu.scala:256:32] reg stq_committed_5; // @[lsu.scala:256:32] reg stq_committed_6; // @[lsu.scala:256:32] reg stq_committed_7; // @[lsu.scala:256:32] reg stq_committed_8; // @[lsu.scala:256:32] reg stq_committed_9; // @[lsu.scala:256:32] reg stq_committed_10; // @[lsu.scala:256:32] reg stq_committed_11; // @[lsu.scala:256:32] reg stq_committed_12; // @[lsu.scala:256:32] reg stq_committed_13; // @[lsu.scala:256:32] reg stq_committed_14; // @[lsu.scala:256:32] reg stq_committed_15; // @[lsu.scala:256:32] reg stq_succeeded_0; // @[lsu.scala:257:32] reg stq_succeeded_1; // @[lsu.scala:257:32] reg stq_succeeded_2; // @[lsu.scala:257:32] reg stq_succeeded_3; // @[lsu.scala:257:32] reg stq_succeeded_4; // @[lsu.scala:257:32] reg stq_succeeded_5; // @[lsu.scala:257:32] reg stq_succeeded_6; // @[lsu.scala:257:32] reg stq_succeeded_7; // @[lsu.scala:257:32] reg stq_succeeded_8; // @[lsu.scala:257:32] reg stq_succeeded_9; // @[lsu.scala:257:32] reg stq_succeeded_10; // @[lsu.scala:257:32] reg stq_succeeded_11; // @[lsu.scala:257:32] reg stq_succeeded_12; // @[lsu.scala:257:32] reg stq_succeeded_13; // @[lsu.scala:257:32] reg stq_succeeded_14; // @[lsu.scala:257:32] reg stq_succeeded_15; // @[lsu.scala:257:32] reg stq_can_execute_0; // @[lsu.scala:258:32] reg stq_can_execute_1; // @[lsu.scala:258:32] reg stq_can_execute_2; // @[lsu.scala:258:32] reg stq_can_execute_3; // @[lsu.scala:258:32] reg stq_can_execute_4; // @[lsu.scala:258:32] reg stq_can_execute_5; // @[lsu.scala:258:32] reg stq_can_execute_6; // @[lsu.scala:258:32] reg stq_can_execute_7; // @[lsu.scala:258:32] reg stq_can_execute_8; // @[lsu.scala:258:32] reg stq_can_execute_9; // @[lsu.scala:258:32] reg stq_can_execute_10; // @[lsu.scala:258:32] reg stq_can_execute_11; // @[lsu.scala:258:32] reg stq_can_execute_12; // @[lsu.scala:258:32] reg stq_can_execute_13; // @[lsu.scala:258:32] reg stq_can_execute_14; // @[lsu.scala:258:32] reg stq_can_execute_15; // @[lsu.scala:258:32] reg stq_cleared_0; // @[lsu.scala:259:32] reg stq_cleared_1; // @[lsu.scala:259:32] reg stq_cleared_2; // @[lsu.scala:259:32] reg stq_cleared_3; // @[lsu.scala:259:32] reg stq_cleared_4; // @[lsu.scala:259:32] reg stq_cleared_5; // @[lsu.scala:259:32] reg stq_cleared_6; // @[lsu.scala:259:32] reg stq_cleared_7; // @[lsu.scala:259:32] reg stq_cleared_8; // @[lsu.scala:259:32] reg stq_cleared_9; // @[lsu.scala:259:32] reg stq_cleared_10; // @[lsu.scala:259:32] reg stq_cleared_11; // @[lsu.scala:259:32] reg stq_cleared_12; // @[lsu.scala:259:32] reg stq_cleared_13; // @[lsu.scala:259:32] reg stq_cleared_14; // @[lsu.scala:259:32] reg stq_cleared_15; // @[lsu.scala:259:32] reg [63:0] stq_debug_wb_data_0; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_1; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_2; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_3; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_4; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_5; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_6; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_7; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_8; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_9; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_10; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_11; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_12; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_13; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_14; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_15; // @[lsu.scala:260:32] reg [3:0] ldq_head; // @[lsu.scala:278:29] reg [3:0] ldq_tail; // @[lsu.scala:279:29] assign io_core_dis_ldq_idx_0_0 = ldq_tail; // @[lsu.scala:211:7, :279:29] reg [3:0] stq_head; // @[lsu.scala:280:29] reg [3:0] stq_tail; // @[lsu.scala:281:29] assign io_core_dis_stq_idx_0_0 = stq_tail; // @[lsu.scala:211:7, :281:29] reg [3:0] stq_commit_head; // @[lsu.scala:282:29] reg [3:0] stq_execute_head; // @[lsu.scala:283:29] reg [2:0] hella_state; // @[lsu.scala:301:38] reg [39:0] hella_req_addr; // @[lsu.scala:302:34] assign io_hellacache_resp_bits_addr_0 = hella_req_addr; // @[lsu.scala:211:7, :302:34] reg hella_req_dv; // @[lsu.scala:302:34] reg [63:0] hella_data_data; // @[lsu.scala:303:34] wire [63:0] _dmem_req_0_bits_data_T_42 = hella_data_data; // @[AMOALU.scala:29:13] reg [7:0] hella_data_mask; // @[lsu.scala:303:34] reg [31:0] hella_paddr; // @[lsu.scala:304:34] reg hella_xcpt_ma_ld; // @[lsu.scala:305:34] reg hella_xcpt_ma_st; // @[lsu.scala:305:34] reg hella_xcpt_pf_ld; // @[lsu.scala:305:34] reg hella_xcpt_pf_st; // @[lsu.scala:305:34] reg hella_xcpt_gf_ld; // @[lsu.scala:305:34] reg hella_xcpt_gf_st; // @[lsu.scala:305:34] reg hella_xcpt_ae_ld; // @[lsu.scala:305:34] reg hella_xcpt_ae_st; // @[lsu.scala:305:34] assign _io_core_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] assign io_core_perf_tlbMiss_0 = _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire clear_store; // @[lsu.scala:318:33] wire ldq_will_succeed_0; // @[lsu.scala:325:44] wire ldq_will_succeed_1; // @[lsu.scala:325:44] wire ldq_will_succeed_2; // @[lsu.scala:325:44] wire ldq_will_succeed_3; // @[lsu.scala:325:44] wire ldq_will_succeed_4; // @[lsu.scala:325:44] wire ldq_will_succeed_5; // @[lsu.scala:325:44] wire ldq_will_succeed_6; // @[lsu.scala:325:44] wire ldq_will_succeed_7; // @[lsu.scala:325:44] wire ldq_will_succeed_8; // @[lsu.scala:325:44] wire ldq_will_succeed_9; // @[lsu.scala:325:44] wire ldq_will_succeed_10; // @[lsu.scala:325:44] wire ldq_will_succeed_11; // @[lsu.scala:325:44] wire ldq_will_succeed_12; // @[lsu.scala:325:44] wire ldq_will_succeed_13; // @[lsu.scala:325:44] wire ldq_will_succeed_14; // @[lsu.scala:325:44] wire ldq_will_succeed_15; // @[lsu.scala:325:44] wire [15:0] _GEN = 16'h1 << stq_head; // @[lsu.scala:280:29, :340:56] wire [15:0] _ldq_st_dep_mask_0_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_0_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_1_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_1_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_2_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_2_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_3_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_3_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_4_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_4_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_5_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_5_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_6_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_6_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_7_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_7_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_8_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_8_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_9_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_9_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_10_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_10_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_11_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_11_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_12_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_12_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_13_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_13_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_14_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_14_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _ldq_st_dep_mask_15_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_15_T = _GEN; // @[lsu.scala:340:56] wire [15:0] _next_live_store_mask_T; // @[lsu.scala:355:71] assign _next_live_store_mask_T = _GEN; // @[lsu.scala:340:56, :355:71] wire [15:0] _ldq_st_dep_mask_0_T_1 = ~_ldq_st_dep_mask_0_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_0_T_2 = ldq_st_dep_mask_0 & _ldq_st_dep_mask_0_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_1_T_1 = ~_ldq_st_dep_mask_1_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_1_T_2 = ldq_st_dep_mask_1 & _ldq_st_dep_mask_1_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_2_T_1 = ~_ldq_st_dep_mask_2_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_2_T_2 = ldq_st_dep_mask_2 & _ldq_st_dep_mask_2_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_3_T_1 = ~_ldq_st_dep_mask_3_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_3_T_2 = ldq_st_dep_mask_3 & _ldq_st_dep_mask_3_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_4_T_1 = ~_ldq_st_dep_mask_4_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_4_T_2 = ldq_st_dep_mask_4 & _ldq_st_dep_mask_4_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_5_T_1 = ~_ldq_st_dep_mask_5_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_5_T_2 = ldq_st_dep_mask_5 & _ldq_st_dep_mask_5_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_6_T_1 = ~_ldq_st_dep_mask_6_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_6_T_2 = ldq_st_dep_mask_6 & _ldq_st_dep_mask_6_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_7_T_1 = ~_ldq_st_dep_mask_7_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_7_T_2 = ldq_st_dep_mask_7 & _ldq_st_dep_mask_7_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_8_T_1 = ~_ldq_st_dep_mask_8_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_8_T_2 = ldq_st_dep_mask_8 & _ldq_st_dep_mask_8_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_9_T_1 = ~_ldq_st_dep_mask_9_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_9_T_2 = ldq_st_dep_mask_9 & _ldq_st_dep_mask_9_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_10_T_1 = ~_ldq_st_dep_mask_10_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_10_T_2 = ldq_st_dep_mask_10 & _ldq_st_dep_mask_10_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_11_T_1 = ~_ldq_st_dep_mask_11_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_11_T_2 = ldq_st_dep_mask_11 & _ldq_st_dep_mask_11_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_12_T_1 = ~_ldq_st_dep_mask_12_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_12_T_2 = ldq_st_dep_mask_12 & _ldq_st_dep_mask_12_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_13_T_1 = ~_ldq_st_dep_mask_13_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_13_T_2 = ldq_st_dep_mask_13 & _ldq_st_dep_mask_13_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_14_T_1 = ~_ldq_st_dep_mask_14_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_14_T_2 = ldq_st_dep_mask_14 & _ldq_st_dep_mask_14_T_1; // @[lsu.scala:227:36, :340:{48,50}] wire [15:0] _ldq_st_dep_mask_15_T_1 = ~_ldq_st_dep_mask_15_T; // @[lsu.scala:340:{50,56}] wire [15:0] _ldq_st_dep_mask_15_T_2 = ldq_st_dep_mask_15 & _ldq_st_dep_mask_15_T_1; // @[lsu.scala:227:36, :340:{48,50}] reg dis_ldq_oh_0; // @[lsu.scala:348:23] reg dis_ldq_oh_1; // @[lsu.scala:348:23] reg dis_ldq_oh_2; // @[lsu.scala:348:23] reg dis_ldq_oh_3; // @[lsu.scala:348:23] reg dis_ldq_oh_4; // @[lsu.scala:348:23] reg dis_ldq_oh_5; // @[lsu.scala:348:23] reg dis_ldq_oh_6; // @[lsu.scala:348:23] reg dis_ldq_oh_7; // @[lsu.scala:348:23] reg dis_ldq_oh_8; // @[lsu.scala:348:23] reg dis_ldq_oh_9; // @[lsu.scala:348:23] reg dis_ldq_oh_10; // @[lsu.scala:348:23] reg dis_ldq_oh_11; // @[lsu.scala:348:23] reg dis_ldq_oh_12; // @[lsu.scala:348:23] reg dis_ldq_oh_13; // @[lsu.scala:348:23] reg dis_ldq_oh_14; // @[lsu.scala:348:23] reg dis_ldq_oh_15; // @[lsu.scala:348:23] reg dis_stq_oh_0; // @[lsu.scala:349:23] reg dis_stq_oh_1; // @[lsu.scala:349:23] reg dis_stq_oh_2; // @[lsu.scala:349:23] reg dis_stq_oh_3; // @[lsu.scala:349:23] reg dis_stq_oh_4; // @[lsu.scala:349:23] reg dis_stq_oh_5; // @[lsu.scala:349:23] reg dis_stq_oh_6; // @[lsu.scala:349:23] reg dis_stq_oh_7; // @[lsu.scala:349:23] reg dis_stq_oh_8; // @[lsu.scala:349:23] reg dis_stq_oh_9; // @[lsu.scala:349:23] reg dis_stq_oh_10; // @[lsu.scala:349:23] reg dis_stq_oh_11; // @[lsu.scala:349:23] reg dis_stq_oh_12; // @[lsu.scala:349:23] reg dis_stq_oh_13; // @[lsu.scala:349:23] reg dis_stq_oh_14; // @[lsu.scala:349:23] reg dis_stq_oh_15; // @[lsu.scala:349:23] reg dis_uops_0_valid; // @[lsu.scala:352:23] reg [31:0] dis_uops_0_bits_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_inst = dis_uops_0_bits_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_inst = dis_uops_0_bits_inst; // @[util.scala:104:23] reg [31:0] dis_uops_0_bits_debug_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_debug_inst = dis_uops_0_bits_debug_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_debug_inst = dis_uops_0_bits_debug_inst; // @[util.scala:104:23] reg dis_uops_0_bits_is_rvc; // @[lsu.scala:352:23] wire ldq_uop_out_is_rvc = dis_uops_0_bits_is_rvc; // @[util.scala:104:23] wire stq_uop_out_is_rvc = dis_uops_0_bits_is_rvc; // @[util.scala:104:23] reg [39:0] dis_uops_0_bits_debug_pc; // @[lsu.scala:352:23] wire [39:0] ldq_uop_out_debug_pc = dis_uops_0_bits_debug_pc; // @[util.scala:104:23] wire [39:0] stq_uop_out_debug_pc = dis_uops_0_bits_debug_pc; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_0; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_0 = dis_uops_0_bits_iq_type_0; // @[util.scala:104:23] wire stq_uop_out_iq_type_0 = dis_uops_0_bits_iq_type_0; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_1; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_1 = dis_uops_0_bits_iq_type_1; // @[util.scala:104:23] wire stq_uop_out_iq_type_1 = dis_uops_0_bits_iq_type_1; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_2; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_2 = dis_uops_0_bits_iq_type_2; // @[util.scala:104:23] wire stq_uop_out_iq_type_2 = dis_uops_0_bits_iq_type_2; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_3; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_3 = dis_uops_0_bits_iq_type_3; // @[util.scala:104:23] wire stq_uop_out_iq_type_3 = dis_uops_0_bits_iq_type_3; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_0; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_0 = dis_uops_0_bits_fu_code_0; // @[util.scala:104:23] wire stq_uop_out_fu_code_0 = dis_uops_0_bits_fu_code_0; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_1; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_1 = dis_uops_0_bits_fu_code_1; // @[util.scala:104:23] wire stq_uop_out_fu_code_1 = dis_uops_0_bits_fu_code_1; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_2; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_2 = dis_uops_0_bits_fu_code_2; // @[util.scala:104:23] wire stq_uop_out_fu_code_2 = dis_uops_0_bits_fu_code_2; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_3; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_3 = dis_uops_0_bits_fu_code_3; // @[util.scala:104:23] wire stq_uop_out_fu_code_3 = dis_uops_0_bits_fu_code_3; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_4; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_4 = dis_uops_0_bits_fu_code_4; // @[util.scala:104:23] wire stq_uop_out_fu_code_4 = dis_uops_0_bits_fu_code_4; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_5; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_5 = dis_uops_0_bits_fu_code_5; // @[util.scala:104:23] wire stq_uop_out_fu_code_5 = dis_uops_0_bits_fu_code_5; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_6; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_6 = dis_uops_0_bits_fu_code_6; // @[util.scala:104:23] wire stq_uop_out_fu_code_6 = dis_uops_0_bits_fu_code_6; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_7; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_7 = dis_uops_0_bits_fu_code_7; // @[util.scala:104:23] wire stq_uop_out_fu_code_7 = dis_uops_0_bits_fu_code_7; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_8; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_8 = dis_uops_0_bits_fu_code_8; // @[util.scala:104:23] wire stq_uop_out_fu_code_8 = dis_uops_0_bits_fu_code_8; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_9; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_9 = dis_uops_0_bits_fu_code_9; // @[util.scala:104:23] wire stq_uop_out_fu_code_9 = dis_uops_0_bits_fu_code_9; // @[util.scala:104:23] reg dis_uops_0_bits_iw_issued; // @[lsu.scala:352:23] wire ldq_uop_out_iw_issued = dis_uops_0_bits_iw_issued; // @[util.scala:104:23] wire stq_uop_out_iw_issued = dis_uops_0_bits_iw_issued; // @[util.scala:104:23] reg dis_uops_0_bits_iw_issued_partial_agen; // @[lsu.scala:352:23] wire ldq_uop_out_iw_issued_partial_agen = dis_uops_0_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire stq_uop_out_iw_issued_partial_agen = dis_uops_0_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg dis_uops_0_bits_iw_issued_partial_dgen; // @[lsu.scala:352:23] wire ldq_uop_out_iw_issued_partial_dgen = dis_uops_0_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire stq_uop_out_iw_issued_partial_dgen = dis_uops_0_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_iw_p1_speculative_child; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_iw_p1_speculative_child = dis_uops_0_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] stq_uop_out_iw_p1_speculative_child = dis_uops_0_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_iw_p2_speculative_child; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_iw_p2_speculative_child = dis_uops_0_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire [1:0] stq_uop_out_iw_p2_speculative_child = dis_uops_0_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg dis_uops_0_bits_iw_p1_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_iw_p1_bypass_hint = dis_uops_0_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_iw_p1_bypass_hint = dis_uops_0_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg dis_uops_0_bits_iw_p2_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_iw_p2_bypass_hint = dis_uops_0_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_iw_p2_bypass_hint = dis_uops_0_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg dis_uops_0_bits_iw_p3_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_iw_p3_bypass_hint = dis_uops_0_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_iw_p3_bypass_hint = dis_uops_0_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_dis_col_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_dis_col_sel = dis_uops_0_bits_dis_col_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_dis_col_sel = dis_uops_0_bits_dis_col_sel; // @[util.scala:104:23] reg [11:0] dis_uops_0_bits_br_mask; // @[lsu.scala:352:23] reg [3:0] dis_uops_0_bits_br_tag; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_br_tag = dis_uops_0_bits_br_tag; // @[util.scala:104:23] wire [3:0] stq_uop_out_br_tag = dis_uops_0_bits_br_tag; // @[util.scala:104:23] reg [3:0] dis_uops_0_bits_br_type; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_br_type = dis_uops_0_bits_br_type; // @[util.scala:104:23] wire [3:0] stq_uop_out_br_type = dis_uops_0_bits_br_type; // @[util.scala:104:23] reg dis_uops_0_bits_is_sfb; // @[lsu.scala:352:23] wire ldq_uop_out_is_sfb = dis_uops_0_bits_is_sfb; // @[util.scala:104:23] wire stq_uop_out_is_sfb = dis_uops_0_bits_is_sfb; // @[util.scala:104:23] reg dis_uops_0_bits_is_fence; // @[lsu.scala:352:23] wire ldq_uop_out_is_fence = dis_uops_0_bits_is_fence; // @[util.scala:104:23] wire stq_uop_out_is_fence = dis_uops_0_bits_is_fence; // @[util.scala:104:23] reg dis_uops_0_bits_is_fencei; // @[lsu.scala:352:23] wire ldq_uop_out_is_fencei = dis_uops_0_bits_is_fencei; // @[util.scala:104:23] wire stq_uop_out_is_fencei = dis_uops_0_bits_is_fencei; // @[util.scala:104:23] reg dis_uops_0_bits_is_sfence; // @[lsu.scala:352:23] wire ldq_uop_out_is_sfence = dis_uops_0_bits_is_sfence; // @[util.scala:104:23] wire stq_uop_out_is_sfence = dis_uops_0_bits_is_sfence; // @[util.scala:104:23] reg dis_uops_0_bits_is_amo; // @[lsu.scala:352:23] wire ldq_uop_out_is_amo = dis_uops_0_bits_is_amo; // @[util.scala:104:23] wire stq_uop_out_is_amo = dis_uops_0_bits_is_amo; // @[util.scala:104:23] reg dis_uops_0_bits_is_eret; // @[lsu.scala:352:23] wire ldq_uop_out_is_eret = dis_uops_0_bits_is_eret; // @[util.scala:104:23] wire stq_uop_out_is_eret = dis_uops_0_bits_is_eret; // @[util.scala:104:23] reg dis_uops_0_bits_is_sys_pc2epc; // @[lsu.scala:352:23] wire ldq_uop_out_is_sys_pc2epc = dis_uops_0_bits_is_sys_pc2epc; // @[util.scala:104:23] wire stq_uop_out_is_sys_pc2epc = dis_uops_0_bits_is_sys_pc2epc; // @[util.scala:104:23] reg dis_uops_0_bits_is_rocc; // @[lsu.scala:352:23] wire ldq_uop_out_is_rocc = dis_uops_0_bits_is_rocc; // @[util.scala:104:23] wire stq_uop_out_is_rocc = dis_uops_0_bits_is_rocc; // @[util.scala:104:23] reg dis_uops_0_bits_is_mov; // @[lsu.scala:352:23] wire ldq_uop_out_is_mov = dis_uops_0_bits_is_mov; // @[util.scala:104:23] wire stq_uop_out_is_mov = dis_uops_0_bits_is_mov; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_ftq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_ftq_idx = dis_uops_0_bits_ftq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_ftq_idx = dis_uops_0_bits_ftq_idx; // @[util.scala:104:23] reg dis_uops_0_bits_edge_inst; // @[lsu.scala:352:23] wire ldq_uop_out_edge_inst = dis_uops_0_bits_edge_inst; // @[util.scala:104:23] wire stq_uop_out_edge_inst = dis_uops_0_bits_edge_inst; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_pc_lob; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_pc_lob = dis_uops_0_bits_pc_lob; // @[util.scala:104:23] wire [5:0] stq_uop_out_pc_lob = dis_uops_0_bits_pc_lob; // @[util.scala:104:23] reg dis_uops_0_bits_taken; // @[lsu.scala:352:23] wire ldq_uop_out_taken = dis_uops_0_bits_taken; // @[util.scala:104:23] wire stq_uop_out_taken = dis_uops_0_bits_taken; // @[util.scala:104:23] reg dis_uops_0_bits_imm_rename; // @[lsu.scala:352:23] wire ldq_uop_out_imm_rename = dis_uops_0_bits_imm_rename; // @[util.scala:104:23] wire stq_uop_out_imm_rename = dis_uops_0_bits_imm_rename; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_imm_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_imm_sel = dis_uops_0_bits_imm_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_imm_sel = dis_uops_0_bits_imm_sel; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_pimm; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_pimm = dis_uops_0_bits_pimm; // @[util.scala:104:23] wire [4:0] stq_uop_out_pimm = dis_uops_0_bits_pimm; // @[util.scala:104:23] reg [19:0] dis_uops_0_bits_imm_packed; // @[lsu.scala:352:23] wire [19:0] ldq_uop_out_imm_packed = dis_uops_0_bits_imm_packed; // @[util.scala:104:23] wire [19:0] stq_uop_out_imm_packed = dis_uops_0_bits_imm_packed; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_op1_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_op1_sel = dis_uops_0_bits_op1_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_op1_sel = dis_uops_0_bits_op1_sel; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_op2_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_op2_sel = dis_uops_0_bits_op2_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_op2_sel = dis_uops_0_bits_op2_sel; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ldst; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ldst = dis_uops_0_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ldst = dis_uops_0_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_wen; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_wen = dis_uops_0_bits_fp_ctrl_wen; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_wen = dis_uops_0_bits_fp_ctrl_wen; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ren1; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ren1 = dis_uops_0_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ren1 = dis_uops_0_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ren2; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ren2 = dis_uops_0_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ren2 = dis_uops_0_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ren3; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ren3 = dis_uops_0_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ren3 = dis_uops_0_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_swap12; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_swap12 = dis_uops_0_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_swap12 = dis_uops_0_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_swap23; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_swap23 = dis_uops_0_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_swap23 = dis_uops_0_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_fp_ctrl_typeTagIn; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_fp_ctrl_typeTagIn = dis_uops_0_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] stq_uop_out_fp_ctrl_typeTagIn = dis_uops_0_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_fp_ctrl_typeTagOut; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_fp_ctrl_typeTagOut = dis_uops_0_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire [1:0] stq_uop_out_fp_ctrl_typeTagOut = dis_uops_0_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_fromint; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_fromint = dis_uops_0_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_fromint = dis_uops_0_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_toint; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_toint = dis_uops_0_bits_fp_ctrl_toint; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_toint = dis_uops_0_bits_fp_ctrl_toint; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_fastpipe; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_fastpipe = dis_uops_0_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_fastpipe = dis_uops_0_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_fma; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_fma = dis_uops_0_bits_fp_ctrl_fma; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_fma = dis_uops_0_bits_fp_ctrl_fma; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_div; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_div = dis_uops_0_bits_fp_ctrl_div; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_div = dis_uops_0_bits_fp_ctrl_div; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_sqrt; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_sqrt = dis_uops_0_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_sqrt = dis_uops_0_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_wflags; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_wflags = dis_uops_0_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_wflags = dis_uops_0_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_vec; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_vec = dis_uops_0_bits_fp_ctrl_vec; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_vec = dis_uops_0_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_rob_idx; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_rob_idx = dis_uops_0_bits_rob_idx; // @[util.scala:104:23] wire [5:0] stq_uop_out_rob_idx = dis_uops_0_bits_rob_idx; // @[util.scala:104:23] reg [3:0] dis_uops_0_bits_ldq_idx; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_ldq_idx = dis_uops_0_bits_ldq_idx; // @[util.scala:104:23] wire [3:0] stq_uop_out_ldq_idx = dis_uops_0_bits_ldq_idx; // @[util.scala:104:23] reg [3:0] dis_uops_0_bits_stq_idx; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_stq_idx = dis_uops_0_bits_stq_idx; // @[util.scala:104:23] wire [3:0] stq_uop_out_stq_idx = dis_uops_0_bits_stq_idx; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_rxq_idx; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_rxq_idx = dis_uops_0_bits_rxq_idx; // @[util.scala:104:23] wire [1:0] stq_uop_out_rxq_idx = dis_uops_0_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_pdst = dis_uops_0_bits_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_pdst = dis_uops_0_bits_pdst; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_prs1; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_prs1 = dis_uops_0_bits_prs1; // @[util.scala:104:23] wire [6:0] stq_uop_out_prs1 = dis_uops_0_bits_prs1; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_prs2; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_prs2 = dis_uops_0_bits_prs2; // @[util.scala:104:23] wire [6:0] stq_uop_out_prs2 = dis_uops_0_bits_prs2; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_prs3; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_prs3 = dis_uops_0_bits_prs3; // @[util.scala:104:23] wire [6:0] stq_uop_out_prs3 = dis_uops_0_bits_prs3; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_ppred; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_ppred = dis_uops_0_bits_ppred; // @[util.scala:104:23] wire [4:0] stq_uop_out_ppred = dis_uops_0_bits_ppred; // @[util.scala:104:23] reg dis_uops_0_bits_prs1_busy; // @[lsu.scala:352:23] wire ldq_uop_out_prs1_busy = dis_uops_0_bits_prs1_busy; // @[util.scala:104:23] wire stq_uop_out_prs1_busy = dis_uops_0_bits_prs1_busy; // @[util.scala:104:23] reg dis_uops_0_bits_prs2_busy; // @[lsu.scala:352:23] wire ldq_uop_out_prs2_busy = dis_uops_0_bits_prs2_busy; // @[util.scala:104:23] wire stq_uop_out_prs2_busy = dis_uops_0_bits_prs2_busy; // @[util.scala:104:23] reg dis_uops_0_bits_prs3_busy; // @[lsu.scala:352:23] wire ldq_uop_out_prs3_busy = dis_uops_0_bits_prs3_busy; // @[util.scala:104:23] wire stq_uop_out_prs3_busy = dis_uops_0_bits_prs3_busy; // @[util.scala:104:23] reg dis_uops_0_bits_ppred_busy; // @[lsu.scala:352:23] wire ldq_uop_out_ppred_busy = dis_uops_0_bits_ppred_busy; // @[util.scala:104:23] wire stq_uop_out_ppred_busy = dis_uops_0_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_stale_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_stale_pdst = dis_uops_0_bits_stale_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_stale_pdst = dis_uops_0_bits_stale_pdst; // @[util.scala:104:23] reg dis_uops_0_bits_exception; // @[lsu.scala:352:23] wire ldq_uop_out_exception = dis_uops_0_bits_exception; // @[util.scala:104:23] wire stq_uop_out_exception = dis_uops_0_bits_exception; // @[util.scala:104:23] reg [63:0] dis_uops_0_bits_exc_cause; // @[lsu.scala:352:23] wire [63:0] ldq_uop_out_exc_cause = dis_uops_0_bits_exc_cause; // @[util.scala:104:23] wire [63:0] stq_uop_out_exc_cause = dis_uops_0_bits_exc_cause; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_mem_cmd; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_mem_cmd = dis_uops_0_bits_mem_cmd; // @[util.scala:104:23] wire [4:0] stq_uop_out_mem_cmd = dis_uops_0_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_mem_size; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_mem_size = dis_uops_0_bits_mem_size; // @[util.scala:104:23] wire [1:0] stq_uop_out_mem_size = dis_uops_0_bits_mem_size; // @[util.scala:104:23] reg dis_uops_0_bits_mem_signed; // @[lsu.scala:352:23] wire ldq_uop_out_mem_signed = dis_uops_0_bits_mem_signed; // @[util.scala:104:23] wire stq_uop_out_mem_signed = dis_uops_0_bits_mem_signed; // @[util.scala:104:23] reg dis_uops_0_bits_uses_ldq; // @[lsu.scala:352:23] wire ldq_uop_out_uses_ldq = dis_uops_0_bits_uses_ldq; // @[util.scala:104:23] wire stq_uop_out_uses_ldq = dis_uops_0_bits_uses_ldq; // @[util.scala:104:23] reg dis_uops_0_bits_uses_stq; // @[lsu.scala:352:23] wire ldq_uop_out_uses_stq = dis_uops_0_bits_uses_stq; // @[util.scala:104:23] wire stq_uop_out_uses_stq = dis_uops_0_bits_uses_stq; // @[util.scala:104:23] reg dis_uops_0_bits_is_unique; // @[lsu.scala:352:23] wire ldq_uop_out_is_unique = dis_uops_0_bits_is_unique; // @[util.scala:104:23] wire stq_uop_out_is_unique = dis_uops_0_bits_is_unique; // @[util.scala:104:23] reg dis_uops_0_bits_flush_on_commit; // @[lsu.scala:352:23] wire ldq_uop_out_flush_on_commit = dis_uops_0_bits_flush_on_commit; // @[util.scala:104:23] wire stq_uop_out_flush_on_commit = dis_uops_0_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_csr_cmd; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_csr_cmd = dis_uops_0_bits_csr_cmd; // @[util.scala:104:23] wire [2:0] stq_uop_out_csr_cmd = dis_uops_0_bits_csr_cmd; // @[util.scala:104:23] reg dis_uops_0_bits_ldst_is_rs1; // @[lsu.scala:352:23] wire ldq_uop_out_ldst_is_rs1 = dis_uops_0_bits_ldst_is_rs1; // @[util.scala:104:23] wire stq_uop_out_ldst_is_rs1 = dis_uops_0_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_ldst; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_ldst = dis_uops_0_bits_ldst; // @[util.scala:104:23] wire [5:0] stq_uop_out_ldst = dis_uops_0_bits_ldst; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_lrs1; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_lrs1 = dis_uops_0_bits_lrs1; // @[util.scala:104:23] wire [5:0] stq_uop_out_lrs1 = dis_uops_0_bits_lrs1; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_lrs2; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_lrs2 = dis_uops_0_bits_lrs2; // @[util.scala:104:23] wire [5:0] stq_uop_out_lrs2 = dis_uops_0_bits_lrs2; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_lrs3; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_lrs3 = dis_uops_0_bits_lrs3; // @[util.scala:104:23] wire [5:0] stq_uop_out_lrs3 = dis_uops_0_bits_lrs3; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_dst_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_dst_rtype = dis_uops_0_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_dst_rtype = dis_uops_0_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_lrs1_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_lrs1_rtype = dis_uops_0_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_lrs1_rtype = dis_uops_0_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_lrs2_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_lrs2_rtype = dis_uops_0_bits_lrs2_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_lrs2_rtype = dis_uops_0_bits_lrs2_rtype; // @[util.scala:104:23] reg dis_uops_0_bits_frs3_en; // @[lsu.scala:352:23] wire ldq_uop_out_frs3_en = dis_uops_0_bits_frs3_en; // @[util.scala:104:23] wire stq_uop_out_frs3_en = dis_uops_0_bits_frs3_en; // @[util.scala:104:23] reg dis_uops_0_bits_fcn_dw; // @[lsu.scala:352:23] wire ldq_uop_out_fcn_dw = dis_uops_0_bits_fcn_dw; // @[util.scala:104:23] wire stq_uop_out_fcn_dw = dis_uops_0_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_fcn_op; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_fcn_op = dis_uops_0_bits_fcn_op; // @[util.scala:104:23] wire [4:0] stq_uop_out_fcn_op = dis_uops_0_bits_fcn_op; // @[util.scala:104:23] reg dis_uops_0_bits_fp_val; // @[lsu.scala:352:23] wire ldq_uop_out_fp_val = dis_uops_0_bits_fp_val; // @[util.scala:104:23] wire stq_uop_out_fp_val = dis_uops_0_bits_fp_val; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_fp_rm; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_fp_rm = dis_uops_0_bits_fp_rm; // @[util.scala:104:23] wire [2:0] stq_uop_out_fp_rm = dis_uops_0_bits_fp_rm; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_fp_typ; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_fp_typ = dis_uops_0_bits_fp_typ; // @[util.scala:104:23] wire [1:0] stq_uop_out_fp_typ = dis_uops_0_bits_fp_typ; // @[util.scala:104:23] reg dis_uops_0_bits_xcpt_pf_if; // @[lsu.scala:352:23] wire ldq_uop_out_xcpt_pf_if = dis_uops_0_bits_xcpt_pf_if; // @[util.scala:104:23] wire stq_uop_out_xcpt_pf_if = dis_uops_0_bits_xcpt_pf_if; // @[util.scala:104:23] reg dis_uops_0_bits_xcpt_ae_if; // @[lsu.scala:352:23] wire ldq_uop_out_xcpt_ae_if = dis_uops_0_bits_xcpt_ae_if; // @[util.scala:104:23] wire stq_uop_out_xcpt_ae_if = dis_uops_0_bits_xcpt_ae_if; // @[util.scala:104:23] reg dis_uops_0_bits_xcpt_ma_if; // @[lsu.scala:352:23] wire ldq_uop_out_xcpt_ma_if = dis_uops_0_bits_xcpt_ma_if; // @[util.scala:104:23] wire stq_uop_out_xcpt_ma_if = dis_uops_0_bits_xcpt_ma_if; // @[util.scala:104:23] reg dis_uops_0_bits_bp_debug_if; // @[lsu.scala:352:23] wire ldq_uop_out_bp_debug_if = dis_uops_0_bits_bp_debug_if; // @[util.scala:104:23] wire stq_uop_out_bp_debug_if = dis_uops_0_bits_bp_debug_if; // @[util.scala:104:23] reg dis_uops_0_bits_bp_xcpt_if; // @[lsu.scala:352:23] wire ldq_uop_out_bp_xcpt_if = dis_uops_0_bits_bp_xcpt_if; // @[util.scala:104:23] wire stq_uop_out_bp_xcpt_if = dis_uops_0_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_debug_fsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_debug_fsrc = dis_uops_0_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_debug_fsrc = dis_uops_0_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_debug_tsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_debug_tsrc = dis_uops_0_bits_debug_tsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_debug_tsrc = dis_uops_0_bits_debug_tsrc; // @[util.scala:104:23] reg dis_uops_1_valid; // @[lsu.scala:352:23] reg [31:0] dis_uops_1_bits_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_1_inst = dis_uops_1_bits_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_1_inst = dis_uops_1_bits_inst; // @[util.scala:104:23] reg [31:0] dis_uops_1_bits_debug_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_1_debug_inst = dis_uops_1_bits_debug_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_1_debug_inst = dis_uops_1_bits_debug_inst; // @[util.scala:104:23] reg dis_uops_1_bits_is_rvc; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_rvc = dis_uops_1_bits_is_rvc; // @[util.scala:104:23] wire stq_uop_out_1_is_rvc = dis_uops_1_bits_is_rvc; // @[util.scala:104:23] reg [39:0] dis_uops_1_bits_debug_pc; // @[lsu.scala:352:23] wire [39:0] ldq_uop_out_1_debug_pc = dis_uops_1_bits_debug_pc; // @[util.scala:104:23] wire [39:0] stq_uop_out_1_debug_pc = dis_uops_1_bits_debug_pc; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_0; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_0 = dis_uops_1_bits_iq_type_0; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_0 = dis_uops_1_bits_iq_type_0; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_1; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_1 = dis_uops_1_bits_iq_type_1; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_1 = dis_uops_1_bits_iq_type_1; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_2; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_2 = dis_uops_1_bits_iq_type_2; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_2 = dis_uops_1_bits_iq_type_2; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_3; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_3 = dis_uops_1_bits_iq_type_3; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_3 = dis_uops_1_bits_iq_type_3; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_0; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_0 = dis_uops_1_bits_fu_code_0; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_0 = dis_uops_1_bits_fu_code_0; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_1; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_1 = dis_uops_1_bits_fu_code_1; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_1 = dis_uops_1_bits_fu_code_1; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_2; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_2 = dis_uops_1_bits_fu_code_2; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_2 = dis_uops_1_bits_fu_code_2; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_3; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_3 = dis_uops_1_bits_fu_code_3; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_3 = dis_uops_1_bits_fu_code_3; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_4; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_4 = dis_uops_1_bits_fu_code_4; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_4 = dis_uops_1_bits_fu_code_4; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_5; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_5 = dis_uops_1_bits_fu_code_5; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_5 = dis_uops_1_bits_fu_code_5; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_6; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_6 = dis_uops_1_bits_fu_code_6; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_6 = dis_uops_1_bits_fu_code_6; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_7; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_7 = dis_uops_1_bits_fu_code_7; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_7 = dis_uops_1_bits_fu_code_7; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_8; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_8 = dis_uops_1_bits_fu_code_8; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_8 = dis_uops_1_bits_fu_code_8; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_9; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_9 = dis_uops_1_bits_fu_code_9; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_9 = dis_uops_1_bits_fu_code_9; // @[util.scala:104:23] reg dis_uops_1_bits_iw_issued; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_issued = dis_uops_1_bits_iw_issued; // @[util.scala:104:23] wire stq_uop_out_1_iw_issued = dis_uops_1_bits_iw_issued; // @[util.scala:104:23] reg dis_uops_1_bits_iw_issued_partial_agen; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_issued_partial_agen = dis_uops_1_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire stq_uop_out_1_iw_issued_partial_agen = dis_uops_1_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg dis_uops_1_bits_iw_issued_partial_dgen; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_issued_partial_dgen = dis_uops_1_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire stq_uop_out_1_iw_issued_partial_dgen = dis_uops_1_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_iw_p1_speculative_child; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_iw_p1_speculative_child = dis_uops_1_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_iw_p1_speculative_child = dis_uops_1_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_iw_p2_speculative_child; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_iw_p2_speculative_child = dis_uops_1_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_iw_p2_speculative_child = dis_uops_1_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg dis_uops_1_bits_iw_p1_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_p1_bypass_hint = dis_uops_1_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_1_iw_p1_bypass_hint = dis_uops_1_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg dis_uops_1_bits_iw_p2_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_p2_bypass_hint = dis_uops_1_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_1_iw_p2_bypass_hint = dis_uops_1_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg dis_uops_1_bits_iw_p3_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_p3_bypass_hint = dis_uops_1_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_1_iw_p3_bypass_hint = dis_uops_1_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_dis_col_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_dis_col_sel = dis_uops_1_bits_dis_col_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_dis_col_sel = dis_uops_1_bits_dis_col_sel; // @[util.scala:104:23] reg [11:0] dis_uops_1_bits_br_mask; // @[lsu.scala:352:23] reg [3:0] dis_uops_1_bits_br_tag; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_1_br_tag = dis_uops_1_bits_br_tag; // @[util.scala:104:23] wire [3:0] stq_uop_out_1_br_tag = dis_uops_1_bits_br_tag; // @[util.scala:104:23] reg [3:0] dis_uops_1_bits_br_type; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_1_br_type = dis_uops_1_bits_br_type; // @[util.scala:104:23] wire [3:0] stq_uop_out_1_br_type = dis_uops_1_bits_br_type; // @[util.scala:104:23] reg dis_uops_1_bits_is_sfb; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_sfb = dis_uops_1_bits_is_sfb; // @[util.scala:104:23] wire stq_uop_out_1_is_sfb = dis_uops_1_bits_is_sfb; // @[util.scala:104:23] reg dis_uops_1_bits_is_fence; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_fence = dis_uops_1_bits_is_fence; // @[util.scala:104:23] wire stq_uop_out_1_is_fence = dis_uops_1_bits_is_fence; // @[util.scala:104:23] reg dis_uops_1_bits_is_fencei; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_fencei = dis_uops_1_bits_is_fencei; // @[util.scala:104:23] wire stq_uop_out_1_is_fencei = dis_uops_1_bits_is_fencei; // @[util.scala:104:23] reg dis_uops_1_bits_is_sfence; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_sfence = dis_uops_1_bits_is_sfence; // @[util.scala:104:23] wire stq_uop_out_1_is_sfence = dis_uops_1_bits_is_sfence; // @[util.scala:104:23] reg dis_uops_1_bits_is_amo; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_amo = dis_uops_1_bits_is_amo; // @[util.scala:104:23] wire stq_uop_out_1_is_amo = dis_uops_1_bits_is_amo; // @[util.scala:104:23] reg dis_uops_1_bits_is_eret; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_eret = dis_uops_1_bits_is_eret; // @[util.scala:104:23] wire stq_uop_out_1_is_eret = dis_uops_1_bits_is_eret; // @[util.scala:104:23] reg dis_uops_1_bits_is_sys_pc2epc; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_sys_pc2epc = dis_uops_1_bits_is_sys_pc2epc; // @[util.scala:104:23] wire stq_uop_out_1_is_sys_pc2epc = dis_uops_1_bits_is_sys_pc2epc; // @[util.scala:104:23] reg dis_uops_1_bits_is_rocc; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_rocc = dis_uops_1_bits_is_rocc; // @[util.scala:104:23] wire stq_uop_out_1_is_rocc = dis_uops_1_bits_is_rocc; // @[util.scala:104:23] reg dis_uops_1_bits_is_mov; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_mov = dis_uops_1_bits_is_mov; // @[util.scala:104:23] wire stq_uop_out_1_is_mov = dis_uops_1_bits_is_mov; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_ftq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_ftq_idx = dis_uops_1_bits_ftq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_ftq_idx = dis_uops_1_bits_ftq_idx; // @[util.scala:104:23] reg dis_uops_1_bits_edge_inst; // @[lsu.scala:352:23] wire ldq_uop_out_1_edge_inst = dis_uops_1_bits_edge_inst; // @[util.scala:104:23] wire stq_uop_out_1_edge_inst = dis_uops_1_bits_edge_inst; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_pc_lob; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_pc_lob = dis_uops_1_bits_pc_lob; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_pc_lob = dis_uops_1_bits_pc_lob; // @[util.scala:104:23] reg dis_uops_1_bits_taken; // @[lsu.scala:352:23] wire ldq_uop_out_1_taken = dis_uops_1_bits_taken; // @[util.scala:104:23] wire stq_uop_out_1_taken = dis_uops_1_bits_taken; // @[util.scala:104:23] reg dis_uops_1_bits_imm_rename; // @[lsu.scala:352:23] wire ldq_uop_out_1_imm_rename = dis_uops_1_bits_imm_rename; // @[util.scala:104:23] wire stq_uop_out_1_imm_rename = dis_uops_1_bits_imm_rename; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_imm_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_imm_sel = dis_uops_1_bits_imm_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_imm_sel = dis_uops_1_bits_imm_sel; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_pimm; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_pimm = dis_uops_1_bits_pimm; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_pimm = dis_uops_1_bits_pimm; // @[util.scala:104:23] reg [19:0] dis_uops_1_bits_imm_packed; // @[lsu.scala:352:23] wire [19:0] ldq_uop_out_1_imm_packed = dis_uops_1_bits_imm_packed; // @[util.scala:104:23] wire [19:0] stq_uop_out_1_imm_packed = dis_uops_1_bits_imm_packed; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_op1_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_op1_sel = dis_uops_1_bits_op1_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_op1_sel = dis_uops_1_bits_op1_sel; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_op2_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_op2_sel = dis_uops_1_bits_op2_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_op2_sel = dis_uops_1_bits_op2_sel; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ldst; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ldst = dis_uops_1_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ldst = dis_uops_1_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_wen; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_wen = dis_uops_1_bits_fp_ctrl_wen; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_wen = dis_uops_1_bits_fp_ctrl_wen; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ren1; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ren1 = dis_uops_1_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ren1 = dis_uops_1_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ren2; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ren2 = dis_uops_1_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ren2 = dis_uops_1_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ren3; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ren3 = dis_uops_1_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ren3 = dis_uops_1_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_swap12; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_swap12 = dis_uops_1_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_swap12 = dis_uops_1_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_swap23; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_swap23 = dis_uops_1_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_swap23 = dis_uops_1_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_fp_ctrl_typeTagIn; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_fp_ctrl_typeTagIn = dis_uops_1_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_fp_ctrl_typeTagIn = dis_uops_1_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_fp_ctrl_typeTagOut; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_fp_ctrl_typeTagOut = dis_uops_1_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_fp_ctrl_typeTagOut = dis_uops_1_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_fromint; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_fromint = dis_uops_1_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_fromint = dis_uops_1_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_toint; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_toint = dis_uops_1_bits_fp_ctrl_toint; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_toint = dis_uops_1_bits_fp_ctrl_toint; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_fastpipe; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_fastpipe = dis_uops_1_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_fastpipe = dis_uops_1_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_fma; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_fma = dis_uops_1_bits_fp_ctrl_fma; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_fma = dis_uops_1_bits_fp_ctrl_fma; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_div; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_div = dis_uops_1_bits_fp_ctrl_div; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_div = dis_uops_1_bits_fp_ctrl_div; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_sqrt; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_sqrt = dis_uops_1_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_sqrt = dis_uops_1_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_wflags; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_wflags = dis_uops_1_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_wflags = dis_uops_1_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_vec; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_vec = dis_uops_1_bits_fp_ctrl_vec; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_vec = dis_uops_1_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_rob_idx; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_rob_idx = dis_uops_1_bits_rob_idx; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_rob_idx = dis_uops_1_bits_rob_idx; // @[util.scala:104:23] reg [3:0] dis_uops_1_bits_ldq_idx; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_1_ldq_idx = dis_uops_1_bits_ldq_idx; // @[util.scala:104:23] wire [3:0] stq_uop_out_1_ldq_idx = dis_uops_1_bits_ldq_idx; // @[util.scala:104:23] reg [3:0] dis_uops_1_bits_stq_idx; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_1_stq_idx = dis_uops_1_bits_stq_idx; // @[util.scala:104:23] wire [3:0] stq_uop_out_1_stq_idx = dis_uops_1_bits_stq_idx; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_rxq_idx; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_rxq_idx = dis_uops_1_bits_rxq_idx; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_rxq_idx = dis_uops_1_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_pdst = dis_uops_1_bits_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_pdst = dis_uops_1_bits_pdst; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_prs1; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_prs1 = dis_uops_1_bits_prs1; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_prs1 = dis_uops_1_bits_prs1; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_prs2; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_prs2 = dis_uops_1_bits_prs2; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_prs2 = dis_uops_1_bits_prs2; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_prs3; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_prs3 = dis_uops_1_bits_prs3; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_prs3 = dis_uops_1_bits_prs3; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_ppred; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_ppred = dis_uops_1_bits_ppred; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_ppred = dis_uops_1_bits_ppred; // @[util.scala:104:23] reg dis_uops_1_bits_prs1_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_prs1_busy = dis_uops_1_bits_prs1_busy; // @[util.scala:104:23] wire stq_uop_out_1_prs1_busy = dis_uops_1_bits_prs1_busy; // @[util.scala:104:23] reg dis_uops_1_bits_prs2_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_prs2_busy = dis_uops_1_bits_prs2_busy; // @[util.scala:104:23] wire stq_uop_out_1_prs2_busy = dis_uops_1_bits_prs2_busy; // @[util.scala:104:23] reg dis_uops_1_bits_prs3_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_prs3_busy = dis_uops_1_bits_prs3_busy; // @[util.scala:104:23] wire stq_uop_out_1_prs3_busy = dis_uops_1_bits_prs3_busy; // @[util.scala:104:23] reg dis_uops_1_bits_ppred_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_ppred_busy = dis_uops_1_bits_ppred_busy; // @[util.scala:104:23] wire stq_uop_out_1_ppred_busy = dis_uops_1_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_stale_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_stale_pdst = dis_uops_1_bits_stale_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_stale_pdst = dis_uops_1_bits_stale_pdst; // @[util.scala:104:23] reg dis_uops_1_bits_exception; // @[lsu.scala:352:23] wire ldq_uop_out_1_exception = dis_uops_1_bits_exception; // @[util.scala:104:23] wire stq_uop_out_1_exception = dis_uops_1_bits_exception; // @[util.scala:104:23] reg [63:0] dis_uops_1_bits_exc_cause; // @[lsu.scala:352:23] wire [63:0] ldq_uop_out_1_exc_cause = dis_uops_1_bits_exc_cause; // @[util.scala:104:23] wire [63:0] stq_uop_out_1_exc_cause = dis_uops_1_bits_exc_cause; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_mem_cmd; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_mem_cmd = dis_uops_1_bits_mem_cmd; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_mem_cmd = dis_uops_1_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_mem_size; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_mem_size = dis_uops_1_bits_mem_size; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_mem_size = dis_uops_1_bits_mem_size; // @[util.scala:104:23] reg dis_uops_1_bits_mem_signed; // @[lsu.scala:352:23] wire ldq_uop_out_1_mem_signed = dis_uops_1_bits_mem_signed; // @[util.scala:104:23] wire stq_uop_out_1_mem_signed = dis_uops_1_bits_mem_signed; // @[util.scala:104:23] reg dis_uops_1_bits_uses_ldq; // @[lsu.scala:352:23] wire ldq_uop_out_1_uses_ldq = dis_uops_1_bits_uses_ldq; // @[util.scala:104:23] wire stq_uop_out_1_uses_ldq = dis_uops_1_bits_uses_ldq; // @[util.scala:104:23] reg dis_uops_1_bits_uses_stq; // @[lsu.scala:352:23] wire ldq_uop_out_1_uses_stq = dis_uops_1_bits_uses_stq; // @[util.scala:104:23] wire stq_uop_out_1_uses_stq = dis_uops_1_bits_uses_stq; // @[util.scala:104:23] reg dis_uops_1_bits_is_unique; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_unique = dis_uops_1_bits_is_unique; // @[util.scala:104:23] wire stq_uop_out_1_is_unique = dis_uops_1_bits_is_unique; // @[util.scala:104:23] reg dis_uops_1_bits_flush_on_commit; // @[lsu.scala:352:23] wire ldq_uop_out_1_flush_on_commit = dis_uops_1_bits_flush_on_commit; // @[util.scala:104:23] wire stq_uop_out_1_flush_on_commit = dis_uops_1_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_csr_cmd; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_csr_cmd = dis_uops_1_bits_csr_cmd; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_csr_cmd = dis_uops_1_bits_csr_cmd; // @[util.scala:104:23] reg dis_uops_1_bits_ldst_is_rs1; // @[lsu.scala:352:23] wire ldq_uop_out_1_ldst_is_rs1 = dis_uops_1_bits_ldst_is_rs1; // @[util.scala:104:23] wire stq_uop_out_1_ldst_is_rs1 = dis_uops_1_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_ldst; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_ldst = dis_uops_1_bits_ldst; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_ldst = dis_uops_1_bits_ldst; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_lrs1; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_lrs1 = dis_uops_1_bits_lrs1; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_lrs1 = dis_uops_1_bits_lrs1; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_lrs2; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_lrs2 = dis_uops_1_bits_lrs2; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_lrs2 = dis_uops_1_bits_lrs2; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_lrs3; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_lrs3 = dis_uops_1_bits_lrs3; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_lrs3 = dis_uops_1_bits_lrs3; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_dst_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_dst_rtype = dis_uops_1_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_dst_rtype = dis_uops_1_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_lrs1_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_lrs1_rtype = dis_uops_1_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_lrs1_rtype = dis_uops_1_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_lrs2_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_lrs2_rtype = dis_uops_1_bits_lrs2_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_lrs2_rtype = dis_uops_1_bits_lrs2_rtype; // @[util.scala:104:23] reg dis_uops_1_bits_frs3_en; // @[lsu.scala:352:23] wire ldq_uop_out_1_frs3_en = dis_uops_1_bits_frs3_en; // @[util.scala:104:23] wire stq_uop_out_1_frs3_en = dis_uops_1_bits_frs3_en; // @[util.scala:104:23] reg dis_uops_1_bits_fcn_dw; // @[lsu.scala:352:23] wire ldq_uop_out_1_fcn_dw = dis_uops_1_bits_fcn_dw; // @[util.scala:104:23] wire stq_uop_out_1_fcn_dw = dis_uops_1_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_fcn_op; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_fcn_op = dis_uops_1_bits_fcn_op; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_fcn_op = dis_uops_1_bits_fcn_op; // @[util.scala:104:23] reg dis_uops_1_bits_fp_val; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_val = dis_uops_1_bits_fp_val; // @[util.scala:104:23] wire stq_uop_out_1_fp_val = dis_uops_1_bits_fp_val; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_fp_rm; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_fp_rm = dis_uops_1_bits_fp_rm; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_fp_rm = dis_uops_1_bits_fp_rm; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_fp_typ; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_fp_typ = dis_uops_1_bits_fp_typ; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_fp_typ = dis_uops_1_bits_fp_typ; // @[util.scala:104:23] reg dis_uops_1_bits_xcpt_pf_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_xcpt_pf_if = dis_uops_1_bits_xcpt_pf_if; // @[util.scala:104:23] wire stq_uop_out_1_xcpt_pf_if = dis_uops_1_bits_xcpt_pf_if; // @[util.scala:104:23] reg dis_uops_1_bits_xcpt_ae_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_xcpt_ae_if = dis_uops_1_bits_xcpt_ae_if; // @[util.scala:104:23] wire stq_uop_out_1_xcpt_ae_if = dis_uops_1_bits_xcpt_ae_if; // @[util.scala:104:23] reg dis_uops_1_bits_xcpt_ma_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_xcpt_ma_if = dis_uops_1_bits_xcpt_ma_if; // @[util.scala:104:23] wire stq_uop_out_1_xcpt_ma_if = dis_uops_1_bits_xcpt_ma_if; // @[util.scala:104:23] reg dis_uops_1_bits_bp_debug_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_bp_debug_if = dis_uops_1_bits_bp_debug_if; // @[util.scala:104:23] wire stq_uop_out_1_bp_debug_if = dis_uops_1_bits_bp_debug_if; // @[util.scala:104:23] reg dis_uops_1_bits_bp_xcpt_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_bp_xcpt_if = dis_uops_1_bits_bp_xcpt_if; // @[util.scala:104:23] wire stq_uop_out_1_bp_xcpt_if = dis_uops_1_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_debug_fsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_debug_fsrc = dis_uops_1_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_debug_fsrc = dis_uops_1_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_debug_tsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_debug_tsrc = dis_uops_1_bits_debug_tsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_debug_tsrc = dis_uops_1_bits_debug_tsrc; // @[util.scala:104:23] wire [1:0] _GEN_0 = {stq_valid_1, stq_valid_0}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_lo_lo; // @[lsu.scala:354:35] assign live_store_mask_lo_lo_lo = _GEN_0; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_lo_lo; // @[lsu.scala:362:31] assign stq_valids_lo_lo_lo = _GEN_0; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_lo_lo; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_lo_lo = _GEN_0; // @[lsu.scala:354:35, :1342:35] wire [1:0] _GEN_1 = {stq_valid_3, stq_valid_2}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_lo_hi; // @[lsu.scala:354:35] assign live_store_mask_lo_lo_hi = _GEN_1; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_lo_hi; // @[lsu.scala:362:31] assign stq_valids_lo_lo_hi = _GEN_1; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_lo_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_lo_hi = _GEN_1; // @[lsu.scala:354:35, :1342:35] wire [3:0] live_store_mask_lo_lo = {live_store_mask_lo_lo_hi, live_store_mask_lo_lo_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_2 = {stq_valid_5, stq_valid_4}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_hi_lo; // @[lsu.scala:354:35] assign live_store_mask_lo_hi_lo = _GEN_2; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_hi_lo; // @[lsu.scala:362:31] assign stq_valids_lo_hi_lo = _GEN_2; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_hi_lo; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_hi_lo = _GEN_2; // @[lsu.scala:354:35, :1342:35] wire [1:0] _GEN_3 = {stq_valid_7, stq_valid_6}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_hi_hi; // @[lsu.scala:354:35] assign live_store_mask_lo_hi_hi = _GEN_3; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_hi_hi; // @[lsu.scala:362:31] assign stq_valids_lo_hi_hi = _GEN_3; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_hi_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_hi_hi = _GEN_3; // @[lsu.scala:354:35, :1342:35] wire [3:0] live_store_mask_lo_hi = {live_store_mask_lo_hi_hi, live_store_mask_lo_hi_lo}; // @[lsu.scala:354:35] wire [7:0] live_store_mask_lo = {live_store_mask_lo_hi, live_store_mask_lo_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_4 = {stq_valid_9, stq_valid_8}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_lo_lo; // @[lsu.scala:354:35] assign live_store_mask_hi_lo_lo = _GEN_4; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_lo_lo; // @[lsu.scala:362:31] assign stq_valids_hi_lo_lo = _GEN_4; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_lo_lo; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_lo_lo = _GEN_4; // @[lsu.scala:354:35, :1342:35] wire [1:0] _GEN_5 = {stq_valid_11, stq_valid_10}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_lo_hi; // @[lsu.scala:354:35] assign live_store_mask_hi_lo_hi = _GEN_5; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_lo_hi; // @[lsu.scala:362:31] assign stq_valids_hi_lo_hi = _GEN_5; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_lo_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_lo_hi = _GEN_5; // @[lsu.scala:354:35, :1342:35] wire [3:0] live_store_mask_hi_lo = {live_store_mask_hi_lo_hi, live_store_mask_hi_lo_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_6 = {stq_valid_13, stq_valid_12}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_hi_lo; // @[lsu.scala:354:35] assign live_store_mask_hi_hi_lo = _GEN_6; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_hi_lo; // @[lsu.scala:362:31] assign stq_valids_hi_hi_lo = _GEN_6; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_hi_lo; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_hi_lo = _GEN_6; // @[lsu.scala:354:35, :1342:35] wire [1:0] _GEN_7 = {stq_valid_15, stq_valid_14}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_hi_hi; // @[lsu.scala:354:35] assign live_store_mask_hi_hi_hi = _GEN_7; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_hi_hi; // @[lsu.scala:362:31] assign stq_valids_hi_hi_hi = _GEN_7; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_hi_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_hi_hi = _GEN_7; // @[lsu.scala:354:35, :1342:35] wire [3:0] live_store_mask_hi_hi = {live_store_mask_hi_hi_hi, live_store_mask_hi_hi_lo}; // @[lsu.scala:354:35] wire [7:0] live_store_mask_hi = {live_store_mask_hi_hi, live_store_mask_hi_lo}; // @[lsu.scala:354:35] wire [15:0] _live_store_mask_T = {live_store_mask_hi, live_store_mask_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_8 = {dis_stq_oh_1, dis_stq_oh_0}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_lo_lo_1; // @[lsu.scala:354:55] assign live_store_mask_lo_lo_lo_1 = _GEN_8; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_lo_lo_1; // @[lsu.scala:362:51] assign stq_valids_lo_lo_lo_1 = _GEN_8; // @[lsu.scala:354:55, :362:51] wire [1:0] _GEN_9 = {dis_stq_oh_3, dis_stq_oh_2}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_lo_hi_1; // @[lsu.scala:354:55] assign live_store_mask_lo_lo_hi_1 = _GEN_9; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_lo_hi_1; // @[lsu.scala:362:51] assign stq_valids_lo_lo_hi_1 = _GEN_9; // @[lsu.scala:354:55, :362:51] wire [3:0] live_store_mask_lo_lo_1 = {live_store_mask_lo_lo_hi_1, live_store_mask_lo_lo_lo_1}; // @[lsu.scala:354:55] wire [1:0] _GEN_10 = {dis_stq_oh_5, dis_stq_oh_4}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_hi_lo_1; // @[lsu.scala:354:55] assign live_store_mask_lo_hi_lo_1 = _GEN_10; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_hi_lo_1; // @[lsu.scala:362:51] assign stq_valids_lo_hi_lo_1 = _GEN_10; // @[lsu.scala:354:55, :362:51] wire [1:0] _GEN_11 = {dis_stq_oh_7, dis_stq_oh_6}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_hi_hi_1; // @[lsu.scala:354:55] assign live_store_mask_lo_hi_hi_1 = _GEN_11; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_hi_hi_1; // @[lsu.scala:362:51] assign stq_valids_lo_hi_hi_1 = _GEN_11; // @[lsu.scala:354:55, :362:51] wire [3:0] live_store_mask_lo_hi_1 = {live_store_mask_lo_hi_hi_1, live_store_mask_lo_hi_lo_1}; // @[lsu.scala:354:55] wire [7:0] live_store_mask_lo_1 = {live_store_mask_lo_hi_1, live_store_mask_lo_lo_1}; // @[lsu.scala:354:55] wire [1:0] _GEN_12 = {dis_stq_oh_9, dis_stq_oh_8}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_lo_lo_1; // @[lsu.scala:354:55] assign live_store_mask_hi_lo_lo_1 = _GEN_12; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_lo_lo_1; // @[lsu.scala:362:51] assign stq_valids_hi_lo_lo_1 = _GEN_12; // @[lsu.scala:354:55, :362:51] wire [1:0] _GEN_13 = {dis_stq_oh_11, dis_stq_oh_10}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_lo_hi_1; // @[lsu.scala:354:55] assign live_store_mask_hi_lo_hi_1 = _GEN_13; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_lo_hi_1; // @[lsu.scala:362:51] assign stq_valids_hi_lo_hi_1 = _GEN_13; // @[lsu.scala:354:55, :362:51] wire [3:0] live_store_mask_hi_lo_1 = {live_store_mask_hi_lo_hi_1, live_store_mask_hi_lo_lo_1}; // @[lsu.scala:354:55] wire [1:0] _GEN_14 = {dis_stq_oh_13, dis_stq_oh_12}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_hi_lo_1; // @[lsu.scala:354:55] assign live_store_mask_hi_hi_lo_1 = _GEN_14; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_hi_lo_1; // @[lsu.scala:362:51] assign stq_valids_hi_hi_lo_1 = _GEN_14; // @[lsu.scala:354:55, :362:51] wire [1:0] _GEN_15 = {dis_stq_oh_15, dis_stq_oh_14}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_hi_hi_1; // @[lsu.scala:354:55] assign live_store_mask_hi_hi_hi_1 = _GEN_15; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_hi_hi_1; // @[lsu.scala:362:51] assign stq_valids_hi_hi_hi_1 = _GEN_15; // @[lsu.scala:354:55, :362:51] wire [3:0] live_store_mask_hi_hi_1 = {live_store_mask_hi_hi_hi_1, live_store_mask_hi_hi_lo_1}; // @[lsu.scala:354:55] wire [7:0] live_store_mask_hi_1 = {live_store_mask_hi_hi_1, live_store_mask_hi_lo_1}; // @[lsu.scala:354:55] wire [15:0] _live_store_mask_T_1 = {live_store_mask_hi_1, live_store_mask_lo_1}; // @[lsu.scala:354:55] wire [15:0] live_store_mask = _live_store_mask_T | _live_store_mask_T_1; // @[lsu.scala:354:{35,42,55}] wire [15:0] _next_live_store_mask_T_1 = ~_next_live_store_mask_T; // @[lsu.scala:355:{65,71}] wire [15:0] _next_live_store_mask_T_2 = live_store_mask & _next_live_store_mask_T_1; // @[lsu.scala:354:42, :355:{63,65}] wire [15:0] next_live_store_mask = clear_store ? _next_live_store_mask_T_2 : live_store_mask; // @[lsu.scala:318:33, :354:42, :355:{33,63}] wire [15:0] _ldq_tail_oh_T = 16'h1 << ldq_tail; // @[OneHot.scala:58:35] wire [15:0] ldq_tail_oh = _ldq_tail_oh_T; // @[OneHot.scala:58:35] wire [1:0] _GEN_16 = {ldq_valid_1, ldq_valid_0}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_lo_lo; // @[lsu.scala:360:31] assign ldq_valids_lo_lo_lo = _GEN_16; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_lo_lo_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_lo_lo_1 = _GEN_16; // @[lsu.scala:360:31, :1437:58] wire [1:0] _GEN_17 = {ldq_valid_3, ldq_valid_2}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_lo_hi; // @[lsu.scala:360:31] assign ldq_valids_lo_lo_hi = _GEN_17; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_lo_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_lo_hi_1 = _GEN_17; // @[lsu.scala:360:31, :1437:58] wire [3:0] ldq_valids_lo_lo = {ldq_valids_lo_lo_hi, ldq_valids_lo_lo_lo}; // @[lsu.scala:360:31] wire [1:0] _GEN_18 = {ldq_valid_5, ldq_valid_4}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_hi_lo; // @[lsu.scala:360:31] assign ldq_valids_lo_hi_lo = _GEN_18; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_hi_lo_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_hi_lo_1 = _GEN_18; // @[lsu.scala:360:31, :1437:58] wire [1:0] _GEN_19 = {ldq_valid_7, ldq_valid_6}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_hi_hi; // @[lsu.scala:360:31] assign ldq_valids_lo_hi_hi = _GEN_19; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_hi_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_hi_hi_1 = _GEN_19; // @[lsu.scala:360:31, :1437:58] wire [3:0] ldq_valids_lo_hi = {ldq_valids_lo_hi_hi, ldq_valids_lo_hi_lo}; // @[lsu.scala:360:31] wire [7:0] ldq_valids_lo = {ldq_valids_lo_hi, ldq_valids_lo_lo}; // @[lsu.scala:360:31] wire [1:0] _GEN_20 = {ldq_valid_9, ldq_valid_8}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_lo_lo; // @[lsu.scala:360:31] assign ldq_valids_hi_lo_lo = _GEN_20; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_lo_lo_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_lo_lo_1 = _GEN_20; // @[lsu.scala:360:31, :1437:58] wire [1:0] _GEN_21 = {ldq_valid_11, ldq_valid_10}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_lo_hi; // @[lsu.scala:360:31] assign ldq_valids_hi_lo_hi = _GEN_21; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_lo_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_lo_hi_1 = _GEN_21; // @[lsu.scala:360:31, :1437:58] wire [3:0] ldq_valids_hi_lo = {ldq_valids_hi_lo_hi, ldq_valids_hi_lo_lo}; // @[lsu.scala:360:31] wire [1:0] _GEN_22 = {ldq_valid_13, ldq_valid_12}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_hi_lo; // @[lsu.scala:360:31] assign ldq_valids_hi_hi_lo = _GEN_22; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_hi_lo_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_hi_lo_1 = _GEN_22; // @[lsu.scala:360:31, :1437:58] wire [1:0] _GEN_23 = {ldq_valid_15, ldq_valid_14}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_hi_hi; // @[lsu.scala:360:31] assign ldq_valids_hi_hi_hi = _GEN_23; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_hi_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_hi_hi_1 = _GEN_23; // @[lsu.scala:360:31, :1437:58] wire [3:0] ldq_valids_hi_hi = {ldq_valids_hi_hi_hi, ldq_valids_hi_hi_lo}; // @[lsu.scala:360:31] wire [7:0] ldq_valids_hi = {ldq_valids_hi_hi, ldq_valids_hi_lo}; // @[lsu.scala:360:31] wire [15:0] _ldq_valids_T = {ldq_valids_hi, ldq_valids_lo}; // @[lsu.scala:360:31] wire [1:0] ldq_valids_lo_lo_lo_1 = {dis_ldq_oh_1, dis_ldq_oh_0}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_lo_lo_hi_1 = {dis_ldq_oh_3, dis_ldq_oh_2}; // @[lsu.scala:348:23, :360:51] wire [3:0] ldq_valids_lo_lo_1 = {ldq_valids_lo_lo_hi_1, ldq_valids_lo_lo_lo_1}; // @[lsu.scala:360:51] wire [1:0] ldq_valids_lo_hi_lo_1 = {dis_ldq_oh_5, dis_ldq_oh_4}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_lo_hi_hi_1 = {dis_ldq_oh_7, dis_ldq_oh_6}; // @[lsu.scala:348:23, :360:51] wire [3:0] ldq_valids_lo_hi_1 = {ldq_valids_lo_hi_hi_1, ldq_valids_lo_hi_lo_1}; // @[lsu.scala:360:51] wire [7:0] ldq_valids_lo_1 = {ldq_valids_lo_hi_1, ldq_valids_lo_lo_1}; // @[lsu.scala:360:51] wire [1:0] ldq_valids_hi_lo_lo_1 = {dis_ldq_oh_9, dis_ldq_oh_8}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_hi_lo_hi_1 = {dis_ldq_oh_11, dis_ldq_oh_10}; // @[lsu.scala:348:23, :360:51] wire [3:0] ldq_valids_hi_lo_1 = {ldq_valids_hi_lo_hi_1, ldq_valids_hi_lo_lo_1}; // @[lsu.scala:360:51] wire [1:0] ldq_valids_hi_hi_lo_1 = {dis_ldq_oh_13, dis_ldq_oh_12}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_hi_hi_hi_1 = {dis_ldq_oh_15, dis_ldq_oh_14}; // @[lsu.scala:348:23, :360:51] wire [3:0] ldq_valids_hi_hi_1 = {ldq_valids_hi_hi_hi_1, ldq_valids_hi_hi_lo_1}; // @[lsu.scala:360:51] wire [7:0] ldq_valids_hi_1 = {ldq_valids_hi_hi_1, ldq_valids_hi_lo_1}; // @[lsu.scala:360:51] wire [15:0] _ldq_valids_T_1 = {ldq_valids_hi_1, ldq_valids_lo_1}; // @[lsu.scala:360:51] wire [15:0] ldq_valids = _ldq_valids_T | _ldq_valids_T_1; // @[lsu.scala:360:{31,38,51}] wire [15:0] _stq_tail_oh_T = 16'h1 << stq_tail; // @[OneHot.scala:58:35] wire [15:0] stq_tail_oh = _stq_tail_oh_T; // @[OneHot.scala:58:35] wire [3:0] stq_valids_lo_lo = {stq_valids_lo_lo_hi, stq_valids_lo_lo_lo}; // @[lsu.scala:362:31] wire [3:0] stq_valids_lo_hi = {stq_valids_lo_hi_hi, stq_valids_lo_hi_lo}; // @[lsu.scala:362:31] wire [7:0] stq_valids_lo = {stq_valids_lo_hi, stq_valids_lo_lo}; // @[lsu.scala:362:31] wire [3:0] stq_valids_hi_lo = {stq_valids_hi_lo_hi, stq_valids_hi_lo_lo}; // @[lsu.scala:362:31] wire [3:0] stq_valids_hi_hi = {stq_valids_hi_hi_hi, stq_valids_hi_hi_lo}; // @[lsu.scala:362:31] wire [7:0] stq_valids_hi = {stq_valids_hi_hi, stq_valids_hi_lo}; // @[lsu.scala:362:31] wire [15:0] _stq_valids_T = {stq_valids_hi, stq_valids_lo}; // @[lsu.scala:362:31] wire [3:0] stq_valids_lo_lo_1 = {stq_valids_lo_lo_hi_1, stq_valids_lo_lo_lo_1}; // @[lsu.scala:362:51] wire [3:0] stq_valids_lo_hi_1 = {stq_valids_lo_hi_hi_1, stq_valids_lo_hi_lo_1}; // @[lsu.scala:362:51] wire [7:0] stq_valids_lo_1 = {stq_valids_lo_hi_1, stq_valids_lo_lo_1}; // @[lsu.scala:362:51] wire [3:0] stq_valids_hi_lo_1 = {stq_valids_hi_lo_hi_1, stq_valids_hi_lo_lo_1}; // @[lsu.scala:362:51] wire [3:0] stq_valids_hi_hi_1 = {stq_valids_hi_hi_hi_1, stq_valids_hi_hi_lo_1}; // @[lsu.scala:362:51] wire [7:0] stq_valids_hi_1 = {stq_valids_hi_hi_1, stq_valids_hi_lo_1}; // @[lsu.scala:362:51] wire [15:0] _stq_valids_T_1 = {stq_valids_hi_1, stq_valids_lo_1}; // @[lsu.scala:362:51] wire [15:0] stq_valids = _stq_valids_T | _stq_valids_T_1; // @[lsu.scala:362:{31,38,51}] wire _GEN_24 = stq_valid_0 | stq_valid_1; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T; // @[lsu.scala:364:40] assign _stq_nonempty_T = _GEN_24; // @[lsu.scala:364:40] wire _io_hellacache_store_pending_T; // @[lsu.scala:1804:52] assign _io_hellacache_store_pending_T = _GEN_24; // @[lsu.scala:364:40, :1804:52] wire _stq_nonempty_T_1 = _stq_nonempty_T | stq_valid_2; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_2 = _stq_nonempty_T_1 | stq_valid_3; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_3 = _stq_nonempty_T_2 | stq_valid_4; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_4 = _stq_nonempty_T_3 | stq_valid_5; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_5 = _stq_nonempty_T_4 | stq_valid_6; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_6 = _stq_nonempty_T_5 | stq_valid_7; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_7 = _stq_nonempty_T_6 | stq_valid_8; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_8 = _stq_nonempty_T_7 | stq_valid_9; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_9 = _stq_nonempty_T_8 | stq_valid_10; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_10 = _stq_nonempty_T_9 | stq_valid_11; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_11 = _stq_nonempty_T_10 | stq_valid_12; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_12 = _stq_nonempty_T_11 | stq_valid_13; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_13 = _stq_nonempty_T_12 | stq_valid_14; // @[lsu.scala:251:32, :364:40] wire stq_nonempty = _stq_nonempty_T_13 | stq_valid_15; // @[lsu.scala:251:32, :364:40] wire [15:0] _ldq_full_T = ldq_tail_oh & ldq_valids; // @[lsu.scala:359:39, :360:38, :369:33] assign ldq_full = |_ldq_full_T; // @[lsu.scala:369:{33,47}] assign io_core_ldq_full_0_0 = ldq_full; // @[lsu.scala:211:7, :369:47] wire [15:0] _stq_full_T = stq_tail_oh & stq_valids; // @[lsu.scala:361:39, :362:38, :373:33] assign stq_full = |_stq_full_T; // @[lsu.scala:373:{33,47}] assign io_core_stq_full_0_0 = stq_full; // @[lsu.scala:211:7, :373:47] wire _dis_ld_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_ldq_0; // @[lsu.scala:211:7, :377:48] wire _dis_ld_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:211:7, :377:88] wire dis_ld_val = _dis_ld_val_T & _dis_ld_val_T_1; // @[lsu.scala:377:{48,85,88}] wire _dis_st_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_stq_0; // @[lsu.scala:211:7, :378:48] wire _dis_st_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:211:7, :377:88, :378:88] wire dis_st_val = _dis_st_val_T & _dis_st_val_T_1; // @[lsu.scala:378:{48,85,88}] wire _dis_uops_0_valid_T = dis_ld_val | dis_st_val; // @[lsu.scala:377:85, :378:85, :380:37] wire [15:0] _GEN_25 = {{ldq_valid_15}, {ldq_valid_14}, {ldq_valid_13}, {ldq_valid_12}, {ldq_valid_11}, {ldq_valid_10}, {ldq_valid_9}, {ldq_valid_8}, {ldq_valid_7}, {ldq_valid_6}, {ldq_valid_5}, {ldq_valid_4}, {ldq_valid_3}, {ldq_valid_2}, {ldq_valid_1}, {ldq_valid_0}}; // @[lsu.scala:218:36, :387:15] wire [15:0] _GEN_26 = {{stq_valid_15}, {stq_valid_14}, {stq_valid_13}, {stq_valid_12}, {stq_valid_11}, {stq_valid_10}, {stq_valid_9}, {stq_valid_8}, {stq_valid_7}, {stq_valid_6}, {stq_valid_5}, {stq_valid_4}, {stq_valid_3}, {stq_valid_2}, {stq_valid_1}, {stq_valid_0}}; // @[lsu.scala:251:32, :392:15] wire _T_16 = dis_uops_0_valid & dis_uops_0_bits_uses_ldq; // @[lsu.scala:352:23, :394:29] wire [11:0] _GEN_27 = io_core_brupdate_b1_mispredict_mask_0 & dis_uops_0_bits_br_mask; // @[util.scala:126:51] wire [11:0] _ldq_valid_T; // @[util.scala:126:51] assign _ldq_valid_T = _GEN_27; // @[util.scala:126:51] wire [11:0] _stq_valid_T; // @[util.scala:126:51] assign _stq_valid_T = _GEN_27; // @[util.scala:126:51] wire _ldq_valid_T_1 = |_ldq_valid_T; // @[util.scala:126:{51,59}] wire _ldq_valid_T_2 = _ldq_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _ldq_valid_T_3 = ~_ldq_valid_T_2; // @[util.scala:61:61] wire _GEN_28 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h0; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_29 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h1; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_30 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h2; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_31 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h3; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_32 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h4; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_33 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h5; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_34 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h6; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_35 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h7; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_36 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h8; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_37 = _T_16 & dis_uops_0_bits_ldq_idx == 4'h9; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_38 = _T_16 & dis_uops_0_bits_ldq_idx == 4'hA; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_39 = _T_16 & dis_uops_0_bits_ldq_idx == 4'hB; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_40 = _T_16 & dis_uops_0_bits_ldq_idx == 4'hC; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_41 = _T_16 & dis_uops_0_bits_ldq_idx == 4'hD; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_42 = _T_16 & dis_uops_0_bits_ldq_idx == 4'hE; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_43 = _T_16 & (&dis_uops_0_bits_ldq_idx); // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire [11:0] _ldq_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] ldq_uop_out_br_mask; // @[util.scala:104:23] wire [11:0] _ldq_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _ldq_uop_out_br_mask_T_1 = dis_uops_0_bits_br_mask & _ldq_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign ldq_uop_out_br_mask = _ldq_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire _stq_valid_T_1 = |_stq_valid_T; // @[util.scala:126:{51,59}] wire _stq_valid_T_2 = _stq_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _stq_valid_T_3 = ~_stq_valid_T_2; // @[util.scala:61:61] wire [11:0] _stq_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] stq_uop_out_br_mask; // @[util.scala:104:23] wire [11:0] _stq_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _stq_uop_out_br_mask_T_1 = dis_uops_0_bits_br_mask & _stq_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign stq_uop_out_br_mask = _stq_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire [3:0] _T_18 = ldq_tail + 4'h1; // @[util.scala:211:14] assign io_core_dis_ldq_idx_1_0 = dis_ld_val ? _T_18 : ldq_tail; // @[util.scala:211:14] wire [3:0] _T_25 = stq_tail + 4'h1; // @[util.scala:211:14] assign io_core_dis_stq_idx_1_0 = dis_st_val ? _T_25 : stq_tail; // @[util.scala:211:14] wire [14:0] _out_T = ldq_tail_oh[14:0]; // @[util.scala:256:25] wire _out_T_1 = ldq_tail_oh[15]; // @[util.scala:256:40] wire [15:0] out = {_out_T, _out_T_1}; // @[util.scala:256:{18,25,40}] wire [15:0] _T_38 = io_core_dis_uops_0_bits_uses_ldq_0 & ~io_core_dis_uops_0_bits_exception_0 ? out : ldq_tail_oh; // @[util.scala:256:18] wire [14:0] _out_T_2 = stq_tail_oh[14:0]; // @[util.scala:256:25] wire _out_T_3 = stq_tail_oh[15]; // @[util.scala:256:40] wire [15:0] out_1 = {_out_T_2, _out_T_3}; // @[util.scala:256:{18,25,40}] wire [15:0] _T_43 = io_core_dis_uops_0_bits_uses_stq_0 & ~io_core_dis_uops_0_bits_exception_0 ? out_1 : stq_tail_oh; // @[util.scala:256:18] wire [15:0] _ldq_full_T_1 = _T_38 & ldq_valids; // @[lsu.scala:360:38, :369:33, :428:22] assign ldq_full_1 = |_ldq_full_T_1; // @[lsu.scala:369:{33,47}] assign io_core_ldq_full_1_0 = ldq_full_1; // @[lsu.scala:211:7, :369:47] wire [15:0] _stq_full_T_1 = _T_43 & stq_valids; // @[lsu.scala:362:38, :373:33, :430:22] assign stq_full_1 = |_stq_full_T_1; // @[lsu.scala:373:{33,47}] assign io_core_stq_full_1_0 = stq_full_1; // @[lsu.scala:211:7, :373:47] wire _dis_ld_val_T_2 = io_core_dis_uops_1_valid_0 & io_core_dis_uops_1_bits_uses_ldq_0; // @[lsu.scala:211:7, :377:48] wire _dis_ld_val_T_3 = ~io_core_dis_uops_1_bits_exception_0; // @[lsu.scala:211:7, :377:88] wire dis_ld_val_1 = _dis_ld_val_T_2 & _dis_ld_val_T_3; // @[lsu.scala:377:{48,85,88}] wire _dis_st_val_T_2 = io_core_dis_uops_1_valid_0 & io_core_dis_uops_1_bits_uses_stq_0; // @[lsu.scala:211:7, :378:48] wire _dis_st_val_T_3 = ~io_core_dis_uops_1_bits_exception_0; // @[lsu.scala:211:7, :377:88, :378:88] wire dis_st_val_1 = _dis_st_val_T_2 & _dis_st_val_T_3; // @[lsu.scala:378:{48,85,88}] wire _dis_uops_1_valid_T = dis_ld_val_1 | dis_st_val_1; // @[lsu.scala:377:85, :378:85, :380:37] wire _T_60 = dis_uops_1_valid & dis_uops_1_bits_uses_ldq; // @[lsu.scala:352:23, :394:29] wire [11:0] _GEN_44 = io_core_brupdate_b1_mispredict_mask_0 & dis_uops_1_bits_br_mask; // @[util.scala:126:51] wire [11:0] _ldq_valid_T_4; // @[util.scala:126:51] assign _ldq_valid_T_4 = _GEN_44; // @[util.scala:126:51] wire [11:0] _stq_valid_T_4; // @[util.scala:126:51] assign _stq_valid_T_4 = _GEN_44; // @[util.scala:126:51] wire _ldq_valid_T_5 = |_ldq_valid_T_4; // @[util.scala:126:{51,59}] wire _ldq_valid_T_6 = _ldq_valid_T_5 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _ldq_valid_T_7 = ~_ldq_valid_T_6; // @[util.scala:61:61] wire _GEN_45 = dis_uops_1_bits_ldq_idx == 4'h0; // @[lsu.scala:352:23, :396:42] wire _GEN_46 = dis_uops_1_bits_ldq_idx == 4'h1; // @[lsu.scala:352:23, :396:42] wire _GEN_47 = dis_uops_1_bits_ldq_idx == 4'h2; // @[lsu.scala:352:23, :396:42] wire _GEN_48 = dis_uops_1_bits_ldq_idx == 4'h3; // @[lsu.scala:352:23, :396:42] wire _GEN_49 = dis_uops_1_bits_ldq_idx == 4'h4; // @[lsu.scala:352:23, :396:42] wire _GEN_50 = dis_uops_1_bits_ldq_idx == 4'h5; // @[lsu.scala:352:23, :396:42] wire _GEN_51 = dis_uops_1_bits_ldq_idx == 4'h6; // @[lsu.scala:352:23, :396:42] wire _GEN_52 = dis_uops_1_bits_ldq_idx == 4'h7; // @[lsu.scala:352:23, :396:42] wire _GEN_53 = dis_uops_1_bits_ldq_idx == 4'h8; // @[lsu.scala:352:23, :396:42] wire _GEN_54 = dis_uops_1_bits_ldq_idx == 4'h9; // @[lsu.scala:352:23, :396:42] wire _GEN_55 = dis_uops_1_bits_ldq_idx == 4'hA; // @[lsu.scala:352:23, :396:42] wire _GEN_56 = dis_uops_1_bits_ldq_idx == 4'hB; // @[lsu.scala:352:23, :396:42] wire _GEN_57 = dis_uops_1_bits_ldq_idx == 4'hC; // @[lsu.scala:352:23, :396:42] wire _GEN_58 = dis_uops_1_bits_ldq_idx == 4'hD; // @[lsu.scala:352:23, :396:42] wire _GEN_59 = dis_uops_1_bits_ldq_idx == 4'hE; // @[lsu.scala:352:23, :396:42] wire [11:0] _ldq_uop_out_br_mask_T_3; // @[util.scala:93:25] wire [11:0] ldq_uop_out_1_br_mask; // @[util.scala:104:23] wire [11:0] _ldq_uop_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _ldq_uop_out_br_mask_T_3 = dis_uops_1_bits_br_mask & _ldq_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign ldq_uop_out_1_br_mask = _ldq_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire _GEN_60 = _GEN_45 | _GEN_28; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_61 = _GEN_46 | _GEN_29; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_62 = _GEN_47 | _GEN_30; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_63 = _GEN_48 | _GEN_31; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_64 = _GEN_49 | _GEN_32; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_65 = _GEN_50 | _GEN_33; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_66 = _GEN_51 | _GEN_34; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_67 = _GEN_52 | _GEN_35; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_68 = _GEN_53 | _GEN_36; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_69 = _GEN_54 | _GEN_37; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_70 = _GEN_55 | _GEN_38; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_71 = _GEN_56 | _GEN_39; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_72 = _GEN_57 | _GEN_40; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_73 = _GEN_58 | _GEN_41; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_74 = _GEN_59 | _GEN_42; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_75 = (&dis_uops_1_bits_ldq_idx) | _GEN_43; // @[lsu.scala:218:36, :220:36, :352:23, :394:59, :396:42, :399:42] wire _stq_valid_T_5 = |_stq_valid_T_4; // @[util.scala:126:{51,59}] wire _stq_valid_T_6 = _stq_valid_T_5 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _stq_valid_T_7 = ~_stq_valid_T_6; // @[util.scala:61:61] wire [11:0] _stq_uop_out_br_mask_T_3; // @[util.scala:93:25] wire [11:0] stq_uop_out_1_br_mask; // @[util.scala:104:23] wire [11:0] _stq_uop_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _stq_uop_out_br_mask_T_3 = dis_uops_1_bits_br_mask & _stq_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign stq_uop_out_1_br_mask = _stq_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire [14:0] _out_T_4 = _T_38[14:0]; // @[util.scala:256:25] wire _out_T_5 = _T_38[15]; // @[util.scala:256:40] wire [15:0] out_2 = {_out_T_4, _out_T_5}; // @[util.scala:256:{18,25,40}] wire [14:0] _out_T_6 = _T_43[14:0]; // @[util.scala:256:25] wire _out_T_7 = _T_43[15]; // @[util.scala:256:40] wire [15:0] out_3 = {_out_T_6, _out_T_7}; // @[util.scala:256:{18,25,40}] wire stq_enq_e_e_valid = _GEN_26[stq_execute_head]; // @[lsu.scala:262:17, :283:29, :392:15, :438:42] wire _io_core_fencei_rdy_T = ~stq_nonempty; // @[lsu.scala:364:40, :446:28] assign _io_core_fencei_rdy_T_1 = _io_core_fencei_rdy_T & io_dmem_ordered_0; // @[lsu.scala:211:7, :446:{28,42}] assign io_core_fencei_rdy_0 = _io_core_fencei_rdy_T_1; // @[lsu.scala:211:7, :446:42] wire mem_xcpt_valid; // @[lsu.scala:457:29] wire [3:0] mem_xcpt_cause; // @[lsu.scala:458:29] wire mem_xcpt_uop_iq_type_0; // @[lsu.scala:459:29] wire mem_xcpt_uop_iq_type_1; // @[lsu.scala:459:29] wire mem_xcpt_uop_iq_type_2; // @[lsu.scala:459:29] wire mem_xcpt_uop_iq_type_3; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_0; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_1; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_2; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_3; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_4; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_5; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_6; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_7; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_8; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_9; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_div; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:459:29] wire [31:0] mem_xcpt_uop_inst; // @[lsu.scala:459:29] wire [31:0] mem_xcpt_uop_debug_inst; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_rvc; // @[lsu.scala:459:29] wire [39:0] mem_xcpt_uop_debug_pc; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_issued; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_dis_col_sel; // @[lsu.scala:459:29] wire [11:0] mem_xcpt_uop_br_mask; // @[lsu.scala:459:29] wire [3:0] mem_xcpt_uop_br_tag; // @[lsu.scala:459:29] wire [3:0] mem_xcpt_uop_br_type; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_sfb; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_fence; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_fencei; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_sfence; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_amo; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_eret; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_rocc; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_mov; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_ftq_idx; // @[lsu.scala:459:29] wire mem_xcpt_uop_edge_inst; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_pc_lob; // @[lsu.scala:459:29] wire mem_xcpt_uop_taken; // @[lsu.scala:459:29] wire mem_xcpt_uop_imm_rename; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_imm_sel; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_pimm; // @[lsu.scala:459:29] wire [19:0] mem_xcpt_uop_imm_packed; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_op1_sel; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_op2_sel; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_rob_idx; // @[lsu.scala:459:29] wire [3:0] mem_xcpt_uop_ldq_idx; // @[lsu.scala:459:29] wire [3:0] mem_xcpt_uop_stq_idx; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_rxq_idx; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_pdst; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_prs1; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_prs2; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_prs3; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_ppred; // @[lsu.scala:459:29] wire mem_xcpt_uop_prs1_busy; // @[lsu.scala:459:29] wire mem_xcpt_uop_prs2_busy; // @[lsu.scala:459:29] wire mem_xcpt_uop_prs3_busy; // @[lsu.scala:459:29] wire mem_xcpt_uop_ppred_busy; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_stale_pdst; // @[lsu.scala:459:29] wire mem_xcpt_uop_exception; // @[lsu.scala:459:29] wire [63:0] mem_xcpt_uop_exc_cause; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_mem_cmd; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_mem_size; // @[lsu.scala:459:29] wire mem_xcpt_uop_mem_signed; // @[lsu.scala:459:29] wire mem_xcpt_uop_uses_ldq; // @[lsu.scala:459:29] wire mem_xcpt_uop_uses_stq; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_unique; // @[lsu.scala:459:29] wire mem_xcpt_uop_flush_on_commit; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_csr_cmd; // @[lsu.scala:459:29] wire mem_xcpt_uop_ldst_is_rs1; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_ldst; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_lrs1; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_lrs2; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_lrs3; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_dst_rtype; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_lrs1_rtype; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_lrs2_rtype; // @[lsu.scala:459:29] wire mem_xcpt_uop_frs3_en; // @[lsu.scala:459:29] wire mem_xcpt_uop_fcn_dw; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_fcn_op; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_val; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_fp_rm; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_fp_typ; // @[lsu.scala:459:29] wire mem_xcpt_uop_xcpt_pf_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_xcpt_ae_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_xcpt_ma_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_bp_debug_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_bp_xcpt_if; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_debug_fsrc; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_debug_tsrc; // @[lsu.scala:459:29] wire [63:0] mem_xcpt_vaddr; // @[lsu.scala:460:29] wire will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_agen_exec_0; // @[lsu.scala:469:39] wire will_fire_load_agen_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_agen_0; // @[lsu.scala:470:41] wire will_fire_store_agen_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_agen_0; // @[lsu.scala:471:41] wire will_fire_sfence_0_will_fire; // @[lsu.scala:657:65] wire will_fire_sfence_0; // @[lsu.scala:472:41] wire will_fire_hella_incoming_0_will_fire; // @[lsu.scala:657:65] wire will_fire_hella_incoming_0; // @[lsu.scala:473:41] wire _exe_passthr_T = will_fire_hella_incoming_0; // @[lsu.scala:473:41, :756:23] wire will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:657:65] wire will_fire_hella_wakeup_0; // @[lsu.scala:474:41] wire will_fire_release_0_will_fire; // @[lsu.scala:657:65] assign io_dmem_release_ready_0 = will_fire_release_0; // @[lsu.scala:211:7, :475:41] wire will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_retry_0; // @[lsu.scala:476:41] wire will_fire_store_retry_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_retry_0; // @[lsu.scala:477:41] wire will_fire_store_commit_fast_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_commit_fast_0; // @[lsu.scala:478:41] wire will_fire_store_commit_slow_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_commit_slow_0; // @[lsu.scala:479:41] wire will_fire_load_wakeup_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_wakeup_0; // @[lsu.scala:480:41] wire block_load_mask_0; // @[lsu.scala:488:36] wire block_load_mask_1; // @[lsu.scala:488:36] wire block_load_mask_2; // @[lsu.scala:488:36] wire block_load_mask_3; // @[lsu.scala:488:36] wire block_load_mask_4; // @[lsu.scala:488:36] wire block_load_mask_5; // @[lsu.scala:488:36] wire block_load_mask_6; // @[lsu.scala:488:36] wire block_load_mask_7; // @[lsu.scala:488:36] wire block_load_mask_8; // @[lsu.scala:488:36] wire block_load_mask_9; // @[lsu.scala:488:36] wire block_load_mask_10; // @[lsu.scala:488:36] wire block_load_mask_11; // @[lsu.scala:488:36] wire block_load_mask_12; // @[lsu.scala:488:36] wire block_load_mask_13; // @[lsu.scala:488:36] wire block_load_mask_14; // @[lsu.scala:488:36] wire block_load_mask_15; // @[lsu.scala:488:36] reg p1_block_load_mask_0; // @[lsu.scala:489:35] reg p1_block_load_mask_1; // @[lsu.scala:489:35] reg p1_block_load_mask_2; // @[lsu.scala:489:35] reg p1_block_load_mask_3; // @[lsu.scala:489:35] reg p1_block_load_mask_4; // @[lsu.scala:489:35] reg p1_block_load_mask_5; // @[lsu.scala:489:35] reg p1_block_load_mask_6; // @[lsu.scala:489:35] reg p1_block_load_mask_7; // @[lsu.scala:489:35] reg p1_block_load_mask_8; // @[lsu.scala:489:35] reg p1_block_load_mask_9; // @[lsu.scala:489:35] reg p1_block_load_mask_10; // @[lsu.scala:489:35] reg p1_block_load_mask_11; // @[lsu.scala:489:35] reg p1_block_load_mask_12; // @[lsu.scala:489:35] reg p1_block_load_mask_13; // @[lsu.scala:489:35] reg p1_block_load_mask_14; // @[lsu.scala:489:35] reg p1_block_load_mask_15; // @[lsu.scala:489:35] reg p2_block_load_mask_0; // @[lsu.scala:490:35] reg p2_block_load_mask_1; // @[lsu.scala:490:35] reg p2_block_load_mask_2; // @[lsu.scala:490:35] reg p2_block_load_mask_3; // @[lsu.scala:490:35] reg p2_block_load_mask_4; // @[lsu.scala:490:35] reg p2_block_load_mask_5; // @[lsu.scala:490:35] reg p2_block_load_mask_6; // @[lsu.scala:490:35] reg p2_block_load_mask_7; // @[lsu.scala:490:35] reg p2_block_load_mask_8; // @[lsu.scala:490:35] reg p2_block_load_mask_9; // @[lsu.scala:490:35] reg p2_block_load_mask_10; // @[lsu.scala:490:35] reg p2_block_load_mask_11; // @[lsu.scala:490:35] reg p2_block_load_mask_12; // @[lsu.scala:490:35] reg p2_block_load_mask_13; // @[lsu.scala:490:35] reg p2_block_load_mask_14; // @[lsu.scala:490:35] reg p2_block_load_mask_15; // @[lsu.scala:490:35] wire [4:0] _stq_tail_plus_T = {1'h0, stq_tail} + 5'h4; // @[util.scala:172:14, :211:14] wire [3:0] _stq_tail_plus_T_1 = _stq_tail_plus_T[3:0]; // @[util.scala:172:14] wire [3:0] stq_tail_plus = _stq_tail_plus_T_1; // @[util.scala:172:{14,20}] wire _stq_almost_full_T = stq_head < stq_tail_plus; // @[util.scala:172:20, :364:52] wire _stq_almost_full_T_1 = stq_head < stq_tail; // @[util.scala:364:64] wire _stq_almost_full_T_2 = _stq_almost_full_T ^ _stq_almost_full_T_1; // @[util.scala:364:{52,58,64}] wire _stq_almost_full_T_3 = stq_tail_plus < stq_tail; // @[util.scala:172:20, :364:78] wire _stq_almost_full_T_4 = _stq_almost_full_T_2 ^ _stq_almost_full_T_3; // @[util.scala:364:{58,72,78}] reg stq_almost_full; // @[lsu.scala:494:32] wire store_needs_order; // @[lsu.scala:498:35] wire _ldq_incoming_e_WIRE_valid = ldq_incoming_e_e_valid; // @[lsu.scala:233:17, :501:48] wire [31:0] _ldq_incoming_e_WIRE_bits_uop_inst = ldq_incoming_e_e_bits_uop_inst; // @[lsu.scala:233:17, :501:48] wire [31:0] _ldq_incoming_e_WIRE_bits_uop_debug_inst = ldq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_rvc = ldq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17, :501:48] wire [39:0] _ldq_incoming_e_WIRE_bits_uop_debug_pc = ldq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_0 = ldq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_1 = ldq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_2 = ldq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_3 = ldq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_0 = ldq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_1 = ldq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_2 = ldq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_3 = ldq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_4 = ldq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_5 = ldq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_6 = ldq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_7 = ldq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_8 = ldq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_9 = ldq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_issued = ldq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen = ldq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen = ldq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child = ldq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child = ldq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint = ldq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint = ldq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint = ldq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_dis_col_sel = ldq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17, :501:48] wire [11:0] _ldq_incoming_e_WIRE_bits_uop_br_mask = ldq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_uop_br_tag = ldq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_uop_br_type = ldq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_sfb = ldq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_fence = ldq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_fencei = ldq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_sfence = ldq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_amo = ldq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_eret = ldq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_sys_pc2epc = ldq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_rocc = ldq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_mov = ldq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_ftq_idx = ldq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_edge_inst = ldq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_pc_lob = ldq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_taken = ldq_incoming_e_e_bits_uop_taken; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_imm_rename = ldq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_imm_sel = ldq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_pimm = ldq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:233:17, :501:48] wire [19:0] _ldq_incoming_e_WIRE_bits_uop_imm_packed = ldq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_op1_sel = ldq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_op2_sel = ldq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst = ldq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wen = ldq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1 = ldq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2 = ldq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3 = ldq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12 = ldq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23 = ldq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn = ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut = ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint = ldq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_toint = ldq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe = ldq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fma = ldq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_div = ldq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt = ldq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags = ldq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_vec = ldq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_rob_idx = ldq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_uop_ldq_idx = ldq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_uop_stq_idx = ldq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_rxq_idx = ldq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_pdst = ldq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_prs1 = ldq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_prs2 = ldq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_prs3 = ldq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_ppred = ldq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_prs1_busy = ldq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_prs2_busy = ldq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_prs3_busy = ldq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_ppred_busy = ldq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_stale_pdst = ldq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_exception = ldq_incoming_e_e_bits_uop_exception; // @[lsu.scala:233:17, :501:48] wire [63:0] _ldq_incoming_e_WIRE_bits_uop_exc_cause = ldq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_mem_cmd = ldq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_mem_size = ldq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_mem_signed = ldq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_uses_ldq = ldq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_uses_stq = ldq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_unique = ldq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_flush_on_commit = ldq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_csr_cmd = ldq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_ldst_is_rs1 = ldq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_ldst = ldq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_lrs1 = ldq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_lrs2 = ldq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_lrs3 = ldq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_dst_rtype = ldq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_lrs1_rtype = ldq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_lrs2_rtype = ldq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_frs3_en = ldq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fcn_dw = ldq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_fcn_op = ldq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_val = ldq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_fp_rm = ldq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_fp_typ = ldq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_xcpt_pf_if = ldq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_xcpt_ae_if = ldq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_xcpt_ma_if = ldq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_bp_debug_if = ldq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_bp_xcpt_if = ldq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_debug_fsrc = ldq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_debug_tsrc = ldq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_addr_valid = ldq_incoming_e_e_bits_addr_valid; // @[lsu.scala:233:17, :501:48] wire [39:0] _ldq_incoming_e_WIRE_bits_addr_bits = ldq_incoming_e_e_bits_addr_bits; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_addr_is_virtual = ldq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_addr_is_uncacheable = ldq_incoming_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_executed = ldq_incoming_e_e_bits_executed; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_succeeded = ldq_incoming_e_e_bits_succeeded; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_order_fail = ldq_incoming_e_e_bits_order_fail; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_observed = ldq_incoming_e_e_bits_observed; // @[lsu.scala:233:17, :501:48] wire [15:0] _ldq_incoming_e_WIRE_bits_st_dep_mask = ldq_incoming_e_e_bits_st_dep_mask; // @[lsu.scala:233:17, :501:48] wire [7:0] _ldq_incoming_e_WIRE_bits_ld_byte_mask = ldq_incoming_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_forward_std_val = ldq_incoming_e_e_bits_forward_std_val; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_forward_stq_idx = ldq_incoming_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17, :501:48] wire [63:0] _ldq_incoming_e_WIRE_bits_debug_wb_data = ldq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:233:17, :501:48] assign ldq_incoming_e_e_valid = _GEN_25[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :234:32, :321:49, :387:15] wire [15:0][31:0] _GEN_76 = {{ldq_uop_15_inst}, {ldq_uop_14_inst}, {ldq_uop_13_inst}, {ldq_uop_12_inst}, {ldq_uop_11_inst}, {ldq_uop_10_inst}, {ldq_uop_9_inst}, {ldq_uop_8_inst}, {ldq_uop_7_inst}, {ldq_uop_6_inst}, {ldq_uop_5_inst}, {ldq_uop_4_inst}, {ldq_uop_3_inst}, {ldq_uop_2_inst}, {ldq_uop_1_inst}, {ldq_uop_0_inst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_inst = _GEN_76[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][31:0] _GEN_77 = {{ldq_uop_15_debug_inst}, {ldq_uop_14_debug_inst}, {ldq_uop_13_debug_inst}, {ldq_uop_12_debug_inst}, {ldq_uop_11_debug_inst}, {ldq_uop_10_debug_inst}, {ldq_uop_9_debug_inst}, {ldq_uop_8_debug_inst}, {ldq_uop_7_debug_inst}, {ldq_uop_6_debug_inst}, {ldq_uop_5_debug_inst}, {ldq_uop_4_debug_inst}, {ldq_uop_3_debug_inst}, {ldq_uop_2_debug_inst}, {ldq_uop_1_debug_inst}, {ldq_uop_0_debug_inst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_inst = _GEN_77[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_78 = {{ldq_uop_15_is_rvc}, {ldq_uop_14_is_rvc}, {ldq_uop_13_is_rvc}, {ldq_uop_12_is_rvc}, {ldq_uop_11_is_rvc}, {ldq_uop_10_is_rvc}, {ldq_uop_9_is_rvc}, {ldq_uop_8_is_rvc}, {ldq_uop_7_is_rvc}, {ldq_uop_6_is_rvc}, {ldq_uop_5_is_rvc}, {ldq_uop_4_is_rvc}, {ldq_uop_3_is_rvc}, {ldq_uop_2_is_rvc}, {ldq_uop_1_is_rvc}, {ldq_uop_0_is_rvc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_rvc = _GEN_78[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][39:0] _GEN_79 = {{ldq_uop_15_debug_pc}, {ldq_uop_14_debug_pc}, {ldq_uop_13_debug_pc}, {ldq_uop_12_debug_pc}, {ldq_uop_11_debug_pc}, {ldq_uop_10_debug_pc}, {ldq_uop_9_debug_pc}, {ldq_uop_8_debug_pc}, {ldq_uop_7_debug_pc}, {ldq_uop_6_debug_pc}, {ldq_uop_5_debug_pc}, {ldq_uop_4_debug_pc}, {ldq_uop_3_debug_pc}, {ldq_uop_2_debug_pc}, {ldq_uop_1_debug_pc}, {ldq_uop_0_debug_pc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_pc = _GEN_79[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_80 = {{ldq_uop_15_iq_type_0}, {ldq_uop_14_iq_type_0}, {ldq_uop_13_iq_type_0}, {ldq_uop_12_iq_type_0}, {ldq_uop_11_iq_type_0}, {ldq_uop_10_iq_type_0}, {ldq_uop_9_iq_type_0}, {ldq_uop_8_iq_type_0}, {ldq_uop_7_iq_type_0}, {ldq_uop_6_iq_type_0}, {ldq_uop_5_iq_type_0}, {ldq_uop_4_iq_type_0}, {ldq_uop_3_iq_type_0}, {ldq_uop_2_iq_type_0}, {ldq_uop_1_iq_type_0}, {ldq_uop_0_iq_type_0}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_0 = _GEN_80[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_81 = {{ldq_uop_15_iq_type_1}, {ldq_uop_14_iq_type_1}, {ldq_uop_13_iq_type_1}, {ldq_uop_12_iq_type_1}, {ldq_uop_11_iq_type_1}, {ldq_uop_10_iq_type_1}, {ldq_uop_9_iq_type_1}, {ldq_uop_8_iq_type_1}, {ldq_uop_7_iq_type_1}, {ldq_uop_6_iq_type_1}, {ldq_uop_5_iq_type_1}, {ldq_uop_4_iq_type_1}, {ldq_uop_3_iq_type_1}, {ldq_uop_2_iq_type_1}, {ldq_uop_1_iq_type_1}, {ldq_uop_0_iq_type_1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_1 = _GEN_81[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_82 = {{ldq_uop_15_iq_type_2}, {ldq_uop_14_iq_type_2}, {ldq_uop_13_iq_type_2}, {ldq_uop_12_iq_type_2}, {ldq_uop_11_iq_type_2}, {ldq_uop_10_iq_type_2}, {ldq_uop_9_iq_type_2}, {ldq_uop_8_iq_type_2}, {ldq_uop_7_iq_type_2}, {ldq_uop_6_iq_type_2}, {ldq_uop_5_iq_type_2}, {ldq_uop_4_iq_type_2}, {ldq_uop_3_iq_type_2}, {ldq_uop_2_iq_type_2}, {ldq_uop_1_iq_type_2}, {ldq_uop_0_iq_type_2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_2 = _GEN_82[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_83 = {{ldq_uop_15_iq_type_3}, {ldq_uop_14_iq_type_3}, {ldq_uop_13_iq_type_3}, {ldq_uop_12_iq_type_3}, {ldq_uop_11_iq_type_3}, {ldq_uop_10_iq_type_3}, {ldq_uop_9_iq_type_3}, {ldq_uop_8_iq_type_3}, {ldq_uop_7_iq_type_3}, {ldq_uop_6_iq_type_3}, {ldq_uop_5_iq_type_3}, {ldq_uop_4_iq_type_3}, {ldq_uop_3_iq_type_3}, {ldq_uop_2_iq_type_3}, {ldq_uop_1_iq_type_3}, {ldq_uop_0_iq_type_3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_3 = _GEN_83[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_84 = {{ldq_uop_15_fu_code_0}, {ldq_uop_14_fu_code_0}, {ldq_uop_13_fu_code_0}, {ldq_uop_12_fu_code_0}, {ldq_uop_11_fu_code_0}, {ldq_uop_10_fu_code_0}, {ldq_uop_9_fu_code_0}, {ldq_uop_8_fu_code_0}, {ldq_uop_7_fu_code_0}, {ldq_uop_6_fu_code_0}, {ldq_uop_5_fu_code_0}, {ldq_uop_4_fu_code_0}, {ldq_uop_3_fu_code_0}, {ldq_uop_2_fu_code_0}, {ldq_uop_1_fu_code_0}, {ldq_uop_0_fu_code_0}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_0 = _GEN_84[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_85 = {{ldq_uop_15_fu_code_1}, {ldq_uop_14_fu_code_1}, {ldq_uop_13_fu_code_1}, {ldq_uop_12_fu_code_1}, {ldq_uop_11_fu_code_1}, {ldq_uop_10_fu_code_1}, {ldq_uop_9_fu_code_1}, {ldq_uop_8_fu_code_1}, {ldq_uop_7_fu_code_1}, {ldq_uop_6_fu_code_1}, {ldq_uop_5_fu_code_1}, {ldq_uop_4_fu_code_1}, {ldq_uop_3_fu_code_1}, {ldq_uop_2_fu_code_1}, {ldq_uop_1_fu_code_1}, {ldq_uop_0_fu_code_1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_1 = _GEN_85[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_86 = {{ldq_uop_15_fu_code_2}, {ldq_uop_14_fu_code_2}, {ldq_uop_13_fu_code_2}, {ldq_uop_12_fu_code_2}, {ldq_uop_11_fu_code_2}, {ldq_uop_10_fu_code_2}, {ldq_uop_9_fu_code_2}, {ldq_uop_8_fu_code_2}, {ldq_uop_7_fu_code_2}, {ldq_uop_6_fu_code_2}, {ldq_uop_5_fu_code_2}, {ldq_uop_4_fu_code_2}, {ldq_uop_3_fu_code_2}, {ldq_uop_2_fu_code_2}, {ldq_uop_1_fu_code_2}, {ldq_uop_0_fu_code_2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_2 = _GEN_86[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_87 = {{ldq_uop_15_fu_code_3}, {ldq_uop_14_fu_code_3}, {ldq_uop_13_fu_code_3}, {ldq_uop_12_fu_code_3}, {ldq_uop_11_fu_code_3}, {ldq_uop_10_fu_code_3}, {ldq_uop_9_fu_code_3}, {ldq_uop_8_fu_code_3}, {ldq_uop_7_fu_code_3}, {ldq_uop_6_fu_code_3}, {ldq_uop_5_fu_code_3}, {ldq_uop_4_fu_code_3}, {ldq_uop_3_fu_code_3}, {ldq_uop_2_fu_code_3}, {ldq_uop_1_fu_code_3}, {ldq_uop_0_fu_code_3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_3 = _GEN_87[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_88 = {{ldq_uop_15_fu_code_4}, {ldq_uop_14_fu_code_4}, {ldq_uop_13_fu_code_4}, {ldq_uop_12_fu_code_4}, {ldq_uop_11_fu_code_4}, {ldq_uop_10_fu_code_4}, {ldq_uop_9_fu_code_4}, {ldq_uop_8_fu_code_4}, {ldq_uop_7_fu_code_4}, {ldq_uop_6_fu_code_4}, {ldq_uop_5_fu_code_4}, {ldq_uop_4_fu_code_4}, {ldq_uop_3_fu_code_4}, {ldq_uop_2_fu_code_4}, {ldq_uop_1_fu_code_4}, {ldq_uop_0_fu_code_4}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_4 = _GEN_88[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_89 = {{ldq_uop_15_fu_code_5}, {ldq_uop_14_fu_code_5}, {ldq_uop_13_fu_code_5}, {ldq_uop_12_fu_code_5}, {ldq_uop_11_fu_code_5}, {ldq_uop_10_fu_code_5}, {ldq_uop_9_fu_code_5}, {ldq_uop_8_fu_code_5}, {ldq_uop_7_fu_code_5}, {ldq_uop_6_fu_code_5}, {ldq_uop_5_fu_code_5}, {ldq_uop_4_fu_code_5}, {ldq_uop_3_fu_code_5}, {ldq_uop_2_fu_code_5}, {ldq_uop_1_fu_code_5}, {ldq_uop_0_fu_code_5}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_5 = _GEN_89[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_90 = {{ldq_uop_15_fu_code_6}, {ldq_uop_14_fu_code_6}, {ldq_uop_13_fu_code_6}, {ldq_uop_12_fu_code_6}, {ldq_uop_11_fu_code_6}, {ldq_uop_10_fu_code_6}, {ldq_uop_9_fu_code_6}, {ldq_uop_8_fu_code_6}, {ldq_uop_7_fu_code_6}, {ldq_uop_6_fu_code_6}, {ldq_uop_5_fu_code_6}, {ldq_uop_4_fu_code_6}, {ldq_uop_3_fu_code_6}, {ldq_uop_2_fu_code_6}, {ldq_uop_1_fu_code_6}, {ldq_uop_0_fu_code_6}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_6 = _GEN_90[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_91 = {{ldq_uop_15_fu_code_7}, {ldq_uop_14_fu_code_7}, {ldq_uop_13_fu_code_7}, {ldq_uop_12_fu_code_7}, {ldq_uop_11_fu_code_7}, {ldq_uop_10_fu_code_7}, {ldq_uop_9_fu_code_7}, {ldq_uop_8_fu_code_7}, {ldq_uop_7_fu_code_7}, {ldq_uop_6_fu_code_7}, {ldq_uop_5_fu_code_7}, {ldq_uop_4_fu_code_7}, {ldq_uop_3_fu_code_7}, {ldq_uop_2_fu_code_7}, {ldq_uop_1_fu_code_7}, {ldq_uop_0_fu_code_7}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_7 = _GEN_91[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_92 = {{ldq_uop_15_fu_code_8}, {ldq_uop_14_fu_code_8}, {ldq_uop_13_fu_code_8}, {ldq_uop_12_fu_code_8}, {ldq_uop_11_fu_code_8}, {ldq_uop_10_fu_code_8}, {ldq_uop_9_fu_code_8}, {ldq_uop_8_fu_code_8}, {ldq_uop_7_fu_code_8}, {ldq_uop_6_fu_code_8}, {ldq_uop_5_fu_code_8}, {ldq_uop_4_fu_code_8}, {ldq_uop_3_fu_code_8}, {ldq_uop_2_fu_code_8}, {ldq_uop_1_fu_code_8}, {ldq_uop_0_fu_code_8}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_8 = _GEN_92[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_93 = {{ldq_uop_15_fu_code_9}, {ldq_uop_14_fu_code_9}, {ldq_uop_13_fu_code_9}, {ldq_uop_12_fu_code_9}, {ldq_uop_11_fu_code_9}, {ldq_uop_10_fu_code_9}, {ldq_uop_9_fu_code_9}, {ldq_uop_8_fu_code_9}, {ldq_uop_7_fu_code_9}, {ldq_uop_6_fu_code_9}, {ldq_uop_5_fu_code_9}, {ldq_uop_4_fu_code_9}, {ldq_uop_3_fu_code_9}, {ldq_uop_2_fu_code_9}, {ldq_uop_1_fu_code_9}, {ldq_uop_0_fu_code_9}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_9 = _GEN_93[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_94 = {{ldq_uop_15_iw_issued}, {ldq_uop_14_iw_issued}, {ldq_uop_13_iw_issued}, {ldq_uop_12_iw_issued}, {ldq_uop_11_iw_issued}, {ldq_uop_10_iw_issued}, {ldq_uop_9_iw_issued}, {ldq_uop_8_iw_issued}, {ldq_uop_7_iw_issued}, {ldq_uop_6_iw_issued}, {ldq_uop_5_iw_issued}, {ldq_uop_4_iw_issued}, {ldq_uop_3_iw_issued}, {ldq_uop_2_iw_issued}, {ldq_uop_1_iw_issued}, {ldq_uop_0_iw_issued}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_issued = _GEN_94[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_95 = {{ldq_uop_15_iw_issued_partial_agen}, {ldq_uop_14_iw_issued_partial_agen}, {ldq_uop_13_iw_issued_partial_agen}, {ldq_uop_12_iw_issued_partial_agen}, {ldq_uop_11_iw_issued_partial_agen}, {ldq_uop_10_iw_issued_partial_agen}, {ldq_uop_9_iw_issued_partial_agen}, {ldq_uop_8_iw_issued_partial_agen}, {ldq_uop_7_iw_issued_partial_agen}, {ldq_uop_6_iw_issued_partial_agen}, {ldq_uop_5_iw_issued_partial_agen}, {ldq_uop_4_iw_issued_partial_agen}, {ldq_uop_3_iw_issued_partial_agen}, {ldq_uop_2_iw_issued_partial_agen}, {ldq_uop_1_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_issued_partial_agen = _GEN_95[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_96 = {{ldq_uop_15_iw_issued_partial_dgen}, {ldq_uop_14_iw_issued_partial_dgen}, {ldq_uop_13_iw_issued_partial_dgen}, {ldq_uop_12_iw_issued_partial_dgen}, {ldq_uop_11_iw_issued_partial_dgen}, {ldq_uop_10_iw_issued_partial_dgen}, {ldq_uop_9_iw_issued_partial_dgen}, {ldq_uop_8_iw_issued_partial_dgen}, {ldq_uop_7_iw_issued_partial_dgen}, {ldq_uop_6_iw_issued_partial_dgen}, {ldq_uop_5_iw_issued_partial_dgen}, {ldq_uop_4_iw_issued_partial_dgen}, {ldq_uop_3_iw_issued_partial_dgen}, {ldq_uop_2_iw_issued_partial_dgen}, {ldq_uop_1_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_issued_partial_dgen = _GEN_96[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_97 = {{ldq_uop_15_iw_p1_speculative_child}, {ldq_uop_14_iw_p1_speculative_child}, {ldq_uop_13_iw_p1_speculative_child}, {ldq_uop_12_iw_p1_speculative_child}, {ldq_uop_11_iw_p1_speculative_child}, {ldq_uop_10_iw_p1_speculative_child}, {ldq_uop_9_iw_p1_speculative_child}, {ldq_uop_8_iw_p1_speculative_child}, {ldq_uop_7_iw_p1_speculative_child}, {ldq_uop_6_iw_p1_speculative_child}, {ldq_uop_5_iw_p1_speculative_child}, {ldq_uop_4_iw_p1_speculative_child}, {ldq_uop_3_iw_p1_speculative_child}, {ldq_uop_2_iw_p1_speculative_child}, {ldq_uop_1_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p1_speculative_child = _GEN_97[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_98 = {{ldq_uop_15_iw_p2_speculative_child}, {ldq_uop_14_iw_p2_speculative_child}, {ldq_uop_13_iw_p2_speculative_child}, {ldq_uop_12_iw_p2_speculative_child}, {ldq_uop_11_iw_p2_speculative_child}, {ldq_uop_10_iw_p2_speculative_child}, {ldq_uop_9_iw_p2_speculative_child}, {ldq_uop_8_iw_p2_speculative_child}, {ldq_uop_7_iw_p2_speculative_child}, {ldq_uop_6_iw_p2_speculative_child}, {ldq_uop_5_iw_p2_speculative_child}, {ldq_uop_4_iw_p2_speculative_child}, {ldq_uop_3_iw_p2_speculative_child}, {ldq_uop_2_iw_p2_speculative_child}, {ldq_uop_1_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p2_speculative_child = _GEN_98[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_99 = {{ldq_uop_15_iw_p1_bypass_hint}, {ldq_uop_14_iw_p1_bypass_hint}, {ldq_uop_13_iw_p1_bypass_hint}, {ldq_uop_12_iw_p1_bypass_hint}, {ldq_uop_11_iw_p1_bypass_hint}, {ldq_uop_10_iw_p1_bypass_hint}, {ldq_uop_9_iw_p1_bypass_hint}, {ldq_uop_8_iw_p1_bypass_hint}, {ldq_uop_7_iw_p1_bypass_hint}, {ldq_uop_6_iw_p1_bypass_hint}, {ldq_uop_5_iw_p1_bypass_hint}, {ldq_uop_4_iw_p1_bypass_hint}, {ldq_uop_3_iw_p1_bypass_hint}, {ldq_uop_2_iw_p1_bypass_hint}, {ldq_uop_1_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p1_bypass_hint = _GEN_99[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_100 = {{ldq_uop_15_iw_p2_bypass_hint}, {ldq_uop_14_iw_p2_bypass_hint}, {ldq_uop_13_iw_p2_bypass_hint}, {ldq_uop_12_iw_p2_bypass_hint}, {ldq_uop_11_iw_p2_bypass_hint}, {ldq_uop_10_iw_p2_bypass_hint}, {ldq_uop_9_iw_p2_bypass_hint}, {ldq_uop_8_iw_p2_bypass_hint}, {ldq_uop_7_iw_p2_bypass_hint}, {ldq_uop_6_iw_p2_bypass_hint}, {ldq_uop_5_iw_p2_bypass_hint}, {ldq_uop_4_iw_p2_bypass_hint}, {ldq_uop_3_iw_p2_bypass_hint}, {ldq_uop_2_iw_p2_bypass_hint}, {ldq_uop_1_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p2_bypass_hint = _GEN_100[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_101 = {{ldq_uop_15_iw_p3_bypass_hint}, {ldq_uop_14_iw_p3_bypass_hint}, {ldq_uop_13_iw_p3_bypass_hint}, {ldq_uop_12_iw_p3_bypass_hint}, {ldq_uop_11_iw_p3_bypass_hint}, {ldq_uop_10_iw_p3_bypass_hint}, {ldq_uop_9_iw_p3_bypass_hint}, {ldq_uop_8_iw_p3_bypass_hint}, {ldq_uop_7_iw_p3_bypass_hint}, {ldq_uop_6_iw_p3_bypass_hint}, {ldq_uop_5_iw_p3_bypass_hint}, {ldq_uop_4_iw_p3_bypass_hint}, {ldq_uop_3_iw_p3_bypass_hint}, {ldq_uop_2_iw_p3_bypass_hint}, {ldq_uop_1_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p3_bypass_hint = _GEN_101[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_102 = {{ldq_uop_15_dis_col_sel}, {ldq_uop_14_dis_col_sel}, {ldq_uop_13_dis_col_sel}, {ldq_uop_12_dis_col_sel}, {ldq_uop_11_dis_col_sel}, {ldq_uop_10_dis_col_sel}, {ldq_uop_9_dis_col_sel}, {ldq_uop_8_dis_col_sel}, {ldq_uop_7_dis_col_sel}, {ldq_uop_6_dis_col_sel}, {ldq_uop_5_dis_col_sel}, {ldq_uop_4_dis_col_sel}, {ldq_uop_3_dis_col_sel}, {ldq_uop_2_dis_col_sel}, {ldq_uop_1_dis_col_sel}, {ldq_uop_0_dis_col_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_dis_col_sel = _GEN_102[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][11:0] _GEN_103 = {{ldq_uop_15_br_mask}, {ldq_uop_14_br_mask}, {ldq_uop_13_br_mask}, {ldq_uop_12_br_mask}, {ldq_uop_11_br_mask}, {ldq_uop_10_br_mask}, {ldq_uop_9_br_mask}, {ldq_uop_8_br_mask}, {ldq_uop_7_br_mask}, {ldq_uop_6_br_mask}, {ldq_uop_5_br_mask}, {ldq_uop_4_br_mask}, {ldq_uop_3_br_mask}, {ldq_uop_2_br_mask}, {ldq_uop_1_br_mask}, {ldq_uop_0_br_mask}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_br_mask = _GEN_103[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][3:0] _GEN_104 = {{ldq_uop_15_br_tag}, {ldq_uop_14_br_tag}, {ldq_uop_13_br_tag}, {ldq_uop_12_br_tag}, {ldq_uop_11_br_tag}, {ldq_uop_10_br_tag}, {ldq_uop_9_br_tag}, {ldq_uop_8_br_tag}, {ldq_uop_7_br_tag}, {ldq_uop_6_br_tag}, {ldq_uop_5_br_tag}, {ldq_uop_4_br_tag}, {ldq_uop_3_br_tag}, {ldq_uop_2_br_tag}, {ldq_uop_1_br_tag}, {ldq_uop_0_br_tag}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_br_tag = _GEN_104[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][3:0] _GEN_105 = {{ldq_uop_15_br_type}, {ldq_uop_14_br_type}, {ldq_uop_13_br_type}, {ldq_uop_12_br_type}, {ldq_uop_11_br_type}, {ldq_uop_10_br_type}, {ldq_uop_9_br_type}, {ldq_uop_8_br_type}, {ldq_uop_7_br_type}, {ldq_uop_6_br_type}, {ldq_uop_5_br_type}, {ldq_uop_4_br_type}, {ldq_uop_3_br_type}, {ldq_uop_2_br_type}, {ldq_uop_1_br_type}, {ldq_uop_0_br_type}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_br_type = _GEN_105[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_106 = {{ldq_uop_15_is_sfb}, {ldq_uop_14_is_sfb}, {ldq_uop_13_is_sfb}, {ldq_uop_12_is_sfb}, {ldq_uop_11_is_sfb}, {ldq_uop_10_is_sfb}, {ldq_uop_9_is_sfb}, {ldq_uop_8_is_sfb}, {ldq_uop_7_is_sfb}, {ldq_uop_6_is_sfb}, {ldq_uop_5_is_sfb}, {ldq_uop_4_is_sfb}, {ldq_uop_3_is_sfb}, {ldq_uop_2_is_sfb}, {ldq_uop_1_is_sfb}, {ldq_uop_0_is_sfb}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_sfb = _GEN_106[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_107 = {{ldq_uop_15_is_fence}, {ldq_uop_14_is_fence}, {ldq_uop_13_is_fence}, {ldq_uop_12_is_fence}, {ldq_uop_11_is_fence}, {ldq_uop_10_is_fence}, {ldq_uop_9_is_fence}, {ldq_uop_8_is_fence}, {ldq_uop_7_is_fence}, {ldq_uop_6_is_fence}, {ldq_uop_5_is_fence}, {ldq_uop_4_is_fence}, {ldq_uop_3_is_fence}, {ldq_uop_2_is_fence}, {ldq_uop_1_is_fence}, {ldq_uop_0_is_fence}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_fence = _GEN_107[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_108 = {{ldq_uop_15_is_fencei}, {ldq_uop_14_is_fencei}, {ldq_uop_13_is_fencei}, {ldq_uop_12_is_fencei}, {ldq_uop_11_is_fencei}, {ldq_uop_10_is_fencei}, {ldq_uop_9_is_fencei}, {ldq_uop_8_is_fencei}, {ldq_uop_7_is_fencei}, {ldq_uop_6_is_fencei}, {ldq_uop_5_is_fencei}, {ldq_uop_4_is_fencei}, {ldq_uop_3_is_fencei}, {ldq_uop_2_is_fencei}, {ldq_uop_1_is_fencei}, {ldq_uop_0_is_fencei}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_fencei = _GEN_108[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_109 = {{ldq_uop_15_is_sfence}, {ldq_uop_14_is_sfence}, {ldq_uop_13_is_sfence}, {ldq_uop_12_is_sfence}, {ldq_uop_11_is_sfence}, {ldq_uop_10_is_sfence}, {ldq_uop_9_is_sfence}, {ldq_uop_8_is_sfence}, {ldq_uop_7_is_sfence}, {ldq_uop_6_is_sfence}, {ldq_uop_5_is_sfence}, {ldq_uop_4_is_sfence}, {ldq_uop_3_is_sfence}, {ldq_uop_2_is_sfence}, {ldq_uop_1_is_sfence}, {ldq_uop_0_is_sfence}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_sfence = _GEN_109[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_110 = {{ldq_uop_15_is_amo}, {ldq_uop_14_is_amo}, {ldq_uop_13_is_amo}, {ldq_uop_12_is_amo}, {ldq_uop_11_is_amo}, {ldq_uop_10_is_amo}, {ldq_uop_9_is_amo}, {ldq_uop_8_is_amo}, {ldq_uop_7_is_amo}, {ldq_uop_6_is_amo}, {ldq_uop_5_is_amo}, {ldq_uop_4_is_amo}, {ldq_uop_3_is_amo}, {ldq_uop_2_is_amo}, {ldq_uop_1_is_amo}, {ldq_uop_0_is_amo}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_amo = _GEN_110[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_111 = {{ldq_uop_15_is_eret}, {ldq_uop_14_is_eret}, {ldq_uop_13_is_eret}, {ldq_uop_12_is_eret}, {ldq_uop_11_is_eret}, {ldq_uop_10_is_eret}, {ldq_uop_9_is_eret}, {ldq_uop_8_is_eret}, {ldq_uop_7_is_eret}, {ldq_uop_6_is_eret}, {ldq_uop_5_is_eret}, {ldq_uop_4_is_eret}, {ldq_uop_3_is_eret}, {ldq_uop_2_is_eret}, {ldq_uop_1_is_eret}, {ldq_uop_0_is_eret}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_eret = _GEN_111[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_112 = {{ldq_uop_15_is_sys_pc2epc}, {ldq_uop_14_is_sys_pc2epc}, {ldq_uop_13_is_sys_pc2epc}, {ldq_uop_12_is_sys_pc2epc}, {ldq_uop_11_is_sys_pc2epc}, {ldq_uop_10_is_sys_pc2epc}, {ldq_uop_9_is_sys_pc2epc}, {ldq_uop_8_is_sys_pc2epc}, {ldq_uop_7_is_sys_pc2epc}, {ldq_uop_6_is_sys_pc2epc}, {ldq_uop_5_is_sys_pc2epc}, {ldq_uop_4_is_sys_pc2epc}, {ldq_uop_3_is_sys_pc2epc}, {ldq_uop_2_is_sys_pc2epc}, {ldq_uop_1_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_sys_pc2epc = _GEN_112[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_113 = {{ldq_uop_15_is_rocc}, {ldq_uop_14_is_rocc}, {ldq_uop_13_is_rocc}, {ldq_uop_12_is_rocc}, {ldq_uop_11_is_rocc}, {ldq_uop_10_is_rocc}, {ldq_uop_9_is_rocc}, {ldq_uop_8_is_rocc}, {ldq_uop_7_is_rocc}, {ldq_uop_6_is_rocc}, {ldq_uop_5_is_rocc}, {ldq_uop_4_is_rocc}, {ldq_uop_3_is_rocc}, {ldq_uop_2_is_rocc}, {ldq_uop_1_is_rocc}, {ldq_uop_0_is_rocc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_rocc = _GEN_113[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_114 = {{ldq_uop_15_is_mov}, {ldq_uop_14_is_mov}, {ldq_uop_13_is_mov}, {ldq_uop_12_is_mov}, {ldq_uop_11_is_mov}, {ldq_uop_10_is_mov}, {ldq_uop_9_is_mov}, {ldq_uop_8_is_mov}, {ldq_uop_7_is_mov}, {ldq_uop_6_is_mov}, {ldq_uop_5_is_mov}, {ldq_uop_4_is_mov}, {ldq_uop_3_is_mov}, {ldq_uop_2_is_mov}, {ldq_uop_1_is_mov}, {ldq_uop_0_is_mov}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_mov = _GEN_114[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][4:0] _GEN_115 = {{ldq_uop_15_ftq_idx}, {ldq_uop_14_ftq_idx}, {ldq_uop_13_ftq_idx}, {ldq_uop_12_ftq_idx}, {ldq_uop_11_ftq_idx}, {ldq_uop_10_ftq_idx}, {ldq_uop_9_ftq_idx}, {ldq_uop_8_ftq_idx}, {ldq_uop_7_ftq_idx}, {ldq_uop_6_ftq_idx}, {ldq_uop_5_ftq_idx}, {ldq_uop_4_ftq_idx}, {ldq_uop_3_ftq_idx}, {ldq_uop_2_ftq_idx}, {ldq_uop_1_ftq_idx}, {ldq_uop_0_ftq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ftq_idx = _GEN_115[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_116 = {{ldq_uop_15_edge_inst}, {ldq_uop_14_edge_inst}, {ldq_uop_13_edge_inst}, {ldq_uop_12_edge_inst}, {ldq_uop_11_edge_inst}, {ldq_uop_10_edge_inst}, {ldq_uop_9_edge_inst}, {ldq_uop_8_edge_inst}, {ldq_uop_7_edge_inst}, {ldq_uop_6_edge_inst}, {ldq_uop_5_edge_inst}, {ldq_uop_4_edge_inst}, {ldq_uop_3_edge_inst}, {ldq_uop_2_edge_inst}, {ldq_uop_1_edge_inst}, {ldq_uop_0_edge_inst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_edge_inst = _GEN_116[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][5:0] _GEN_117 = {{ldq_uop_15_pc_lob}, {ldq_uop_14_pc_lob}, {ldq_uop_13_pc_lob}, {ldq_uop_12_pc_lob}, {ldq_uop_11_pc_lob}, {ldq_uop_10_pc_lob}, {ldq_uop_9_pc_lob}, {ldq_uop_8_pc_lob}, {ldq_uop_7_pc_lob}, {ldq_uop_6_pc_lob}, {ldq_uop_5_pc_lob}, {ldq_uop_4_pc_lob}, {ldq_uop_3_pc_lob}, {ldq_uop_2_pc_lob}, {ldq_uop_1_pc_lob}, {ldq_uop_0_pc_lob}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_pc_lob = _GEN_117[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_118 = {{ldq_uop_15_taken}, {ldq_uop_14_taken}, {ldq_uop_13_taken}, {ldq_uop_12_taken}, {ldq_uop_11_taken}, {ldq_uop_10_taken}, {ldq_uop_9_taken}, {ldq_uop_8_taken}, {ldq_uop_7_taken}, {ldq_uop_6_taken}, {ldq_uop_5_taken}, {ldq_uop_4_taken}, {ldq_uop_3_taken}, {ldq_uop_2_taken}, {ldq_uop_1_taken}, {ldq_uop_0_taken}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_taken = _GEN_118[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_119 = {{ldq_uop_15_imm_rename}, {ldq_uop_14_imm_rename}, {ldq_uop_13_imm_rename}, {ldq_uop_12_imm_rename}, {ldq_uop_11_imm_rename}, {ldq_uop_10_imm_rename}, {ldq_uop_9_imm_rename}, {ldq_uop_8_imm_rename}, {ldq_uop_7_imm_rename}, {ldq_uop_6_imm_rename}, {ldq_uop_5_imm_rename}, {ldq_uop_4_imm_rename}, {ldq_uop_3_imm_rename}, {ldq_uop_2_imm_rename}, {ldq_uop_1_imm_rename}, {ldq_uop_0_imm_rename}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_imm_rename = _GEN_119[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][2:0] _GEN_120 = {{ldq_uop_15_imm_sel}, {ldq_uop_14_imm_sel}, {ldq_uop_13_imm_sel}, {ldq_uop_12_imm_sel}, {ldq_uop_11_imm_sel}, {ldq_uop_10_imm_sel}, {ldq_uop_9_imm_sel}, {ldq_uop_8_imm_sel}, {ldq_uop_7_imm_sel}, {ldq_uop_6_imm_sel}, {ldq_uop_5_imm_sel}, {ldq_uop_4_imm_sel}, {ldq_uop_3_imm_sel}, {ldq_uop_2_imm_sel}, {ldq_uop_1_imm_sel}, {ldq_uop_0_imm_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_imm_sel = _GEN_120[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][4:0] _GEN_121 = {{ldq_uop_15_pimm}, {ldq_uop_14_pimm}, {ldq_uop_13_pimm}, {ldq_uop_12_pimm}, {ldq_uop_11_pimm}, {ldq_uop_10_pimm}, {ldq_uop_9_pimm}, {ldq_uop_8_pimm}, {ldq_uop_7_pimm}, {ldq_uop_6_pimm}, {ldq_uop_5_pimm}, {ldq_uop_4_pimm}, {ldq_uop_3_pimm}, {ldq_uop_2_pimm}, {ldq_uop_1_pimm}, {ldq_uop_0_pimm}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_pimm = _GEN_121[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][19:0] _GEN_122 = {{ldq_uop_15_imm_packed}, {ldq_uop_14_imm_packed}, {ldq_uop_13_imm_packed}, {ldq_uop_12_imm_packed}, {ldq_uop_11_imm_packed}, {ldq_uop_10_imm_packed}, {ldq_uop_9_imm_packed}, {ldq_uop_8_imm_packed}, {ldq_uop_7_imm_packed}, {ldq_uop_6_imm_packed}, {ldq_uop_5_imm_packed}, {ldq_uop_4_imm_packed}, {ldq_uop_3_imm_packed}, {ldq_uop_2_imm_packed}, {ldq_uop_1_imm_packed}, {ldq_uop_0_imm_packed}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_imm_packed = _GEN_122[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_123 = {{ldq_uop_15_op1_sel}, {ldq_uop_14_op1_sel}, {ldq_uop_13_op1_sel}, {ldq_uop_12_op1_sel}, {ldq_uop_11_op1_sel}, {ldq_uop_10_op1_sel}, {ldq_uop_9_op1_sel}, {ldq_uop_8_op1_sel}, {ldq_uop_7_op1_sel}, {ldq_uop_6_op1_sel}, {ldq_uop_5_op1_sel}, {ldq_uop_4_op1_sel}, {ldq_uop_3_op1_sel}, {ldq_uop_2_op1_sel}, {ldq_uop_1_op1_sel}, {ldq_uop_0_op1_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_op1_sel = _GEN_123[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][2:0] _GEN_124 = {{ldq_uop_15_op2_sel}, {ldq_uop_14_op2_sel}, {ldq_uop_13_op2_sel}, {ldq_uop_12_op2_sel}, {ldq_uop_11_op2_sel}, {ldq_uop_10_op2_sel}, {ldq_uop_9_op2_sel}, {ldq_uop_8_op2_sel}, {ldq_uop_7_op2_sel}, {ldq_uop_6_op2_sel}, {ldq_uop_5_op2_sel}, {ldq_uop_4_op2_sel}, {ldq_uop_3_op2_sel}, {ldq_uop_2_op2_sel}, {ldq_uop_1_op2_sel}, {ldq_uop_0_op2_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_op2_sel = _GEN_124[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_125 = {{ldq_uop_15_fp_ctrl_ldst}, {ldq_uop_14_fp_ctrl_ldst}, {ldq_uop_13_fp_ctrl_ldst}, {ldq_uop_12_fp_ctrl_ldst}, {ldq_uop_11_fp_ctrl_ldst}, {ldq_uop_10_fp_ctrl_ldst}, {ldq_uop_9_fp_ctrl_ldst}, {ldq_uop_8_fp_ctrl_ldst}, {ldq_uop_7_fp_ctrl_ldst}, {ldq_uop_6_fp_ctrl_ldst}, {ldq_uop_5_fp_ctrl_ldst}, {ldq_uop_4_fp_ctrl_ldst}, {ldq_uop_3_fp_ctrl_ldst}, {ldq_uop_2_fp_ctrl_ldst}, {ldq_uop_1_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ldst = _GEN_125[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_126 = {{ldq_uop_15_fp_ctrl_wen}, {ldq_uop_14_fp_ctrl_wen}, {ldq_uop_13_fp_ctrl_wen}, {ldq_uop_12_fp_ctrl_wen}, {ldq_uop_11_fp_ctrl_wen}, {ldq_uop_10_fp_ctrl_wen}, {ldq_uop_9_fp_ctrl_wen}, {ldq_uop_8_fp_ctrl_wen}, {ldq_uop_7_fp_ctrl_wen}, {ldq_uop_6_fp_ctrl_wen}, {ldq_uop_5_fp_ctrl_wen}, {ldq_uop_4_fp_ctrl_wen}, {ldq_uop_3_fp_ctrl_wen}, {ldq_uop_2_fp_ctrl_wen}, {ldq_uop_1_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_wen = _GEN_126[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_127 = {{ldq_uop_15_fp_ctrl_ren1}, {ldq_uop_14_fp_ctrl_ren1}, {ldq_uop_13_fp_ctrl_ren1}, {ldq_uop_12_fp_ctrl_ren1}, {ldq_uop_11_fp_ctrl_ren1}, {ldq_uop_10_fp_ctrl_ren1}, {ldq_uop_9_fp_ctrl_ren1}, {ldq_uop_8_fp_ctrl_ren1}, {ldq_uop_7_fp_ctrl_ren1}, {ldq_uop_6_fp_ctrl_ren1}, {ldq_uop_5_fp_ctrl_ren1}, {ldq_uop_4_fp_ctrl_ren1}, {ldq_uop_3_fp_ctrl_ren1}, {ldq_uop_2_fp_ctrl_ren1}, {ldq_uop_1_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ren1 = _GEN_127[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_128 = {{ldq_uop_15_fp_ctrl_ren2}, {ldq_uop_14_fp_ctrl_ren2}, {ldq_uop_13_fp_ctrl_ren2}, {ldq_uop_12_fp_ctrl_ren2}, {ldq_uop_11_fp_ctrl_ren2}, {ldq_uop_10_fp_ctrl_ren2}, {ldq_uop_9_fp_ctrl_ren2}, {ldq_uop_8_fp_ctrl_ren2}, {ldq_uop_7_fp_ctrl_ren2}, {ldq_uop_6_fp_ctrl_ren2}, {ldq_uop_5_fp_ctrl_ren2}, {ldq_uop_4_fp_ctrl_ren2}, {ldq_uop_3_fp_ctrl_ren2}, {ldq_uop_2_fp_ctrl_ren2}, {ldq_uop_1_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ren2 = _GEN_128[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_129 = {{ldq_uop_15_fp_ctrl_ren3}, {ldq_uop_14_fp_ctrl_ren3}, {ldq_uop_13_fp_ctrl_ren3}, {ldq_uop_12_fp_ctrl_ren3}, {ldq_uop_11_fp_ctrl_ren3}, {ldq_uop_10_fp_ctrl_ren3}, {ldq_uop_9_fp_ctrl_ren3}, {ldq_uop_8_fp_ctrl_ren3}, {ldq_uop_7_fp_ctrl_ren3}, {ldq_uop_6_fp_ctrl_ren3}, {ldq_uop_5_fp_ctrl_ren3}, {ldq_uop_4_fp_ctrl_ren3}, {ldq_uop_3_fp_ctrl_ren3}, {ldq_uop_2_fp_ctrl_ren3}, {ldq_uop_1_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ren3 = _GEN_129[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_130 = {{ldq_uop_15_fp_ctrl_swap12}, {ldq_uop_14_fp_ctrl_swap12}, {ldq_uop_13_fp_ctrl_swap12}, {ldq_uop_12_fp_ctrl_swap12}, {ldq_uop_11_fp_ctrl_swap12}, {ldq_uop_10_fp_ctrl_swap12}, {ldq_uop_9_fp_ctrl_swap12}, {ldq_uop_8_fp_ctrl_swap12}, {ldq_uop_7_fp_ctrl_swap12}, {ldq_uop_6_fp_ctrl_swap12}, {ldq_uop_5_fp_ctrl_swap12}, {ldq_uop_4_fp_ctrl_swap12}, {ldq_uop_3_fp_ctrl_swap12}, {ldq_uop_2_fp_ctrl_swap12}, {ldq_uop_1_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_swap12 = _GEN_130[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_131 = {{ldq_uop_15_fp_ctrl_swap23}, {ldq_uop_14_fp_ctrl_swap23}, {ldq_uop_13_fp_ctrl_swap23}, {ldq_uop_12_fp_ctrl_swap23}, {ldq_uop_11_fp_ctrl_swap23}, {ldq_uop_10_fp_ctrl_swap23}, {ldq_uop_9_fp_ctrl_swap23}, {ldq_uop_8_fp_ctrl_swap23}, {ldq_uop_7_fp_ctrl_swap23}, {ldq_uop_6_fp_ctrl_swap23}, {ldq_uop_5_fp_ctrl_swap23}, {ldq_uop_4_fp_ctrl_swap23}, {ldq_uop_3_fp_ctrl_swap23}, {ldq_uop_2_fp_ctrl_swap23}, {ldq_uop_1_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_swap23 = _GEN_131[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_132 = {{ldq_uop_15_fp_ctrl_typeTagIn}, {ldq_uop_14_fp_ctrl_typeTagIn}, {ldq_uop_13_fp_ctrl_typeTagIn}, {ldq_uop_12_fp_ctrl_typeTagIn}, {ldq_uop_11_fp_ctrl_typeTagIn}, {ldq_uop_10_fp_ctrl_typeTagIn}, {ldq_uop_9_fp_ctrl_typeTagIn}, {ldq_uop_8_fp_ctrl_typeTagIn}, {ldq_uop_7_fp_ctrl_typeTagIn}, {ldq_uop_6_fp_ctrl_typeTagIn}, {ldq_uop_5_fp_ctrl_typeTagIn}, {ldq_uop_4_fp_ctrl_typeTagIn}, {ldq_uop_3_fp_ctrl_typeTagIn}, {ldq_uop_2_fp_ctrl_typeTagIn}, {ldq_uop_1_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_132[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_133 = {{ldq_uop_15_fp_ctrl_typeTagOut}, {ldq_uop_14_fp_ctrl_typeTagOut}, {ldq_uop_13_fp_ctrl_typeTagOut}, {ldq_uop_12_fp_ctrl_typeTagOut}, {ldq_uop_11_fp_ctrl_typeTagOut}, {ldq_uop_10_fp_ctrl_typeTagOut}, {ldq_uop_9_fp_ctrl_typeTagOut}, {ldq_uop_8_fp_ctrl_typeTagOut}, {ldq_uop_7_fp_ctrl_typeTagOut}, {ldq_uop_6_fp_ctrl_typeTagOut}, {ldq_uop_5_fp_ctrl_typeTagOut}, {ldq_uop_4_fp_ctrl_typeTagOut}, {ldq_uop_3_fp_ctrl_typeTagOut}, {ldq_uop_2_fp_ctrl_typeTagOut}, {ldq_uop_1_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_133[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_134 = {{ldq_uop_15_fp_ctrl_fromint}, {ldq_uop_14_fp_ctrl_fromint}, {ldq_uop_13_fp_ctrl_fromint}, {ldq_uop_12_fp_ctrl_fromint}, {ldq_uop_11_fp_ctrl_fromint}, {ldq_uop_10_fp_ctrl_fromint}, {ldq_uop_9_fp_ctrl_fromint}, {ldq_uop_8_fp_ctrl_fromint}, {ldq_uop_7_fp_ctrl_fromint}, {ldq_uop_6_fp_ctrl_fromint}, {ldq_uop_5_fp_ctrl_fromint}, {ldq_uop_4_fp_ctrl_fromint}, {ldq_uop_3_fp_ctrl_fromint}, {ldq_uop_2_fp_ctrl_fromint}, {ldq_uop_1_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_fromint = _GEN_134[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_135 = {{ldq_uop_15_fp_ctrl_toint}, {ldq_uop_14_fp_ctrl_toint}, {ldq_uop_13_fp_ctrl_toint}, {ldq_uop_12_fp_ctrl_toint}, {ldq_uop_11_fp_ctrl_toint}, {ldq_uop_10_fp_ctrl_toint}, {ldq_uop_9_fp_ctrl_toint}, {ldq_uop_8_fp_ctrl_toint}, {ldq_uop_7_fp_ctrl_toint}, {ldq_uop_6_fp_ctrl_toint}, {ldq_uop_5_fp_ctrl_toint}, {ldq_uop_4_fp_ctrl_toint}, {ldq_uop_3_fp_ctrl_toint}, {ldq_uop_2_fp_ctrl_toint}, {ldq_uop_1_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_toint = _GEN_135[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_136 = {{ldq_uop_15_fp_ctrl_fastpipe}, {ldq_uop_14_fp_ctrl_fastpipe}, {ldq_uop_13_fp_ctrl_fastpipe}, {ldq_uop_12_fp_ctrl_fastpipe}, {ldq_uop_11_fp_ctrl_fastpipe}, {ldq_uop_10_fp_ctrl_fastpipe}, {ldq_uop_9_fp_ctrl_fastpipe}, {ldq_uop_8_fp_ctrl_fastpipe}, {ldq_uop_7_fp_ctrl_fastpipe}, {ldq_uop_6_fp_ctrl_fastpipe}, {ldq_uop_5_fp_ctrl_fastpipe}, {ldq_uop_4_fp_ctrl_fastpipe}, {ldq_uop_3_fp_ctrl_fastpipe}, {ldq_uop_2_fp_ctrl_fastpipe}, {ldq_uop_1_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_136[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_137 = {{ldq_uop_15_fp_ctrl_fma}, {ldq_uop_14_fp_ctrl_fma}, {ldq_uop_13_fp_ctrl_fma}, {ldq_uop_12_fp_ctrl_fma}, {ldq_uop_11_fp_ctrl_fma}, {ldq_uop_10_fp_ctrl_fma}, {ldq_uop_9_fp_ctrl_fma}, {ldq_uop_8_fp_ctrl_fma}, {ldq_uop_7_fp_ctrl_fma}, {ldq_uop_6_fp_ctrl_fma}, {ldq_uop_5_fp_ctrl_fma}, {ldq_uop_4_fp_ctrl_fma}, {ldq_uop_3_fp_ctrl_fma}, {ldq_uop_2_fp_ctrl_fma}, {ldq_uop_1_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_fma = _GEN_137[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_138 = {{ldq_uop_15_fp_ctrl_div}, {ldq_uop_14_fp_ctrl_div}, {ldq_uop_13_fp_ctrl_div}, {ldq_uop_12_fp_ctrl_div}, {ldq_uop_11_fp_ctrl_div}, {ldq_uop_10_fp_ctrl_div}, {ldq_uop_9_fp_ctrl_div}, {ldq_uop_8_fp_ctrl_div}, {ldq_uop_7_fp_ctrl_div}, {ldq_uop_6_fp_ctrl_div}, {ldq_uop_5_fp_ctrl_div}, {ldq_uop_4_fp_ctrl_div}, {ldq_uop_3_fp_ctrl_div}, {ldq_uop_2_fp_ctrl_div}, {ldq_uop_1_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_div = _GEN_138[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_139 = {{ldq_uop_15_fp_ctrl_sqrt}, {ldq_uop_14_fp_ctrl_sqrt}, {ldq_uop_13_fp_ctrl_sqrt}, {ldq_uop_12_fp_ctrl_sqrt}, {ldq_uop_11_fp_ctrl_sqrt}, {ldq_uop_10_fp_ctrl_sqrt}, {ldq_uop_9_fp_ctrl_sqrt}, {ldq_uop_8_fp_ctrl_sqrt}, {ldq_uop_7_fp_ctrl_sqrt}, {ldq_uop_6_fp_ctrl_sqrt}, {ldq_uop_5_fp_ctrl_sqrt}, {ldq_uop_4_fp_ctrl_sqrt}, {ldq_uop_3_fp_ctrl_sqrt}, {ldq_uop_2_fp_ctrl_sqrt}, {ldq_uop_1_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_sqrt = _GEN_139[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_140 = {{ldq_uop_15_fp_ctrl_wflags}, {ldq_uop_14_fp_ctrl_wflags}, {ldq_uop_13_fp_ctrl_wflags}, {ldq_uop_12_fp_ctrl_wflags}, {ldq_uop_11_fp_ctrl_wflags}, {ldq_uop_10_fp_ctrl_wflags}, {ldq_uop_9_fp_ctrl_wflags}, {ldq_uop_8_fp_ctrl_wflags}, {ldq_uop_7_fp_ctrl_wflags}, {ldq_uop_6_fp_ctrl_wflags}, {ldq_uop_5_fp_ctrl_wflags}, {ldq_uop_4_fp_ctrl_wflags}, {ldq_uop_3_fp_ctrl_wflags}, {ldq_uop_2_fp_ctrl_wflags}, {ldq_uop_1_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_wflags = _GEN_140[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_141 = {{ldq_uop_15_fp_ctrl_vec}, {ldq_uop_14_fp_ctrl_vec}, {ldq_uop_13_fp_ctrl_vec}, {ldq_uop_12_fp_ctrl_vec}, {ldq_uop_11_fp_ctrl_vec}, {ldq_uop_10_fp_ctrl_vec}, {ldq_uop_9_fp_ctrl_vec}, {ldq_uop_8_fp_ctrl_vec}, {ldq_uop_7_fp_ctrl_vec}, {ldq_uop_6_fp_ctrl_vec}, {ldq_uop_5_fp_ctrl_vec}, {ldq_uop_4_fp_ctrl_vec}, {ldq_uop_3_fp_ctrl_vec}, {ldq_uop_2_fp_ctrl_vec}, {ldq_uop_1_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_vec = _GEN_141[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][5:0] _GEN_142 = {{ldq_uop_15_rob_idx}, {ldq_uop_14_rob_idx}, {ldq_uop_13_rob_idx}, {ldq_uop_12_rob_idx}, {ldq_uop_11_rob_idx}, {ldq_uop_10_rob_idx}, {ldq_uop_9_rob_idx}, {ldq_uop_8_rob_idx}, {ldq_uop_7_rob_idx}, {ldq_uop_6_rob_idx}, {ldq_uop_5_rob_idx}, {ldq_uop_4_rob_idx}, {ldq_uop_3_rob_idx}, {ldq_uop_2_rob_idx}, {ldq_uop_1_rob_idx}, {ldq_uop_0_rob_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_rob_idx = _GEN_142[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][3:0] _GEN_143 = {{ldq_uop_15_ldq_idx}, {ldq_uop_14_ldq_idx}, {ldq_uop_13_ldq_idx}, {ldq_uop_12_ldq_idx}, {ldq_uop_11_ldq_idx}, {ldq_uop_10_ldq_idx}, {ldq_uop_9_ldq_idx}, {ldq_uop_8_ldq_idx}, {ldq_uop_7_ldq_idx}, {ldq_uop_6_ldq_idx}, {ldq_uop_5_ldq_idx}, {ldq_uop_4_ldq_idx}, {ldq_uop_3_ldq_idx}, {ldq_uop_2_ldq_idx}, {ldq_uop_1_ldq_idx}, {ldq_uop_0_ldq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ldq_idx = _GEN_143[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][3:0] _GEN_144 = {{ldq_uop_15_stq_idx}, {ldq_uop_14_stq_idx}, {ldq_uop_13_stq_idx}, {ldq_uop_12_stq_idx}, {ldq_uop_11_stq_idx}, {ldq_uop_10_stq_idx}, {ldq_uop_9_stq_idx}, {ldq_uop_8_stq_idx}, {ldq_uop_7_stq_idx}, {ldq_uop_6_stq_idx}, {ldq_uop_5_stq_idx}, {ldq_uop_4_stq_idx}, {ldq_uop_3_stq_idx}, {ldq_uop_2_stq_idx}, {ldq_uop_1_stq_idx}, {ldq_uop_0_stq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_stq_idx = _GEN_144[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_145 = {{ldq_uop_15_rxq_idx}, {ldq_uop_14_rxq_idx}, {ldq_uop_13_rxq_idx}, {ldq_uop_12_rxq_idx}, {ldq_uop_11_rxq_idx}, {ldq_uop_10_rxq_idx}, {ldq_uop_9_rxq_idx}, {ldq_uop_8_rxq_idx}, {ldq_uop_7_rxq_idx}, {ldq_uop_6_rxq_idx}, {ldq_uop_5_rxq_idx}, {ldq_uop_4_rxq_idx}, {ldq_uop_3_rxq_idx}, {ldq_uop_2_rxq_idx}, {ldq_uop_1_rxq_idx}, {ldq_uop_0_rxq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_rxq_idx = _GEN_145[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][6:0] _GEN_146 = {{ldq_uop_15_pdst}, {ldq_uop_14_pdst}, {ldq_uop_13_pdst}, {ldq_uop_12_pdst}, {ldq_uop_11_pdst}, {ldq_uop_10_pdst}, {ldq_uop_9_pdst}, {ldq_uop_8_pdst}, {ldq_uop_7_pdst}, {ldq_uop_6_pdst}, {ldq_uop_5_pdst}, {ldq_uop_4_pdst}, {ldq_uop_3_pdst}, {ldq_uop_2_pdst}, {ldq_uop_1_pdst}, {ldq_uop_0_pdst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_pdst = _GEN_146[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][6:0] _GEN_147 = {{ldq_uop_15_prs1}, {ldq_uop_14_prs1}, {ldq_uop_13_prs1}, {ldq_uop_12_prs1}, {ldq_uop_11_prs1}, {ldq_uop_10_prs1}, {ldq_uop_9_prs1}, {ldq_uop_8_prs1}, {ldq_uop_7_prs1}, {ldq_uop_6_prs1}, {ldq_uop_5_prs1}, {ldq_uop_4_prs1}, {ldq_uop_3_prs1}, {ldq_uop_2_prs1}, {ldq_uop_1_prs1}, {ldq_uop_0_prs1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs1 = _GEN_147[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][6:0] _GEN_148 = {{ldq_uop_15_prs2}, {ldq_uop_14_prs2}, {ldq_uop_13_prs2}, {ldq_uop_12_prs2}, {ldq_uop_11_prs2}, {ldq_uop_10_prs2}, {ldq_uop_9_prs2}, {ldq_uop_8_prs2}, {ldq_uop_7_prs2}, {ldq_uop_6_prs2}, {ldq_uop_5_prs2}, {ldq_uop_4_prs2}, {ldq_uop_3_prs2}, {ldq_uop_2_prs2}, {ldq_uop_1_prs2}, {ldq_uop_0_prs2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs2 = _GEN_148[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][6:0] _GEN_149 = {{ldq_uop_15_prs3}, {ldq_uop_14_prs3}, {ldq_uop_13_prs3}, {ldq_uop_12_prs3}, {ldq_uop_11_prs3}, {ldq_uop_10_prs3}, {ldq_uop_9_prs3}, {ldq_uop_8_prs3}, {ldq_uop_7_prs3}, {ldq_uop_6_prs3}, {ldq_uop_5_prs3}, {ldq_uop_4_prs3}, {ldq_uop_3_prs3}, {ldq_uop_2_prs3}, {ldq_uop_1_prs3}, {ldq_uop_0_prs3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs3 = _GEN_149[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][4:0] _GEN_150 = {{ldq_uop_15_ppred}, {ldq_uop_14_ppred}, {ldq_uop_13_ppred}, {ldq_uop_12_ppred}, {ldq_uop_11_ppred}, {ldq_uop_10_ppred}, {ldq_uop_9_ppred}, {ldq_uop_8_ppred}, {ldq_uop_7_ppred}, {ldq_uop_6_ppred}, {ldq_uop_5_ppred}, {ldq_uop_4_ppred}, {ldq_uop_3_ppred}, {ldq_uop_2_ppred}, {ldq_uop_1_ppred}, {ldq_uop_0_ppred}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ppred = _GEN_150[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_151 = {{ldq_uop_15_prs1_busy}, {ldq_uop_14_prs1_busy}, {ldq_uop_13_prs1_busy}, {ldq_uop_12_prs1_busy}, {ldq_uop_11_prs1_busy}, {ldq_uop_10_prs1_busy}, {ldq_uop_9_prs1_busy}, {ldq_uop_8_prs1_busy}, {ldq_uop_7_prs1_busy}, {ldq_uop_6_prs1_busy}, {ldq_uop_5_prs1_busy}, {ldq_uop_4_prs1_busy}, {ldq_uop_3_prs1_busy}, {ldq_uop_2_prs1_busy}, {ldq_uop_1_prs1_busy}, {ldq_uop_0_prs1_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs1_busy = _GEN_151[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_152 = {{ldq_uop_15_prs2_busy}, {ldq_uop_14_prs2_busy}, {ldq_uop_13_prs2_busy}, {ldq_uop_12_prs2_busy}, {ldq_uop_11_prs2_busy}, {ldq_uop_10_prs2_busy}, {ldq_uop_9_prs2_busy}, {ldq_uop_8_prs2_busy}, {ldq_uop_7_prs2_busy}, {ldq_uop_6_prs2_busy}, {ldq_uop_5_prs2_busy}, {ldq_uop_4_prs2_busy}, {ldq_uop_3_prs2_busy}, {ldq_uop_2_prs2_busy}, {ldq_uop_1_prs2_busy}, {ldq_uop_0_prs2_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs2_busy = _GEN_152[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_153 = {{ldq_uop_15_prs3_busy}, {ldq_uop_14_prs3_busy}, {ldq_uop_13_prs3_busy}, {ldq_uop_12_prs3_busy}, {ldq_uop_11_prs3_busy}, {ldq_uop_10_prs3_busy}, {ldq_uop_9_prs3_busy}, {ldq_uop_8_prs3_busy}, {ldq_uop_7_prs3_busy}, {ldq_uop_6_prs3_busy}, {ldq_uop_5_prs3_busy}, {ldq_uop_4_prs3_busy}, {ldq_uop_3_prs3_busy}, {ldq_uop_2_prs3_busy}, {ldq_uop_1_prs3_busy}, {ldq_uop_0_prs3_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs3_busy = _GEN_153[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_154 = {{ldq_uop_15_ppred_busy}, {ldq_uop_14_ppred_busy}, {ldq_uop_13_ppred_busy}, {ldq_uop_12_ppred_busy}, {ldq_uop_11_ppred_busy}, {ldq_uop_10_ppred_busy}, {ldq_uop_9_ppred_busy}, {ldq_uop_8_ppred_busy}, {ldq_uop_7_ppred_busy}, {ldq_uop_6_ppred_busy}, {ldq_uop_5_ppred_busy}, {ldq_uop_4_ppred_busy}, {ldq_uop_3_ppred_busy}, {ldq_uop_2_ppred_busy}, {ldq_uop_1_ppred_busy}, {ldq_uop_0_ppred_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ppred_busy = _GEN_154[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][6:0] _GEN_155 = {{ldq_uop_15_stale_pdst}, {ldq_uop_14_stale_pdst}, {ldq_uop_13_stale_pdst}, {ldq_uop_12_stale_pdst}, {ldq_uop_11_stale_pdst}, {ldq_uop_10_stale_pdst}, {ldq_uop_9_stale_pdst}, {ldq_uop_8_stale_pdst}, {ldq_uop_7_stale_pdst}, {ldq_uop_6_stale_pdst}, {ldq_uop_5_stale_pdst}, {ldq_uop_4_stale_pdst}, {ldq_uop_3_stale_pdst}, {ldq_uop_2_stale_pdst}, {ldq_uop_1_stale_pdst}, {ldq_uop_0_stale_pdst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_stale_pdst = _GEN_155[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_156 = {{ldq_uop_15_exception}, {ldq_uop_14_exception}, {ldq_uop_13_exception}, {ldq_uop_12_exception}, {ldq_uop_11_exception}, {ldq_uop_10_exception}, {ldq_uop_9_exception}, {ldq_uop_8_exception}, {ldq_uop_7_exception}, {ldq_uop_6_exception}, {ldq_uop_5_exception}, {ldq_uop_4_exception}, {ldq_uop_3_exception}, {ldq_uop_2_exception}, {ldq_uop_1_exception}, {ldq_uop_0_exception}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_exception = _GEN_156[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][63:0] _GEN_157 = {{ldq_uop_15_exc_cause}, {ldq_uop_14_exc_cause}, {ldq_uop_13_exc_cause}, {ldq_uop_12_exc_cause}, {ldq_uop_11_exc_cause}, {ldq_uop_10_exc_cause}, {ldq_uop_9_exc_cause}, {ldq_uop_8_exc_cause}, {ldq_uop_7_exc_cause}, {ldq_uop_6_exc_cause}, {ldq_uop_5_exc_cause}, {ldq_uop_4_exc_cause}, {ldq_uop_3_exc_cause}, {ldq_uop_2_exc_cause}, {ldq_uop_1_exc_cause}, {ldq_uop_0_exc_cause}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_exc_cause = _GEN_157[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][4:0] _GEN_158 = {{ldq_uop_15_mem_cmd}, {ldq_uop_14_mem_cmd}, {ldq_uop_13_mem_cmd}, {ldq_uop_12_mem_cmd}, {ldq_uop_11_mem_cmd}, {ldq_uop_10_mem_cmd}, {ldq_uop_9_mem_cmd}, {ldq_uop_8_mem_cmd}, {ldq_uop_7_mem_cmd}, {ldq_uop_6_mem_cmd}, {ldq_uop_5_mem_cmd}, {ldq_uop_4_mem_cmd}, {ldq_uop_3_mem_cmd}, {ldq_uop_2_mem_cmd}, {ldq_uop_1_mem_cmd}, {ldq_uop_0_mem_cmd}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_mem_cmd = _GEN_158[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_159 = {{ldq_uop_15_mem_size}, {ldq_uop_14_mem_size}, {ldq_uop_13_mem_size}, {ldq_uop_12_mem_size}, {ldq_uop_11_mem_size}, {ldq_uop_10_mem_size}, {ldq_uop_9_mem_size}, {ldq_uop_8_mem_size}, {ldq_uop_7_mem_size}, {ldq_uop_6_mem_size}, {ldq_uop_5_mem_size}, {ldq_uop_4_mem_size}, {ldq_uop_3_mem_size}, {ldq_uop_2_mem_size}, {ldq_uop_1_mem_size}, {ldq_uop_0_mem_size}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_mem_size = _GEN_159[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_160 = {{ldq_uop_15_mem_signed}, {ldq_uop_14_mem_signed}, {ldq_uop_13_mem_signed}, {ldq_uop_12_mem_signed}, {ldq_uop_11_mem_signed}, {ldq_uop_10_mem_signed}, {ldq_uop_9_mem_signed}, {ldq_uop_8_mem_signed}, {ldq_uop_7_mem_signed}, {ldq_uop_6_mem_signed}, {ldq_uop_5_mem_signed}, {ldq_uop_4_mem_signed}, {ldq_uop_3_mem_signed}, {ldq_uop_2_mem_signed}, {ldq_uop_1_mem_signed}, {ldq_uop_0_mem_signed}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_mem_signed = _GEN_160[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_161 = {{ldq_uop_15_uses_ldq}, {ldq_uop_14_uses_ldq}, {ldq_uop_13_uses_ldq}, {ldq_uop_12_uses_ldq}, {ldq_uop_11_uses_ldq}, {ldq_uop_10_uses_ldq}, {ldq_uop_9_uses_ldq}, {ldq_uop_8_uses_ldq}, {ldq_uop_7_uses_ldq}, {ldq_uop_6_uses_ldq}, {ldq_uop_5_uses_ldq}, {ldq_uop_4_uses_ldq}, {ldq_uop_3_uses_ldq}, {ldq_uop_2_uses_ldq}, {ldq_uop_1_uses_ldq}, {ldq_uop_0_uses_ldq}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_uses_ldq = _GEN_161[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_162 = {{ldq_uop_15_uses_stq}, {ldq_uop_14_uses_stq}, {ldq_uop_13_uses_stq}, {ldq_uop_12_uses_stq}, {ldq_uop_11_uses_stq}, {ldq_uop_10_uses_stq}, {ldq_uop_9_uses_stq}, {ldq_uop_8_uses_stq}, {ldq_uop_7_uses_stq}, {ldq_uop_6_uses_stq}, {ldq_uop_5_uses_stq}, {ldq_uop_4_uses_stq}, {ldq_uop_3_uses_stq}, {ldq_uop_2_uses_stq}, {ldq_uop_1_uses_stq}, {ldq_uop_0_uses_stq}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_uses_stq = _GEN_162[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_163 = {{ldq_uop_15_is_unique}, {ldq_uop_14_is_unique}, {ldq_uop_13_is_unique}, {ldq_uop_12_is_unique}, {ldq_uop_11_is_unique}, {ldq_uop_10_is_unique}, {ldq_uop_9_is_unique}, {ldq_uop_8_is_unique}, {ldq_uop_7_is_unique}, {ldq_uop_6_is_unique}, {ldq_uop_5_is_unique}, {ldq_uop_4_is_unique}, {ldq_uop_3_is_unique}, {ldq_uop_2_is_unique}, {ldq_uop_1_is_unique}, {ldq_uop_0_is_unique}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_unique = _GEN_163[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_164 = {{ldq_uop_15_flush_on_commit}, {ldq_uop_14_flush_on_commit}, {ldq_uop_13_flush_on_commit}, {ldq_uop_12_flush_on_commit}, {ldq_uop_11_flush_on_commit}, {ldq_uop_10_flush_on_commit}, {ldq_uop_9_flush_on_commit}, {ldq_uop_8_flush_on_commit}, {ldq_uop_7_flush_on_commit}, {ldq_uop_6_flush_on_commit}, {ldq_uop_5_flush_on_commit}, {ldq_uop_4_flush_on_commit}, {ldq_uop_3_flush_on_commit}, {ldq_uop_2_flush_on_commit}, {ldq_uop_1_flush_on_commit}, {ldq_uop_0_flush_on_commit}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_flush_on_commit = _GEN_164[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][2:0] _GEN_165 = {{ldq_uop_15_csr_cmd}, {ldq_uop_14_csr_cmd}, {ldq_uop_13_csr_cmd}, {ldq_uop_12_csr_cmd}, {ldq_uop_11_csr_cmd}, {ldq_uop_10_csr_cmd}, {ldq_uop_9_csr_cmd}, {ldq_uop_8_csr_cmd}, {ldq_uop_7_csr_cmd}, {ldq_uop_6_csr_cmd}, {ldq_uop_5_csr_cmd}, {ldq_uop_4_csr_cmd}, {ldq_uop_3_csr_cmd}, {ldq_uop_2_csr_cmd}, {ldq_uop_1_csr_cmd}, {ldq_uop_0_csr_cmd}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_csr_cmd = _GEN_165[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_166 = {{ldq_uop_15_ldst_is_rs1}, {ldq_uop_14_ldst_is_rs1}, {ldq_uop_13_ldst_is_rs1}, {ldq_uop_12_ldst_is_rs1}, {ldq_uop_11_ldst_is_rs1}, {ldq_uop_10_ldst_is_rs1}, {ldq_uop_9_ldst_is_rs1}, {ldq_uop_8_ldst_is_rs1}, {ldq_uop_7_ldst_is_rs1}, {ldq_uop_6_ldst_is_rs1}, {ldq_uop_5_ldst_is_rs1}, {ldq_uop_4_ldst_is_rs1}, {ldq_uop_3_ldst_is_rs1}, {ldq_uop_2_ldst_is_rs1}, {ldq_uop_1_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ldst_is_rs1 = _GEN_166[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][5:0] _GEN_167 = {{ldq_uop_15_ldst}, {ldq_uop_14_ldst}, {ldq_uop_13_ldst}, {ldq_uop_12_ldst}, {ldq_uop_11_ldst}, {ldq_uop_10_ldst}, {ldq_uop_9_ldst}, {ldq_uop_8_ldst}, {ldq_uop_7_ldst}, {ldq_uop_6_ldst}, {ldq_uop_5_ldst}, {ldq_uop_4_ldst}, {ldq_uop_3_ldst}, {ldq_uop_2_ldst}, {ldq_uop_1_ldst}, {ldq_uop_0_ldst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ldst = _GEN_167[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][5:0] _GEN_168 = {{ldq_uop_15_lrs1}, {ldq_uop_14_lrs1}, {ldq_uop_13_lrs1}, {ldq_uop_12_lrs1}, {ldq_uop_11_lrs1}, {ldq_uop_10_lrs1}, {ldq_uop_9_lrs1}, {ldq_uop_8_lrs1}, {ldq_uop_7_lrs1}, {ldq_uop_6_lrs1}, {ldq_uop_5_lrs1}, {ldq_uop_4_lrs1}, {ldq_uop_3_lrs1}, {ldq_uop_2_lrs1}, {ldq_uop_1_lrs1}, {ldq_uop_0_lrs1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs1 = _GEN_168[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][5:0] _GEN_169 = {{ldq_uop_15_lrs2}, {ldq_uop_14_lrs2}, {ldq_uop_13_lrs2}, {ldq_uop_12_lrs2}, {ldq_uop_11_lrs2}, {ldq_uop_10_lrs2}, {ldq_uop_9_lrs2}, {ldq_uop_8_lrs2}, {ldq_uop_7_lrs2}, {ldq_uop_6_lrs2}, {ldq_uop_5_lrs2}, {ldq_uop_4_lrs2}, {ldq_uop_3_lrs2}, {ldq_uop_2_lrs2}, {ldq_uop_1_lrs2}, {ldq_uop_0_lrs2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs2 = _GEN_169[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][5:0] _GEN_170 = {{ldq_uop_15_lrs3}, {ldq_uop_14_lrs3}, {ldq_uop_13_lrs3}, {ldq_uop_12_lrs3}, {ldq_uop_11_lrs3}, {ldq_uop_10_lrs3}, {ldq_uop_9_lrs3}, {ldq_uop_8_lrs3}, {ldq_uop_7_lrs3}, {ldq_uop_6_lrs3}, {ldq_uop_5_lrs3}, {ldq_uop_4_lrs3}, {ldq_uop_3_lrs3}, {ldq_uop_2_lrs3}, {ldq_uop_1_lrs3}, {ldq_uop_0_lrs3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs3 = _GEN_170[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_171 = {{ldq_uop_15_dst_rtype}, {ldq_uop_14_dst_rtype}, {ldq_uop_13_dst_rtype}, {ldq_uop_12_dst_rtype}, {ldq_uop_11_dst_rtype}, {ldq_uop_10_dst_rtype}, {ldq_uop_9_dst_rtype}, {ldq_uop_8_dst_rtype}, {ldq_uop_7_dst_rtype}, {ldq_uop_6_dst_rtype}, {ldq_uop_5_dst_rtype}, {ldq_uop_4_dst_rtype}, {ldq_uop_3_dst_rtype}, {ldq_uop_2_dst_rtype}, {ldq_uop_1_dst_rtype}, {ldq_uop_0_dst_rtype}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_dst_rtype = _GEN_171[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_172 = {{ldq_uop_15_lrs1_rtype}, {ldq_uop_14_lrs1_rtype}, {ldq_uop_13_lrs1_rtype}, {ldq_uop_12_lrs1_rtype}, {ldq_uop_11_lrs1_rtype}, {ldq_uop_10_lrs1_rtype}, {ldq_uop_9_lrs1_rtype}, {ldq_uop_8_lrs1_rtype}, {ldq_uop_7_lrs1_rtype}, {ldq_uop_6_lrs1_rtype}, {ldq_uop_5_lrs1_rtype}, {ldq_uop_4_lrs1_rtype}, {ldq_uop_3_lrs1_rtype}, {ldq_uop_2_lrs1_rtype}, {ldq_uop_1_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs1_rtype = _GEN_172[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_173 = {{ldq_uop_15_lrs2_rtype}, {ldq_uop_14_lrs2_rtype}, {ldq_uop_13_lrs2_rtype}, {ldq_uop_12_lrs2_rtype}, {ldq_uop_11_lrs2_rtype}, {ldq_uop_10_lrs2_rtype}, {ldq_uop_9_lrs2_rtype}, {ldq_uop_8_lrs2_rtype}, {ldq_uop_7_lrs2_rtype}, {ldq_uop_6_lrs2_rtype}, {ldq_uop_5_lrs2_rtype}, {ldq_uop_4_lrs2_rtype}, {ldq_uop_3_lrs2_rtype}, {ldq_uop_2_lrs2_rtype}, {ldq_uop_1_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs2_rtype = _GEN_173[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_174 = {{ldq_uop_15_frs3_en}, {ldq_uop_14_frs3_en}, {ldq_uop_13_frs3_en}, {ldq_uop_12_frs3_en}, {ldq_uop_11_frs3_en}, {ldq_uop_10_frs3_en}, {ldq_uop_9_frs3_en}, {ldq_uop_8_frs3_en}, {ldq_uop_7_frs3_en}, {ldq_uop_6_frs3_en}, {ldq_uop_5_frs3_en}, {ldq_uop_4_frs3_en}, {ldq_uop_3_frs3_en}, {ldq_uop_2_frs3_en}, {ldq_uop_1_frs3_en}, {ldq_uop_0_frs3_en}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_frs3_en = _GEN_174[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_175 = {{ldq_uop_15_fcn_dw}, {ldq_uop_14_fcn_dw}, {ldq_uop_13_fcn_dw}, {ldq_uop_12_fcn_dw}, {ldq_uop_11_fcn_dw}, {ldq_uop_10_fcn_dw}, {ldq_uop_9_fcn_dw}, {ldq_uop_8_fcn_dw}, {ldq_uop_7_fcn_dw}, {ldq_uop_6_fcn_dw}, {ldq_uop_5_fcn_dw}, {ldq_uop_4_fcn_dw}, {ldq_uop_3_fcn_dw}, {ldq_uop_2_fcn_dw}, {ldq_uop_1_fcn_dw}, {ldq_uop_0_fcn_dw}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fcn_dw = _GEN_175[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][4:0] _GEN_176 = {{ldq_uop_15_fcn_op}, {ldq_uop_14_fcn_op}, {ldq_uop_13_fcn_op}, {ldq_uop_12_fcn_op}, {ldq_uop_11_fcn_op}, {ldq_uop_10_fcn_op}, {ldq_uop_9_fcn_op}, {ldq_uop_8_fcn_op}, {ldq_uop_7_fcn_op}, {ldq_uop_6_fcn_op}, {ldq_uop_5_fcn_op}, {ldq_uop_4_fcn_op}, {ldq_uop_3_fcn_op}, {ldq_uop_2_fcn_op}, {ldq_uop_1_fcn_op}, {ldq_uop_0_fcn_op}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fcn_op = _GEN_176[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_177 = {{ldq_uop_15_fp_val}, {ldq_uop_14_fp_val}, {ldq_uop_13_fp_val}, {ldq_uop_12_fp_val}, {ldq_uop_11_fp_val}, {ldq_uop_10_fp_val}, {ldq_uop_9_fp_val}, {ldq_uop_8_fp_val}, {ldq_uop_7_fp_val}, {ldq_uop_6_fp_val}, {ldq_uop_5_fp_val}, {ldq_uop_4_fp_val}, {ldq_uop_3_fp_val}, {ldq_uop_2_fp_val}, {ldq_uop_1_fp_val}, {ldq_uop_0_fp_val}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_val = _GEN_177[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][2:0] _GEN_178 = {{ldq_uop_15_fp_rm}, {ldq_uop_14_fp_rm}, {ldq_uop_13_fp_rm}, {ldq_uop_12_fp_rm}, {ldq_uop_11_fp_rm}, {ldq_uop_10_fp_rm}, {ldq_uop_9_fp_rm}, {ldq_uop_8_fp_rm}, {ldq_uop_7_fp_rm}, {ldq_uop_6_fp_rm}, {ldq_uop_5_fp_rm}, {ldq_uop_4_fp_rm}, {ldq_uop_3_fp_rm}, {ldq_uop_2_fp_rm}, {ldq_uop_1_fp_rm}, {ldq_uop_0_fp_rm}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_rm = _GEN_178[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][1:0] _GEN_179 = {{ldq_uop_15_fp_typ}, {ldq_uop_14_fp_typ}, {ldq_uop_13_fp_typ}, {ldq_uop_12_fp_typ}, {ldq_uop_11_fp_typ}, {ldq_uop_10_fp_typ}, {ldq_uop_9_fp_typ}, {ldq_uop_8_fp_typ}, {ldq_uop_7_fp_typ}, {ldq_uop_6_fp_typ}, {ldq_uop_5_fp_typ}, {ldq_uop_4_fp_typ}, {ldq_uop_3_fp_typ}, {ldq_uop_2_fp_typ}, {ldq_uop_1_fp_typ}, {ldq_uop_0_fp_typ}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_typ = _GEN_179[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_180 = {{ldq_uop_15_xcpt_pf_if}, {ldq_uop_14_xcpt_pf_if}, {ldq_uop_13_xcpt_pf_if}, {ldq_uop_12_xcpt_pf_if}, {ldq_uop_11_xcpt_pf_if}, {ldq_uop_10_xcpt_pf_if}, {ldq_uop_9_xcpt_pf_if}, {ldq_uop_8_xcpt_pf_if}, {ldq_uop_7_xcpt_pf_if}, {ldq_uop_6_xcpt_pf_if}, {ldq_uop_5_xcpt_pf_if}, {ldq_uop_4_xcpt_pf_if}, {ldq_uop_3_xcpt_pf_if}, {ldq_uop_2_xcpt_pf_if}, {ldq_uop_1_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_xcpt_pf_if = _GEN_180[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_181 = {{ldq_uop_15_xcpt_ae_if}, {ldq_uop_14_xcpt_ae_if}, {ldq_uop_13_xcpt_ae_if}, {ldq_uop_12_xcpt_ae_if}, {ldq_uop_11_xcpt_ae_if}, {ldq_uop_10_xcpt_ae_if}, {ldq_uop_9_xcpt_ae_if}, {ldq_uop_8_xcpt_ae_if}, {ldq_uop_7_xcpt_ae_if}, {ldq_uop_6_xcpt_ae_if}, {ldq_uop_5_xcpt_ae_if}, {ldq_uop_4_xcpt_ae_if}, {ldq_uop_3_xcpt_ae_if}, {ldq_uop_2_xcpt_ae_if}, {ldq_uop_1_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_xcpt_ae_if = _GEN_181[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_182 = {{ldq_uop_15_xcpt_ma_if}, {ldq_uop_14_xcpt_ma_if}, {ldq_uop_13_xcpt_ma_if}, {ldq_uop_12_xcpt_ma_if}, {ldq_uop_11_xcpt_ma_if}, {ldq_uop_10_xcpt_ma_if}, {ldq_uop_9_xcpt_ma_if}, {ldq_uop_8_xcpt_ma_if}, {ldq_uop_7_xcpt_ma_if}, {ldq_uop_6_xcpt_ma_if}, {ldq_uop_5_xcpt_ma_if}, {ldq_uop_4_xcpt_ma_if}, {ldq_uop_3_xcpt_ma_if}, {ldq_uop_2_xcpt_ma_if}, {ldq_uop_1_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_xcpt_ma_if = _GEN_182[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_183 = {{ldq_uop_15_bp_debug_if}, {ldq_uop_14_bp_debug_if}, {ldq_uop_13_bp_debug_if}, {ldq_uop_12_bp_debug_if}, {ldq_uop_11_bp_debug_if}, {ldq_uop_10_bp_debug_if}, {ldq_uop_9_bp_debug_if}, {ldq_uop_8_bp_debug_if}, {ldq_uop_7_bp_debug_if}, {ldq_uop_6_bp_debug_if}, {ldq_uop_5_bp_debug_if}, {ldq_uop_4_bp_debug_if}, {ldq_uop_3_bp_debug_if}, {ldq_uop_2_bp_debug_if}, {ldq_uop_1_bp_debug_if}, {ldq_uop_0_bp_debug_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_bp_debug_if = _GEN_183[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_184 = {{ldq_uop_15_bp_xcpt_if}, {ldq_uop_14_bp_xcpt_if}, {ldq_uop_13_bp_xcpt_if}, {ldq_uop_12_bp_xcpt_if}, {ldq_uop_11_bp_xcpt_if}, {ldq_uop_10_bp_xcpt_if}, {ldq_uop_9_bp_xcpt_if}, {ldq_uop_8_bp_xcpt_if}, {ldq_uop_7_bp_xcpt_if}, {ldq_uop_6_bp_xcpt_if}, {ldq_uop_5_bp_xcpt_if}, {ldq_uop_4_bp_xcpt_if}, {ldq_uop_3_bp_xcpt_if}, {ldq_uop_2_bp_xcpt_if}, {ldq_uop_1_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_bp_xcpt_if = _GEN_184[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][2:0] _GEN_185 = {{ldq_uop_15_debug_fsrc}, {ldq_uop_14_debug_fsrc}, {ldq_uop_13_debug_fsrc}, {ldq_uop_12_debug_fsrc}, {ldq_uop_11_debug_fsrc}, {ldq_uop_10_debug_fsrc}, {ldq_uop_9_debug_fsrc}, {ldq_uop_8_debug_fsrc}, {ldq_uop_7_debug_fsrc}, {ldq_uop_6_debug_fsrc}, {ldq_uop_5_debug_fsrc}, {ldq_uop_4_debug_fsrc}, {ldq_uop_3_debug_fsrc}, {ldq_uop_2_debug_fsrc}, {ldq_uop_1_debug_fsrc}, {ldq_uop_0_debug_fsrc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_fsrc = _GEN_185[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0][2:0] _GEN_186 = {{ldq_uop_15_debug_tsrc}, {ldq_uop_14_debug_tsrc}, {ldq_uop_13_debug_tsrc}, {ldq_uop_12_debug_tsrc}, {ldq_uop_11_debug_tsrc}, {ldq_uop_10_debug_tsrc}, {ldq_uop_9_debug_tsrc}, {ldq_uop_8_debug_tsrc}, {ldq_uop_7_debug_tsrc}, {ldq_uop_6_debug_tsrc}, {ldq_uop_5_debug_tsrc}, {ldq_uop_4_debug_tsrc}, {ldq_uop_3_debug_tsrc}, {ldq_uop_2_debug_tsrc}, {ldq_uop_1_debug_tsrc}, {ldq_uop_0_debug_tsrc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_tsrc = _GEN_186[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [15:0] _GEN_187 = {{ldq_addr_15_valid}, {ldq_addr_14_valid}, {ldq_addr_13_valid}, {ldq_addr_12_valid}, {ldq_addr_11_valid}, {ldq_addr_10_valid}, {ldq_addr_9_valid}, {ldq_addr_8_valid}, {ldq_addr_7_valid}, {ldq_addr_6_valid}, {ldq_addr_5_valid}, {ldq_addr_4_valid}, {ldq_addr_3_valid}, {ldq_addr_2_valid}, {ldq_addr_1_valid}, {ldq_addr_0_valid}}; // @[lsu.scala:220:36, :236:32] assign ldq_incoming_e_e_bits_addr_valid = _GEN_187[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :236:32, :321:49] wire [15:0][39:0] _GEN_188 = {{ldq_addr_15_bits}, {ldq_addr_14_bits}, {ldq_addr_13_bits}, {ldq_addr_12_bits}, {ldq_addr_11_bits}, {ldq_addr_10_bits}, {ldq_addr_9_bits}, {ldq_addr_8_bits}, {ldq_addr_7_bits}, {ldq_addr_6_bits}, {ldq_addr_5_bits}, {ldq_addr_4_bits}, {ldq_addr_3_bits}, {ldq_addr_2_bits}, {ldq_addr_1_bits}, {ldq_addr_0_bits}}; // @[lsu.scala:220:36, :236:32] assign ldq_incoming_e_e_bits_addr_bits = _GEN_188[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :236:32, :321:49] wire [15:0] _GEN_189 = {{ldq_addr_is_virtual_15}, {ldq_addr_is_virtual_14}, {ldq_addr_is_virtual_13}, {ldq_addr_is_virtual_12}, {ldq_addr_is_virtual_11}, {ldq_addr_is_virtual_10}, {ldq_addr_is_virtual_9}, {ldq_addr_is_virtual_8}, {ldq_addr_is_virtual_7}, {ldq_addr_is_virtual_6}, {ldq_addr_is_virtual_5}, {ldq_addr_is_virtual_4}, {ldq_addr_is_virtual_3}, {ldq_addr_is_virtual_2}, {ldq_addr_is_virtual_1}, {ldq_addr_is_virtual_0}}; // @[lsu.scala:221:36, :237:32] assign ldq_incoming_e_e_bits_addr_is_virtual = _GEN_189[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :237:32, :321:49] wire [15:0] _GEN_190 = {{ldq_addr_is_uncacheable_15}, {ldq_addr_is_uncacheable_14}, {ldq_addr_is_uncacheable_13}, {ldq_addr_is_uncacheable_12}, {ldq_addr_is_uncacheable_11}, {ldq_addr_is_uncacheable_10}, {ldq_addr_is_uncacheable_9}, {ldq_addr_is_uncacheable_8}, {ldq_addr_is_uncacheable_7}, {ldq_addr_is_uncacheable_6}, {ldq_addr_is_uncacheable_5}, {ldq_addr_is_uncacheable_4}, {ldq_addr_is_uncacheable_3}, {ldq_addr_is_uncacheable_2}, {ldq_addr_is_uncacheable_1}, {ldq_addr_is_uncacheable_0}}; // @[lsu.scala:222:36, :238:32] assign ldq_incoming_e_e_bits_addr_is_uncacheable = _GEN_190[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :238:32, :321:49] wire [15:0] _GEN_191 = {{ldq_executed_15}, {ldq_executed_14}, {ldq_executed_13}, {ldq_executed_12}, {ldq_executed_11}, {ldq_executed_10}, {ldq_executed_9}, {ldq_executed_8}, {ldq_executed_7}, {ldq_executed_6}, {ldq_executed_5}, {ldq_executed_4}, {ldq_executed_3}, {ldq_executed_2}, {ldq_executed_1}, {ldq_executed_0}}; // @[lsu.scala:223:36, :239:32] assign ldq_incoming_e_e_bits_executed = _GEN_191[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :239:32, :321:49] wire [15:0] _GEN_192 = {{ldq_succeeded_15}, {ldq_succeeded_14}, {ldq_succeeded_13}, {ldq_succeeded_12}, {ldq_succeeded_11}, {ldq_succeeded_10}, {ldq_succeeded_9}, {ldq_succeeded_8}, {ldq_succeeded_7}, {ldq_succeeded_6}, {ldq_succeeded_5}, {ldq_succeeded_4}, {ldq_succeeded_3}, {ldq_succeeded_2}, {ldq_succeeded_1}, {ldq_succeeded_0}}; // @[lsu.scala:224:36, :240:32] assign ldq_incoming_e_e_bits_succeeded = _GEN_192[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :240:32, :321:49] wire [15:0] _GEN_193 = {{ldq_order_fail_15}, {ldq_order_fail_14}, {ldq_order_fail_13}, {ldq_order_fail_12}, {ldq_order_fail_11}, {ldq_order_fail_10}, {ldq_order_fail_9}, {ldq_order_fail_8}, {ldq_order_fail_7}, {ldq_order_fail_6}, {ldq_order_fail_5}, {ldq_order_fail_4}, {ldq_order_fail_3}, {ldq_order_fail_2}, {ldq_order_fail_1}, {ldq_order_fail_0}}; // @[lsu.scala:225:36, :241:32] assign ldq_incoming_e_e_bits_order_fail = _GEN_193[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :241:32, :321:49] wire [15:0] _GEN_194 = {{ldq_observed_15}, {ldq_observed_14}, {ldq_observed_13}, {ldq_observed_12}, {ldq_observed_11}, {ldq_observed_10}, {ldq_observed_9}, {ldq_observed_8}, {ldq_observed_7}, {ldq_observed_6}, {ldq_observed_5}, {ldq_observed_4}, {ldq_observed_3}, {ldq_observed_2}, {ldq_observed_1}, {ldq_observed_0}}; // @[lsu.scala:226:36, :242:32] assign ldq_incoming_e_e_bits_observed = _GEN_194[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :242:32, :321:49] wire [15:0][15:0] _GEN_195 = {{ldq_st_dep_mask_15}, {ldq_st_dep_mask_14}, {ldq_st_dep_mask_13}, {ldq_st_dep_mask_12}, {ldq_st_dep_mask_11}, {ldq_st_dep_mask_10}, {ldq_st_dep_mask_9}, {ldq_st_dep_mask_8}, {ldq_st_dep_mask_7}, {ldq_st_dep_mask_6}, {ldq_st_dep_mask_5}, {ldq_st_dep_mask_4}, {ldq_st_dep_mask_3}, {ldq_st_dep_mask_2}, {ldq_st_dep_mask_1}, {ldq_st_dep_mask_0}}; // @[lsu.scala:227:36, :243:32] assign ldq_incoming_e_e_bits_st_dep_mask = _GEN_195[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :243:32, :321:49] wire [15:0][7:0] _GEN_196 = {{ldq_ld_byte_mask_15}, {ldq_ld_byte_mask_14}, {ldq_ld_byte_mask_13}, {ldq_ld_byte_mask_12}, {ldq_ld_byte_mask_11}, {ldq_ld_byte_mask_10}, {ldq_ld_byte_mask_9}, {ldq_ld_byte_mask_8}, {ldq_ld_byte_mask_7}, {ldq_ld_byte_mask_6}, {ldq_ld_byte_mask_5}, {ldq_ld_byte_mask_4}, {ldq_ld_byte_mask_3}, {ldq_ld_byte_mask_2}, {ldq_ld_byte_mask_1}, {ldq_ld_byte_mask_0}}; // @[lsu.scala:228:36, :244:32] assign ldq_incoming_e_e_bits_ld_byte_mask = _GEN_196[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :244:32, :321:49] wire [15:0] _GEN_197 = {{ldq_forward_std_val_15}, {ldq_forward_std_val_14}, {ldq_forward_std_val_13}, {ldq_forward_std_val_12}, {ldq_forward_std_val_11}, {ldq_forward_std_val_10}, {ldq_forward_std_val_9}, {ldq_forward_std_val_8}, {ldq_forward_std_val_7}, {ldq_forward_std_val_6}, {ldq_forward_std_val_5}, {ldq_forward_std_val_4}, {ldq_forward_std_val_3}, {ldq_forward_std_val_2}, {ldq_forward_std_val_1}, {ldq_forward_std_val_0}}; // @[lsu.scala:229:36, :245:32] assign ldq_incoming_e_e_bits_forward_std_val = _GEN_197[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :245:32, :321:49] wire [15:0][3:0] _GEN_198 = {{ldq_forward_stq_idx_15}, {ldq_forward_stq_idx_14}, {ldq_forward_stq_idx_13}, {ldq_forward_stq_idx_12}, {ldq_forward_stq_idx_11}, {ldq_forward_stq_idx_10}, {ldq_forward_stq_idx_9}, {ldq_forward_stq_idx_8}, {ldq_forward_stq_idx_7}, {ldq_forward_stq_idx_6}, {ldq_forward_stq_idx_5}, {ldq_forward_stq_idx_4}, {ldq_forward_stq_idx_3}, {ldq_forward_stq_idx_2}, {ldq_forward_stq_idx_1}, {ldq_forward_stq_idx_0}}; // @[lsu.scala:230:36, :246:32] assign ldq_incoming_e_e_bits_forward_stq_idx = _GEN_198[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :246:32, :321:49] wire [15:0][63:0] _GEN_199 = {{ldq_debug_wb_data_15}, {ldq_debug_wb_data_14}, {ldq_debug_wb_data_13}, {ldq_debug_wb_data_12}, {ldq_debug_wb_data_11}, {ldq_debug_wb_data_10}, {ldq_debug_wb_data_9}, {ldq_debug_wb_data_8}, {ldq_debug_wb_data_7}, {ldq_debug_wb_data_6}, {ldq_debug_wb_data_5}, {ldq_debug_wb_data_4}, {ldq_debug_wb_data_3}, {ldq_debug_wb_data_2}, {ldq_debug_wb_data_1}, {ldq_debug_wb_data_0}}; // @[lsu.scala:231:36, :247:32] assign ldq_incoming_e_e_bits_debug_wb_data = _GEN_199[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :247:32, :321:49] wire ldq_incoming_e_0_valid = _ldq_incoming_e_WIRE_valid; // @[lsu.scala:321:49, :501:48] wire [31:0] ldq_incoming_e_0_bits_uop_inst = _ldq_incoming_e_WIRE_bits_uop_inst; // @[lsu.scala:321:49, :501:48] wire [31:0] ldq_incoming_e_0_bits_uop_debug_inst = _ldq_incoming_e_WIRE_bits_uop_debug_inst; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_rvc = _ldq_incoming_e_WIRE_bits_uop_is_rvc; // @[lsu.scala:321:49, :501:48] wire [39:0] ldq_incoming_e_0_bits_uop_debug_pc = _ldq_incoming_e_WIRE_bits_uop_debug_pc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_0 = _ldq_incoming_e_WIRE_bits_uop_iq_type_0; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_1 = _ldq_incoming_e_WIRE_bits_uop_iq_type_1; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_2 = _ldq_incoming_e_WIRE_bits_uop_iq_type_2; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_3 = _ldq_incoming_e_WIRE_bits_uop_iq_type_3; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_0 = _ldq_incoming_e_WIRE_bits_uop_fu_code_0; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_1 = _ldq_incoming_e_WIRE_bits_uop_fu_code_1; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_2 = _ldq_incoming_e_WIRE_bits_uop_fu_code_2; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_3 = _ldq_incoming_e_WIRE_bits_uop_fu_code_3; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_4 = _ldq_incoming_e_WIRE_bits_uop_fu_code_4; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_5 = _ldq_incoming_e_WIRE_bits_uop_fu_code_5; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_6 = _ldq_incoming_e_WIRE_bits_uop_fu_code_6; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_7 = _ldq_incoming_e_WIRE_bits_uop_fu_code_7; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_8 = _ldq_incoming_e_WIRE_bits_uop_fu_code_8; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_9 = _ldq_incoming_e_WIRE_bits_uop_fu_code_9; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_issued = _ldq_incoming_e_WIRE_bits_uop_iw_issued; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_issued_partial_agen = _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen = _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_iw_p1_speculative_child = _ldq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_iw_p2_speculative_child = _ldq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint = _ldq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint = _ldq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint = _ldq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_dis_col_sel = _ldq_incoming_e_WIRE_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :501:48] wire [11:0] ldq_incoming_e_0_bits_uop_br_mask = _ldq_incoming_e_WIRE_bits_uop_br_mask; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_uop_br_tag = _ldq_incoming_e_WIRE_bits_uop_br_tag; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_uop_br_type = _ldq_incoming_e_WIRE_bits_uop_br_type; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_sfb = _ldq_incoming_e_WIRE_bits_uop_is_sfb; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_fence = _ldq_incoming_e_WIRE_bits_uop_is_fence; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_fencei = _ldq_incoming_e_WIRE_bits_uop_is_fencei; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_sfence = _ldq_incoming_e_WIRE_bits_uop_is_sfence; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_amo = _ldq_incoming_e_WIRE_bits_uop_is_amo; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_eret = _ldq_incoming_e_WIRE_bits_uop_is_eret; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_sys_pc2epc = _ldq_incoming_e_WIRE_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_rocc = _ldq_incoming_e_WIRE_bits_uop_is_rocc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_mov = _ldq_incoming_e_WIRE_bits_uop_is_mov; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_ftq_idx = _ldq_incoming_e_WIRE_bits_uop_ftq_idx; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_edge_inst = _ldq_incoming_e_WIRE_bits_uop_edge_inst; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_pc_lob = _ldq_incoming_e_WIRE_bits_uop_pc_lob; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_taken = _ldq_incoming_e_WIRE_bits_uop_taken; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_imm_rename = _ldq_incoming_e_WIRE_bits_uop_imm_rename; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_imm_sel = _ldq_incoming_e_WIRE_bits_uop_imm_sel; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_pimm = _ldq_incoming_e_WIRE_bits_uop_pimm; // @[lsu.scala:321:49, :501:48] wire [19:0] ldq_incoming_e_0_bits_uop_imm_packed = _ldq_incoming_e_WIRE_bits_uop_imm_packed; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_op1_sel = _ldq_incoming_e_WIRE_bits_uop_op1_sel; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_op2_sel = _ldq_incoming_e_WIRE_bits_uop_op2_sel; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ldst = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_wen = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ren1 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ren2 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ren3 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_swap12 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_swap23 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_fromint = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_toint = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_fma = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_div = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_wflags = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_vec = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_rob_idx = _ldq_incoming_e_WIRE_bits_uop_rob_idx; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_uop_ldq_idx = _ldq_incoming_e_WIRE_bits_uop_ldq_idx; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_uop_stq_idx = _ldq_incoming_e_WIRE_bits_uop_stq_idx; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_rxq_idx = _ldq_incoming_e_WIRE_bits_uop_rxq_idx; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_pdst = _ldq_incoming_e_WIRE_bits_uop_pdst; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_prs1 = _ldq_incoming_e_WIRE_bits_uop_prs1; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_prs2 = _ldq_incoming_e_WIRE_bits_uop_prs2; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_prs3 = _ldq_incoming_e_WIRE_bits_uop_prs3; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_ppred = _ldq_incoming_e_WIRE_bits_uop_ppred; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_prs1_busy = _ldq_incoming_e_WIRE_bits_uop_prs1_busy; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_prs2_busy = _ldq_incoming_e_WIRE_bits_uop_prs2_busy; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_prs3_busy = _ldq_incoming_e_WIRE_bits_uop_prs3_busy; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_ppred_busy = _ldq_incoming_e_WIRE_bits_uop_ppred_busy; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_stale_pdst = _ldq_incoming_e_WIRE_bits_uop_stale_pdst; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_exception = _ldq_incoming_e_WIRE_bits_uop_exception; // @[lsu.scala:321:49, :501:48] wire [63:0] ldq_incoming_e_0_bits_uop_exc_cause = _ldq_incoming_e_WIRE_bits_uop_exc_cause; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_mem_cmd = _ldq_incoming_e_WIRE_bits_uop_mem_cmd; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_mem_size = _ldq_incoming_e_WIRE_bits_uop_mem_size; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_mem_signed = _ldq_incoming_e_WIRE_bits_uop_mem_signed; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_uses_ldq = _ldq_incoming_e_WIRE_bits_uop_uses_ldq; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_uses_stq = _ldq_incoming_e_WIRE_bits_uop_uses_stq; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_unique = _ldq_incoming_e_WIRE_bits_uop_is_unique; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_flush_on_commit = _ldq_incoming_e_WIRE_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_csr_cmd = _ldq_incoming_e_WIRE_bits_uop_csr_cmd; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_ldst_is_rs1 = _ldq_incoming_e_WIRE_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_ldst = _ldq_incoming_e_WIRE_bits_uop_ldst; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_lrs1 = _ldq_incoming_e_WIRE_bits_uop_lrs1; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_lrs2 = _ldq_incoming_e_WIRE_bits_uop_lrs2; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_lrs3 = _ldq_incoming_e_WIRE_bits_uop_lrs3; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_dst_rtype = _ldq_incoming_e_WIRE_bits_uop_dst_rtype; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_lrs1_rtype = _ldq_incoming_e_WIRE_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_lrs2_rtype = _ldq_incoming_e_WIRE_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_frs3_en = _ldq_incoming_e_WIRE_bits_uop_frs3_en; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fcn_dw = _ldq_incoming_e_WIRE_bits_uop_fcn_dw; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_fcn_op = _ldq_incoming_e_WIRE_bits_uop_fcn_op; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_val = _ldq_incoming_e_WIRE_bits_uop_fp_val; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_fp_rm = _ldq_incoming_e_WIRE_bits_uop_fp_rm; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_fp_typ = _ldq_incoming_e_WIRE_bits_uop_fp_typ; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_xcpt_pf_if = _ldq_incoming_e_WIRE_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_xcpt_ae_if = _ldq_incoming_e_WIRE_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_xcpt_ma_if = _ldq_incoming_e_WIRE_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_bp_debug_if = _ldq_incoming_e_WIRE_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_bp_xcpt_if = _ldq_incoming_e_WIRE_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_debug_fsrc = _ldq_incoming_e_WIRE_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_debug_tsrc = _ldq_incoming_e_WIRE_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_addr_valid = _ldq_incoming_e_WIRE_bits_addr_valid; // @[lsu.scala:321:49, :501:48] wire [39:0] ldq_incoming_e_0_bits_addr_bits = _ldq_incoming_e_WIRE_bits_addr_bits; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_addr_is_virtual = _ldq_incoming_e_WIRE_bits_addr_is_virtual; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_addr_is_uncacheable = _ldq_incoming_e_WIRE_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_executed = _ldq_incoming_e_WIRE_bits_executed; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_succeeded = _ldq_incoming_e_WIRE_bits_succeeded; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_order_fail = _ldq_incoming_e_WIRE_bits_order_fail; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_observed = _ldq_incoming_e_WIRE_bits_observed; // @[lsu.scala:321:49, :501:48] wire [15:0] ldq_incoming_e_0_bits_st_dep_mask = _ldq_incoming_e_WIRE_bits_st_dep_mask; // @[lsu.scala:321:49, :501:48] wire [7:0] ldq_incoming_e_0_bits_ld_byte_mask = _ldq_incoming_e_WIRE_bits_ld_byte_mask; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_forward_std_val = _ldq_incoming_e_WIRE_bits_forward_std_val; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_forward_stq_idx = _ldq_incoming_e_WIRE_bits_forward_stq_idx; // @[lsu.scala:321:49, :501:48] wire [63:0] ldq_incoming_e_0_bits_debug_wb_data = _ldq_incoming_e_WIRE_bits_debug_wb_data; // @[lsu.scala:321:49, :501:48] wire [31:0] mem_ldq_incoming_e_out_bits_uop_inst = ldq_incoming_e_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_ldq_incoming_e_out_bits_uop_debug_inst = ldq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_rvc = ldq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_ldq_incoming_e_out_bits_uop_debug_pc = ldq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_0 = ldq_incoming_e_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_1 = ldq_incoming_e_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_2 = ldq_incoming_e_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_3 = ldq_incoming_e_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_0 = ldq_incoming_e_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_1 = ldq_incoming_e_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_2 = ldq_incoming_e_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_3 = ldq_incoming_e_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_4 = ldq_incoming_e_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_5 = ldq_incoming_e_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_6 = ldq_incoming_e_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_7 = ldq_incoming_e_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_8 = ldq_incoming_e_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_9 = ldq_incoming_e_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_issued = ldq_incoming_e_0_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_agen = ldq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_dgen = ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_iw_p1_speculative_child = ldq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_iw_p2_speculative_child = ldq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p1_bypass_hint = ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p2_bypass_hint = ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p3_bypass_hint = ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_dis_col_sel = ldq_incoming_e_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_br_tag = ldq_incoming_e_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_br_type = ldq_incoming_e_0_bits_uop_br_type; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_sfb = ldq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_fence = ldq_incoming_e_0_bits_uop_is_fence; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_fencei = ldq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_sfence = ldq_incoming_e_0_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_amo = ldq_incoming_e_0_bits_uop_is_amo; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_eret = ldq_incoming_e_0_bits_uop_is_eret; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc = ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_rocc = ldq_incoming_e_0_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_mov = ldq_incoming_e_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ftq_idx = ldq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_edge_inst = ldq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_pc_lob = ldq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_taken = ldq_incoming_e_0_bits_uop_taken; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_imm_rename = ldq_incoming_e_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_imm_sel = ldq_incoming_e_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_pimm = ldq_incoming_e_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_ldq_incoming_e_out_bits_uop_imm_packed = ldq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_op1_sel = ldq_incoming_e_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_op2_sel = ldq_incoming_e_0_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ldst = ldq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wen = ldq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren1 = ldq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren2 = ldq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren3 = ldq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap12 = ldq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap23 = ldq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn = ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut = ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fromint = ldq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_toint = ldq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fastpipe = ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fma = ldq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_div = ldq_incoming_e_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_sqrt = ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wflags = ldq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_vec = ldq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_rob_idx = ldq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_ldq_idx = ldq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_stq_idx = ldq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_rxq_idx = ldq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_pdst = ldq_incoming_e_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs1 = ldq_incoming_e_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs2 = ldq_incoming_e_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs3 = ldq_incoming_e_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ppred = ldq_incoming_e_0_bits_uop_ppred; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_prs1_busy = ldq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_prs2_busy = ldq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_prs3_busy = ldq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_ppred_busy = ldq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_stale_pdst = ldq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_exception = ldq_incoming_e_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_ldq_incoming_e_out_bits_uop_exc_cause = ldq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_mem_cmd = ldq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_mem_size = ldq_incoming_e_0_bits_uop_mem_size; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_mem_signed = ldq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_uses_ldq = ldq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_uses_stq = ldq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_unique = ldq_incoming_e_0_bits_uop_is_unique; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_flush_on_commit = ldq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_csr_cmd = ldq_incoming_e_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1 = ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_ldst = ldq_incoming_e_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs1 = ldq_incoming_e_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs2 = ldq_incoming_e_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs3 = ldq_incoming_e_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_dst_rtype = ldq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs1_rtype = ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs2_rtype = ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_frs3_en = ldq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fcn_dw = ldq_incoming_e_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_fcn_op = ldq_incoming_e_0_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_val = ldq_incoming_e_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_fp_rm = ldq_incoming_e_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_fp_typ = ldq_incoming_e_0_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if = ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if = ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if = ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_bp_debug_if = ldq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if = ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_debug_fsrc = ldq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_debug_tsrc = ldq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_addr_valid = ldq_incoming_e_0_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_ldq_incoming_e_out_bits_addr_bits = ldq_incoming_e_0_bits_addr_bits; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_addr_is_virtual = ldq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_addr_is_uncacheable = ldq_incoming_e_0_bits_addr_is_uncacheable; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_executed = ldq_incoming_e_0_bits_executed; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_succeeded = ldq_incoming_e_0_bits_succeeded; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_order_fail = ldq_incoming_e_0_bits_order_fail; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_observed = ldq_incoming_e_0_bits_observed; // @[util.scala:114:23] wire [15:0] mem_ldq_incoming_e_out_bits_st_dep_mask = ldq_incoming_e_0_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] mem_ldq_incoming_e_out_bits_ld_byte_mask = ldq_incoming_e_0_bits_ld_byte_mask; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_forward_std_val = ldq_incoming_e_0_bits_forward_std_val; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_forward_stq_idx = ldq_incoming_e_0_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] mem_ldq_incoming_e_out_bits_debug_wb_data = ldq_incoming_e_0_bits_debug_wb_data; // @[util.scala:114:23] wire _stq_incoming_e_WIRE_valid = stq_incoming_e_e_valid; // @[lsu.scala:262:17, :504:48] wire [31:0] _stq_incoming_e_WIRE_bits_uop_inst = stq_incoming_e_e_bits_uop_inst; // @[lsu.scala:262:17, :504:48] wire [31:0] _stq_incoming_e_WIRE_bits_uop_debug_inst = stq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_rvc = stq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17, :504:48] wire [39:0] _stq_incoming_e_WIRE_bits_uop_debug_pc = stq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_0 = stq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_1 = stq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_2 = stq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_3 = stq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_0 = stq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_1 = stq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_2 = stq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_3 = stq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_4 = stq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_5 = stq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_6 = stq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_7 = stq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_8 = stq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_9 = stq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_issued = stq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen = stq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen = stq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child = stq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child = stq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint = stq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint = stq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint = stq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_dis_col_sel = stq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17, :504:48] wire [11:0] _stq_incoming_e_WIRE_bits_uop_br_mask = stq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:262:17, :504:48] wire [3:0] _stq_incoming_e_WIRE_bits_uop_br_tag = stq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:262:17, :504:48] wire [3:0] _stq_incoming_e_WIRE_bits_uop_br_type = stq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_sfb = stq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_fence = stq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_fencei = stq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_sfence = stq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_amo = stq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_eret = stq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_sys_pc2epc = stq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_rocc = stq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_mov = stq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_ftq_idx = stq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_edge_inst = stq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_pc_lob = stq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_taken = stq_incoming_e_e_bits_uop_taken; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_imm_rename = stq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_imm_sel = stq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_pimm = stq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:262:17, :504:48] wire [19:0] _stq_incoming_e_WIRE_bits_uop_imm_packed = stq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_op1_sel = stq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_op2_sel = stq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst = stq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wen = stq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1 = stq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2 = stq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3 = stq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12 = stq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23 = stq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn = stq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut = stq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint = stq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_toint = stq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe = stq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fma = stq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_div = stq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt = stq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags = stq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_vec = stq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_rob_idx = stq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17, :504:48] wire [3:0] _stq_incoming_e_WIRE_bits_uop_ldq_idx = stq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17, :504:48] wire [3:0] _stq_incoming_e_WIRE_bits_uop_stq_idx = stq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_rxq_idx = stq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_pdst = stq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_prs1 = stq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_prs2 = stq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_prs3 = stq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_ppred = stq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_prs1_busy = stq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_prs2_busy = stq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_prs3_busy = stq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_ppred_busy = stq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_stale_pdst = stq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_exception = stq_incoming_e_e_bits_uop_exception; // @[lsu.scala:262:17, :504:48] wire [63:0] _stq_incoming_e_WIRE_bits_uop_exc_cause = stq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_mem_cmd = stq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_mem_size = stq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_mem_signed = stq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_uses_ldq = stq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_uses_stq = stq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_unique = stq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_flush_on_commit = stq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_csr_cmd = stq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_ldst_is_rs1 = stq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_ldst = stq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_lrs1 = stq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_lrs2 = stq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_lrs3 = stq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_dst_rtype = stq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_lrs1_rtype = stq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_lrs2_rtype = stq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_frs3_en = stq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fcn_dw = stq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_fcn_op = stq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_val = stq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_fp_rm = stq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_fp_typ = stq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_xcpt_pf_if = stq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_xcpt_ae_if = stq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_xcpt_ma_if = stq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_bp_debug_if = stq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_bp_xcpt_if = stq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_debug_fsrc = stq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_debug_tsrc = stq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_addr_valid = stq_incoming_e_e_bits_addr_valid; // @[lsu.scala:262:17, :504:48] wire [39:0] _stq_incoming_e_WIRE_bits_addr_bits = stq_incoming_e_e_bits_addr_bits; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_addr_is_virtual = stq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_data_valid = stq_incoming_e_e_bits_data_valid; // @[lsu.scala:262:17, :504:48] wire [63:0] _stq_incoming_e_WIRE_bits_data_bits = stq_incoming_e_e_bits_data_bits; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_committed = stq_incoming_e_e_bits_committed; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_succeeded = stq_incoming_e_e_bits_succeeded; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_can_execute = stq_incoming_e_e_bits_can_execute; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_cleared = stq_incoming_e_e_bits_cleared; // @[lsu.scala:262:17, :504:48] wire [63:0] _stq_incoming_e_WIRE_bits_debug_wb_data = stq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:262:17, :504:48] assign stq_incoming_e_e_valid = _GEN_26[stq_incoming_idx_0]; // @[lsu.scala:262:17, :263:32, :321:49, :392:15] wire [15:0][31:0] _GEN_200 = {{stq_uop_15_inst}, {stq_uop_14_inst}, {stq_uop_13_inst}, {stq_uop_12_inst}, {stq_uop_11_inst}, {stq_uop_10_inst}, {stq_uop_9_inst}, {stq_uop_8_inst}, {stq_uop_7_inst}, {stq_uop_6_inst}, {stq_uop_5_inst}, {stq_uop_4_inst}, {stq_uop_3_inst}, {stq_uop_2_inst}, {stq_uop_1_inst}, {stq_uop_0_inst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_inst = _GEN_200[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][31:0] _GEN_201 = {{stq_uop_15_debug_inst}, {stq_uop_14_debug_inst}, {stq_uop_13_debug_inst}, {stq_uop_12_debug_inst}, {stq_uop_11_debug_inst}, {stq_uop_10_debug_inst}, {stq_uop_9_debug_inst}, {stq_uop_8_debug_inst}, {stq_uop_7_debug_inst}, {stq_uop_6_debug_inst}, {stq_uop_5_debug_inst}, {stq_uop_4_debug_inst}, {stq_uop_3_debug_inst}, {stq_uop_2_debug_inst}, {stq_uop_1_debug_inst}, {stq_uop_0_debug_inst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_inst = _GEN_201[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_202 = {{stq_uop_15_is_rvc}, {stq_uop_14_is_rvc}, {stq_uop_13_is_rvc}, {stq_uop_12_is_rvc}, {stq_uop_11_is_rvc}, {stq_uop_10_is_rvc}, {stq_uop_9_is_rvc}, {stq_uop_8_is_rvc}, {stq_uop_7_is_rvc}, {stq_uop_6_is_rvc}, {stq_uop_5_is_rvc}, {stq_uop_4_is_rvc}, {stq_uop_3_is_rvc}, {stq_uop_2_is_rvc}, {stq_uop_1_is_rvc}, {stq_uop_0_is_rvc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_rvc = _GEN_202[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][39:0] _GEN_203 = {{stq_uop_15_debug_pc}, {stq_uop_14_debug_pc}, {stq_uop_13_debug_pc}, {stq_uop_12_debug_pc}, {stq_uop_11_debug_pc}, {stq_uop_10_debug_pc}, {stq_uop_9_debug_pc}, {stq_uop_8_debug_pc}, {stq_uop_7_debug_pc}, {stq_uop_6_debug_pc}, {stq_uop_5_debug_pc}, {stq_uop_4_debug_pc}, {stq_uop_3_debug_pc}, {stq_uop_2_debug_pc}, {stq_uop_1_debug_pc}, {stq_uop_0_debug_pc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_pc = _GEN_203[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_204 = {{stq_uop_15_iq_type_0}, {stq_uop_14_iq_type_0}, {stq_uop_13_iq_type_0}, {stq_uop_12_iq_type_0}, {stq_uop_11_iq_type_0}, {stq_uop_10_iq_type_0}, {stq_uop_9_iq_type_0}, {stq_uop_8_iq_type_0}, {stq_uop_7_iq_type_0}, {stq_uop_6_iq_type_0}, {stq_uop_5_iq_type_0}, {stq_uop_4_iq_type_0}, {stq_uop_3_iq_type_0}, {stq_uop_2_iq_type_0}, {stq_uop_1_iq_type_0}, {stq_uop_0_iq_type_0}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_0 = _GEN_204[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_205 = {{stq_uop_15_iq_type_1}, {stq_uop_14_iq_type_1}, {stq_uop_13_iq_type_1}, {stq_uop_12_iq_type_1}, {stq_uop_11_iq_type_1}, {stq_uop_10_iq_type_1}, {stq_uop_9_iq_type_1}, {stq_uop_8_iq_type_1}, {stq_uop_7_iq_type_1}, {stq_uop_6_iq_type_1}, {stq_uop_5_iq_type_1}, {stq_uop_4_iq_type_1}, {stq_uop_3_iq_type_1}, {stq_uop_2_iq_type_1}, {stq_uop_1_iq_type_1}, {stq_uop_0_iq_type_1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_1 = _GEN_205[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_206 = {{stq_uop_15_iq_type_2}, {stq_uop_14_iq_type_2}, {stq_uop_13_iq_type_2}, {stq_uop_12_iq_type_2}, {stq_uop_11_iq_type_2}, {stq_uop_10_iq_type_2}, {stq_uop_9_iq_type_2}, {stq_uop_8_iq_type_2}, {stq_uop_7_iq_type_2}, {stq_uop_6_iq_type_2}, {stq_uop_5_iq_type_2}, {stq_uop_4_iq_type_2}, {stq_uop_3_iq_type_2}, {stq_uop_2_iq_type_2}, {stq_uop_1_iq_type_2}, {stq_uop_0_iq_type_2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_2 = _GEN_206[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_207 = {{stq_uop_15_iq_type_3}, {stq_uop_14_iq_type_3}, {stq_uop_13_iq_type_3}, {stq_uop_12_iq_type_3}, {stq_uop_11_iq_type_3}, {stq_uop_10_iq_type_3}, {stq_uop_9_iq_type_3}, {stq_uop_8_iq_type_3}, {stq_uop_7_iq_type_3}, {stq_uop_6_iq_type_3}, {stq_uop_5_iq_type_3}, {stq_uop_4_iq_type_3}, {stq_uop_3_iq_type_3}, {stq_uop_2_iq_type_3}, {stq_uop_1_iq_type_3}, {stq_uop_0_iq_type_3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_3 = _GEN_207[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_208 = {{stq_uop_15_fu_code_0}, {stq_uop_14_fu_code_0}, {stq_uop_13_fu_code_0}, {stq_uop_12_fu_code_0}, {stq_uop_11_fu_code_0}, {stq_uop_10_fu_code_0}, {stq_uop_9_fu_code_0}, {stq_uop_8_fu_code_0}, {stq_uop_7_fu_code_0}, {stq_uop_6_fu_code_0}, {stq_uop_5_fu_code_0}, {stq_uop_4_fu_code_0}, {stq_uop_3_fu_code_0}, {stq_uop_2_fu_code_0}, {stq_uop_1_fu_code_0}, {stq_uop_0_fu_code_0}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_0 = _GEN_208[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_209 = {{stq_uop_15_fu_code_1}, {stq_uop_14_fu_code_1}, {stq_uop_13_fu_code_1}, {stq_uop_12_fu_code_1}, {stq_uop_11_fu_code_1}, {stq_uop_10_fu_code_1}, {stq_uop_9_fu_code_1}, {stq_uop_8_fu_code_1}, {stq_uop_7_fu_code_1}, {stq_uop_6_fu_code_1}, {stq_uop_5_fu_code_1}, {stq_uop_4_fu_code_1}, {stq_uop_3_fu_code_1}, {stq_uop_2_fu_code_1}, {stq_uop_1_fu_code_1}, {stq_uop_0_fu_code_1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_1 = _GEN_209[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_210 = {{stq_uop_15_fu_code_2}, {stq_uop_14_fu_code_2}, {stq_uop_13_fu_code_2}, {stq_uop_12_fu_code_2}, {stq_uop_11_fu_code_2}, {stq_uop_10_fu_code_2}, {stq_uop_9_fu_code_2}, {stq_uop_8_fu_code_2}, {stq_uop_7_fu_code_2}, {stq_uop_6_fu_code_2}, {stq_uop_5_fu_code_2}, {stq_uop_4_fu_code_2}, {stq_uop_3_fu_code_2}, {stq_uop_2_fu_code_2}, {stq_uop_1_fu_code_2}, {stq_uop_0_fu_code_2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_2 = _GEN_210[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_211 = {{stq_uop_15_fu_code_3}, {stq_uop_14_fu_code_3}, {stq_uop_13_fu_code_3}, {stq_uop_12_fu_code_3}, {stq_uop_11_fu_code_3}, {stq_uop_10_fu_code_3}, {stq_uop_9_fu_code_3}, {stq_uop_8_fu_code_3}, {stq_uop_7_fu_code_3}, {stq_uop_6_fu_code_3}, {stq_uop_5_fu_code_3}, {stq_uop_4_fu_code_3}, {stq_uop_3_fu_code_3}, {stq_uop_2_fu_code_3}, {stq_uop_1_fu_code_3}, {stq_uop_0_fu_code_3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_3 = _GEN_211[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_212 = {{stq_uop_15_fu_code_4}, {stq_uop_14_fu_code_4}, {stq_uop_13_fu_code_4}, {stq_uop_12_fu_code_4}, {stq_uop_11_fu_code_4}, {stq_uop_10_fu_code_4}, {stq_uop_9_fu_code_4}, {stq_uop_8_fu_code_4}, {stq_uop_7_fu_code_4}, {stq_uop_6_fu_code_4}, {stq_uop_5_fu_code_4}, {stq_uop_4_fu_code_4}, {stq_uop_3_fu_code_4}, {stq_uop_2_fu_code_4}, {stq_uop_1_fu_code_4}, {stq_uop_0_fu_code_4}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_4 = _GEN_212[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_213 = {{stq_uop_15_fu_code_5}, {stq_uop_14_fu_code_5}, {stq_uop_13_fu_code_5}, {stq_uop_12_fu_code_5}, {stq_uop_11_fu_code_5}, {stq_uop_10_fu_code_5}, {stq_uop_9_fu_code_5}, {stq_uop_8_fu_code_5}, {stq_uop_7_fu_code_5}, {stq_uop_6_fu_code_5}, {stq_uop_5_fu_code_5}, {stq_uop_4_fu_code_5}, {stq_uop_3_fu_code_5}, {stq_uop_2_fu_code_5}, {stq_uop_1_fu_code_5}, {stq_uop_0_fu_code_5}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_5 = _GEN_213[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_214 = {{stq_uop_15_fu_code_6}, {stq_uop_14_fu_code_6}, {stq_uop_13_fu_code_6}, {stq_uop_12_fu_code_6}, {stq_uop_11_fu_code_6}, {stq_uop_10_fu_code_6}, {stq_uop_9_fu_code_6}, {stq_uop_8_fu_code_6}, {stq_uop_7_fu_code_6}, {stq_uop_6_fu_code_6}, {stq_uop_5_fu_code_6}, {stq_uop_4_fu_code_6}, {stq_uop_3_fu_code_6}, {stq_uop_2_fu_code_6}, {stq_uop_1_fu_code_6}, {stq_uop_0_fu_code_6}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_6 = _GEN_214[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_215 = {{stq_uop_15_fu_code_7}, {stq_uop_14_fu_code_7}, {stq_uop_13_fu_code_7}, {stq_uop_12_fu_code_7}, {stq_uop_11_fu_code_7}, {stq_uop_10_fu_code_7}, {stq_uop_9_fu_code_7}, {stq_uop_8_fu_code_7}, {stq_uop_7_fu_code_7}, {stq_uop_6_fu_code_7}, {stq_uop_5_fu_code_7}, {stq_uop_4_fu_code_7}, {stq_uop_3_fu_code_7}, {stq_uop_2_fu_code_7}, {stq_uop_1_fu_code_7}, {stq_uop_0_fu_code_7}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_7 = _GEN_215[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_216 = {{stq_uop_15_fu_code_8}, {stq_uop_14_fu_code_8}, {stq_uop_13_fu_code_8}, {stq_uop_12_fu_code_8}, {stq_uop_11_fu_code_8}, {stq_uop_10_fu_code_8}, {stq_uop_9_fu_code_8}, {stq_uop_8_fu_code_8}, {stq_uop_7_fu_code_8}, {stq_uop_6_fu_code_8}, {stq_uop_5_fu_code_8}, {stq_uop_4_fu_code_8}, {stq_uop_3_fu_code_8}, {stq_uop_2_fu_code_8}, {stq_uop_1_fu_code_8}, {stq_uop_0_fu_code_8}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_8 = _GEN_216[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_217 = {{stq_uop_15_fu_code_9}, {stq_uop_14_fu_code_9}, {stq_uop_13_fu_code_9}, {stq_uop_12_fu_code_9}, {stq_uop_11_fu_code_9}, {stq_uop_10_fu_code_9}, {stq_uop_9_fu_code_9}, {stq_uop_8_fu_code_9}, {stq_uop_7_fu_code_9}, {stq_uop_6_fu_code_9}, {stq_uop_5_fu_code_9}, {stq_uop_4_fu_code_9}, {stq_uop_3_fu_code_9}, {stq_uop_2_fu_code_9}, {stq_uop_1_fu_code_9}, {stq_uop_0_fu_code_9}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_9 = _GEN_217[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_218 = {{stq_uop_15_iw_issued}, {stq_uop_14_iw_issued}, {stq_uop_13_iw_issued}, {stq_uop_12_iw_issued}, {stq_uop_11_iw_issued}, {stq_uop_10_iw_issued}, {stq_uop_9_iw_issued}, {stq_uop_8_iw_issued}, {stq_uop_7_iw_issued}, {stq_uop_6_iw_issued}, {stq_uop_5_iw_issued}, {stq_uop_4_iw_issued}, {stq_uop_3_iw_issued}, {stq_uop_2_iw_issued}, {stq_uop_1_iw_issued}, {stq_uop_0_iw_issued}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_issued = _GEN_218[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_219 = {{stq_uop_15_iw_issued_partial_agen}, {stq_uop_14_iw_issued_partial_agen}, {stq_uop_13_iw_issued_partial_agen}, {stq_uop_12_iw_issued_partial_agen}, {stq_uop_11_iw_issued_partial_agen}, {stq_uop_10_iw_issued_partial_agen}, {stq_uop_9_iw_issued_partial_agen}, {stq_uop_8_iw_issued_partial_agen}, {stq_uop_7_iw_issued_partial_agen}, {stq_uop_6_iw_issued_partial_agen}, {stq_uop_5_iw_issued_partial_agen}, {stq_uop_4_iw_issued_partial_agen}, {stq_uop_3_iw_issued_partial_agen}, {stq_uop_2_iw_issued_partial_agen}, {stq_uop_1_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_issued_partial_agen = _GEN_219[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_220 = {{stq_uop_15_iw_issued_partial_dgen}, {stq_uop_14_iw_issued_partial_dgen}, {stq_uop_13_iw_issued_partial_dgen}, {stq_uop_12_iw_issued_partial_dgen}, {stq_uop_11_iw_issued_partial_dgen}, {stq_uop_10_iw_issued_partial_dgen}, {stq_uop_9_iw_issued_partial_dgen}, {stq_uop_8_iw_issued_partial_dgen}, {stq_uop_7_iw_issued_partial_dgen}, {stq_uop_6_iw_issued_partial_dgen}, {stq_uop_5_iw_issued_partial_dgen}, {stq_uop_4_iw_issued_partial_dgen}, {stq_uop_3_iw_issued_partial_dgen}, {stq_uop_2_iw_issued_partial_dgen}, {stq_uop_1_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_issued_partial_dgen = _GEN_220[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_221 = {{stq_uop_15_iw_p1_speculative_child}, {stq_uop_14_iw_p1_speculative_child}, {stq_uop_13_iw_p1_speculative_child}, {stq_uop_12_iw_p1_speculative_child}, {stq_uop_11_iw_p1_speculative_child}, {stq_uop_10_iw_p1_speculative_child}, {stq_uop_9_iw_p1_speculative_child}, {stq_uop_8_iw_p1_speculative_child}, {stq_uop_7_iw_p1_speculative_child}, {stq_uop_6_iw_p1_speculative_child}, {stq_uop_5_iw_p1_speculative_child}, {stq_uop_4_iw_p1_speculative_child}, {stq_uop_3_iw_p1_speculative_child}, {stq_uop_2_iw_p1_speculative_child}, {stq_uop_1_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p1_speculative_child = _GEN_221[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_222 = {{stq_uop_15_iw_p2_speculative_child}, {stq_uop_14_iw_p2_speculative_child}, {stq_uop_13_iw_p2_speculative_child}, {stq_uop_12_iw_p2_speculative_child}, {stq_uop_11_iw_p2_speculative_child}, {stq_uop_10_iw_p2_speculative_child}, {stq_uop_9_iw_p2_speculative_child}, {stq_uop_8_iw_p2_speculative_child}, {stq_uop_7_iw_p2_speculative_child}, {stq_uop_6_iw_p2_speculative_child}, {stq_uop_5_iw_p2_speculative_child}, {stq_uop_4_iw_p2_speculative_child}, {stq_uop_3_iw_p2_speculative_child}, {stq_uop_2_iw_p2_speculative_child}, {stq_uop_1_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p2_speculative_child = _GEN_222[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_223 = {{stq_uop_15_iw_p1_bypass_hint}, {stq_uop_14_iw_p1_bypass_hint}, {stq_uop_13_iw_p1_bypass_hint}, {stq_uop_12_iw_p1_bypass_hint}, {stq_uop_11_iw_p1_bypass_hint}, {stq_uop_10_iw_p1_bypass_hint}, {stq_uop_9_iw_p1_bypass_hint}, {stq_uop_8_iw_p1_bypass_hint}, {stq_uop_7_iw_p1_bypass_hint}, {stq_uop_6_iw_p1_bypass_hint}, {stq_uop_5_iw_p1_bypass_hint}, {stq_uop_4_iw_p1_bypass_hint}, {stq_uop_3_iw_p1_bypass_hint}, {stq_uop_2_iw_p1_bypass_hint}, {stq_uop_1_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p1_bypass_hint = _GEN_223[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_224 = {{stq_uop_15_iw_p2_bypass_hint}, {stq_uop_14_iw_p2_bypass_hint}, {stq_uop_13_iw_p2_bypass_hint}, {stq_uop_12_iw_p2_bypass_hint}, {stq_uop_11_iw_p2_bypass_hint}, {stq_uop_10_iw_p2_bypass_hint}, {stq_uop_9_iw_p2_bypass_hint}, {stq_uop_8_iw_p2_bypass_hint}, {stq_uop_7_iw_p2_bypass_hint}, {stq_uop_6_iw_p2_bypass_hint}, {stq_uop_5_iw_p2_bypass_hint}, {stq_uop_4_iw_p2_bypass_hint}, {stq_uop_3_iw_p2_bypass_hint}, {stq_uop_2_iw_p2_bypass_hint}, {stq_uop_1_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p2_bypass_hint = _GEN_224[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_225 = {{stq_uop_15_iw_p3_bypass_hint}, {stq_uop_14_iw_p3_bypass_hint}, {stq_uop_13_iw_p3_bypass_hint}, {stq_uop_12_iw_p3_bypass_hint}, {stq_uop_11_iw_p3_bypass_hint}, {stq_uop_10_iw_p3_bypass_hint}, {stq_uop_9_iw_p3_bypass_hint}, {stq_uop_8_iw_p3_bypass_hint}, {stq_uop_7_iw_p3_bypass_hint}, {stq_uop_6_iw_p3_bypass_hint}, {stq_uop_5_iw_p3_bypass_hint}, {stq_uop_4_iw_p3_bypass_hint}, {stq_uop_3_iw_p3_bypass_hint}, {stq_uop_2_iw_p3_bypass_hint}, {stq_uop_1_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p3_bypass_hint = _GEN_225[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_226 = {{stq_uop_15_dis_col_sel}, {stq_uop_14_dis_col_sel}, {stq_uop_13_dis_col_sel}, {stq_uop_12_dis_col_sel}, {stq_uop_11_dis_col_sel}, {stq_uop_10_dis_col_sel}, {stq_uop_9_dis_col_sel}, {stq_uop_8_dis_col_sel}, {stq_uop_7_dis_col_sel}, {stq_uop_6_dis_col_sel}, {stq_uop_5_dis_col_sel}, {stq_uop_4_dis_col_sel}, {stq_uop_3_dis_col_sel}, {stq_uop_2_dis_col_sel}, {stq_uop_1_dis_col_sel}, {stq_uop_0_dis_col_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_dis_col_sel = _GEN_226[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][11:0] _GEN_227 = {{stq_uop_15_br_mask}, {stq_uop_14_br_mask}, {stq_uop_13_br_mask}, {stq_uop_12_br_mask}, {stq_uop_11_br_mask}, {stq_uop_10_br_mask}, {stq_uop_9_br_mask}, {stq_uop_8_br_mask}, {stq_uop_7_br_mask}, {stq_uop_6_br_mask}, {stq_uop_5_br_mask}, {stq_uop_4_br_mask}, {stq_uop_3_br_mask}, {stq_uop_2_br_mask}, {stq_uop_1_br_mask}, {stq_uop_0_br_mask}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_br_mask = _GEN_227[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][3:0] _GEN_228 = {{stq_uop_15_br_tag}, {stq_uop_14_br_tag}, {stq_uop_13_br_tag}, {stq_uop_12_br_tag}, {stq_uop_11_br_tag}, {stq_uop_10_br_tag}, {stq_uop_9_br_tag}, {stq_uop_8_br_tag}, {stq_uop_7_br_tag}, {stq_uop_6_br_tag}, {stq_uop_5_br_tag}, {stq_uop_4_br_tag}, {stq_uop_3_br_tag}, {stq_uop_2_br_tag}, {stq_uop_1_br_tag}, {stq_uop_0_br_tag}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_br_tag = _GEN_228[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][3:0] _GEN_229 = {{stq_uop_15_br_type}, {stq_uop_14_br_type}, {stq_uop_13_br_type}, {stq_uop_12_br_type}, {stq_uop_11_br_type}, {stq_uop_10_br_type}, {stq_uop_9_br_type}, {stq_uop_8_br_type}, {stq_uop_7_br_type}, {stq_uop_6_br_type}, {stq_uop_5_br_type}, {stq_uop_4_br_type}, {stq_uop_3_br_type}, {stq_uop_2_br_type}, {stq_uop_1_br_type}, {stq_uop_0_br_type}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_br_type = _GEN_229[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_230 = {{stq_uop_15_is_sfb}, {stq_uop_14_is_sfb}, {stq_uop_13_is_sfb}, {stq_uop_12_is_sfb}, {stq_uop_11_is_sfb}, {stq_uop_10_is_sfb}, {stq_uop_9_is_sfb}, {stq_uop_8_is_sfb}, {stq_uop_7_is_sfb}, {stq_uop_6_is_sfb}, {stq_uop_5_is_sfb}, {stq_uop_4_is_sfb}, {stq_uop_3_is_sfb}, {stq_uop_2_is_sfb}, {stq_uop_1_is_sfb}, {stq_uop_0_is_sfb}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_sfb = _GEN_230[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_231 = {{stq_uop_15_is_fence}, {stq_uop_14_is_fence}, {stq_uop_13_is_fence}, {stq_uop_12_is_fence}, {stq_uop_11_is_fence}, {stq_uop_10_is_fence}, {stq_uop_9_is_fence}, {stq_uop_8_is_fence}, {stq_uop_7_is_fence}, {stq_uop_6_is_fence}, {stq_uop_5_is_fence}, {stq_uop_4_is_fence}, {stq_uop_3_is_fence}, {stq_uop_2_is_fence}, {stq_uop_1_is_fence}, {stq_uop_0_is_fence}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_fence = _GEN_231[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_232 = {{stq_uop_15_is_fencei}, {stq_uop_14_is_fencei}, {stq_uop_13_is_fencei}, {stq_uop_12_is_fencei}, {stq_uop_11_is_fencei}, {stq_uop_10_is_fencei}, {stq_uop_9_is_fencei}, {stq_uop_8_is_fencei}, {stq_uop_7_is_fencei}, {stq_uop_6_is_fencei}, {stq_uop_5_is_fencei}, {stq_uop_4_is_fencei}, {stq_uop_3_is_fencei}, {stq_uop_2_is_fencei}, {stq_uop_1_is_fencei}, {stq_uop_0_is_fencei}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_fencei = _GEN_232[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_233 = {{stq_uop_15_is_sfence}, {stq_uop_14_is_sfence}, {stq_uop_13_is_sfence}, {stq_uop_12_is_sfence}, {stq_uop_11_is_sfence}, {stq_uop_10_is_sfence}, {stq_uop_9_is_sfence}, {stq_uop_8_is_sfence}, {stq_uop_7_is_sfence}, {stq_uop_6_is_sfence}, {stq_uop_5_is_sfence}, {stq_uop_4_is_sfence}, {stq_uop_3_is_sfence}, {stq_uop_2_is_sfence}, {stq_uop_1_is_sfence}, {stq_uop_0_is_sfence}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_sfence = _GEN_233[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_234 = {{stq_uop_15_is_amo}, {stq_uop_14_is_amo}, {stq_uop_13_is_amo}, {stq_uop_12_is_amo}, {stq_uop_11_is_amo}, {stq_uop_10_is_amo}, {stq_uop_9_is_amo}, {stq_uop_8_is_amo}, {stq_uop_7_is_amo}, {stq_uop_6_is_amo}, {stq_uop_5_is_amo}, {stq_uop_4_is_amo}, {stq_uop_3_is_amo}, {stq_uop_2_is_amo}, {stq_uop_1_is_amo}, {stq_uop_0_is_amo}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_amo = _GEN_234[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_235 = {{stq_uop_15_is_eret}, {stq_uop_14_is_eret}, {stq_uop_13_is_eret}, {stq_uop_12_is_eret}, {stq_uop_11_is_eret}, {stq_uop_10_is_eret}, {stq_uop_9_is_eret}, {stq_uop_8_is_eret}, {stq_uop_7_is_eret}, {stq_uop_6_is_eret}, {stq_uop_5_is_eret}, {stq_uop_4_is_eret}, {stq_uop_3_is_eret}, {stq_uop_2_is_eret}, {stq_uop_1_is_eret}, {stq_uop_0_is_eret}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_eret = _GEN_235[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_236 = {{stq_uop_15_is_sys_pc2epc}, {stq_uop_14_is_sys_pc2epc}, {stq_uop_13_is_sys_pc2epc}, {stq_uop_12_is_sys_pc2epc}, {stq_uop_11_is_sys_pc2epc}, {stq_uop_10_is_sys_pc2epc}, {stq_uop_9_is_sys_pc2epc}, {stq_uop_8_is_sys_pc2epc}, {stq_uop_7_is_sys_pc2epc}, {stq_uop_6_is_sys_pc2epc}, {stq_uop_5_is_sys_pc2epc}, {stq_uop_4_is_sys_pc2epc}, {stq_uop_3_is_sys_pc2epc}, {stq_uop_2_is_sys_pc2epc}, {stq_uop_1_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_sys_pc2epc = _GEN_236[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_237 = {{stq_uop_15_is_rocc}, {stq_uop_14_is_rocc}, {stq_uop_13_is_rocc}, {stq_uop_12_is_rocc}, {stq_uop_11_is_rocc}, {stq_uop_10_is_rocc}, {stq_uop_9_is_rocc}, {stq_uop_8_is_rocc}, {stq_uop_7_is_rocc}, {stq_uop_6_is_rocc}, {stq_uop_5_is_rocc}, {stq_uop_4_is_rocc}, {stq_uop_3_is_rocc}, {stq_uop_2_is_rocc}, {stq_uop_1_is_rocc}, {stq_uop_0_is_rocc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_rocc = _GEN_237[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_238 = {{stq_uop_15_is_mov}, {stq_uop_14_is_mov}, {stq_uop_13_is_mov}, {stq_uop_12_is_mov}, {stq_uop_11_is_mov}, {stq_uop_10_is_mov}, {stq_uop_9_is_mov}, {stq_uop_8_is_mov}, {stq_uop_7_is_mov}, {stq_uop_6_is_mov}, {stq_uop_5_is_mov}, {stq_uop_4_is_mov}, {stq_uop_3_is_mov}, {stq_uop_2_is_mov}, {stq_uop_1_is_mov}, {stq_uop_0_is_mov}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_mov = _GEN_238[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][4:0] _GEN_239 = {{stq_uop_15_ftq_idx}, {stq_uop_14_ftq_idx}, {stq_uop_13_ftq_idx}, {stq_uop_12_ftq_idx}, {stq_uop_11_ftq_idx}, {stq_uop_10_ftq_idx}, {stq_uop_9_ftq_idx}, {stq_uop_8_ftq_idx}, {stq_uop_7_ftq_idx}, {stq_uop_6_ftq_idx}, {stq_uop_5_ftq_idx}, {stq_uop_4_ftq_idx}, {stq_uop_3_ftq_idx}, {stq_uop_2_ftq_idx}, {stq_uop_1_ftq_idx}, {stq_uop_0_ftq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ftq_idx = _GEN_239[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_240 = {{stq_uop_15_edge_inst}, {stq_uop_14_edge_inst}, {stq_uop_13_edge_inst}, {stq_uop_12_edge_inst}, {stq_uop_11_edge_inst}, {stq_uop_10_edge_inst}, {stq_uop_9_edge_inst}, {stq_uop_8_edge_inst}, {stq_uop_7_edge_inst}, {stq_uop_6_edge_inst}, {stq_uop_5_edge_inst}, {stq_uop_4_edge_inst}, {stq_uop_3_edge_inst}, {stq_uop_2_edge_inst}, {stq_uop_1_edge_inst}, {stq_uop_0_edge_inst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_edge_inst = _GEN_240[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][5:0] _GEN_241 = {{stq_uop_15_pc_lob}, {stq_uop_14_pc_lob}, {stq_uop_13_pc_lob}, {stq_uop_12_pc_lob}, {stq_uop_11_pc_lob}, {stq_uop_10_pc_lob}, {stq_uop_9_pc_lob}, {stq_uop_8_pc_lob}, {stq_uop_7_pc_lob}, {stq_uop_6_pc_lob}, {stq_uop_5_pc_lob}, {stq_uop_4_pc_lob}, {stq_uop_3_pc_lob}, {stq_uop_2_pc_lob}, {stq_uop_1_pc_lob}, {stq_uop_0_pc_lob}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_pc_lob = _GEN_241[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_242 = {{stq_uop_15_taken}, {stq_uop_14_taken}, {stq_uop_13_taken}, {stq_uop_12_taken}, {stq_uop_11_taken}, {stq_uop_10_taken}, {stq_uop_9_taken}, {stq_uop_8_taken}, {stq_uop_7_taken}, {stq_uop_6_taken}, {stq_uop_5_taken}, {stq_uop_4_taken}, {stq_uop_3_taken}, {stq_uop_2_taken}, {stq_uop_1_taken}, {stq_uop_0_taken}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_taken = _GEN_242[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_243 = {{stq_uop_15_imm_rename}, {stq_uop_14_imm_rename}, {stq_uop_13_imm_rename}, {stq_uop_12_imm_rename}, {stq_uop_11_imm_rename}, {stq_uop_10_imm_rename}, {stq_uop_9_imm_rename}, {stq_uop_8_imm_rename}, {stq_uop_7_imm_rename}, {stq_uop_6_imm_rename}, {stq_uop_5_imm_rename}, {stq_uop_4_imm_rename}, {stq_uop_3_imm_rename}, {stq_uop_2_imm_rename}, {stq_uop_1_imm_rename}, {stq_uop_0_imm_rename}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_imm_rename = _GEN_243[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][2:0] _GEN_244 = {{stq_uop_15_imm_sel}, {stq_uop_14_imm_sel}, {stq_uop_13_imm_sel}, {stq_uop_12_imm_sel}, {stq_uop_11_imm_sel}, {stq_uop_10_imm_sel}, {stq_uop_9_imm_sel}, {stq_uop_8_imm_sel}, {stq_uop_7_imm_sel}, {stq_uop_6_imm_sel}, {stq_uop_5_imm_sel}, {stq_uop_4_imm_sel}, {stq_uop_3_imm_sel}, {stq_uop_2_imm_sel}, {stq_uop_1_imm_sel}, {stq_uop_0_imm_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_imm_sel = _GEN_244[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][4:0] _GEN_245 = {{stq_uop_15_pimm}, {stq_uop_14_pimm}, {stq_uop_13_pimm}, {stq_uop_12_pimm}, {stq_uop_11_pimm}, {stq_uop_10_pimm}, {stq_uop_9_pimm}, {stq_uop_8_pimm}, {stq_uop_7_pimm}, {stq_uop_6_pimm}, {stq_uop_5_pimm}, {stq_uop_4_pimm}, {stq_uop_3_pimm}, {stq_uop_2_pimm}, {stq_uop_1_pimm}, {stq_uop_0_pimm}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_pimm = _GEN_245[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][19:0] _GEN_246 = {{stq_uop_15_imm_packed}, {stq_uop_14_imm_packed}, {stq_uop_13_imm_packed}, {stq_uop_12_imm_packed}, {stq_uop_11_imm_packed}, {stq_uop_10_imm_packed}, {stq_uop_9_imm_packed}, {stq_uop_8_imm_packed}, {stq_uop_7_imm_packed}, {stq_uop_6_imm_packed}, {stq_uop_5_imm_packed}, {stq_uop_4_imm_packed}, {stq_uop_3_imm_packed}, {stq_uop_2_imm_packed}, {stq_uop_1_imm_packed}, {stq_uop_0_imm_packed}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_imm_packed = _GEN_246[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_247 = {{stq_uop_15_op1_sel}, {stq_uop_14_op1_sel}, {stq_uop_13_op1_sel}, {stq_uop_12_op1_sel}, {stq_uop_11_op1_sel}, {stq_uop_10_op1_sel}, {stq_uop_9_op1_sel}, {stq_uop_8_op1_sel}, {stq_uop_7_op1_sel}, {stq_uop_6_op1_sel}, {stq_uop_5_op1_sel}, {stq_uop_4_op1_sel}, {stq_uop_3_op1_sel}, {stq_uop_2_op1_sel}, {stq_uop_1_op1_sel}, {stq_uop_0_op1_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_op1_sel = _GEN_247[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][2:0] _GEN_248 = {{stq_uop_15_op2_sel}, {stq_uop_14_op2_sel}, {stq_uop_13_op2_sel}, {stq_uop_12_op2_sel}, {stq_uop_11_op2_sel}, {stq_uop_10_op2_sel}, {stq_uop_9_op2_sel}, {stq_uop_8_op2_sel}, {stq_uop_7_op2_sel}, {stq_uop_6_op2_sel}, {stq_uop_5_op2_sel}, {stq_uop_4_op2_sel}, {stq_uop_3_op2_sel}, {stq_uop_2_op2_sel}, {stq_uop_1_op2_sel}, {stq_uop_0_op2_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_op2_sel = _GEN_248[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_249 = {{stq_uop_15_fp_ctrl_ldst}, {stq_uop_14_fp_ctrl_ldst}, {stq_uop_13_fp_ctrl_ldst}, {stq_uop_12_fp_ctrl_ldst}, {stq_uop_11_fp_ctrl_ldst}, {stq_uop_10_fp_ctrl_ldst}, {stq_uop_9_fp_ctrl_ldst}, {stq_uop_8_fp_ctrl_ldst}, {stq_uop_7_fp_ctrl_ldst}, {stq_uop_6_fp_ctrl_ldst}, {stq_uop_5_fp_ctrl_ldst}, {stq_uop_4_fp_ctrl_ldst}, {stq_uop_3_fp_ctrl_ldst}, {stq_uop_2_fp_ctrl_ldst}, {stq_uop_1_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ldst = _GEN_249[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_250 = {{stq_uop_15_fp_ctrl_wen}, {stq_uop_14_fp_ctrl_wen}, {stq_uop_13_fp_ctrl_wen}, {stq_uop_12_fp_ctrl_wen}, {stq_uop_11_fp_ctrl_wen}, {stq_uop_10_fp_ctrl_wen}, {stq_uop_9_fp_ctrl_wen}, {stq_uop_8_fp_ctrl_wen}, {stq_uop_7_fp_ctrl_wen}, {stq_uop_6_fp_ctrl_wen}, {stq_uop_5_fp_ctrl_wen}, {stq_uop_4_fp_ctrl_wen}, {stq_uop_3_fp_ctrl_wen}, {stq_uop_2_fp_ctrl_wen}, {stq_uop_1_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_wen = _GEN_250[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_251 = {{stq_uop_15_fp_ctrl_ren1}, {stq_uop_14_fp_ctrl_ren1}, {stq_uop_13_fp_ctrl_ren1}, {stq_uop_12_fp_ctrl_ren1}, {stq_uop_11_fp_ctrl_ren1}, {stq_uop_10_fp_ctrl_ren1}, {stq_uop_9_fp_ctrl_ren1}, {stq_uop_8_fp_ctrl_ren1}, {stq_uop_7_fp_ctrl_ren1}, {stq_uop_6_fp_ctrl_ren1}, {stq_uop_5_fp_ctrl_ren1}, {stq_uop_4_fp_ctrl_ren1}, {stq_uop_3_fp_ctrl_ren1}, {stq_uop_2_fp_ctrl_ren1}, {stq_uop_1_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ren1 = _GEN_251[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_252 = {{stq_uop_15_fp_ctrl_ren2}, {stq_uop_14_fp_ctrl_ren2}, {stq_uop_13_fp_ctrl_ren2}, {stq_uop_12_fp_ctrl_ren2}, {stq_uop_11_fp_ctrl_ren2}, {stq_uop_10_fp_ctrl_ren2}, {stq_uop_9_fp_ctrl_ren2}, {stq_uop_8_fp_ctrl_ren2}, {stq_uop_7_fp_ctrl_ren2}, {stq_uop_6_fp_ctrl_ren2}, {stq_uop_5_fp_ctrl_ren2}, {stq_uop_4_fp_ctrl_ren2}, {stq_uop_3_fp_ctrl_ren2}, {stq_uop_2_fp_ctrl_ren2}, {stq_uop_1_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ren2 = _GEN_252[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_253 = {{stq_uop_15_fp_ctrl_ren3}, {stq_uop_14_fp_ctrl_ren3}, {stq_uop_13_fp_ctrl_ren3}, {stq_uop_12_fp_ctrl_ren3}, {stq_uop_11_fp_ctrl_ren3}, {stq_uop_10_fp_ctrl_ren3}, {stq_uop_9_fp_ctrl_ren3}, {stq_uop_8_fp_ctrl_ren3}, {stq_uop_7_fp_ctrl_ren3}, {stq_uop_6_fp_ctrl_ren3}, {stq_uop_5_fp_ctrl_ren3}, {stq_uop_4_fp_ctrl_ren3}, {stq_uop_3_fp_ctrl_ren3}, {stq_uop_2_fp_ctrl_ren3}, {stq_uop_1_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ren3 = _GEN_253[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_254 = {{stq_uop_15_fp_ctrl_swap12}, {stq_uop_14_fp_ctrl_swap12}, {stq_uop_13_fp_ctrl_swap12}, {stq_uop_12_fp_ctrl_swap12}, {stq_uop_11_fp_ctrl_swap12}, {stq_uop_10_fp_ctrl_swap12}, {stq_uop_9_fp_ctrl_swap12}, {stq_uop_8_fp_ctrl_swap12}, {stq_uop_7_fp_ctrl_swap12}, {stq_uop_6_fp_ctrl_swap12}, {stq_uop_5_fp_ctrl_swap12}, {stq_uop_4_fp_ctrl_swap12}, {stq_uop_3_fp_ctrl_swap12}, {stq_uop_2_fp_ctrl_swap12}, {stq_uop_1_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_swap12 = _GEN_254[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_255 = {{stq_uop_15_fp_ctrl_swap23}, {stq_uop_14_fp_ctrl_swap23}, {stq_uop_13_fp_ctrl_swap23}, {stq_uop_12_fp_ctrl_swap23}, {stq_uop_11_fp_ctrl_swap23}, {stq_uop_10_fp_ctrl_swap23}, {stq_uop_9_fp_ctrl_swap23}, {stq_uop_8_fp_ctrl_swap23}, {stq_uop_7_fp_ctrl_swap23}, {stq_uop_6_fp_ctrl_swap23}, {stq_uop_5_fp_ctrl_swap23}, {stq_uop_4_fp_ctrl_swap23}, {stq_uop_3_fp_ctrl_swap23}, {stq_uop_2_fp_ctrl_swap23}, {stq_uop_1_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_swap23 = _GEN_255[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_256 = {{stq_uop_15_fp_ctrl_typeTagIn}, {stq_uop_14_fp_ctrl_typeTagIn}, {stq_uop_13_fp_ctrl_typeTagIn}, {stq_uop_12_fp_ctrl_typeTagIn}, {stq_uop_11_fp_ctrl_typeTagIn}, {stq_uop_10_fp_ctrl_typeTagIn}, {stq_uop_9_fp_ctrl_typeTagIn}, {stq_uop_8_fp_ctrl_typeTagIn}, {stq_uop_7_fp_ctrl_typeTagIn}, {stq_uop_6_fp_ctrl_typeTagIn}, {stq_uop_5_fp_ctrl_typeTagIn}, {stq_uop_4_fp_ctrl_typeTagIn}, {stq_uop_3_fp_ctrl_typeTagIn}, {stq_uop_2_fp_ctrl_typeTagIn}, {stq_uop_1_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_256[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_257 = {{stq_uop_15_fp_ctrl_typeTagOut}, {stq_uop_14_fp_ctrl_typeTagOut}, {stq_uop_13_fp_ctrl_typeTagOut}, {stq_uop_12_fp_ctrl_typeTagOut}, {stq_uop_11_fp_ctrl_typeTagOut}, {stq_uop_10_fp_ctrl_typeTagOut}, {stq_uop_9_fp_ctrl_typeTagOut}, {stq_uop_8_fp_ctrl_typeTagOut}, {stq_uop_7_fp_ctrl_typeTagOut}, {stq_uop_6_fp_ctrl_typeTagOut}, {stq_uop_5_fp_ctrl_typeTagOut}, {stq_uop_4_fp_ctrl_typeTagOut}, {stq_uop_3_fp_ctrl_typeTagOut}, {stq_uop_2_fp_ctrl_typeTagOut}, {stq_uop_1_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_257[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_258 = {{stq_uop_15_fp_ctrl_fromint}, {stq_uop_14_fp_ctrl_fromint}, {stq_uop_13_fp_ctrl_fromint}, {stq_uop_12_fp_ctrl_fromint}, {stq_uop_11_fp_ctrl_fromint}, {stq_uop_10_fp_ctrl_fromint}, {stq_uop_9_fp_ctrl_fromint}, {stq_uop_8_fp_ctrl_fromint}, {stq_uop_7_fp_ctrl_fromint}, {stq_uop_6_fp_ctrl_fromint}, {stq_uop_5_fp_ctrl_fromint}, {stq_uop_4_fp_ctrl_fromint}, {stq_uop_3_fp_ctrl_fromint}, {stq_uop_2_fp_ctrl_fromint}, {stq_uop_1_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_fromint = _GEN_258[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_259 = {{stq_uop_15_fp_ctrl_toint}, {stq_uop_14_fp_ctrl_toint}, {stq_uop_13_fp_ctrl_toint}, {stq_uop_12_fp_ctrl_toint}, {stq_uop_11_fp_ctrl_toint}, {stq_uop_10_fp_ctrl_toint}, {stq_uop_9_fp_ctrl_toint}, {stq_uop_8_fp_ctrl_toint}, {stq_uop_7_fp_ctrl_toint}, {stq_uop_6_fp_ctrl_toint}, {stq_uop_5_fp_ctrl_toint}, {stq_uop_4_fp_ctrl_toint}, {stq_uop_3_fp_ctrl_toint}, {stq_uop_2_fp_ctrl_toint}, {stq_uop_1_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_toint = _GEN_259[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_260 = {{stq_uop_15_fp_ctrl_fastpipe}, {stq_uop_14_fp_ctrl_fastpipe}, {stq_uop_13_fp_ctrl_fastpipe}, {stq_uop_12_fp_ctrl_fastpipe}, {stq_uop_11_fp_ctrl_fastpipe}, {stq_uop_10_fp_ctrl_fastpipe}, {stq_uop_9_fp_ctrl_fastpipe}, {stq_uop_8_fp_ctrl_fastpipe}, {stq_uop_7_fp_ctrl_fastpipe}, {stq_uop_6_fp_ctrl_fastpipe}, {stq_uop_5_fp_ctrl_fastpipe}, {stq_uop_4_fp_ctrl_fastpipe}, {stq_uop_3_fp_ctrl_fastpipe}, {stq_uop_2_fp_ctrl_fastpipe}, {stq_uop_1_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_260[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_261 = {{stq_uop_15_fp_ctrl_fma}, {stq_uop_14_fp_ctrl_fma}, {stq_uop_13_fp_ctrl_fma}, {stq_uop_12_fp_ctrl_fma}, {stq_uop_11_fp_ctrl_fma}, {stq_uop_10_fp_ctrl_fma}, {stq_uop_9_fp_ctrl_fma}, {stq_uop_8_fp_ctrl_fma}, {stq_uop_7_fp_ctrl_fma}, {stq_uop_6_fp_ctrl_fma}, {stq_uop_5_fp_ctrl_fma}, {stq_uop_4_fp_ctrl_fma}, {stq_uop_3_fp_ctrl_fma}, {stq_uop_2_fp_ctrl_fma}, {stq_uop_1_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_fma = _GEN_261[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_262 = {{stq_uop_15_fp_ctrl_div}, {stq_uop_14_fp_ctrl_div}, {stq_uop_13_fp_ctrl_div}, {stq_uop_12_fp_ctrl_div}, {stq_uop_11_fp_ctrl_div}, {stq_uop_10_fp_ctrl_div}, {stq_uop_9_fp_ctrl_div}, {stq_uop_8_fp_ctrl_div}, {stq_uop_7_fp_ctrl_div}, {stq_uop_6_fp_ctrl_div}, {stq_uop_5_fp_ctrl_div}, {stq_uop_4_fp_ctrl_div}, {stq_uop_3_fp_ctrl_div}, {stq_uop_2_fp_ctrl_div}, {stq_uop_1_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_div = _GEN_262[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_263 = {{stq_uop_15_fp_ctrl_sqrt}, {stq_uop_14_fp_ctrl_sqrt}, {stq_uop_13_fp_ctrl_sqrt}, {stq_uop_12_fp_ctrl_sqrt}, {stq_uop_11_fp_ctrl_sqrt}, {stq_uop_10_fp_ctrl_sqrt}, {stq_uop_9_fp_ctrl_sqrt}, {stq_uop_8_fp_ctrl_sqrt}, {stq_uop_7_fp_ctrl_sqrt}, {stq_uop_6_fp_ctrl_sqrt}, {stq_uop_5_fp_ctrl_sqrt}, {stq_uop_4_fp_ctrl_sqrt}, {stq_uop_3_fp_ctrl_sqrt}, {stq_uop_2_fp_ctrl_sqrt}, {stq_uop_1_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_sqrt = _GEN_263[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_264 = {{stq_uop_15_fp_ctrl_wflags}, {stq_uop_14_fp_ctrl_wflags}, {stq_uop_13_fp_ctrl_wflags}, {stq_uop_12_fp_ctrl_wflags}, {stq_uop_11_fp_ctrl_wflags}, {stq_uop_10_fp_ctrl_wflags}, {stq_uop_9_fp_ctrl_wflags}, {stq_uop_8_fp_ctrl_wflags}, {stq_uop_7_fp_ctrl_wflags}, {stq_uop_6_fp_ctrl_wflags}, {stq_uop_5_fp_ctrl_wflags}, {stq_uop_4_fp_ctrl_wflags}, {stq_uop_3_fp_ctrl_wflags}, {stq_uop_2_fp_ctrl_wflags}, {stq_uop_1_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_wflags = _GEN_264[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_265 = {{stq_uop_15_fp_ctrl_vec}, {stq_uop_14_fp_ctrl_vec}, {stq_uop_13_fp_ctrl_vec}, {stq_uop_12_fp_ctrl_vec}, {stq_uop_11_fp_ctrl_vec}, {stq_uop_10_fp_ctrl_vec}, {stq_uop_9_fp_ctrl_vec}, {stq_uop_8_fp_ctrl_vec}, {stq_uop_7_fp_ctrl_vec}, {stq_uop_6_fp_ctrl_vec}, {stq_uop_5_fp_ctrl_vec}, {stq_uop_4_fp_ctrl_vec}, {stq_uop_3_fp_ctrl_vec}, {stq_uop_2_fp_ctrl_vec}, {stq_uop_1_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_vec = _GEN_265[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][5:0] _GEN_266 = {{stq_uop_15_rob_idx}, {stq_uop_14_rob_idx}, {stq_uop_13_rob_idx}, {stq_uop_12_rob_idx}, {stq_uop_11_rob_idx}, {stq_uop_10_rob_idx}, {stq_uop_9_rob_idx}, {stq_uop_8_rob_idx}, {stq_uop_7_rob_idx}, {stq_uop_6_rob_idx}, {stq_uop_5_rob_idx}, {stq_uop_4_rob_idx}, {stq_uop_3_rob_idx}, {stq_uop_2_rob_idx}, {stq_uop_1_rob_idx}, {stq_uop_0_rob_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_rob_idx = _GEN_266[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][3:0] _GEN_267 = {{stq_uop_15_ldq_idx}, {stq_uop_14_ldq_idx}, {stq_uop_13_ldq_idx}, {stq_uop_12_ldq_idx}, {stq_uop_11_ldq_idx}, {stq_uop_10_ldq_idx}, {stq_uop_9_ldq_idx}, {stq_uop_8_ldq_idx}, {stq_uop_7_ldq_idx}, {stq_uop_6_ldq_idx}, {stq_uop_5_ldq_idx}, {stq_uop_4_ldq_idx}, {stq_uop_3_ldq_idx}, {stq_uop_2_ldq_idx}, {stq_uop_1_ldq_idx}, {stq_uop_0_ldq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ldq_idx = _GEN_267[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][3:0] _GEN_268 = {{stq_uop_15_stq_idx}, {stq_uop_14_stq_idx}, {stq_uop_13_stq_idx}, {stq_uop_12_stq_idx}, {stq_uop_11_stq_idx}, {stq_uop_10_stq_idx}, {stq_uop_9_stq_idx}, {stq_uop_8_stq_idx}, {stq_uop_7_stq_idx}, {stq_uop_6_stq_idx}, {stq_uop_5_stq_idx}, {stq_uop_4_stq_idx}, {stq_uop_3_stq_idx}, {stq_uop_2_stq_idx}, {stq_uop_1_stq_idx}, {stq_uop_0_stq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_stq_idx = _GEN_268[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_269 = {{stq_uop_15_rxq_idx}, {stq_uop_14_rxq_idx}, {stq_uop_13_rxq_idx}, {stq_uop_12_rxq_idx}, {stq_uop_11_rxq_idx}, {stq_uop_10_rxq_idx}, {stq_uop_9_rxq_idx}, {stq_uop_8_rxq_idx}, {stq_uop_7_rxq_idx}, {stq_uop_6_rxq_idx}, {stq_uop_5_rxq_idx}, {stq_uop_4_rxq_idx}, {stq_uop_3_rxq_idx}, {stq_uop_2_rxq_idx}, {stq_uop_1_rxq_idx}, {stq_uop_0_rxq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_rxq_idx = _GEN_269[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][6:0] _GEN_270 = {{stq_uop_15_pdst}, {stq_uop_14_pdst}, {stq_uop_13_pdst}, {stq_uop_12_pdst}, {stq_uop_11_pdst}, {stq_uop_10_pdst}, {stq_uop_9_pdst}, {stq_uop_8_pdst}, {stq_uop_7_pdst}, {stq_uop_6_pdst}, {stq_uop_5_pdst}, {stq_uop_4_pdst}, {stq_uop_3_pdst}, {stq_uop_2_pdst}, {stq_uop_1_pdst}, {stq_uop_0_pdst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_pdst = _GEN_270[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][6:0] _GEN_271 = {{stq_uop_15_prs1}, {stq_uop_14_prs1}, {stq_uop_13_prs1}, {stq_uop_12_prs1}, {stq_uop_11_prs1}, {stq_uop_10_prs1}, {stq_uop_9_prs1}, {stq_uop_8_prs1}, {stq_uop_7_prs1}, {stq_uop_6_prs1}, {stq_uop_5_prs1}, {stq_uop_4_prs1}, {stq_uop_3_prs1}, {stq_uop_2_prs1}, {stq_uop_1_prs1}, {stq_uop_0_prs1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs1 = _GEN_271[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][6:0] _GEN_272 = {{stq_uop_15_prs2}, {stq_uop_14_prs2}, {stq_uop_13_prs2}, {stq_uop_12_prs2}, {stq_uop_11_prs2}, {stq_uop_10_prs2}, {stq_uop_9_prs2}, {stq_uop_8_prs2}, {stq_uop_7_prs2}, {stq_uop_6_prs2}, {stq_uop_5_prs2}, {stq_uop_4_prs2}, {stq_uop_3_prs2}, {stq_uop_2_prs2}, {stq_uop_1_prs2}, {stq_uop_0_prs2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs2 = _GEN_272[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][6:0] _GEN_273 = {{stq_uop_15_prs3}, {stq_uop_14_prs3}, {stq_uop_13_prs3}, {stq_uop_12_prs3}, {stq_uop_11_prs3}, {stq_uop_10_prs3}, {stq_uop_9_prs3}, {stq_uop_8_prs3}, {stq_uop_7_prs3}, {stq_uop_6_prs3}, {stq_uop_5_prs3}, {stq_uop_4_prs3}, {stq_uop_3_prs3}, {stq_uop_2_prs3}, {stq_uop_1_prs3}, {stq_uop_0_prs3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs3 = _GEN_273[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][4:0] _GEN_274 = {{stq_uop_15_ppred}, {stq_uop_14_ppred}, {stq_uop_13_ppred}, {stq_uop_12_ppred}, {stq_uop_11_ppred}, {stq_uop_10_ppred}, {stq_uop_9_ppred}, {stq_uop_8_ppred}, {stq_uop_7_ppred}, {stq_uop_6_ppred}, {stq_uop_5_ppred}, {stq_uop_4_ppred}, {stq_uop_3_ppred}, {stq_uop_2_ppred}, {stq_uop_1_ppred}, {stq_uop_0_ppred}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ppred = _GEN_274[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_275 = {{stq_uop_15_prs1_busy}, {stq_uop_14_prs1_busy}, {stq_uop_13_prs1_busy}, {stq_uop_12_prs1_busy}, {stq_uop_11_prs1_busy}, {stq_uop_10_prs1_busy}, {stq_uop_9_prs1_busy}, {stq_uop_8_prs1_busy}, {stq_uop_7_prs1_busy}, {stq_uop_6_prs1_busy}, {stq_uop_5_prs1_busy}, {stq_uop_4_prs1_busy}, {stq_uop_3_prs1_busy}, {stq_uop_2_prs1_busy}, {stq_uop_1_prs1_busy}, {stq_uop_0_prs1_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs1_busy = _GEN_275[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_276 = {{stq_uop_15_prs2_busy}, {stq_uop_14_prs2_busy}, {stq_uop_13_prs2_busy}, {stq_uop_12_prs2_busy}, {stq_uop_11_prs2_busy}, {stq_uop_10_prs2_busy}, {stq_uop_9_prs2_busy}, {stq_uop_8_prs2_busy}, {stq_uop_7_prs2_busy}, {stq_uop_6_prs2_busy}, {stq_uop_5_prs2_busy}, {stq_uop_4_prs2_busy}, {stq_uop_3_prs2_busy}, {stq_uop_2_prs2_busy}, {stq_uop_1_prs2_busy}, {stq_uop_0_prs2_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs2_busy = _GEN_276[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_277 = {{stq_uop_15_prs3_busy}, {stq_uop_14_prs3_busy}, {stq_uop_13_prs3_busy}, {stq_uop_12_prs3_busy}, {stq_uop_11_prs3_busy}, {stq_uop_10_prs3_busy}, {stq_uop_9_prs3_busy}, {stq_uop_8_prs3_busy}, {stq_uop_7_prs3_busy}, {stq_uop_6_prs3_busy}, {stq_uop_5_prs3_busy}, {stq_uop_4_prs3_busy}, {stq_uop_3_prs3_busy}, {stq_uop_2_prs3_busy}, {stq_uop_1_prs3_busy}, {stq_uop_0_prs3_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs3_busy = _GEN_277[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_278 = {{stq_uop_15_ppred_busy}, {stq_uop_14_ppred_busy}, {stq_uop_13_ppred_busy}, {stq_uop_12_ppred_busy}, {stq_uop_11_ppred_busy}, {stq_uop_10_ppred_busy}, {stq_uop_9_ppred_busy}, {stq_uop_8_ppred_busy}, {stq_uop_7_ppred_busy}, {stq_uop_6_ppred_busy}, {stq_uop_5_ppred_busy}, {stq_uop_4_ppred_busy}, {stq_uop_3_ppred_busy}, {stq_uop_2_ppred_busy}, {stq_uop_1_ppred_busy}, {stq_uop_0_ppred_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ppred_busy = _GEN_278[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][6:0] _GEN_279 = {{stq_uop_15_stale_pdst}, {stq_uop_14_stale_pdst}, {stq_uop_13_stale_pdst}, {stq_uop_12_stale_pdst}, {stq_uop_11_stale_pdst}, {stq_uop_10_stale_pdst}, {stq_uop_9_stale_pdst}, {stq_uop_8_stale_pdst}, {stq_uop_7_stale_pdst}, {stq_uop_6_stale_pdst}, {stq_uop_5_stale_pdst}, {stq_uop_4_stale_pdst}, {stq_uop_3_stale_pdst}, {stq_uop_2_stale_pdst}, {stq_uop_1_stale_pdst}, {stq_uop_0_stale_pdst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_stale_pdst = _GEN_279[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_280 = {{stq_uop_15_exception}, {stq_uop_14_exception}, {stq_uop_13_exception}, {stq_uop_12_exception}, {stq_uop_11_exception}, {stq_uop_10_exception}, {stq_uop_9_exception}, {stq_uop_8_exception}, {stq_uop_7_exception}, {stq_uop_6_exception}, {stq_uop_5_exception}, {stq_uop_4_exception}, {stq_uop_3_exception}, {stq_uop_2_exception}, {stq_uop_1_exception}, {stq_uop_0_exception}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_exception = _GEN_280[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][63:0] _GEN_281 = {{stq_uop_15_exc_cause}, {stq_uop_14_exc_cause}, {stq_uop_13_exc_cause}, {stq_uop_12_exc_cause}, {stq_uop_11_exc_cause}, {stq_uop_10_exc_cause}, {stq_uop_9_exc_cause}, {stq_uop_8_exc_cause}, {stq_uop_7_exc_cause}, {stq_uop_6_exc_cause}, {stq_uop_5_exc_cause}, {stq_uop_4_exc_cause}, {stq_uop_3_exc_cause}, {stq_uop_2_exc_cause}, {stq_uop_1_exc_cause}, {stq_uop_0_exc_cause}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_exc_cause = _GEN_281[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][4:0] _GEN_282 = {{stq_uop_15_mem_cmd}, {stq_uop_14_mem_cmd}, {stq_uop_13_mem_cmd}, {stq_uop_12_mem_cmd}, {stq_uop_11_mem_cmd}, {stq_uop_10_mem_cmd}, {stq_uop_9_mem_cmd}, {stq_uop_8_mem_cmd}, {stq_uop_7_mem_cmd}, {stq_uop_6_mem_cmd}, {stq_uop_5_mem_cmd}, {stq_uop_4_mem_cmd}, {stq_uop_3_mem_cmd}, {stq_uop_2_mem_cmd}, {stq_uop_1_mem_cmd}, {stq_uop_0_mem_cmd}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_mem_cmd = _GEN_282[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_283 = {{stq_uop_15_mem_size}, {stq_uop_14_mem_size}, {stq_uop_13_mem_size}, {stq_uop_12_mem_size}, {stq_uop_11_mem_size}, {stq_uop_10_mem_size}, {stq_uop_9_mem_size}, {stq_uop_8_mem_size}, {stq_uop_7_mem_size}, {stq_uop_6_mem_size}, {stq_uop_5_mem_size}, {stq_uop_4_mem_size}, {stq_uop_3_mem_size}, {stq_uop_2_mem_size}, {stq_uop_1_mem_size}, {stq_uop_0_mem_size}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_mem_size = _GEN_283[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_284 = {{stq_uop_15_mem_signed}, {stq_uop_14_mem_signed}, {stq_uop_13_mem_signed}, {stq_uop_12_mem_signed}, {stq_uop_11_mem_signed}, {stq_uop_10_mem_signed}, {stq_uop_9_mem_signed}, {stq_uop_8_mem_signed}, {stq_uop_7_mem_signed}, {stq_uop_6_mem_signed}, {stq_uop_5_mem_signed}, {stq_uop_4_mem_signed}, {stq_uop_3_mem_signed}, {stq_uop_2_mem_signed}, {stq_uop_1_mem_signed}, {stq_uop_0_mem_signed}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_mem_signed = _GEN_284[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_285 = {{stq_uop_15_uses_ldq}, {stq_uop_14_uses_ldq}, {stq_uop_13_uses_ldq}, {stq_uop_12_uses_ldq}, {stq_uop_11_uses_ldq}, {stq_uop_10_uses_ldq}, {stq_uop_9_uses_ldq}, {stq_uop_8_uses_ldq}, {stq_uop_7_uses_ldq}, {stq_uop_6_uses_ldq}, {stq_uop_5_uses_ldq}, {stq_uop_4_uses_ldq}, {stq_uop_3_uses_ldq}, {stq_uop_2_uses_ldq}, {stq_uop_1_uses_ldq}, {stq_uop_0_uses_ldq}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_uses_ldq = _GEN_285[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_286 = {{stq_uop_15_uses_stq}, {stq_uop_14_uses_stq}, {stq_uop_13_uses_stq}, {stq_uop_12_uses_stq}, {stq_uop_11_uses_stq}, {stq_uop_10_uses_stq}, {stq_uop_9_uses_stq}, {stq_uop_8_uses_stq}, {stq_uop_7_uses_stq}, {stq_uop_6_uses_stq}, {stq_uop_5_uses_stq}, {stq_uop_4_uses_stq}, {stq_uop_3_uses_stq}, {stq_uop_2_uses_stq}, {stq_uop_1_uses_stq}, {stq_uop_0_uses_stq}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_uses_stq = _GEN_286[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_287 = {{stq_uop_15_is_unique}, {stq_uop_14_is_unique}, {stq_uop_13_is_unique}, {stq_uop_12_is_unique}, {stq_uop_11_is_unique}, {stq_uop_10_is_unique}, {stq_uop_9_is_unique}, {stq_uop_8_is_unique}, {stq_uop_7_is_unique}, {stq_uop_6_is_unique}, {stq_uop_5_is_unique}, {stq_uop_4_is_unique}, {stq_uop_3_is_unique}, {stq_uop_2_is_unique}, {stq_uop_1_is_unique}, {stq_uop_0_is_unique}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_unique = _GEN_287[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_288 = {{stq_uop_15_flush_on_commit}, {stq_uop_14_flush_on_commit}, {stq_uop_13_flush_on_commit}, {stq_uop_12_flush_on_commit}, {stq_uop_11_flush_on_commit}, {stq_uop_10_flush_on_commit}, {stq_uop_9_flush_on_commit}, {stq_uop_8_flush_on_commit}, {stq_uop_7_flush_on_commit}, {stq_uop_6_flush_on_commit}, {stq_uop_5_flush_on_commit}, {stq_uop_4_flush_on_commit}, {stq_uop_3_flush_on_commit}, {stq_uop_2_flush_on_commit}, {stq_uop_1_flush_on_commit}, {stq_uop_0_flush_on_commit}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_flush_on_commit = _GEN_288[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][2:0] _GEN_289 = {{stq_uop_15_csr_cmd}, {stq_uop_14_csr_cmd}, {stq_uop_13_csr_cmd}, {stq_uop_12_csr_cmd}, {stq_uop_11_csr_cmd}, {stq_uop_10_csr_cmd}, {stq_uop_9_csr_cmd}, {stq_uop_8_csr_cmd}, {stq_uop_7_csr_cmd}, {stq_uop_6_csr_cmd}, {stq_uop_5_csr_cmd}, {stq_uop_4_csr_cmd}, {stq_uop_3_csr_cmd}, {stq_uop_2_csr_cmd}, {stq_uop_1_csr_cmd}, {stq_uop_0_csr_cmd}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_csr_cmd = _GEN_289[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_290 = {{stq_uop_15_ldst_is_rs1}, {stq_uop_14_ldst_is_rs1}, {stq_uop_13_ldst_is_rs1}, {stq_uop_12_ldst_is_rs1}, {stq_uop_11_ldst_is_rs1}, {stq_uop_10_ldst_is_rs1}, {stq_uop_9_ldst_is_rs1}, {stq_uop_8_ldst_is_rs1}, {stq_uop_7_ldst_is_rs1}, {stq_uop_6_ldst_is_rs1}, {stq_uop_5_ldst_is_rs1}, {stq_uop_4_ldst_is_rs1}, {stq_uop_3_ldst_is_rs1}, {stq_uop_2_ldst_is_rs1}, {stq_uop_1_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ldst_is_rs1 = _GEN_290[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][5:0] _GEN_291 = {{stq_uop_15_ldst}, {stq_uop_14_ldst}, {stq_uop_13_ldst}, {stq_uop_12_ldst}, {stq_uop_11_ldst}, {stq_uop_10_ldst}, {stq_uop_9_ldst}, {stq_uop_8_ldst}, {stq_uop_7_ldst}, {stq_uop_6_ldst}, {stq_uop_5_ldst}, {stq_uop_4_ldst}, {stq_uop_3_ldst}, {stq_uop_2_ldst}, {stq_uop_1_ldst}, {stq_uop_0_ldst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ldst = _GEN_291[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][5:0] _GEN_292 = {{stq_uop_15_lrs1}, {stq_uop_14_lrs1}, {stq_uop_13_lrs1}, {stq_uop_12_lrs1}, {stq_uop_11_lrs1}, {stq_uop_10_lrs1}, {stq_uop_9_lrs1}, {stq_uop_8_lrs1}, {stq_uop_7_lrs1}, {stq_uop_6_lrs1}, {stq_uop_5_lrs1}, {stq_uop_4_lrs1}, {stq_uop_3_lrs1}, {stq_uop_2_lrs1}, {stq_uop_1_lrs1}, {stq_uop_0_lrs1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs1 = _GEN_292[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][5:0] _GEN_293 = {{stq_uop_15_lrs2}, {stq_uop_14_lrs2}, {stq_uop_13_lrs2}, {stq_uop_12_lrs2}, {stq_uop_11_lrs2}, {stq_uop_10_lrs2}, {stq_uop_9_lrs2}, {stq_uop_8_lrs2}, {stq_uop_7_lrs2}, {stq_uop_6_lrs2}, {stq_uop_5_lrs2}, {stq_uop_4_lrs2}, {stq_uop_3_lrs2}, {stq_uop_2_lrs2}, {stq_uop_1_lrs2}, {stq_uop_0_lrs2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs2 = _GEN_293[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][5:0] _GEN_294 = {{stq_uop_15_lrs3}, {stq_uop_14_lrs3}, {stq_uop_13_lrs3}, {stq_uop_12_lrs3}, {stq_uop_11_lrs3}, {stq_uop_10_lrs3}, {stq_uop_9_lrs3}, {stq_uop_8_lrs3}, {stq_uop_7_lrs3}, {stq_uop_6_lrs3}, {stq_uop_5_lrs3}, {stq_uop_4_lrs3}, {stq_uop_3_lrs3}, {stq_uop_2_lrs3}, {stq_uop_1_lrs3}, {stq_uop_0_lrs3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs3 = _GEN_294[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_295 = {{stq_uop_15_dst_rtype}, {stq_uop_14_dst_rtype}, {stq_uop_13_dst_rtype}, {stq_uop_12_dst_rtype}, {stq_uop_11_dst_rtype}, {stq_uop_10_dst_rtype}, {stq_uop_9_dst_rtype}, {stq_uop_8_dst_rtype}, {stq_uop_7_dst_rtype}, {stq_uop_6_dst_rtype}, {stq_uop_5_dst_rtype}, {stq_uop_4_dst_rtype}, {stq_uop_3_dst_rtype}, {stq_uop_2_dst_rtype}, {stq_uop_1_dst_rtype}, {stq_uop_0_dst_rtype}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_dst_rtype = _GEN_295[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_296 = {{stq_uop_15_lrs1_rtype}, {stq_uop_14_lrs1_rtype}, {stq_uop_13_lrs1_rtype}, {stq_uop_12_lrs1_rtype}, {stq_uop_11_lrs1_rtype}, {stq_uop_10_lrs1_rtype}, {stq_uop_9_lrs1_rtype}, {stq_uop_8_lrs1_rtype}, {stq_uop_7_lrs1_rtype}, {stq_uop_6_lrs1_rtype}, {stq_uop_5_lrs1_rtype}, {stq_uop_4_lrs1_rtype}, {stq_uop_3_lrs1_rtype}, {stq_uop_2_lrs1_rtype}, {stq_uop_1_lrs1_rtype}, {stq_uop_0_lrs1_rtype}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs1_rtype = _GEN_296[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_297 = {{stq_uop_15_lrs2_rtype}, {stq_uop_14_lrs2_rtype}, {stq_uop_13_lrs2_rtype}, {stq_uop_12_lrs2_rtype}, {stq_uop_11_lrs2_rtype}, {stq_uop_10_lrs2_rtype}, {stq_uop_9_lrs2_rtype}, {stq_uop_8_lrs2_rtype}, {stq_uop_7_lrs2_rtype}, {stq_uop_6_lrs2_rtype}, {stq_uop_5_lrs2_rtype}, {stq_uop_4_lrs2_rtype}, {stq_uop_3_lrs2_rtype}, {stq_uop_2_lrs2_rtype}, {stq_uop_1_lrs2_rtype}, {stq_uop_0_lrs2_rtype}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs2_rtype = _GEN_297[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_298 = {{stq_uop_15_frs3_en}, {stq_uop_14_frs3_en}, {stq_uop_13_frs3_en}, {stq_uop_12_frs3_en}, {stq_uop_11_frs3_en}, {stq_uop_10_frs3_en}, {stq_uop_9_frs3_en}, {stq_uop_8_frs3_en}, {stq_uop_7_frs3_en}, {stq_uop_6_frs3_en}, {stq_uop_5_frs3_en}, {stq_uop_4_frs3_en}, {stq_uop_3_frs3_en}, {stq_uop_2_frs3_en}, {stq_uop_1_frs3_en}, {stq_uop_0_frs3_en}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_frs3_en = _GEN_298[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_299 = {{stq_uop_15_fcn_dw}, {stq_uop_14_fcn_dw}, {stq_uop_13_fcn_dw}, {stq_uop_12_fcn_dw}, {stq_uop_11_fcn_dw}, {stq_uop_10_fcn_dw}, {stq_uop_9_fcn_dw}, {stq_uop_8_fcn_dw}, {stq_uop_7_fcn_dw}, {stq_uop_6_fcn_dw}, {stq_uop_5_fcn_dw}, {stq_uop_4_fcn_dw}, {stq_uop_3_fcn_dw}, {stq_uop_2_fcn_dw}, {stq_uop_1_fcn_dw}, {stq_uop_0_fcn_dw}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fcn_dw = _GEN_299[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][4:0] _GEN_300 = {{stq_uop_15_fcn_op}, {stq_uop_14_fcn_op}, {stq_uop_13_fcn_op}, {stq_uop_12_fcn_op}, {stq_uop_11_fcn_op}, {stq_uop_10_fcn_op}, {stq_uop_9_fcn_op}, {stq_uop_8_fcn_op}, {stq_uop_7_fcn_op}, {stq_uop_6_fcn_op}, {stq_uop_5_fcn_op}, {stq_uop_4_fcn_op}, {stq_uop_3_fcn_op}, {stq_uop_2_fcn_op}, {stq_uop_1_fcn_op}, {stq_uop_0_fcn_op}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fcn_op = _GEN_300[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_301 = {{stq_uop_15_fp_val}, {stq_uop_14_fp_val}, {stq_uop_13_fp_val}, {stq_uop_12_fp_val}, {stq_uop_11_fp_val}, {stq_uop_10_fp_val}, {stq_uop_9_fp_val}, {stq_uop_8_fp_val}, {stq_uop_7_fp_val}, {stq_uop_6_fp_val}, {stq_uop_5_fp_val}, {stq_uop_4_fp_val}, {stq_uop_3_fp_val}, {stq_uop_2_fp_val}, {stq_uop_1_fp_val}, {stq_uop_0_fp_val}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_val = _GEN_301[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][2:0] _GEN_302 = {{stq_uop_15_fp_rm}, {stq_uop_14_fp_rm}, {stq_uop_13_fp_rm}, {stq_uop_12_fp_rm}, {stq_uop_11_fp_rm}, {stq_uop_10_fp_rm}, {stq_uop_9_fp_rm}, {stq_uop_8_fp_rm}, {stq_uop_7_fp_rm}, {stq_uop_6_fp_rm}, {stq_uop_5_fp_rm}, {stq_uop_4_fp_rm}, {stq_uop_3_fp_rm}, {stq_uop_2_fp_rm}, {stq_uop_1_fp_rm}, {stq_uop_0_fp_rm}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_rm = _GEN_302[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][1:0] _GEN_303 = {{stq_uop_15_fp_typ}, {stq_uop_14_fp_typ}, {stq_uop_13_fp_typ}, {stq_uop_12_fp_typ}, {stq_uop_11_fp_typ}, {stq_uop_10_fp_typ}, {stq_uop_9_fp_typ}, {stq_uop_8_fp_typ}, {stq_uop_7_fp_typ}, {stq_uop_6_fp_typ}, {stq_uop_5_fp_typ}, {stq_uop_4_fp_typ}, {stq_uop_3_fp_typ}, {stq_uop_2_fp_typ}, {stq_uop_1_fp_typ}, {stq_uop_0_fp_typ}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_typ = _GEN_303[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_304 = {{stq_uop_15_xcpt_pf_if}, {stq_uop_14_xcpt_pf_if}, {stq_uop_13_xcpt_pf_if}, {stq_uop_12_xcpt_pf_if}, {stq_uop_11_xcpt_pf_if}, {stq_uop_10_xcpt_pf_if}, {stq_uop_9_xcpt_pf_if}, {stq_uop_8_xcpt_pf_if}, {stq_uop_7_xcpt_pf_if}, {stq_uop_6_xcpt_pf_if}, {stq_uop_5_xcpt_pf_if}, {stq_uop_4_xcpt_pf_if}, {stq_uop_3_xcpt_pf_if}, {stq_uop_2_xcpt_pf_if}, {stq_uop_1_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_xcpt_pf_if = _GEN_304[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_305 = {{stq_uop_15_xcpt_ae_if}, {stq_uop_14_xcpt_ae_if}, {stq_uop_13_xcpt_ae_if}, {stq_uop_12_xcpt_ae_if}, {stq_uop_11_xcpt_ae_if}, {stq_uop_10_xcpt_ae_if}, {stq_uop_9_xcpt_ae_if}, {stq_uop_8_xcpt_ae_if}, {stq_uop_7_xcpt_ae_if}, {stq_uop_6_xcpt_ae_if}, {stq_uop_5_xcpt_ae_if}, {stq_uop_4_xcpt_ae_if}, {stq_uop_3_xcpt_ae_if}, {stq_uop_2_xcpt_ae_if}, {stq_uop_1_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_xcpt_ae_if = _GEN_305[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_306 = {{stq_uop_15_xcpt_ma_if}, {stq_uop_14_xcpt_ma_if}, {stq_uop_13_xcpt_ma_if}, {stq_uop_12_xcpt_ma_if}, {stq_uop_11_xcpt_ma_if}, {stq_uop_10_xcpt_ma_if}, {stq_uop_9_xcpt_ma_if}, {stq_uop_8_xcpt_ma_if}, {stq_uop_7_xcpt_ma_if}, {stq_uop_6_xcpt_ma_if}, {stq_uop_5_xcpt_ma_if}, {stq_uop_4_xcpt_ma_if}, {stq_uop_3_xcpt_ma_if}, {stq_uop_2_xcpt_ma_if}, {stq_uop_1_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_xcpt_ma_if = _GEN_306[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_307 = {{stq_uop_15_bp_debug_if}, {stq_uop_14_bp_debug_if}, {stq_uop_13_bp_debug_if}, {stq_uop_12_bp_debug_if}, {stq_uop_11_bp_debug_if}, {stq_uop_10_bp_debug_if}, {stq_uop_9_bp_debug_if}, {stq_uop_8_bp_debug_if}, {stq_uop_7_bp_debug_if}, {stq_uop_6_bp_debug_if}, {stq_uop_5_bp_debug_if}, {stq_uop_4_bp_debug_if}, {stq_uop_3_bp_debug_if}, {stq_uop_2_bp_debug_if}, {stq_uop_1_bp_debug_if}, {stq_uop_0_bp_debug_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_bp_debug_if = _GEN_307[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_308 = {{stq_uop_15_bp_xcpt_if}, {stq_uop_14_bp_xcpt_if}, {stq_uop_13_bp_xcpt_if}, {stq_uop_12_bp_xcpt_if}, {stq_uop_11_bp_xcpt_if}, {stq_uop_10_bp_xcpt_if}, {stq_uop_9_bp_xcpt_if}, {stq_uop_8_bp_xcpt_if}, {stq_uop_7_bp_xcpt_if}, {stq_uop_6_bp_xcpt_if}, {stq_uop_5_bp_xcpt_if}, {stq_uop_4_bp_xcpt_if}, {stq_uop_3_bp_xcpt_if}, {stq_uop_2_bp_xcpt_if}, {stq_uop_1_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_bp_xcpt_if = _GEN_308[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][2:0] _GEN_309 = {{stq_uop_15_debug_fsrc}, {stq_uop_14_debug_fsrc}, {stq_uop_13_debug_fsrc}, {stq_uop_12_debug_fsrc}, {stq_uop_11_debug_fsrc}, {stq_uop_10_debug_fsrc}, {stq_uop_9_debug_fsrc}, {stq_uop_8_debug_fsrc}, {stq_uop_7_debug_fsrc}, {stq_uop_6_debug_fsrc}, {stq_uop_5_debug_fsrc}, {stq_uop_4_debug_fsrc}, {stq_uop_3_debug_fsrc}, {stq_uop_2_debug_fsrc}, {stq_uop_1_debug_fsrc}, {stq_uop_0_debug_fsrc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_fsrc = _GEN_309[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0][2:0] _GEN_310 = {{stq_uop_15_debug_tsrc}, {stq_uop_14_debug_tsrc}, {stq_uop_13_debug_tsrc}, {stq_uop_12_debug_tsrc}, {stq_uop_11_debug_tsrc}, {stq_uop_10_debug_tsrc}, {stq_uop_9_debug_tsrc}, {stq_uop_8_debug_tsrc}, {stq_uop_7_debug_tsrc}, {stq_uop_6_debug_tsrc}, {stq_uop_5_debug_tsrc}, {stq_uop_4_debug_tsrc}, {stq_uop_3_debug_tsrc}, {stq_uop_2_debug_tsrc}, {stq_uop_1_debug_tsrc}, {stq_uop_0_debug_tsrc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_tsrc = _GEN_310[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [15:0] _GEN_311 = {{stq_addr_15_valid}, {stq_addr_14_valid}, {stq_addr_13_valid}, {stq_addr_12_valid}, {stq_addr_11_valid}, {stq_addr_10_valid}, {stq_addr_9_valid}, {stq_addr_8_valid}, {stq_addr_7_valid}, {stq_addr_6_valid}, {stq_addr_5_valid}, {stq_addr_4_valid}, {stq_addr_3_valid}, {stq_addr_2_valid}, {stq_addr_1_valid}, {stq_addr_0_valid}}; // @[lsu.scala:253:32, :265:32] assign stq_incoming_e_e_bits_addr_valid = _GEN_311[stq_incoming_idx_0]; // @[lsu.scala:262:17, :265:32, :321:49] wire [15:0][39:0] _GEN_312 = {{stq_addr_15_bits}, {stq_addr_14_bits}, {stq_addr_13_bits}, {stq_addr_12_bits}, {stq_addr_11_bits}, {stq_addr_10_bits}, {stq_addr_9_bits}, {stq_addr_8_bits}, {stq_addr_7_bits}, {stq_addr_6_bits}, {stq_addr_5_bits}, {stq_addr_4_bits}, {stq_addr_3_bits}, {stq_addr_2_bits}, {stq_addr_1_bits}, {stq_addr_0_bits}}; // @[lsu.scala:253:32, :265:32] assign stq_incoming_e_e_bits_addr_bits = _GEN_312[stq_incoming_idx_0]; // @[lsu.scala:262:17, :265:32, :321:49] wire [15:0] _GEN_313 = {{stq_addr_is_virtual_15}, {stq_addr_is_virtual_14}, {stq_addr_is_virtual_13}, {stq_addr_is_virtual_12}, {stq_addr_is_virtual_11}, {stq_addr_is_virtual_10}, {stq_addr_is_virtual_9}, {stq_addr_is_virtual_8}, {stq_addr_is_virtual_7}, {stq_addr_is_virtual_6}, {stq_addr_is_virtual_5}, {stq_addr_is_virtual_4}, {stq_addr_is_virtual_3}, {stq_addr_is_virtual_2}, {stq_addr_is_virtual_1}, {stq_addr_is_virtual_0}}; // @[lsu.scala:254:32, :266:32] assign stq_incoming_e_e_bits_addr_is_virtual = _GEN_313[stq_incoming_idx_0]; // @[lsu.scala:262:17, :266:32, :321:49] wire [15:0] _GEN_314 = {{stq_data_15_valid}, {stq_data_14_valid}, {stq_data_13_valid}, {stq_data_12_valid}, {stq_data_11_valid}, {stq_data_10_valid}, {stq_data_9_valid}, {stq_data_8_valid}, {stq_data_7_valid}, {stq_data_6_valid}, {stq_data_5_valid}, {stq_data_4_valid}, {stq_data_3_valid}, {stq_data_2_valid}, {stq_data_1_valid}, {stq_data_0_valid}}; // @[lsu.scala:255:32, :267:32] assign stq_incoming_e_e_bits_data_valid = _GEN_314[stq_incoming_idx_0]; // @[lsu.scala:262:17, :267:32, :321:49] wire [15:0][63:0] _GEN_315 = {{stq_data_15_bits}, {stq_data_14_bits}, {stq_data_13_bits}, {stq_data_12_bits}, {stq_data_11_bits}, {stq_data_10_bits}, {stq_data_9_bits}, {stq_data_8_bits}, {stq_data_7_bits}, {stq_data_6_bits}, {stq_data_5_bits}, {stq_data_4_bits}, {stq_data_3_bits}, {stq_data_2_bits}, {stq_data_1_bits}, {stq_data_0_bits}}; // @[lsu.scala:255:32, :267:32] assign stq_incoming_e_e_bits_data_bits = _GEN_315[stq_incoming_idx_0]; // @[lsu.scala:262:17, :267:32, :321:49] wire [15:0] _GEN_316 = {{stq_committed_15}, {stq_committed_14}, {stq_committed_13}, {stq_committed_12}, {stq_committed_11}, {stq_committed_10}, {stq_committed_9}, {stq_committed_8}, {stq_committed_7}, {stq_committed_6}, {stq_committed_5}, {stq_committed_4}, {stq_committed_3}, {stq_committed_2}, {stq_committed_1}, {stq_committed_0}}; // @[lsu.scala:256:32, :268:32] assign stq_incoming_e_e_bits_committed = _GEN_316[stq_incoming_idx_0]; // @[lsu.scala:262:17, :268:32, :321:49] wire [15:0] _GEN_317 = {{stq_succeeded_15}, {stq_succeeded_14}, {stq_succeeded_13}, {stq_succeeded_12}, {stq_succeeded_11}, {stq_succeeded_10}, {stq_succeeded_9}, {stq_succeeded_8}, {stq_succeeded_7}, {stq_succeeded_6}, {stq_succeeded_5}, {stq_succeeded_4}, {stq_succeeded_3}, {stq_succeeded_2}, {stq_succeeded_1}, {stq_succeeded_0}}; // @[lsu.scala:257:32, :269:32] assign stq_incoming_e_e_bits_succeeded = _GEN_317[stq_incoming_idx_0]; // @[lsu.scala:262:17, :269:32, :321:49] wire [15:0] _GEN_318 = {{stq_can_execute_15}, {stq_can_execute_14}, {stq_can_execute_13}, {stq_can_execute_12}, {stq_can_execute_11}, {stq_can_execute_10}, {stq_can_execute_9}, {stq_can_execute_8}, {stq_can_execute_7}, {stq_can_execute_6}, {stq_can_execute_5}, {stq_can_execute_4}, {stq_can_execute_3}, {stq_can_execute_2}, {stq_can_execute_1}, {stq_can_execute_0}}; // @[lsu.scala:258:32, :270:32] assign stq_incoming_e_e_bits_can_execute = _GEN_318[stq_incoming_idx_0]; // @[lsu.scala:262:17, :270:32, :321:49] wire [15:0] _GEN_319 = {{stq_cleared_15}, {stq_cleared_14}, {stq_cleared_13}, {stq_cleared_12}, {stq_cleared_11}, {stq_cleared_10}, {stq_cleared_9}, {stq_cleared_8}, {stq_cleared_7}, {stq_cleared_6}, {stq_cleared_5}, {stq_cleared_4}, {stq_cleared_3}, {stq_cleared_2}, {stq_cleared_1}, {stq_cleared_0}}; // @[lsu.scala:259:32, :271:32] assign stq_incoming_e_e_bits_cleared = _GEN_319[stq_incoming_idx_0]; // @[lsu.scala:262:17, :271:32, :321:49] wire [15:0][63:0] _GEN_320 = {{stq_debug_wb_data_15}, {stq_debug_wb_data_14}, {stq_debug_wb_data_13}, {stq_debug_wb_data_12}, {stq_debug_wb_data_11}, {stq_debug_wb_data_10}, {stq_debug_wb_data_9}, {stq_debug_wb_data_8}, {stq_debug_wb_data_7}, {stq_debug_wb_data_6}, {stq_debug_wb_data_5}, {stq_debug_wb_data_4}, {stq_debug_wb_data_3}, {stq_debug_wb_data_2}, {stq_debug_wb_data_1}, {stq_debug_wb_data_0}}; // @[lsu.scala:260:32, :272:32] assign stq_incoming_e_e_bits_debug_wb_data = _GEN_320[stq_incoming_idx_0]; // @[lsu.scala:262:17, :272:32, :321:49] wire stq_incoming_e_0_valid = _stq_incoming_e_WIRE_valid; // @[lsu.scala:321:49, :504:48] wire [31:0] stq_incoming_e_0_bits_uop_inst = _stq_incoming_e_WIRE_bits_uop_inst; // @[lsu.scala:321:49, :504:48] wire [31:0] stq_incoming_e_0_bits_uop_debug_inst = _stq_incoming_e_WIRE_bits_uop_debug_inst; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_rvc = _stq_incoming_e_WIRE_bits_uop_is_rvc; // @[lsu.scala:321:49, :504:48] wire [39:0] stq_incoming_e_0_bits_uop_debug_pc = _stq_incoming_e_WIRE_bits_uop_debug_pc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_0 = _stq_incoming_e_WIRE_bits_uop_iq_type_0; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_1 = _stq_incoming_e_WIRE_bits_uop_iq_type_1; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_2 = _stq_incoming_e_WIRE_bits_uop_iq_type_2; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_3 = _stq_incoming_e_WIRE_bits_uop_iq_type_3; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_0 = _stq_incoming_e_WIRE_bits_uop_fu_code_0; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_1 = _stq_incoming_e_WIRE_bits_uop_fu_code_1; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_2 = _stq_incoming_e_WIRE_bits_uop_fu_code_2; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_3 = _stq_incoming_e_WIRE_bits_uop_fu_code_3; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_4 = _stq_incoming_e_WIRE_bits_uop_fu_code_4; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_5 = _stq_incoming_e_WIRE_bits_uop_fu_code_5; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_6 = _stq_incoming_e_WIRE_bits_uop_fu_code_6; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_7 = _stq_incoming_e_WIRE_bits_uop_fu_code_7; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_8 = _stq_incoming_e_WIRE_bits_uop_fu_code_8; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_9 = _stq_incoming_e_WIRE_bits_uop_fu_code_9; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_issued = _stq_incoming_e_WIRE_bits_uop_iw_issued; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_issued_partial_agen = _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_issued_partial_dgen = _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_iw_p1_speculative_child = _stq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_iw_p2_speculative_child = _stq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_p1_bypass_hint = _stq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_p2_bypass_hint = _stq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_p3_bypass_hint = _stq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_dis_col_sel = _stq_incoming_e_WIRE_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :504:48] wire [11:0] stq_incoming_e_0_bits_uop_br_mask = _stq_incoming_e_WIRE_bits_uop_br_mask; // @[lsu.scala:321:49, :504:48] wire [3:0] stq_incoming_e_0_bits_uop_br_tag = _stq_incoming_e_WIRE_bits_uop_br_tag; // @[lsu.scala:321:49, :504:48] wire [3:0] stq_incoming_e_0_bits_uop_br_type = _stq_incoming_e_WIRE_bits_uop_br_type; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_sfb = _stq_incoming_e_WIRE_bits_uop_is_sfb; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_fence = _stq_incoming_e_WIRE_bits_uop_is_fence; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_fencei = _stq_incoming_e_WIRE_bits_uop_is_fencei; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_sfence = _stq_incoming_e_WIRE_bits_uop_is_sfence; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_amo = _stq_incoming_e_WIRE_bits_uop_is_amo; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_eret = _stq_incoming_e_WIRE_bits_uop_is_eret; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_sys_pc2epc = _stq_incoming_e_WIRE_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_rocc = _stq_incoming_e_WIRE_bits_uop_is_rocc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_mov = _stq_incoming_e_WIRE_bits_uop_is_mov; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_ftq_idx = _stq_incoming_e_WIRE_bits_uop_ftq_idx; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_edge_inst = _stq_incoming_e_WIRE_bits_uop_edge_inst; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_pc_lob = _stq_incoming_e_WIRE_bits_uop_pc_lob; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_taken = _stq_incoming_e_WIRE_bits_uop_taken; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_imm_rename = _stq_incoming_e_WIRE_bits_uop_imm_rename; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_imm_sel = _stq_incoming_e_WIRE_bits_uop_imm_sel; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_pimm = _stq_incoming_e_WIRE_bits_uop_pimm; // @[lsu.scala:321:49, :504:48] wire [19:0] stq_incoming_e_0_bits_uop_imm_packed = _stq_incoming_e_WIRE_bits_uop_imm_packed; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_op1_sel = _stq_incoming_e_WIRE_bits_uop_op1_sel; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_op2_sel = _stq_incoming_e_WIRE_bits_uop_op2_sel; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ldst = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_wen = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ren1 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ren2 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ren3 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_swap12 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_swap23 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_fromint = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_toint = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_fma = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_div = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_sqrt = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_wflags = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_vec = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_rob_idx = _stq_incoming_e_WIRE_bits_uop_rob_idx; // @[lsu.scala:321:49, :504:48] wire [3:0] stq_incoming_e_0_bits_uop_ldq_idx = _stq_incoming_e_WIRE_bits_uop_ldq_idx; // @[lsu.scala:321:49, :504:48] wire [3:0] stq_incoming_e_0_bits_uop_stq_idx = _stq_incoming_e_WIRE_bits_uop_stq_idx; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_rxq_idx = _stq_incoming_e_WIRE_bits_uop_rxq_idx; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_pdst = _stq_incoming_e_WIRE_bits_uop_pdst; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_prs1 = _stq_incoming_e_WIRE_bits_uop_prs1; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_prs2 = _stq_incoming_e_WIRE_bits_uop_prs2; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_prs3 = _stq_incoming_e_WIRE_bits_uop_prs3; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_ppred = _stq_incoming_e_WIRE_bits_uop_ppred; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_prs1_busy = _stq_incoming_e_WIRE_bits_uop_prs1_busy; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_prs2_busy = _stq_incoming_e_WIRE_bits_uop_prs2_busy; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_prs3_busy = _stq_incoming_e_WIRE_bits_uop_prs3_busy; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_ppred_busy = _stq_incoming_e_WIRE_bits_uop_ppred_busy; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_stale_pdst = _stq_incoming_e_WIRE_bits_uop_stale_pdst; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_exception = _stq_incoming_e_WIRE_bits_uop_exception; // @[lsu.scala:321:49, :504:48] wire [63:0] stq_incoming_e_0_bits_uop_exc_cause = _stq_incoming_e_WIRE_bits_uop_exc_cause; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_mem_cmd = _stq_incoming_e_WIRE_bits_uop_mem_cmd; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_mem_size = _stq_incoming_e_WIRE_bits_uop_mem_size; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_mem_signed = _stq_incoming_e_WIRE_bits_uop_mem_signed; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_uses_ldq = _stq_incoming_e_WIRE_bits_uop_uses_ldq; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_uses_stq = _stq_incoming_e_WIRE_bits_uop_uses_stq; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_unique = _stq_incoming_e_WIRE_bits_uop_is_unique; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_flush_on_commit = _stq_incoming_e_WIRE_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_csr_cmd = _stq_incoming_e_WIRE_bits_uop_csr_cmd; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_ldst_is_rs1 = _stq_incoming_e_WIRE_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_ldst = _stq_incoming_e_WIRE_bits_uop_ldst; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_lrs1 = _stq_incoming_e_WIRE_bits_uop_lrs1; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_lrs2 = _stq_incoming_e_WIRE_bits_uop_lrs2; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_lrs3 = _stq_incoming_e_WIRE_bits_uop_lrs3; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_dst_rtype = _stq_incoming_e_WIRE_bits_uop_dst_rtype; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_lrs1_rtype = _stq_incoming_e_WIRE_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_lrs2_rtype = _stq_incoming_e_WIRE_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_frs3_en = _stq_incoming_e_WIRE_bits_uop_frs3_en; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fcn_dw = _stq_incoming_e_WIRE_bits_uop_fcn_dw; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_fcn_op = _stq_incoming_e_WIRE_bits_uop_fcn_op; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_val = _stq_incoming_e_WIRE_bits_uop_fp_val; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_fp_rm = _stq_incoming_e_WIRE_bits_uop_fp_rm; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_fp_typ = _stq_incoming_e_WIRE_bits_uop_fp_typ; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_xcpt_pf_if = _stq_incoming_e_WIRE_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_xcpt_ae_if = _stq_incoming_e_WIRE_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_xcpt_ma_if = _stq_incoming_e_WIRE_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_bp_debug_if = _stq_incoming_e_WIRE_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_bp_xcpt_if = _stq_incoming_e_WIRE_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_debug_fsrc = _stq_incoming_e_WIRE_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_debug_tsrc = _stq_incoming_e_WIRE_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_addr_valid = _stq_incoming_e_WIRE_bits_addr_valid; // @[lsu.scala:321:49, :504:48] wire [39:0] stq_incoming_e_0_bits_addr_bits = _stq_incoming_e_WIRE_bits_addr_bits; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_addr_is_virtual = _stq_incoming_e_WIRE_bits_addr_is_virtual; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_data_valid = _stq_incoming_e_WIRE_bits_data_valid; // @[lsu.scala:321:49, :504:48] wire [63:0] stq_incoming_e_0_bits_data_bits = _stq_incoming_e_WIRE_bits_data_bits; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_committed = _stq_incoming_e_WIRE_bits_committed; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_succeeded = _stq_incoming_e_WIRE_bits_succeeded; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_can_execute = _stq_incoming_e_WIRE_bits_can_execute; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_cleared = _stq_incoming_e_WIRE_bits_cleared; // @[lsu.scala:321:49, :504:48] wire [63:0] stq_incoming_e_0_bits_debug_wb_data = _stq_incoming_e_WIRE_bits_debug_wb_data; // @[lsu.scala:321:49, :504:48] wire [31:0] mem_stq_incoming_e_out_bits_uop_inst = stq_incoming_e_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_stq_incoming_e_out_bits_uop_debug_inst = stq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_rvc = stq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_stq_incoming_e_out_bits_uop_debug_pc = stq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_0 = stq_incoming_e_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_1 = stq_incoming_e_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_2 = stq_incoming_e_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_3 = stq_incoming_e_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_0 = stq_incoming_e_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_1 = stq_incoming_e_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_2 = stq_incoming_e_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_3 = stq_incoming_e_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_4 = stq_incoming_e_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_5 = stq_incoming_e_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_6 = stq_incoming_e_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_7 = stq_incoming_e_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_8 = stq_incoming_e_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_9 = stq_incoming_e_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_issued = stq_incoming_e_0_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_issued_partial_agen = stq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_issued_partial_dgen = stq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_iw_p1_speculative_child = stq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_iw_p2_speculative_child = stq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_p1_bypass_hint = stq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_p2_bypass_hint = stq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_p3_bypass_hint = stq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_dis_col_sel = stq_incoming_e_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_br_tag = stq_incoming_e_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_br_type = stq_incoming_e_0_bits_uop_br_type; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_sfb = stq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_fence = stq_incoming_e_0_bits_uop_is_fence; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_fencei = stq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_sfence = stq_incoming_e_0_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_amo = stq_incoming_e_0_bits_uop_is_amo; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_eret = stq_incoming_e_0_bits_uop_is_eret; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc = stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_rocc = stq_incoming_e_0_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_mov = stq_incoming_e_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ftq_idx = stq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_edge_inst = stq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_pc_lob = stq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_taken = stq_incoming_e_0_bits_uop_taken; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_imm_rename = stq_incoming_e_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_imm_sel = stq_incoming_e_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_pimm = stq_incoming_e_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_stq_incoming_e_out_bits_uop_imm_packed = stq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_op1_sel = stq_incoming_e_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_op2_sel = stq_incoming_e_0_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ldst = stq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_wen = stq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren1 = stq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren2 = stq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren3 = stq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap12 = stq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap23 = stq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn = stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut = stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_fromint = stq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_toint = stq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_fastpipe = stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_fma = stq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_div = stq_incoming_e_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_sqrt = stq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_wflags = stq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_vec = stq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_rob_idx = stq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_ldq_idx = stq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_stq_idx = stq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_rxq_idx = stq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_pdst = stq_incoming_e_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs1 = stq_incoming_e_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs2 = stq_incoming_e_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs3 = stq_incoming_e_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ppred = stq_incoming_e_0_bits_uop_ppred; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_prs1_busy = stq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_prs2_busy = stq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_prs3_busy = stq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_ppred_busy = stq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_stale_pdst = stq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_exception = stq_incoming_e_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_stq_incoming_e_out_bits_uop_exc_cause = stq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_mem_cmd = stq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_mem_size = stq_incoming_e_0_bits_uop_mem_size; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_mem_signed = stq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_uses_ldq = stq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_uses_stq = stq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_unique = stq_incoming_e_0_bits_uop_is_unique; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_flush_on_commit = stq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_csr_cmd = stq_incoming_e_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_ldst_is_rs1 = stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_ldst = stq_incoming_e_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs1 = stq_incoming_e_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs2 = stq_incoming_e_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs3 = stq_incoming_e_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_dst_rtype = stq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs1_rtype = stq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs2_rtype = stq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_frs3_en = stq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fcn_dw = stq_incoming_e_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_fcn_op = stq_incoming_e_0_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_val = stq_incoming_e_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_fp_rm = stq_incoming_e_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_fp_typ = stq_incoming_e_0_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_pf_if = stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ae_if = stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ma_if = stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_bp_debug_if = stq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_bp_xcpt_if = stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_debug_fsrc = stq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_debug_tsrc = stq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_addr_valid = stq_incoming_e_0_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_stq_incoming_e_out_bits_addr_bits = stq_incoming_e_0_bits_addr_bits; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_addr_is_virtual = stq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_data_valid = stq_incoming_e_0_bits_data_valid; // @[util.scala:114:23] wire [63:0] mem_stq_incoming_e_out_bits_data_bits = stq_incoming_e_0_bits_data_bits; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_committed = stq_incoming_e_0_bits_committed; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_succeeded = stq_incoming_e_0_bits_succeeded; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_can_execute = stq_incoming_e_0_bits_can_execute; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_cleared = stq_incoming_e_0_bits_cleared; // @[util.scala:114:23] wire [63:0] mem_stq_incoming_e_out_bits_debug_wb_data = stq_incoming_e_0_bits_debug_wb_data; // @[util.scala:114:23] wire ldq_wakeup_idx_block = block_load_mask_0 | p1_block_load_mask_0; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T = ~ldq_executed_0; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_1 = ldq_addr_0_valid & _ldq_wakeup_idx_T; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_2 = ~ldq_succeeded_0; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_3 = _ldq_wakeup_idx_T_1 & _ldq_wakeup_idx_T_2; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_4 = ~ldq_addr_is_virtual_0; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_5 = _ldq_wakeup_idx_T_3 & _ldq_wakeup_idx_T_4; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_6 = ~ldq_wakeup_idx_block; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_7 = _ldq_wakeup_idx_T_5 & _ldq_wakeup_idx_T_6; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_1 = block_load_mask_1 | p1_block_load_mask_1; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_8 = ~ldq_executed_1; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_9 = ldq_addr_1_valid & _ldq_wakeup_idx_T_8; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_10 = ~ldq_succeeded_1; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_11 = _ldq_wakeup_idx_T_9 & _ldq_wakeup_idx_T_10; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_12 = ~ldq_addr_is_virtual_1; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_13 = _ldq_wakeup_idx_T_11 & _ldq_wakeup_idx_T_12; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_14 = ~ldq_wakeup_idx_block_1; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_15 = _ldq_wakeup_idx_T_13 & _ldq_wakeup_idx_T_14; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_2 = block_load_mask_2 | p1_block_load_mask_2; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_16 = ~ldq_executed_2; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_17 = ldq_addr_2_valid & _ldq_wakeup_idx_T_16; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_18 = ~ldq_succeeded_2; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_19 = _ldq_wakeup_idx_T_17 & _ldq_wakeup_idx_T_18; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_20 = ~ldq_addr_is_virtual_2; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_21 = _ldq_wakeup_idx_T_19 & _ldq_wakeup_idx_T_20; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_22 = ~ldq_wakeup_idx_block_2; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_23 = _ldq_wakeup_idx_T_21 & _ldq_wakeup_idx_T_22; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_3 = block_load_mask_3 | p1_block_load_mask_3; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_24 = ~ldq_executed_3; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_25 = ldq_addr_3_valid & _ldq_wakeup_idx_T_24; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_26 = ~ldq_succeeded_3; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_27 = _ldq_wakeup_idx_T_25 & _ldq_wakeup_idx_T_26; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_28 = ~ldq_addr_is_virtual_3; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_29 = _ldq_wakeup_idx_T_27 & _ldq_wakeup_idx_T_28; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_30 = ~ldq_wakeup_idx_block_3; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_31 = _ldq_wakeup_idx_T_29 & _ldq_wakeup_idx_T_30; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_4 = block_load_mask_4 | p1_block_load_mask_4; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_32 = ~ldq_executed_4; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_33 = ldq_addr_4_valid & _ldq_wakeup_idx_T_32; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_34 = ~ldq_succeeded_4; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_35 = _ldq_wakeup_idx_T_33 & _ldq_wakeup_idx_T_34; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_36 = ~ldq_addr_is_virtual_4; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_37 = _ldq_wakeup_idx_T_35 & _ldq_wakeup_idx_T_36; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_38 = ~ldq_wakeup_idx_block_4; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_39 = _ldq_wakeup_idx_T_37 & _ldq_wakeup_idx_T_38; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_5 = block_load_mask_5 | p1_block_load_mask_5; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_40 = ~ldq_executed_5; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_41 = ldq_addr_5_valid & _ldq_wakeup_idx_T_40; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_42 = ~ldq_succeeded_5; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_43 = _ldq_wakeup_idx_T_41 & _ldq_wakeup_idx_T_42; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_44 = ~ldq_addr_is_virtual_5; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_45 = _ldq_wakeup_idx_T_43 & _ldq_wakeup_idx_T_44; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_46 = ~ldq_wakeup_idx_block_5; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_47 = _ldq_wakeup_idx_T_45 & _ldq_wakeup_idx_T_46; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_6 = block_load_mask_6 | p1_block_load_mask_6; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_48 = ~ldq_executed_6; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_49 = ldq_addr_6_valid & _ldq_wakeup_idx_T_48; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_50 = ~ldq_succeeded_6; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_51 = _ldq_wakeup_idx_T_49 & _ldq_wakeup_idx_T_50; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_52 = ~ldq_addr_is_virtual_6; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_53 = _ldq_wakeup_idx_T_51 & _ldq_wakeup_idx_T_52; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_54 = ~ldq_wakeup_idx_block_6; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_55 = _ldq_wakeup_idx_T_53 & _ldq_wakeup_idx_T_54; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_7 = block_load_mask_7 | p1_block_load_mask_7; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_56 = ~ldq_executed_7; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_57 = ldq_addr_7_valid & _ldq_wakeup_idx_T_56; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_58 = ~ldq_succeeded_7; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_59 = _ldq_wakeup_idx_T_57 & _ldq_wakeup_idx_T_58; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_60 = ~ldq_addr_is_virtual_7; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_61 = _ldq_wakeup_idx_T_59 & _ldq_wakeup_idx_T_60; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_62 = ~ldq_wakeup_idx_block_7; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_63 = _ldq_wakeup_idx_T_61 & _ldq_wakeup_idx_T_62; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_8 = block_load_mask_8 | p1_block_load_mask_8; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_64 = ~ldq_executed_8; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_65 = ldq_addr_8_valid & _ldq_wakeup_idx_T_64; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_66 = ~ldq_succeeded_8; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_67 = _ldq_wakeup_idx_T_65 & _ldq_wakeup_idx_T_66; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_68 = ~ldq_addr_is_virtual_8; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_69 = _ldq_wakeup_idx_T_67 & _ldq_wakeup_idx_T_68; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_70 = ~ldq_wakeup_idx_block_8; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_71 = _ldq_wakeup_idx_T_69 & _ldq_wakeup_idx_T_70; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_9 = block_load_mask_9 | p1_block_load_mask_9; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_72 = ~ldq_executed_9; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_73 = ldq_addr_9_valid & _ldq_wakeup_idx_T_72; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_74 = ~ldq_succeeded_9; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_75 = _ldq_wakeup_idx_T_73 & _ldq_wakeup_idx_T_74; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_76 = ~ldq_addr_is_virtual_9; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_77 = _ldq_wakeup_idx_T_75 & _ldq_wakeup_idx_T_76; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_78 = ~ldq_wakeup_idx_block_9; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_79 = _ldq_wakeup_idx_T_77 & _ldq_wakeup_idx_T_78; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_10 = block_load_mask_10 | p1_block_load_mask_10; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_80 = ~ldq_executed_10; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_81 = ldq_addr_10_valid & _ldq_wakeup_idx_T_80; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_82 = ~ldq_succeeded_10; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_83 = _ldq_wakeup_idx_T_81 & _ldq_wakeup_idx_T_82; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_84 = ~ldq_addr_is_virtual_10; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_85 = _ldq_wakeup_idx_T_83 & _ldq_wakeup_idx_T_84; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_86 = ~ldq_wakeup_idx_block_10; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_87 = _ldq_wakeup_idx_T_85 & _ldq_wakeup_idx_T_86; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_11 = block_load_mask_11 | p1_block_load_mask_11; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_88 = ~ldq_executed_11; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_89 = ldq_addr_11_valid & _ldq_wakeup_idx_T_88; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_90 = ~ldq_succeeded_11; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_91 = _ldq_wakeup_idx_T_89 & _ldq_wakeup_idx_T_90; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_92 = ~ldq_addr_is_virtual_11; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_93 = _ldq_wakeup_idx_T_91 & _ldq_wakeup_idx_T_92; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_94 = ~ldq_wakeup_idx_block_11; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_95 = _ldq_wakeup_idx_T_93 & _ldq_wakeup_idx_T_94; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_12 = block_load_mask_12 | p1_block_load_mask_12; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_96 = ~ldq_executed_12; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_97 = ldq_addr_12_valid & _ldq_wakeup_idx_T_96; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_98 = ~ldq_succeeded_12; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_99 = _ldq_wakeup_idx_T_97 & _ldq_wakeup_idx_T_98; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_100 = ~ldq_addr_is_virtual_12; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_101 = _ldq_wakeup_idx_T_99 & _ldq_wakeup_idx_T_100; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_102 = ~ldq_wakeup_idx_block_12; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_103 = _ldq_wakeup_idx_T_101 & _ldq_wakeup_idx_T_102; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_13 = block_load_mask_13 | p1_block_load_mask_13; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_104 = ~ldq_executed_13; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_105 = ldq_addr_13_valid & _ldq_wakeup_idx_T_104; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_106 = ~ldq_succeeded_13; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_107 = _ldq_wakeup_idx_T_105 & _ldq_wakeup_idx_T_106; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_108 = ~ldq_addr_is_virtual_13; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_109 = _ldq_wakeup_idx_T_107 & _ldq_wakeup_idx_T_108; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_110 = ~ldq_wakeup_idx_block_13; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_111 = _ldq_wakeup_idx_T_109 & _ldq_wakeup_idx_T_110; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_14 = block_load_mask_14 | p1_block_load_mask_14; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_112 = ~ldq_executed_14; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_113 = ldq_addr_14_valid & _ldq_wakeup_idx_T_112; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_114 = ~ldq_succeeded_14; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_115 = _ldq_wakeup_idx_T_113 & _ldq_wakeup_idx_T_114; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_116 = ~ldq_addr_is_virtual_14; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_117 = _ldq_wakeup_idx_T_115 & _ldq_wakeup_idx_T_116; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_118 = ~ldq_wakeup_idx_block_14; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_119 = _ldq_wakeup_idx_T_117 & _ldq_wakeup_idx_T_118; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_15 = block_load_mask_15 | p1_block_load_mask_15; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_120 = ~ldq_executed_15; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_121 = ldq_addr_15_valid & _ldq_wakeup_idx_T_120; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_122 = ~ldq_succeeded_15; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_123 = _ldq_wakeup_idx_T_121 & _ldq_wakeup_idx_T_122; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_124 = ~ldq_addr_is_virtual_15; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_125 = _ldq_wakeup_idx_T_123 & _ldq_wakeup_idx_T_124; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_126 = ~ldq_wakeup_idx_block_15; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_127 = _ldq_wakeup_idx_T_125 & _ldq_wakeup_idx_T_126; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_temp_vec_15 = _ldq_wakeup_idx_T_127; // @[util.scala:352:65] wire _GEN_321 = ldq_head == 4'h0; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T = _GEN_321; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T = _GEN_321; // @[util.scala:352:72] wire _l_idx_temp_vec_T; // @[util.scala:352:72] assign _l_idx_temp_vec_T = _GEN_321; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_0 = _ldq_wakeup_idx_T_7 & _ldq_wakeup_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire _GEN_322 = ldq_head < 4'h2; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_1 = _GEN_322; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_1 = _GEN_322; // @[util.scala:352:72] wire _l_idx_temp_vec_T_1; // @[util.scala:352:72] assign _l_idx_temp_vec_T_1 = _GEN_322; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_1 = _ldq_wakeup_idx_T_15 & _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire _GEN_323 = ldq_head < 4'h3; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_2 = _GEN_323; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_2 = _GEN_323; // @[util.scala:352:72] wire _l_idx_temp_vec_T_2; // @[util.scala:352:72] assign _l_idx_temp_vec_T_2 = _GEN_323; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_2 = _ldq_wakeup_idx_T_23 & _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire _GEN_324 = ldq_head < 4'h4; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_3 = _GEN_324; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_3 = _GEN_324; // @[util.scala:352:72] wire _l_idx_temp_vec_T_3; // @[util.scala:352:72] assign _l_idx_temp_vec_T_3 = _GEN_324; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_3 = _ldq_wakeup_idx_T_31 & _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire _GEN_325 = ldq_head < 4'h5; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_4 = _GEN_325; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_4 = _GEN_325; // @[util.scala:352:72] wire _l_idx_temp_vec_T_4; // @[util.scala:352:72] assign _l_idx_temp_vec_T_4 = _GEN_325; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_4 = _ldq_wakeup_idx_T_39 & _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire _GEN_326 = ldq_head < 4'h6; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_5 = _GEN_326; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_5 = _GEN_326; // @[util.scala:352:72] wire _l_idx_temp_vec_T_5; // @[util.scala:352:72] assign _l_idx_temp_vec_T_5 = _GEN_326; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_5 = _ldq_wakeup_idx_T_47 & _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire _GEN_327 = ldq_head < 4'h7; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_6 = _GEN_327; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_6 = _GEN_327; // @[util.scala:352:72] wire _l_idx_temp_vec_T_6; // @[util.scala:352:72] assign _l_idx_temp_vec_T_6 = _GEN_327; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_6 = _ldq_wakeup_idx_T_55 & _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _ldq_wakeup_idx_temp_vec_T_7 = ~(ldq_head[3]); // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_7 = _ldq_wakeup_idx_T_63 & _ldq_wakeup_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire _GEN_328 = ldq_head < 4'h9; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_8; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_8 = _GEN_328; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_8 = _GEN_328; // @[util.scala:352:72] wire _l_idx_temp_vec_T_8; // @[util.scala:352:72] assign _l_idx_temp_vec_T_8 = _GEN_328; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_8 = _ldq_wakeup_idx_T_71 & _ldq_wakeup_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire _GEN_329 = ldq_head < 4'hA; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_9; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_9 = _GEN_329; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_9 = _GEN_329; // @[util.scala:352:72] wire _l_idx_temp_vec_T_9; // @[util.scala:352:72] assign _l_idx_temp_vec_T_9 = _GEN_329; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_9 = _ldq_wakeup_idx_T_79 & _ldq_wakeup_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire _GEN_330 = ldq_head < 4'hB; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_10; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_10 = _GEN_330; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_10 = _GEN_330; // @[util.scala:352:72] wire _l_idx_temp_vec_T_10; // @[util.scala:352:72] assign _l_idx_temp_vec_T_10 = _GEN_330; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_10 = _ldq_wakeup_idx_T_87 & _ldq_wakeup_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire _GEN_331 = ldq_head[3:2] != 2'h3; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_11; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_11 = _GEN_331; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_11 = _GEN_331; // @[util.scala:352:72] wire _l_idx_temp_vec_T_11; // @[util.scala:352:72] assign _l_idx_temp_vec_T_11 = _GEN_331; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_11 = _ldq_wakeup_idx_T_95 & _ldq_wakeup_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire _GEN_332 = ldq_head < 4'hD; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_12; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_12 = _GEN_332; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_12 = _GEN_332; // @[util.scala:352:72] wire _l_idx_temp_vec_T_12; // @[util.scala:352:72] assign _l_idx_temp_vec_T_12 = _GEN_332; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_12 = _ldq_wakeup_idx_T_103 & _ldq_wakeup_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire _GEN_333 = ldq_head[3:1] != 3'h7; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_13; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_13 = _GEN_333; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_13 = _GEN_333; // @[util.scala:352:72] wire _l_idx_temp_vec_T_13; // @[util.scala:352:72] assign _l_idx_temp_vec_T_13 = _GEN_333; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_13 = _ldq_wakeup_idx_T_111 & _ldq_wakeup_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire _GEN_334 = ldq_head != 4'hF; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_14; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_14 = _GEN_334; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_14 = _GEN_334; // @[util.scala:352:72] wire _l_idx_temp_vec_T_14; // @[util.scala:352:72] assign _l_idx_temp_vec_T_14 = _GEN_334; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_14 = _ldq_wakeup_idx_T_119 & _ldq_wakeup_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire [4:0] _ldq_wakeup_idx_idx_T = {4'hF, ~_ldq_wakeup_idx_T_119}; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_1 = _ldq_wakeup_idx_T_111 ? 5'h1D : _ldq_wakeup_idx_idx_T; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_2 = _ldq_wakeup_idx_T_103 ? 5'h1C : _ldq_wakeup_idx_idx_T_1; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_3 = _ldq_wakeup_idx_T_95 ? 5'h1B : _ldq_wakeup_idx_idx_T_2; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_4 = _ldq_wakeup_idx_T_87 ? 5'h1A : _ldq_wakeup_idx_idx_T_3; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_5 = _ldq_wakeup_idx_T_79 ? 5'h19 : _ldq_wakeup_idx_idx_T_4; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_6 = _ldq_wakeup_idx_T_71 ? 5'h18 : _ldq_wakeup_idx_idx_T_5; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_7 = _ldq_wakeup_idx_T_63 ? 5'h17 : _ldq_wakeup_idx_idx_T_6; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_8 = _ldq_wakeup_idx_T_55 ? 5'h16 : _ldq_wakeup_idx_idx_T_7; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_9 = _ldq_wakeup_idx_T_47 ? 5'h15 : _ldq_wakeup_idx_idx_T_8; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_10 = _ldq_wakeup_idx_T_39 ? 5'h14 : _ldq_wakeup_idx_idx_T_9; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_11 = _ldq_wakeup_idx_T_31 ? 5'h13 : _ldq_wakeup_idx_idx_T_10; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_12 = _ldq_wakeup_idx_T_23 ? 5'h12 : _ldq_wakeup_idx_idx_T_11; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_13 = _ldq_wakeup_idx_T_15 ? 5'h11 : _ldq_wakeup_idx_idx_T_12; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_14 = _ldq_wakeup_idx_T_7 ? 5'h10 : _ldq_wakeup_idx_idx_T_13; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_15 = ldq_wakeup_idx_temp_vec_15 ? 5'hF : _ldq_wakeup_idx_idx_T_14; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_16 = ldq_wakeup_idx_temp_vec_14 ? 5'hE : _ldq_wakeup_idx_idx_T_15; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_17 = ldq_wakeup_idx_temp_vec_13 ? 5'hD : _ldq_wakeup_idx_idx_T_16; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_18 = ldq_wakeup_idx_temp_vec_12 ? 5'hC : _ldq_wakeup_idx_idx_T_17; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_19 = ldq_wakeup_idx_temp_vec_11 ? 5'hB : _ldq_wakeup_idx_idx_T_18; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_20 = ldq_wakeup_idx_temp_vec_10 ? 5'hA : _ldq_wakeup_idx_idx_T_19; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_21 = ldq_wakeup_idx_temp_vec_9 ? 5'h9 : _ldq_wakeup_idx_idx_T_20; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_22 = ldq_wakeup_idx_temp_vec_8 ? 5'h8 : _ldq_wakeup_idx_idx_T_21; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_23 = ldq_wakeup_idx_temp_vec_7 ? 5'h7 : _ldq_wakeup_idx_idx_T_22; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_24 = ldq_wakeup_idx_temp_vec_6 ? 5'h6 : _ldq_wakeup_idx_idx_T_23; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_25 = ldq_wakeup_idx_temp_vec_5 ? 5'h5 : _ldq_wakeup_idx_idx_T_24; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_26 = ldq_wakeup_idx_temp_vec_4 ? 5'h4 : _ldq_wakeup_idx_idx_T_25; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_27 = ldq_wakeup_idx_temp_vec_3 ? 5'h3 : _ldq_wakeup_idx_idx_T_26; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_28 = ldq_wakeup_idx_temp_vec_2 ? 5'h2 : _ldq_wakeup_idx_idx_T_27; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_idx_T_29 = ldq_wakeup_idx_temp_vec_1 ? 5'h1 : _ldq_wakeup_idx_idx_T_28; // @[Mux.scala:50:70] wire [4:0] ldq_wakeup_idx_idx = ldq_wakeup_idx_temp_vec_0 ? 5'h0 : _ldq_wakeup_idx_idx_T_29; // @[Mux.scala:50:70] wire [3:0] _ldq_wakeup_idx_T_128 = ldq_wakeup_idx_idx[3:0]; // @[Mux.scala:50:70] reg [3:0] ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_valid_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_uop_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_addr_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_addr_is_virtual_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_addr_is_uncacheable_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_executed_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_succeeded_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_order_fail_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_observed_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_st_dep_mask_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_ld_byte_mask_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_forward_std_val_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_forward_stq_idx_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _ldq_wakeup_e_e_bits_debug_wb_data_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _can_fire_load_wakeup_T_9 = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [3:0] _can_fire_load_wakeup_T_13 = ldq_wakeup_idx; // @[lsu.scala:506:31] wire ldq_wakeup_e_valid = ldq_wakeup_e_e_valid; // @[lsu.scala:233:17, :510:32] wire [31:0] ldq_wakeup_e_bits_uop_inst = ldq_wakeup_e_e_bits_uop_inst; // @[lsu.scala:233:17, :510:32] wire [31:0] ldq_wakeup_e_bits_uop_debug_inst = ldq_wakeup_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_rvc = ldq_wakeup_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17, :510:32] wire [39:0] ldq_wakeup_e_bits_uop_debug_pc = ldq_wakeup_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_0 = ldq_wakeup_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_1 = ldq_wakeup_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_2 = ldq_wakeup_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_3 = ldq_wakeup_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_0 = ldq_wakeup_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_1 = ldq_wakeup_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_2 = ldq_wakeup_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_3 = ldq_wakeup_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_4 = ldq_wakeup_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_5 = ldq_wakeup_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_6 = ldq_wakeup_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_7 = ldq_wakeup_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_8 = ldq_wakeup_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_9 = ldq_wakeup_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_issued = ldq_wakeup_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_issued_partial_agen = ldq_wakeup_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_issued_partial_dgen = ldq_wakeup_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_iw_p1_speculative_child = ldq_wakeup_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_iw_p2_speculative_child = ldq_wakeup_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_p1_bypass_hint = ldq_wakeup_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_p2_bypass_hint = ldq_wakeup_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_p3_bypass_hint = ldq_wakeup_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_dis_col_sel = ldq_wakeup_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17, :510:32] wire [11:0] ldq_wakeup_e_bits_uop_br_mask = ldq_wakeup_e_e_bits_uop_br_mask; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_uop_br_tag = ldq_wakeup_e_e_bits_uop_br_tag; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_uop_br_type = ldq_wakeup_e_e_bits_uop_br_type; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_sfb = ldq_wakeup_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_fence = ldq_wakeup_e_e_bits_uop_is_fence; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_fencei = ldq_wakeup_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_sfence = ldq_wakeup_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_amo = ldq_wakeup_e_e_bits_uop_is_amo; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_eret = ldq_wakeup_e_e_bits_uop_is_eret; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_sys_pc2epc = ldq_wakeup_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_rocc = ldq_wakeup_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_mov = ldq_wakeup_e_e_bits_uop_is_mov; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_ftq_idx = ldq_wakeup_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_edge_inst = ldq_wakeup_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_pc_lob = ldq_wakeup_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_taken = ldq_wakeup_e_e_bits_uop_taken; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_imm_rename = ldq_wakeup_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_imm_sel = ldq_wakeup_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_pimm = ldq_wakeup_e_e_bits_uop_pimm; // @[lsu.scala:233:17, :510:32] wire [19:0] ldq_wakeup_e_bits_uop_imm_packed = ldq_wakeup_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_op1_sel = ldq_wakeup_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_op2_sel = ldq_wakeup_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ldst = ldq_wakeup_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_wen = ldq_wakeup_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ren1 = ldq_wakeup_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ren2 = ldq_wakeup_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ren3 = ldq_wakeup_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_swap12 = ldq_wakeup_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_swap23 = ldq_wakeup_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn = ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut = ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_fromint = ldq_wakeup_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_toint = ldq_wakeup_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe = ldq_wakeup_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_fma = ldq_wakeup_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_div = ldq_wakeup_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_sqrt = ldq_wakeup_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_wflags = ldq_wakeup_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_vec = ldq_wakeup_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_rob_idx = ldq_wakeup_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_uop_ldq_idx = ldq_wakeup_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_uop_stq_idx = ldq_wakeup_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_rxq_idx = ldq_wakeup_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_pdst = ldq_wakeup_e_e_bits_uop_pdst; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_prs1 = ldq_wakeup_e_e_bits_uop_prs1; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_prs2 = ldq_wakeup_e_e_bits_uop_prs2; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_prs3 = ldq_wakeup_e_e_bits_uop_prs3; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_ppred = ldq_wakeup_e_e_bits_uop_ppred; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_prs1_busy = ldq_wakeup_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_prs2_busy = ldq_wakeup_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_prs3_busy = ldq_wakeup_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_ppred_busy = ldq_wakeup_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_stale_pdst = ldq_wakeup_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_exception = ldq_wakeup_e_e_bits_uop_exception; // @[lsu.scala:233:17, :510:32] wire [63:0] ldq_wakeup_e_bits_uop_exc_cause = ldq_wakeup_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_mem_cmd = ldq_wakeup_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_mem_size = ldq_wakeup_e_e_bits_uop_mem_size; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_mem_signed = ldq_wakeup_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_uses_ldq = ldq_wakeup_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_uses_stq = ldq_wakeup_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_unique = ldq_wakeup_e_e_bits_uop_is_unique; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_flush_on_commit = ldq_wakeup_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_csr_cmd = ldq_wakeup_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_ldst_is_rs1 = ldq_wakeup_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_ldst = ldq_wakeup_e_e_bits_uop_ldst; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_lrs1 = ldq_wakeup_e_e_bits_uop_lrs1; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_lrs2 = ldq_wakeup_e_e_bits_uop_lrs2; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_lrs3 = ldq_wakeup_e_e_bits_uop_lrs3; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_dst_rtype = ldq_wakeup_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_lrs1_rtype = ldq_wakeup_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_lrs2_rtype = ldq_wakeup_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_frs3_en = ldq_wakeup_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fcn_dw = ldq_wakeup_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_fcn_op = ldq_wakeup_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_val = ldq_wakeup_e_e_bits_uop_fp_val; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_fp_rm = ldq_wakeup_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_fp_typ = ldq_wakeup_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_xcpt_pf_if = ldq_wakeup_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_xcpt_ae_if = ldq_wakeup_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_xcpt_ma_if = ldq_wakeup_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_bp_debug_if = ldq_wakeup_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_bp_xcpt_if = ldq_wakeup_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_debug_fsrc = ldq_wakeup_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_debug_tsrc = ldq_wakeup_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_addr_valid = ldq_wakeup_e_e_bits_addr_valid; // @[lsu.scala:233:17, :510:32] wire [39:0] ldq_wakeup_e_bits_addr_bits = ldq_wakeup_e_e_bits_addr_bits; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_addr_is_virtual = ldq_wakeup_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_addr_is_uncacheable = ldq_wakeup_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_executed = ldq_wakeup_e_e_bits_executed; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_succeeded = ldq_wakeup_e_e_bits_succeeded; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_order_fail = ldq_wakeup_e_e_bits_order_fail; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_observed = ldq_wakeup_e_e_bits_observed; // @[lsu.scala:233:17, :510:32] wire [15:0] ldq_wakeup_e_bits_st_dep_mask = ldq_wakeup_e_e_bits_st_dep_mask; // @[lsu.scala:233:17, :510:32] wire [7:0] ldq_wakeup_e_bits_ld_byte_mask = ldq_wakeup_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_forward_std_val = ldq_wakeup_e_e_bits_forward_std_val; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_forward_stq_idx = ldq_wakeup_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17, :510:32] wire [63:0] ldq_wakeup_e_bits_debug_wb_data = ldq_wakeup_e_e_bits_debug_wb_data; // @[lsu.scala:233:17, :510:32] wire [3:0] _ldq_wakeup_e_e_valid_T_1 = _ldq_wakeup_e_e_valid_T; assign ldq_wakeup_e_e_valid = _GEN_25[_ldq_wakeup_e_e_valid_T_1]; // @[lsu.scala:233:17, :234:32, :387:15] wire [3:0] _ldq_wakeup_e_e_bits_uop_T_1 = _ldq_wakeup_e_e_bits_uop_T; assign ldq_wakeup_e_e_bits_uop_inst = _GEN_76[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_inst = _GEN_77[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_rvc = _GEN_78[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_pc = _GEN_79[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_0 = _GEN_80[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_1 = _GEN_81[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_2 = _GEN_82[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_3 = _GEN_83[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_0 = _GEN_84[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_1 = _GEN_85[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_2 = _GEN_86[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_3 = _GEN_87[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_4 = _GEN_88[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_5 = _GEN_89[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_6 = _GEN_90[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_7 = _GEN_91[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_8 = _GEN_92[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_9 = _GEN_93[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_issued = _GEN_94[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_issued_partial_agen = _GEN_95[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_issued_partial_dgen = _GEN_96[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p1_speculative_child = _GEN_97[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p2_speculative_child = _GEN_98[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p1_bypass_hint = _GEN_99[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p2_bypass_hint = _GEN_100[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p3_bypass_hint = _GEN_101[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_dis_col_sel = _GEN_102[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_br_mask = _GEN_103[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_br_tag = _GEN_104[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_br_type = _GEN_105[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_sfb = _GEN_106[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_fence = _GEN_107[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_fencei = _GEN_108[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_sfence = _GEN_109[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_amo = _GEN_110[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_eret = _GEN_111[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_sys_pc2epc = _GEN_112[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_rocc = _GEN_113[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_mov = _GEN_114[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ftq_idx = _GEN_115[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_edge_inst = _GEN_116[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_pc_lob = _GEN_117[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_taken = _GEN_118[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_imm_rename = _GEN_119[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_imm_sel = _GEN_120[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_pimm = _GEN_121[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_imm_packed = _GEN_122[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_op1_sel = _GEN_123[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_op2_sel = _GEN_124[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ldst = _GEN_125[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_wen = _GEN_126[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ren1 = _GEN_127[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ren2 = _GEN_128[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ren3 = _GEN_129[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_swap12 = _GEN_130[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_swap23 = _GEN_131[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_132[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_133[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_fromint = _GEN_134[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_toint = _GEN_135[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_136[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_fma = _GEN_137[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_div = _GEN_138[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_sqrt = _GEN_139[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_wflags = _GEN_140[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_vec = _GEN_141[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_rob_idx = _GEN_142[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ldq_idx = _GEN_143[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_stq_idx = _GEN_144[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_rxq_idx = _GEN_145[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_pdst = _GEN_146[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs1 = _GEN_147[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs2 = _GEN_148[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs3 = _GEN_149[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ppred = _GEN_150[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs1_busy = _GEN_151[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs2_busy = _GEN_152[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs3_busy = _GEN_153[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ppred_busy = _GEN_154[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_stale_pdst = _GEN_155[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_exception = _GEN_156[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_exc_cause = _GEN_157[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_mem_cmd = _GEN_158[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_mem_size = _GEN_159[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_mem_signed = _GEN_160[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_uses_ldq = _GEN_161[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_uses_stq = _GEN_162[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_unique = _GEN_163[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_flush_on_commit = _GEN_164[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_csr_cmd = _GEN_165[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ldst_is_rs1 = _GEN_166[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ldst = _GEN_167[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs1 = _GEN_168[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs2 = _GEN_169[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs3 = _GEN_170[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_dst_rtype = _GEN_171[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs1_rtype = _GEN_172[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs2_rtype = _GEN_173[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_frs3_en = _GEN_174[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fcn_dw = _GEN_175[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fcn_op = _GEN_176[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_val = _GEN_177[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_rm = _GEN_178[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_typ = _GEN_179[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_xcpt_pf_if = _GEN_180[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_xcpt_ae_if = _GEN_181[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_xcpt_ma_if = _GEN_182[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_bp_debug_if = _GEN_183[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_bp_xcpt_if = _GEN_184[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_fsrc = _GEN_185[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_tsrc = _GEN_186[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] wire [3:0] _ldq_wakeup_e_e_bits_addr_T_1 = _ldq_wakeup_e_e_bits_addr_T; assign ldq_wakeup_e_e_bits_addr_valid = _GEN_187[_ldq_wakeup_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] assign ldq_wakeup_e_e_bits_addr_bits = _GEN_188[_ldq_wakeup_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] wire [3:0] _ldq_wakeup_e_e_bits_addr_is_virtual_T_1 = _ldq_wakeup_e_e_bits_addr_is_virtual_T; assign ldq_wakeup_e_e_bits_addr_is_virtual = _GEN_189[_ldq_wakeup_e_e_bits_addr_is_virtual_T_1]; // @[lsu.scala:233:17, :237:32] wire [3:0] _ldq_wakeup_e_e_bits_addr_is_uncacheable_T_1 = _ldq_wakeup_e_e_bits_addr_is_uncacheable_T; assign ldq_wakeup_e_e_bits_addr_is_uncacheable = _GEN_190[_ldq_wakeup_e_e_bits_addr_is_uncacheable_T_1]; // @[lsu.scala:233:17, :238:32] wire [3:0] _ldq_wakeup_e_e_bits_executed_T_1 = _ldq_wakeup_e_e_bits_executed_T; assign ldq_wakeup_e_e_bits_executed = _GEN_191[_ldq_wakeup_e_e_bits_executed_T_1]; // @[lsu.scala:233:17, :239:32] wire [3:0] _ldq_wakeup_e_e_bits_succeeded_T_1 = _ldq_wakeup_e_e_bits_succeeded_T; assign ldq_wakeup_e_e_bits_succeeded = _GEN_192[_ldq_wakeup_e_e_bits_succeeded_T_1]; // @[lsu.scala:233:17, :240:32] wire [3:0] _ldq_wakeup_e_e_bits_order_fail_T_1 = _ldq_wakeup_e_e_bits_order_fail_T; assign ldq_wakeup_e_e_bits_order_fail = _GEN_193[_ldq_wakeup_e_e_bits_order_fail_T_1]; // @[lsu.scala:233:17, :241:32] wire [3:0] _ldq_wakeup_e_e_bits_observed_T_1 = _ldq_wakeup_e_e_bits_observed_T; assign ldq_wakeup_e_e_bits_observed = _GEN_194[_ldq_wakeup_e_e_bits_observed_T_1]; // @[lsu.scala:233:17, :242:32] wire [3:0] _ldq_wakeup_e_e_bits_st_dep_mask_T_1 = _ldq_wakeup_e_e_bits_st_dep_mask_T; assign ldq_wakeup_e_e_bits_st_dep_mask = _GEN_195[_ldq_wakeup_e_e_bits_st_dep_mask_T_1]; // @[lsu.scala:233:17, :243:32] wire [3:0] _ldq_wakeup_e_e_bits_ld_byte_mask_T_1 = _ldq_wakeup_e_e_bits_ld_byte_mask_T; assign ldq_wakeup_e_e_bits_ld_byte_mask = _GEN_196[_ldq_wakeup_e_e_bits_ld_byte_mask_T_1]; // @[lsu.scala:233:17, :244:32] wire [3:0] _ldq_wakeup_e_e_bits_forward_std_val_T_1 = _ldq_wakeup_e_e_bits_forward_std_val_T; assign ldq_wakeup_e_e_bits_forward_std_val = _GEN_197[_ldq_wakeup_e_e_bits_forward_std_val_T_1]; // @[lsu.scala:233:17, :245:32] wire [3:0] _ldq_wakeup_e_e_bits_forward_stq_idx_T_1 = _ldq_wakeup_e_e_bits_forward_stq_idx_T; assign ldq_wakeup_e_e_bits_forward_stq_idx = _GEN_198[_ldq_wakeup_e_e_bits_forward_stq_idx_T_1]; // @[lsu.scala:233:17, :246:32] wire [3:0] _ldq_wakeup_e_e_bits_debug_wb_data_T_1 = _ldq_wakeup_e_e_bits_debug_wb_data_T; assign ldq_wakeup_e_e_bits_debug_wb_data = _GEN_199[_ldq_wakeup_e_e_bits_debug_wb_data_T_1]; // @[lsu.scala:233:17, :247:32] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_inst = ldq_wakeup_e_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_debug_inst = ldq_wakeup_e_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_rvc = ldq_wakeup_e_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_ldq_wakeup_e_out_bits_uop_debug_pc = ldq_wakeup_e_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_0 = ldq_wakeup_e_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_1 = ldq_wakeup_e_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_2 = ldq_wakeup_e_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_3 = ldq_wakeup_e_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_0 = ldq_wakeup_e_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_1 = ldq_wakeup_e_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_2 = ldq_wakeup_e_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_3 = ldq_wakeup_e_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_4 = ldq_wakeup_e_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_5 = ldq_wakeup_e_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_6 = ldq_wakeup_e_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_7 = ldq_wakeup_e_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_8 = ldq_wakeup_e_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_9 = ldq_wakeup_e_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_issued = ldq_wakeup_e_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_issued_partial_agen = ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_issued_partial_dgen = ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_iw_p1_speculative_child = ldq_wakeup_e_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_iw_p2_speculative_child = ldq_wakeup_e_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p1_bypass_hint = ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p2_bypass_hint = ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p3_bypass_hint = ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_dis_col_sel = ldq_wakeup_e_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_br_tag = ldq_wakeup_e_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_br_type = ldq_wakeup_e_bits_uop_br_type; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sfb = ldq_wakeup_e_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fence = ldq_wakeup_e_bits_uop_is_fence; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fencei = ldq_wakeup_e_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sfence = ldq_wakeup_e_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_amo = ldq_wakeup_e_bits_uop_is_amo; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_eret = ldq_wakeup_e_bits_uop_is_eret; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sys_pc2epc = ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_rocc = ldq_wakeup_e_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_mov = ldq_wakeup_e_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ftq_idx = ldq_wakeup_e_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_edge_inst = ldq_wakeup_e_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_pc_lob = ldq_wakeup_e_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_taken = ldq_wakeup_e_bits_uop_taken; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_imm_rename = ldq_wakeup_e_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_imm_sel = ldq_wakeup_e_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_pimm = ldq_wakeup_e_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_ldq_wakeup_e_out_bits_uop_imm_packed = ldq_wakeup_e_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_op1_sel = ldq_wakeup_e_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_op2_sel = ldq_wakeup_e_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ldst = ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_wen = ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ren1 = ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ren2 = ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ren3 = ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_swap12 = ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_swap23 = ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_typeTagIn = ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_typeTagOut = ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_fromint = ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_toint = ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_fastpipe = ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_fma = ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_div = ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_sqrt = ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_wflags = ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_vec = ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_rob_idx = ldq_wakeup_e_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_ldq_idx = ldq_wakeup_e_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_stq_idx = ldq_wakeup_e_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_rxq_idx = ldq_wakeup_e_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_pdst = ldq_wakeup_e_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs1 = ldq_wakeup_e_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs2 = ldq_wakeup_e_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs3 = ldq_wakeup_e_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ppred = ldq_wakeup_e_bits_uop_ppred; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_prs1_busy = ldq_wakeup_e_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_prs2_busy = ldq_wakeup_e_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_prs3_busy = ldq_wakeup_e_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_ppred_busy = ldq_wakeup_e_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_stale_pdst = ldq_wakeup_e_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_exception = ldq_wakeup_e_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_ldq_wakeup_e_out_bits_uop_exc_cause = ldq_wakeup_e_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_mem_cmd = ldq_wakeup_e_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_mem_size = ldq_wakeup_e_bits_uop_mem_size; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_mem_signed = ldq_wakeup_e_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_ldq = ldq_wakeup_e_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_stq = ldq_wakeup_e_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_unique = ldq_wakeup_e_bits_uop_is_unique; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_flush_on_commit = ldq_wakeup_e_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_csr_cmd = ldq_wakeup_e_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_ldst_is_rs1 = ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_ldst = ldq_wakeup_e_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs1 = ldq_wakeup_e_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs2 = ldq_wakeup_e_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs3 = ldq_wakeup_e_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_dst_rtype = ldq_wakeup_e_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs1_rtype = ldq_wakeup_e_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs2_rtype = ldq_wakeup_e_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_frs3_en = ldq_wakeup_e_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fcn_dw = ldq_wakeup_e_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_fcn_op = ldq_wakeup_e_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_val = ldq_wakeup_e_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_fp_rm = ldq_wakeup_e_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_fp_typ = ldq_wakeup_e_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_pf_if = ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ae_if = ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ma_if = ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_debug_if = ldq_wakeup_e_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_xcpt_if = ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_debug_fsrc = ldq_wakeup_e_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_debug_tsrc = ldq_wakeup_e_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_addr_valid = ldq_wakeup_e_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_ldq_wakeup_e_out_bits_addr_bits = ldq_wakeup_e_bits_addr_bits; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_addr_is_virtual = ldq_wakeup_e_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_addr_is_uncacheable = ldq_wakeup_e_bits_addr_is_uncacheable; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_executed = ldq_wakeup_e_bits_executed; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_succeeded = ldq_wakeup_e_bits_succeeded; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_order_fail = ldq_wakeup_e_bits_order_fail; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_observed = ldq_wakeup_e_bits_observed; // @[util.scala:114:23] wire [15:0] mem_ldq_wakeup_e_out_bits_st_dep_mask = ldq_wakeup_e_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] mem_ldq_wakeup_e_out_bits_ld_byte_mask = ldq_wakeup_e_bits_ld_byte_mask; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_forward_std_val = ldq_wakeup_e_bits_forward_std_val; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_forward_stq_idx = ldq_wakeup_e_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] mem_ldq_wakeup_e_out_bits_debug_wb_data = ldq_wakeup_e_bits_debug_wb_data; // @[util.scala:114:23] reg [3:0] ldq_enq_retry_idx; // @[lsu.scala:514:30] wire _ldq_enq_retry_idx_T = ldq_addr_0_valid & ldq_addr_is_virtual_0; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_1 = |ldq_enq_retry_idx; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_2 = _ldq_enq_retry_idx_T & _ldq_enq_retry_idx_T_1; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_3 = ldq_addr_1_valid & ldq_addr_is_virtual_1; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_4 = ldq_enq_retry_idx != 4'h1; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_5 = _ldq_enq_retry_idx_T_3 & _ldq_enq_retry_idx_T_4; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_6 = ldq_addr_2_valid & ldq_addr_is_virtual_2; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_7 = ldq_enq_retry_idx != 4'h2; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_8 = _ldq_enq_retry_idx_T_6 & _ldq_enq_retry_idx_T_7; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_9 = ldq_addr_3_valid & ldq_addr_is_virtual_3; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_10 = ldq_enq_retry_idx != 4'h3; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_11 = _ldq_enq_retry_idx_T_9 & _ldq_enq_retry_idx_T_10; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_12 = ldq_addr_4_valid & ldq_addr_is_virtual_4; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_13 = ldq_enq_retry_idx != 4'h4; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_14 = _ldq_enq_retry_idx_T_12 & _ldq_enq_retry_idx_T_13; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_15 = ldq_addr_5_valid & ldq_addr_is_virtual_5; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_16 = ldq_enq_retry_idx != 4'h5; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_17 = _ldq_enq_retry_idx_T_15 & _ldq_enq_retry_idx_T_16; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_18 = ldq_addr_6_valid & ldq_addr_is_virtual_6; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_19 = ldq_enq_retry_idx != 4'h6; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_20 = _ldq_enq_retry_idx_T_18 & _ldq_enq_retry_idx_T_19; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_21 = ldq_addr_7_valid & ldq_addr_is_virtual_7; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_22 = ldq_enq_retry_idx != 4'h7; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_23 = _ldq_enq_retry_idx_T_21 & _ldq_enq_retry_idx_T_22; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_24 = ldq_addr_8_valid & ldq_addr_is_virtual_8; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_25 = ldq_enq_retry_idx != 4'h8; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_26 = _ldq_enq_retry_idx_T_24 & _ldq_enq_retry_idx_T_25; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_27 = ldq_addr_9_valid & ldq_addr_is_virtual_9; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_28 = ldq_enq_retry_idx != 4'h9; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_29 = _ldq_enq_retry_idx_T_27 & _ldq_enq_retry_idx_T_28; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_30 = ldq_addr_10_valid & ldq_addr_is_virtual_10; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_31 = ldq_enq_retry_idx != 4'hA; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_32 = _ldq_enq_retry_idx_T_30 & _ldq_enq_retry_idx_T_31; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_33 = ldq_addr_11_valid & ldq_addr_is_virtual_11; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_34 = ldq_enq_retry_idx != 4'hB; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_35 = _ldq_enq_retry_idx_T_33 & _ldq_enq_retry_idx_T_34; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_36 = ldq_addr_12_valid & ldq_addr_is_virtual_12; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_37 = ldq_enq_retry_idx != 4'hC; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_38 = _ldq_enq_retry_idx_T_36 & _ldq_enq_retry_idx_T_37; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_39 = ldq_addr_13_valid & ldq_addr_is_virtual_13; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_40 = ldq_enq_retry_idx != 4'hD; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_41 = _ldq_enq_retry_idx_T_39 & _ldq_enq_retry_idx_T_40; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_42 = ldq_addr_14_valid & ldq_addr_is_virtual_14; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_43 = ldq_enq_retry_idx != 4'hE; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_44 = _ldq_enq_retry_idx_T_42 & _ldq_enq_retry_idx_T_43; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_45 = ldq_addr_15_valid & ldq_addr_is_virtual_15; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_46 = ~(&ldq_enq_retry_idx); // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_47 = _ldq_enq_retry_idx_T_45 & _ldq_enq_retry_idx_T_46; // @[lsu.scala:516:{23,49,57}] wire ldq_enq_retry_idx_temp_vec_15 = _ldq_enq_retry_idx_T_47; // @[util.scala:352:65] wire ldq_enq_retry_idx_temp_vec_0 = _ldq_enq_retry_idx_T_2 & _ldq_enq_retry_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_1 = _ldq_enq_retry_idx_T_5 & _ldq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_2 = _ldq_enq_retry_idx_T_8 & _ldq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_3 = _ldq_enq_retry_idx_T_11 & _ldq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_4 = _ldq_enq_retry_idx_T_14 & _ldq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_5 = _ldq_enq_retry_idx_T_17 & _ldq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_6 = _ldq_enq_retry_idx_T_20 & _ldq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _ldq_enq_retry_idx_temp_vec_T_7 = ~(ldq_head[3]); // @[util.scala:352:72] wire ldq_enq_retry_idx_temp_vec_7 = _ldq_enq_retry_idx_T_23 & _ldq_enq_retry_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_8 = _ldq_enq_retry_idx_T_26 & _ldq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_9 = _ldq_enq_retry_idx_T_29 & _ldq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_10 = _ldq_enq_retry_idx_T_32 & _ldq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_11 = _ldq_enq_retry_idx_T_35 & _ldq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_12 = _ldq_enq_retry_idx_T_38 & _ldq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_13 = _ldq_enq_retry_idx_T_41 & _ldq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_14 = _ldq_enq_retry_idx_T_44 & _ldq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire [4:0] _ldq_enq_retry_idx_idx_T = {4'hF, ~_ldq_enq_retry_idx_T_44}; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_1 = _ldq_enq_retry_idx_T_41 ? 5'h1D : _ldq_enq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_2 = _ldq_enq_retry_idx_T_38 ? 5'h1C : _ldq_enq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_3 = _ldq_enq_retry_idx_T_35 ? 5'h1B : _ldq_enq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_4 = _ldq_enq_retry_idx_T_32 ? 5'h1A : _ldq_enq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_5 = _ldq_enq_retry_idx_T_29 ? 5'h19 : _ldq_enq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_6 = _ldq_enq_retry_idx_T_26 ? 5'h18 : _ldq_enq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_7 = _ldq_enq_retry_idx_T_23 ? 5'h17 : _ldq_enq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_8 = _ldq_enq_retry_idx_T_20 ? 5'h16 : _ldq_enq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_9 = _ldq_enq_retry_idx_T_17 ? 5'h15 : _ldq_enq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_10 = _ldq_enq_retry_idx_T_14 ? 5'h14 : _ldq_enq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_11 = _ldq_enq_retry_idx_T_11 ? 5'h13 : _ldq_enq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_12 = _ldq_enq_retry_idx_T_8 ? 5'h12 : _ldq_enq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_13 = _ldq_enq_retry_idx_T_5 ? 5'h11 : _ldq_enq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_14 = _ldq_enq_retry_idx_T_2 ? 5'h10 : _ldq_enq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_15 = ldq_enq_retry_idx_temp_vec_15 ? 5'hF : _ldq_enq_retry_idx_idx_T_14; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_16 = ldq_enq_retry_idx_temp_vec_14 ? 5'hE : _ldq_enq_retry_idx_idx_T_15; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_17 = ldq_enq_retry_idx_temp_vec_13 ? 5'hD : _ldq_enq_retry_idx_idx_T_16; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_18 = ldq_enq_retry_idx_temp_vec_12 ? 5'hC : _ldq_enq_retry_idx_idx_T_17; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_19 = ldq_enq_retry_idx_temp_vec_11 ? 5'hB : _ldq_enq_retry_idx_idx_T_18; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_20 = ldq_enq_retry_idx_temp_vec_10 ? 5'hA : _ldq_enq_retry_idx_idx_T_19; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_21 = ldq_enq_retry_idx_temp_vec_9 ? 5'h9 : _ldq_enq_retry_idx_idx_T_20; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_22 = ldq_enq_retry_idx_temp_vec_8 ? 5'h8 : _ldq_enq_retry_idx_idx_T_21; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_23 = ldq_enq_retry_idx_temp_vec_7 ? 5'h7 : _ldq_enq_retry_idx_idx_T_22; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_24 = ldq_enq_retry_idx_temp_vec_6 ? 5'h6 : _ldq_enq_retry_idx_idx_T_23; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_25 = ldq_enq_retry_idx_temp_vec_5 ? 5'h5 : _ldq_enq_retry_idx_idx_T_24; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_26 = ldq_enq_retry_idx_temp_vec_4 ? 5'h4 : _ldq_enq_retry_idx_idx_T_25; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_27 = ldq_enq_retry_idx_temp_vec_3 ? 5'h3 : _ldq_enq_retry_idx_idx_T_26; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_28 = ldq_enq_retry_idx_temp_vec_2 ? 5'h2 : _ldq_enq_retry_idx_idx_T_27; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_idx_T_29 = ldq_enq_retry_idx_temp_vec_1 ? 5'h1 : _ldq_enq_retry_idx_idx_T_28; // @[Mux.scala:50:70] wire [4:0] ldq_enq_retry_idx_idx = ldq_enq_retry_idx_temp_vec_0 ? 5'h0 : _ldq_enq_retry_idx_idx_T_29; // @[Mux.scala:50:70] wire [3:0] _ldq_enq_retry_idx_T_48 = ldq_enq_retry_idx_idx[3:0]; // @[Mux.scala:50:70] wire ldq_enq_retry_e_valid = ldq_enq_retry_e_e_valid; // @[lsu.scala:233:17, :518:33] wire [31:0] ldq_enq_retry_e_bits_uop_inst = ldq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:233:17, :518:33] wire [31:0] ldq_enq_retry_e_bits_uop_debug_inst = ldq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_rvc = ldq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17, :518:33] wire [39:0] ldq_enq_retry_e_bits_uop_debug_pc = ldq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_0 = ldq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_1 = ldq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_2 = ldq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_3 = ldq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_0 = ldq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_1 = ldq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_2 = ldq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_3 = ldq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_4 = ldq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_5 = ldq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_6 = ldq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_7 = ldq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_8 = ldq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_9 = ldq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_issued = ldq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_issued_partial_agen = ldq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_issued_partial_dgen = ldq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_iw_p1_speculative_child = ldq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_iw_p2_speculative_child = ldq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_p1_bypass_hint = ldq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_p2_bypass_hint = ldq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_p3_bypass_hint = ldq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_dis_col_sel = ldq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17, :518:33] wire [11:0] ldq_enq_retry_e_bits_uop_br_mask = ldq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_uop_br_tag = ldq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_uop_br_type = ldq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_sfb = ldq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_fence = ldq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_fencei = ldq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_sfence = ldq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_amo = ldq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_eret = ldq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_sys_pc2epc = ldq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_rocc = ldq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_mov = ldq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_ftq_idx = ldq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_edge_inst = ldq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_pc_lob = ldq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_taken = ldq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_imm_rename = ldq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_imm_sel = ldq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_pimm = ldq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:233:17, :518:33] wire [19:0] ldq_enq_retry_e_bits_uop_imm_packed = ldq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_op1_sel = ldq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_op2_sel = ldq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ldst = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_wen = ldq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ren1 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ren2 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ren3 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_swap12 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_swap23 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn = ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut = ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_fromint = ldq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_toint = ldq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_fastpipe = ldq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_fma = ldq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_div = ldq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_sqrt = ldq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_wflags = ldq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_vec = ldq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_rob_idx = ldq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_uop_ldq_idx = ldq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_uop_stq_idx = ldq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_rxq_idx = ldq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_pdst = ldq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_prs1 = ldq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_prs2 = ldq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_prs3 = ldq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_ppred = ldq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_prs1_busy = ldq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_prs2_busy = ldq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_prs3_busy = ldq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_ppred_busy = ldq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_stale_pdst = ldq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_exception = ldq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:233:17, :518:33] wire [63:0] ldq_enq_retry_e_bits_uop_exc_cause = ldq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_mem_cmd = ldq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_mem_size = ldq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_mem_signed = ldq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_uses_ldq = ldq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_uses_stq = ldq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_unique = ldq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_flush_on_commit = ldq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_csr_cmd = ldq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_ldst_is_rs1 = ldq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_ldst = ldq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_lrs1 = ldq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_lrs2 = ldq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_lrs3 = ldq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_dst_rtype = ldq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_lrs1_rtype = ldq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_lrs2_rtype = ldq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_frs3_en = ldq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fcn_dw = ldq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_fcn_op = ldq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_val = ldq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_fp_rm = ldq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_fp_typ = ldq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_xcpt_pf_if = ldq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_xcpt_ae_if = ldq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_xcpt_ma_if = ldq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_bp_debug_if = ldq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_bp_xcpt_if = ldq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_debug_fsrc = ldq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_debug_tsrc = ldq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_addr_valid = ldq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:233:17, :518:33] wire [39:0] ldq_enq_retry_e_bits_addr_bits = ldq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_addr_is_virtual = ldq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_addr_is_uncacheable = ldq_enq_retry_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_executed = ldq_enq_retry_e_e_bits_executed; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_succeeded = ldq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_order_fail = ldq_enq_retry_e_e_bits_order_fail; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_observed = ldq_enq_retry_e_e_bits_observed; // @[lsu.scala:233:17, :518:33] wire [15:0] ldq_enq_retry_e_bits_st_dep_mask = ldq_enq_retry_e_e_bits_st_dep_mask; // @[lsu.scala:233:17, :518:33] wire [7:0] ldq_enq_retry_e_bits_ld_byte_mask = ldq_enq_retry_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_forward_std_val = ldq_enq_retry_e_e_bits_forward_std_val; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_forward_stq_idx = ldq_enq_retry_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17, :518:33] wire [63:0] ldq_enq_retry_e_bits_debug_wb_data = ldq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:233:17, :518:33] assign ldq_enq_retry_e_e_valid = _GEN_25[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :234:32, :387:15, :514:30] assign ldq_enq_retry_e_e_bits_uop_inst = _GEN_76[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_inst = _GEN_77[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_rvc = _GEN_78[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_pc = _GEN_79[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_0 = _GEN_80[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_1 = _GEN_81[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_2 = _GEN_82[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_3 = _GEN_83[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_0 = _GEN_84[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_1 = _GEN_85[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_2 = _GEN_86[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_3 = _GEN_87[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_4 = _GEN_88[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_5 = _GEN_89[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_6 = _GEN_90[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_7 = _GEN_91[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_8 = _GEN_92[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_9 = _GEN_93[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_issued = _GEN_94[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_95[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_96[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_97[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_98[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_99[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_100[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_101[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_dis_col_sel = _GEN_102[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_br_mask = _GEN_103[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_br_tag = _GEN_104[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_br_type = _GEN_105[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_sfb = _GEN_106[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_fence = _GEN_107[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_fencei = _GEN_108[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_sfence = _GEN_109[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_amo = _GEN_110[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_eret = _GEN_111[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_112[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_rocc = _GEN_113[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_mov = _GEN_114[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ftq_idx = _GEN_115[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_edge_inst = _GEN_116[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_pc_lob = _GEN_117[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_taken = _GEN_118[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_imm_rename = _GEN_119[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_imm_sel = _GEN_120[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_pimm = _GEN_121[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_imm_packed = _GEN_122[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_op1_sel = _GEN_123[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_op2_sel = _GEN_124[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_125[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_126[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_127[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_128[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_129[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_130[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_131[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_132[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_133[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_134[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_135[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_136[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_137[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_138[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_139[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_140[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_141[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_rob_idx = _GEN_142[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ldq_idx = _GEN_143[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_stq_idx = _GEN_144[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_rxq_idx = _GEN_145[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_pdst = _GEN_146[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs1 = _GEN_147[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs2 = _GEN_148[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs3 = _GEN_149[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ppred = _GEN_150[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs1_busy = _GEN_151[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs2_busy = _GEN_152[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs3_busy = _GEN_153[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ppred_busy = _GEN_154[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_stale_pdst = _GEN_155[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_exception = _GEN_156[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_exc_cause = _GEN_157[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_mem_cmd = _GEN_158[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_mem_size = _GEN_159[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_mem_signed = _GEN_160[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_uses_ldq = _GEN_161[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_uses_stq = _GEN_162[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_unique = _GEN_163[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_flush_on_commit = _GEN_164[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_csr_cmd = _GEN_165[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_166[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ldst = _GEN_167[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs1 = _GEN_168[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs2 = _GEN_169[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs3 = _GEN_170[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_dst_rtype = _GEN_171[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs1_rtype = _GEN_172[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs2_rtype = _GEN_173[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_frs3_en = _GEN_174[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fcn_dw = _GEN_175[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fcn_op = _GEN_176[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_val = _GEN_177[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_rm = _GEN_178[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_typ = _GEN_179[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_180[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_181[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_182[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_bp_debug_if = _GEN_183[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_184[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_fsrc = _GEN_185[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_tsrc = _GEN_186[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_valid = _GEN_187[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :236:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_bits = _GEN_188[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :236:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_is_virtual = _GEN_189[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :237:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_is_uncacheable = _GEN_190[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :238:32, :514:30] assign ldq_enq_retry_e_e_bits_executed = _GEN_191[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :239:32, :514:30] assign ldq_enq_retry_e_e_bits_succeeded = _GEN_192[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :240:32, :514:30] assign ldq_enq_retry_e_e_bits_order_fail = _GEN_193[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :241:32, :514:30] assign ldq_enq_retry_e_e_bits_observed = _GEN_194[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :242:32, :514:30] assign ldq_enq_retry_e_e_bits_st_dep_mask = _GEN_195[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :243:32, :514:30] assign ldq_enq_retry_e_e_bits_ld_byte_mask = _GEN_196[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :244:32, :514:30] assign ldq_enq_retry_e_e_bits_forward_std_val = _GEN_197[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :245:32, :514:30] assign ldq_enq_retry_e_e_bits_forward_stq_idx = _GEN_198[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :246:32, :514:30] assign ldq_enq_retry_e_e_bits_debug_wb_data = _GEN_199[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :247:32, :514:30] reg [3:0] stq_enq_retry_idx; // @[lsu.scala:520:30] wire _stq_enq_retry_idx_T = stq_addr_0_valid & stq_addr_is_virtual_0; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_1 = |stq_enq_retry_idx; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_2 = _stq_enq_retry_idx_T & _stq_enq_retry_idx_T_1; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_3 = stq_addr_1_valid & stq_addr_is_virtual_1; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_4 = stq_enq_retry_idx != 4'h1; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_5 = _stq_enq_retry_idx_T_3 & _stq_enq_retry_idx_T_4; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_6 = stq_addr_2_valid & stq_addr_is_virtual_2; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_7 = stq_enq_retry_idx != 4'h2; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_8 = _stq_enq_retry_idx_T_6 & _stq_enq_retry_idx_T_7; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_9 = stq_addr_3_valid & stq_addr_is_virtual_3; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_10 = stq_enq_retry_idx != 4'h3; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_11 = _stq_enq_retry_idx_T_9 & _stq_enq_retry_idx_T_10; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_12 = stq_addr_4_valid & stq_addr_is_virtual_4; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_13 = stq_enq_retry_idx != 4'h4; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_14 = _stq_enq_retry_idx_T_12 & _stq_enq_retry_idx_T_13; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_15 = stq_addr_5_valid & stq_addr_is_virtual_5; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_16 = stq_enq_retry_idx != 4'h5; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_17 = _stq_enq_retry_idx_T_15 & _stq_enq_retry_idx_T_16; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_18 = stq_addr_6_valid & stq_addr_is_virtual_6; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_19 = stq_enq_retry_idx != 4'h6; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_20 = _stq_enq_retry_idx_T_18 & _stq_enq_retry_idx_T_19; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_21 = stq_addr_7_valid & stq_addr_is_virtual_7; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_22 = stq_enq_retry_idx != 4'h7; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_23 = _stq_enq_retry_idx_T_21 & _stq_enq_retry_idx_T_22; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_24 = stq_addr_8_valid & stq_addr_is_virtual_8; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_25 = stq_enq_retry_idx != 4'h8; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_26 = _stq_enq_retry_idx_T_24 & _stq_enq_retry_idx_T_25; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_27 = stq_addr_9_valid & stq_addr_is_virtual_9; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_28 = stq_enq_retry_idx != 4'h9; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_29 = _stq_enq_retry_idx_T_27 & _stq_enq_retry_idx_T_28; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_30 = stq_addr_10_valid & stq_addr_is_virtual_10; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_31 = stq_enq_retry_idx != 4'hA; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_32 = _stq_enq_retry_idx_T_30 & _stq_enq_retry_idx_T_31; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_33 = stq_addr_11_valid & stq_addr_is_virtual_11; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_34 = stq_enq_retry_idx != 4'hB; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_35 = _stq_enq_retry_idx_T_33 & _stq_enq_retry_idx_T_34; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_36 = stq_addr_12_valid & stq_addr_is_virtual_12; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_37 = stq_enq_retry_idx != 4'hC; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_38 = _stq_enq_retry_idx_T_36 & _stq_enq_retry_idx_T_37; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_39 = stq_addr_13_valid & stq_addr_is_virtual_13; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_40 = stq_enq_retry_idx != 4'hD; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_41 = _stq_enq_retry_idx_T_39 & _stq_enq_retry_idx_T_40; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_42 = stq_addr_14_valid & stq_addr_is_virtual_14; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_43 = stq_enq_retry_idx != 4'hE; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_44 = _stq_enq_retry_idx_T_42 & _stq_enq_retry_idx_T_43; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_45 = stq_addr_15_valid & stq_addr_is_virtual_15; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_46 = ~(&stq_enq_retry_idx); // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_47 = _stq_enq_retry_idx_T_45 & _stq_enq_retry_idx_T_46; // @[lsu.scala:522:{23,49,57}] wire stq_enq_retry_idx_temp_vec_15 = _stq_enq_retry_idx_T_47; // @[util.scala:352:65] wire _GEN_335 = stq_commit_head == 4'h0; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T = _GEN_335; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T = _GEN_335; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_0 = _stq_enq_retry_idx_T_2 & _stq_enq_retry_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire _GEN_336 = stq_commit_head < 4'h2; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_1 = _GEN_336; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_1; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_1 = _GEN_336; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_1 = _stq_enq_retry_idx_T_5 & _stq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire _GEN_337 = stq_commit_head < 4'h3; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_2 = _GEN_337; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_2; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_2 = _GEN_337; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_2 = _stq_enq_retry_idx_T_8 & _stq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire _GEN_338 = stq_commit_head < 4'h4; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_3 = _GEN_338; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_3; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_3 = _GEN_338; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_3 = _stq_enq_retry_idx_T_11 & _stq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire _GEN_339 = stq_commit_head < 4'h5; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_4 = _GEN_339; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_4; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_4 = _GEN_339; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_4 = _stq_enq_retry_idx_T_14 & _stq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire _GEN_340 = stq_commit_head < 4'h6; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_5 = _GEN_340; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_5; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_5 = _GEN_340; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_5 = _stq_enq_retry_idx_T_17 & _stq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire _GEN_341 = stq_commit_head < 4'h7; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_6 = _GEN_341; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_6; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_6 = _GEN_341; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_6 = _stq_enq_retry_idx_T_20 & _stq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _stq_enq_retry_idx_temp_vec_T_7 = ~(stq_commit_head[3]); // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_7 = _stq_enq_retry_idx_T_23 & _stq_enq_retry_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire _GEN_342 = stq_commit_head < 4'h9; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_8 = _GEN_342; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_8; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_8 = _GEN_342; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_8 = _stq_enq_retry_idx_T_26 & _stq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire _GEN_343 = stq_commit_head < 4'hA; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_9 = _GEN_343; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_9; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_9 = _GEN_343; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_9 = _stq_enq_retry_idx_T_29 & _stq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire _GEN_344 = stq_commit_head < 4'hB; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_10 = _GEN_344; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_10; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_10 = _GEN_344; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_10 = _stq_enq_retry_idx_T_32 & _stq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire _GEN_345 = stq_commit_head[3:2] != 2'h3; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_11 = _GEN_345; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_11; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_11 = _GEN_345; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_11 = _stq_enq_retry_idx_T_35 & _stq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire _GEN_346 = stq_commit_head < 4'hD; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_12 = _GEN_346; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_12; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_12 = _GEN_346; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_12 = _stq_enq_retry_idx_T_38 & _stq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire _GEN_347 = stq_commit_head[3:1] != 3'h7; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_13 = _GEN_347; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_13; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_13 = _GEN_347; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_13 = _stq_enq_retry_idx_T_41 & _stq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire _GEN_348 = stq_commit_head != 4'hF; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_14 = _GEN_348; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_14; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_14 = _GEN_348; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_14 = _stq_enq_retry_idx_T_44 & _stq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire [4:0] _stq_enq_retry_idx_idx_T = {4'hF, ~_stq_enq_retry_idx_T_44}; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_1 = _stq_enq_retry_idx_T_41 ? 5'h1D : _stq_enq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_2 = _stq_enq_retry_idx_T_38 ? 5'h1C : _stq_enq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_3 = _stq_enq_retry_idx_T_35 ? 5'h1B : _stq_enq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_4 = _stq_enq_retry_idx_T_32 ? 5'h1A : _stq_enq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_5 = _stq_enq_retry_idx_T_29 ? 5'h19 : _stq_enq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_6 = _stq_enq_retry_idx_T_26 ? 5'h18 : _stq_enq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_7 = _stq_enq_retry_idx_T_23 ? 5'h17 : _stq_enq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_8 = _stq_enq_retry_idx_T_20 ? 5'h16 : _stq_enq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_9 = _stq_enq_retry_idx_T_17 ? 5'h15 : _stq_enq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_10 = _stq_enq_retry_idx_T_14 ? 5'h14 : _stq_enq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_11 = _stq_enq_retry_idx_T_11 ? 5'h13 : _stq_enq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_12 = _stq_enq_retry_idx_T_8 ? 5'h12 : _stq_enq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_13 = _stq_enq_retry_idx_T_5 ? 5'h11 : _stq_enq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_14 = _stq_enq_retry_idx_T_2 ? 5'h10 : _stq_enq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_15 = stq_enq_retry_idx_temp_vec_15 ? 5'hF : _stq_enq_retry_idx_idx_T_14; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_16 = stq_enq_retry_idx_temp_vec_14 ? 5'hE : _stq_enq_retry_idx_idx_T_15; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_17 = stq_enq_retry_idx_temp_vec_13 ? 5'hD : _stq_enq_retry_idx_idx_T_16; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_18 = stq_enq_retry_idx_temp_vec_12 ? 5'hC : _stq_enq_retry_idx_idx_T_17; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_19 = stq_enq_retry_idx_temp_vec_11 ? 5'hB : _stq_enq_retry_idx_idx_T_18; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_20 = stq_enq_retry_idx_temp_vec_10 ? 5'hA : _stq_enq_retry_idx_idx_T_19; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_21 = stq_enq_retry_idx_temp_vec_9 ? 5'h9 : _stq_enq_retry_idx_idx_T_20; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_22 = stq_enq_retry_idx_temp_vec_8 ? 5'h8 : _stq_enq_retry_idx_idx_T_21; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_23 = stq_enq_retry_idx_temp_vec_7 ? 5'h7 : _stq_enq_retry_idx_idx_T_22; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_24 = stq_enq_retry_idx_temp_vec_6 ? 5'h6 : _stq_enq_retry_idx_idx_T_23; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_25 = stq_enq_retry_idx_temp_vec_5 ? 5'h5 : _stq_enq_retry_idx_idx_T_24; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_26 = stq_enq_retry_idx_temp_vec_4 ? 5'h4 : _stq_enq_retry_idx_idx_T_25; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_27 = stq_enq_retry_idx_temp_vec_3 ? 5'h3 : _stq_enq_retry_idx_idx_T_26; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_28 = stq_enq_retry_idx_temp_vec_2 ? 5'h2 : _stq_enq_retry_idx_idx_T_27; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_idx_T_29 = stq_enq_retry_idx_temp_vec_1 ? 5'h1 : _stq_enq_retry_idx_idx_T_28; // @[Mux.scala:50:70] wire [4:0] stq_enq_retry_idx_idx = stq_enq_retry_idx_temp_vec_0 ? 5'h0 : _stq_enq_retry_idx_idx_T_29; // @[Mux.scala:50:70] wire [3:0] _stq_enq_retry_idx_T_48 = stq_enq_retry_idx_idx[3:0]; // @[Mux.scala:50:70] wire stq_enq_retry_e_valid = stq_enq_retry_e_e_valid; // @[lsu.scala:262:17, :524:35] wire [31:0] stq_enq_retry_e_bits_uop_inst = stq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:262:17, :524:35] wire [31:0] stq_enq_retry_e_bits_uop_debug_inst = stq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_rvc = stq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17, :524:35] wire [39:0] stq_enq_retry_e_bits_uop_debug_pc = stq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_0 = stq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_1 = stq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_2 = stq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_3 = stq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_0 = stq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_1 = stq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_2 = stq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_3 = stq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_4 = stq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_5 = stq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_6 = stq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_7 = stq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_8 = stq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_9 = stq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_issued = stq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_issued_partial_agen = stq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_issued_partial_dgen = stq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_iw_p1_speculative_child = stq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_iw_p2_speculative_child = stq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_p1_bypass_hint = stq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_p2_bypass_hint = stq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_p3_bypass_hint = stq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_dis_col_sel = stq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17, :524:35] wire [11:0] stq_enq_retry_e_bits_uop_br_mask = stq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:262:17, :524:35] wire [3:0] stq_enq_retry_e_bits_uop_br_tag = stq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:262:17, :524:35] wire [3:0] stq_enq_retry_e_bits_uop_br_type = stq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_sfb = stq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_fence = stq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_fencei = stq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_sfence = stq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_amo = stq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_eret = stq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_sys_pc2epc = stq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_rocc = stq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_mov = stq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_ftq_idx = stq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_edge_inst = stq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_pc_lob = stq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_taken = stq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_imm_rename = stq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_imm_sel = stq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_pimm = stq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:262:17, :524:35] wire [19:0] stq_enq_retry_e_bits_uop_imm_packed = stq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_op1_sel = stq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_op2_sel = stq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ldst = stq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_wen = stq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ren1 = stq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ren2 = stq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ren3 = stq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_swap12 = stq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_swap23 = stq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn = stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut = stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_fromint = stq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_toint = stq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_fastpipe = stq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_fma = stq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_div = stq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_sqrt = stq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_wflags = stq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_vec = stq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_rob_idx = stq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17, :524:35] wire [3:0] stq_enq_retry_e_bits_uop_ldq_idx = stq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17, :524:35] wire [3:0] stq_enq_retry_e_bits_uop_stq_idx = stq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_rxq_idx = stq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_pdst = stq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_prs1 = stq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_prs2 = stq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_prs3 = stq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_ppred = stq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_prs1_busy = stq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_prs2_busy = stq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_prs3_busy = stq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_ppred_busy = stq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_stale_pdst = stq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_exception = stq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:262:17, :524:35] wire [63:0] stq_enq_retry_e_bits_uop_exc_cause = stq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_mem_cmd = stq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_mem_size = stq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_mem_signed = stq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_uses_ldq = stq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_uses_stq = stq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_unique = stq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_flush_on_commit = stq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_csr_cmd = stq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_ldst_is_rs1 = stq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_ldst = stq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_lrs1 = stq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_lrs2 = stq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_lrs3 = stq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_dst_rtype = stq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_lrs1_rtype = stq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_lrs2_rtype = stq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_frs3_en = stq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fcn_dw = stq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_fcn_op = stq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_val = stq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_fp_rm = stq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_fp_typ = stq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_xcpt_pf_if = stq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_xcpt_ae_if = stq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_xcpt_ma_if = stq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_bp_debug_if = stq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_bp_xcpt_if = stq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_debug_fsrc = stq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_debug_tsrc = stq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_addr_valid = stq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:262:17, :524:35] wire [39:0] stq_enq_retry_e_bits_addr_bits = stq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_addr_is_virtual = stq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_data_valid = stq_enq_retry_e_e_bits_data_valid; // @[lsu.scala:262:17, :524:35] wire [63:0] stq_enq_retry_e_bits_data_bits = stq_enq_retry_e_e_bits_data_bits; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_committed = stq_enq_retry_e_e_bits_committed; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_succeeded = stq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_can_execute = stq_enq_retry_e_e_bits_can_execute; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_cleared = stq_enq_retry_e_e_bits_cleared; // @[lsu.scala:262:17, :524:35] wire [63:0] stq_enq_retry_e_bits_debug_wb_data = stq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:262:17, :524:35] assign stq_enq_retry_e_e_valid = _GEN_26[stq_enq_retry_idx]; // @[lsu.scala:262:17, :263:32, :392:15, :520:30] assign stq_enq_retry_e_e_bits_uop_inst = _GEN_200[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_inst = _GEN_201[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_rvc = _GEN_202[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_pc = _GEN_203[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_0 = _GEN_204[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_1 = _GEN_205[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_2 = _GEN_206[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_3 = _GEN_207[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_0 = _GEN_208[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_1 = _GEN_209[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_2 = _GEN_210[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_3 = _GEN_211[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_4 = _GEN_212[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_5 = _GEN_213[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_6 = _GEN_214[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_7 = _GEN_215[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_8 = _GEN_216[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_9 = _GEN_217[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_issued = _GEN_218[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_219[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_220[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_221[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_222[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_223[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_224[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_225[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_dis_col_sel = _GEN_226[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_br_mask = _GEN_227[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_br_tag = _GEN_228[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_br_type = _GEN_229[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_sfb = _GEN_230[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_fence = _GEN_231[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_fencei = _GEN_232[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_sfence = _GEN_233[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_amo = _GEN_234[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_eret = _GEN_235[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_236[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_rocc = _GEN_237[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_mov = _GEN_238[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ftq_idx = _GEN_239[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_edge_inst = _GEN_240[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_pc_lob = _GEN_241[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_taken = _GEN_242[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_imm_rename = _GEN_243[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_imm_sel = _GEN_244[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_pimm = _GEN_245[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_imm_packed = _GEN_246[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_op1_sel = _GEN_247[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_op2_sel = _GEN_248[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_249[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_250[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_251[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_252[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_253[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_254[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_255[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_256[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_257[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_258[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_259[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_260[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_261[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_262[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_263[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_264[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_265[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_rob_idx = _GEN_266[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ldq_idx = _GEN_267[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_stq_idx = _GEN_268[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_rxq_idx = _GEN_269[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_pdst = _GEN_270[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs1 = _GEN_271[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs2 = _GEN_272[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs3 = _GEN_273[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ppred = _GEN_274[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs1_busy = _GEN_275[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs2_busy = _GEN_276[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs3_busy = _GEN_277[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ppred_busy = _GEN_278[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_stale_pdst = _GEN_279[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_exception = _GEN_280[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_exc_cause = _GEN_281[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_mem_cmd = _GEN_282[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_mem_size = _GEN_283[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_mem_signed = _GEN_284[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_uses_ldq = _GEN_285[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_uses_stq = _GEN_286[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_unique = _GEN_287[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_flush_on_commit = _GEN_288[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_csr_cmd = _GEN_289[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_290[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ldst = _GEN_291[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs1 = _GEN_292[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs2 = _GEN_293[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs3 = _GEN_294[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_dst_rtype = _GEN_295[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs1_rtype = _GEN_296[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs2_rtype = _GEN_297[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_frs3_en = _GEN_298[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fcn_dw = _GEN_299[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fcn_op = _GEN_300[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_val = _GEN_301[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_rm = _GEN_302[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_typ = _GEN_303[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_304[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_305[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_306[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_bp_debug_if = _GEN_307[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_308[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_fsrc = _GEN_309[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_tsrc = _GEN_310[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_addr_valid = _GEN_311[stq_enq_retry_idx]; // @[lsu.scala:262:17, :265:32, :520:30] assign stq_enq_retry_e_e_bits_addr_bits = _GEN_312[stq_enq_retry_idx]; // @[lsu.scala:262:17, :265:32, :520:30] assign stq_enq_retry_e_e_bits_addr_is_virtual = _GEN_313[stq_enq_retry_idx]; // @[lsu.scala:262:17, :266:32, :520:30] assign stq_enq_retry_e_e_bits_data_valid = _GEN_314[stq_enq_retry_idx]; // @[lsu.scala:262:17, :267:32, :520:30] assign stq_enq_retry_e_e_bits_data_bits = _GEN_315[stq_enq_retry_idx]; // @[lsu.scala:262:17, :267:32, :520:30] assign stq_enq_retry_e_e_bits_committed = _GEN_316[stq_enq_retry_idx]; // @[lsu.scala:262:17, :268:32, :520:30] assign stq_enq_retry_e_e_bits_succeeded = _GEN_317[stq_enq_retry_idx]; // @[lsu.scala:262:17, :269:32, :520:30] assign stq_enq_retry_e_e_bits_can_execute = _GEN_318[stq_enq_retry_idx]; // @[lsu.scala:262:17, :270:32, :520:30] assign stq_enq_retry_e_e_bits_cleared = _GEN_319[stq_enq_retry_idx]; // @[lsu.scala:262:17, :271:32, :520:30] assign stq_enq_retry_e_e_bits_debug_wb_data = _GEN_320[stq_enq_retry_idx]; // @[lsu.scala:262:17, :272:32, :520:30] wire _can_enq_load_retry_T = ldq_enq_retry_e_valid & ldq_enq_retry_e_bits_addr_valid; // @[lsu.scala:518:33, :526:81] wire can_enq_load_retry = _can_enq_load_retry_T & ldq_enq_retry_e_bits_addr_is_virtual; // @[lsu.scala:518:33, :526:81, :527:81] wire _can_enq_store_retry_T = stq_enq_retry_e_valid & stq_enq_retry_e_bits_addr_valid; // @[lsu.scala:524:35, :529:81] wire can_enq_store_retry = _can_enq_store_retry_T & stq_enq_retry_e_bits_addr_is_virtual; // @[lsu.scala:524:35, :529:81, :530:81] wire _retry_queue_io_enq_valid_T = can_enq_store_retry | can_enq_load_retry; // @[lsu.scala:527:81, :530:81, :537:55] wire [39:0] _retry_queue_io_enq_bits_data_T = can_enq_store_retry ? stq_enq_retry_e_bits_addr_bits : ldq_enq_retry_e_bits_addr_bits; // @[lsu.scala:518:33, :524:35, :530:81, :539:38] wire [31:0] _retry_queue_io_enq_bits_uop_T_inst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_inst : ldq_enq_retry_e_bits_uop_inst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [31:0] _retry_queue_io_enq_bits_uop_T_debug_inst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_inst : ldq_enq_retry_e_bits_uop_debug_inst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_rvc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_rvc : ldq_enq_retry_e_bits_uop_is_rvc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [39:0] _retry_queue_io_enq_bits_uop_T_debug_pc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_pc : ldq_enq_retry_e_bits_uop_debug_pc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_0 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_0 : ldq_enq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_1 : ldq_enq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_2 : ldq_enq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_3 : ldq_enq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_0 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_0 : ldq_enq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_1 : ldq_enq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_2 : ldq_enq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_3 : ldq_enq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_4 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_4 : ldq_enq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_5 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_5 : ldq_enq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_6 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_6 : ldq_enq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_7 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_7 : ldq_enq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_8 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_8 : ldq_enq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_9 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_9 : ldq_enq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_issued = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_issued : ldq_enq_retry_e_bits_uop_iw_issued; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_issued_partial_agen = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_issued_partial_agen : ldq_enq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_issued_partial_dgen = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_issued_partial_dgen : ldq_enq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_iw_p1_speculative_child = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p1_speculative_child : ldq_enq_retry_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_iw_p2_speculative_child = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p2_speculative_child : ldq_enq_retry_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_p1_bypass_hint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p1_bypass_hint : ldq_enq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_p2_bypass_hint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p2_bypass_hint : ldq_enq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_p3_bypass_hint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p3_bypass_hint : ldq_enq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_dis_col_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_dis_col_sel : ldq_enq_retry_e_bits_uop_dis_col_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [11:0] _retry_queue_io_enq_bits_uop_T_br_mask = can_enq_store_retry ? stq_enq_retry_e_bits_uop_br_mask : ldq_enq_retry_e_bits_uop_br_mask; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [3:0] _retry_queue_io_enq_bits_uop_T_br_tag = can_enq_store_retry ? stq_enq_retry_e_bits_uop_br_tag : ldq_enq_retry_e_bits_uop_br_tag; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [3:0] _retry_queue_io_enq_bits_uop_T_br_type = can_enq_store_retry ? stq_enq_retry_e_bits_uop_br_type : ldq_enq_retry_e_bits_uop_br_type; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_sfb = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_sfb : ldq_enq_retry_e_bits_uop_is_sfb; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_fence = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_fence : ldq_enq_retry_e_bits_uop_is_fence; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_fencei = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_fencei : ldq_enq_retry_e_bits_uop_is_fencei; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_sfence = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_sfence : ldq_enq_retry_e_bits_uop_is_sfence; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_amo = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_amo : ldq_enq_retry_e_bits_uop_is_amo; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_eret = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_eret : ldq_enq_retry_e_bits_uop_is_eret; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_sys_pc2epc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_sys_pc2epc : ldq_enq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_rocc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_rocc : ldq_enq_retry_e_bits_uop_is_rocc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_mov = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_mov : ldq_enq_retry_e_bits_uop_is_mov; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_ftq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ftq_idx : ldq_enq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_edge_inst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_edge_inst : ldq_enq_retry_e_bits_uop_edge_inst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_pc_lob = can_enq_store_retry ? stq_enq_retry_e_bits_uop_pc_lob : ldq_enq_retry_e_bits_uop_pc_lob; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_taken = can_enq_store_retry ? stq_enq_retry_e_bits_uop_taken : ldq_enq_retry_e_bits_uop_taken; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_imm_rename = can_enq_store_retry ? stq_enq_retry_e_bits_uop_imm_rename : ldq_enq_retry_e_bits_uop_imm_rename; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_imm_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_imm_sel : ldq_enq_retry_e_bits_uop_imm_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_pimm = can_enq_store_retry ? stq_enq_retry_e_bits_uop_pimm : ldq_enq_retry_e_bits_uop_pimm; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [19:0] _retry_queue_io_enq_bits_uop_T_imm_packed = can_enq_store_retry ? stq_enq_retry_e_bits_uop_imm_packed : ldq_enq_retry_e_bits_uop_imm_packed; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_op1_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_op1_sel : ldq_enq_retry_e_bits_uop_op1_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_op2_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_op2_sel : ldq_enq_retry_e_bits_uop_op2_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ldst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ldst : ldq_enq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_wen = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_wen : ldq_enq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ren1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ren1 : ldq_enq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ren2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ren2 : ldq_enq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ren3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ren3 : ldq_enq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_swap12 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_swap12 : ldq_enq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_swap23 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_swap23 : ldq_enq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_fp_ctrl_typeTagIn = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn : ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_fp_ctrl_typeTagOut = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut : ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_fromint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_fromint : ldq_enq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_toint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_toint : ldq_enq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_fastpipe = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_fastpipe : ldq_enq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_fma = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_fma : ldq_enq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_div = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_div : ldq_enq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_sqrt = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_sqrt : ldq_enq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_wflags = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_wflags : ldq_enq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_vec = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_vec : ldq_enq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_rob_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_rob_idx : ldq_enq_retry_e_bits_uop_rob_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [3:0] _retry_queue_io_enq_bits_uop_T_ldq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ldq_idx : ldq_enq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [3:0] _retry_queue_io_enq_bits_uop_T_stq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_stq_idx : ldq_enq_retry_e_bits_uop_stq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_rxq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_rxq_idx : ldq_enq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_pdst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_pdst : ldq_enq_retry_e_bits_uop_pdst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_prs1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs1 : ldq_enq_retry_e_bits_uop_prs1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_prs2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs2 : ldq_enq_retry_e_bits_uop_prs2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_prs3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs3 : ldq_enq_retry_e_bits_uop_prs3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_ppred = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ppred : ldq_enq_retry_e_bits_uop_ppred; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_prs1_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs1_busy : ldq_enq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_prs2_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs2_busy : ldq_enq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_prs3_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs3_busy : ldq_enq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_ppred_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ppred_busy : ldq_enq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_stale_pdst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_stale_pdst : ldq_enq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_exception = can_enq_store_retry ? stq_enq_retry_e_bits_uop_exception : ldq_enq_retry_e_bits_uop_exception; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [63:0] _retry_queue_io_enq_bits_uop_T_exc_cause = can_enq_store_retry ? stq_enq_retry_e_bits_uop_exc_cause : ldq_enq_retry_e_bits_uop_exc_cause; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_mem_cmd = can_enq_store_retry ? stq_enq_retry_e_bits_uop_mem_cmd : ldq_enq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_mem_size = can_enq_store_retry ? stq_enq_retry_e_bits_uop_mem_size : ldq_enq_retry_e_bits_uop_mem_size; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_mem_signed = can_enq_store_retry ? stq_enq_retry_e_bits_uop_mem_signed : ldq_enq_retry_e_bits_uop_mem_signed; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_uses_ldq = can_enq_store_retry ? stq_enq_retry_e_bits_uop_uses_ldq : ldq_enq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_uses_stq = can_enq_store_retry ? stq_enq_retry_e_bits_uop_uses_stq : ldq_enq_retry_e_bits_uop_uses_stq; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_unique = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_unique : ldq_enq_retry_e_bits_uop_is_unique; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_flush_on_commit = can_enq_store_retry ? stq_enq_retry_e_bits_uop_flush_on_commit : ldq_enq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_csr_cmd = can_enq_store_retry ? stq_enq_retry_e_bits_uop_csr_cmd : ldq_enq_retry_e_bits_uop_csr_cmd; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_ldst_is_rs1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ldst_is_rs1 : ldq_enq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_ldst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ldst : ldq_enq_retry_e_bits_uop_ldst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_lrs1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs1 : ldq_enq_retry_e_bits_uop_lrs1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_lrs2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs2 : ldq_enq_retry_e_bits_uop_lrs2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_lrs3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs3 : ldq_enq_retry_e_bits_uop_lrs3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_dst_rtype = can_enq_store_retry ? stq_enq_retry_e_bits_uop_dst_rtype : ldq_enq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_lrs1_rtype = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs1_rtype : ldq_enq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_lrs2_rtype = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs2_rtype : ldq_enq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_frs3_en = can_enq_store_retry ? stq_enq_retry_e_bits_uop_frs3_en : ldq_enq_retry_e_bits_uop_frs3_en; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fcn_dw = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fcn_dw : ldq_enq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_fcn_op = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fcn_op : ldq_enq_retry_e_bits_uop_fcn_op; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_val = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_val : ldq_enq_retry_e_bits_uop_fp_val; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_fp_rm = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_rm : ldq_enq_retry_e_bits_uop_fp_rm; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_fp_typ = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_typ : ldq_enq_retry_e_bits_uop_fp_typ; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_xcpt_pf_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_xcpt_pf_if : ldq_enq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_xcpt_ae_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_xcpt_ae_if : ldq_enq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_xcpt_ma_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_xcpt_ma_if : ldq_enq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_bp_debug_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_bp_debug_if : ldq_enq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_bp_xcpt_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_bp_xcpt_if : ldq_enq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_debug_fsrc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_fsrc : ldq_enq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_debug_tsrc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_tsrc : ldq_enq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_uses_ldq_T = ~can_enq_store_retry; // @[lsu.scala:530:81, :541:65] wire _retry_queue_io_enq_bits_uop_uses_ldq_T_1 = can_enq_load_retry & _retry_queue_io_enq_bits_uop_uses_ldq_T; // @[lsu.scala:527:81, :541:{62,65}] wire _GEN_349 = will_fire_load_retry_0 | will_fire_store_retry_0; // @[lsu.scala:476:41, :477:41, :554:65] wire _retry_queue_io_deq_ready_T; // @[lsu.scala:554:65] assign _retry_queue_io_deq_ready_T = _GEN_349; // @[lsu.scala:554:65] wire _exe_tlb_uop_T_1; // @[lsu.scala:720:53] assign _exe_tlb_uop_T_1 = _GEN_349; // @[lsu.scala:554:65, :720:53] wire _exe_tlb_vaddr_T_2; // @[lsu.scala:730:53] assign _exe_tlb_vaddr_T_2 = _GEN_349; // @[lsu.scala:554:65, :730:53] wire stq_execute_queue_flush; // @[lsu.scala:556:41] wire stq_enq_e_valid = stq_enq_e_e_valid; // @[lsu.scala:262:17, :561:27] wire [31:0] stq_enq_e_bits_uop_inst = stq_enq_e_e_bits_uop_inst; // @[lsu.scala:262:17, :561:27] wire [31:0] stq_enq_e_bits_uop_debug_inst = stq_enq_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_rvc = stq_enq_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17, :561:27] wire [39:0] stq_enq_e_bits_uop_debug_pc = stq_enq_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_0 = stq_enq_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_1 = stq_enq_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_2 = stq_enq_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_3 = stq_enq_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_0 = stq_enq_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_1 = stq_enq_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_2 = stq_enq_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_3 = stq_enq_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_4 = stq_enq_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_5 = stq_enq_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_6 = stq_enq_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_7 = stq_enq_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_8 = stq_enq_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_9 = stq_enq_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_issued = stq_enq_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_issued_partial_agen = stq_enq_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_issued_partial_dgen = stq_enq_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_iw_p1_speculative_child = stq_enq_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_iw_p2_speculative_child = stq_enq_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_p1_bypass_hint = stq_enq_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_p2_bypass_hint = stq_enq_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_p3_bypass_hint = stq_enq_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_dis_col_sel = stq_enq_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17, :561:27] wire [11:0] stq_enq_e_bits_uop_br_mask = stq_enq_e_e_bits_uop_br_mask; // @[lsu.scala:262:17, :561:27] wire [3:0] stq_enq_e_bits_uop_br_tag = stq_enq_e_e_bits_uop_br_tag; // @[lsu.scala:262:17, :561:27] wire [3:0] stq_enq_e_bits_uop_br_type = stq_enq_e_e_bits_uop_br_type; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_sfb = stq_enq_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_fence = stq_enq_e_e_bits_uop_is_fence; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_fencei = stq_enq_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_sfence = stq_enq_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_amo = stq_enq_e_e_bits_uop_is_amo; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_eret = stq_enq_e_e_bits_uop_is_eret; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_sys_pc2epc = stq_enq_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_rocc = stq_enq_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_mov = stq_enq_e_e_bits_uop_is_mov; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_ftq_idx = stq_enq_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_edge_inst = stq_enq_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_pc_lob = stq_enq_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_taken = stq_enq_e_e_bits_uop_taken; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_imm_rename = stq_enq_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_imm_sel = stq_enq_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_pimm = stq_enq_e_e_bits_uop_pimm; // @[lsu.scala:262:17, :561:27] wire [19:0] stq_enq_e_bits_uop_imm_packed = stq_enq_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_op1_sel = stq_enq_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_op2_sel = stq_enq_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ldst = stq_enq_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_wen = stq_enq_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ren1 = stq_enq_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ren2 = stq_enq_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ren3 = stq_enq_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_swap12 = stq_enq_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_swap23 = stq_enq_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_fp_ctrl_typeTagIn = stq_enq_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_fp_ctrl_typeTagOut = stq_enq_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_fromint = stq_enq_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_toint = stq_enq_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_fastpipe = stq_enq_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_fma = stq_enq_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_div = stq_enq_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_sqrt = stq_enq_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_wflags = stq_enq_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_vec = stq_enq_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_rob_idx = stq_enq_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17, :561:27] wire [3:0] stq_enq_e_bits_uop_ldq_idx = stq_enq_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17, :561:27] wire [3:0] stq_enq_e_bits_uop_stq_idx = stq_enq_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_rxq_idx = stq_enq_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_pdst = stq_enq_e_e_bits_uop_pdst; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_prs1 = stq_enq_e_e_bits_uop_prs1; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_prs2 = stq_enq_e_e_bits_uop_prs2; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_prs3 = stq_enq_e_e_bits_uop_prs3; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_ppred = stq_enq_e_e_bits_uop_ppred; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_prs1_busy = stq_enq_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_prs2_busy = stq_enq_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_prs3_busy = stq_enq_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_ppred_busy = stq_enq_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_stale_pdst = stq_enq_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_exception = stq_enq_e_e_bits_uop_exception; // @[lsu.scala:262:17, :561:27] wire [63:0] stq_enq_e_bits_uop_exc_cause = stq_enq_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_mem_cmd = stq_enq_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_mem_size = stq_enq_e_e_bits_uop_mem_size; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_mem_signed = stq_enq_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_uses_ldq = stq_enq_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_uses_stq = stq_enq_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_unique = stq_enq_e_e_bits_uop_is_unique; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_flush_on_commit = stq_enq_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_csr_cmd = stq_enq_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_ldst_is_rs1 = stq_enq_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_ldst = stq_enq_e_e_bits_uop_ldst; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_lrs1 = stq_enq_e_e_bits_uop_lrs1; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_lrs2 = stq_enq_e_e_bits_uop_lrs2; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_lrs3 = stq_enq_e_e_bits_uop_lrs3; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_dst_rtype = stq_enq_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_lrs1_rtype = stq_enq_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_lrs2_rtype = stq_enq_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_frs3_en = stq_enq_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fcn_dw = stq_enq_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_fcn_op = stq_enq_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_val = stq_enq_e_e_bits_uop_fp_val; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_fp_rm = stq_enq_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_fp_typ = stq_enq_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_xcpt_pf_if = stq_enq_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_xcpt_ae_if = stq_enq_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_xcpt_ma_if = stq_enq_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_bp_debug_if = stq_enq_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_bp_xcpt_if = stq_enq_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_debug_fsrc = stq_enq_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_debug_tsrc = stq_enq_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_addr_valid = stq_enq_e_e_bits_addr_valid; // @[lsu.scala:262:17, :561:27] wire [39:0] stq_enq_e_bits_addr_bits = stq_enq_e_e_bits_addr_bits; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_addr_is_virtual = stq_enq_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_data_valid = stq_enq_e_e_bits_data_valid; // @[lsu.scala:262:17, :561:27] wire [63:0] stq_enq_e_bits_data_bits = stq_enq_e_e_bits_data_bits; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_committed = stq_enq_e_e_bits_committed; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_succeeded = stq_enq_e_e_bits_succeeded; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_can_execute = stq_enq_e_e_bits_can_execute; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_cleared = stq_enq_e_e_bits_cleared; // @[lsu.scala:262:17, :561:27] wire [63:0] stq_enq_e_bits_debug_wb_data = stq_enq_e_e_bits_debug_wb_data; // @[lsu.scala:262:17, :561:27] assign stq_enq_e_e_bits_uop_inst = _GEN_200[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_inst = _GEN_201[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_rvc = _GEN_202[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_pc = _GEN_203[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_0 = _GEN_204[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_1 = _GEN_205[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_2 = _GEN_206[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_3 = _GEN_207[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_0 = _GEN_208[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_1 = _GEN_209[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_2 = _GEN_210[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_3 = _GEN_211[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_4 = _GEN_212[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_5 = _GEN_213[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_6 = _GEN_214[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_7 = _GEN_215[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_8 = _GEN_216[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_9 = _GEN_217[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_issued = _GEN_218[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_issued_partial_agen = _GEN_219[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_issued_partial_dgen = _GEN_220[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p1_speculative_child = _GEN_221[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p2_speculative_child = _GEN_222[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p1_bypass_hint = _GEN_223[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p2_bypass_hint = _GEN_224[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p3_bypass_hint = _GEN_225[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_dis_col_sel = _GEN_226[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_br_mask = _GEN_227[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_br_tag = _GEN_228[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_br_type = _GEN_229[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_sfb = _GEN_230[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_fence = _GEN_231[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_fencei = _GEN_232[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_sfence = _GEN_233[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_amo = _GEN_234[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_eret = _GEN_235[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_sys_pc2epc = _GEN_236[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_rocc = _GEN_237[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_mov = _GEN_238[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ftq_idx = _GEN_239[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_edge_inst = _GEN_240[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_pc_lob = _GEN_241[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_taken = _GEN_242[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_imm_rename = _GEN_243[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_imm_sel = _GEN_244[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_pimm = _GEN_245[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_imm_packed = _GEN_246[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_op1_sel = _GEN_247[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_op2_sel = _GEN_248[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ldst = _GEN_249[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_wen = _GEN_250[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ren1 = _GEN_251[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ren2 = _GEN_252[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ren3 = _GEN_253[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_swap12 = _GEN_254[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_swap23 = _GEN_255[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_256[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_257[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_fromint = _GEN_258[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_toint = _GEN_259[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_260[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_fma = _GEN_261[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_div = _GEN_262[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_sqrt = _GEN_263[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_wflags = _GEN_264[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_vec = _GEN_265[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_rob_idx = _GEN_266[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ldq_idx = _GEN_267[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_stq_idx = _GEN_268[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_rxq_idx = _GEN_269[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_pdst = _GEN_270[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs1 = _GEN_271[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs2 = _GEN_272[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs3 = _GEN_273[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ppred = _GEN_274[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs1_busy = _GEN_275[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs2_busy = _GEN_276[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs3_busy = _GEN_277[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ppred_busy = _GEN_278[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_stale_pdst = _GEN_279[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_exception = _GEN_280[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_exc_cause = _GEN_281[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_mem_cmd = _GEN_282[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_mem_size = _GEN_283[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_mem_signed = _GEN_284[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_uses_ldq = _GEN_285[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_uses_stq = _GEN_286[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_unique = _GEN_287[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_flush_on_commit = _GEN_288[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_csr_cmd = _GEN_289[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ldst_is_rs1 = _GEN_290[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ldst = _GEN_291[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs1 = _GEN_292[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs2 = _GEN_293[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs3 = _GEN_294[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_dst_rtype = _GEN_295[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs1_rtype = _GEN_296[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs2_rtype = _GEN_297[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_frs3_en = _GEN_298[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fcn_dw = _GEN_299[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fcn_op = _GEN_300[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_val = _GEN_301[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_rm = _GEN_302[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_typ = _GEN_303[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_xcpt_pf_if = _GEN_304[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_xcpt_ae_if = _GEN_305[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_xcpt_ma_if = _GEN_306[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_bp_debug_if = _GEN_307[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_bp_xcpt_if = _GEN_308[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_fsrc = _GEN_309[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_tsrc = _GEN_310[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_addr_valid = _GEN_311[stq_execute_head]; // @[lsu.scala:262:17, :265:32, :283:29] assign stq_enq_e_e_bits_addr_bits = _GEN_312[stq_execute_head]; // @[lsu.scala:262:17, :265:32, :283:29] assign stq_enq_e_e_bits_addr_is_virtual = _GEN_313[stq_execute_head]; // @[lsu.scala:262:17, :266:32, :283:29] assign stq_enq_e_e_bits_data_valid = _GEN_314[stq_execute_head]; // @[lsu.scala:262:17, :267:32, :283:29] assign stq_enq_e_e_bits_data_bits = _GEN_315[stq_execute_head]; // @[lsu.scala:262:17, :267:32, :283:29] assign stq_enq_e_e_bits_committed = _GEN_316[stq_execute_head]; // @[lsu.scala:262:17, :268:32, :283:29] assign stq_enq_e_e_bits_succeeded = _GEN_317[stq_execute_head]; // @[lsu.scala:262:17, :269:32, :283:29] assign stq_enq_e_e_bits_can_execute = _GEN_318[stq_execute_head]; // @[lsu.scala:262:17, :270:32, :283:29] assign stq_enq_e_e_bits_cleared = _GEN_319[stq_execute_head]; // @[lsu.scala:262:17, :271:32, :283:29] assign stq_enq_e_e_bits_debug_wb_data = _GEN_320[stq_execute_head]; // @[lsu.scala:262:17, :272:32, :283:29] wire _T_1139 = will_fire_store_commit_fast_0 | will_fire_store_commit_slow_0; // @[lsu.scala:478:41, :479:41, :565:78] wire _stq_execute_queue_io_deq_ready_T; // @[lsu.scala:565:78] assign _stq_execute_queue_io_deq_ready_T = _T_1139; // @[lsu.scala:565:78] wire _fired_store_commit_T; // @[lsu.scala:1048:83] assign _fired_store_commit_T = _T_1139; // @[lsu.scala:565:78, :1048:83] wire _can_enq_store_execute_T = stq_enq_e_valid & stq_enq_e_bits_addr_valid; // @[lsu.scala:561:27, :568:21] wire _can_enq_store_execute_T_1 = _can_enq_store_execute_T & stq_enq_e_bits_data_valid; // @[lsu.scala:561:27, :568:21, :569:31] wire _can_enq_store_execute_T_2 = ~stq_enq_e_bits_addr_is_virtual; // @[lsu.scala:561:27, :571:4] wire _can_enq_store_execute_T_3 = _can_enq_store_execute_T_1 & _can_enq_store_execute_T_2; // @[lsu.scala:569:31, :570:31, :571:4] wire _can_enq_store_execute_T_4 = ~stq_enq_e_bits_uop_exception; // @[lsu.scala:561:27, :572:4] wire _can_enq_store_execute_T_5 = _can_enq_store_execute_T_3 & _can_enq_store_execute_T_4; // @[lsu.scala:570:31, :571:36, :572:4] wire _can_enq_store_execute_T_6 = ~stq_enq_e_bits_uop_is_fence; // @[lsu.scala:561:27, :573:4] wire _can_enq_store_execute_T_7 = _can_enq_store_execute_T_5 & _can_enq_store_execute_T_6; // @[lsu.scala:571:36, :572:34, :573:4] wire _can_enq_store_execute_T_8 = stq_enq_e_bits_committed | stq_enq_e_bits_uop_is_amo; // @[lsu.scala:561:27, :574:30] wire can_enq_store_execute = _can_enq_store_execute_T_7 & _can_enq_store_execute_T_8; // @[lsu.scala:572:34, :573:33, :574:30] wire [4:0] _GEN_350 = {1'h0, stq_execute_head} + 5'h1; // @[util.scala:211:14] wire [4:0] _stq_execute_head_T; // @[util.scala:211:14] assign _stq_execute_head_T = _GEN_350; // @[util.scala:211:14] wire [4:0] _stq_execute_head_T_3; // @[util.scala:211:14] assign _stq_execute_head_T_3 = _GEN_350; // @[util.scala:211:14] wire [3:0] _stq_execute_head_T_1 = _stq_execute_head_T[3:0]; // @[util.scala:211:14] wire [3:0] _stq_execute_head_T_2 = _stq_execute_head_T_1; // @[util.scala:211:{14,20}] wire _can_fire_load_agen_exec_T = io_core_agen_0_valid_0 & io_core_agen_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7, :586:61] wire can_fire_load_agen_exec_0 = _can_fire_load_agen_exec_T; // @[lsu.scala:321:49, :586:61] wire _can_fire_store_agen_T = io_core_agen_0_valid_0 & io_core_agen_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7, :590:61] wire can_fire_store_agen_0 = _can_fire_store_agen_T; // @[lsu.scala:321:49, :590:61] wire _will_fire_sfence_0_will_fire_T_3 = can_fire_sfence_0; // @[lsu.scala:321:49, :656:32] wire can_fire_release_0 = _can_fire_release_T; // @[lsu.scala:321:49, :598:66] wire _will_fire_release_0_will_fire_T_3 = can_fire_release_0; // @[lsu.scala:321:49, :656:32] wire _can_fire_load_retry_T = _retry_queue_io_deq_valid & _retry_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:533:27, :603:79] reg can_fire_load_retry_REG; // @[lsu.scala:605:41] wire _can_fire_load_retry_T_1 = ~can_fire_load_retry_REG; // @[lsu.scala:605:{33,41}] wire _can_fire_load_retry_T_2 = _can_fire_load_retry_T & _can_fire_load_retry_T_1; // @[lsu.scala:603:79, :604:79, :605:33] wire _can_fire_load_retry_T_3 = _can_fire_load_retry_T_2; // @[lsu.scala:604:79, :605:79] wire can_fire_load_retry_0 = _can_fire_load_retry_T_3; // @[lsu.scala:321:49, :605:79] wire _can_fire_store_retry_T = _retry_queue_io_deq_valid & _retry_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:533:27, :610:79] wire _can_fire_store_retry_T_1 = _can_fire_store_retry_T; // @[lsu.scala:610:79, :611:79] wire can_fire_store_retry_0 = _can_fire_store_retry_T_1; // @[lsu.scala:321:49, :611:79] wire _can_fire_store_commit_slow_T = ~mem_xcpt_valid; // @[lsu.scala:457:29, :617:38] wire _can_fire_store_commit_slow_T_1 = _stq_execute_queue_io_deq_valid & _can_fire_store_commit_slow_T; // @[lsu.scala:558:11, :616:84, :617:38] wire _can_fire_store_commit_slow_T_2 = _can_fire_store_commit_slow_T_1; // @[lsu.scala:616:84, :617:84] wire can_fire_store_commit_slow_0 = _can_fire_store_commit_slow_T_2; // @[lsu.scala:321:49, :617:84] wire _will_fire_store_commit_slow_0_will_fire_T_3 = can_fire_store_commit_slow_0; // @[lsu.scala:321:49, :656:32] wire _can_fire_store_commit_fast_T = can_fire_store_commit_slow_0 & stq_almost_full; // @[lsu.scala:321:49, :494:32, :620:80] wire can_fire_store_commit_fast_0 = _can_fire_store_commit_fast_T; // @[lsu.scala:321:49, :620:80] wire _will_fire_store_commit_fast_0_will_fire_T_3 = can_fire_store_commit_fast_0; // @[lsu.scala:321:49, :656:32] wire block_load_wakeup; // @[lsu.scala:623:35] wire _can_fire_load_wakeup_T = ldq_wakeup_e_valid & ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:510:32, :625:88] wire _can_fire_load_wakeup_T_1 = ~ldq_wakeup_e_bits_succeeded; // @[lsu.scala:510:32, :627:31] wire _can_fire_load_wakeup_T_2 = _can_fire_load_wakeup_T & _can_fire_load_wakeup_T_1; // @[lsu.scala:625:88, :626:88, :627:31] wire _can_fire_load_wakeup_T_3 = ~ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:510:32, :628:31] wire _can_fire_load_wakeup_T_4 = _can_fire_load_wakeup_T_2 & _can_fire_load_wakeup_T_3; // @[lsu.scala:626:88, :627:88, :628:31] wire _can_fire_load_wakeup_T_5 = ~ldq_wakeup_e_bits_executed; // @[lsu.scala:510:32, :629:31] wire _can_fire_load_wakeup_T_6 = _can_fire_load_wakeup_T_4 & _can_fire_load_wakeup_T_5; // @[lsu.scala:627:88, :628:88, :629:31] wire _can_fire_load_wakeup_T_7 = ~ldq_wakeup_e_bits_order_fail; // @[lsu.scala:510:32, :630:31] wire _can_fire_load_wakeup_T_8 = _can_fire_load_wakeup_T_6 & _can_fire_load_wakeup_T_7; // @[lsu.scala:628:88, :629:88, :630:31] wire [3:0] _can_fire_load_wakeup_T_10 = _can_fire_load_wakeup_T_9; wire [15:0] _GEN_351 = {{p1_block_load_mask_15}, {p1_block_load_mask_14}, {p1_block_load_mask_13}, {p1_block_load_mask_12}, {p1_block_load_mask_11}, {p1_block_load_mask_10}, {p1_block_load_mask_9}, {p1_block_load_mask_8}, {p1_block_load_mask_7}, {p1_block_load_mask_6}, {p1_block_load_mask_5}, {p1_block_load_mask_4}, {p1_block_load_mask_3}, {p1_block_load_mask_2}, {p1_block_load_mask_1}, {p1_block_load_mask_0}}; // @[lsu.scala:489:35, :631:31] wire _can_fire_load_wakeup_T_11 = ~_GEN_351[_can_fire_load_wakeup_T_10]; // @[lsu.scala:631:31] wire _can_fire_load_wakeup_T_12 = _can_fire_load_wakeup_T_8 & _can_fire_load_wakeup_T_11; // @[lsu.scala:629:88, :630:88, :631:31] wire [3:0] _can_fire_load_wakeup_T_14 = _can_fire_load_wakeup_T_13; wire [15:0] _GEN_352 = {{p2_block_load_mask_15}, {p2_block_load_mask_14}, {p2_block_load_mask_13}, {p2_block_load_mask_12}, {p2_block_load_mask_11}, {p2_block_load_mask_10}, {p2_block_load_mask_9}, {p2_block_load_mask_8}, {p2_block_load_mask_7}, {p2_block_load_mask_6}, {p2_block_load_mask_5}, {p2_block_load_mask_4}, {p2_block_load_mask_3}, {p2_block_load_mask_2}, {p2_block_load_mask_1}, {p2_block_load_mask_0}}; // @[lsu.scala:490:35, :632:31] wire _can_fire_load_wakeup_T_15 = ~_GEN_352[_can_fire_load_wakeup_T_14]; // @[lsu.scala:632:31] wire _can_fire_load_wakeup_T_16 = _can_fire_load_wakeup_T_12 & _can_fire_load_wakeup_T_15; // @[lsu.scala:630:88, :631:88, :632:31] reg can_fire_load_wakeup_REG; // @[lsu.scala:633:39] wire _can_fire_load_wakeup_T_17 = ~can_fire_load_wakeup_REG; // @[lsu.scala:633:{31,39}] wire _can_fire_load_wakeup_T_18 = _can_fire_load_wakeup_T_16 & _can_fire_load_wakeup_T_17; // @[lsu.scala:631:88, :632:88, :633:31] wire _can_fire_load_wakeup_T_19 = ~block_load_wakeup; // @[lsu.scala:623:35, :634:31] wire _can_fire_load_wakeup_T_20 = _can_fire_load_wakeup_T_18 & _can_fire_load_wakeup_T_19; // @[lsu.scala:632:88, :633:88, :634:31] wire _can_fire_load_wakeup_T_21 = _can_fire_load_wakeup_T_20; // @[lsu.scala:633:88, :634:88] wire _can_fire_load_wakeup_T_22 = ~ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:510:32, :636:32] wire _can_fire_load_wakeup_T_23 = ldq_head == ldq_wakeup_idx; // @[lsu.scala:278:29, :506:31, :637:84] wire _can_fire_load_wakeup_T_24 = io_core_commit_load_at_rob_head_0 & _can_fire_load_wakeup_T_23; // @[lsu.scala:211:7, :636:107, :637:84] wire _can_fire_load_wakeup_T_25 = ldq_wakeup_e_bits_st_dep_mask == 16'h0; // @[lsu.scala:510:32, :638:112] wire _can_fire_load_wakeup_T_26 = _can_fire_load_wakeup_T_24 & _can_fire_load_wakeup_T_25; // @[lsu.scala:636:107, :637:103, :638:112] wire _can_fire_load_wakeup_T_27 = _can_fire_load_wakeup_T_22 | _can_fire_load_wakeup_T_26; // @[lsu.scala:636:{32,71}, :637:103] wire _can_fire_load_wakeup_T_28 = _can_fire_load_wakeup_T_21 & _can_fire_load_wakeup_T_27; // @[lsu.scala:634:88, :635:88, :636:71] wire can_fire_load_wakeup_0 = _can_fire_load_wakeup_T_28; // @[lsu.scala:321:49, :635:88] wire _will_fire_load_wakeup_0_will_fire_T_3 = can_fire_load_wakeup_0; // @[lsu.scala:321:49, :656:32] wire can_fire_hella_incoming_0; // @[lsu.scala:641:42] wire can_fire_hella_wakeup_0; // @[lsu.scala:644:42] wire _will_fire_hella_wakeup_0_will_fire_T_3 = can_fire_hella_wakeup_0; // @[lsu.scala:644:42, :656:32] wire _exe_tlb_valid_0_T; // @[lsu.scala:696:25] wire exe_tlb_valid_0; // @[lsu.scala:649:27] wire _will_fire_sfence_0_will_fire_T_7 = _will_fire_sfence_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] assign will_fire_sfence_0_will_fire = _will_fire_sfence_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] assign will_fire_sfence_0 = will_fire_sfence_0_will_fire; // @[lsu.scala:472:41, :657:65] wire _will_fire_sfence_0_T = will_fire_sfence_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_sfence_0_T_1 = ~_will_fire_sfence_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_sfence_0_T_2 = _will_fire_sfence_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_store_commit_fast_0_T_2 = _will_fire_sfence_0_T_2; // @[lsu.scala:659:31] wire _will_fire_store_commit_fast_0_will_fire_T = ~_will_fire_sfence_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_commit_fast_0_will_fire_T_7 = _will_fire_store_commit_fast_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] assign will_fire_store_commit_fast_0_will_fire = _will_fire_store_commit_fast_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] assign will_fire_store_commit_fast_0 = will_fire_store_commit_fast_0_will_fire; // @[lsu.scala:478:41, :657:65] wire _will_fire_store_commit_fast_0_T_6 = will_fire_store_commit_fast_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_store_commit_fast_0_T_7 = ~_will_fire_store_commit_fast_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_store_commit_fast_0_T_8 = _will_fire_store_commit_fast_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_load_agen_exec_0_will_fire_T = ~_will_fire_store_commit_fast_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_agen_exec_0_will_fire_T_1 = _will_fire_load_agen_exec_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_load_agen_exec_0_will_fire_T_2 = ~_will_fire_load_agen_exec_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_load_agen_exec_0_will_fire_T_3 = can_fire_load_agen_exec_0 & _will_fire_load_agen_exec_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_load_agen_exec_0_will_fire_T_7 = _will_fire_load_agen_exec_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_load_agen_exec_0_will_fire_T_8 = ~_will_fire_store_commit_fast_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_load_agen_exec_0_will_fire_T_9 = _will_fire_load_agen_exec_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_load_agen_exec_0_will_fire_T_10 = ~_will_fire_load_agen_exec_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_load_agen_exec_0_will_fire = _will_fire_load_agen_exec_0_will_fire_T_7 & _will_fire_load_agen_exec_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_load_agen_exec_0 = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:469:39, :657:65] wire _will_fire_load_agen_exec_0_T = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_load_agen_exec_0_T_3 = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_agen_exec_0_T_6 = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_load_agen_exec_0_T_1 = ~_will_fire_load_agen_exec_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_load_agen_exec_0_T_2 = _will_fire_store_commit_fast_0_T_2 & _will_fire_load_agen_exec_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_load_agen_exec_0_T_4 = ~_will_fire_load_agen_exec_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_agen_exec_0_T_5 = _will_fire_load_agen_exec_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_load_agen_exec_0_T_7 = ~_will_fire_load_agen_exec_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_load_agen_exec_0_T_8 = _will_fire_store_commit_fast_0_T_8 & _will_fire_load_agen_exec_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_load_agen_0_T_8 = _will_fire_load_agen_exec_0_T_8; // @[lsu.scala:661:31] wire _will_fire_load_agen_0_will_fire_T = ~_will_fire_load_agen_exec_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_agen_0_will_fire_T_1 = _will_fire_load_agen_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_load_agen_0_will_fire_T_2 = ~_will_fire_load_agen_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_load_agen_0_will_fire_T_3 = can_fire_load_agen_exec_0 & _will_fire_load_agen_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_load_agen_0_will_fire_T_4 = ~_will_fire_load_agen_exec_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_load_agen_0_will_fire_T_5 = _will_fire_load_agen_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_load_agen_0_will_fire_T_6 = ~_will_fire_load_agen_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_load_agen_0_will_fire_T_7 = _will_fire_load_agen_0_will_fire_T_3 & _will_fire_load_agen_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_load_agen_0_will_fire = _will_fire_load_agen_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_load_agen_0_will_fire_T_8 = ~_will_fire_load_agen_exec_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_load_agen_0 = will_fire_load_agen_0_will_fire; // @[lsu.scala:470:41, :657:65] wire _will_fire_load_agen_0_T = will_fire_load_agen_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_load_agen_0_T_3 = will_fire_load_agen_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_agen_0_T_1 = ~_will_fire_load_agen_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_load_agen_0_T_2 = _will_fire_load_agen_exec_0_T_2 & _will_fire_load_agen_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_load_agen_0_T_4 = ~_will_fire_load_agen_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_agen_0_T_5 = _will_fire_load_agen_exec_0_T_5 & _will_fire_load_agen_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_store_agen_0_T_8 = _will_fire_load_agen_0_T_8; // @[lsu.scala:661:31] wire _will_fire_store_agen_0_will_fire_T = ~_will_fire_load_agen_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_agen_0_will_fire_T_1 = _will_fire_store_agen_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_store_agen_0_will_fire_T_2 = ~_will_fire_store_agen_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_store_agen_0_will_fire_T_3 = can_fire_store_agen_0 & _will_fire_store_agen_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_store_agen_0_will_fire_T_4 = ~_will_fire_load_agen_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_store_agen_0_will_fire_T_5 = _will_fire_store_agen_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_store_agen_0_will_fire_T_6 = ~_will_fire_store_agen_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_store_agen_0_will_fire_T_7 = _will_fire_store_agen_0_will_fire_T_3 & _will_fire_store_agen_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_store_agen_0_will_fire = _will_fire_store_agen_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_store_agen_0_will_fire_T_8 = ~_will_fire_load_agen_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_store_agen_0 = will_fire_store_agen_0_will_fire; // @[lsu.scala:471:41, :657:65] wire _will_fire_store_agen_0_T = will_fire_store_agen_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_store_agen_0_T_3 = will_fire_store_agen_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_store_agen_0_T_1 = ~_will_fire_store_agen_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_store_agen_0_T_2 = _will_fire_load_agen_0_T_2 & _will_fire_store_agen_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_release_0_T_2 = _will_fire_store_agen_0_T_2; // @[lsu.scala:659:31] wire _will_fire_store_agen_0_T_4 = ~_will_fire_store_agen_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_store_agen_0_T_5 = _will_fire_load_agen_0_T_5 & _will_fire_store_agen_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_release_0_T_8 = _will_fire_store_agen_0_T_8; // @[lsu.scala:661:31] wire _will_fire_release_0_will_fire_T = ~_will_fire_store_agen_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_release_0_will_fire_T_4 = ~_will_fire_store_agen_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_release_0_will_fire_T_5 = _will_fire_release_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_release_0_will_fire_T_6 = ~_will_fire_release_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_release_0_will_fire_T_7 = _will_fire_release_0_will_fire_T_3 & _will_fire_release_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_release_0_will_fire = _will_fire_release_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_release_0_will_fire_T_8 = ~_will_fire_store_agen_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_release_0 = will_fire_release_0_will_fire; // @[lsu.scala:475:41, :657:65] wire _will_fire_release_0_T_3 = will_fire_release_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_release_0_T_4 = ~_will_fire_release_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_release_0_T_5 = _will_fire_store_agen_0_T_5 & _will_fire_release_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_hella_incoming_0_T_5 = _will_fire_release_0_T_5; // @[lsu.scala:660:31] wire _will_fire_hella_incoming_0_will_fire_T = ~_will_fire_release_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_hella_incoming_0_will_fire_T_1 = _will_fire_hella_incoming_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_hella_incoming_0_will_fire_T_2 = ~_will_fire_hella_incoming_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_hella_incoming_0_will_fire_T_3 = can_fire_hella_incoming_0 & _will_fire_hella_incoming_0_will_fire_T_2; // @[lsu.scala:641:42, :656:{32,35}] wire _will_fire_hella_incoming_0_will_fire_T_7 = _will_fire_hella_incoming_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_hella_incoming_0_will_fire_T_4 = ~_will_fire_release_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_hella_incoming_0_will_fire_T_8 = ~_will_fire_release_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_hella_incoming_0_will_fire_T_9 = _will_fire_hella_incoming_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_hella_incoming_0_will_fire_T_10 = ~_will_fire_hella_incoming_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_hella_incoming_0_will_fire = _will_fire_hella_incoming_0_will_fire_T_7 & _will_fire_hella_incoming_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_hella_incoming_0 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:473:41, :657:65] wire _will_fire_hella_incoming_0_T = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_hella_incoming_0_T_6 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_hella_incoming_0_T_1 = ~_will_fire_hella_incoming_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_hella_incoming_0_T_2 = _will_fire_release_0_T_2 & _will_fire_hella_incoming_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_hella_wakeup_0_T_2 = _will_fire_hella_incoming_0_T_2; // @[lsu.scala:659:31] wire _will_fire_hella_wakeup_0_T_5 = _will_fire_hella_incoming_0_T_5; // @[lsu.scala:660:31] wire _will_fire_hella_incoming_0_T_7 = ~_will_fire_hella_incoming_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_hella_incoming_0_T_8 = _will_fire_release_0_T_8 & _will_fire_hella_incoming_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_hella_wakeup_0_will_fire_T = ~_will_fire_hella_incoming_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_hella_wakeup_0_will_fire_T_7 = _will_fire_hella_wakeup_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_hella_wakeup_0_will_fire_T_4 = ~_will_fire_hella_incoming_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_hella_wakeup_0_will_fire_T_8 = ~_will_fire_hella_incoming_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_hella_wakeup_0_will_fire_T_9 = _will_fire_hella_wakeup_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_hella_wakeup_0_will_fire_T_10 = ~_will_fire_hella_wakeup_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_hella_wakeup_0_will_fire = _will_fire_hella_wakeup_0_will_fire_T_7 & _will_fire_hella_wakeup_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_hella_wakeup_0 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:474:41, :657:65] wire _will_fire_hella_wakeup_0_T_6 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_hella_wakeup_0_T_7 = ~_will_fire_hella_wakeup_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_hella_wakeup_0_T_8 = _will_fire_hella_incoming_0_T_8 & _will_fire_hella_wakeup_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_store_retry_0_T_8 = _will_fire_hella_wakeup_0_T_8; // @[lsu.scala:661:31] wire _will_fire_store_retry_0_will_fire_T = ~_will_fire_hella_wakeup_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_retry_0_will_fire_T_1 = _will_fire_store_retry_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_store_retry_0_will_fire_T_2 = ~_will_fire_store_retry_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_store_retry_0_will_fire_T_3 = can_fire_store_retry_0 & _will_fire_store_retry_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_store_retry_0_will_fire_T_4 = ~_will_fire_hella_wakeup_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_store_retry_0_will_fire_T_5 = _will_fire_store_retry_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_store_retry_0_will_fire_T_6 = ~_will_fire_store_retry_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_store_retry_0_will_fire_T_7 = _will_fire_store_retry_0_will_fire_T_3 & _will_fire_store_retry_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_store_retry_0_will_fire = _will_fire_store_retry_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_store_retry_0_will_fire_T_8 = ~_will_fire_hella_wakeup_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_store_retry_0 = will_fire_store_retry_0_will_fire; // @[lsu.scala:477:41, :657:65] wire _will_fire_store_retry_0_T = will_fire_store_retry_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_store_retry_0_T_3 = will_fire_store_retry_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_store_retry_0_T_1 = ~_will_fire_store_retry_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_store_retry_0_T_2 = _will_fire_hella_wakeup_0_T_2 & _will_fire_store_retry_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_store_retry_0_T_4 = ~_will_fire_store_retry_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_store_retry_0_T_5 = _will_fire_hella_wakeup_0_T_5 & _will_fire_store_retry_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_load_retry_0_will_fire_T = ~_will_fire_store_retry_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_retry_0_will_fire_T_1 = _will_fire_load_retry_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_load_retry_0_will_fire_T_2 = ~_will_fire_load_retry_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_load_retry_0_will_fire_T_3 = can_fire_load_retry_0 & _will_fire_load_retry_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_load_retry_0_will_fire_T_4 = ~_will_fire_store_retry_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_load_retry_0_will_fire_T_5 = _will_fire_load_retry_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_load_retry_0_will_fire_T_6 = ~_will_fire_load_retry_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_load_retry_0_will_fire_T_7 = _will_fire_load_retry_0_will_fire_T_3 & _will_fire_load_retry_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] wire _will_fire_load_retry_0_will_fire_T_8 = ~_will_fire_store_retry_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_load_retry_0_will_fire_T_9 = _will_fire_load_retry_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_load_retry_0_will_fire_T_10 = ~_will_fire_load_retry_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_load_retry_0_will_fire = _will_fire_load_retry_0_will_fire_T_7 & _will_fire_load_retry_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_load_retry_0 = will_fire_load_retry_0_will_fire; // @[lsu.scala:476:41, :657:65] wire _will_fire_load_retry_0_T = will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_load_retry_0_T_3 = will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_retry_0_T_6 = will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_load_retry_0_T_1 = ~_will_fire_load_retry_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_load_retry_0_T_2 = _will_fire_store_retry_0_T_2 & _will_fire_load_retry_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_load_wakeup_0_T_2 = _will_fire_load_retry_0_T_2; // @[lsu.scala:659:31] wire _will_fire_load_retry_0_T_4 = ~_will_fire_load_retry_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_retry_0_T_5 = _will_fire_store_retry_0_T_5 & _will_fire_load_retry_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_load_retry_0_T_7 = ~_will_fire_load_retry_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_load_retry_0_T_8 = _will_fire_store_retry_0_T_8 & _will_fire_load_retry_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_load_wakeup_0_will_fire_T = ~_will_fire_load_retry_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_wakeup_0_will_fire_T_4 = ~_will_fire_load_retry_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_load_wakeup_0_will_fire_T_5 = _will_fire_load_wakeup_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_load_wakeup_0_will_fire_T_6 = ~_will_fire_load_wakeup_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_load_wakeup_0_will_fire_T_7 = _will_fire_load_wakeup_0_will_fire_T_3 & _will_fire_load_wakeup_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] wire _will_fire_load_wakeup_0_will_fire_T_8 = ~_will_fire_load_retry_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_load_wakeup_0_will_fire_T_9 = _will_fire_load_wakeup_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_load_wakeup_0_will_fire_T_10 = ~_will_fire_load_wakeup_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_load_wakeup_0_will_fire = _will_fire_load_wakeup_0_will_fire_T_7 & _will_fire_load_wakeup_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_load_wakeup_0 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:480:41, :657:65] wire _will_fire_load_wakeup_0_T_3 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_wakeup_0_T_6 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_store_commit_slow_0_T_2 = _will_fire_load_wakeup_0_T_2; // @[lsu.scala:659:31] wire _will_fire_load_wakeup_0_T_4 = ~_will_fire_load_wakeup_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_wakeup_0_T_5 = _will_fire_load_retry_0_T_5 & _will_fire_load_wakeup_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_store_commit_slow_0_T_5 = _will_fire_load_wakeup_0_T_5; // @[lsu.scala:660:31] wire _will_fire_load_wakeup_0_T_7 = ~_will_fire_load_wakeup_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_load_wakeup_0_T_8 = _will_fire_load_retry_0_T_8 & _will_fire_load_wakeup_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_store_commit_slow_0_will_fire_T = ~_will_fire_load_wakeup_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_commit_slow_0_will_fire_T_7 = _will_fire_store_commit_slow_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_store_commit_slow_0_will_fire_T_4 = ~_will_fire_load_wakeup_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_store_commit_slow_0_will_fire_T_8 = ~_will_fire_load_wakeup_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_store_commit_slow_0_will_fire_T_9 = _will_fire_store_commit_slow_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_store_commit_slow_0_will_fire_T_10 = ~_will_fire_store_commit_slow_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_store_commit_slow_0_will_fire = _will_fire_store_commit_slow_0_will_fire_T_7 & _will_fire_store_commit_slow_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_store_commit_slow_0 = will_fire_store_commit_slow_0_will_fire; // @[lsu.scala:479:41, :657:65] wire _will_fire_store_commit_slow_0_T_6 = will_fire_store_commit_slow_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_store_commit_slow_0_T_7 = ~_will_fire_store_commit_slow_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_store_commit_slow_0_T_8 = _will_fire_load_wakeup_0_T_8 & _will_fire_store_commit_slow_0_T_7; // @[lsu.scala:661:{31,34}] wire _T_182 = will_fire_load_agen_exec_0 | will_fire_load_agen_0; // @[lsu.scala:469:39, :470:41, :687:61] wire _exe_tlb_uop_T; // @[lsu.scala:717:53] assign _exe_tlb_uop_T = _T_182; // @[lsu.scala:687:61, :717:53] wire _exe_tlb_vaddr_T; // @[lsu.scala:726:53] assign _exe_tlb_vaddr_T = _T_182; // @[lsu.scala:687:61, :726:53] wire _exe_size_T; // @[lsu.scala:738:52] assign _exe_size_T = _T_182; // @[lsu.scala:687:61, :738:52] wire _exe_cmd_T; // @[lsu.scala:746:52] assign _exe_cmd_T = _T_182; // @[lsu.scala:687:61, :746:52] wire _ldq_idx_T; // @[lsu.scala:969:48] assign _ldq_idx_T = _T_182; // @[lsu.scala:687:61, :969:48] wire _GEN_353 = ldq_wakeup_idx == 4'h0; // @[lsu.scala:506:31, :690:49] wire _GEN_354 = ldq_wakeup_idx == 4'h1; // @[lsu.scala:506:31, :690:49] wire _GEN_355 = ldq_wakeup_idx == 4'h2; // @[lsu.scala:506:31, :690:49] wire _GEN_356 = ldq_wakeup_idx == 4'h3; // @[lsu.scala:506:31, :690:49] wire _GEN_357 = ldq_wakeup_idx == 4'h4; // @[lsu.scala:506:31, :690:49] wire _GEN_358 = ldq_wakeup_idx == 4'h5; // @[lsu.scala:506:31, :690:49] wire _GEN_359 = ldq_wakeup_idx == 4'h6; // @[lsu.scala:506:31, :690:49] wire _GEN_360 = ldq_wakeup_idx == 4'h7; // @[lsu.scala:506:31, :690:49] wire _GEN_361 = ldq_wakeup_idx == 4'h8; // @[lsu.scala:506:31, :690:49] wire _GEN_362 = ldq_wakeup_idx == 4'h9; // @[lsu.scala:506:31, :690:49] wire _GEN_363 = ldq_wakeup_idx == 4'hA; // @[lsu.scala:506:31, :690:49] wire _GEN_364 = ldq_wakeup_idx == 4'hB; // @[lsu.scala:506:31, :690:49] wire _GEN_365 = ldq_wakeup_idx == 4'hC; // @[lsu.scala:506:31, :690:49] wire _GEN_366 = ldq_wakeup_idx == 4'hD; // @[lsu.scala:506:31, :690:49] wire _GEN_367 = ldq_wakeup_idx == 4'hE; // @[lsu.scala:506:31, :690:49] wire _GEN_368 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h0; // @[lsu.scala:533:27, :694:49] assign block_load_mask_0 = will_fire_load_wakeup_0 ? _GEN_353 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h0 : will_fire_load_retry_0 & _GEN_368; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_369 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h1; // @[lsu.scala:533:27, :694:49] assign block_load_mask_1 = will_fire_load_wakeup_0 ? _GEN_354 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h1 : will_fire_load_retry_0 & _GEN_369; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_370 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h2; // @[lsu.scala:533:27, :694:49] assign block_load_mask_2 = will_fire_load_wakeup_0 ? _GEN_355 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h2 : will_fire_load_retry_0 & _GEN_370; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_371 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h3; // @[lsu.scala:533:27, :694:49] assign block_load_mask_3 = will_fire_load_wakeup_0 ? _GEN_356 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h3 : will_fire_load_retry_0 & _GEN_371; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_372 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h4; // @[lsu.scala:533:27, :694:49] assign block_load_mask_4 = will_fire_load_wakeup_0 ? _GEN_357 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h4 : will_fire_load_retry_0 & _GEN_372; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_373 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h5; // @[lsu.scala:533:27, :694:49] assign block_load_mask_5 = will_fire_load_wakeup_0 ? _GEN_358 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h5 : will_fire_load_retry_0 & _GEN_373; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_374 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h6; // @[lsu.scala:533:27, :694:49] assign block_load_mask_6 = will_fire_load_wakeup_0 ? _GEN_359 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h6 : will_fire_load_retry_0 & _GEN_374; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_375 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h7; // @[lsu.scala:533:27, :694:49] assign block_load_mask_7 = will_fire_load_wakeup_0 ? _GEN_360 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h7 : will_fire_load_retry_0 & _GEN_375; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_376 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h8; // @[lsu.scala:533:27, :694:49] assign block_load_mask_8 = will_fire_load_wakeup_0 ? _GEN_361 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h8 : will_fire_load_retry_0 & _GEN_376; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_377 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'h9; // @[lsu.scala:533:27, :694:49] assign block_load_mask_9 = will_fire_load_wakeup_0 ? _GEN_362 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'h9 : will_fire_load_retry_0 & _GEN_377; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_378 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'hA; // @[lsu.scala:533:27, :694:49] assign block_load_mask_10 = will_fire_load_wakeup_0 ? _GEN_363 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'hA : will_fire_load_retry_0 & _GEN_378; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_379 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'hB; // @[lsu.scala:533:27, :694:49] assign block_load_mask_11 = will_fire_load_wakeup_0 ? _GEN_364 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'hB : will_fire_load_retry_0 & _GEN_379; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_380 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'hC; // @[lsu.scala:533:27, :694:49] assign block_load_mask_12 = will_fire_load_wakeup_0 ? _GEN_365 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'hC : will_fire_load_retry_0 & _GEN_380; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_381 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'hD; // @[lsu.scala:533:27, :694:49] assign block_load_mask_13 = will_fire_load_wakeup_0 ? _GEN_366 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'hD : will_fire_load_retry_0 & _GEN_381; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_382 = _retry_queue_io_deq_bits_uop_ldq_idx == 4'hE; // @[lsu.scala:533:27, :694:49] assign block_load_mask_14 = will_fire_load_wakeup_0 ? _GEN_367 : _T_182 ? io_core_agen_0_bits_uop_ldq_idx_0 == 4'hE : will_fire_load_retry_0 & _GEN_382; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] assign block_load_mask_15 = will_fire_load_wakeup_0 ? (&ldq_wakeup_idx) : _T_182 ? (&io_core_agen_0_bits_uop_ldq_idx_0) : will_fire_load_retry_0 & (&_retry_queue_io_deq_bits_uop_ldq_idx); // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :506:31, :533:27, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] assign _exe_tlb_valid_0_T = ~_will_fire_store_commit_slow_0_T_2; // @[lsu.scala:659:31, :696:25] assign exe_tlb_valid_0 = _exe_tlb_valid_0_T; // @[lsu.scala:649:27, :696:25] wire [31:0] _exe_tlb_uop_T_3_inst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_inst : 32'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [31:0] _exe_tlb_uop_T_3_debug_inst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_inst : 32'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_rvc = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_rvc; // @[lsu.scala:533:27, :720:{24,53}] wire [39:0] _exe_tlb_uop_T_3_debug_pc = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_pc : 40'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_0 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_1; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_2 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_2; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_3 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_3; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_0 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_1; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_2 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_2; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_3 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_3; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_4 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_4; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_5 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_5; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_6 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_6; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_7 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_7; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_8 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_8; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_9 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_9; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_issued = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_issued; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_issued_partial_agen = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_issued_partial_agen; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_issued_partial_dgen = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_iw_p1_speculative_child = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_iw_p1_speculative_child : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_iw_p2_speculative_child = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_iw_p2_speculative_child : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_p1_bypass_hint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_p2_bypass_hint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_p3_bypass_hint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_dis_col_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_dis_col_sel : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [11:0] _exe_tlb_uop_T_3_br_mask = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_br_mask : 12'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [3:0] _exe_tlb_uop_T_3_br_tag = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_br_tag : 4'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [3:0] _exe_tlb_uop_T_3_br_type = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_br_type : 4'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_sfb = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_sfb; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_fence = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_fence; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_fencei = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_fencei; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_sfence = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_sfence; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_amo = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_amo; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_eret = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_eret; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_sys_pc2epc = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_sys_pc2epc; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_rocc = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_rocc; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_mov = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_mov; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_ftq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_edge_inst = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_edge_inst; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_pc_lob = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_pc_lob : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_taken = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_taken; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_imm_rename = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_imm_rename; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_imm_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_imm_sel : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_pimm = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_pimm : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [19:0] _exe_tlb_uop_T_3_imm_packed = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_imm_packed : 20'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_op1_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_op1_sel : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_op2_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_op2_sel : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ldst = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ldst; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_wen = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_wen; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ren1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ren1; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ren2 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ren2; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ren3 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ren3; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_swap12 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_swap12; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_swap23 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_swap23; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_fp_ctrl_typeTagIn = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_fp_ctrl_typeTagOut = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_fromint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_fromint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_toint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_toint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_fastpipe = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_fma = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_fma; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_div = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_div; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_sqrt = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_wflags = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_wflags; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_vec = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_vec; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_rob_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_rob_idx : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [3:0] _exe_tlb_uop_T_3_ldq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ldq_idx : 4'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [3:0] _exe_tlb_uop_T_3_stq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_stq_idx : 4'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_rxq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_pdst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_pdst : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_prs1 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_prs1 : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_prs2 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_prs2 : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_prs3 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_prs3 : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_ppred = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ppred : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_prs1_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_prs1_busy; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_prs2_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_prs2_busy; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_prs3_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_prs3_busy; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_ppred_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_ppred_busy; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_stale_pdst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_exception = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_exception; // @[lsu.scala:533:27, :720:{24,53}] wire [63:0] _exe_tlb_uop_T_3_exc_cause = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_exc_cause : 64'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_mem_cmd = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_mem_size = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_mem_size : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_mem_signed = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_mem_signed; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_uses_ldq = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_uses_stq = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_unique = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_unique; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_flush_on_commit = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_flush_on_commit; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_csr_cmd = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_ldst_is_rs1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_ldst_is_rs1; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_ldst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ldst : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_lrs1 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs1 : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_lrs2 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs2 : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_lrs3 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs3 : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_dst_rtype = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_lrs1_rtype = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_lrs2_rtype = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_frs3_en = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_frs3_en; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fcn_dw = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fcn_dw; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_fcn_op = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fcn_op : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_val = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_val; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_fp_rm = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_rm : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_fp_typ = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_typ : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_xcpt_pf_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_xcpt_pf_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_xcpt_ae_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_xcpt_ae_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_xcpt_ma_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_xcpt_ma_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_bp_debug_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_bp_debug_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_bp_xcpt_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_bp_xcpt_if; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_debug_fsrc = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_debug_tsrc = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [31:0] _exe_tlb_uop_T_4_inst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_inst : _exe_tlb_uop_T_3_inst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [31:0] _exe_tlb_uop_T_4_debug_inst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_inst : _exe_tlb_uop_T_3_debug_inst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_rvc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_rvc : _exe_tlb_uop_T_3_is_rvc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [39:0] _exe_tlb_uop_T_4_debug_pc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_pc : _exe_tlb_uop_T_3_debug_pc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_0 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_0 : _exe_tlb_uop_T_3_iq_type_0; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_1 : _exe_tlb_uop_T_3_iq_type_1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_2 : _exe_tlb_uop_T_3_iq_type_2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_3 : _exe_tlb_uop_T_3_iq_type_3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_0 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_0 : _exe_tlb_uop_T_3_fu_code_0; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_1 : _exe_tlb_uop_T_3_fu_code_1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_2 : _exe_tlb_uop_T_3_fu_code_2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_3 : _exe_tlb_uop_T_3_fu_code_3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_4 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_4 : _exe_tlb_uop_T_3_fu_code_4; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_5 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_5 : _exe_tlb_uop_T_3_fu_code_5; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_6 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_6 : _exe_tlb_uop_T_3_fu_code_6; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_7 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_7 : _exe_tlb_uop_T_3_fu_code_7; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_8 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_8 : _exe_tlb_uop_T_3_fu_code_8; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_9 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_9 : _exe_tlb_uop_T_3_fu_code_9; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_issued = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_issued : _exe_tlb_uop_T_3_iw_issued; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_issued_partial_agen = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_issued_partial_agen : _exe_tlb_uop_T_3_iw_issued_partial_agen; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_issued_partial_dgen = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _exe_tlb_uop_T_3_iw_issued_partial_dgen; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_iw_p1_speculative_child = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p1_speculative_child : _exe_tlb_uop_T_3_iw_p1_speculative_child; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_iw_p2_speculative_child = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p2_speculative_child : _exe_tlb_uop_T_3_iw_p2_speculative_child; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_p1_bypass_hint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _exe_tlb_uop_T_3_iw_p1_bypass_hint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_p2_bypass_hint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _exe_tlb_uop_T_3_iw_p2_bypass_hint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_p3_bypass_hint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _exe_tlb_uop_T_3_iw_p3_bypass_hint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_dis_col_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_dis_col_sel : _exe_tlb_uop_T_3_dis_col_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [11:0] _exe_tlb_uop_T_4_br_mask = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_br_mask : _exe_tlb_uop_T_3_br_mask; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [3:0] _exe_tlb_uop_T_4_br_tag = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_br_tag : _exe_tlb_uop_T_3_br_tag; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [3:0] _exe_tlb_uop_T_4_br_type = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_br_type : _exe_tlb_uop_T_3_br_type; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_sfb = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_sfb : _exe_tlb_uop_T_3_is_sfb; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_fence = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_fence : _exe_tlb_uop_T_3_is_fence; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_fencei = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_fencei : _exe_tlb_uop_T_3_is_fencei; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_sfence = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_sfence : _exe_tlb_uop_T_3_is_sfence; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_amo = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_amo : _exe_tlb_uop_T_3_is_amo; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_eret = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_eret : _exe_tlb_uop_T_3_is_eret; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_sys_pc2epc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_3_is_sys_pc2epc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_rocc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_rocc : _exe_tlb_uop_T_3_is_rocc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_mov = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_mov : _exe_tlb_uop_T_3_is_mov; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_ftq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ftq_idx : _exe_tlb_uop_T_3_ftq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_edge_inst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_edge_inst : _exe_tlb_uop_T_3_edge_inst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_pc_lob = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_pc_lob : _exe_tlb_uop_T_3_pc_lob; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_taken = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_taken : _exe_tlb_uop_T_3_taken; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_imm_rename = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_imm_rename : _exe_tlb_uop_T_3_imm_rename; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_imm_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_imm_sel : _exe_tlb_uop_T_3_imm_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_pimm = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_pimm : _exe_tlb_uop_T_3_pimm; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [19:0] _exe_tlb_uop_T_4_imm_packed = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_imm_packed : _exe_tlb_uop_T_3_imm_packed; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_op1_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_op1_sel : _exe_tlb_uop_T_3_op1_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_op2_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_op2_sel : _exe_tlb_uop_T_3_op2_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ldst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ldst : _exe_tlb_uop_T_3_fp_ctrl_ldst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_wen = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_wen : _exe_tlb_uop_T_3_fp_ctrl_wen; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ren1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _exe_tlb_uop_T_3_fp_ctrl_ren1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ren2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _exe_tlb_uop_T_3_fp_ctrl_ren2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ren3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _exe_tlb_uop_T_3_fp_ctrl_ren3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_swap12 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _exe_tlb_uop_T_3_fp_ctrl_swap12; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_swap23 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _exe_tlb_uop_T_3_fp_ctrl_swap23; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_fp_ctrl_typeTagIn = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _exe_tlb_uop_T_3_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_fp_ctrl_typeTagOut = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _exe_tlb_uop_T_3_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_fromint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_fromint : _exe_tlb_uop_T_3_fp_ctrl_fromint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_toint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_toint : _exe_tlb_uop_T_3_fp_ctrl_toint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_fastpipe = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _exe_tlb_uop_T_3_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_fma = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_fma : _exe_tlb_uop_T_3_fp_ctrl_fma; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_div = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_div : _exe_tlb_uop_T_3_fp_ctrl_div; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_sqrt = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _exe_tlb_uop_T_3_fp_ctrl_sqrt; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_wflags = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_wflags : _exe_tlb_uop_T_3_fp_ctrl_wflags; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_vec = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_vec : _exe_tlb_uop_T_3_fp_ctrl_vec; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_rob_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_rob_idx : _exe_tlb_uop_T_3_rob_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [3:0] _exe_tlb_uop_T_4_ldq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ldq_idx : _exe_tlb_uop_T_3_ldq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [3:0] _exe_tlb_uop_T_4_stq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_stq_idx : _exe_tlb_uop_T_3_stq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_rxq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_rxq_idx : _exe_tlb_uop_T_3_rxq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_pdst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_pdst : _exe_tlb_uop_T_3_pdst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_prs1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs1 : _exe_tlb_uop_T_3_prs1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_prs2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs2 : _exe_tlb_uop_T_3_prs2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_prs3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs3 : _exe_tlb_uop_T_3_prs3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_ppred = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ppred : _exe_tlb_uop_T_3_ppred; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_prs1_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs1_busy : _exe_tlb_uop_T_3_prs1_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_prs2_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs2_busy : _exe_tlb_uop_T_3_prs2_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_prs3_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs3_busy : _exe_tlb_uop_T_3_prs3_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_ppred_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ppred_busy : _exe_tlb_uop_T_3_ppred_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_stale_pdst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_stale_pdst : _exe_tlb_uop_T_3_stale_pdst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_exception = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_exception : _exe_tlb_uop_T_3_exception; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [63:0] _exe_tlb_uop_T_4_exc_cause = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_exc_cause : _exe_tlb_uop_T_3_exc_cause; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_mem_cmd = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_mem_cmd : _exe_tlb_uop_T_3_mem_cmd; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_mem_size = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_mem_size : _exe_tlb_uop_T_3_mem_size; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_mem_signed = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_mem_signed : _exe_tlb_uop_T_3_mem_signed; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_uses_ldq = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_uses_ldq : _exe_tlb_uop_T_3_uses_ldq; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_uses_stq = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_uses_stq : _exe_tlb_uop_T_3_uses_stq; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_unique = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_unique : _exe_tlb_uop_T_3_is_unique; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_flush_on_commit = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_flush_on_commit : _exe_tlb_uop_T_3_flush_on_commit; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_csr_cmd = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_csr_cmd : _exe_tlb_uop_T_3_csr_cmd; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_ldst_is_rs1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_3_ldst_is_rs1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_ldst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ldst : _exe_tlb_uop_T_3_ldst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_lrs1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs1 : _exe_tlb_uop_T_3_lrs1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_lrs2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs2 : _exe_tlb_uop_T_3_lrs2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_lrs3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs3 : _exe_tlb_uop_T_3_lrs3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_dst_rtype = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_dst_rtype : _exe_tlb_uop_T_3_dst_rtype; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_lrs1_rtype = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs1_rtype : _exe_tlb_uop_T_3_lrs1_rtype; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_lrs2_rtype = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs2_rtype : _exe_tlb_uop_T_3_lrs2_rtype; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_frs3_en = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_frs3_en : _exe_tlb_uop_T_3_frs3_en; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fcn_dw = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fcn_dw : _exe_tlb_uop_T_3_fcn_dw; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_fcn_op = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fcn_op : _exe_tlb_uop_T_3_fcn_op; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_val = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_val : _exe_tlb_uop_T_3_fp_val; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_fp_rm = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_rm : _exe_tlb_uop_T_3_fp_rm; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_fp_typ = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_typ : _exe_tlb_uop_T_3_fp_typ; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_xcpt_pf_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_3_xcpt_pf_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_xcpt_ae_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_3_xcpt_ae_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_xcpt_ma_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_3_xcpt_ma_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_bp_debug_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_bp_debug_if : _exe_tlb_uop_T_3_bp_debug_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_bp_xcpt_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_3_bp_xcpt_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_debug_fsrc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_fsrc : _exe_tlb_uop_T_3_debug_fsrc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_debug_tsrc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_tsrc : _exe_tlb_uop_T_3_debug_tsrc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [31:0] _exe_tlb_uop_T_5_inst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_inst : _exe_tlb_uop_T_4_inst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [31:0] _exe_tlb_uop_T_5_debug_inst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_inst : _exe_tlb_uop_T_4_debug_inst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_rvc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_rvc : _exe_tlb_uop_T_4_is_rvc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [39:0] _exe_tlb_uop_T_5_debug_pc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_pc : _exe_tlb_uop_T_4_debug_pc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_0 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_0 : _exe_tlb_uop_T_4_iq_type_0; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_1 : _exe_tlb_uop_T_4_iq_type_1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_2 : _exe_tlb_uop_T_4_iq_type_2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_3 : _exe_tlb_uop_T_4_iq_type_3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_0 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_0 : _exe_tlb_uop_T_4_fu_code_0; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_1 : _exe_tlb_uop_T_4_fu_code_1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_2 : _exe_tlb_uop_T_4_fu_code_2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_3 : _exe_tlb_uop_T_4_fu_code_3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_4 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_4 : _exe_tlb_uop_T_4_fu_code_4; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_5 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_5 : _exe_tlb_uop_T_4_fu_code_5; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_6 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_6 : _exe_tlb_uop_T_4_fu_code_6; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_7 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_7 : _exe_tlb_uop_T_4_fu_code_7; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_8 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_8 : _exe_tlb_uop_T_4_fu_code_8; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_9 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_9 : _exe_tlb_uop_T_4_fu_code_9; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_issued = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_issued : _exe_tlb_uop_T_4_iw_issued; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_issued_partial_agen = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_issued_partial_agen : _exe_tlb_uop_T_4_iw_issued_partial_agen; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_issued_partial_dgen = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _exe_tlb_uop_T_4_iw_issued_partial_dgen; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_iw_p1_speculative_child = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p1_speculative_child : _exe_tlb_uop_T_4_iw_p1_speculative_child; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_iw_p2_speculative_child = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p2_speculative_child : _exe_tlb_uop_T_4_iw_p2_speculative_child; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_p1_bypass_hint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _exe_tlb_uop_T_4_iw_p1_bypass_hint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_p2_bypass_hint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _exe_tlb_uop_T_4_iw_p2_bypass_hint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_p3_bypass_hint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _exe_tlb_uop_T_4_iw_p3_bypass_hint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_dis_col_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_dis_col_sel : _exe_tlb_uop_T_4_dis_col_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [11:0] _exe_tlb_uop_T_5_br_mask = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_br_mask : _exe_tlb_uop_T_4_br_mask; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [3:0] _exe_tlb_uop_T_5_br_tag = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_br_tag : _exe_tlb_uop_T_4_br_tag; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [3:0] _exe_tlb_uop_T_5_br_type = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_br_type : _exe_tlb_uop_T_4_br_type; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_sfb = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_sfb : _exe_tlb_uop_T_4_is_sfb; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_fence = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_fence : _exe_tlb_uop_T_4_is_fence; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_fencei = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_fencei : _exe_tlb_uop_T_4_is_fencei; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_sfence = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_sfence : _exe_tlb_uop_T_4_is_sfence; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_amo = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_amo : _exe_tlb_uop_T_4_is_amo; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_eret = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_eret : _exe_tlb_uop_T_4_is_eret; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_sys_pc2epc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_4_is_sys_pc2epc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_rocc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_rocc : _exe_tlb_uop_T_4_is_rocc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_mov = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_mov : _exe_tlb_uop_T_4_is_mov; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_ftq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ftq_idx : _exe_tlb_uop_T_4_ftq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_edge_inst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_edge_inst : _exe_tlb_uop_T_4_edge_inst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_pc_lob = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_pc_lob : _exe_tlb_uop_T_4_pc_lob; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_taken = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_taken : _exe_tlb_uop_T_4_taken; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_imm_rename = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_imm_rename : _exe_tlb_uop_T_4_imm_rename; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_imm_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_imm_sel : _exe_tlb_uop_T_4_imm_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_pimm = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_pimm : _exe_tlb_uop_T_4_pimm; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [19:0] _exe_tlb_uop_T_5_imm_packed = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_imm_packed : _exe_tlb_uop_T_4_imm_packed; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_op1_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_op1_sel : _exe_tlb_uop_T_4_op1_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_op2_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_op2_sel : _exe_tlb_uop_T_4_op2_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ldst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ldst : _exe_tlb_uop_T_4_fp_ctrl_ldst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_wen = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_wen : _exe_tlb_uop_T_4_fp_ctrl_wen; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ren1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _exe_tlb_uop_T_4_fp_ctrl_ren1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ren2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _exe_tlb_uop_T_4_fp_ctrl_ren2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ren3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _exe_tlb_uop_T_4_fp_ctrl_ren3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_swap12 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _exe_tlb_uop_T_4_fp_ctrl_swap12; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_swap23 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _exe_tlb_uop_T_4_fp_ctrl_swap23; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_fp_ctrl_typeTagIn = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _exe_tlb_uop_T_4_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_fp_ctrl_typeTagOut = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _exe_tlb_uop_T_4_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_fromint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_fromint : _exe_tlb_uop_T_4_fp_ctrl_fromint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_toint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_toint : _exe_tlb_uop_T_4_fp_ctrl_toint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_fastpipe = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _exe_tlb_uop_T_4_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_fma = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_fma : _exe_tlb_uop_T_4_fp_ctrl_fma; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_div = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_div : _exe_tlb_uop_T_4_fp_ctrl_div; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_sqrt = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _exe_tlb_uop_T_4_fp_ctrl_sqrt; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_wflags = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_wflags : _exe_tlb_uop_T_4_fp_ctrl_wflags; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_vec = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_vec : _exe_tlb_uop_T_4_fp_ctrl_vec; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_rob_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_rob_idx : _exe_tlb_uop_T_4_rob_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [3:0] _exe_tlb_uop_T_5_ldq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ldq_idx : _exe_tlb_uop_T_4_ldq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [3:0] _exe_tlb_uop_T_5_stq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_stq_idx : _exe_tlb_uop_T_4_stq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_rxq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_rxq_idx : _exe_tlb_uop_T_4_rxq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_pdst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_pdst : _exe_tlb_uop_T_4_pdst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_prs1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs1 : _exe_tlb_uop_T_4_prs1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_prs2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs2 : _exe_tlb_uop_T_4_prs2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_prs3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs3 : _exe_tlb_uop_T_4_prs3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_ppred = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ppred : _exe_tlb_uop_T_4_ppred; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_prs1_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs1_busy : _exe_tlb_uop_T_4_prs1_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_prs2_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs2_busy : _exe_tlb_uop_T_4_prs2_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_prs3_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs3_busy : _exe_tlb_uop_T_4_prs3_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_ppred_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ppred_busy : _exe_tlb_uop_T_4_ppred_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_stale_pdst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_stale_pdst : _exe_tlb_uop_T_4_stale_pdst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_exception = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_exception : _exe_tlb_uop_T_4_exception; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [63:0] _exe_tlb_uop_T_5_exc_cause = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_exc_cause : _exe_tlb_uop_T_4_exc_cause; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_mem_cmd = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_mem_cmd : _exe_tlb_uop_T_4_mem_cmd; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_mem_size = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_mem_size : _exe_tlb_uop_T_4_mem_size; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_mem_signed = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_mem_signed : _exe_tlb_uop_T_4_mem_signed; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_uses_ldq = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_uses_ldq : _exe_tlb_uop_T_4_uses_ldq; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_uses_stq = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_uses_stq : _exe_tlb_uop_T_4_uses_stq; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_unique = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_unique : _exe_tlb_uop_T_4_is_unique; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_flush_on_commit = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_flush_on_commit : _exe_tlb_uop_T_4_flush_on_commit; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_csr_cmd = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_csr_cmd : _exe_tlb_uop_T_4_csr_cmd; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_ldst_is_rs1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_4_ldst_is_rs1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_ldst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ldst : _exe_tlb_uop_T_4_ldst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_lrs1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs1 : _exe_tlb_uop_T_4_lrs1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_lrs2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs2 : _exe_tlb_uop_T_4_lrs2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_lrs3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs3 : _exe_tlb_uop_T_4_lrs3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_dst_rtype = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_dst_rtype : _exe_tlb_uop_T_4_dst_rtype; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_lrs1_rtype = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs1_rtype : _exe_tlb_uop_T_4_lrs1_rtype; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_lrs2_rtype = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs2_rtype : _exe_tlb_uop_T_4_lrs2_rtype; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_frs3_en = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_frs3_en : _exe_tlb_uop_T_4_frs3_en; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fcn_dw = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fcn_dw : _exe_tlb_uop_T_4_fcn_dw; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_fcn_op = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fcn_op : _exe_tlb_uop_T_4_fcn_op; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_val = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_val : _exe_tlb_uop_T_4_fp_val; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_fp_rm = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_rm : _exe_tlb_uop_T_4_fp_rm; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_fp_typ = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_typ : _exe_tlb_uop_T_4_fp_typ; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_xcpt_pf_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_4_xcpt_pf_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_xcpt_ae_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_4_xcpt_ae_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_xcpt_ma_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_4_xcpt_ma_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_bp_debug_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_bp_debug_if : _exe_tlb_uop_T_4_bp_debug_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_bp_xcpt_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_4_bp_xcpt_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_debug_fsrc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_fsrc : _exe_tlb_uop_T_4_debug_fsrc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_debug_tsrc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_tsrc : _exe_tlb_uop_T_4_debug_tsrc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [31:0] exe_tlb_uop_0_inst = _exe_tlb_uop_T_5_inst; // @[lsu.scala:321:49, :717:24] wire [31:0] exe_tlb_uop_0_debug_inst = _exe_tlb_uop_T_5_debug_inst; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_rvc = _exe_tlb_uop_T_5_is_rvc; // @[lsu.scala:321:49, :717:24] wire [39:0] exe_tlb_uop_0_debug_pc = _exe_tlb_uop_T_5_debug_pc; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_0 = _exe_tlb_uop_T_5_iq_type_0; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_1 = _exe_tlb_uop_T_5_iq_type_1; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_2 = _exe_tlb_uop_T_5_iq_type_2; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_3 = _exe_tlb_uop_T_5_iq_type_3; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_0 = _exe_tlb_uop_T_5_fu_code_0; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_1 = _exe_tlb_uop_T_5_fu_code_1; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_2 = _exe_tlb_uop_T_5_fu_code_2; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_3 = _exe_tlb_uop_T_5_fu_code_3; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_4 = _exe_tlb_uop_T_5_fu_code_4; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_5 = _exe_tlb_uop_T_5_fu_code_5; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_6 = _exe_tlb_uop_T_5_fu_code_6; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_7 = _exe_tlb_uop_T_5_fu_code_7; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_8 = _exe_tlb_uop_T_5_fu_code_8; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_9 = _exe_tlb_uop_T_5_fu_code_9; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_issued = _exe_tlb_uop_T_5_iw_issued; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_issued_partial_agen = _exe_tlb_uop_T_5_iw_issued_partial_agen; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_issued_partial_dgen = _exe_tlb_uop_T_5_iw_issued_partial_dgen; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_iw_p1_speculative_child = _exe_tlb_uop_T_5_iw_p1_speculative_child; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_iw_p2_speculative_child = _exe_tlb_uop_T_5_iw_p2_speculative_child; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_p1_bypass_hint = _exe_tlb_uop_T_5_iw_p1_bypass_hint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_p2_bypass_hint = _exe_tlb_uop_T_5_iw_p2_bypass_hint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_p3_bypass_hint = _exe_tlb_uop_T_5_iw_p3_bypass_hint; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_dis_col_sel = _exe_tlb_uop_T_5_dis_col_sel; // @[lsu.scala:321:49, :717:24] wire [11:0] exe_tlb_uop_0_br_mask = _exe_tlb_uop_T_5_br_mask; // @[lsu.scala:321:49, :717:24] wire [3:0] exe_tlb_uop_0_br_tag = _exe_tlb_uop_T_5_br_tag; // @[lsu.scala:321:49, :717:24] wire [3:0] exe_tlb_uop_0_br_type = _exe_tlb_uop_T_5_br_type; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_sfb = _exe_tlb_uop_T_5_is_sfb; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_fence = _exe_tlb_uop_T_5_is_fence; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_fencei = _exe_tlb_uop_T_5_is_fencei; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_sfence = _exe_tlb_uop_T_5_is_sfence; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_amo = _exe_tlb_uop_T_5_is_amo; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_eret = _exe_tlb_uop_T_5_is_eret; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_sys_pc2epc = _exe_tlb_uop_T_5_is_sys_pc2epc; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_rocc = _exe_tlb_uop_T_5_is_rocc; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_mov = _exe_tlb_uop_T_5_is_mov; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_ftq_idx = _exe_tlb_uop_T_5_ftq_idx; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_edge_inst = _exe_tlb_uop_T_5_edge_inst; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_pc_lob = _exe_tlb_uop_T_5_pc_lob; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_taken = _exe_tlb_uop_T_5_taken; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_imm_rename = _exe_tlb_uop_T_5_imm_rename; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_imm_sel = _exe_tlb_uop_T_5_imm_sel; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_pimm = _exe_tlb_uop_T_5_pimm; // @[lsu.scala:321:49, :717:24] wire [19:0] exe_tlb_uop_0_imm_packed = _exe_tlb_uop_T_5_imm_packed; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_op1_sel = _exe_tlb_uop_T_5_op1_sel; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_op2_sel = _exe_tlb_uop_T_5_op2_sel; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ldst = _exe_tlb_uop_T_5_fp_ctrl_ldst; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_wen = _exe_tlb_uop_T_5_fp_ctrl_wen; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ren1 = _exe_tlb_uop_T_5_fp_ctrl_ren1; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ren2 = _exe_tlb_uop_T_5_fp_ctrl_ren2; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ren3 = _exe_tlb_uop_T_5_fp_ctrl_ren3; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_swap12 = _exe_tlb_uop_T_5_fp_ctrl_swap12; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_swap23 = _exe_tlb_uop_T_5_fp_ctrl_swap23; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_fp_ctrl_typeTagIn = _exe_tlb_uop_T_5_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_fp_ctrl_typeTagOut = _exe_tlb_uop_T_5_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_fromint = _exe_tlb_uop_T_5_fp_ctrl_fromint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_toint = _exe_tlb_uop_T_5_fp_ctrl_toint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_fastpipe = _exe_tlb_uop_T_5_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_fma = _exe_tlb_uop_T_5_fp_ctrl_fma; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_div = _exe_tlb_uop_T_5_fp_ctrl_div; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_sqrt = _exe_tlb_uop_T_5_fp_ctrl_sqrt; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_wflags = _exe_tlb_uop_T_5_fp_ctrl_wflags; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_vec = _exe_tlb_uop_T_5_fp_ctrl_vec; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_rob_idx = _exe_tlb_uop_T_5_rob_idx; // @[lsu.scala:321:49, :717:24] wire [3:0] exe_tlb_uop_0_ldq_idx = _exe_tlb_uop_T_5_ldq_idx; // @[lsu.scala:321:49, :717:24] wire [3:0] exe_tlb_uop_0_stq_idx = _exe_tlb_uop_T_5_stq_idx; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_rxq_idx = _exe_tlb_uop_T_5_rxq_idx; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_pdst = _exe_tlb_uop_T_5_pdst; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_prs1 = _exe_tlb_uop_T_5_prs1; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_prs2 = _exe_tlb_uop_T_5_prs2; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_prs3 = _exe_tlb_uop_T_5_prs3; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_ppred = _exe_tlb_uop_T_5_ppred; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_prs1_busy = _exe_tlb_uop_T_5_prs1_busy; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_prs2_busy = _exe_tlb_uop_T_5_prs2_busy; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_prs3_busy = _exe_tlb_uop_T_5_prs3_busy; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_ppred_busy = _exe_tlb_uop_T_5_ppred_busy; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_stale_pdst = _exe_tlb_uop_T_5_stale_pdst; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_exception = _exe_tlb_uop_T_5_exception; // @[lsu.scala:321:49, :717:24] wire [63:0] exe_tlb_uop_0_exc_cause = _exe_tlb_uop_T_5_exc_cause; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_mem_cmd = _exe_tlb_uop_T_5_mem_cmd; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_mem_size = _exe_tlb_uop_T_5_mem_size; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_mem_signed = _exe_tlb_uop_T_5_mem_signed; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_uses_ldq = _exe_tlb_uop_T_5_uses_ldq; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_uses_stq = _exe_tlb_uop_T_5_uses_stq; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_unique = _exe_tlb_uop_T_5_is_unique; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_flush_on_commit = _exe_tlb_uop_T_5_flush_on_commit; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_csr_cmd = _exe_tlb_uop_T_5_csr_cmd; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_ldst_is_rs1 = _exe_tlb_uop_T_5_ldst_is_rs1; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_ldst = _exe_tlb_uop_T_5_ldst; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_lrs1 = _exe_tlb_uop_T_5_lrs1; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_lrs2 = _exe_tlb_uop_T_5_lrs2; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_lrs3 = _exe_tlb_uop_T_5_lrs3; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_dst_rtype = _exe_tlb_uop_T_5_dst_rtype; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_lrs1_rtype = _exe_tlb_uop_T_5_lrs1_rtype; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_lrs2_rtype = _exe_tlb_uop_T_5_lrs2_rtype; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_frs3_en = _exe_tlb_uop_T_5_frs3_en; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fcn_dw = _exe_tlb_uop_T_5_fcn_dw; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_fcn_op = _exe_tlb_uop_T_5_fcn_op; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_val = _exe_tlb_uop_T_5_fp_val; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_fp_rm = _exe_tlb_uop_T_5_fp_rm; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_fp_typ = _exe_tlb_uop_T_5_fp_typ; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_xcpt_pf_if = _exe_tlb_uop_T_5_xcpt_pf_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_xcpt_ae_if = _exe_tlb_uop_T_5_xcpt_ae_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_xcpt_ma_if = _exe_tlb_uop_T_5_xcpt_ma_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_bp_debug_if = _exe_tlb_uop_T_5_bp_debug_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_bp_xcpt_if = _exe_tlb_uop_T_5_bp_xcpt_if; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_debug_fsrc = _exe_tlb_uop_T_5_debug_fsrc; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_debug_tsrc = _exe_tlb_uop_T_5_debug_tsrc; // @[lsu.scala:321:49, :717:24] wire [31:0] mem_xcpt_uops_out_inst = exe_tlb_uop_0_inst; // @[util.scala:104:23] wire [31:0] mem_xcpt_uops_out_debug_inst = exe_tlb_uop_0_debug_inst; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_rvc = exe_tlb_uop_0_is_rvc; // @[util.scala:104:23] wire [39:0] mem_xcpt_uops_out_debug_pc = exe_tlb_uop_0_debug_pc; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_0 = exe_tlb_uop_0_iq_type_0; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_1 = exe_tlb_uop_0_iq_type_1; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_2 = exe_tlb_uop_0_iq_type_2; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_3 = exe_tlb_uop_0_iq_type_3; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_0 = exe_tlb_uop_0_fu_code_0; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_1 = exe_tlb_uop_0_fu_code_1; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_2 = exe_tlb_uop_0_fu_code_2; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_3 = exe_tlb_uop_0_fu_code_3; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_4 = exe_tlb_uop_0_fu_code_4; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_5 = exe_tlb_uop_0_fu_code_5; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_6 = exe_tlb_uop_0_fu_code_6; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_7 = exe_tlb_uop_0_fu_code_7; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_8 = exe_tlb_uop_0_fu_code_8; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_9 = exe_tlb_uop_0_fu_code_9; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_issued = exe_tlb_uop_0_iw_issued; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_issued_partial_agen = exe_tlb_uop_0_iw_issued_partial_agen; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_issued_partial_dgen = exe_tlb_uop_0_iw_issued_partial_dgen; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_iw_p1_speculative_child = exe_tlb_uop_0_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_iw_p2_speculative_child = exe_tlb_uop_0_iw_p2_speculative_child; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_p1_bypass_hint = exe_tlb_uop_0_iw_p1_bypass_hint; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_p2_bypass_hint = exe_tlb_uop_0_iw_p2_bypass_hint; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_p3_bypass_hint = exe_tlb_uop_0_iw_p3_bypass_hint; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_dis_col_sel = exe_tlb_uop_0_dis_col_sel; // @[util.scala:104:23] wire [3:0] mem_xcpt_uops_out_br_tag = exe_tlb_uop_0_br_tag; // @[util.scala:104:23] wire [3:0] mem_xcpt_uops_out_br_type = exe_tlb_uop_0_br_type; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_sfb = exe_tlb_uop_0_is_sfb; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_fence = exe_tlb_uop_0_is_fence; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_fencei = exe_tlb_uop_0_is_fencei; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_sfence = exe_tlb_uop_0_is_sfence; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_amo = exe_tlb_uop_0_is_amo; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_eret = exe_tlb_uop_0_is_eret; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_sys_pc2epc = exe_tlb_uop_0_is_sys_pc2epc; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_rocc = exe_tlb_uop_0_is_rocc; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_mov = exe_tlb_uop_0_is_mov; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_ftq_idx = exe_tlb_uop_0_ftq_idx; // @[util.scala:104:23] wire mem_xcpt_uops_out_edge_inst = exe_tlb_uop_0_edge_inst; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_pc_lob = exe_tlb_uop_0_pc_lob; // @[util.scala:104:23] wire mem_xcpt_uops_out_taken = exe_tlb_uop_0_taken; // @[util.scala:104:23] wire mem_xcpt_uops_out_imm_rename = exe_tlb_uop_0_imm_rename; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_imm_sel = exe_tlb_uop_0_imm_sel; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_pimm = exe_tlb_uop_0_pimm; // @[util.scala:104:23] wire [19:0] mem_xcpt_uops_out_imm_packed = exe_tlb_uop_0_imm_packed; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_op1_sel = exe_tlb_uop_0_op1_sel; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_op2_sel = exe_tlb_uop_0_op2_sel; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ldst = exe_tlb_uop_0_fp_ctrl_ldst; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_wen = exe_tlb_uop_0_fp_ctrl_wen; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ren1 = exe_tlb_uop_0_fp_ctrl_ren1; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ren2 = exe_tlb_uop_0_fp_ctrl_ren2; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ren3 = exe_tlb_uop_0_fp_ctrl_ren3; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_swap12 = exe_tlb_uop_0_fp_ctrl_swap12; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_swap23 = exe_tlb_uop_0_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_fp_ctrl_typeTagIn = exe_tlb_uop_0_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_fp_ctrl_typeTagOut = exe_tlb_uop_0_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_fromint = exe_tlb_uop_0_fp_ctrl_fromint; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_toint = exe_tlb_uop_0_fp_ctrl_toint; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_fastpipe = exe_tlb_uop_0_fp_ctrl_fastpipe; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_fma = exe_tlb_uop_0_fp_ctrl_fma; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_div = exe_tlb_uop_0_fp_ctrl_div; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_sqrt = exe_tlb_uop_0_fp_ctrl_sqrt; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_wflags = exe_tlb_uop_0_fp_ctrl_wflags; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_vec = exe_tlb_uop_0_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_rob_idx = exe_tlb_uop_0_rob_idx; // @[util.scala:104:23] wire [3:0] mem_xcpt_uops_out_ldq_idx = exe_tlb_uop_0_ldq_idx; // @[util.scala:104:23] wire [3:0] mem_xcpt_uops_out_stq_idx = exe_tlb_uop_0_stq_idx; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_rxq_idx = exe_tlb_uop_0_rxq_idx; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_pdst = exe_tlb_uop_0_pdst; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_prs1 = exe_tlb_uop_0_prs1; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_prs2 = exe_tlb_uop_0_prs2; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_prs3 = exe_tlb_uop_0_prs3; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_ppred = exe_tlb_uop_0_ppred; // @[util.scala:104:23] wire mem_xcpt_uops_out_prs1_busy = exe_tlb_uop_0_prs1_busy; // @[util.scala:104:23] wire mem_xcpt_uops_out_prs2_busy = exe_tlb_uop_0_prs2_busy; // @[util.scala:104:23] wire mem_xcpt_uops_out_prs3_busy = exe_tlb_uop_0_prs3_busy; // @[util.scala:104:23] wire mem_xcpt_uops_out_ppred_busy = exe_tlb_uop_0_ppred_busy; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_stale_pdst = exe_tlb_uop_0_stale_pdst; // @[util.scala:104:23] wire mem_xcpt_uops_out_exception = exe_tlb_uop_0_exception; // @[util.scala:104:23] wire [63:0] mem_xcpt_uops_out_exc_cause = exe_tlb_uop_0_exc_cause; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_mem_cmd = exe_tlb_uop_0_mem_cmd; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_mem_size = exe_tlb_uop_0_mem_size; // @[util.scala:104:23] wire mem_xcpt_uops_out_mem_signed = exe_tlb_uop_0_mem_signed; // @[util.scala:104:23] wire mem_xcpt_uops_out_uses_ldq = exe_tlb_uop_0_uses_ldq; // @[util.scala:104:23] wire mem_xcpt_uops_out_uses_stq = exe_tlb_uop_0_uses_stq; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_unique = exe_tlb_uop_0_is_unique; // @[util.scala:104:23] wire mem_xcpt_uops_out_flush_on_commit = exe_tlb_uop_0_flush_on_commit; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_csr_cmd = exe_tlb_uop_0_csr_cmd; // @[util.scala:104:23] wire mem_xcpt_uops_out_ldst_is_rs1 = exe_tlb_uop_0_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_ldst = exe_tlb_uop_0_ldst; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_lrs1 = exe_tlb_uop_0_lrs1; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_lrs2 = exe_tlb_uop_0_lrs2; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_lrs3 = exe_tlb_uop_0_lrs3; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_dst_rtype = exe_tlb_uop_0_dst_rtype; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_lrs1_rtype = exe_tlb_uop_0_lrs1_rtype; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_lrs2_rtype = exe_tlb_uop_0_lrs2_rtype; // @[util.scala:104:23] wire mem_xcpt_uops_out_frs3_en = exe_tlb_uop_0_frs3_en; // @[util.scala:104:23] wire mem_xcpt_uops_out_fcn_dw = exe_tlb_uop_0_fcn_dw; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_fcn_op = exe_tlb_uop_0_fcn_op; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_val = exe_tlb_uop_0_fp_val; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_fp_rm = exe_tlb_uop_0_fp_rm; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_fp_typ = exe_tlb_uop_0_fp_typ; // @[util.scala:104:23] wire mem_xcpt_uops_out_xcpt_pf_if = exe_tlb_uop_0_xcpt_pf_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_xcpt_ae_if = exe_tlb_uop_0_xcpt_ae_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_xcpt_ma_if = exe_tlb_uop_0_xcpt_ma_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_bp_debug_if = exe_tlb_uop_0_bp_debug_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_bp_xcpt_if = exe_tlb_uop_0_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_debug_fsrc = exe_tlb_uop_0_debug_fsrc; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_debug_tsrc = exe_tlb_uop_0_debug_tsrc; // @[util.scala:104:23] wire _exe_tlb_vaddr_T_1 = _exe_tlb_vaddr_T | will_fire_store_agen_0; // @[lsu.scala:471:41, :726:53, :727:53] wire [39:0] _exe_tlb_vaddr_T_3 = will_fire_hella_incoming_0 ? hella_req_addr : 40'h0; // @[lsu.scala:302:34, :473:41, :732:24] wire [63:0] _exe_tlb_vaddr_T_4 = _exe_tlb_vaddr_T_2 ? _retry_queue_io_deq_bits_data : {24'h0, _exe_tlb_vaddr_T_3}; // @[lsu.scala:533:27, :539:32, :730:{24,53}, :732:24] wire [63:0] _exe_tlb_vaddr_T_5 = will_fire_sfence_0 ? {25'h0, io_core_sfence_bits_addr_0} : _exe_tlb_vaddr_T_4; // @[lsu.scala:211:7, :472:41, :729:24, :730:24] wire [63:0] _exe_tlb_vaddr_T_6 = _exe_tlb_vaddr_T_1 ? io_core_agen_0_bits_data_0 : _exe_tlb_vaddr_T_5; // @[lsu.scala:211:7, :726:24, :727:53, :729:24] wire [63:0] exe_tlb_vaddr_0 = _exe_tlb_vaddr_T_6; // @[lsu.scala:321:49, :726:24] wire _exe_size_T_1 = _exe_size_T | will_fire_store_agen_0; // @[lsu.scala:471:41, :738:52, :739:52] wire _exe_size_T_2 = _exe_size_T_1 | will_fire_load_retry_0; // @[lsu.scala:476:41, :739:52, :740:52] wire _exe_size_T_3 = _exe_size_T_2 | will_fire_store_retry_0; // @[lsu.scala:477:41, :740:52, :741:52] wire [1:0] _exe_size_T_4 = {2{will_fire_hella_incoming_0}}; // @[lsu.scala:473:41, :743:23] wire [1:0] _exe_size_T_5 = _exe_size_T_3 ? exe_tlb_uop_0_mem_size : _exe_size_T_4; // @[lsu.scala:321:49, :738:23, :741:52, :743:23] wire [1:0] exe_size_0 = _exe_size_T_5; // @[lsu.scala:321:49, :738:23] wire _exe_cmd_T_1 = _exe_cmd_T | will_fire_store_agen_0; // @[lsu.scala:471:41, :746:52, :747:52] wire _exe_cmd_T_2 = _exe_cmd_T_1 | will_fire_load_retry_0; // @[lsu.scala:476:41, :747:52, :748:52] wire _exe_cmd_T_3 = _exe_cmd_T_2 | will_fire_store_retry_0; // @[lsu.scala:477:41, :748:52, :749:52] wire [4:0] _exe_cmd_T_4 = will_fire_sfence_0 ? 5'h14 : 5'h0; // @[lsu.scala:472:41, :752:23] wire [4:0] _exe_cmd_T_5 = will_fire_hella_incoming_0 ? 5'h0 : _exe_cmd_T_4; // @[lsu.scala:473:41, :751:23, :752:23] wire [4:0] _exe_cmd_T_6 = _exe_cmd_T_3 ? exe_tlb_uop_0_mem_cmd : _exe_cmd_T_5; // @[lsu.scala:321:49, :746:23, :749:52, :751:23] wire [4:0] exe_cmd_0 = _exe_cmd_T_6; // @[lsu.scala:321:49, :746:23] wire exe_passthr_0 = _exe_passthr_T; // @[lsu.scala:321:49, :756:23] wire _exe_kill_T = will_fire_hella_incoming_0 & io_hellacache_s1_kill_0; // @[lsu.scala:211:7, :473:41, :759:23] wire exe_kill_0 = _exe_kill_T; // @[lsu.scala:321:49, :759:23] wire _ma_ld_T = _dtlb_io_resp_0_ma_ld & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:308:20, :321:49, :782:52] wire ma_ld_0 = _ma_ld_T; // @[lsu.scala:321:49, :782:52] wire _ma_st_T = _dtlb_io_resp_0_ma_st & exe_tlb_uop_0_uses_stq; // @[lsu.scala:308:20, :321:49, :783:52] wire _ma_st_T_1 = ~exe_tlb_uop_0_is_fence; // @[lsu.scala:321:49, :783:82] wire _ma_st_T_2 = _ma_st_T & _ma_st_T_1; // @[lsu.scala:783:{52,79,82}] wire ma_st_0 = _ma_st_T_2; // @[lsu.scala:321:49, :783:79] wire _pf_ld_T = _dtlb_io_resp_0_pf_ld & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:308:20, :321:49, :784:52] wire pf_ld_0 = _pf_ld_T; // @[lsu.scala:321:49, :784:52] wire _pf_st_T = _dtlb_io_resp_0_pf_st & exe_tlb_uop_0_uses_stq; // @[lsu.scala:308:20, :321:49, :785:52] wire pf_st_0 = _pf_st_T; // @[lsu.scala:321:49, :785:52] wire _ae_ld_T = _dtlb_io_resp_0_ae_ld & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:308:20, :321:49, :786:52] wire ae_ld_0 = _ae_ld_T; // @[lsu.scala:321:49, :786:52] wire _ae_st_T = _dtlb_io_resp_0_ae_st & exe_tlb_uop_0_uses_stq; // @[lsu.scala:308:20, :321:49, :787:52] wire ae_st_0 = _ae_st_T; // @[lsu.scala:321:49, :787:52] wire _dbg_bp_T_2 = ~exe_tlb_uop_0_is_fence; // @[lsu.scala:321:49, :783:82, :789:107] wire _bp_T_2 = ~exe_tlb_uop_0_is_fence; // @[lsu.scala:321:49, :783:82, :791:106] wire _mem_xcpt_valids_T = pf_ld_0 | pf_st_0; // @[lsu.scala:321:49, :797:32] wire _mem_xcpt_valids_T_1 = _mem_xcpt_valids_T | ae_ld_0; // @[lsu.scala:321:49, :797:{32,44}] wire _mem_xcpt_valids_T_2 = _mem_xcpt_valids_T_1 | ae_st_0; // @[lsu.scala:321:49, :797:{44,56}] wire _mem_xcpt_valids_T_3 = _mem_xcpt_valids_T_2 | ma_ld_0; // @[lsu.scala:321:49, :797:{56,68}] wire _mem_xcpt_valids_T_4 = _mem_xcpt_valids_T_3 | ma_st_0; // @[lsu.scala:321:49, :797:{68,80}] wire _mem_xcpt_valids_T_5 = _mem_xcpt_valids_T_4; // @[lsu.scala:797:{80,92}] wire _mem_xcpt_valids_T_6 = _mem_xcpt_valids_T_5; // @[lsu.scala:797:{92,105}] wire _mem_xcpt_valids_T_7 = exe_tlb_valid_0 & _mem_xcpt_valids_T_6; // @[lsu.scala:649:27, :796:39, :797:105] wire [11:0] _mem_xcpt_valids_T_8 = io_core_brupdate_b1_mispredict_mask_0 & exe_tlb_uop_0_br_mask; // @[util.scala:126:51] wire _mem_xcpt_valids_T_9 = |_mem_xcpt_valids_T_8; // @[util.scala:126:{51,59}] wire _mem_xcpt_valids_T_10 = _mem_xcpt_valids_T_9 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_xcpt_valids_T_11 = ~_mem_xcpt_valids_T_10; // @[util.scala:61:61] wire _mem_xcpt_valids_T_12 = _mem_xcpt_valids_T_7 & _mem_xcpt_valids_T_11; // @[lsu.scala:796:39, :797:115, :798:22] wire _mem_xcpt_valids_WIRE_0 = _mem_xcpt_valids_T_12; // @[lsu.scala:321:49, :797:115] reg mem_xcpt_valids_0; // @[lsu.scala:795:32] assign mem_xcpt_valid = mem_xcpt_valids_0; // @[lsu.scala:457:29, :795:32] wire [31:0] _mem_xcpt_uops_WIRE_0_inst = mem_xcpt_uops_out_inst; // @[util.scala:104:23] wire [31:0] _mem_xcpt_uops_WIRE_0_debug_inst = mem_xcpt_uops_out_debug_inst; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_rvc = mem_xcpt_uops_out_is_rvc; // @[util.scala:104:23] wire [39:0] _mem_xcpt_uops_WIRE_0_debug_pc = mem_xcpt_uops_out_debug_pc; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_0 = mem_xcpt_uops_out_iq_type_0; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_1 = mem_xcpt_uops_out_iq_type_1; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_2 = mem_xcpt_uops_out_iq_type_2; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_3 = mem_xcpt_uops_out_iq_type_3; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_0 = mem_xcpt_uops_out_fu_code_0; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_1 = mem_xcpt_uops_out_fu_code_1; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_2 = mem_xcpt_uops_out_fu_code_2; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_3 = mem_xcpt_uops_out_fu_code_3; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_4 = mem_xcpt_uops_out_fu_code_4; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_5 = mem_xcpt_uops_out_fu_code_5; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_6 = mem_xcpt_uops_out_fu_code_6; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_7 = mem_xcpt_uops_out_fu_code_7; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_8 = mem_xcpt_uops_out_fu_code_8; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_9 = mem_xcpt_uops_out_fu_code_9; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_issued = mem_xcpt_uops_out_iw_issued; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_issued_partial_agen = mem_xcpt_uops_out_iw_issued_partial_agen; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_issued_partial_dgen = mem_xcpt_uops_out_iw_issued_partial_dgen; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_iw_p1_speculative_child = mem_xcpt_uops_out_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_iw_p2_speculative_child = mem_xcpt_uops_out_iw_p2_speculative_child; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_p1_bypass_hint = mem_xcpt_uops_out_iw_p1_bypass_hint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_p2_bypass_hint = mem_xcpt_uops_out_iw_p2_bypass_hint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_p3_bypass_hint = mem_xcpt_uops_out_iw_p3_bypass_hint; // @[util.scala:104:23] wire [11:0] _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:93:25] wire [1:0] _mem_xcpt_uops_WIRE_0_dis_col_sel = mem_xcpt_uops_out_dis_col_sel; // @[util.scala:104:23] wire [11:0] _mem_xcpt_uops_WIRE_0_br_mask = mem_xcpt_uops_out_br_mask; // @[util.scala:104:23] wire [3:0] _mem_xcpt_uops_WIRE_0_br_tag = mem_xcpt_uops_out_br_tag; // @[util.scala:104:23] wire [3:0] _mem_xcpt_uops_WIRE_0_br_type = mem_xcpt_uops_out_br_type; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_sfb = mem_xcpt_uops_out_is_sfb; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_fence = mem_xcpt_uops_out_is_fence; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_fencei = mem_xcpt_uops_out_is_fencei; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_sfence = mem_xcpt_uops_out_is_sfence; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_amo = mem_xcpt_uops_out_is_amo; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_eret = mem_xcpt_uops_out_is_eret; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_sys_pc2epc = mem_xcpt_uops_out_is_sys_pc2epc; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_rocc = mem_xcpt_uops_out_is_rocc; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_mov = mem_xcpt_uops_out_is_mov; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ftq_idx = mem_xcpt_uops_out_ftq_idx; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_edge_inst = mem_xcpt_uops_out_edge_inst; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_pc_lob = mem_xcpt_uops_out_pc_lob; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_taken = mem_xcpt_uops_out_taken; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_imm_rename = mem_xcpt_uops_out_imm_rename; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_imm_sel = mem_xcpt_uops_out_imm_sel; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_pimm = mem_xcpt_uops_out_pimm; // @[util.scala:104:23] wire [19:0] _mem_xcpt_uops_WIRE_0_imm_packed = mem_xcpt_uops_out_imm_packed; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_op1_sel = mem_xcpt_uops_out_op1_sel; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_op2_sel = mem_xcpt_uops_out_op2_sel; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ldst = mem_xcpt_uops_out_fp_ctrl_ldst; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_wen = mem_xcpt_uops_out_fp_ctrl_wen; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ren1 = mem_xcpt_uops_out_fp_ctrl_ren1; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ren2 = mem_xcpt_uops_out_fp_ctrl_ren2; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ren3 = mem_xcpt_uops_out_fp_ctrl_ren3; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_swap12 = mem_xcpt_uops_out_fp_ctrl_swap12; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_swap23 = mem_xcpt_uops_out_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_fp_ctrl_typeTagIn = mem_xcpt_uops_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_fp_ctrl_typeTagOut = mem_xcpt_uops_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_fromint = mem_xcpt_uops_out_fp_ctrl_fromint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_toint = mem_xcpt_uops_out_fp_ctrl_toint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_fastpipe = mem_xcpt_uops_out_fp_ctrl_fastpipe; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_fma = mem_xcpt_uops_out_fp_ctrl_fma; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_div = mem_xcpt_uops_out_fp_ctrl_div; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_sqrt = mem_xcpt_uops_out_fp_ctrl_sqrt; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_wflags = mem_xcpt_uops_out_fp_ctrl_wflags; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_vec = mem_xcpt_uops_out_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_rob_idx = mem_xcpt_uops_out_rob_idx; // @[util.scala:104:23] wire [3:0] _mem_xcpt_uops_WIRE_0_ldq_idx = mem_xcpt_uops_out_ldq_idx; // @[util.scala:104:23] wire [3:0] _mem_xcpt_uops_WIRE_0_stq_idx = mem_xcpt_uops_out_stq_idx; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_rxq_idx = mem_xcpt_uops_out_rxq_idx; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_pdst = mem_xcpt_uops_out_pdst; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs1 = mem_xcpt_uops_out_prs1; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs2 = mem_xcpt_uops_out_prs2; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs3 = mem_xcpt_uops_out_prs3; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ppred = mem_xcpt_uops_out_ppred; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_prs1_busy = mem_xcpt_uops_out_prs1_busy; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_prs2_busy = mem_xcpt_uops_out_prs2_busy; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_prs3_busy = mem_xcpt_uops_out_prs3_busy; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_ppred_busy = mem_xcpt_uops_out_ppred_busy; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_stale_pdst = mem_xcpt_uops_out_stale_pdst; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_exception = mem_xcpt_uops_out_exception; // @[util.scala:104:23] wire [63:0] _mem_xcpt_uops_WIRE_0_exc_cause = mem_xcpt_uops_out_exc_cause; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_mem_cmd = mem_xcpt_uops_out_mem_cmd; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_mem_size = mem_xcpt_uops_out_mem_size; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_mem_signed = mem_xcpt_uops_out_mem_signed; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_uses_ldq = mem_xcpt_uops_out_uses_ldq; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_uses_stq = mem_xcpt_uops_out_uses_stq; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_unique = mem_xcpt_uops_out_is_unique; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_flush_on_commit = mem_xcpt_uops_out_flush_on_commit; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_csr_cmd = mem_xcpt_uops_out_csr_cmd; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_ldst_is_rs1 = mem_xcpt_uops_out_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_ldst = mem_xcpt_uops_out_ldst; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs1 = mem_xcpt_uops_out_lrs1; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs2 = mem_xcpt_uops_out_lrs2; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs3 = mem_xcpt_uops_out_lrs3; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_dst_rtype = mem_xcpt_uops_out_dst_rtype; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs1_rtype = mem_xcpt_uops_out_lrs1_rtype; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs2_rtype = mem_xcpt_uops_out_lrs2_rtype; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_frs3_en = mem_xcpt_uops_out_frs3_en; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fcn_dw = mem_xcpt_uops_out_fcn_dw; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_fcn_op = mem_xcpt_uops_out_fcn_op; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_val = mem_xcpt_uops_out_fp_val; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_fp_rm = mem_xcpt_uops_out_fp_rm; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_fp_typ = mem_xcpt_uops_out_fp_typ; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_xcpt_pf_if = mem_xcpt_uops_out_xcpt_pf_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ae_if = mem_xcpt_uops_out_xcpt_ae_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ma_if = mem_xcpt_uops_out_xcpt_ma_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_bp_debug_if = mem_xcpt_uops_out_bp_debug_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_bp_xcpt_if = mem_xcpt_uops_out_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_debug_fsrc = mem_xcpt_uops_out_debug_fsrc; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_debug_tsrc = mem_xcpt_uops_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _mem_xcpt_uops_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _mem_xcpt_uops_out_br_mask_T_1 = exe_tlb_uop_0_br_mask & _mem_xcpt_uops_out_br_mask_T; // @[util.scala:93:{25,27}] assign mem_xcpt_uops_out_br_mask = _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg [31:0] mem_xcpt_uops_0_inst; // @[lsu.scala:799:32] assign mem_xcpt_uop_inst = mem_xcpt_uops_0_inst; // @[lsu.scala:459:29, :799:32] reg [31:0] mem_xcpt_uops_0_debug_inst; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_inst = mem_xcpt_uops_0_debug_inst; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_rvc; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_rvc = mem_xcpt_uops_0_is_rvc; // @[lsu.scala:459:29, :799:32] reg [39:0] mem_xcpt_uops_0_debug_pc; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_pc = mem_xcpt_uops_0_debug_pc; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_0; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_0 = mem_xcpt_uops_0_iq_type_0; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_1; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_1 = mem_xcpt_uops_0_iq_type_1; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_2; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_2 = mem_xcpt_uops_0_iq_type_2; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_3; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_3 = mem_xcpt_uops_0_iq_type_3; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_0; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_0 = mem_xcpt_uops_0_fu_code_0; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_1; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_1 = mem_xcpt_uops_0_fu_code_1; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_2; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_2 = mem_xcpt_uops_0_fu_code_2; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_3; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_3 = mem_xcpt_uops_0_fu_code_3; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_4; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_4 = mem_xcpt_uops_0_fu_code_4; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_5; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_5 = mem_xcpt_uops_0_fu_code_5; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_6; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_6 = mem_xcpt_uops_0_fu_code_6; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_7; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_7 = mem_xcpt_uops_0_fu_code_7; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_8; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_8 = mem_xcpt_uops_0_fu_code_8; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_9; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_9 = mem_xcpt_uops_0_fu_code_9; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_issued; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_issued = mem_xcpt_uops_0_iw_issued; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_issued_partial_agen; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_issued_partial_agen = mem_xcpt_uops_0_iw_issued_partial_agen; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_issued_partial_dgen; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_issued_partial_dgen = mem_xcpt_uops_0_iw_issued_partial_dgen; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_iw_p1_speculative_child; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p1_speculative_child = mem_xcpt_uops_0_iw_p1_speculative_child; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_iw_p2_speculative_child; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p2_speculative_child = mem_xcpt_uops_0_iw_p2_speculative_child; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_p1_bypass_hint; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p1_bypass_hint = mem_xcpt_uops_0_iw_p1_bypass_hint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_p2_bypass_hint; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p2_bypass_hint = mem_xcpt_uops_0_iw_p2_bypass_hint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_p3_bypass_hint; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p3_bypass_hint = mem_xcpt_uops_0_iw_p3_bypass_hint; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_dis_col_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_dis_col_sel = mem_xcpt_uops_0_dis_col_sel; // @[lsu.scala:459:29, :799:32] reg [11:0] mem_xcpt_uops_0_br_mask; // @[lsu.scala:799:32] assign mem_xcpt_uop_br_mask = mem_xcpt_uops_0_br_mask; // @[lsu.scala:459:29, :799:32] reg [3:0] mem_xcpt_uops_0_br_tag; // @[lsu.scala:799:32] assign mem_xcpt_uop_br_tag = mem_xcpt_uops_0_br_tag; // @[lsu.scala:459:29, :799:32] reg [3:0] mem_xcpt_uops_0_br_type; // @[lsu.scala:799:32] assign mem_xcpt_uop_br_type = mem_xcpt_uops_0_br_type; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_sfb; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_sfb = mem_xcpt_uops_0_is_sfb; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_fence; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_fence = mem_xcpt_uops_0_is_fence; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_fencei; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_fencei = mem_xcpt_uops_0_is_fencei; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_sfence; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_sfence = mem_xcpt_uops_0_is_sfence; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_amo; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_amo = mem_xcpt_uops_0_is_amo; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_eret; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_eret = mem_xcpt_uops_0_is_eret; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_sys_pc2epc = mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_rocc; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_rocc = mem_xcpt_uops_0_is_rocc; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_mov; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_mov = mem_xcpt_uops_0_is_mov; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_ftq_idx = mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_edge_inst; // @[lsu.scala:799:32] assign mem_xcpt_uop_edge_inst = mem_xcpt_uops_0_edge_inst; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_pc_lob; // @[lsu.scala:799:32] assign mem_xcpt_uop_pc_lob = mem_xcpt_uops_0_pc_lob; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_taken; // @[lsu.scala:799:32] assign mem_xcpt_uop_taken = mem_xcpt_uops_0_taken; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_imm_rename; // @[lsu.scala:799:32] assign mem_xcpt_uop_imm_rename = mem_xcpt_uops_0_imm_rename; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_imm_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_imm_sel = mem_xcpt_uops_0_imm_sel; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_pimm; // @[lsu.scala:799:32] assign mem_xcpt_uop_pimm = mem_xcpt_uops_0_pimm; // @[lsu.scala:459:29, :799:32] reg [19:0] mem_xcpt_uops_0_imm_packed; // @[lsu.scala:799:32] assign mem_xcpt_uop_imm_packed = mem_xcpt_uops_0_imm_packed; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_op1_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_op1_sel = mem_xcpt_uops_0_op1_sel; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_op2_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_op2_sel = mem_xcpt_uops_0_op2_sel; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ldst; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ldst = mem_xcpt_uops_0_fp_ctrl_ldst; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_wen; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_wen = mem_xcpt_uops_0_fp_ctrl_wen; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ren1; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ren1 = mem_xcpt_uops_0_fp_ctrl_ren1; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ren2; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ren2 = mem_xcpt_uops_0_fp_ctrl_ren2; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ren3; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ren3 = mem_xcpt_uops_0_fp_ctrl_ren3; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_swap12; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_swap12 = mem_xcpt_uops_0_fp_ctrl_swap12; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_swap23; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_swap23 = mem_xcpt_uops_0_fp_ctrl_swap23; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_fp_ctrl_typeTagIn; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_typeTagIn = mem_xcpt_uops_0_fp_ctrl_typeTagIn; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_fp_ctrl_typeTagOut; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_typeTagOut = mem_xcpt_uops_0_fp_ctrl_typeTagOut; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_fromint; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_fromint = mem_xcpt_uops_0_fp_ctrl_fromint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_toint; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_toint = mem_xcpt_uops_0_fp_ctrl_toint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_fastpipe; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_fastpipe = mem_xcpt_uops_0_fp_ctrl_fastpipe; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_fma; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_fma = mem_xcpt_uops_0_fp_ctrl_fma; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_div; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_div = mem_xcpt_uops_0_fp_ctrl_div; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_sqrt; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_sqrt = mem_xcpt_uops_0_fp_ctrl_sqrt; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_wflags; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_wflags = mem_xcpt_uops_0_fp_ctrl_wflags; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_vec; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_vec = mem_xcpt_uops_0_fp_ctrl_vec; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_rob_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_rob_idx = mem_xcpt_uops_0_rob_idx; // @[lsu.scala:459:29, :799:32] reg [3:0] mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_ldq_idx = mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:459:29, :799:32] reg [3:0] mem_xcpt_uops_0_stq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_stq_idx = mem_xcpt_uops_0_stq_idx; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_rxq_idx = mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_pdst; // @[lsu.scala:799:32] assign mem_xcpt_uop_pdst = mem_xcpt_uops_0_pdst; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_prs1; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs1 = mem_xcpt_uops_0_prs1; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_prs2; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs2 = mem_xcpt_uops_0_prs2; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_prs3; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs3 = mem_xcpt_uops_0_prs3; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_ppred; // @[lsu.scala:799:32] assign mem_xcpt_uop_ppred = mem_xcpt_uops_0_ppred; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs1_busy = mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs2_busy = mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs3_busy = mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_ppred_busy = mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:799:32] assign mem_xcpt_uop_stale_pdst = mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_exception; // @[lsu.scala:799:32] assign mem_xcpt_uop_exception = mem_xcpt_uops_0_exception; // @[lsu.scala:459:29, :799:32] reg [63:0] mem_xcpt_uops_0_exc_cause; // @[lsu.scala:799:32] assign mem_xcpt_uop_exc_cause = mem_xcpt_uops_0_exc_cause; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:799:32] assign mem_xcpt_uop_mem_cmd = mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_mem_size; // @[lsu.scala:799:32] assign mem_xcpt_uop_mem_size = mem_xcpt_uops_0_mem_size; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_mem_signed; // @[lsu.scala:799:32] assign mem_xcpt_uop_mem_signed = mem_xcpt_uops_0_mem_signed; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:799:32] assign mem_xcpt_uop_uses_ldq = mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_uses_stq; // @[lsu.scala:799:32] assign mem_xcpt_uop_uses_stq = mem_xcpt_uops_0_uses_stq; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_unique; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_unique = mem_xcpt_uops_0_is_unique; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:799:32] assign mem_xcpt_uop_flush_on_commit = mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_csr_cmd; // @[lsu.scala:799:32] assign mem_xcpt_uop_csr_cmd = mem_xcpt_uops_0_csr_cmd; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:799:32] assign mem_xcpt_uop_ldst_is_rs1 = mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_ldst; // @[lsu.scala:799:32] assign mem_xcpt_uop_ldst = mem_xcpt_uops_0_ldst; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_lrs1; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs1 = mem_xcpt_uops_0_lrs1; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_lrs2; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs2 = mem_xcpt_uops_0_lrs2; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_lrs3; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs3 = mem_xcpt_uops_0_lrs3; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:799:32] assign mem_xcpt_uop_dst_rtype = mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs1_rtype = mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs2_rtype = mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_frs3_en; // @[lsu.scala:799:32] assign mem_xcpt_uop_frs3_en = mem_xcpt_uops_0_frs3_en; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fcn_dw; // @[lsu.scala:799:32] assign mem_xcpt_uop_fcn_dw = mem_xcpt_uops_0_fcn_dw; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_fcn_op; // @[lsu.scala:799:32] assign mem_xcpt_uop_fcn_op = mem_xcpt_uops_0_fcn_op; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_val; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_val = mem_xcpt_uops_0_fp_val; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_fp_rm; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_rm = mem_xcpt_uops_0_fp_rm; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_fp_typ; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_typ = mem_xcpt_uops_0_fp_typ; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_xcpt_pf_if = mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_xcpt_ae_if = mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_xcpt_ma_if = mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_bp_debug_if = mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_bp_xcpt_if = mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_fsrc = mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_tsrc = mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:459:29, :799:32] wire [2:0] _mem_xcpt_causes_T = ae_ld_0 ? 3'h5 : 3'h0; // @[lsu.scala:321:49, :808:8] wire [2:0] _mem_xcpt_causes_T_1 = ae_st_0 ? 3'h7 : _mem_xcpt_causes_T; // @[lsu.scala:321:49, :807:8, :808:8] wire [3:0] _mem_xcpt_causes_T_2 = pf_ld_0 ? 4'hD : {1'h0, _mem_xcpt_causes_T_1}; // @[lsu.scala:321:49, :806:8, :807:8] wire [3:0] _mem_xcpt_causes_T_3 = pf_st_0 ? 4'hF : _mem_xcpt_causes_T_2; // @[lsu.scala:321:49, :805:8, :806:8] wire [3:0] _mem_xcpt_causes_T_4 = ma_ld_0 ? 4'h4 : _mem_xcpt_causes_T_3; // @[lsu.scala:321:49, :804:8, :805:8] wire [3:0] _mem_xcpt_causes_T_5 = ma_st_0 ? 4'h6 : _mem_xcpt_causes_T_4; // @[lsu.scala:321:49, :803:8, :804:8] wire [3:0] _mem_xcpt_causes_T_6 = _mem_xcpt_causes_T_5; // @[lsu.scala:802:8, :803:8] wire [3:0] _mem_xcpt_causes_T_7 = _mem_xcpt_causes_T_6; // @[lsu.scala:801:8, :802:8] wire [3:0] _mem_xcpt_causes_WIRE_0 = _mem_xcpt_causes_T_7; // @[lsu.scala:321:49, :801:8] reg [3:0] mem_xcpt_causes_0; // @[lsu.scala:800:32] assign mem_xcpt_cause = mem_xcpt_causes_0; // @[lsu.scala:458:29, :800:32] reg [63:0] mem_xcpt_vaddrs_0; // @[lsu.scala:810:32] assign mem_xcpt_vaddr = mem_xcpt_vaddrs_0; // @[lsu.scala:460:29, :810:32] wire _exe_tlb_miss_T_1; // @[lsu.scala:835:83] wire _exe_tlb_miss_T_2 = exe_tlb_valid_0 & _exe_tlb_miss_T_1; // @[lsu.scala:649:27, :835:{58,83}] wire exe_tlb_miss_0 = _exe_tlb_miss_T_2; // @[lsu.scala:321:49, :835:58] wire [19:0] _exe_tlb_paddr_T = _dtlb_io_resp_0_paddr[31:12]; // @[lsu.scala:308:20, :836:62] wire [11:0] _exe_tlb_paddr_T_1 = exe_tlb_vaddr_0[11:0]; // @[lsu.scala:321:49, :837:57] wire [31:0] _exe_tlb_paddr_T_2 = {_exe_tlb_paddr_T, _exe_tlb_paddr_T_1}; // @[lsu.scala:836:{40,62}, :837:57] wire [31:0] exe_tlb_paddr_0 = _exe_tlb_paddr_T_2; // @[lsu.scala:321:49, :836:40] wire _exe_tlb_uncacheable_T = ~_dtlb_io_resp_0_cacheable; // @[lsu.scala:308:20, :838:43] wire exe_tlb_uncacheable_0 = _exe_tlb_uncacheable_T; // @[lsu.scala:321:49, :838:43] reg REG; // @[lsu.scala:845:21] wire [11:0] _exe_agen_killed_T = io_core_brupdate_b1_mispredict_mask_0 & io_core_agen_0_bits_uop_br_mask_0; // @[util.scala:126:51] wire _exe_agen_killed_T_1 = |_exe_agen_killed_T; // @[util.scala:126:{51,59}] wire _exe_agen_killed_T_2 = _exe_agen_killed_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire exe_agen_killed_0 = _exe_agen_killed_T_2; // @[util.scala:61:61] assign io_dmem_req_valid_0 = dmem_req_0_valid; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_valid_0 = dmem_req_0_valid; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_inst_0 = dmem_req_0_bits_uop_inst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_inst_0 = dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_rvc_0 = dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_pc_0 = dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_0_0 = dmem_req_0_bits_uop_iq_type_0; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_1_0 = dmem_req_0_bits_uop_iq_type_1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_2_0 = dmem_req_0_bits_uop_iq_type_2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_3_0 = dmem_req_0_bits_uop_iq_type_3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_0_0 = dmem_req_0_bits_uop_fu_code_0; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_1_0 = dmem_req_0_bits_uop_fu_code_1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_2_0 = dmem_req_0_bits_uop_fu_code_2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_3_0 = dmem_req_0_bits_uop_fu_code_3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_4_0 = dmem_req_0_bits_uop_fu_code_4; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_5_0 = dmem_req_0_bits_uop_fu_code_5; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_6_0 = dmem_req_0_bits_uop_fu_code_6; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_7_0 = dmem_req_0_bits_uop_fu_code_7; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_8_0 = dmem_req_0_bits_uop_fu_code_8; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_9_0 = dmem_req_0_bits_uop_fu_code_9; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_issued_0 = dmem_req_0_bits_uop_iw_issued; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen_0 = dmem_req_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen_0 = dmem_req_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child_0 = dmem_req_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child_0 = dmem_req_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint_0 = dmem_req_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint_0 = dmem_req_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint_0 = dmem_req_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_dis_col_sel_0 = dmem_req_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_br_mask_0 = dmem_req_0_bits_uop_br_mask; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_br_tag_0 = dmem_req_0_bits_uop_br_tag; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_br_type_0 = dmem_req_0_bits_uop_br_type; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_sfb_0 = dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_fence_0 = dmem_req_0_bits_uop_is_fence; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_fencei_0 = dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_sfence_0 = dmem_req_0_bits_uop_is_sfence; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_amo_0 = dmem_req_0_bits_uop_is_amo; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_eret_0 = dmem_req_0_bits_uop_is_eret; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0 = dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_rocc_0 = dmem_req_0_bits_uop_is_rocc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_mov_0 = dmem_req_0_bits_uop_is_mov; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ftq_idx_0 = dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_edge_inst_0 = dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_pc_lob_0 = dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_taken_0 = dmem_req_0_bits_uop_taken; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_imm_rename_0 = dmem_req_0_bits_uop_imm_rename; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_imm_sel_0 = dmem_req_0_bits_uop_imm_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_pimm_0 = dmem_req_0_bits_uop_pimm; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_imm_packed_0 = dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_op1_sel_0 = dmem_req_0_bits_uop_op1_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_op2_sel_0 = dmem_req_0_bits_uop_op2_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst_0 = dmem_req_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_wen_0 = dmem_req_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1_0 = dmem_req_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2_0 = dmem_req_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3_0 = dmem_req_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12_0 = dmem_req_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23_0 = dmem_req_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn_0 = dmem_req_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut_0 = dmem_req_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint_0 = dmem_req_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_toint_0 = dmem_req_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe_0 = dmem_req_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_fma_0 = dmem_req_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_div_0 = dmem_req_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt_0 = dmem_req_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags_0 = dmem_req_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_vec_0 = dmem_req_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_rob_idx_0 = dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ldq_idx_0 = dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_stq_idx_0 = dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_rxq_idx_0 = dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_pdst_0 = dmem_req_0_bits_uop_pdst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs1_0 = dmem_req_0_bits_uop_prs1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs2_0 = dmem_req_0_bits_uop_prs2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs3_0 = dmem_req_0_bits_uop_prs3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ppred_0 = dmem_req_0_bits_uop_ppred; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs1_busy_0 = dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs2_busy_0 = dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs3_busy_0 = dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ppred_busy_0 = dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_stale_pdst_0 = dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_exception_0 = dmem_req_0_bits_uop_exception; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_exc_cause_0 = dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_mem_cmd_0 = dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_mem_size_0 = dmem_req_0_bits_uop_mem_size; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_mem_signed_0 = dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_uses_ldq_0 = dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_uses_stq_0 = dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_unique_0 = dmem_req_0_bits_uop_is_unique; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_flush_on_commit_0 = dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_csr_cmd_0 = dmem_req_0_bits_uop_csr_cmd; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0 = dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ldst_0 = dmem_req_0_bits_uop_ldst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs1_0 = dmem_req_0_bits_uop_lrs1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs2_0 = dmem_req_0_bits_uop_lrs2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs3_0 = dmem_req_0_bits_uop_lrs3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_dst_rtype_0 = dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs1_rtype_0 = dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs2_rtype_0 = dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_frs3_en_0 = dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fcn_dw_0 = dmem_req_0_bits_uop_fcn_dw; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fcn_op_0 = dmem_req_0_bits_uop_fcn_op; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_val_0 = dmem_req_0_bits_uop_fp_val; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_rm_0 = dmem_req_0_bits_uop_fp_rm; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_typ_0 = dmem_req_0_bits_uop_fp_typ; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0 = dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0 = dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0 = dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_bp_debug_if_0 = dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0 = dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_fsrc_0 = dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_tsrc_0 = dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_addr_0 = dmem_req_0_bits_addr; // @[lsu.scala:211:7, :877:22] wire [39:0] _mem_paddr_WIRE_0 = dmem_req_0_bits_addr; // @[lsu.scala:321:49, :877:22] assign io_dmem_req_bits_0_bits_data_0 = dmem_req_0_bits_data; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_is_hella_0 = dmem_req_0_bits_is_hella; // @[lsu.scala:211:7, :877:22] wire _dmem_req_fire_T = io_dmem_req_ready_0 & io_dmem_req_valid_0; // @[Decoupled.scala:51:35] wire _dmem_req_fire_T_1 = dmem_req_0_valid & _dmem_req_fire_T; // @[Decoupled.scala:51:35] wire dmem_req_fire_0 = _dmem_req_fire_T_1; // @[lsu.scala:321:49, :880:55] wire s0_executing_loads_0; // @[lsu.scala:882:36] wire s0_executing_loads_1; // @[lsu.scala:882:36] wire s0_executing_loads_2; // @[lsu.scala:882:36] wire s0_executing_loads_3; // @[lsu.scala:882:36] wire s0_executing_loads_4; // @[lsu.scala:882:36] wire s0_executing_loads_5; // @[lsu.scala:882:36] wire s0_executing_loads_6; // @[lsu.scala:882:36] wire s0_executing_loads_7; // @[lsu.scala:882:36] wire s0_executing_loads_8; // @[lsu.scala:882:36] wire s0_executing_loads_9; // @[lsu.scala:882:36] wire s0_executing_loads_10; // @[lsu.scala:882:36] wire s0_executing_loads_11; // @[lsu.scala:882:36] wire s0_executing_loads_12; // @[lsu.scala:882:36] wire s0_executing_loads_13; // @[lsu.scala:882:36] wire s0_executing_loads_14; // @[lsu.scala:882:36] wire s0_executing_loads_15; // @[lsu.scala:882:36] wire s0_kills_0; // @[lsu.scala:883:22] wire _io_dmem_s1_kill_0_T = s0_kills_0 & dmem_req_fire_0; // @[lsu.scala:321:49, :883:22, :893:47] reg io_dmem_s1_kill_0_REG; // @[lsu.scala:893:34] wire [39:0] _GEN_383 = {8'h0, exe_tlb_paddr_0}; // @[lsu.scala:321:49, :897:30] wire _GEN_384 = exe_tlb_miss_0 | exe_tlb_uncacheable_0; // @[lsu.scala:321:49, :900:49] wire _s0_kills_0_T; // @[lsu.scala:900:49] assign _s0_kills_0_T = _GEN_384; // @[lsu.scala:900:49] wire _s0_kills_0_T_4; // @[lsu.scala:909:38] assign _s0_kills_0_T_4 = _GEN_384; // @[lsu.scala:900:49, :909:38] wire _s0_kills_0_T_1 = _s0_kills_0_T | ma_ld_0; // @[lsu.scala:321:49, :900:{49,75}] wire _s0_kills_0_T_2 = _s0_kills_0_T_1 | ae_ld_0; // @[lsu.scala:321:49, :900:{75,87}] wire _s0_kills_0_T_3 = _s0_kills_0_T_2 | pf_ld_0; // @[lsu.scala:321:49, :900:{87,99}] wire _s0_executing_loads_T = ~s0_kills_0; // @[lsu.scala:883:22, :901:70] wire _s0_executing_loads_T_1 = dmem_req_fire_0 & _s0_executing_loads_T; // @[lsu.scala:321:49, :901:{67,70}] wire _s0_kills_0_T_5 = _s0_kills_0_T_4 | ma_ld_0; // @[lsu.scala:321:49, :909:{38,64}] wire _s0_kills_0_T_6 = _s0_kills_0_T_5 | ae_ld_0; // @[lsu.scala:321:49, :909:{64,76}] wire _s0_kills_0_T_7 = _s0_kills_0_T_6 | pf_ld_0; // @[lsu.scala:321:49, :909:{76,88}] assign s0_kills_0 = will_fire_load_agen_exec_0 ? _s0_kills_0_T_3 : will_fire_load_retry_0 & _s0_kills_0_T_7; // @[lsu.scala:469:39, :476:41, :883:22, :892:17, :895:40, :900:{30,99}, :904:43, :909:{19,88}] wire _s0_executing_loads_T_2 = ~s0_kills_0; // @[lsu.scala:883:22, :901:70, :910:64] wire _s0_executing_loads_T_3 = dmem_req_fire_0 & _s0_executing_loads_T_2; // @[lsu.scala:321:49, :910:{61,64}] wire [1:0] dmem_req_0_bits_data_size; // @[AMOALU.scala:11:18] wire _dmem_req_0_bits_data_T = dmem_req_0_bits_data_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _dmem_req_0_bits_data_T_1 = _stq_execute_queue_io_deq_bits_data_bits[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_2 = {2{_dmem_req_0_bits_data_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_3 = {2{_dmem_req_0_bits_data_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_4 = {2{_dmem_req_0_bits_data_T_3}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_5 = dmem_req_0_bits_data_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _dmem_req_0_bits_data_T_6 = _stq_execute_queue_io_deq_bits_data_bits[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_7 = {2{_dmem_req_0_bits_data_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_8 = {2{_dmem_req_0_bits_data_T_7}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_9 = dmem_req_0_bits_data_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _dmem_req_0_bits_data_T_10 = _stq_execute_queue_io_deq_bits_data_bits[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_11 = {2{_dmem_req_0_bits_data_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_12 = _dmem_req_0_bits_data_T_9 ? _dmem_req_0_bits_data_T_11 : _stq_execute_queue_io_deq_bits_data_bits; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_13 = _dmem_req_0_bits_data_T_5 ? _dmem_req_0_bits_data_T_8 : _dmem_req_0_bits_data_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_14 = _dmem_req_0_bits_data_T ? _dmem_req_0_bits_data_T_4 : _dmem_req_0_bits_data_T_13; // @[AMOALU.scala:29:{13,19,32}] wire _GEN_385 = will_fire_load_agen_exec_0 | will_fire_load_retry_0; // @[lsu.scala:469:39, :476:41, :556:41, :895:40, :904:43, :911:84] assign dmem_req_0_bits_uop_inst = _GEN_385 ? exe_tlb_uop_0_inst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_inst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_inst = _GEN_385 ? exe_tlb_uop_0_debug_inst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_debug_inst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_rvc = _GEN_385 ? exe_tlb_uop_0_is_rvc : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_rvc : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_pc = _GEN_385 ? exe_tlb_uop_0_debug_pc : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_debug_pc : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_0 = _GEN_385 ? exe_tlb_uop_0_iq_type_0 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iq_type_0 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_1 = _GEN_385 ? exe_tlb_uop_0_iq_type_1 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iq_type_1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_2 = _GEN_385 ? exe_tlb_uop_0_iq_type_2 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iq_type_2 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_2; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_3 = _GEN_385 ? exe_tlb_uop_0_iq_type_3 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iq_type_3 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_3; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_0 = _GEN_385 ? exe_tlb_uop_0_fu_code_0 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_0 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_1 = _GEN_385 ? exe_tlb_uop_0_fu_code_1 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_2 = _GEN_385 ? exe_tlb_uop_0_fu_code_2 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_2 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_2; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_3 = _GEN_385 ? exe_tlb_uop_0_fu_code_3 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_3 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_3; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_4 = _GEN_385 ? exe_tlb_uop_0_fu_code_4 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_4 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_4; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_5 = _GEN_385 ? exe_tlb_uop_0_fu_code_5 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_5 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_5; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_6 = _GEN_385 ? exe_tlb_uop_0_fu_code_6 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_6 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_6; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_7 = _GEN_385 ? exe_tlb_uop_0_fu_code_7 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_7 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_7; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_8 = _GEN_385 ? exe_tlb_uop_0_fu_code_8 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_8 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_8; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_9 = _GEN_385 ? exe_tlb_uop_0_fu_code_9 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fu_code_9 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_9; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_issued = _GEN_385 ? exe_tlb_uop_0_iw_issued : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_issued : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_issued; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_issued_partial_agen = _GEN_385 ? exe_tlb_uop_0_iw_issued_partial_agen : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_agen : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_issued_partial_dgen = _GEN_385 ? exe_tlb_uop_0_iw_issued_partial_dgen : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_dgen : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p1_speculative_child = _GEN_385 ? exe_tlb_uop_0_iw_p1_speculative_child : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_p1_speculative_child : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_iw_p1_speculative_child : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p2_speculative_child = _GEN_385 ? exe_tlb_uop_0_iw_p2_speculative_child : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_p2_speculative_child : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_iw_p2_speculative_child : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p1_bypass_hint = _GEN_385 ? exe_tlb_uop_0_iw_p1_bypass_hint : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_p1_bypass_hint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p2_bypass_hint = _GEN_385 ? exe_tlb_uop_0_iw_p2_bypass_hint : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_p2_bypass_hint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p3_bypass_hint = _GEN_385 ? exe_tlb_uop_0_iw_p3_bypass_hint : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_iw_p3_bypass_hint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_dis_col_sel = _GEN_385 ? exe_tlb_uop_0_dis_col_sel : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_dis_col_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_dis_col_sel : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_br_mask = _GEN_385 ? exe_tlb_uop_0_br_mask : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_br_mask : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_br_mask : 12'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_br_tag = _GEN_385 ? exe_tlb_uop_0_br_tag : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_br_tag : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_br_type = _GEN_385 ? exe_tlb_uop_0_br_type : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_br_type : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_sfb = _GEN_385 ? exe_tlb_uop_0_is_sfb : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_sfb : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_fence = _GEN_385 ? exe_tlb_uop_0_is_fence : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_fence : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_fencei = _GEN_385 ? exe_tlb_uop_0_is_fencei : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_fencei : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_sfence = _GEN_385 ? exe_tlb_uop_0_is_sfence : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_sfence : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_sfence; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_amo = _GEN_385 ? exe_tlb_uop_0_is_amo : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_amo : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_eret = _GEN_385 ? exe_tlb_uop_0_is_eret : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_eret : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_eret; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_sys_pc2epc = _GEN_385 ? exe_tlb_uop_0_is_sys_pc2epc : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_sys_pc2epc : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_rocc = _GEN_385 ? exe_tlb_uop_0_is_rocc : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_rocc : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_rocc; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_mov = _GEN_385 ? exe_tlb_uop_0_is_mov : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_mov : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_mov; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ftq_idx = _GEN_385 ? exe_tlb_uop_0_ftq_idx : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_ftq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_edge_inst = _GEN_385 ? exe_tlb_uop_0_edge_inst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_edge_inst : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_pc_lob = _GEN_385 ? exe_tlb_uop_0_pc_lob : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_pc_lob : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_taken = _GEN_385 ? exe_tlb_uop_0_taken : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_taken : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_imm_rename = _GEN_385 ? exe_tlb_uop_0_imm_rename : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_imm_rename : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_imm_rename; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_imm_sel = _GEN_385 ? exe_tlb_uop_0_imm_sel : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_imm_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_pimm = _GEN_385 ? exe_tlb_uop_0_pimm : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_pimm : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_imm_packed = _GEN_385 ? exe_tlb_uop_0_imm_packed : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_imm_packed : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_op1_sel = _GEN_385 ? exe_tlb_uop_0_op1_sel : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_op1_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_op2_sel = _GEN_385 ? exe_tlb_uop_0_op2_sel : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_op2_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ldst = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_ldst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ldst : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_wen = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_wen : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wen : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ren1 = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_ren1 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ren2 = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_ren2 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren2 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ren3 = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_ren3 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren3 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_swap12 = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_swap12 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap12 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_swap23 = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_swap23 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap23 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_typeTagIn = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_typeTagIn : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagIn : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_typeTagOut = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_typeTagOut : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagOut : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_fromint = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_fromint : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fromint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_toint = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_toint : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_toint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_fastpipe = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_fastpipe : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fastpipe : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_fma = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_fma : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fma : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_div = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_div : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_div : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_sqrt = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_sqrt : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_sqrt : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_wflags = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_wflags : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wflags : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_vec = _GEN_385 ? exe_tlb_uop_0_fp_ctrl_vec : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_vec : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_rob_idx = _GEN_385 ? exe_tlb_uop_0_rob_idx : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_rob_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_rob_idx : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ldq_idx = _GEN_385 ? exe_tlb_uop_0_ldq_idx : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_ldq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ldq_idx : 4'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_stq_idx = _GEN_385 ? exe_tlb_uop_0_stq_idx : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_stq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_stq_idx : 4'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_rxq_idx = _GEN_385 ? exe_tlb_uop_0_rxq_idx : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_rxq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_pdst = _GEN_385 ? exe_tlb_uop_0_pdst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_pdst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs1 = _GEN_385 ? exe_tlb_uop_0_prs1 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_prs1 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs2 = _GEN_385 ? exe_tlb_uop_0_prs2 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_prs2 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs3 = _GEN_385 ? exe_tlb_uop_0_prs3 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_prs3 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ppred = _GEN_385 ? exe_tlb_uop_0_ppred : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_ppred : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs1_busy = _GEN_385 ? exe_tlb_uop_0_prs1_busy : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_prs1_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs2_busy = _GEN_385 ? exe_tlb_uop_0_prs2_busy : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_prs2_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs3_busy = _GEN_385 ? exe_tlb_uop_0_prs3_busy : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_prs3_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ppred_busy = _GEN_385 ? exe_tlb_uop_0_ppred_busy : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_ppred_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_stale_pdst = _GEN_385 ? exe_tlb_uop_0_stale_pdst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_stale_pdst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_exception = _GEN_385 ? exe_tlb_uop_0_exception : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_exception : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_exc_cause = _GEN_385 ? exe_tlb_uop_0_exc_cause : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_exc_cause : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_uses_ldq = _GEN_385 ? exe_tlb_uop_0_uses_ldq : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_uses_ldq : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_uses_stq = _GEN_385 ? exe_tlb_uop_0_uses_stq : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_uses_stq : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_unique = _GEN_385 ? exe_tlb_uop_0_is_unique : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_is_unique : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_flush_on_commit = _GEN_385 ? exe_tlb_uop_0_flush_on_commit : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_flush_on_commit : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_csr_cmd = _GEN_385 ? exe_tlb_uop_0_csr_cmd : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_csr_cmd : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ldst_is_rs1 = _GEN_385 ? exe_tlb_uop_0_ldst_is_rs1 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_ldst_is_rs1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ldst = _GEN_385 ? exe_tlb_uop_0_ldst : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_ldst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs1 = _GEN_385 ? exe_tlb_uop_0_lrs1 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_lrs1 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs2 = _GEN_385 ? exe_tlb_uop_0_lrs2 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_lrs2 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs3 = _GEN_385 ? exe_tlb_uop_0_lrs3 : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_lrs3 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_dst_rtype = _GEN_385 ? exe_tlb_uop_0_dst_rtype : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_dst_rtype : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs1_rtype = _GEN_385 ? exe_tlb_uop_0_lrs1_rtype : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_lrs1_rtype : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs2_rtype = _GEN_385 ? exe_tlb_uop_0_lrs2_rtype : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_lrs2_rtype : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_frs3_en = _GEN_385 ? exe_tlb_uop_0_frs3_en : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_frs3_en : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fcn_dw = _GEN_385 ? exe_tlb_uop_0_fcn_dw : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fcn_dw : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fcn_dw; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fcn_op = _GEN_385 ? exe_tlb_uop_0_fcn_op : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fcn_op : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_val = _GEN_385 ? exe_tlb_uop_0_fp_val : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_val : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_rm = _GEN_385 ? exe_tlb_uop_0_fp_rm : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_rm : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_typ = _GEN_385 ? exe_tlb_uop_0_fp_typ : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_fp_typ : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_xcpt_pf_if = _GEN_385 ? exe_tlb_uop_0_xcpt_pf_if : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_xcpt_pf_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_xcpt_ae_if = _GEN_385 ? exe_tlb_uop_0_xcpt_ae_if : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_xcpt_ae_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_xcpt_ma_if = _GEN_385 ? exe_tlb_uop_0_xcpt_ma_if : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_xcpt_ma_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_bp_debug_if = _GEN_385 ? exe_tlb_uop_0_bp_debug_if : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_bp_debug_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_bp_xcpt_if = _GEN_385 ? exe_tlb_uop_0_bp_xcpt_if : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_bp_xcpt_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_fsrc = _GEN_385 ? exe_tlb_uop_0_debug_fsrc : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_debug_fsrc : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_tsrc = _GEN_385 ? exe_tlb_uop_0_debug_tsrc : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_debug_tsrc : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign s0_executing_loads_0 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h0 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_368 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_353 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_1 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h1 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_369 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_354 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_2 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h2 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_370 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_355 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_3 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h3 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_371 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_356 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_4 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h4 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_372 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_357 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_5 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h5 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_373 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_358 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_6 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h6 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_374 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_359 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_7 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h7 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_375 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_360 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_8 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h8 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_376 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_361 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_9 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'h9 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_377 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_362 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_10 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'hA & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_378 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_363 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_11 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'hB & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_379 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_364 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_12 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'hC & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_380 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_365 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_13 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'hD & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_381 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_366 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_14 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 4'hE & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_382 & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & _GEN_367 & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_15 = will_fire_load_agen_exec_0 ? (&ldq_incoming_idx_0) & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? (&_retry_queue_io_deq_bits_uop_ldq_idx) & _s0_executing_loads_T_3 : ~_T_1139 & will_fire_load_wakeup_0 & (&ldq_wakeup_idx) & dmem_req_fire_0; // @[lsu.scala:321:49, :469:39, :476:41, :480:41, :506:31, :533:27, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] wire _dmem_req_0_valid_T = ~io_hellacache_s1_kill_0; // @[lsu.scala:211:7, :937:42] wire _dmem_req_0_valid_T_3 = _dmem_req_0_valid_T; // @[lsu.scala:937:{42,65}] wire _dmem_req_0_valid_T_1 = ~exe_tlb_miss_0; // @[lsu.scala:321:49, :937:69] wire _GEN_386 = will_fire_load_agen_exec_0 | will_fire_load_retry_0 | _T_1139 | will_fire_load_wakeup_0; // @[lsu.scala:304:34, :469:39, :476:41, :480:41, :565:78, :895:40, :904:43, :911:84, :926:44, :934:47] assign dmem_req_0_valid = _GEN_386 | (will_fire_hella_incoming_0 ? _dmem_req_0_valid_T_3 : will_fire_hella_wakeup_0); // @[lsu.scala:304:34, :473:41, :474:41, :877:22, :895:40, :896:30, :904:43, :905:30, :911:84, :912:33, :926:44, :927:30, :934:47, :937:{39,65}, :951:5] assign dmem_req_0_bits_addr = will_fire_load_agen_exec_0 | will_fire_load_retry_0 ? _GEN_383 : _T_1139 ? _stq_execute_queue_io_deq_bits_addr_bits : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_addr_bits : will_fire_hella_incoming_0 ? _GEN_383 : will_fire_hella_wakeup_0 ? {8'h0, hella_paddr} : 40'h0; // @[lsu.scala:304:34, :469:39, :473:41, :474:41, :476:41, :480:41, :510:32, :558:11, :565:78, :877:22, :888:28, :895:40, :897:30, :904:43, :911:84, :913:33, :926:44, :928:30, :934:47, :938:39, :951:5, :954:39] wire [7:0] _dmem_req_0_bits_data_T_31 = hella_data_data[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_32 = {2{_dmem_req_0_bits_data_T_31}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_33 = {2{_dmem_req_0_bits_data_T_32}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_34 = {2{_dmem_req_0_bits_data_T_33}}; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_36 = hella_data_data[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_37 = {2{_dmem_req_0_bits_data_T_36}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_38 = {2{_dmem_req_0_bits_data_T_37}}; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_40 = hella_data_data[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_41 = {2{_dmem_req_0_bits_data_T_40}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_43 = _dmem_req_0_bits_data_T_42; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_44 = _dmem_req_0_bits_data_T_43; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_data = _GEN_385 ? 64'h0 : _T_1139 ? _dmem_req_0_bits_data_T_14 : will_fire_load_wakeup_0 | will_fire_hella_incoming_0 | ~will_fire_hella_wakeup_0 ? 64'h0 : _dmem_req_0_bits_data_T_44; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_uop_mem_cmd = _GEN_385 ? exe_tlb_uop_0_mem_cmd : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_mem_cmd : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30, :934:47] assign dmem_req_0_bits_uop_mem_size = _GEN_385 ? exe_tlb_uop_0_mem_size : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_mem_size : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_mem_size : {2{will_fire_hella_incoming_0 | will_fire_hella_wakeup_0}}; // @[lsu.scala:321:49, :473:41, :474:41, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30, :934:47, :944:39, :951:5, :960:39] assign dmem_req_0_bits_uop_mem_signed = _GEN_385 ? exe_tlb_uop_0_mem_signed : _T_1139 ? _stq_execute_queue_io_deq_bits_uop_mem_signed : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30, :934:47] assign dmem_req_0_bits_is_hella = ~_GEN_386 & (will_fire_hella_incoming_0 | will_fire_hella_wakeup_0); // @[lsu.scala:304:34, :473:41, :474:41, :877:22, :890:31, :895:40, :904:43, :911:84, :926:44, :934:47, :946:39, :951:5] wire _T_183 = _T_182 | will_fire_load_retry_0; // @[lsu.scala:476:41, :687:61, :967:65] wire [3:0] ldq_idx = _ldq_idx_T ? ldq_incoming_idx_0 : _retry_queue_io_deq_bits_uop_ldq_idx; // @[lsu.scala:321:49, :533:27, :969:{24,48}] wire _ldq_addr_valid_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50] wire _ldq_addr_valid_T_1 = _ldq_addr_valid_T | will_fire_load_retry_0; // @[lsu.scala:476:41, :970:{50,70}] wire [63:0] _GEN_387 = exe_tlb_miss_0 ? exe_tlb_vaddr_0 : {32'h0, exe_tlb_paddr_0}; // @[lsu.scala:321:49, :971:53] wire [63:0] _ldq_addr_bits_T; // @[lsu.scala:971:53] assign _ldq_addr_bits_T = _GEN_387; // @[lsu.scala:971:53] wire [63:0] _stq_addr_bits_T; // @[lsu.scala:987:48] assign _stq_addr_bits_T = _GEN_387; // @[lsu.scala:971:53, :987:48] wire [7:0] ldq_ld_byte_mask_mask; // @[lsu.scala:1951:22] wire _ldq_ld_byte_mask_mask_T = exe_tlb_uop_0_mem_size == 2'h0; // @[lsu.scala:321:49, :1953:26] wire [2:0] _ldq_ld_byte_mask_mask_T_1 = exe_tlb_vaddr_0[2:0]; // @[lsu.scala:321:49, :1953:55] wire [14:0] _ldq_ld_byte_mask_mask_T_2 = 15'h1 << _ldq_ld_byte_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _ldq_ld_byte_mask_mask_T_3 = exe_tlb_uop_0_mem_size == 2'h1; // @[lsu.scala:321:49, :1954:26] wire [1:0] _ldq_ld_byte_mask_mask_T_4 = exe_tlb_vaddr_0[2:1]; // @[lsu.scala:321:49, :1954:56] wire [2:0] _ldq_ld_byte_mask_mask_T_5 = {_ldq_ld_byte_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _ldq_ld_byte_mask_mask_T_6 = 15'h3 << _ldq_ld_byte_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _ldq_ld_byte_mask_mask_T_7 = exe_tlb_uop_0_mem_size == 2'h2; // @[lsu.scala:321:49, :1955:26] wire _ldq_ld_byte_mask_mask_T_8 = exe_tlb_vaddr_0[2]; // @[lsu.scala:321:49, :1955:46] wire [7:0] _ldq_ld_byte_mask_mask_T_9 = _ldq_ld_byte_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _ldq_ld_byte_mask_mask_T_10 = &exe_tlb_uop_0_mem_size; // @[lsu.scala:321:49, :1956:26] wire [7:0] _ldq_ld_byte_mask_mask_T_12 = _ldq_ld_byte_mask_mask_T_7 ? _ldq_ld_byte_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _ldq_ld_byte_mask_mask_T_13 = _ldq_ld_byte_mask_mask_T_3 ? _ldq_ld_byte_mask_mask_T_6 : {7'h0, _ldq_ld_byte_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _ldq_ld_byte_mask_mask_T_14 = _ldq_ld_byte_mask_mask_T ? _ldq_ld_byte_mask_mask_T_2 : _ldq_ld_byte_mask_mask_T_13; // @[Mux.scala:126:16] assign ldq_ld_byte_mask_mask = _ldq_ld_byte_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _ldq_addr_is_uncacheable_T = ~exe_tlb_miss_0; // @[lsu.scala:321:49, :937:69, :975:76] wire _ldq_addr_is_uncacheable_T_1 = exe_tlb_uncacheable_0 & _ldq_addr_is_uncacheable_T; // @[lsu.scala:321:49, :975:{73,76}] wire _T_188 = will_fire_store_agen_0 | will_fire_store_retry_0; // @[lsu.scala:471:41, :477:41, :981:35] wire [3:0] stq_idx = will_fire_store_agen_0 ? stq_incoming_idx_0 : _retry_queue_io_deq_bits_uop_stq_idx; // @[lsu.scala:321:49, :471:41, :533:27, :983:24] wire _stq_addr_valid_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :986:46] wire _stq_addr_valid_T_1 = _stq_addr_valid_T | will_fire_store_retry_0; // @[lsu.scala:477:41, :986:{46,66}] wire _stq_addr_valid_T_2 = ~pf_st_0; // @[lsu.scala:321:49, :986:98] wire _stq_addr_valid_T_3 = _stq_addr_valid_T_1 & _stq_addr_valid_T_2; // @[lsu.scala:986:{66,95,98}] wire slow_wakeups_0_valid; // @[lsu.scala:1495:26] wire _fired_load_agen_exec_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :1041:83] wire _fired_load_agen_exec_T_1 = will_fire_load_agen_exec_0 & _fired_load_agen_exec_T; // @[lsu.scala:469:39, :1041:{80,83}] reg fired_load_agen_exec_REG; // @[lsu.scala:1041:51] wire fired_load_agen_exec_0 = fired_load_agen_exec_REG; // @[lsu.scala:321:49, :1041:51] wire _fired_load_agen_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :1042:83] wire _fired_load_agen_T_1 = will_fire_load_agen_0 & _fired_load_agen_T; // @[lsu.scala:470:41, :1042:{80,83}] reg fired_load_agen_REG; // @[lsu.scala:1042:51] wire fired_load_agen_0 = fired_load_agen_REG; // @[lsu.scala:321:49, :1042:51] wire _fired_store_agen_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :1043:83] wire _fired_store_agen_T_1 = will_fire_store_agen_0 & _fired_store_agen_T; // @[lsu.scala:471:41, :1043:{80,83}] reg fired_store_agen_REG; // @[lsu.scala:1043:51] wire fired_store_agen_0 = fired_store_agen_REG; // @[lsu.scala:321:49, :1043:51] reg fired_sfence_0; // @[lsu.scala:1044:37] reg fired_release_0; // @[lsu.scala:1045:37] wire do_release_search_0 = fired_release_0; // @[lsu.scala:321:49, :1045:37] wire lcam_is_release_0 = fired_release_0; // @[lsu.scala:321:49, :1045:37] wire [11:0] _GEN_388 = io_core_brupdate_b1_mispredict_mask_0 & _retry_queue_io_deq_bits_uop_br_mask; // @[util.scala:126:51] wire [11:0] _fired_load_retry_T; // @[util.scala:126:51] assign _fired_load_retry_T = _GEN_388; // @[util.scala:126:51] wire [11:0] _fired_store_retry_T; // @[util.scala:126:51] assign _fired_store_retry_T = _GEN_388; // @[util.scala:126:51] wire _fired_load_retry_T_1 = |_fired_load_retry_T; // @[util.scala:126:{51,59}] wire _fired_load_retry_T_2 = _fired_load_retry_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _fired_load_retry_T_3 = ~_fired_load_retry_T_2; // @[util.scala:61:61] wire _fired_load_retry_T_4 = will_fire_load_retry_0 & _fired_load_retry_T_3; // @[lsu.scala:476:41, :1046:{79,82}] reg fired_load_retry_REG; // @[lsu.scala:1046:51] wire fired_load_retry_0 = fired_load_retry_REG; // @[lsu.scala:321:49, :1046:51] wire _fired_store_retry_T_1 = |_fired_store_retry_T; // @[util.scala:126:{51,59}] wire _fired_store_retry_T_2 = _fired_store_retry_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _fired_store_retry_T_3 = ~_fired_store_retry_T_2; // @[util.scala:61:61] wire _fired_store_retry_T_4 = will_fire_store_retry_0 & _fired_store_retry_T_3; // @[lsu.scala:477:41, :1047:{79,82}] reg fired_store_retry_REG; // @[lsu.scala:1047:51] wire fired_store_retry_0 = fired_store_retry_REG; // @[lsu.scala:321:49, :1047:51] reg fired_store_commit_REG; // @[lsu.scala:1048:51] wire fired_store_commit_0 = fired_store_commit_REG; // @[lsu.scala:321:49, :1048:51] wire [11:0] _GEN_389 = io_core_brupdate_b1_mispredict_mask_0 & ldq_wakeup_e_bits_uop_br_mask; // @[util.scala:126:51] wire [11:0] _fired_load_wakeup_T; // @[util.scala:126:51] assign _fired_load_wakeup_T = _GEN_389; // @[util.scala:126:51] wire [11:0] _mem_ldq_wakeup_e_out_valid_T; // @[util.scala:126:51] assign _mem_ldq_wakeup_e_out_valid_T = _GEN_389; // @[util.scala:126:51] wire _fired_load_wakeup_T_1 = |_fired_load_wakeup_T; // @[util.scala:126:{51,59}] wire _fired_load_wakeup_T_2 = _fired_load_wakeup_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _fired_load_wakeup_T_3 = ~_fired_load_wakeup_T_2; // @[util.scala:61:61] wire _fired_load_wakeup_T_4 = will_fire_load_wakeup_0 & _fired_load_wakeup_T_3; // @[lsu.scala:480:41, :1049:{79,82}] reg fired_load_wakeup_REG; // @[lsu.scala:1049:51] wire fired_load_wakeup_0 = fired_load_wakeup_REG; // @[lsu.scala:321:49, :1049:51] reg fired_hella_incoming_0; // @[lsu.scala:1050:37] reg fired_hella_wakeup_0; // @[lsu.scala:1051:37] wire [31:0] _mem_incoming_uop_WIRE_0_inst = mem_incoming_uop_out_inst; // @[util.scala:104:23] wire [31:0] _mem_incoming_uop_WIRE_0_debug_inst = mem_incoming_uop_out_debug_inst; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_rvc = mem_incoming_uop_out_is_rvc; // @[util.scala:104:23] wire [39:0] _mem_incoming_uop_WIRE_0_debug_pc = mem_incoming_uop_out_debug_pc; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_0 = mem_incoming_uop_out_iq_type_0; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_1 = mem_incoming_uop_out_iq_type_1; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_2 = mem_incoming_uop_out_iq_type_2; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_3 = mem_incoming_uop_out_iq_type_3; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_0 = mem_incoming_uop_out_fu_code_0; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_1 = mem_incoming_uop_out_fu_code_1; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_2 = mem_incoming_uop_out_fu_code_2; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_3 = mem_incoming_uop_out_fu_code_3; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_4 = mem_incoming_uop_out_fu_code_4; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_5 = mem_incoming_uop_out_fu_code_5; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_6 = mem_incoming_uop_out_fu_code_6; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_7 = mem_incoming_uop_out_fu_code_7; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_8 = mem_incoming_uop_out_fu_code_8; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_9 = mem_incoming_uop_out_fu_code_9; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_issued = mem_incoming_uop_out_iw_issued; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_issued_partial_agen = mem_incoming_uop_out_iw_issued_partial_agen; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_issued_partial_dgen = mem_incoming_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_iw_p1_speculative_child = mem_incoming_uop_out_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_iw_p2_speculative_child = mem_incoming_uop_out_iw_p2_speculative_child; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_p1_bypass_hint = mem_incoming_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_p2_bypass_hint = mem_incoming_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_p3_bypass_hint = mem_incoming_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23] wire [11:0] _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [1:0] _mem_incoming_uop_WIRE_0_dis_col_sel = mem_incoming_uop_out_dis_col_sel; // @[util.scala:104:23] wire [11:0] _mem_incoming_uop_WIRE_0_br_mask = mem_incoming_uop_out_br_mask; // @[util.scala:104:23] wire [3:0] _mem_incoming_uop_WIRE_0_br_tag = mem_incoming_uop_out_br_tag; // @[util.scala:104:23] wire [3:0] _mem_incoming_uop_WIRE_0_br_type = mem_incoming_uop_out_br_type; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_sfb = mem_incoming_uop_out_is_sfb; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_fence = mem_incoming_uop_out_is_fence; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_fencei = mem_incoming_uop_out_is_fencei; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_sfence = mem_incoming_uop_out_is_sfence; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_amo = mem_incoming_uop_out_is_amo; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_eret = mem_incoming_uop_out_is_eret; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_sys_pc2epc = mem_incoming_uop_out_is_sys_pc2epc; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_rocc = mem_incoming_uop_out_is_rocc; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_mov = mem_incoming_uop_out_is_mov; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_ftq_idx = mem_incoming_uop_out_ftq_idx; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_edge_inst = mem_incoming_uop_out_edge_inst; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_pc_lob = mem_incoming_uop_out_pc_lob; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_taken = mem_incoming_uop_out_taken; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_imm_rename = mem_incoming_uop_out_imm_rename; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_imm_sel = mem_incoming_uop_out_imm_sel; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_pimm = mem_incoming_uop_out_pimm; // @[util.scala:104:23] wire [19:0] _mem_incoming_uop_WIRE_0_imm_packed = mem_incoming_uop_out_imm_packed; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_op1_sel = mem_incoming_uop_out_op1_sel; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_op2_sel = mem_incoming_uop_out_op2_sel; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ldst = mem_incoming_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_wen = mem_incoming_uop_out_fp_ctrl_wen; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ren1 = mem_incoming_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ren2 = mem_incoming_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ren3 = mem_incoming_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_swap12 = mem_incoming_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_swap23 = mem_incoming_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_fp_ctrl_typeTagIn = mem_incoming_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_fp_ctrl_typeTagOut = mem_incoming_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_fromint = mem_incoming_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_toint = mem_incoming_uop_out_fp_ctrl_toint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_fastpipe = mem_incoming_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_fma = mem_incoming_uop_out_fp_ctrl_fma; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_div = mem_incoming_uop_out_fp_ctrl_div; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_sqrt = mem_incoming_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_wflags = mem_incoming_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_vec = mem_incoming_uop_out_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_rob_idx = mem_incoming_uop_out_rob_idx; // @[util.scala:104:23] wire [3:0] _mem_incoming_uop_WIRE_0_ldq_idx = mem_incoming_uop_out_ldq_idx; // @[util.scala:104:23] wire [3:0] _mem_incoming_uop_WIRE_0_stq_idx = mem_incoming_uop_out_stq_idx; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_rxq_idx = mem_incoming_uop_out_rxq_idx; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_pdst = mem_incoming_uop_out_pdst; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs1 = mem_incoming_uop_out_prs1; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs2 = mem_incoming_uop_out_prs2; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs3 = mem_incoming_uop_out_prs3; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_ppred = mem_incoming_uop_out_ppred; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_prs1_busy = mem_incoming_uop_out_prs1_busy; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_prs2_busy = mem_incoming_uop_out_prs2_busy; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_prs3_busy = mem_incoming_uop_out_prs3_busy; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_ppred_busy = mem_incoming_uop_out_ppred_busy; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_stale_pdst = mem_incoming_uop_out_stale_pdst; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_exception = mem_incoming_uop_out_exception; // @[util.scala:104:23] wire [63:0] _mem_incoming_uop_WIRE_0_exc_cause = mem_incoming_uop_out_exc_cause; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_mem_cmd = mem_incoming_uop_out_mem_cmd; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_mem_size = mem_incoming_uop_out_mem_size; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_mem_signed = mem_incoming_uop_out_mem_signed; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_uses_ldq = mem_incoming_uop_out_uses_ldq; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_uses_stq = mem_incoming_uop_out_uses_stq; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_unique = mem_incoming_uop_out_is_unique; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_flush_on_commit = mem_incoming_uop_out_flush_on_commit; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_csr_cmd = mem_incoming_uop_out_csr_cmd; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_ldst_is_rs1 = mem_incoming_uop_out_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_ldst = mem_incoming_uop_out_ldst; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs1 = mem_incoming_uop_out_lrs1; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs2 = mem_incoming_uop_out_lrs2; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs3 = mem_incoming_uop_out_lrs3; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_dst_rtype = mem_incoming_uop_out_dst_rtype; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs1_rtype = mem_incoming_uop_out_lrs1_rtype; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs2_rtype = mem_incoming_uop_out_lrs2_rtype; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_frs3_en = mem_incoming_uop_out_frs3_en; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fcn_dw = mem_incoming_uop_out_fcn_dw; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_fcn_op = mem_incoming_uop_out_fcn_op; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_val = mem_incoming_uop_out_fp_val; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_fp_rm = mem_incoming_uop_out_fp_rm; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_fp_typ = mem_incoming_uop_out_fp_typ; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_xcpt_pf_if = mem_incoming_uop_out_xcpt_pf_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_xcpt_ae_if = mem_incoming_uop_out_xcpt_ae_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_xcpt_ma_if = mem_incoming_uop_out_xcpt_ma_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_bp_debug_if = mem_incoming_uop_out_bp_debug_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_bp_xcpt_if = mem_incoming_uop_out_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_debug_fsrc = mem_incoming_uop_out_debug_fsrc; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_debug_tsrc = mem_incoming_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _mem_incoming_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _mem_incoming_uop_out_br_mask_T_1 = io_core_agen_0_bits_uop_br_mask_0 & _mem_incoming_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign mem_incoming_uop_out_br_mask = _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg [31:0] mem_incoming_uop_0_inst; // @[lsu.scala:1053:37] wire [31:0] w1_bits_out_uop_inst = mem_incoming_uop_0_inst; // @[util.scala:109:23] reg [31:0] mem_incoming_uop_0_debug_inst; // @[lsu.scala:1053:37] wire [31:0] w1_bits_out_uop_debug_inst = mem_incoming_uop_0_debug_inst; // @[util.scala:109:23] reg mem_incoming_uop_0_is_rvc; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_rvc = mem_incoming_uop_0_is_rvc; // @[util.scala:109:23] reg [39:0] mem_incoming_uop_0_debug_pc; // @[lsu.scala:1053:37] wire [39:0] w1_bits_out_uop_debug_pc = mem_incoming_uop_0_debug_pc; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_0; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_0 = mem_incoming_uop_0_iq_type_0; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_1 = mem_incoming_uop_0_iq_type_1; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_2; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_2 = mem_incoming_uop_0_iq_type_2; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_3; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_3 = mem_incoming_uop_0_iq_type_3; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_0; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_0 = mem_incoming_uop_0_fu_code_0; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_1 = mem_incoming_uop_0_fu_code_1; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_2; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_2 = mem_incoming_uop_0_fu_code_2; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_3; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_3 = mem_incoming_uop_0_fu_code_3; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_4; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_4 = mem_incoming_uop_0_fu_code_4; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_5; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_5 = mem_incoming_uop_0_fu_code_5; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_6; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_6 = mem_incoming_uop_0_fu_code_6; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_7; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_7 = mem_incoming_uop_0_fu_code_7; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_8; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_8 = mem_incoming_uop_0_fu_code_8; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_9; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_9 = mem_incoming_uop_0_fu_code_9; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_issued; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_issued = mem_incoming_uop_0_iw_issued; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_issued_partial_agen; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_issued_partial_agen = mem_incoming_uop_0_iw_issued_partial_agen; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_issued_partial_dgen; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_issued_partial_dgen = mem_incoming_uop_0_iw_issued_partial_dgen; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_iw_p1_speculative_child; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_iw_p1_speculative_child = mem_incoming_uop_0_iw_p1_speculative_child; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_iw_p2_speculative_child; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_iw_p2_speculative_child = mem_incoming_uop_0_iw_p2_speculative_child; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_p1_bypass_hint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_p1_bypass_hint = mem_incoming_uop_0_iw_p1_bypass_hint; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_p2_bypass_hint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_p2_bypass_hint = mem_incoming_uop_0_iw_p2_bypass_hint; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_p3_bypass_hint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_p3_bypass_hint = mem_incoming_uop_0_iw_p3_bypass_hint; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_dis_col_sel; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_dis_col_sel = mem_incoming_uop_0_dis_col_sel; // @[util.scala:109:23] reg [11:0] mem_incoming_uop_0_br_mask; // @[lsu.scala:1053:37] reg [3:0] mem_incoming_uop_0_br_tag; // @[lsu.scala:1053:37] wire [3:0] w1_bits_out_uop_br_tag = mem_incoming_uop_0_br_tag; // @[util.scala:109:23] reg [3:0] mem_incoming_uop_0_br_type; // @[lsu.scala:1053:37] wire [3:0] w1_bits_out_uop_br_type = mem_incoming_uop_0_br_type; // @[util.scala:109:23] reg mem_incoming_uop_0_is_sfb; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_sfb = mem_incoming_uop_0_is_sfb; // @[util.scala:109:23] reg mem_incoming_uop_0_is_fence; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_fence = mem_incoming_uop_0_is_fence; // @[util.scala:109:23] reg mem_incoming_uop_0_is_fencei; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_fencei = mem_incoming_uop_0_is_fencei; // @[util.scala:109:23] reg mem_incoming_uop_0_is_sfence; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_sfence = mem_incoming_uop_0_is_sfence; // @[util.scala:109:23] reg mem_incoming_uop_0_is_amo; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_amo = mem_incoming_uop_0_is_amo; // @[util.scala:109:23] reg mem_incoming_uop_0_is_eret; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_eret = mem_incoming_uop_0_is_eret; // @[util.scala:109:23] reg mem_incoming_uop_0_is_sys_pc2epc; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_sys_pc2epc = mem_incoming_uop_0_is_sys_pc2epc; // @[util.scala:109:23] reg mem_incoming_uop_0_is_rocc; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_rocc = mem_incoming_uop_0_is_rocc; // @[util.scala:109:23] reg mem_incoming_uop_0_is_mov; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_mov = mem_incoming_uop_0_is_mov; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_ftq_idx; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_ftq_idx = mem_incoming_uop_0_ftq_idx; // @[util.scala:109:23] reg mem_incoming_uop_0_edge_inst; // @[lsu.scala:1053:37] wire w1_bits_out_uop_edge_inst = mem_incoming_uop_0_edge_inst; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_pc_lob; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_pc_lob = mem_incoming_uop_0_pc_lob; // @[util.scala:109:23] reg mem_incoming_uop_0_taken; // @[lsu.scala:1053:37] wire w1_bits_out_uop_taken = mem_incoming_uop_0_taken; // @[util.scala:109:23] reg mem_incoming_uop_0_imm_rename; // @[lsu.scala:1053:37] wire w1_bits_out_uop_imm_rename = mem_incoming_uop_0_imm_rename; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_imm_sel; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_imm_sel = mem_incoming_uop_0_imm_sel; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_pimm; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_pimm = mem_incoming_uop_0_pimm; // @[util.scala:109:23] reg [19:0] mem_incoming_uop_0_imm_packed; // @[lsu.scala:1053:37] wire [19:0] w1_bits_out_uop_imm_packed = mem_incoming_uop_0_imm_packed; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_op1_sel; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_op1_sel = mem_incoming_uop_0_op1_sel; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_op2_sel; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_op2_sel = mem_incoming_uop_0_op2_sel; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ldst; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ldst = mem_incoming_uop_0_fp_ctrl_ldst; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_wen; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_wen = mem_incoming_uop_0_fp_ctrl_wen; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ren1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ren1 = mem_incoming_uop_0_fp_ctrl_ren1; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ren2; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ren2 = mem_incoming_uop_0_fp_ctrl_ren2; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ren3; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ren3 = mem_incoming_uop_0_fp_ctrl_ren3; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_swap12; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_swap12 = mem_incoming_uop_0_fp_ctrl_swap12; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_swap23; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_swap23 = mem_incoming_uop_0_fp_ctrl_swap23; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_fp_ctrl_typeTagIn = mem_incoming_uop_0_fp_ctrl_typeTagIn; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_fp_ctrl_typeTagOut = mem_incoming_uop_0_fp_ctrl_typeTagOut; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_fromint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_fromint = mem_incoming_uop_0_fp_ctrl_fromint; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_toint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_toint = mem_incoming_uop_0_fp_ctrl_toint; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_fastpipe = mem_incoming_uop_0_fp_ctrl_fastpipe; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_fma; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_fma = mem_incoming_uop_0_fp_ctrl_fma; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_div; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_div = mem_incoming_uop_0_fp_ctrl_div; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_sqrt; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_sqrt = mem_incoming_uop_0_fp_ctrl_sqrt; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_wflags; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_wflags = mem_incoming_uop_0_fp_ctrl_wflags; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_vec; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_vec = mem_incoming_uop_0_fp_ctrl_vec; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_rob_idx; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_rob_idx = mem_incoming_uop_0_rob_idx; // @[util.scala:109:23] reg [3:0] mem_incoming_uop_0_ldq_idx; // @[lsu.scala:1053:37] wire [3:0] w1_bits_out_uop_ldq_idx = mem_incoming_uop_0_ldq_idx; // @[util.scala:109:23] reg [3:0] mem_incoming_uop_0_stq_idx; // @[lsu.scala:1053:37] wire [3:0] w1_bits_out_uop_stq_idx = mem_incoming_uop_0_stq_idx; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_rxq_idx; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_rxq_idx = mem_incoming_uop_0_rxq_idx; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_pdst; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_pdst = mem_incoming_uop_0_pdst; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_prs1; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_prs1 = mem_incoming_uop_0_prs1; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_prs2; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_prs2 = mem_incoming_uop_0_prs2; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_prs3; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_prs3 = mem_incoming_uop_0_prs3; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_ppred; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_ppred = mem_incoming_uop_0_ppred; // @[util.scala:109:23] reg mem_incoming_uop_0_prs1_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_prs1_busy = mem_incoming_uop_0_prs1_busy; // @[util.scala:109:23] reg mem_incoming_uop_0_prs2_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_prs2_busy = mem_incoming_uop_0_prs2_busy; // @[util.scala:109:23] reg mem_incoming_uop_0_prs3_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_prs3_busy = mem_incoming_uop_0_prs3_busy; // @[util.scala:109:23] reg mem_incoming_uop_0_ppred_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_ppred_busy = mem_incoming_uop_0_ppred_busy; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_stale_pdst; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_stale_pdst = mem_incoming_uop_0_stale_pdst; // @[util.scala:109:23] reg mem_incoming_uop_0_exception; // @[lsu.scala:1053:37] wire w1_bits_out_uop_exception = mem_incoming_uop_0_exception; // @[util.scala:109:23] reg [63:0] mem_incoming_uop_0_exc_cause; // @[lsu.scala:1053:37] wire [63:0] w1_bits_out_uop_exc_cause = mem_incoming_uop_0_exc_cause; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_mem_cmd; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_mem_cmd = mem_incoming_uop_0_mem_cmd; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_mem_size; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_mem_size = mem_incoming_uop_0_mem_size; // @[util.scala:109:23] reg mem_incoming_uop_0_mem_signed; // @[lsu.scala:1053:37] wire w1_bits_out_uop_mem_signed = mem_incoming_uop_0_mem_signed; // @[util.scala:109:23] reg mem_incoming_uop_0_uses_ldq; // @[lsu.scala:1053:37] wire w1_bits_out_uop_uses_ldq = mem_incoming_uop_0_uses_ldq; // @[util.scala:109:23] reg mem_incoming_uop_0_uses_stq; // @[lsu.scala:1053:37] wire w1_bits_out_uop_uses_stq = mem_incoming_uop_0_uses_stq; // @[util.scala:109:23] reg mem_incoming_uop_0_is_unique; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_unique = mem_incoming_uop_0_is_unique; // @[util.scala:109:23] reg mem_incoming_uop_0_flush_on_commit; // @[lsu.scala:1053:37] wire w1_bits_out_uop_flush_on_commit = mem_incoming_uop_0_flush_on_commit; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_csr_cmd; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_csr_cmd = mem_incoming_uop_0_csr_cmd; // @[util.scala:109:23] reg mem_incoming_uop_0_ldst_is_rs1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_ldst_is_rs1 = mem_incoming_uop_0_ldst_is_rs1; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_ldst; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_ldst = mem_incoming_uop_0_ldst; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_lrs1; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_lrs1 = mem_incoming_uop_0_lrs1; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_lrs2; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_lrs2 = mem_incoming_uop_0_lrs2; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_lrs3; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_lrs3 = mem_incoming_uop_0_lrs3; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_dst_rtype; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_dst_rtype = mem_incoming_uop_0_dst_rtype; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_lrs1_rtype; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_lrs1_rtype = mem_incoming_uop_0_lrs1_rtype; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_lrs2_rtype; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_lrs2_rtype = mem_incoming_uop_0_lrs2_rtype; // @[util.scala:109:23] reg mem_incoming_uop_0_frs3_en; // @[lsu.scala:1053:37] wire w1_bits_out_uop_frs3_en = mem_incoming_uop_0_frs3_en; // @[util.scala:109:23] reg mem_incoming_uop_0_fcn_dw; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fcn_dw = mem_incoming_uop_0_fcn_dw; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_fcn_op; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_fcn_op = mem_incoming_uop_0_fcn_op; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_val; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_val = mem_incoming_uop_0_fp_val; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_fp_rm; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_fp_rm = mem_incoming_uop_0_fp_rm; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_fp_typ; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_fp_typ = mem_incoming_uop_0_fp_typ; // @[util.scala:109:23] reg mem_incoming_uop_0_xcpt_pf_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_xcpt_pf_if = mem_incoming_uop_0_xcpt_pf_if; // @[util.scala:109:23] reg mem_incoming_uop_0_xcpt_ae_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_xcpt_ae_if = mem_incoming_uop_0_xcpt_ae_if; // @[util.scala:109:23] reg mem_incoming_uop_0_xcpt_ma_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_xcpt_ma_if = mem_incoming_uop_0_xcpt_ma_if; // @[util.scala:109:23] reg mem_incoming_uop_0_bp_debug_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_bp_debug_if = mem_incoming_uop_0_bp_debug_if; // @[util.scala:109:23] reg mem_incoming_uop_0_bp_xcpt_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_bp_xcpt_if = mem_incoming_uop_0_bp_xcpt_if; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_debug_fsrc; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_debug_fsrc = mem_incoming_uop_0_debug_fsrc; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_debug_tsrc; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_debug_tsrc = mem_incoming_uop_0_debug_tsrc; // @[util.scala:109:23] wire _mem_ldq_incoming_e_out_valid_T_4; // @[util.scala:116:31] wire _mem_ldq_incoming_e_WIRE_0_valid = mem_ldq_incoming_e_out_valid; // @[util.scala:114:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_inst = mem_ldq_incoming_e_out_bits_uop_inst; // @[util.scala:114:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_ldq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_ldq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_ldq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_0 = mem_ldq_incoming_e_out_bits_uop_iq_type_0; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_1 = mem_ldq_incoming_e_out_bits_uop_iq_type_1; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_2 = mem_ldq_incoming_e_out_bits_uop_iq_type_2; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_3 = mem_ldq_incoming_e_out_bits_uop_iq_type_3; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_0 = mem_ldq_incoming_e_out_bits_uop_fu_code_0; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_1 = mem_ldq_incoming_e_out_bits_uop_fu_code_1; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_2 = mem_ldq_incoming_e_out_bits_uop_fu_code_2; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_3 = mem_ldq_incoming_e_out_bits_uop_fu_code_3; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_4 = mem_ldq_incoming_e_out_bits_uop_fu_code_4; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_5 = mem_ldq_incoming_e_out_bits_uop_fu_code_5; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_6 = mem_ldq_incoming_e_out_bits_uop_fu_code_6; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_7 = mem_ldq_incoming_e_out_bits_uop_fu_code_7; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_8 = mem_ldq_incoming_e_out_bits_uop_fu_code_8; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_9 = mem_ldq_incoming_e_out_bits_uop_fu_code_9; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_issued = mem_ldq_incoming_e_out_bits_uop_iw_issued; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_agen = mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_dgen = mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p1_speculative_child = mem_ldq_incoming_e_out_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p2_speculative_child = mem_ldq_incoming_e_out_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p1_bypass_hint = mem_ldq_incoming_e_out_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p2_bypass_hint = mem_ldq_incoming_e_out_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p3_bypass_hint = mem_ldq_incoming_e_out_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [11:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_dis_col_sel = mem_ldq_incoming_e_out_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [11:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_mask = mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_tag = mem_ldq_incoming_e_out_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_type = mem_ldq_incoming_e_out_bits_uop_br_type; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_ldq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fence = mem_ldq_incoming_e_out_bits_uop_is_fence; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_ldq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sfence = mem_ldq_incoming_e_out_bits_uop_is_sfence; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_amo = mem_ldq_incoming_e_out_bits_uop_is_amo; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_eret = mem_ldq_incoming_e_out_bits_uop_is_eret; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_rocc = mem_ldq_incoming_e_out_bits_uop_is_rocc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_mov = mem_ldq_incoming_e_out_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_ldq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_ldq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_ldq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_taken = mem_ldq_incoming_e_out_bits_uop_taken; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_rename = mem_ldq_incoming_e_out_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_sel = mem_ldq_incoming_e_out_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pimm = mem_ldq_incoming_e_out_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_ldq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_op1_sel = mem_ldq_incoming_e_out_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_op2_sel = mem_ldq_incoming_e_out_bits_uop_op2_sel; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ldst = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wen = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren1 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren2 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren3 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap12 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap23 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagIn = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagOut = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fromint = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_toint = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fastpipe = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fma = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_div = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_sqrt = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wflags = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_vec = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_ldq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_ldq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_ldq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_ldq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pdst = mem_ldq_incoming_e_out_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1 = mem_ldq_incoming_e_out_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2 = mem_ldq_incoming_e_out_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3 = mem_ldq_incoming_e_out_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred = mem_ldq_incoming_e_out_bits_uop_ppred; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_ldq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_ldq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_ldq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_ldq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_ldq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_exception = mem_ldq_incoming_e_out_bits_uop_exception; // @[util.scala:114:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_ldq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_ldq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_size = mem_ldq_incoming_e_out_bits_uop_mem_size; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_ldq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_ldq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_ldq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_unique = mem_ldq_incoming_e_out_bits_uop_is_unique; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_ldq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_csr_cmd = mem_ldq_incoming_e_out_bits_uop_csr_cmd; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst = mem_ldq_incoming_e_out_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_ldq_incoming_e_out_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_ldq_incoming_e_out_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_ldq_incoming_e_out_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_ldq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_ldq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_ldq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_ldq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fcn_dw = mem_ldq_incoming_e_out_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fcn_op = mem_ldq_incoming_e_out_bits_uop_fcn_op; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_val = mem_ldq_incoming_e_out_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_rm = mem_ldq_incoming_e_out_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_typ = mem_ldq_incoming_e_out_bits_uop_fp_typ; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_ldq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_ldq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_ldq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_valid = mem_ldq_incoming_e_out_bits_addr_valid; // @[util.scala:114:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_addr_bits = mem_ldq_incoming_e_out_bits_addr_bits; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_ldq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_uncacheable = mem_ldq_incoming_e_out_bits_addr_is_uncacheable; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_executed = mem_ldq_incoming_e_out_bits_executed; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_succeeded = mem_ldq_incoming_e_out_bits_succeeded; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_order_fail = mem_ldq_incoming_e_out_bits_order_fail; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_observed = mem_ldq_incoming_e_out_bits_observed; // @[util.scala:114:23] wire [15:0] _mem_ldq_incoming_e_WIRE_0_bits_st_dep_mask = mem_ldq_incoming_e_out_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] _mem_ldq_incoming_e_WIRE_0_bits_ld_byte_mask = mem_ldq_incoming_e_out_bits_ld_byte_mask; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_forward_std_val = mem_ldq_incoming_e_out_bits_forward_std_val; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_forward_stq_idx = mem_ldq_incoming_e_out_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_debug_wb_data = mem_ldq_incoming_e_out_bits_debug_wb_data; // @[util.scala:114:23] wire [11:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1 = ldq_incoming_e_0_bits_uop_br_mask & _mem_ldq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_ldq_incoming_e_out_bits_uop_br_mask = _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [11:0] _mem_ldq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & ldq_incoming_e_0_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_ldq_incoming_e_out_valid_T_1 = |_mem_ldq_incoming_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_ldq_incoming_e_out_valid_T_2 = _mem_ldq_incoming_e_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_ldq_incoming_e_out_valid_T_3 = ~_mem_ldq_incoming_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_ldq_incoming_e_out_valid_T_4 = ldq_incoming_e_0_valid & _mem_ldq_incoming_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_ldq_incoming_e_out_valid = _mem_ldq_incoming_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_ldq_incoming_e_0_valid; // @[lsu.scala:1054:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_inst; // @[lsu.scala:1054:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:1054:37] reg [39:0] mem_ldq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_0; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_1; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_2; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_3; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_0; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_1; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_2; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_3; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_4; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_5; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_6; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_7; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_8; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_9; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_issued; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_dis_col_sel; // @[lsu.scala:1054:37] reg [11:0] mem_ldq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_br_type; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_sfence; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_eret; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_rocc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_mov; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_taken; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_imm_rename; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_imm_sel; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_pimm; // @[lsu.scala:1054:37] reg [19:0] mem_ldq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_op1_sel; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_op2_sel; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_exception; // @[lsu.scala:1054:37] reg [63:0] mem_ldq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_csr_cmd; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fcn_dw; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_fcn_op; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_fp_rm; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_fp_typ; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_addr_valid; // @[lsu.scala:1054:37] reg [39:0] mem_ldq_incoming_e_0_bits_addr_bits; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_addr_is_uncacheable; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_executed; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_succeeded; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_order_fail; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_observed; // @[lsu.scala:1054:37] reg [15:0] mem_ldq_incoming_e_0_bits_st_dep_mask; // @[lsu.scala:1054:37] reg [7:0] mem_ldq_incoming_e_0_bits_ld_byte_mask; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_forward_std_val; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_forward_stq_idx; // @[lsu.scala:1054:37] reg [63:0] mem_ldq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:1054:37] wire _mem_stq_incoming_e_out_valid_T_4; // @[util.scala:116:31] wire _mem_stq_incoming_e_WIRE_0_valid = mem_stq_incoming_e_out_valid; // @[util.scala:114:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_inst = mem_stq_incoming_e_out_bits_uop_inst; // @[util.scala:114:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_stq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_stq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_stq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_0 = mem_stq_incoming_e_out_bits_uop_iq_type_0; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_1 = mem_stq_incoming_e_out_bits_uop_iq_type_1; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_2 = mem_stq_incoming_e_out_bits_uop_iq_type_2; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_3 = mem_stq_incoming_e_out_bits_uop_iq_type_3; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_0 = mem_stq_incoming_e_out_bits_uop_fu_code_0; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_1 = mem_stq_incoming_e_out_bits_uop_fu_code_1; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_2 = mem_stq_incoming_e_out_bits_uop_fu_code_2; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_3 = mem_stq_incoming_e_out_bits_uop_fu_code_3; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_4 = mem_stq_incoming_e_out_bits_uop_fu_code_4; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_5 = mem_stq_incoming_e_out_bits_uop_fu_code_5; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_6 = mem_stq_incoming_e_out_bits_uop_fu_code_6; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_7 = mem_stq_incoming_e_out_bits_uop_fu_code_7; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_8 = mem_stq_incoming_e_out_bits_uop_fu_code_8; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_9 = mem_stq_incoming_e_out_bits_uop_fu_code_9; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_issued = mem_stq_incoming_e_out_bits_uop_iw_issued; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_agen = mem_stq_incoming_e_out_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_dgen = mem_stq_incoming_e_out_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p1_speculative_child = mem_stq_incoming_e_out_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p2_speculative_child = mem_stq_incoming_e_out_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p1_bypass_hint = mem_stq_incoming_e_out_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p2_bypass_hint = mem_stq_incoming_e_out_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p3_bypass_hint = mem_stq_incoming_e_out_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [11:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_dis_col_sel = mem_stq_incoming_e_out_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [11:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_mask = mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_tag = mem_stq_incoming_e_out_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_type = mem_stq_incoming_e_out_bits_uop_br_type; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_stq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fence = mem_stq_incoming_e_out_bits_uop_is_fence; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_stq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sfence = mem_stq_incoming_e_out_bits_uop_is_sfence; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_amo = mem_stq_incoming_e_out_bits_uop_is_amo; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_eret = mem_stq_incoming_e_out_bits_uop_is_eret; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_rocc = mem_stq_incoming_e_out_bits_uop_is_rocc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_mov = mem_stq_incoming_e_out_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_stq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_stq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_stq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_taken = mem_stq_incoming_e_out_bits_uop_taken; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_imm_rename = mem_stq_incoming_e_out_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_imm_sel = mem_stq_incoming_e_out_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pimm = mem_stq_incoming_e_out_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] _mem_stq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_stq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_op1_sel = mem_stq_incoming_e_out_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_op2_sel = mem_stq_incoming_e_out_bits_uop_op2_sel; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ldst = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wen = mem_stq_incoming_e_out_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren1 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren2 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren3 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap12 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap23 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagIn = mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagOut = mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fromint = mem_stq_incoming_e_out_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_toint = mem_stq_incoming_e_out_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fastpipe = mem_stq_incoming_e_out_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fma = mem_stq_incoming_e_out_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_div = mem_stq_incoming_e_out_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_sqrt = mem_stq_incoming_e_out_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wflags = mem_stq_incoming_e_out_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_vec = mem_stq_incoming_e_out_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_stq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_stq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_stq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_stq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pdst = mem_stq_incoming_e_out_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs1 = mem_stq_incoming_e_out_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs2 = mem_stq_incoming_e_out_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs3 = mem_stq_incoming_e_out_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ppred = mem_stq_incoming_e_out_bits_uop_ppred; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_stq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_stq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_stq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_stq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_stq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_exception = mem_stq_incoming_e_out_bits_uop_exception; // @[util.scala:114:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_stq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_stq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_size = mem_stq_incoming_e_out_bits_uop_mem_size; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_stq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_stq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_stq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_unique = mem_stq_incoming_e_out_bits_uop_is_unique; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_stq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_csr_cmd = mem_stq_incoming_e_out_bits_uop_csr_cmd; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_stq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldst = mem_stq_incoming_e_out_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_stq_incoming_e_out_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_stq_incoming_e_out_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_stq_incoming_e_out_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_stq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_stq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_stq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_stq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fcn_dw = mem_stq_incoming_e_out_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fcn_op = mem_stq_incoming_e_out_bits_uop_fcn_op; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_val = mem_stq_incoming_e_out_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_rm = mem_stq_incoming_e_out_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_typ = mem_stq_incoming_e_out_bits_uop_fp_typ; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_stq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_stq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_stq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_stq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_stq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_stq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_stq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_valid = mem_stq_incoming_e_out_bits_addr_valid; // @[util.scala:114:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_addr_bits = mem_stq_incoming_e_out_bits_addr_bits; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_stq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_data_valid = mem_stq_incoming_e_out_bits_data_valid; // @[util.scala:114:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_data_bits = mem_stq_incoming_e_out_bits_data_bits; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_committed = mem_stq_incoming_e_out_bits_committed; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_succeeded = mem_stq_incoming_e_out_bits_succeeded; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_can_execute = mem_stq_incoming_e_out_bits_can_execute; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_cleared = mem_stq_incoming_e_out_bits_cleared; // @[util.scala:114:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_debug_wb_data = mem_stq_incoming_e_out_bits_debug_wb_data; // @[util.scala:114:23] wire [11:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_stq_incoming_e_out_bits_uop_br_mask_T_1 = stq_incoming_e_0_bits_uop_br_mask & _mem_stq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_stq_incoming_e_out_bits_uop_br_mask = _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [11:0] _mem_stq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & stq_incoming_e_0_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_stq_incoming_e_out_valid_T_1 = |_mem_stq_incoming_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_stq_incoming_e_out_valid_T_2 = _mem_stq_incoming_e_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_stq_incoming_e_out_valid_T_3 = ~_mem_stq_incoming_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_stq_incoming_e_out_valid_T_4 = stq_incoming_e_0_valid & _mem_stq_incoming_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_stq_incoming_e_out_valid = _mem_stq_incoming_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_stq_incoming_e_0_valid; // @[lsu.scala:1055:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_inst; // @[lsu.scala:1055:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:1055:37] reg [39:0] mem_stq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_0; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_1; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_2; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_3; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_0; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_1; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_2; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_3; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_4; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_5; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_6; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_7; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_8; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_9; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_issued; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_dis_col_sel; // @[lsu.scala:1055:37] reg [11:0] mem_stq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:1055:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:1055:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_br_type; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_sfence; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_eret; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_rocc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_mov; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_taken; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_imm_rename; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_imm_sel; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_pimm; // @[lsu.scala:1055:37] reg [19:0] mem_stq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_op1_sel; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_op2_sel; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:1055:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:1055:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_exception; // @[lsu.scala:1055:37] reg [63:0] mem_stq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_csr_cmd; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fcn_dw; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_fcn_op; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_fp_rm; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_fp_typ; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:1055:37] reg [39:0] mem_stq_incoming_e_0_bits_addr_bits; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_data_valid; // @[lsu.scala:1055:37] reg [63:0] mem_stq_incoming_e_0_bits_data_bits; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_committed; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_succeeded; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_can_execute; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_cleared; // @[lsu.scala:1055:37] reg [63:0] mem_stq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:1055:37] wire _mem_ldq_wakeup_e_out_valid_T_4; // @[util.scala:116:31] wire [11:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] mem_ldq_wakeup_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_valid; // @[util.scala:114:23] wire [11:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1 = ldq_wakeup_e_bits_uop_br_mask & _mem_ldq_wakeup_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_ldq_wakeup_e_out_bits_uop_br_mask = _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire _mem_ldq_wakeup_e_out_valid_T_1 = |_mem_ldq_wakeup_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_ldq_wakeup_e_out_valid_T_2 = _mem_ldq_wakeup_e_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_ldq_wakeup_e_out_valid_T_3 = ~_mem_ldq_wakeup_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_ldq_wakeup_e_out_valid_T_4 = ldq_wakeup_e_valid & _mem_ldq_wakeup_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_ldq_wakeup_e_out_valid = _mem_ldq_wakeup_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_ldq_wakeup_e_valid; // @[lsu.scala:1056:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_inst; // @[lsu.scala:1056:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_debug_inst; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:1056:37] reg [39:0] mem_ldq_wakeup_e_bits_uop_debug_pc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_0; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_1; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_2; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_3; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_0; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_1; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_2; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_3; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_4; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_5; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_6; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_7; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_8; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_9; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_issued; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_dis_col_sel; // @[lsu.scala:1056:37] reg [11:0] mem_ldq_wakeup_e_bits_uop_br_mask; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_br_tag; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_br_type; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_sfence; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_eret; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_rocc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_mov; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ftq_idx; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_pc_lob; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_imm_rename; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_imm_sel; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_pimm; // @[lsu.scala:1056:37] reg [19:0] mem_ldq_wakeup_e_bits_uop_imm_packed; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_op1_sel; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_op2_sel; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_rob_idx; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_ldq_idx; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_stq_idx; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_rxq_idx; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_pdst; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs1; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs2; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs3; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ppred; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_stale_pdst; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:1056:37] reg [63:0] mem_ldq_wakeup_e_bits_uop_exc_cause; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_mem_cmd; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_mem_size; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_csr_cmd; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_ldst; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs1; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs2; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs3; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_dst_rtype; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs1_rtype; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs2_rtype; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fcn_dw; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_fcn_op; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_fp_rm; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_fp_typ; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_debug_fsrc; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_debug_tsrc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:1056:37] reg [39:0] mem_ldq_wakeup_e_bits_addr_bits; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:1056:37] reg [15:0] mem_ldq_wakeup_e_bits_st_dep_mask; // @[lsu.scala:1056:37] reg [7:0] mem_ldq_wakeup_e_bits_ld_byte_mask; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_forward_stq_idx; // @[lsu.scala:1056:37] reg [63:0] mem_ldq_wakeup_e_bits_debug_wb_data; // @[lsu.scala:1056:37] wire [31:0] mem_ldq_retry_e_out_bits_uop_inst = mem_ldq_retry_e_e_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_ldq_retry_e_out_bits_uop_debug_inst = mem_ldq_retry_e_e_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_rvc = mem_ldq_retry_e_e_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_ldq_retry_e_out_bits_uop_debug_pc = mem_ldq_retry_e_e_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_0 = mem_ldq_retry_e_e_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_1 = mem_ldq_retry_e_e_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_2 = mem_ldq_retry_e_e_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_3 = mem_ldq_retry_e_e_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_0 = mem_ldq_retry_e_e_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_1 = mem_ldq_retry_e_e_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_2 = mem_ldq_retry_e_e_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_3 = mem_ldq_retry_e_e_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_4 = mem_ldq_retry_e_e_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_5 = mem_ldq_retry_e_e_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_6 = mem_ldq_retry_e_e_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_7 = mem_ldq_retry_e_e_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_8 = mem_ldq_retry_e_e_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_9 = mem_ldq_retry_e_e_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_issued = mem_ldq_retry_e_e_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_issued_partial_agen = mem_ldq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_issued_partial_dgen = mem_ldq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_iw_p1_speculative_child = mem_ldq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_iw_p2_speculative_child = mem_ldq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_p1_bypass_hint = mem_ldq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_p2_bypass_hint = mem_ldq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_p3_bypass_hint = mem_ldq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_dis_col_sel = mem_ldq_retry_e_e_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_br_tag = mem_ldq_retry_e_e_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_br_type = mem_ldq_retry_e_e_bits_uop_br_type; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_sfb = mem_ldq_retry_e_e_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_fence = mem_ldq_retry_e_e_bits_uop_is_fence; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_fencei = mem_ldq_retry_e_e_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_sfence = mem_ldq_retry_e_e_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_amo = mem_ldq_retry_e_e_bits_uop_is_amo; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_eret = mem_ldq_retry_e_e_bits_uop_is_eret; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_sys_pc2epc = mem_ldq_retry_e_e_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_rocc = mem_ldq_retry_e_e_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_mov = mem_ldq_retry_e_e_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ftq_idx = mem_ldq_retry_e_e_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_edge_inst = mem_ldq_retry_e_e_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_pc_lob = mem_ldq_retry_e_e_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_taken = mem_ldq_retry_e_e_bits_uop_taken; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_imm_rename = mem_ldq_retry_e_e_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_imm_sel = mem_ldq_retry_e_e_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_pimm = mem_ldq_retry_e_e_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_ldq_retry_e_out_bits_uop_imm_packed = mem_ldq_retry_e_e_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_op1_sel = mem_ldq_retry_e_e_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_op2_sel = mem_ldq_retry_e_e_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ldst = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_wen = mem_ldq_retry_e_e_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ren1 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ren2 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ren3 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_swap12 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_swap23 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_fp_ctrl_typeTagIn = mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_fp_ctrl_typeTagOut = mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_fromint = mem_ldq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_toint = mem_ldq_retry_e_e_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_fastpipe = mem_ldq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_fma = mem_ldq_retry_e_e_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_div = mem_ldq_retry_e_e_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_sqrt = mem_ldq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_wflags = mem_ldq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_vec = mem_ldq_retry_e_e_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_rob_idx = mem_ldq_retry_e_e_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_ldq_idx = mem_ldq_retry_e_e_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_stq_idx = mem_ldq_retry_e_e_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_rxq_idx = mem_ldq_retry_e_e_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_pdst = mem_ldq_retry_e_e_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs1 = mem_ldq_retry_e_e_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs2 = mem_ldq_retry_e_e_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs3 = mem_ldq_retry_e_e_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ppred = mem_ldq_retry_e_e_bits_uop_ppred; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_prs1_busy = mem_ldq_retry_e_e_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_prs2_busy = mem_ldq_retry_e_e_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_prs3_busy = mem_ldq_retry_e_e_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_ppred_busy = mem_ldq_retry_e_e_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_stale_pdst = mem_ldq_retry_e_e_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_exception = mem_ldq_retry_e_e_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_ldq_retry_e_out_bits_uop_exc_cause = mem_ldq_retry_e_e_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_mem_cmd = mem_ldq_retry_e_e_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_mem_size = mem_ldq_retry_e_e_bits_uop_mem_size; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_mem_signed = mem_ldq_retry_e_e_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_uses_ldq = mem_ldq_retry_e_e_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_uses_stq = mem_ldq_retry_e_e_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_unique = mem_ldq_retry_e_e_bits_uop_is_unique; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_flush_on_commit = mem_ldq_retry_e_e_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_csr_cmd = mem_ldq_retry_e_e_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_ldst_is_rs1 = mem_ldq_retry_e_e_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_ldst = mem_ldq_retry_e_e_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs1 = mem_ldq_retry_e_e_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs2 = mem_ldq_retry_e_e_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs3 = mem_ldq_retry_e_e_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_dst_rtype = mem_ldq_retry_e_e_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs1_rtype = mem_ldq_retry_e_e_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs2_rtype = mem_ldq_retry_e_e_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_frs3_en = mem_ldq_retry_e_e_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fcn_dw = mem_ldq_retry_e_e_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_fcn_op = mem_ldq_retry_e_e_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_val = mem_ldq_retry_e_e_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_fp_rm = mem_ldq_retry_e_e_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_fp_typ = mem_ldq_retry_e_e_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_pf_if = mem_ldq_retry_e_e_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ae_if = mem_ldq_retry_e_e_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ma_if = mem_ldq_retry_e_e_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_bp_debug_if = mem_ldq_retry_e_e_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_bp_xcpt_if = mem_ldq_retry_e_e_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_debug_fsrc = mem_ldq_retry_e_e_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_debug_tsrc = mem_ldq_retry_e_e_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_addr_valid = mem_ldq_retry_e_e_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_ldq_retry_e_out_bits_addr_bits = mem_ldq_retry_e_e_bits_addr_bits; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_addr_is_virtual = mem_ldq_retry_e_e_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_addr_is_uncacheable = mem_ldq_retry_e_e_bits_addr_is_uncacheable; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_executed = mem_ldq_retry_e_e_bits_executed; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_succeeded = mem_ldq_retry_e_e_bits_succeeded; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_order_fail = mem_ldq_retry_e_e_bits_order_fail; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_observed = mem_ldq_retry_e_e_bits_observed; // @[util.scala:114:23] wire [15:0] mem_ldq_retry_e_out_bits_st_dep_mask = mem_ldq_retry_e_e_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] mem_ldq_retry_e_out_bits_ld_byte_mask = mem_ldq_retry_e_e_bits_ld_byte_mask; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_forward_std_val = mem_ldq_retry_e_e_bits_forward_std_val; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_forward_stq_idx = mem_ldq_retry_e_e_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] mem_ldq_retry_e_out_bits_debug_wb_data = mem_ldq_retry_e_e_bits_debug_wb_data; // @[util.scala:114:23] wire [11:0] mem_ldq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_valid; // @[lsu.scala:233:17] assign mem_ldq_retry_e_e_valid = _GEN_25[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :234:32, :387:15, :533:27] assign mem_ldq_retry_e_e_bits_uop_inst = _GEN_76[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_inst = _GEN_77[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_rvc = _GEN_78[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_pc = _GEN_79[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_0 = _GEN_80[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_1 = _GEN_81[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_2 = _GEN_82[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_3 = _GEN_83[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_0 = _GEN_84[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_1 = _GEN_85[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_2 = _GEN_86[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_3 = _GEN_87[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_4 = _GEN_88[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_5 = _GEN_89[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_6 = _GEN_90[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_7 = _GEN_91[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_8 = _GEN_92[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_9 = _GEN_93[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_issued = _GEN_94[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_95[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_96[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_97[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_98[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_99[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_100[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_101[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_dis_col_sel = _GEN_102[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_br_mask = _GEN_103[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_br_tag = _GEN_104[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_br_type = _GEN_105[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_sfb = _GEN_106[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_fence = _GEN_107[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_fencei = _GEN_108[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_sfence = _GEN_109[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_amo = _GEN_110[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_eret = _GEN_111[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_112[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_rocc = _GEN_113[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_mov = _GEN_114[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ftq_idx = _GEN_115[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_edge_inst = _GEN_116[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_pc_lob = _GEN_117[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_taken = _GEN_118[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_imm_rename = _GEN_119[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_imm_sel = _GEN_120[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_pimm = _GEN_121[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_imm_packed = _GEN_122[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_op1_sel = _GEN_123[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_op2_sel = _GEN_124[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_125[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_126[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_127[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_128[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_129[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_130[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_131[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_132[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_133[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_134[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_135[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_136[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_137[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_138[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_139[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_140[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_141[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_rob_idx = _GEN_142[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ldq_idx = _GEN_143[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_stq_idx = _GEN_144[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_rxq_idx = _GEN_145[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_pdst = _GEN_146[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs1 = _GEN_147[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs2 = _GEN_148[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs3 = _GEN_149[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ppred = _GEN_150[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs1_busy = _GEN_151[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs2_busy = _GEN_152[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs3_busy = _GEN_153[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ppred_busy = _GEN_154[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_stale_pdst = _GEN_155[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_exception = _GEN_156[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_exc_cause = _GEN_157[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_mem_cmd = _GEN_158[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_mem_size = _GEN_159[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_mem_signed = _GEN_160[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_uses_ldq = _GEN_161[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_uses_stq = _GEN_162[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_unique = _GEN_163[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_flush_on_commit = _GEN_164[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_csr_cmd = _GEN_165[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_166[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ldst = _GEN_167[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs1 = _GEN_168[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs2 = _GEN_169[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs3 = _GEN_170[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_dst_rtype = _GEN_171[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs1_rtype = _GEN_172[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs2_rtype = _GEN_173[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_frs3_en = _GEN_174[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fcn_dw = _GEN_175[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fcn_op = _GEN_176[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_val = _GEN_177[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_rm = _GEN_178[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_typ = _GEN_179[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_180[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_181[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_182[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_bp_debug_if = _GEN_183[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_184[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_fsrc = _GEN_185[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_tsrc = _GEN_186[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_valid = _GEN_187[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :236:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_bits = _GEN_188[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :236:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_is_virtual = _GEN_189[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :237:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_is_uncacheable = _GEN_190[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :238:32, :533:27] assign mem_ldq_retry_e_e_bits_executed = _GEN_191[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :239:32, :533:27] assign mem_ldq_retry_e_e_bits_succeeded = _GEN_192[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :240:32, :533:27] assign mem_ldq_retry_e_e_bits_order_fail = _GEN_193[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :241:32, :533:27] assign mem_ldq_retry_e_e_bits_observed = _GEN_194[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :242:32, :533:27] assign mem_ldq_retry_e_e_bits_st_dep_mask = _GEN_195[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :243:32, :533:27] assign mem_ldq_retry_e_e_bits_ld_byte_mask = _GEN_196[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :244:32, :533:27] assign mem_ldq_retry_e_e_bits_forward_std_val = _GEN_197[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :245:32, :533:27] assign mem_ldq_retry_e_e_bits_forward_stq_idx = _GEN_198[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :246:32, :533:27] assign mem_ldq_retry_e_e_bits_debug_wb_data = _GEN_199[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :247:32, :533:27] wire _mem_ldq_retry_e_out_valid_T_4; // @[util.scala:116:31] wire [11:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] mem_ldq_retry_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_ldq_retry_e_out_valid; // @[util.scala:114:23] wire [11:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_ldq_retry_e_out_bits_uop_br_mask_T_1 = mem_ldq_retry_e_e_bits_uop_br_mask & _mem_ldq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_ldq_retry_e_out_bits_uop_br_mask = _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [11:0] _mem_ldq_retry_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & mem_ldq_retry_e_e_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_ldq_retry_e_out_valid_T_1 = |_mem_ldq_retry_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_ldq_retry_e_out_valid_T_2 = _mem_ldq_retry_e_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_ldq_retry_e_out_valid_T_3 = ~_mem_ldq_retry_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_ldq_retry_e_out_valid_T_4 = mem_ldq_retry_e_e_valid & _mem_ldq_retry_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_ldq_retry_e_out_valid = _mem_ldq_retry_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_ldq_retry_e_valid; // @[lsu.scala:1057:37] reg [31:0] mem_ldq_retry_e_bits_uop_inst; // @[lsu.scala:1057:37] reg [31:0] mem_ldq_retry_e_bits_uop_debug_inst; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_rvc; // @[lsu.scala:1057:37] reg [39:0] mem_ldq_retry_e_bits_uop_debug_pc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_issued; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_dis_col_sel; // @[lsu.scala:1057:37] reg [11:0] mem_ldq_retry_e_bits_uop_br_mask; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_uop_br_tag; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_uop_br_type; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_sfb; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_fence; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_fencei; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_sfence; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_amo; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_eret; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_rocc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_mov; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_edge_inst; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_pc_lob; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_taken; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_imm_rename; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_imm_sel; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_pimm; // @[lsu.scala:1057:37] reg [19:0] mem_ldq_retry_e_bits_uop_imm_packed; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_op1_sel; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_op2_sel; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_rob_idx; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_uop_stq_idx; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_pdst; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs1; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs2; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs3; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_ppred; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_exception; // @[lsu.scala:1057:37] reg [63:0] mem_ldq_retry_e_bits_uop_exc_cause; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_mem_size; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_mem_signed; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_uses_stq; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_unique; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_csr_cmd; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_ldst; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs1; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs2; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs3; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_frs3_en; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_fcn_op; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_val; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_fp_rm; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_fp_typ; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_addr_valid; // @[lsu.scala:1057:37] reg [39:0] mem_ldq_retry_e_bits_addr_bits; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_addr_is_virtual; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_addr_is_uncacheable; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_executed; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_succeeded; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_order_fail; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_observed; // @[lsu.scala:1057:37] reg [15:0] mem_ldq_retry_e_bits_st_dep_mask; // @[lsu.scala:1057:37] reg [7:0] mem_ldq_retry_e_bits_ld_byte_mask; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_forward_std_val; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_forward_stq_idx; // @[lsu.scala:1057:37] reg [63:0] mem_ldq_retry_e_bits_debug_wb_data; // @[lsu.scala:1057:37] wire [31:0] mem_stq_retry_e_out_bits_uop_inst = mem_stq_retry_e_e_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_stq_retry_e_out_bits_uop_debug_inst = mem_stq_retry_e_e_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_rvc = mem_stq_retry_e_e_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_stq_retry_e_out_bits_uop_debug_pc = mem_stq_retry_e_e_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_0 = mem_stq_retry_e_e_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_1 = mem_stq_retry_e_e_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_2 = mem_stq_retry_e_e_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_3 = mem_stq_retry_e_e_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_0 = mem_stq_retry_e_e_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_1 = mem_stq_retry_e_e_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_2 = mem_stq_retry_e_e_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_3 = mem_stq_retry_e_e_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_4 = mem_stq_retry_e_e_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_5 = mem_stq_retry_e_e_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_6 = mem_stq_retry_e_e_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_7 = mem_stq_retry_e_e_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_8 = mem_stq_retry_e_e_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_9 = mem_stq_retry_e_e_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_issued = mem_stq_retry_e_e_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_issued_partial_agen = mem_stq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_issued_partial_dgen = mem_stq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_iw_p1_speculative_child = mem_stq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_iw_p2_speculative_child = mem_stq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_p1_bypass_hint = mem_stq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_p2_bypass_hint = mem_stq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_p3_bypass_hint = mem_stq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_dis_col_sel = mem_stq_retry_e_e_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_stq_retry_e_out_bits_uop_br_tag = mem_stq_retry_e_e_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_stq_retry_e_out_bits_uop_br_type = mem_stq_retry_e_e_bits_uop_br_type; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_sfb = mem_stq_retry_e_e_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_fence = mem_stq_retry_e_e_bits_uop_is_fence; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_fencei = mem_stq_retry_e_e_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_sfence = mem_stq_retry_e_e_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_amo = mem_stq_retry_e_e_bits_uop_is_amo; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_eret = mem_stq_retry_e_e_bits_uop_is_eret; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_sys_pc2epc = mem_stq_retry_e_e_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_rocc = mem_stq_retry_e_e_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_mov = mem_stq_retry_e_e_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ftq_idx = mem_stq_retry_e_e_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_edge_inst = mem_stq_retry_e_e_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_pc_lob = mem_stq_retry_e_e_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_taken = mem_stq_retry_e_e_bits_uop_taken; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_imm_rename = mem_stq_retry_e_e_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_imm_sel = mem_stq_retry_e_e_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_pimm = mem_stq_retry_e_e_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_stq_retry_e_out_bits_uop_imm_packed = mem_stq_retry_e_e_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_op1_sel = mem_stq_retry_e_e_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_op2_sel = mem_stq_retry_e_e_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ldst = mem_stq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_wen = mem_stq_retry_e_e_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ren1 = mem_stq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ren2 = mem_stq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ren3 = mem_stq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_swap12 = mem_stq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_swap23 = mem_stq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_fp_ctrl_typeTagIn = mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_fp_ctrl_typeTagOut = mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_fromint = mem_stq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_toint = mem_stq_retry_e_e_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_fastpipe = mem_stq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_fma = mem_stq_retry_e_e_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_div = mem_stq_retry_e_e_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_sqrt = mem_stq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_wflags = mem_stq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_vec = mem_stq_retry_e_e_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_rob_idx = mem_stq_retry_e_e_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] mem_stq_retry_e_out_bits_uop_ldq_idx = mem_stq_retry_e_e_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] mem_stq_retry_e_out_bits_uop_stq_idx = mem_stq_retry_e_e_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_rxq_idx = mem_stq_retry_e_e_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_pdst = mem_stq_retry_e_e_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs1 = mem_stq_retry_e_e_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs2 = mem_stq_retry_e_e_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs3 = mem_stq_retry_e_e_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ppred = mem_stq_retry_e_e_bits_uop_ppred; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_prs1_busy = mem_stq_retry_e_e_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_prs2_busy = mem_stq_retry_e_e_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_prs3_busy = mem_stq_retry_e_e_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_ppred_busy = mem_stq_retry_e_e_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_stale_pdst = mem_stq_retry_e_e_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_exception = mem_stq_retry_e_e_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_stq_retry_e_out_bits_uop_exc_cause = mem_stq_retry_e_e_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_mem_cmd = mem_stq_retry_e_e_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_mem_size = mem_stq_retry_e_e_bits_uop_mem_size; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_mem_signed = mem_stq_retry_e_e_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_uses_ldq = mem_stq_retry_e_e_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_uses_stq = mem_stq_retry_e_e_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_unique = mem_stq_retry_e_e_bits_uop_is_unique; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_flush_on_commit = mem_stq_retry_e_e_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_csr_cmd = mem_stq_retry_e_e_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_ldst_is_rs1 = mem_stq_retry_e_e_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_ldst = mem_stq_retry_e_e_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs1 = mem_stq_retry_e_e_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs2 = mem_stq_retry_e_e_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs3 = mem_stq_retry_e_e_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_dst_rtype = mem_stq_retry_e_e_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs1_rtype = mem_stq_retry_e_e_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs2_rtype = mem_stq_retry_e_e_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_frs3_en = mem_stq_retry_e_e_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fcn_dw = mem_stq_retry_e_e_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_fcn_op = mem_stq_retry_e_e_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_val = mem_stq_retry_e_e_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_fp_rm = mem_stq_retry_e_e_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_fp_typ = mem_stq_retry_e_e_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_xcpt_pf_if = mem_stq_retry_e_e_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ae_if = mem_stq_retry_e_e_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ma_if = mem_stq_retry_e_e_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_bp_debug_if = mem_stq_retry_e_e_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_bp_xcpt_if = mem_stq_retry_e_e_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_debug_fsrc = mem_stq_retry_e_e_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_debug_tsrc = mem_stq_retry_e_e_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_addr_valid = mem_stq_retry_e_e_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_stq_retry_e_out_bits_addr_bits = mem_stq_retry_e_e_bits_addr_bits; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_addr_is_virtual = mem_stq_retry_e_e_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_data_valid = mem_stq_retry_e_e_bits_data_valid; // @[util.scala:114:23] wire [63:0] mem_stq_retry_e_out_bits_data_bits = mem_stq_retry_e_e_bits_data_bits; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_committed = mem_stq_retry_e_e_bits_committed; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_succeeded = mem_stq_retry_e_e_bits_succeeded; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_can_execute = mem_stq_retry_e_e_bits_can_execute; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_cleared = mem_stq_retry_e_e_bits_cleared; // @[util.scala:114:23] wire [63:0] mem_stq_retry_e_out_bits_debug_wb_data = mem_stq_retry_e_e_bits_debug_wb_data; // @[util.scala:114:23] wire [11:0] mem_stq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_valid; // @[lsu.scala:262:17] assign mem_stq_retry_e_e_valid = _GEN_26[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :263:32, :392:15, :533:27] assign mem_stq_retry_e_e_bits_uop_inst = _GEN_200[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_inst = _GEN_201[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_rvc = _GEN_202[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_pc = _GEN_203[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_0 = _GEN_204[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_1 = _GEN_205[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_2 = _GEN_206[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_3 = _GEN_207[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_0 = _GEN_208[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_1 = _GEN_209[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_2 = _GEN_210[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_3 = _GEN_211[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_4 = _GEN_212[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_5 = _GEN_213[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_6 = _GEN_214[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_7 = _GEN_215[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_8 = _GEN_216[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_9 = _GEN_217[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_issued = _GEN_218[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_219[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_220[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_221[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_222[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_223[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_224[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_225[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_dis_col_sel = _GEN_226[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_br_mask = _GEN_227[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_br_tag = _GEN_228[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_br_type = _GEN_229[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_sfb = _GEN_230[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_fence = _GEN_231[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_fencei = _GEN_232[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_sfence = _GEN_233[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_amo = _GEN_234[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_eret = _GEN_235[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_236[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_rocc = _GEN_237[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_mov = _GEN_238[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ftq_idx = _GEN_239[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_edge_inst = _GEN_240[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_pc_lob = _GEN_241[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_taken = _GEN_242[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_imm_rename = _GEN_243[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_imm_sel = _GEN_244[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_pimm = _GEN_245[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_imm_packed = _GEN_246[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_op1_sel = _GEN_247[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_op2_sel = _GEN_248[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_249[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_250[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_251[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_252[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_253[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_254[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_255[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_256[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_257[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_258[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_259[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_260[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_261[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_262[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_263[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_264[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_265[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_rob_idx = _GEN_266[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ldq_idx = _GEN_267[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_stq_idx = _GEN_268[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_rxq_idx = _GEN_269[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_pdst = _GEN_270[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs1 = _GEN_271[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs2 = _GEN_272[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs3 = _GEN_273[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ppred = _GEN_274[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs1_busy = _GEN_275[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs2_busy = _GEN_276[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs3_busy = _GEN_277[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ppred_busy = _GEN_278[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_stale_pdst = _GEN_279[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_exception = _GEN_280[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_exc_cause = _GEN_281[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_mem_cmd = _GEN_282[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_mem_size = _GEN_283[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_mem_signed = _GEN_284[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_uses_ldq = _GEN_285[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_uses_stq = _GEN_286[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_unique = _GEN_287[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_flush_on_commit = _GEN_288[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_csr_cmd = _GEN_289[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_290[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ldst = _GEN_291[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs1 = _GEN_292[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs2 = _GEN_293[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs3 = _GEN_294[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_dst_rtype = _GEN_295[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs1_rtype = _GEN_296[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs2_rtype = _GEN_297[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_frs3_en = _GEN_298[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fcn_dw = _GEN_299[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fcn_op = _GEN_300[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_val = _GEN_301[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_rm = _GEN_302[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_typ = _GEN_303[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_304[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_305[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_306[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_bp_debug_if = _GEN_307[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_308[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_fsrc = _GEN_309[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_tsrc = _GEN_310[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_addr_valid = _GEN_311[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :265:32, :533:27] assign mem_stq_retry_e_e_bits_addr_bits = _GEN_312[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :265:32, :533:27] assign mem_stq_retry_e_e_bits_addr_is_virtual = _GEN_313[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :266:32, :533:27] assign mem_stq_retry_e_e_bits_data_valid = _GEN_314[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :267:32, :533:27] assign mem_stq_retry_e_e_bits_data_bits = _GEN_315[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :267:32, :533:27] assign mem_stq_retry_e_e_bits_committed = _GEN_316[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :268:32, :533:27] assign mem_stq_retry_e_e_bits_succeeded = _GEN_317[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :269:32, :533:27] assign mem_stq_retry_e_e_bits_can_execute = _GEN_318[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :270:32, :533:27] assign mem_stq_retry_e_e_bits_cleared = _GEN_319[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :271:32, :533:27] assign mem_stq_retry_e_e_bits_debug_wb_data = _GEN_320[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :272:32, :533:27] wire _mem_stq_retry_e_out_valid_T_4; // @[util.scala:116:31] wire [11:0] _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] mem_stq_retry_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_stq_retry_e_out_valid; // @[util.scala:114:23] wire [11:0] _mem_stq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_stq_retry_e_out_bits_uop_br_mask_T_1 = mem_stq_retry_e_e_bits_uop_br_mask & _mem_stq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_stq_retry_e_out_bits_uop_br_mask = _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [11:0] _mem_stq_retry_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & mem_stq_retry_e_e_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_stq_retry_e_out_valid_T_1 = |_mem_stq_retry_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_stq_retry_e_out_valid_T_2 = _mem_stq_retry_e_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_stq_retry_e_out_valid_T_3 = ~_mem_stq_retry_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_stq_retry_e_out_valid_T_4 = mem_stq_retry_e_e_valid & _mem_stq_retry_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_stq_retry_e_out_valid = _mem_stq_retry_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_stq_retry_e_valid; // @[lsu.scala:1058:37] reg [31:0] mem_stq_retry_e_bits_uop_inst; // @[lsu.scala:1058:37] reg [31:0] mem_stq_retry_e_bits_uop_debug_inst; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:1058:37] reg [39:0] mem_stq_retry_e_bits_uop_debug_pc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_issued; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_dis_col_sel; // @[lsu.scala:1058:37] reg [11:0] mem_stq_retry_e_bits_uop_br_mask; // @[lsu.scala:1058:37] reg [3:0] mem_stq_retry_e_bits_uop_br_tag; // @[lsu.scala:1058:37] reg [3:0] mem_stq_retry_e_bits_uop_br_type; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_sfence; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_eret; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_rocc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_mov; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_pc_lob; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_imm_rename; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_imm_sel; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_pimm; // @[lsu.scala:1058:37] reg [19:0] mem_stq_retry_e_bits_uop_imm_packed; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_op1_sel; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_op2_sel; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_rob_idx; // @[lsu.scala:1058:37] reg [3:0] mem_stq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:1058:37] reg [3:0] mem_stq_retry_e_bits_uop_stq_idx; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_pdst; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_prs1; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_prs2; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_prs3; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_ppred; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:1058:37] reg [63:0] mem_stq_retry_e_bits_uop_exc_cause; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_mem_size; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_csr_cmd; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_ldst; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs1; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs2; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs3; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_fcn_op; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_fp_rm; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_fp_typ; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:1058:37] reg [39:0] mem_stq_retry_e_bits_addr_bits; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_data_valid; // @[lsu.scala:1058:37] reg [63:0] mem_stq_retry_e_bits_data_bits; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_committed; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_succeeded; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_can_execute; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_cleared; // @[lsu.scala:1058:37] reg [63:0] mem_stq_retry_e_bits_debug_wb_data; // @[lsu.scala:1058:37] wire _GEN_390 = fired_load_agen_0 | fired_load_agen_exec_0; // @[lsu.scala:321:49, :1060:58] wire _mem_ldq_e_T; // @[lsu.scala:1060:58] assign _mem_ldq_e_T = _GEN_390; // @[lsu.scala:1060:58] wire _do_ld_search_T; // @[lsu.scala:1124:57] assign _do_ld_search_T = _GEN_390; // @[lsu.scala:1060:58, :1124:57] wire _lcam_ldq_idx_T; // @[lsu.scala:1144:51] assign _lcam_ldq_idx_T = _GEN_390; // @[lsu.scala:1060:58, :1144:51] wire _can_forward_T; // @[lsu.scala:1154:58] assign _can_forward_T = _GEN_390; // @[lsu.scala:1060:58, :1154:58] wire _mem_ldq_e_T_1_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_valid; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_debug_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_rvc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [39:0] _mem_ldq_e_T_1_bits_uop_debug_pc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_0 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_2 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_3 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_0 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_2 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_3 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_4 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_5 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_6 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_7 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_8 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_9 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_issued = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_issued; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_issued_partial_agen = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_issued_partial_dgen = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_iw_p1_speculative_child = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iw_p1_speculative_child : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_iw_p2_speculative_child = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iw_p2_speculative_child : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_p1_bypass_hint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_p2_bypass_hint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_p3_bypass_hint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_dis_col_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_dis_col_sel : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [11:0] _mem_ldq_e_T_1_bits_uop_br_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_mask : 12'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_br_tag = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_br_type = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_sfb = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_fence = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_fencei = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_sfence = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sfence; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_amo = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_eret = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_eret; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_rocc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_rocc; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_mov = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_mov; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ftq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_edge_inst = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_pc_lob = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_taken = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_imm_rename = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_imm_rename; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_imm_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_pimm = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [19:0] _mem_ldq_e_T_1_bits_uop_imm_packed = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_op1_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_op2_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ldst = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_wen = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren2 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren3 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap12 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap23 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagIn = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagOut = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_fromint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_toint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_fastpipe = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_fma = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_div = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_sqrt = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_wflags = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_vec = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_rob_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rob_idx : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_ldq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldq_idx : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stq_idx : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_rxq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ppred = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_prs1_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_prs2_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_prs3_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_ppred_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_stale_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_exception = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [63:0] _mem_ldq_e_T_1_bits_uop_exc_cause = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_mem_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_mem_size = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_mem_signed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_uses_ldq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_uses_stq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_unique = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_flush_on_commit = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_csr_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_ldst_is_rs1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_ldst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_dst_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs1_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs2_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_frs3_en = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fcn_dw = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_fcn_op = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_fp_rm = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_fp_typ = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_pf_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ae_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ma_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_bp_debug_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_bp_xcpt_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_debug_fsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_debug_tsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_addr_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [39:0] _mem_ldq_e_T_1_bits_addr_bits = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_addr_bits : 40'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_addr_is_virtual = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_addr_is_uncacheable = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_executed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_succeeded = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_order_fail = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_observed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [15:0] _mem_ldq_e_T_1_bits_st_dep_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_st_dep_mask : 16'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [7:0] _mem_ldq_e_T_1_bits_ld_byte_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_ld_byte_mask : 8'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_forward_std_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_forward_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_forward_stq_idx : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [63:0] _mem_ldq_e_T_1_bits_debug_wb_data = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_2_valid = fired_load_retry_0 ? mem_ldq_retry_e_valid : _mem_ldq_e_T_1_valid; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_inst : _mem_ldq_e_T_1_bits_uop_inst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_debug_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_inst : _mem_ldq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_rvc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_rvc : _mem_ldq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [39:0] _mem_ldq_e_T_2_bits_uop_debug_pc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_pc : _mem_ldq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_0 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_0 : _mem_ldq_e_T_1_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_1 : _mem_ldq_e_T_1_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_2 : _mem_ldq_e_T_1_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_3 : _mem_ldq_e_T_1_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_0 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_0 : _mem_ldq_e_T_1_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_1 : _mem_ldq_e_T_1_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_2 : _mem_ldq_e_T_1_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_3 : _mem_ldq_e_T_1_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_4 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_4 : _mem_ldq_e_T_1_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_5 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_5 : _mem_ldq_e_T_1_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_6 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_6 : _mem_ldq_e_T_1_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_7 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_7 : _mem_ldq_e_T_1_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_8 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_8 : _mem_ldq_e_T_1_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_9 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_9 : _mem_ldq_e_T_1_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_issued = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_issued : _mem_ldq_e_T_1_bits_uop_iw_issued; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_issued_partial_agen = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_issued_partial_agen : _mem_ldq_e_T_1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_issued_partial_dgen = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_issued_partial_dgen : _mem_ldq_e_T_1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_iw_p1_speculative_child = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p1_speculative_child : _mem_ldq_e_T_1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_iw_p2_speculative_child = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p2_speculative_child : _mem_ldq_e_T_1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_p1_bypass_hint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p1_bypass_hint : _mem_ldq_e_T_1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_p2_bypass_hint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p2_bypass_hint : _mem_ldq_e_T_1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_p3_bypass_hint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p3_bypass_hint : _mem_ldq_e_T_1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_dis_col_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_dis_col_sel : _mem_ldq_e_T_1_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [11:0] _mem_ldq_e_T_2_bits_uop_br_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_mask : _mem_ldq_e_T_1_bits_uop_br_mask; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_br_tag = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_tag : _mem_ldq_e_T_1_bits_uop_br_tag; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_br_type = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_type : _mem_ldq_e_T_1_bits_uop_br_type; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_sfb = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sfb : _mem_ldq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_fence = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fence : _mem_ldq_e_T_1_bits_uop_is_fence; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_fencei = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fencei : _mem_ldq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_sfence = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sfence : _mem_ldq_e_T_1_bits_uop_is_sfence; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_amo = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_amo : _mem_ldq_e_T_1_bits_uop_is_amo; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_eret = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_eret : _mem_ldq_e_T_1_bits_uop_is_eret; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_rocc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_rocc : _mem_ldq_e_T_1_bits_uop_is_rocc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_mov = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_mov : _mem_ldq_e_T_1_bits_uop_is_mov; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ftq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ftq_idx : _mem_ldq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_edge_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_edge_inst : _mem_ldq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_pc_lob = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pc_lob : _mem_ldq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_taken = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_taken : _mem_ldq_e_T_1_bits_uop_taken; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_imm_rename = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_rename : _mem_ldq_e_T_1_bits_uop_imm_rename; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_imm_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_sel : _mem_ldq_e_T_1_bits_uop_imm_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_pimm = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pimm : _mem_ldq_e_T_1_bits_uop_pimm; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [19:0] _mem_ldq_e_T_2_bits_uop_imm_packed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_packed : _mem_ldq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_op1_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_op1_sel : _mem_ldq_e_T_1_bits_uop_op1_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_op2_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_op2_sel : _mem_ldq_e_T_1_bits_uop_op2_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ldst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ldst : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_wen = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_wen : _mem_ldq_e_T_1_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ren1 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ren2 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ren3 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap12 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_swap12 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap23 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_swap23 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagIn = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagIn : _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagOut = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagOut : _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_fromint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_fromint : _mem_ldq_e_T_1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_toint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_toint : _mem_ldq_e_T_1_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_fastpipe = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_fastpipe : _mem_ldq_e_T_1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_fma = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_fma : _mem_ldq_e_T_1_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_div = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_div : _mem_ldq_e_T_1_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_sqrt = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_sqrt : _mem_ldq_e_T_1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_wflags = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_wflags : _mem_ldq_e_T_1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_vec = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_vec : _mem_ldq_e_T_1_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_rob_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rob_idx : _mem_ldq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_ldq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldq_idx : _mem_ldq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stq_idx : _mem_ldq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_rxq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rxq_idx : _mem_ldq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pdst : _mem_ldq_e_T_1_bits_uop_pdst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1 : _mem_ldq_e_T_1_bits_uop_prs1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2 : _mem_ldq_e_T_1_bits_uop_prs2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3 : _mem_ldq_e_T_1_bits_uop_prs3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ppred = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred : _mem_ldq_e_T_1_bits_uop_ppred; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_prs1_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1_busy : _mem_ldq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_prs2_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2_busy : _mem_ldq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_prs3_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3_busy : _mem_ldq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_ppred_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred_busy : _mem_ldq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_stale_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stale_pdst : _mem_ldq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_exception = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exception : _mem_ldq_e_T_1_bits_uop_exception; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [63:0] _mem_ldq_e_T_2_bits_uop_exc_cause = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exc_cause : _mem_ldq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_mem_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_cmd : _mem_ldq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_mem_size = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_size : _mem_ldq_e_T_1_bits_uop_mem_size; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_mem_signed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_signed : _mem_ldq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_uses_ldq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_ldq : _mem_ldq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_uses_stq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_stq : _mem_ldq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_unique = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_unique : _mem_ldq_e_T_1_bits_uop_is_unique; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_flush_on_commit = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_flush_on_commit : _mem_ldq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_csr_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_csr_cmd : _mem_ldq_e_T_1_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_ldst_is_rs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_ldst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst : _mem_ldq_e_T_1_bits_uop_ldst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1 : _mem_ldq_e_T_1_bits_uop_lrs1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2 : _mem_ldq_e_T_1_bits_uop_lrs2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs3 : _mem_ldq_e_T_1_bits_uop_lrs3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_dst_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_dst_rtype : _mem_ldq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs1_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1_rtype : _mem_ldq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs2_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2_rtype : _mem_ldq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_frs3_en = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_frs3_en : _mem_ldq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fcn_dw = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fcn_dw : _mem_ldq_e_T_1_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_fcn_op = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fcn_op : _mem_ldq_e_T_1_bits_uop_fcn_op; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_val : _mem_ldq_e_T_1_bits_uop_fp_val; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_fp_rm = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_rm : _mem_ldq_e_T_1_bits_uop_fp_rm; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_fp_typ = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_typ : _mem_ldq_e_T_1_bits_uop_fp_typ; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_pf_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_pf_if : _mem_ldq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ae_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ae_if : _mem_ldq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ma_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ma_if : _mem_ldq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_bp_debug_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_debug_if : _mem_ldq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_bp_xcpt_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_xcpt_if : _mem_ldq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_debug_fsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_fsrc : _mem_ldq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_debug_tsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_tsrc : _mem_ldq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_addr_valid = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_valid : _mem_ldq_e_T_1_bits_addr_valid; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [39:0] _mem_ldq_e_T_2_bits_addr_bits = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_bits : _mem_ldq_e_T_1_bits_addr_bits; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_addr_is_virtual = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_virtual : _mem_ldq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_addr_is_uncacheable = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_uncacheable : _mem_ldq_e_T_1_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_executed = fired_load_retry_0 ? mem_ldq_retry_e_bits_executed : _mem_ldq_e_T_1_bits_executed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_succeeded = fired_load_retry_0 ? mem_ldq_retry_e_bits_succeeded : _mem_ldq_e_T_1_bits_succeeded; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_order_fail = fired_load_retry_0 ? mem_ldq_retry_e_bits_order_fail : _mem_ldq_e_T_1_bits_order_fail; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_observed = fired_load_retry_0 ? mem_ldq_retry_e_bits_observed : _mem_ldq_e_T_1_bits_observed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [15:0] _mem_ldq_e_T_2_bits_st_dep_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_st_dep_mask : _mem_ldq_e_T_1_bits_st_dep_mask; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [7:0] _mem_ldq_e_T_2_bits_ld_byte_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_ld_byte_mask : _mem_ldq_e_T_1_bits_ld_byte_mask; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_forward_std_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_std_val : _mem_ldq_e_T_1_bits_forward_std_val; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_forward_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_stq_idx : _mem_ldq_e_T_1_bits_forward_stq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [63:0] _mem_ldq_e_T_2_bits_debug_wb_data = fired_load_retry_0 ? mem_ldq_retry_e_bits_debug_wb_data : _mem_ldq_e_T_1_bits_debug_wb_data; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_3_valid = _mem_ldq_e_T ? mem_ldq_incoming_e_0_valid : _mem_ldq_e_T_2_valid; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [31:0] _mem_ldq_e_T_3_bits_uop_inst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_inst : _mem_ldq_e_T_2_bits_uop_inst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [31:0] _mem_ldq_e_T_3_bits_uop_debug_inst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_inst : _mem_ldq_e_T_2_bits_uop_debug_inst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_rvc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_rvc : _mem_ldq_e_T_2_bits_uop_is_rvc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [39:0] _mem_ldq_e_T_3_bits_uop_debug_pc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_pc : _mem_ldq_e_T_2_bits_uop_debug_pc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_0 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_0 : _mem_ldq_e_T_2_bits_uop_iq_type_0; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_1 : _mem_ldq_e_T_2_bits_uop_iq_type_1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_2 : _mem_ldq_e_T_2_bits_uop_iq_type_2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_3 : _mem_ldq_e_T_2_bits_uop_iq_type_3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_0 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_0 : _mem_ldq_e_T_2_bits_uop_fu_code_0; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_1 : _mem_ldq_e_T_2_bits_uop_fu_code_1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_2 : _mem_ldq_e_T_2_bits_uop_fu_code_2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_3 : _mem_ldq_e_T_2_bits_uop_fu_code_3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_4 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_4 : _mem_ldq_e_T_2_bits_uop_fu_code_4; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_5 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_5 : _mem_ldq_e_T_2_bits_uop_fu_code_5; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_6 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_6 : _mem_ldq_e_T_2_bits_uop_fu_code_6; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_7 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_7 : _mem_ldq_e_T_2_bits_uop_fu_code_7; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_8 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_8 : _mem_ldq_e_T_2_bits_uop_fu_code_8; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_9 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_9 : _mem_ldq_e_T_2_bits_uop_fu_code_9; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_issued = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_issued : _mem_ldq_e_T_2_bits_uop_iw_issued; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_issued_partial_agen = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_agen : _mem_ldq_e_T_2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_issued_partial_dgen = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _mem_ldq_e_T_2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_iw_p1_speculative_child = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p1_speculative_child : _mem_ldq_e_T_2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_iw_p2_speculative_child = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p2_speculative_child : _mem_ldq_e_T_2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_p1_bypass_hint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _mem_ldq_e_T_2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_p2_bypass_hint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _mem_ldq_e_T_2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_p3_bypass_hint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _mem_ldq_e_T_2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_dis_col_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_dis_col_sel : _mem_ldq_e_T_2_bits_uop_dis_col_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [11:0] _mem_ldq_e_T_3_bits_uop_br_mask = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_br_mask : _mem_ldq_e_T_2_bits_uop_br_mask; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_uop_br_tag = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_br_tag : _mem_ldq_e_T_2_bits_uop_br_tag; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_uop_br_type = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_br_type : _mem_ldq_e_T_2_bits_uop_br_type; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_sfb = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_sfb : _mem_ldq_e_T_2_bits_uop_is_sfb; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_fence = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_fence : _mem_ldq_e_T_2_bits_uop_is_fence; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_fencei = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_fencei : _mem_ldq_e_T_2_bits_uop_is_fencei; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_sfence = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_sfence : _mem_ldq_e_T_2_bits_uop_is_sfence; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_amo = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_amo : _mem_ldq_e_T_2_bits_uop_is_amo; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_eret = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_eret : _mem_ldq_e_T_2_bits_uop_is_eret; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_sys_pc2epc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_rocc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_rocc : _mem_ldq_e_T_2_bits_uop_is_rocc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_mov = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_mov : _mem_ldq_e_T_2_bits_uop_is_mov; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_ftq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ftq_idx : _mem_ldq_e_T_2_bits_uop_ftq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_edge_inst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_edge_inst : _mem_ldq_e_T_2_bits_uop_edge_inst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_pc_lob = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_pc_lob : _mem_ldq_e_T_2_bits_uop_pc_lob; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_taken = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_taken : _mem_ldq_e_T_2_bits_uop_taken; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_imm_rename = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_imm_rename : _mem_ldq_e_T_2_bits_uop_imm_rename; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_imm_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_imm_sel : _mem_ldq_e_T_2_bits_uop_imm_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_pimm = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_pimm : _mem_ldq_e_T_2_bits_uop_pimm; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [19:0] _mem_ldq_e_T_3_bits_uop_imm_packed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_imm_packed : _mem_ldq_e_T_2_bits_uop_imm_packed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_op1_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_op1_sel : _mem_ldq_e_T_2_bits_uop_op1_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_op2_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_op2_sel : _mem_ldq_e_T_2_bits_uop_op2_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ldst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ldst : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_wen = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wen : _mem_ldq_e_T_2_bits_uop_fp_ctrl_wen; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap12 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap23 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagIn = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagOut = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_fromint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fromint : _mem_ldq_e_T_2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_toint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_toint : _mem_ldq_e_T_2_bits_uop_fp_ctrl_toint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_fastpipe = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _mem_ldq_e_T_2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_fma = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fma : _mem_ldq_e_T_2_bits_uop_fp_ctrl_fma; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_div = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_div : _mem_ldq_e_T_2_bits_uop_fp_ctrl_div; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_sqrt = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _mem_ldq_e_T_2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_wflags = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wflags : _mem_ldq_e_T_2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_vec = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_vec : _mem_ldq_e_T_2_bits_uop_fp_ctrl_vec; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_rob_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_rob_idx : _mem_ldq_e_T_2_bits_uop_rob_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_uop_ldq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ldq_idx : _mem_ldq_e_T_2_bits_uop_ldq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_uop_stq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_stq_idx : _mem_ldq_e_T_2_bits_uop_stq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_rxq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_rxq_idx : _mem_ldq_e_T_2_bits_uop_rxq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_pdst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_pdst : _mem_ldq_e_T_2_bits_uop_pdst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_prs1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs1 : _mem_ldq_e_T_2_bits_uop_prs1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_prs2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs2 : _mem_ldq_e_T_2_bits_uop_prs2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_prs3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs3 : _mem_ldq_e_T_2_bits_uop_prs3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_ppred = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ppred : _mem_ldq_e_T_2_bits_uop_ppred; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_prs1_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs1_busy : _mem_ldq_e_T_2_bits_uop_prs1_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_prs2_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs2_busy : _mem_ldq_e_T_2_bits_uop_prs2_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_prs3_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs3_busy : _mem_ldq_e_T_2_bits_uop_prs3_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_ppred_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ppred_busy : _mem_ldq_e_T_2_bits_uop_ppred_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_stale_pdst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_stale_pdst : _mem_ldq_e_T_2_bits_uop_stale_pdst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_exception = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_exception : _mem_ldq_e_T_2_bits_uop_exception; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [63:0] _mem_ldq_e_T_3_bits_uop_exc_cause = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_exc_cause : _mem_ldq_e_T_2_bits_uop_exc_cause; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_mem_cmd = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_mem_cmd : _mem_ldq_e_T_2_bits_uop_mem_cmd; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_mem_size = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_mem_size : _mem_ldq_e_T_2_bits_uop_mem_size; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_mem_signed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_mem_signed : _mem_ldq_e_T_2_bits_uop_mem_signed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_uses_ldq = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_uses_ldq : _mem_ldq_e_T_2_bits_uop_uses_ldq; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_uses_stq = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_uses_stq : _mem_ldq_e_T_2_bits_uop_uses_stq; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_unique = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_unique : _mem_ldq_e_T_2_bits_uop_is_unique; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_flush_on_commit = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_flush_on_commit : _mem_ldq_e_T_2_bits_uop_flush_on_commit; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_csr_cmd = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_csr_cmd : _mem_ldq_e_T_2_bits_uop_csr_cmd; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_ldst_is_rs1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_2_bits_uop_ldst_is_rs1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_ldst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ldst : _mem_ldq_e_T_2_bits_uop_ldst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_lrs1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs1 : _mem_ldq_e_T_2_bits_uop_lrs1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_lrs2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs2 : _mem_ldq_e_T_2_bits_uop_lrs2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_lrs3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs3 : _mem_ldq_e_T_2_bits_uop_lrs3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_dst_rtype = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_dst_rtype : _mem_ldq_e_T_2_bits_uop_dst_rtype; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_lrs1_rtype = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs1_rtype : _mem_ldq_e_T_2_bits_uop_lrs1_rtype; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_lrs2_rtype = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs2_rtype : _mem_ldq_e_T_2_bits_uop_lrs2_rtype; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_frs3_en = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_frs3_en : _mem_ldq_e_T_2_bits_uop_frs3_en; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fcn_dw = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fcn_dw : _mem_ldq_e_T_2_bits_uop_fcn_dw; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_fcn_op = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fcn_op : _mem_ldq_e_T_2_bits_uop_fcn_op; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_val = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_val : _mem_ldq_e_T_2_bits_uop_fp_val; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_fp_rm = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_rm : _mem_ldq_e_T_2_bits_uop_fp_rm; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_fp_typ = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_typ : _mem_ldq_e_T_2_bits_uop_fp_typ; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_xcpt_pf_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_ldq_e_T_2_bits_uop_xcpt_pf_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_xcpt_ae_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_ldq_e_T_2_bits_uop_xcpt_ae_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_xcpt_ma_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_ldq_e_T_2_bits_uop_xcpt_ma_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_bp_debug_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_bp_debug_if : _mem_ldq_e_T_2_bits_uop_bp_debug_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_bp_xcpt_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_ldq_e_T_2_bits_uop_bp_xcpt_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_debug_fsrc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_fsrc : _mem_ldq_e_T_2_bits_uop_debug_fsrc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_debug_tsrc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_tsrc : _mem_ldq_e_T_2_bits_uop_debug_tsrc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_addr_valid = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_valid : _mem_ldq_e_T_2_bits_addr_valid; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [39:0] _mem_ldq_e_T_3_bits_addr_bits = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_bits : _mem_ldq_e_T_2_bits_addr_bits; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_addr_is_virtual = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_is_virtual : _mem_ldq_e_T_2_bits_addr_is_virtual; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_addr_is_uncacheable = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_is_uncacheable : _mem_ldq_e_T_2_bits_addr_is_uncacheable; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_executed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_executed : _mem_ldq_e_T_2_bits_executed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_succeeded = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_succeeded : _mem_ldq_e_T_2_bits_succeeded; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_order_fail = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_order_fail : _mem_ldq_e_T_2_bits_order_fail; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_observed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_observed : _mem_ldq_e_T_2_bits_observed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [15:0] _mem_ldq_e_T_3_bits_st_dep_mask = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_st_dep_mask : _mem_ldq_e_T_2_bits_st_dep_mask; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [7:0] _mem_ldq_e_T_3_bits_ld_byte_mask = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_ld_byte_mask : _mem_ldq_e_T_2_bits_ld_byte_mask; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_forward_std_val = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_forward_std_val : _mem_ldq_e_T_2_bits_forward_std_val; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_forward_stq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_forward_stq_idx : _mem_ldq_e_T_2_bits_forward_stq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [63:0] _mem_ldq_e_T_3_bits_debug_wb_data = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_debug_wb_data : _mem_ldq_e_T_2_bits_debug_wb_data; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire mem_ldq_e_0_valid = _mem_ldq_e_T_3_valid; // @[lsu.scala:321:49, :1060:33] wire [31:0] mem_ldq_e_0_bits_uop_inst = _mem_ldq_e_T_3_bits_uop_inst; // @[lsu.scala:321:49, :1060:33] wire [31:0] mem_ldq_e_0_bits_uop_debug_inst = _mem_ldq_e_T_3_bits_uop_debug_inst; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_rvc = _mem_ldq_e_T_3_bits_uop_is_rvc; // @[lsu.scala:321:49, :1060:33] wire [39:0] mem_ldq_e_0_bits_uop_debug_pc = _mem_ldq_e_T_3_bits_uop_debug_pc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_0 = _mem_ldq_e_T_3_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_1 = _mem_ldq_e_T_3_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_2 = _mem_ldq_e_T_3_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_3 = _mem_ldq_e_T_3_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_0 = _mem_ldq_e_T_3_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_1 = _mem_ldq_e_T_3_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_2 = _mem_ldq_e_T_3_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_3 = _mem_ldq_e_T_3_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_4 = _mem_ldq_e_T_3_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_5 = _mem_ldq_e_T_3_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_6 = _mem_ldq_e_T_3_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_7 = _mem_ldq_e_T_3_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_8 = _mem_ldq_e_T_3_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_9 = _mem_ldq_e_T_3_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_issued = _mem_ldq_e_T_3_bits_uop_iw_issued; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_issued_partial_agen = _mem_ldq_e_T_3_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_issued_partial_dgen = _mem_ldq_e_T_3_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_iw_p1_speculative_child = _mem_ldq_e_T_3_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_iw_p2_speculative_child = _mem_ldq_e_T_3_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_p1_bypass_hint = _mem_ldq_e_T_3_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_p2_bypass_hint = _mem_ldq_e_T_3_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_p3_bypass_hint = _mem_ldq_e_T_3_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_dis_col_sel = _mem_ldq_e_T_3_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1060:33] wire [11:0] mem_ldq_e_0_bits_uop_br_mask = _mem_ldq_e_T_3_bits_uop_br_mask; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_uop_br_tag = _mem_ldq_e_T_3_bits_uop_br_tag; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_uop_br_type = _mem_ldq_e_T_3_bits_uop_br_type; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_sfb = _mem_ldq_e_T_3_bits_uop_is_sfb; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_fence = _mem_ldq_e_T_3_bits_uop_is_fence; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_fencei = _mem_ldq_e_T_3_bits_uop_is_fencei; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_sfence = _mem_ldq_e_T_3_bits_uop_is_sfence; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_amo = _mem_ldq_e_T_3_bits_uop_is_amo; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_eret = _mem_ldq_e_T_3_bits_uop_is_eret; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_sys_pc2epc = _mem_ldq_e_T_3_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_rocc = _mem_ldq_e_T_3_bits_uop_is_rocc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_mov = _mem_ldq_e_T_3_bits_uop_is_mov; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_ftq_idx = _mem_ldq_e_T_3_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_edge_inst = _mem_ldq_e_T_3_bits_uop_edge_inst; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_pc_lob = _mem_ldq_e_T_3_bits_uop_pc_lob; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_taken = _mem_ldq_e_T_3_bits_uop_taken; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_imm_rename = _mem_ldq_e_T_3_bits_uop_imm_rename; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_imm_sel = _mem_ldq_e_T_3_bits_uop_imm_sel; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_pimm = _mem_ldq_e_T_3_bits_uop_pimm; // @[lsu.scala:321:49, :1060:33] wire [19:0] mem_ldq_e_0_bits_uop_imm_packed = _mem_ldq_e_T_3_bits_uop_imm_packed; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_op1_sel = _mem_ldq_e_T_3_bits_uop_op1_sel; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_op2_sel = _mem_ldq_e_T_3_bits_uop_op2_sel; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ldst = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_wen = _mem_ldq_e_T_3_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ren1 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ren2 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ren3 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_swap12 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_swap23 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_fp_ctrl_typeTagIn = _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_fp_ctrl_typeTagOut = _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_fromint = _mem_ldq_e_T_3_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_toint = _mem_ldq_e_T_3_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_fastpipe = _mem_ldq_e_T_3_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_fma = _mem_ldq_e_T_3_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_div = _mem_ldq_e_T_3_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_sqrt = _mem_ldq_e_T_3_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_wflags = _mem_ldq_e_T_3_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_vec = _mem_ldq_e_T_3_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_rob_idx = _mem_ldq_e_T_3_bits_uop_rob_idx; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_uop_ldq_idx = _mem_ldq_e_T_3_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_uop_stq_idx = _mem_ldq_e_T_3_bits_uop_stq_idx; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_rxq_idx = _mem_ldq_e_T_3_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_pdst = _mem_ldq_e_T_3_bits_uop_pdst; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_prs1 = _mem_ldq_e_T_3_bits_uop_prs1; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_prs2 = _mem_ldq_e_T_3_bits_uop_prs2; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_prs3 = _mem_ldq_e_T_3_bits_uop_prs3; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_ppred = _mem_ldq_e_T_3_bits_uop_ppred; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_prs1_busy = _mem_ldq_e_T_3_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_prs2_busy = _mem_ldq_e_T_3_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_prs3_busy = _mem_ldq_e_T_3_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_ppred_busy = _mem_ldq_e_T_3_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_stale_pdst = _mem_ldq_e_T_3_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_exception = _mem_ldq_e_T_3_bits_uop_exception; // @[lsu.scala:321:49, :1060:33] wire [63:0] mem_ldq_e_0_bits_uop_exc_cause = _mem_ldq_e_T_3_bits_uop_exc_cause; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_mem_cmd = _mem_ldq_e_T_3_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_mem_size = _mem_ldq_e_T_3_bits_uop_mem_size; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_mem_signed = _mem_ldq_e_T_3_bits_uop_mem_signed; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_uses_ldq = _mem_ldq_e_T_3_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_uses_stq = _mem_ldq_e_T_3_bits_uop_uses_stq; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_unique = _mem_ldq_e_T_3_bits_uop_is_unique; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_flush_on_commit = _mem_ldq_e_T_3_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_csr_cmd = _mem_ldq_e_T_3_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_ldst_is_rs1 = _mem_ldq_e_T_3_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_ldst = _mem_ldq_e_T_3_bits_uop_ldst; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs1 = _mem_ldq_e_T_3_bits_uop_lrs1; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs2 = _mem_ldq_e_T_3_bits_uop_lrs2; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs3 = _mem_ldq_e_T_3_bits_uop_lrs3; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_dst_rtype = _mem_ldq_e_T_3_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs1_rtype = _mem_ldq_e_T_3_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs2_rtype = _mem_ldq_e_T_3_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_frs3_en = _mem_ldq_e_T_3_bits_uop_frs3_en; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fcn_dw = _mem_ldq_e_T_3_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_fcn_op = _mem_ldq_e_T_3_bits_uop_fcn_op; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_val = _mem_ldq_e_T_3_bits_uop_fp_val; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_fp_rm = _mem_ldq_e_T_3_bits_uop_fp_rm; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_fp_typ = _mem_ldq_e_T_3_bits_uop_fp_typ; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_xcpt_pf_if = _mem_ldq_e_T_3_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_xcpt_ae_if = _mem_ldq_e_T_3_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_xcpt_ma_if = _mem_ldq_e_T_3_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_bp_debug_if = _mem_ldq_e_T_3_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_bp_xcpt_if = _mem_ldq_e_T_3_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_debug_fsrc = _mem_ldq_e_T_3_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_debug_tsrc = _mem_ldq_e_T_3_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_addr_valid = _mem_ldq_e_T_3_bits_addr_valid; // @[lsu.scala:321:49, :1060:33] wire [39:0] mem_ldq_e_0_bits_addr_bits = _mem_ldq_e_T_3_bits_addr_bits; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_addr_is_virtual = _mem_ldq_e_T_3_bits_addr_is_virtual; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_addr_is_uncacheable = _mem_ldq_e_T_3_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_executed = _mem_ldq_e_T_3_bits_executed; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_succeeded = _mem_ldq_e_T_3_bits_succeeded; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_order_fail = _mem_ldq_e_T_3_bits_order_fail; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_observed = _mem_ldq_e_T_3_bits_observed; // @[lsu.scala:321:49, :1060:33] wire [15:0] mem_ldq_e_0_bits_st_dep_mask = _mem_ldq_e_T_3_bits_st_dep_mask; // @[lsu.scala:321:49, :1060:33] wire [7:0] mem_ldq_e_0_bits_ld_byte_mask = _mem_ldq_e_T_3_bits_ld_byte_mask; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_forward_std_val = _mem_ldq_e_T_3_bits_forward_std_val; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_forward_stq_idx = _mem_ldq_e_T_3_bits_forward_stq_idx; // @[lsu.scala:321:49, :1060:33] wire [63:0] mem_ldq_e_0_bits_debug_wb_data = _mem_ldq_e_T_3_bits_debug_wb_data; // @[lsu.scala:321:49, :1060:33] wire [15:0] lcam_st_dep_mask_0 = mem_ldq_e_0_bits_st_dep_mask; // @[lsu.scala:321:49] wire _mem_stq_e_T_valid = fired_store_retry_0 & mem_stq_retry_e_valid; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [31:0] _mem_stq_e_T_bits_uop_inst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [31:0] _mem_stq_e_T_bits_uop_debug_inst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_rvc = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [39:0] _mem_stq_e_T_bits_uop_debug_pc = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_0 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_2 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_3 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_0 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_2 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_3 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_4 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_5 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_6 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_7 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_8 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_9 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_issued = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_issued; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_issued_partial_agen = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_issued_partial_dgen = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_iw_p1_speculative_child = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_iw_p1_speculative_child : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_iw_p2_speculative_child = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_iw_p2_speculative_child : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_p1_bypass_hint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_p2_bypass_hint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_p3_bypass_hint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_dis_col_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_dis_col_sel : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [11:0] _mem_stq_e_T_bits_uop_br_mask = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_br_mask : 12'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [3:0] _mem_stq_e_T_bits_uop_br_tag = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [3:0] _mem_stq_e_T_bits_uop_br_type = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_sfb = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_fence = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_fencei = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_sfence = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_sfence; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_amo = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_eret = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_eret; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_sys_pc2epc = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_rocc = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_rocc; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_mov = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_mov; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_ftq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_edge_inst = fired_store_retry_0 & mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_pc_lob = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_taken = fired_store_retry_0 & mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_imm_rename = fired_store_retry_0 & mem_stq_retry_e_bits_uop_imm_rename; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_imm_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_pimm = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [19:0] _mem_stq_e_T_bits_uop_imm_packed = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_op1_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_op2_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ldst = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_wen = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ren1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ren2 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ren3 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_swap12 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_swap23 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_fp_ctrl_typeTagIn = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_fp_ctrl_typeTagOut = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_fromint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_toint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_fastpipe = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_fma = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_div = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_sqrt = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_wflags = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_vec = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_rob_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_rob_idx : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [3:0] _mem_stq_e_T_bits_uop_ldq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ldq_idx : 4'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [3:0] _mem_stq_e_T_bits_uop_stq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_stq_idx : 4'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_rxq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_pdst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_prs1 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_prs2 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_prs3 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_ppred = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_prs1_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_prs2_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_prs3_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_ppred_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_stale_pdst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_exception = fired_store_retry_0 & mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [63:0] _mem_stq_e_T_bits_uop_exc_cause = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_mem_cmd = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_mem_size = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_mem_signed = fired_store_retry_0 & mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_uses_ldq = fired_store_retry_0 & mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_uses_stq = fired_store_retry_0 & mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_unique = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_flush_on_commit = fired_store_retry_0 & mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_csr_cmd = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_ldst_is_rs1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_ldst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_lrs1 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_lrs2 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_lrs3 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_dst_rtype = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_lrs1_rtype = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_lrs2_rtype = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_frs3_en = fired_store_retry_0 & mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fcn_dw = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_fcn_op = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_val = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_fp_rm = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_fp_typ = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_xcpt_pf_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_xcpt_ae_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_xcpt_ma_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_bp_debug_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_bp_xcpt_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_debug_fsrc = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_debug_tsrc = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_addr_valid = fired_store_retry_0 & mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [39:0] _mem_stq_e_T_bits_addr_bits = fired_store_retry_0 ? mem_stq_retry_e_bits_addr_bits : 40'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_addr_is_virtual = fired_store_retry_0 & mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_data_valid = fired_store_retry_0 & mem_stq_retry_e_bits_data_valid; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [63:0] _mem_stq_e_T_bits_data_bits = fired_store_retry_0 ? mem_stq_retry_e_bits_data_bits : 64'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_committed = fired_store_retry_0 & mem_stq_retry_e_bits_committed; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_succeeded = fired_store_retry_0 & mem_stq_retry_e_bits_succeeded; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_can_execute = fired_store_retry_0 & mem_stq_retry_e_bits_can_execute; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_cleared = fired_store_retry_0 & mem_stq_retry_e_bits_cleared; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [63:0] _mem_stq_e_T_bits_debug_wb_data = fired_store_retry_0 ? mem_stq_retry_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_1_valid = fired_store_agen_0 ? mem_stq_incoming_e_0_valid : _mem_stq_e_T_valid; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [31:0] _mem_stq_e_T_1_bits_uop_inst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_inst : _mem_stq_e_T_bits_uop_inst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [31:0] _mem_stq_e_T_1_bits_uop_debug_inst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_inst : _mem_stq_e_T_bits_uop_debug_inst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_rvc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_rvc : _mem_stq_e_T_bits_uop_is_rvc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [39:0] _mem_stq_e_T_1_bits_uop_debug_pc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_pc : _mem_stq_e_T_bits_uop_debug_pc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_0 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_0 : _mem_stq_e_T_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_1 : _mem_stq_e_T_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_2 : _mem_stq_e_T_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_3 : _mem_stq_e_T_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_0 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_0 : _mem_stq_e_T_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_1 : _mem_stq_e_T_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_2 : _mem_stq_e_T_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_3 : _mem_stq_e_T_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_4 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_4 : _mem_stq_e_T_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_5 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_5 : _mem_stq_e_T_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_6 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_6 : _mem_stq_e_T_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_7 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_7 : _mem_stq_e_T_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_8 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_8 : _mem_stq_e_T_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_9 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_9 : _mem_stq_e_T_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_issued = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_issued : _mem_stq_e_T_bits_uop_iw_issued; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_issued_partial_agen = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_issued_partial_agen : _mem_stq_e_T_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_issued_partial_dgen = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _mem_stq_e_T_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_iw_p1_speculative_child = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p1_speculative_child : _mem_stq_e_T_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_iw_p2_speculative_child = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p2_speculative_child : _mem_stq_e_T_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_p1_bypass_hint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _mem_stq_e_T_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_p2_bypass_hint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _mem_stq_e_T_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_p3_bypass_hint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _mem_stq_e_T_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_dis_col_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_dis_col_sel : _mem_stq_e_T_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [11:0] _mem_stq_e_T_1_bits_uop_br_mask = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_br_mask : _mem_stq_e_T_bits_uop_br_mask; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [3:0] _mem_stq_e_T_1_bits_uop_br_tag = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_br_tag : _mem_stq_e_T_bits_uop_br_tag; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [3:0] _mem_stq_e_T_1_bits_uop_br_type = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_br_type : _mem_stq_e_T_bits_uop_br_type; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_sfb = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_sfb : _mem_stq_e_T_bits_uop_is_sfb; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_fence = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_fence : _mem_stq_e_T_bits_uop_is_fence; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_fencei = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_fencei : _mem_stq_e_T_bits_uop_is_fencei; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_sfence = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_sfence : _mem_stq_e_T_bits_uop_is_sfence; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_amo = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_amo : _mem_stq_e_T_bits_uop_is_amo; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_eret = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_eret : _mem_stq_e_T_bits_uop_is_eret; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_sys_pc2epc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_stq_e_T_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_rocc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_rocc : _mem_stq_e_T_bits_uop_is_rocc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_mov = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_mov : _mem_stq_e_T_bits_uop_is_mov; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ftq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ftq_idx : _mem_stq_e_T_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_edge_inst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_edge_inst : _mem_stq_e_T_bits_uop_edge_inst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_pc_lob = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_pc_lob : _mem_stq_e_T_bits_uop_pc_lob; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_taken = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_taken : _mem_stq_e_T_bits_uop_taken; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_imm_rename = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_imm_rename : _mem_stq_e_T_bits_uop_imm_rename; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_imm_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_imm_sel : _mem_stq_e_T_bits_uop_imm_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_pimm = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_pimm : _mem_stq_e_T_bits_uop_pimm; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [19:0] _mem_stq_e_T_1_bits_uop_imm_packed = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_imm_packed : _mem_stq_e_T_bits_uop_imm_packed; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_op1_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_op1_sel : _mem_stq_e_T_bits_uop_op1_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_op2_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_op2_sel : _mem_stq_e_T_bits_uop_op2_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ldst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ldst : _mem_stq_e_T_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_wen = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_wen : _mem_stq_e_T_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ren1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _mem_stq_e_T_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ren2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _mem_stq_e_T_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ren3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _mem_stq_e_T_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_swap12 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _mem_stq_e_T_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_swap23 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _mem_stq_e_T_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagIn = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _mem_stq_e_T_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagOut = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _mem_stq_e_T_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_fromint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_fromint : _mem_stq_e_T_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_toint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_toint : _mem_stq_e_T_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_fastpipe = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _mem_stq_e_T_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_fma = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_fma : _mem_stq_e_T_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_div = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_div : _mem_stq_e_T_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_sqrt = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _mem_stq_e_T_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_wflags = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_wflags : _mem_stq_e_T_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_vec = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_vec : _mem_stq_e_T_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_rob_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_rob_idx : _mem_stq_e_T_bits_uop_rob_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [3:0] _mem_stq_e_T_1_bits_uop_ldq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ldq_idx : _mem_stq_e_T_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [3:0] _mem_stq_e_T_1_bits_uop_stq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_stq_idx : _mem_stq_e_T_bits_uop_stq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_rxq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_rxq_idx : _mem_stq_e_T_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_pdst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_pdst : _mem_stq_e_T_bits_uop_pdst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs1 : _mem_stq_e_T_bits_uop_prs1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs2 : _mem_stq_e_T_bits_uop_prs2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs3 : _mem_stq_e_T_bits_uop_prs3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ppred = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ppred : _mem_stq_e_T_bits_uop_ppred; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_prs1_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs1_busy : _mem_stq_e_T_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_prs2_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs2_busy : _mem_stq_e_T_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_prs3_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs3_busy : _mem_stq_e_T_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_ppred_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ppred_busy : _mem_stq_e_T_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_stale_pdst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_stale_pdst : _mem_stq_e_T_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_exception = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_exception : _mem_stq_e_T_bits_uop_exception; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [63:0] _mem_stq_e_T_1_bits_uop_exc_cause = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_exc_cause : _mem_stq_e_T_bits_uop_exc_cause; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_mem_cmd = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_mem_cmd : _mem_stq_e_T_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_mem_size = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_mem_size : _mem_stq_e_T_bits_uop_mem_size; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_mem_signed = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_mem_signed : _mem_stq_e_T_bits_uop_mem_signed; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_uses_ldq = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_uses_ldq : _mem_stq_e_T_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_uses_stq = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_uses_stq : _mem_stq_e_T_bits_uop_uses_stq; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_unique = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_unique : _mem_stq_e_T_bits_uop_is_unique; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_flush_on_commit = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_flush_on_commit : _mem_stq_e_T_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_csr_cmd = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_csr_cmd : _mem_stq_e_T_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_ldst_is_rs1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_stq_e_T_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_ldst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ldst : _mem_stq_e_T_bits_uop_ldst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs1 : _mem_stq_e_T_bits_uop_lrs1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs2 : _mem_stq_e_T_bits_uop_lrs2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs3 : _mem_stq_e_T_bits_uop_lrs3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_dst_rtype = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_dst_rtype : _mem_stq_e_T_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs1_rtype = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs1_rtype : _mem_stq_e_T_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs2_rtype = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs2_rtype : _mem_stq_e_T_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_frs3_en = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_frs3_en : _mem_stq_e_T_bits_uop_frs3_en; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fcn_dw = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fcn_dw : _mem_stq_e_T_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_fcn_op = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fcn_op : _mem_stq_e_T_bits_uop_fcn_op; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_val = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_val : _mem_stq_e_T_bits_uop_fp_val; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_fp_rm = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_rm : _mem_stq_e_T_bits_uop_fp_rm; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_fp_typ = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_typ : _mem_stq_e_T_bits_uop_fp_typ; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_xcpt_pf_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_stq_e_T_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ae_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_stq_e_T_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ma_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_stq_e_T_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_bp_debug_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_bp_debug_if : _mem_stq_e_T_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_bp_xcpt_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_stq_e_T_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_debug_fsrc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_fsrc : _mem_stq_e_T_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_debug_tsrc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_tsrc : _mem_stq_e_T_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_addr_valid = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_addr_valid : _mem_stq_e_T_bits_addr_valid; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [39:0] _mem_stq_e_T_1_bits_addr_bits = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_addr_bits : _mem_stq_e_T_bits_addr_bits; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_addr_is_virtual = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_addr_is_virtual : _mem_stq_e_T_bits_addr_is_virtual; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_data_valid = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_data_valid : _mem_stq_e_T_bits_data_valid; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [63:0] _mem_stq_e_T_1_bits_data_bits = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_data_bits : _mem_stq_e_T_bits_data_bits; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_committed = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_committed : _mem_stq_e_T_bits_committed; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_succeeded = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_succeeded : _mem_stq_e_T_bits_succeeded; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_can_execute = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_can_execute : _mem_stq_e_T_bits_can_execute; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_cleared = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_cleared : _mem_stq_e_T_bits_cleared; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [63:0] _mem_stq_e_T_1_bits_debug_wb_data = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_debug_wb_data : _mem_stq_e_T_bits_debug_wb_data; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire mem_stq_e_0_valid = _mem_stq_e_T_1_valid; // @[lsu.scala:321:49, :1066:33] wire [31:0] mem_stq_e_0_bits_uop_inst = _mem_stq_e_T_1_bits_uop_inst; // @[lsu.scala:321:49, :1066:33] wire [31:0] mem_stq_e_0_bits_uop_debug_inst = _mem_stq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_rvc = _mem_stq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:321:49, :1066:33] wire [39:0] mem_stq_e_0_bits_uop_debug_pc = _mem_stq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_0 = _mem_stq_e_T_1_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_1 = _mem_stq_e_T_1_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_2 = _mem_stq_e_T_1_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_3 = _mem_stq_e_T_1_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_0 = _mem_stq_e_T_1_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_1 = _mem_stq_e_T_1_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_2 = _mem_stq_e_T_1_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_3 = _mem_stq_e_T_1_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_4 = _mem_stq_e_T_1_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_5 = _mem_stq_e_T_1_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_6 = _mem_stq_e_T_1_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_7 = _mem_stq_e_T_1_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_8 = _mem_stq_e_T_1_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_9 = _mem_stq_e_T_1_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_issued = _mem_stq_e_T_1_bits_uop_iw_issued; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_issued_partial_agen = _mem_stq_e_T_1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_issued_partial_dgen = _mem_stq_e_T_1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_iw_p1_speculative_child = _mem_stq_e_T_1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_iw_p2_speculative_child = _mem_stq_e_T_1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_p1_bypass_hint = _mem_stq_e_T_1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_p2_bypass_hint = _mem_stq_e_T_1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_p3_bypass_hint = _mem_stq_e_T_1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_dis_col_sel = _mem_stq_e_T_1_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1066:33] wire [11:0] mem_stq_e_0_bits_uop_br_mask = _mem_stq_e_T_1_bits_uop_br_mask; // @[lsu.scala:321:49, :1066:33] wire [3:0] mem_stq_e_0_bits_uop_br_tag = _mem_stq_e_T_1_bits_uop_br_tag; // @[lsu.scala:321:49, :1066:33] wire [3:0] mem_stq_e_0_bits_uop_br_type = _mem_stq_e_T_1_bits_uop_br_type; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_sfb = _mem_stq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_fence = _mem_stq_e_T_1_bits_uop_is_fence; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_fencei = _mem_stq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_sfence = _mem_stq_e_T_1_bits_uop_is_sfence; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_amo = _mem_stq_e_T_1_bits_uop_is_amo; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_eret = _mem_stq_e_T_1_bits_uop_is_eret; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_sys_pc2epc = _mem_stq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_rocc = _mem_stq_e_T_1_bits_uop_is_rocc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_mov = _mem_stq_e_T_1_bits_uop_is_mov; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_ftq_idx = _mem_stq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_edge_inst = _mem_stq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_pc_lob = _mem_stq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_taken = _mem_stq_e_T_1_bits_uop_taken; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_imm_rename = _mem_stq_e_T_1_bits_uop_imm_rename; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_imm_sel = _mem_stq_e_T_1_bits_uop_imm_sel; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_pimm = _mem_stq_e_T_1_bits_uop_pimm; // @[lsu.scala:321:49, :1066:33] wire [19:0] mem_stq_e_0_bits_uop_imm_packed = _mem_stq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_op1_sel = _mem_stq_e_T_1_bits_uop_op1_sel; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_op2_sel = _mem_stq_e_T_1_bits_uop_op2_sel; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ldst = _mem_stq_e_T_1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_wen = _mem_stq_e_T_1_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ren1 = _mem_stq_e_T_1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ren2 = _mem_stq_e_T_1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ren3 = _mem_stq_e_T_1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_swap12 = _mem_stq_e_T_1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_swap23 = _mem_stq_e_T_1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_fp_ctrl_typeTagIn = _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_fp_ctrl_typeTagOut = _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_fromint = _mem_stq_e_T_1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_toint = _mem_stq_e_T_1_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_fastpipe = _mem_stq_e_T_1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_fma = _mem_stq_e_T_1_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_div = _mem_stq_e_T_1_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_sqrt = _mem_stq_e_T_1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_wflags = _mem_stq_e_T_1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_vec = _mem_stq_e_T_1_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_rob_idx = _mem_stq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:321:49, :1066:33] wire [3:0] mem_stq_e_0_bits_uop_ldq_idx = _mem_stq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1066:33] wire [3:0] mem_stq_e_0_bits_uop_stq_idx = _mem_stq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_rxq_idx = _mem_stq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_pdst = _mem_stq_e_T_1_bits_uop_pdst; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_prs1 = _mem_stq_e_T_1_bits_uop_prs1; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_prs2 = _mem_stq_e_T_1_bits_uop_prs2; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_prs3 = _mem_stq_e_T_1_bits_uop_prs3; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_ppred = _mem_stq_e_T_1_bits_uop_ppred; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_prs1_busy = _mem_stq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_prs2_busy = _mem_stq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_prs3_busy = _mem_stq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_ppred_busy = _mem_stq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_stale_pdst = _mem_stq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_exception = _mem_stq_e_T_1_bits_uop_exception; // @[lsu.scala:321:49, :1066:33] wire [63:0] mem_stq_e_0_bits_uop_exc_cause = _mem_stq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_mem_cmd = _mem_stq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_mem_size = _mem_stq_e_T_1_bits_uop_mem_size; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_mem_signed = _mem_stq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_uses_ldq = _mem_stq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_uses_stq = _mem_stq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_unique = _mem_stq_e_T_1_bits_uop_is_unique; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_flush_on_commit = _mem_stq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_csr_cmd = _mem_stq_e_T_1_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_ldst_is_rs1 = _mem_stq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_ldst = _mem_stq_e_T_1_bits_uop_ldst; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_lrs1 = _mem_stq_e_T_1_bits_uop_lrs1; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_lrs2 = _mem_stq_e_T_1_bits_uop_lrs2; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_lrs3 = _mem_stq_e_T_1_bits_uop_lrs3; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_dst_rtype = _mem_stq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_lrs1_rtype = _mem_stq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_lrs2_rtype = _mem_stq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_frs3_en = _mem_stq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fcn_dw = _mem_stq_e_T_1_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_fcn_op = _mem_stq_e_T_1_bits_uop_fcn_op; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_val = _mem_stq_e_T_1_bits_uop_fp_val; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_fp_rm = _mem_stq_e_T_1_bits_uop_fp_rm; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_fp_typ = _mem_stq_e_T_1_bits_uop_fp_typ; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_xcpt_pf_if = _mem_stq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_xcpt_ae_if = _mem_stq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_xcpt_ma_if = _mem_stq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_bp_debug_if = _mem_stq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_bp_xcpt_if = _mem_stq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_debug_fsrc = _mem_stq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_debug_tsrc = _mem_stq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_addr_valid = _mem_stq_e_T_1_bits_addr_valid; // @[lsu.scala:321:49, :1066:33] wire [39:0] mem_stq_e_0_bits_addr_bits = _mem_stq_e_T_1_bits_addr_bits; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_addr_is_virtual = _mem_stq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_data_valid = _mem_stq_e_T_1_bits_data_valid; // @[lsu.scala:321:49, :1066:33] wire [63:0] mem_stq_e_0_bits_data_bits = _mem_stq_e_T_1_bits_data_bits; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_committed = _mem_stq_e_T_1_bits_committed; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_succeeded = _mem_stq_e_T_1_bits_succeeded; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_can_execute = _mem_stq_e_T_1_bits_can_execute; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_cleared = _mem_stq_e_T_1_bits_cleared; // @[lsu.scala:321:49, :1066:33] wire [63:0] mem_stq_e_0_bits_debug_wb_data = _mem_stq_e_T_1_bits_debug_wb_data; // @[lsu.scala:321:49, :1066:33] reg mem_tlb_miss_0; // @[lsu.scala:1070:41] reg mem_tlb_uncacheable_0; // @[lsu.scala:1071:41] reg [39:0] mem_paddr_0; // @[lsu.scala:1072:41] wire _stq_clr_head_idx_T = ~stq_cleared_0; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_1 = stq_valid_0 & _stq_clr_head_idx_T; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_2 = ~stq_cleared_1; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_3 = stq_valid_1 & _stq_clr_head_idx_T_2; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_4 = ~stq_cleared_2; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_5 = stq_valid_2 & _stq_clr_head_idx_T_4; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_6 = ~stq_cleared_3; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_7 = stq_valid_3 & _stq_clr_head_idx_T_6; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_8 = ~stq_cleared_4; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_9 = stq_valid_4 & _stq_clr_head_idx_T_8; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_10 = ~stq_cleared_5; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_11 = stq_valid_5 & _stq_clr_head_idx_T_10; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_12 = ~stq_cleared_6; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_13 = stq_valid_6 & _stq_clr_head_idx_T_12; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_14 = ~stq_cleared_7; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_15 = stq_valid_7 & _stq_clr_head_idx_T_14; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_16 = ~stq_cleared_8; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_17 = stq_valid_8 & _stq_clr_head_idx_T_16; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_18 = ~stq_cleared_9; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_19 = stq_valid_9 & _stq_clr_head_idx_T_18; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_20 = ~stq_cleared_10; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_21 = stq_valid_10 & _stq_clr_head_idx_T_20; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_22 = ~stq_cleared_11; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_23 = stq_valid_11 & _stq_clr_head_idx_T_22; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_24 = ~stq_cleared_12; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_25 = stq_valid_12 & _stq_clr_head_idx_T_24; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_26 = ~stq_cleared_13; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_27 = stq_valid_13 & _stq_clr_head_idx_T_26; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_28 = ~stq_cleared_14; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_29 = stq_valid_14 & _stq_clr_head_idx_T_28; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_30 = ~stq_cleared_15; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_31 = stq_valid_15 & _stq_clr_head_idx_T_30; // @[lsu.scala:251:32, :1077:{18,21}] wire stq_clr_head_idx_temp_vec_15 = _stq_clr_head_idx_T_31; // @[util.scala:352:65] wire stq_clr_head_idx_temp_vec_0 = _stq_clr_head_idx_T_1 & _stq_clr_head_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_1 = _stq_clr_head_idx_T_3 & _stq_clr_head_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_2 = _stq_clr_head_idx_T_5 & _stq_clr_head_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_3 = _stq_clr_head_idx_T_7 & _stq_clr_head_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_4 = _stq_clr_head_idx_T_9 & _stq_clr_head_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_5 = _stq_clr_head_idx_T_11 & _stq_clr_head_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_6 = _stq_clr_head_idx_T_13 & _stq_clr_head_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _stq_clr_head_idx_temp_vec_T_7 = ~(stq_commit_head[3]); // @[util.scala:352:72] wire stq_clr_head_idx_temp_vec_7 = _stq_clr_head_idx_T_15 & _stq_clr_head_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_8 = _stq_clr_head_idx_T_17 & _stq_clr_head_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_9 = _stq_clr_head_idx_T_19 & _stq_clr_head_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_10 = _stq_clr_head_idx_T_21 & _stq_clr_head_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_11 = _stq_clr_head_idx_T_23 & _stq_clr_head_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_12 = _stq_clr_head_idx_T_25 & _stq_clr_head_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_13 = _stq_clr_head_idx_T_27 & _stq_clr_head_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_14 = _stq_clr_head_idx_T_29 & _stq_clr_head_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire [4:0] _stq_clr_head_idx_idx_T = {4'hF, ~_stq_clr_head_idx_T_29}; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_1 = _stq_clr_head_idx_T_27 ? 5'h1D : _stq_clr_head_idx_idx_T; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_2 = _stq_clr_head_idx_T_25 ? 5'h1C : _stq_clr_head_idx_idx_T_1; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_3 = _stq_clr_head_idx_T_23 ? 5'h1B : _stq_clr_head_idx_idx_T_2; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_4 = _stq_clr_head_idx_T_21 ? 5'h1A : _stq_clr_head_idx_idx_T_3; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_5 = _stq_clr_head_idx_T_19 ? 5'h19 : _stq_clr_head_idx_idx_T_4; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_6 = _stq_clr_head_idx_T_17 ? 5'h18 : _stq_clr_head_idx_idx_T_5; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_7 = _stq_clr_head_idx_T_15 ? 5'h17 : _stq_clr_head_idx_idx_T_6; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_8 = _stq_clr_head_idx_T_13 ? 5'h16 : _stq_clr_head_idx_idx_T_7; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_9 = _stq_clr_head_idx_T_11 ? 5'h15 : _stq_clr_head_idx_idx_T_8; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_10 = _stq_clr_head_idx_T_9 ? 5'h14 : _stq_clr_head_idx_idx_T_9; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_11 = _stq_clr_head_idx_T_7 ? 5'h13 : _stq_clr_head_idx_idx_T_10; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_12 = _stq_clr_head_idx_T_5 ? 5'h12 : _stq_clr_head_idx_idx_T_11; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_13 = _stq_clr_head_idx_T_3 ? 5'h11 : _stq_clr_head_idx_idx_T_12; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_14 = _stq_clr_head_idx_T_1 ? 5'h10 : _stq_clr_head_idx_idx_T_13; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_15 = stq_clr_head_idx_temp_vec_15 ? 5'hF : _stq_clr_head_idx_idx_T_14; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_16 = stq_clr_head_idx_temp_vec_14 ? 5'hE : _stq_clr_head_idx_idx_T_15; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_17 = stq_clr_head_idx_temp_vec_13 ? 5'hD : _stq_clr_head_idx_idx_T_16; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_18 = stq_clr_head_idx_temp_vec_12 ? 5'hC : _stq_clr_head_idx_idx_T_17; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_19 = stq_clr_head_idx_temp_vec_11 ? 5'hB : _stq_clr_head_idx_idx_T_18; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_20 = stq_clr_head_idx_temp_vec_10 ? 5'hA : _stq_clr_head_idx_idx_T_19; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_21 = stq_clr_head_idx_temp_vec_9 ? 5'h9 : _stq_clr_head_idx_idx_T_20; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_22 = stq_clr_head_idx_temp_vec_8 ? 5'h8 : _stq_clr_head_idx_idx_T_21; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_23 = stq_clr_head_idx_temp_vec_7 ? 5'h7 : _stq_clr_head_idx_idx_T_22; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_24 = stq_clr_head_idx_temp_vec_6 ? 5'h6 : _stq_clr_head_idx_idx_T_23; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_25 = stq_clr_head_idx_temp_vec_5 ? 5'h5 : _stq_clr_head_idx_idx_T_24; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_26 = stq_clr_head_idx_temp_vec_4 ? 5'h4 : _stq_clr_head_idx_idx_T_25; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_27 = stq_clr_head_idx_temp_vec_3 ? 5'h3 : _stq_clr_head_idx_idx_T_26; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_28 = stq_clr_head_idx_temp_vec_2 ? 5'h2 : _stq_clr_head_idx_idx_T_27; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_idx_T_29 = stq_clr_head_idx_temp_vec_1 ? 5'h1 : _stq_clr_head_idx_idx_T_28; // @[Mux.scala:50:70] wire [4:0] stq_clr_head_idx_idx = stq_clr_head_idx_temp_vec_0 ? 5'h0 : _stq_clr_head_idx_idx_T_29; // @[Mux.scala:50:70] wire [3:0] _stq_clr_head_idx_T_32 = stq_clr_head_idx_idx[3:0]; // @[Mux.scala:50:70] reg [3:0] stq_clr_head_idx; // @[lsu.scala:1076:33] wire [3:0] _s_uop_T = stq_clr_head_idx; // @[lsu.scala:1076:33] reg clr_valid; // @[lsu.scala:1084:24] reg [31:0] clr_uop_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_inst = clr_uop_inst; // @[util.scala:104:23] reg [31:0] clr_uop_debug_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_debug_inst = clr_uop_debug_inst; // @[util.scala:104:23] reg clr_uop_is_rvc; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_rvc = clr_uop_is_rvc; // @[util.scala:104:23] reg [39:0] clr_uop_debug_pc; // @[lsu.scala:1086:24] wire [39:0] clr_uop_1_out_debug_pc = clr_uop_debug_pc; // @[util.scala:104:23] reg clr_uop_iq_type_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_0 = clr_uop_iq_type_0; // @[util.scala:104:23] reg clr_uop_iq_type_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_1 = clr_uop_iq_type_1; // @[util.scala:104:23] reg clr_uop_iq_type_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_2 = clr_uop_iq_type_2; // @[util.scala:104:23] reg clr_uop_iq_type_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_3 = clr_uop_iq_type_3; // @[util.scala:104:23] reg clr_uop_fu_code_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_0 = clr_uop_fu_code_0; // @[util.scala:104:23] reg clr_uop_fu_code_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_1 = clr_uop_fu_code_1; // @[util.scala:104:23] reg clr_uop_fu_code_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_2 = clr_uop_fu_code_2; // @[util.scala:104:23] reg clr_uop_fu_code_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_3 = clr_uop_fu_code_3; // @[util.scala:104:23] reg clr_uop_fu_code_4; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_4 = clr_uop_fu_code_4; // @[util.scala:104:23] reg clr_uop_fu_code_5; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_5 = clr_uop_fu_code_5; // @[util.scala:104:23] reg clr_uop_fu_code_6; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_6 = clr_uop_fu_code_6; // @[util.scala:104:23] reg clr_uop_fu_code_7; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_7 = clr_uop_fu_code_7; // @[util.scala:104:23] reg clr_uop_fu_code_8; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_8 = clr_uop_fu_code_8; // @[util.scala:104:23] reg clr_uop_fu_code_9; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_9 = clr_uop_fu_code_9; // @[util.scala:104:23] reg clr_uop_iw_issued; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_issued = clr_uop_iw_issued; // @[util.scala:104:23] reg clr_uop_iw_issued_partial_agen; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_issued_partial_agen = clr_uop_iw_issued_partial_agen; // @[util.scala:104:23] reg clr_uop_iw_issued_partial_dgen; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_issued_partial_dgen = clr_uop_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] clr_uop_iw_p1_speculative_child; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_iw_p1_speculative_child = clr_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] clr_uop_iw_p2_speculative_child; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_iw_p2_speculative_child = clr_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg clr_uop_iw_p1_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_p1_bypass_hint = clr_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg clr_uop_iw_p2_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_p2_bypass_hint = clr_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg clr_uop_iw_p3_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_p3_bypass_hint = clr_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] clr_uop_dis_col_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_dis_col_sel = clr_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] clr_uop_br_mask; // @[lsu.scala:1086:24] reg [3:0] clr_uop_br_tag; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_br_tag = clr_uop_br_tag; // @[util.scala:104:23] reg [3:0] clr_uop_br_type; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_br_type = clr_uop_br_type; // @[util.scala:104:23] reg clr_uop_is_sfb; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_sfb = clr_uop_is_sfb; // @[util.scala:104:23] reg clr_uop_is_fence; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_fence = clr_uop_is_fence; // @[util.scala:104:23] reg clr_uop_is_fencei; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_fencei = clr_uop_is_fencei; // @[util.scala:104:23] reg clr_uop_is_sfence; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_sfence = clr_uop_is_sfence; // @[util.scala:104:23] reg clr_uop_is_amo; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_amo = clr_uop_is_amo; // @[util.scala:104:23] reg clr_uop_is_eret; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_eret = clr_uop_is_eret; // @[util.scala:104:23] reg clr_uop_is_sys_pc2epc; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_sys_pc2epc = clr_uop_is_sys_pc2epc; // @[util.scala:104:23] reg clr_uop_is_rocc; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_rocc = clr_uop_is_rocc; // @[util.scala:104:23] reg clr_uop_is_mov; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_mov = clr_uop_is_mov; // @[util.scala:104:23] reg [4:0] clr_uop_ftq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_ftq_idx = clr_uop_ftq_idx; // @[util.scala:104:23] reg clr_uop_edge_inst; // @[lsu.scala:1086:24] wire clr_uop_1_out_edge_inst = clr_uop_edge_inst; // @[util.scala:104:23] reg [5:0] clr_uop_pc_lob; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_pc_lob = clr_uop_pc_lob; // @[util.scala:104:23] reg clr_uop_taken; // @[lsu.scala:1086:24] wire clr_uop_1_out_taken = clr_uop_taken; // @[util.scala:104:23] reg clr_uop_imm_rename; // @[lsu.scala:1086:24] wire clr_uop_1_out_imm_rename = clr_uop_imm_rename; // @[util.scala:104:23] reg [2:0] clr_uop_imm_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_imm_sel = clr_uop_imm_sel; // @[util.scala:104:23] reg [4:0] clr_uop_pimm; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_pimm = clr_uop_pimm; // @[util.scala:104:23] reg [19:0] clr_uop_imm_packed; // @[lsu.scala:1086:24] wire [19:0] clr_uop_1_out_imm_packed = clr_uop_imm_packed; // @[util.scala:104:23] reg [1:0] clr_uop_op1_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_op1_sel = clr_uop_op1_sel; // @[util.scala:104:23] reg [2:0] clr_uop_op2_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_op2_sel = clr_uop_op2_sel; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ldst; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ldst = clr_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg clr_uop_fp_ctrl_wen; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_wen = clr_uop_fp_ctrl_wen; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ren1; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ren1 = clr_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ren2; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ren2 = clr_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ren3; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ren3 = clr_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg clr_uop_fp_ctrl_swap12; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_swap12 = clr_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg clr_uop_fp_ctrl_swap23; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_swap23 = clr_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] clr_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_fp_ctrl_typeTagIn = clr_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] clr_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_fp_ctrl_typeTagOut = clr_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg clr_uop_fp_ctrl_fromint; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_fromint = clr_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg clr_uop_fp_ctrl_toint; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_toint = clr_uop_fp_ctrl_toint; // @[util.scala:104:23] reg clr_uop_fp_ctrl_fastpipe; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_fastpipe = clr_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg clr_uop_fp_ctrl_fma; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_fma = clr_uop_fp_ctrl_fma; // @[util.scala:104:23] reg clr_uop_fp_ctrl_div; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_div = clr_uop_fp_ctrl_div; // @[util.scala:104:23] reg clr_uop_fp_ctrl_sqrt; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_sqrt = clr_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg clr_uop_fp_ctrl_wflags; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_wflags = clr_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg clr_uop_fp_ctrl_vec; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_vec = clr_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] clr_uop_rob_idx; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_rob_idx = clr_uop_rob_idx; // @[util.scala:104:23] reg [3:0] clr_uop_ldq_idx; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_ldq_idx = clr_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] clr_uop_stq_idx; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_stq_idx = clr_uop_stq_idx; // @[util.scala:104:23] reg [1:0] clr_uop_rxq_idx; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_rxq_idx = clr_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] clr_uop_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_pdst = clr_uop_pdst; // @[util.scala:104:23] reg [6:0] clr_uop_prs1; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_prs1 = clr_uop_prs1; // @[util.scala:104:23] reg [6:0] clr_uop_prs2; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_prs2 = clr_uop_prs2; // @[util.scala:104:23] reg [6:0] clr_uop_prs3; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_prs3 = clr_uop_prs3; // @[util.scala:104:23] reg [4:0] clr_uop_ppred; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_ppred = clr_uop_ppred; // @[util.scala:104:23] reg clr_uop_prs1_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_prs1_busy = clr_uop_prs1_busy; // @[util.scala:104:23] reg clr_uop_prs2_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_prs2_busy = clr_uop_prs2_busy; // @[util.scala:104:23] reg clr_uop_prs3_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_prs3_busy = clr_uop_prs3_busy; // @[util.scala:104:23] reg clr_uop_ppred_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_ppred_busy = clr_uop_ppred_busy; // @[util.scala:104:23] reg [6:0] clr_uop_stale_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_stale_pdst = clr_uop_stale_pdst; // @[util.scala:104:23] reg clr_uop_exception; // @[lsu.scala:1086:24] wire clr_uop_1_out_exception = clr_uop_exception; // @[util.scala:104:23] reg [63:0] clr_uop_exc_cause; // @[lsu.scala:1086:24] wire [63:0] clr_uop_1_out_exc_cause = clr_uop_exc_cause; // @[util.scala:104:23] reg [4:0] clr_uop_mem_cmd; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_mem_cmd = clr_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] clr_uop_mem_size; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_mem_size = clr_uop_mem_size; // @[util.scala:104:23] reg clr_uop_mem_signed; // @[lsu.scala:1086:24] wire clr_uop_1_out_mem_signed = clr_uop_mem_signed; // @[util.scala:104:23] reg clr_uop_uses_ldq; // @[lsu.scala:1086:24] wire clr_uop_1_out_uses_ldq = clr_uop_uses_ldq; // @[util.scala:104:23] reg clr_uop_uses_stq; // @[lsu.scala:1086:24] wire clr_uop_1_out_uses_stq = clr_uop_uses_stq; // @[util.scala:104:23] reg clr_uop_is_unique; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_unique = clr_uop_is_unique; // @[util.scala:104:23] reg clr_uop_flush_on_commit; // @[lsu.scala:1086:24] wire clr_uop_1_out_flush_on_commit = clr_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] clr_uop_csr_cmd; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_csr_cmd = clr_uop_csr_cmd; // @[util.scala:104:23] reg clr_uop_ldst_is_rs1; // @[lsu.scala:1086:24] wire clr_uop_1_out_ldst_is_rs1 = clr_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] clr_uop_ldst; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_ldst = clr_uop_ldst; // @[util.scala:104:23] reg [5:0] clr_uop_lrs1; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_lrs1 = clr_uop_lrs1; // @[util.scala:104:23] reg [5:0] clr_uop_lrs2; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_lrs2 = clr_uop_lrs2; // @[util.scala:104:23] reg [5:0] clr_uop_lrs3; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_lrs3 = clr_uop_lrs3; // @[util.scala:104:23] reg [1:0] clr_uop_dst_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_dst_rtype = clr_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_lrs1_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_lrs1_rtype = clr_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_lrs2_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_lrs2_rtype = clr_uop_lrs2_rtype; // @[util.scala:104:23] reg clr_uop_frs3_en; // @[lsu.scala:1086:24] wire clr_uop_1_out_frs3_en = clr_uop_frs3_en; // @[util.scala:104:23] reg clr_uop_fcn_dw; // @[lsu.scala:1086:24] wire clr_uop_1_out_fcn_dw = clr_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] clr_uop_fcn_op; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_fcn_op = clr_uop_fcn_op; // @[util.scala:104:23] reg clr_uop_fp_val; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_val = clr_uop_fp_val; // @[util.scala:104:23] reg [2:0] clr_uop_fp_rm; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_fp_rm = clr_uop_fp_rm; // @[util.scala:104:23] reg [1:0] clr_uop_fp_typ; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_fp_typ = clr_uop_fp_typ; // @[util.scala:104:23] reg clr_uop_xcpt_pf_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_xcpt_pf_if = clr_uop_xcpt_pf_if; // @[util.scala:104:23] reg clr_uop_xcpt_ae_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_xcpt_ae_if = clr_uop_xcpt_ae_if; // @[util.scala:104:23] reg clr_uop_xcpt_ma_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_xcpt_ma_if = clr_uop_xcpt_ma_if; // @[util.scala:104:23] reg clr_uop_bp_debug_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_bp_debug_if = clr_uop_bp_debug_if; // @[util.scala:104:23] reg clr_uop_bp_xcpt_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_bp_xcpt_if = clr_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] clr_uop_debug_fsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_debug_fsrc = clr_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] clr_uop_debug_tsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_debug_tsrc = clr_uop_debug_tsrc; // @[util.scala:104:23] wire [11:0] _clr_valid_1_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_br_mask; // @[util.scala:126:51] wire _clr_valid_1_T_1 = |_clr_valid_1_T; // @[util.scala:126:{51,59}] wire _clr_valid_1_T_2 = _clr_valid_1_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _clr_valid_1_T_3 = ~_clr_valid_1_T_2; // @[util.scala:61:61] wire _clr_valid_1_T_4 = clr_valid & _clr_valid_1_T_3; // @[lsu.scala:1084:24, :1088:{41,44}] reg clr_valid_1; // @[lsu.scala:1088:30] wire [11:0] _clr_uop_1_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] clr_uop_1_out_br_mask; // @[util.scala:104:23] wire [11:0] _clr_uop_1_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_1_out_br_mask_T_1 = clr_uop_br_mask & _clr_uop_1_out_br_mask_T; // @[util.scala:93:{25,27}] assign clr_uop_1_out_br_mask = _clr_uop_1_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg [31:0] clr_uop_1_inst; // @[lsu.scala:1089:30] reg [31:0] clr_uop_1_debug_inst; // @[lsu.scala:1089:30] reg clr_uop_1_is_rvc; // @[lsu.scala:1089:30] reg [39:0] clr_uop_1_debug_pc; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_0; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_1; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_2; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_3; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_0; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_1; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_2; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_3; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_4; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_5; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_6; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_7; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_8; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_9; // @[lsu.scala:1089:30] reg clr_uop_1_iw_issued; // @[lsu.scala:1089:30] reg clr_uop_1_iw_issued_partial_agen; // @[lsu.scala:1089:30] reg clr_uop_1_iw_issued_partial_dgen; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_iw_p1_speculative_child; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_iw_p2_speculative_child; // @[lsu.scala:1089:30] reg clr_uop_1_iw_p1_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_iw_p2_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_iw_p3_bypass_hint; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_dis_col_sel; // @[lsu.scala:1089:30] reg [11:0] clr_uop_1_br_mask; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_br_tag; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_br_type; // @[lsu.scala:1089:30] reg clr_uop_1_is_sfb; // @[lsu.scala:1089:30] reg clr_uop_1_is_fence; // @[lsu.scala:1089:30] reg clr_uop_1_is_fencei; // @[lsu.scala:1089:30] reg clr_uop_1_is_sfence; // @[lsu.scala:1089:30] reg clr_uop_1_is_amo; // @[lsu.scala:1089:30] reg clr_uop_1_is_eret; // @[lsu.scala:1089:30] reg clr_uop_1_is_sys_pc2epc; // @[lsu.scala:1089:30] reg clr_uop_1_is_rocc; // @[lsu.scala:1089:30] reg clr_uop_1_is_mov; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_ftq_idx; // @[lsu.scala:1089:30] reg clr_uop_1_edge_inst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_pc_lob; // @[lsu.scala:1089:30] reg clr_uop_1_taken; // @[lsu.scala:1089:30] reg clr_uop_1_imm_rename; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_imm_sel; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_pimm; // @[lsu.scala:1089:30] reg [19:0] clr_uop_1_imm_packed; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_op1_sel; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_op2_sel; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ldst; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_wen; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ren1; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ren2; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ren3; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_swap12; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_swap23; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_fromint; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_toint; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_fma; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_div; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_sqrt; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_wflags; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_vec; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_rob_idx; // @[lsu.scala:1089:30] assign io_core_clr_bsy_0_bits_0 = clr_uop_1_rob_idx; // @[lsu.scala:211:7, :1089:30] reg [3:0] clr_uop_1_ldq_idx; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_stq_idx; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_rxq_idx; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_pdst; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_prs1; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_prs2; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_prs3; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_ppred; // @[lsu.scala:1089:30] reg clr_uop_1_prs1_busy; // @[lsu.scala:1089:30] reg clr_uop_1_prs2_busy; // @[lsu.scala:1089:30] reg clr_uop_1_prs3_busy; // @[lsu.scala:1089:30] reg clr_uop_1_ppred_busy; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_stale_pdst; // @[lsu.scala:1089:30] reg clr_uop_1_exception; // @[lsu.scala:1089:30] reg [63:0] clr_uop_1_exc_cause; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_mem_cmd; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_mem_size; // @[lsu.scala:1089:30] reg clr_uop_1_mem_signed; // @[lsu.scala:1089:30] reg clr_uop_1_uses_ldq; // @[lsu.scala:1089:30] reg clr_uop_1_uses_stq; // @[lsu.scala:1089:30] reg clr_uop_1_is_unique; // @[lsu.scala:1089:30] reg clr_uop_1_flush_on_commit; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_csr_cmd; // @[lsu.scala:1089:30] reg clr_uop_1_ldst_is_rs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_ldst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_lrs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_lrs2; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_lrs3; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_dst_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_lrs1_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_lrs2_rtype; // @[lsu.scala:1089:30] reg clr_uop_1_frs3_en; // @[lsu.scala:1089:30] reg clr_uop_1_fcn_dw; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_fcn_op; // @[lsu.scala:1089:30] reg clr_uop_1_fp_val; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_fp_rm; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_fp_typ; // @[lsu.scala:1089:30] reg clr_uop_1_xcpt_pf_if; // @[lsu.scala:1089:30] reg clr_uop_1_xcpt_ae_if; // @[lsu.scala:1089:30] reg clr_uop_1_xcpt_ma_if; // @[lsu.scala:1089:30] reg clr_uop_1_bp_debug_if; // @[lsu.scala:1089:30] reg clr_uop_1_bp_xcpt_if; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_debug_fsrc; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_debug_tsrc; // @[lsu.scala:1089:30] wire [3:0] _s_uop_T_1 = _s_uop_T; wire [31:0] clr_uop_out_inst = s_uop_inst; // @[util.scala:104:23] wire [31:0] clr_uop_out_debug_inst = s_uop_debug_inst; // @[util.scala:104:23] wire clr_uop_out_is_rvc = s_uop_is_rvc; // @[util.scala:104:23] wire [39:0] clr_uop_out_debug_pc = s_uop_debug_pc; // @[util.scala:104:23] wire clr_uop_out_iq_type_0 = s_uop_iq_type_0; // @[util.scala:104:23] wire clr_uop_out_iq_type_1 = s_uop_iq_type_1; // @[util.scala:104:23] wire clr_uop_out_iq_type_2 = s_uop_iq_type_2; // @[util.scala:104:23] wire clr_uop_out_iq_type_3 = s_uop_iq_type_3; // @[util.scala:104:23] wire clr_uop_out_fu_code_0 = s_uop_fu_code_0; // @[util.scala:104:23] wire clr_uop_out_fu_code_1 = s_uop_fu_code_1; // @[util.scala:104:23] wire clr_uop_out_fu_code_2 = s_uop_fu_code_2; // @[util.scala:104:23] wire clr_uop_out_fu_code_3 = s_uop_fu_code_3; // @[util.scala:104:23] wire clr_uop_out_fu_code_4 = s_uop_fu_code_4; // @[util.scala:104:23] wire clr_uop_out_fu_code_5 = s_uop_fu_code_5; // @[util.scala:104:23] wire clr_uop_out_fu_code_6 = s_uop_fu_code_6; // @[util.scala:104:23] wire clr_uop_out_fu_code_7 = s_uop_fu_code_7; // @[util.scala:104:23] wire clr_uop_out_fu_code_8 = s_uop_fu_code_8; // @[util.scala:104:23] wire clr_uop_out_fu_code_9 = s_uop_fu_code_9; // @[util.scala:104:23] wire clr_uop_out_iw_issued = s_uop_iw_issued; // @[util.scala:104:23] wire clr_uop_out_iw_issued_partial_agen = s_uop_iw_issued_partial_agen; // @[util.scala:104:23] wire clr_uop_out_iw_issued_partial_dgen = s_uop_iw_issued_partial_dgen; // @[util.scala:104:23] wire [1:0] clr_uop_out_iw_p1_speculative_child = s_uop_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] clr_uop_out_iw_p2_speculative_child = s_uop_iw_p2_speculative_child; // @[util.scala:104:23] wire clr_uop_out_iw_p1_bypass_hint = s_uop_iw_p1_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_iw_p2_bypass_hint = s_uop_iw_p2_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_iw_p3_bypass_hint = s_uop_iw_p3_bypass_hint; // @[util.scala:104:23] wire [1:0] clr_uop_out_dis_col_sel = s_uop_dis_col_sel; // @[util.scala:104:23] wire [3:0] clr_uop_out_br_tag = s_uop_br_tag; // @[util.scala:104:23] wire [3:0] clr_uop_out_br_type = s_uop_br_type; // @[util.scala:104:23] wire clr_uop_out_is_sfb = s_uop_is_sfb; // @[util.scala:104:23] wire clr_uop_out_is_fence = s_uop_is_fence; // @[util.scala:104:23] wire clr_uop_out_is_fencei = s_uop_is_fencei; // @[util.scala:104:23] wire clr_uop_out_is_sfence = s_uop_is_sfence; // @[util.scala:104:23] wire clr_uop_out_is_amo = s_uop_is_amo; // @[util.scala:104:23] wire clr_uop_out_is_eret = s_uop_is_eret; // @[util.scala:104:23] wire clr_uop_out_is_sys_pc2epc = s_uop_is_sys_pc2epc; // @[util.scala:104:23] wire clr_uop_out_is_rocc = s_uop_is_rocc; // @[util.scala:104:23] wire clr_uop_out_is_mov = s_uop_is_mov; // @[util.scala:104:23] wire [4:0] clr_uop_out_ftq_idx = s_uop_ftq_idx; // @[util.scala:104:23] wire clr_uop_out_edge_inst = s_uop_edge_inst; // @[util.scala:104:23] wire [5:0] clr_uop_out_pc_lob = s_uop_pc_lob; // @[util.scala:104:23] wire clr_uop_out_taken = s_uop_taken; // @[util.scala:104:23] wire clr_uop_out_imm_rename = s_uop_imm_rename; // @[util.scala:104:23] wire [2:0] clr_uop_out_imm_sel = s_uop_imm_sel; // @[util.scala:104:23] wire [4:0] clr_uop_out_pimm = s_uop_pimm; // @[util.scala:104:23] wire [19:0] clr_uop_out_imm_packed = s_uop_imm_packed; // @[util.scala:104:23] wire [1:0] clr_uop_out_op1_sel = s_uop_op1_sel; // @[util.scala:104:23] wire [2:0] clr_uop_out_op2_sel = s_uop_op2_sel; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ldst = s_uop_fp_ctrl_ldst; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_wen = s_uop_fp_ctrl_wen; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ren1 = s_uop_fp_ctrl_ren1; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ren2 = s_uop_fp_ctrl_ren2; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ren3 = s_uop_fp_ctrl_ren3; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_swap12 = s_uop_fp_ctrl_swap12; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_swap23 = s_uop_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] clr_uop_out_fp_ctrl_typeTagIn = s_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] clr_uop_out_fp_ctrl_typeTagOut = s_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_fromint = s_uop_fp_ctrl_fromint; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_toint = s_uop_fp_ctrl_toint; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_fastpipe = s_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_fma = s_uop_fp_ctrl_fma; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_div = s_uop_fp_ctrl_div; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_sqrt = s_uop_fp_ctrl_sqrt; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_wflags = s_uop_fp_ctrl_wflags; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_vec = s_uop_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] clr_uop_out_rob_idx = s_uop_rob_idx; // @[util.scala:104:23] wire [3:0] clr_uop_out_ldq_idx = s_uop_ldq_idx; // @[util.scala:104:23] wire [3:0] clr_uop_out_stq_idx = s_uop_stq_idx; // @[util.scala:104:23] wire [1:0] clr_uop_out_rxq_idx = s_uop_rxq_idx; // @[util.scala:104:23] wire [6:0] clr_uop_out_pdst = s_uop_pdst; // @[util.scala:104:23] wire [6:0] clr_uop_out_prs1 = s_uop_prs1; // @[util.scala:104:23] wire [6:0] clr_uop_out_prs2 = s_uop_prs2; // @[util.scala:104:23] wire [6:0] clr_uop_out_prs3 = s_uop_prs3; // @[util.scala:104:23] wire [4:0] clr_uop_out_ppred = s_uop_ppred; // @[util.scala:104:23] wire clr_uop_out_prs1_busy = s_uop_prs1_busy; // @[util.scala:104:23] wire clr_uop_out_prs2_busy = s_uop_prs2_busy; // @[util.scala:104:23] wire clr_uop_out_prs3_busy = s_uop_prs3_busy; // @[util.scala:104:23] wire clr_uop_out_ppred_busy = s_uop_ppred_busy; // @[util.scala:104:23] wire [6:0] clr_uop_out_stale_pdst = s_uop_stale_pdst; // @[util.scala:104:23] wire clr_uop_out_exception = s_uop_exception; // @[util.scala:104:23] wire [63:0] clr_uop_out_exc_cause = s_uop_exc_cause; // @[util.scala:104:23] wire [4:0] clr_uop_out_mem_cmd = s_uop_mem_cmd; // @[util.scala:104:23] wire [1:0] clr_uop_out_mem_size = s_uop_mem_size; // @[util.scala:104:23] wire clr_uop_out_mem_signed = s_uop_mem_signed; // @[util.scala:104:23] wire clr_uop_out_uses_ldq = s_uop_uses_ldq; // @[util.scala:104:23] wire clr_uop_out_uses_stq = s_uop_uses_stq; // @[util.scala:104:23] wire clr_uop_out_is_unique = s_uop_is_unique; // @[util.scala:104:23] wire clr_uop_out_flush_on_commit = s_uop_flush_on_commit; // @[util.scala:104:23] wire [2:0] clr_uop_out_csr_cmd = s_uop_csr_cmd; // @[util.scala:104:23] wire clr_uop_out_ldst_is_rs1 = s_uop_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_ldst = s_uop_ldst; // @[util.scala:104:23] wire [5:0] clr_uop_out_lrs1 = s_uop_lrs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_lrs2 = s_uop_lrs2; // @[util.scala:104:23] wire [5:0] clr_uop_out_lrs3 = s_uop_lrs3; // @[util.scala:104:23] wire [1:0] clr_uop_out_dst_rtype = s_uop_dst_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_lrs1_rtype = s_uop_lrs1_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_lrs2_rtype = s_uop_lrs2_rtype; // @[util.scala:104:23] wire clr_uop_out_frs3_en = s_uop_frs3_en; // @[util.scala:104:23] wire clr_uop_out_fcn_dw = s_uop_fcn_dw; // @[util.scala:104:23] wire [4:0] clr_uop_out_fcn_op = s_uop_fcn_op; // @[util.scala:104:23] wire clr_uop_out_fp_val = s_uop_fp_val; // @[util.scala:104:23] wire [2:0] clr_uop_out_fp_rm = s_uop_fp_rm; // @[util.scala:104:23] wire [1:0] clr_uop_out_fp_typ = s_uop_fp_typ; // @[util.scala:104:23] wire clr_uop_out_xcpt_pf_if = s_uop_xcpt_pf_if; // @[util.scala:104:23] wire clr_uop_out_xcpt_ae_if = s_uop_xcpt_ae_if; // @[util.scala:104:23] wire clr_uop_out_xcpt_ma_if = s_uop_xcpt_ma_if; // @[util.scala:104:23] wire clr_uop_out_bp_debug_if = s_uop_bp_debug_if; // @[util.scala:104:23] wire clr_uop_out_bp_xcpt_if = s_uop_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] clr_uop_out_debug_fsrc = s_uop_debug_fsrc; // @[util.scala:104:23] wire [2:0] clr_uop_out_debug_tsrc = s_uop_debug_tsrc; // @[util.scala:104:23] wire [11:0] s_uop_br_mask; // @[lsu.scala:1093:25] assign s_uop_inst = _GEN_200[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_inst = _GEN_201[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_rvc = _GEN_202[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_pc = _GEN_203[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_0 = _GEN_204[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_1 = _GEN_205[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_2 = _GEN_206[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_3 = _GEN_207[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_0 = _GEN_208[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_1 = _GEN_209[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_2 = _GEN_210[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_3 = _GEN_211[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_4 = _GEN_212[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_5 = _GEN_213[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_6 = _GEN_214[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_7 = _GEN_215[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_8 = _GEN_216[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_9 = _GEN_217[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_issued = _GEN_218[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_issued_partial_agen = _GEN_219[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_issued_partial_dgen = _GEN_220[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p1_speculative_child = _GEN_221[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p2_speculative_child = _GEN_222[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p1_bypass_hint = _GEN_223[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p2_bypass_hint = _GEN_224[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p3_bypass_hint = _GEN_225[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_dis_col_sel = _GEN_226[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_br_mask = _GEN_227[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_br_tag = _GEN_228[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_br_type = _GEN_229[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_sfb = _GEN_230[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_fence = _GEN_231[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_fencei = _GEN_232[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_sfence = _GEN_233[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_amo = _GEN_234[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_eret = _GEN_235[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_sys_pc2epc = _GEN_236[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_rocc = _GEN_237[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_mov = _GEN_238[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ftq_idx = _GEN_239[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_edge_inst = _GEN_240[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_pc_lob = _GEN_241[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_taken = _GEN_242[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_imm_rename = _GEN_243[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_imm_sel = _GEN_244[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_pimm = _GEN_245[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_imm_packed = _GEN_246[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_op1_sel = _GEN_247[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_op2_sel = _GEN_248[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ldst = _GEN_249[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_wen = _GEN_250[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ren1 = _GEN_251[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ren2 = _GEN_252[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ren3 = _GEN_253[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_swap12 = _GEN_254[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_swap23 = _GEN_255[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_typeTagIn = _GEN_256[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_typeTagOut = _GEN_257[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_fromint = _GEN_258[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_toint = _GEN_259[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_fastpipe = _GEN_260[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_fma = _GEN_261[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_div = _GEN_262[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_sqrt = _GEN_263[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_wflags = _GEN_264[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_vec = _GEN_265[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_rob_idx = _GEN_266[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ldq_idx = _GEN_267[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_stq_idx = _GEN_268[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_rxq_idx = _GEN_269[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_pdst = _GEN_270[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs1 = _GEN_271[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs2 = _GEN_272[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs3 = _GEN_273[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ppred = _GEN_274[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs1_busy = _GEN_275[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs2_busy = _GEN_276[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs3_busy = _GEN_277[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ppred_busy = _GEN_278[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_stale_pdst = _GEN_279[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_exception = _GEN_280[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_exc_cause = _GEN_281[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_mem_cmd = _GEN_282[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_mem_size = _GEN_283[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_mem_signed = _GEN_284[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_uses_ldq = _GEN_285[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_uses_stq = _GEN_286[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_unique = _GEN_287[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_flush_on_commit = _GEN_288[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_csr_cmd = _GEN_289[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ldst_is_rs1 = _GEN_290[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ldst = _GEN_291[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs1 = _GEN_292[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs2 = _GEN_293[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs3 = _GEN_294[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_dst_rtype = _GEN_295[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs1_rtype = _GEN_296[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs2_rtype = _GEN_297[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_frs3_en = _GEN_298[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fcn_dw = _GEN_299[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fcn_op = _GEN_300[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_val = _GEN_301[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_rm = _GEN_302[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_typ = _GEN_303[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_xcpt_pf_if = _GEN_304[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_xcpt_ae_if = _GEN_305[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_xcpt_ma_if = _GEN_306[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_bp_debug_if = _GEN_307[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_bp_xcpt_if = _GEN_308[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_fsrc = _GEN_309[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_tsrc = _GEN_310[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] wire [11:0] _clr_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] clr_uop_out_br_mask; // @[util.scala:104:23] wire [11:0] _clr_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_out_br_mask_T_1 = s_uop_br_mask & _clr_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign clr_uop_out_br_mask = _clr_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire [11:0] _io_core_clr_bsy_0_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_1_br_mask; // @[util.scala:126:51] wire _io_core_clr_bsy_0_valid_T_1 = |_io_core_clr_bsy_0_valid_T; // @[util.scala:126:{51,59}] wire _io_core_clr_bsy_0_valid_T_2 = _io_core_clr_bsy_0_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_clr_bsy_0_valid_T_3 = ~_io_core_clr_bsy_0_valid_T_2; // @[util.scala:61:61] assign _io_core_clr_bsy_0_valid_T_4 = clr_valid_1 & _io_core_clr_bsy_0_valid_T_3; // @[lsu.scala:1088:30, :1107:{45,48}] assign io_core_clr_bsy_0_valid_0 = _io_core_clr_bsy_0_valid_T_4; // @[lsu.scala:211:7, :1107:45] wire [3:0] _T_236 = stq_clr_head_idx + 4'h1; // @[util.scala:211:14] reg clr_valid_2; // @[lsu.scala:1084:24] reg [31:0] clr_uop_2_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_1_inst = clr_uop_2_inst; // @[util.scala:104:23] reg [31:0] clr_uop_2_debug_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_1_debug_inst = clr_uop_2_debug_inst; // @[util.scala:104:23] reg clr_uop_2_is_rvc; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_rvc = clr_uop_2_is_rvc; // @[util.scala:104:23] reg [39:0] clr_uop_2_debug_pc; // @[lsu.scala:1086:24] wire [39:0] clr_uop_1_out_1_debug_pc = clr_uop_2_debug_pc; // @[util.scala:104:23] reg clr_uop_2_iq_type_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_0 = clr_uop_2_iq_type_0; // @[util.scala:104:23] reg clr_uop_2_iq_type_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_1 = clr_uop_2_iq_type_1; // @[util.scala:104:23] reg clr_uop_2_iq_type_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_2 = clr_uop_2_iq_type_2; // @[util.scala:104:23] reg clr_uop_2_iq_type_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_3 = clr_uop_2_iq_type_3; // @[util.scala:104:23] reg clr_uop_2_fu_code_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_0 = clr_uop_2_fu_code_0; // @[util.scala:104:23] reg clr_uop_2_fu_code_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_1 = clr_uop_2_fu_code_1; // @[util.scala:104:23] reg clr_uop_2_fu_code_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_2 = clr_uop_2_fu_code_2; // @[util.scala:104:23] reg clr_uop_2_fu_code_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_3 = clr_uop_2_fu_code_3; // @[util.scala:104:23] reg clr_uop_2_fu_code_4; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_4 = clr_uop_2_fu_code_4; // @[util.scala:104:23] reg clr_uop_2_fu_code_5; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_5 = clr_uop_2_fu_code_5; // @[util.scala:104:23] reg clr_uop_2_fu_code_6; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_6 = clr_uop_2_fu_code_6; // @[util.scala:104:23] reg clr_uop_2_fu_code_7; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_7 = clr_uop_2_fu_code_7; // @[util.scala:104:23] reg clr_uop_2_fu_code_8; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_8 = clr_uop_2_fu_code_8; // @[util.scala:104:23] reg clr_uop_2_fu_code_9; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_9 = clr_uop_2_fu_code_9; // @[util.scala:104:23] reg clr_uop_2_iw_issued; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_issued = clr_uop_2_iw_issued; // @[util.scala:104:23] reg clr_uop_2_iw_issued_partial_agen; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_issued_partial_agen = clr_uop_2_iw_issued_partial_agen; // @[util.scala:104:23] reg clr_uop_2_iw_issued_partial_dgen; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_issued_partial_dgen = clr_uop_2_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] clr_uop_2_iw_p1_speculative_child; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_iw_p1_speculative_child = clr_uop_2_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] clr_uop_2_iw_p2_speculative_child; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_iw_p2_speculative_child = clr_uop_2_iw_p2_speculative_child; // @[util.scala:104:23] reg clr_uop_2_iw_p1_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_p1_bypass_hint = clr_uop_2_iw_p1_bypass_hint; // @[util.scala:104:23] reg clr_uop_2_iw_p2_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_p2_bypass_hint = clr_uop_2_iw_p2_bypass_hint; // @[util.scala:104:23] reg clr_uop_2_iw_p3_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_p3_bypass_hint = clr_uop_2_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] clr_uop_2_dis_col_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_dis_col_sel = clr_uop_2_dis_col_sel; // @[util.scala:104:23] reg [11:0] clr_uop_2_br_mask; // @[lsu.scala:1086:24] reg [3:0] clr_uop_2_br_tag; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_1_br_tag = clr_uop_2_br_tag; // @[util.scala:104:23] reg [3:0] clr_uop_2_br_type; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_1_br_type = clr_uop_2_br_type; // @[util.scala:104:23] reg clr_uop_2_is_sfb; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_sfb = clr_uop_2_is_sfb; // @[util.scala:104:23] reg clr_uop_2_is_fence; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_fence = clr_uop_2_is_fence; // @[util.scala:104:23] reg clr_uop_2_is_fencei; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_fencei = clr_uop_2_is_fencei; // @[util.scala:104:23] reg clr_uop_2_is_sfence; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_sfence = clr_uop_2_is_sfence; // @[util.scala:104:23] reg clr_uop_2_is_amo; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_amo = clr_uop_2_is_amo; // @[util.scala:104:23] reg clr_uop_2_is_eret; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_eret = clr_uop_2_is_eret; // @[util.scala:104:23] reg clr_uop_2_is_sys_pc2epc; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_sys_pc2epc = clr_uop_2_is_sys_pc2epc; // @[util.scala:104:23] reg clr_uop_2_is_rocc; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_rocc = clr_uop_2_is_rocc; // @[util.scala:104:23] reg clr_uop_2_is_mov; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_mov = clr_uop_2_is_mov; // @[util.scala:104:23] reg [4:0] clr_uop_2_ftq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_ftq_idx = clr_uop_2_ftq_idx; // @[util.scala:104:23] reg clr_uop_2_edge_inst; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_edge_inst = clr_uop_2_edge_inst; // @[util.scala:104:23] reg [5:0] clr_uop_2_pc_lob; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_pc_lob = clr_uop_2_pc_lob; // @[util.scala:104:23] reg clr_uop_2_taken; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_taken = clr_uop_2_taken; // @[util.scala:104:23] reg clr_uop_2_imm_rename; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_imm_rename = clr_uop_2_imm_rename; // @[util.scala:104:23] reg [2:0] clr_uop_2_imm_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_imm_sel = clr_uop_2_imm_sel; // @[util.scala:104:23] reg [4:0] clr_uop_2_pimm; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_pimm = clr_uop_2_pimm; // @[util.scala:104:23] reg [19:0] clr_uop_2_imm_packed; // @[lsu.scala:1086:24] wire [19:0] clr_uop_1_out_1_imm_packed = clr_uop_2_imm_packed; // @[util.scala:104:23] reg [1:0] clr_uop_2_op1_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_op1_sel = clr_uop_2_op1_sel; // @[util.scala:104:23] reg [2:0] clr_uop_2_op2_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_op2_sel = clr_uop_2_op2_sel; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ldst; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ldst = clr_uop_2_fp_ctrl_ldst; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_wen; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_wen = clr_uop_2_fp_ctrl_wen; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ren1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ren1 = clr_uop_2_fp_ctrl_ren1; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ren2; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ren2 = clr_uop_2_fp_ctrl_ren2; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ren3; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ren3 = clr_uop_2_fp_ctrl_ren3; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_swap12; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_swap12 = clr_uop_2_fp_ctrl_swap12; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_swap23; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_swap23 = clr_uop_2_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] clr_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_fp_ctrl_typeTagIn = clr_uop_2_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] clr_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_fp_ctrl_typeTagOut = clr_uop_2_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_fromint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_fromint = clr_uop_2_fp_ctrl_fromint; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_toint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_toint = clr_uop_2_fp_ctrl_toint; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_fastpipe = clr_uop_2_fp_ctrl_fastpipe; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_fma; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_fma = clr_uop_2_fp_ctrl_fma; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_div; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_div = clr_uop_2_fp_ctrl_div; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_sqrt; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_sqrt = clr_uop_2_fp_ctrl_sqrt; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_wflags; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_wflags = clr_uop_2_fp_ctrl_wflags; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_vec; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_vec = clr_uop_2_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] clr_uop_2_rob_idx; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_rob_idx = clr_uop_2_rob_idx; // @[util.scala:104:23] reg [3:0] clr_uop_2_ldq_idx; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_1_ldq_idx = clr_uop_2_ldq_idx; // @[util.scala:104:23] reg [3:0] clr_uop_2_stq_idx; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_1_stq_idx = clr_uop_2_stq_idx; // @[util.scala:104:23] reg [1:0] clr_uop_2_rxq_idx; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_rxq_idx = clr_uop_2_rxq_idx; // @[util.scala:104:23] reg [6:0] clr_uop_2_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_pdst = clr_uop_2_pdst; // @[util.scala:104:23] reg [6:0] clr_uop_2_prs1; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_prs1 = clr_uop_2_prs1; // @[util.scala:104:23] reg [6:0] clr_uop_2_prs2; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_prs2 = clr_uop_2_prs2; // @[util.scala:104:23] reg [6:0] clr_uop_2_prs3; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_prs3 = clr_uop_2_prs3; // @[util.scala:104:23] reg [4:0] clr_uop_2_ppred; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_ppred = clr_uop_2_ppred; // @[util.scala:104:23] reg clr_uop_2_prs1_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_prs1_busy = clr_uop_2_prs1_busy; // @[util.scala:104:23] reg clr_uop_2_prs2_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_prs2_busy = clr_uop_2_prs2_busy; // @[util.scala:104:23] reg clr_uop_2_prs3_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_prs3_busy = clr_uop_2_prs3_busy; // @[util.scala:104:23] reg clr_uop_2_ppred_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_ppred_busy = clr_uop_2_ppred_busy; // @[util.scala:104:23] reg [6:0] clr_uop_2_stale_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_stale_pdst = clr_uop_2_stale_pdst; // @[util.scala:104:23] reg clr_uop_2_exception; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_exception = clr_uop_2_exception; // @[util.scala:104:23] reg [63:0] clr_uop_2_exc_cause; // @[lsu.scala:1086:24] wire [63:0] clr_uop_1_out_1_exc_cause = clr_uop_2_exc_cause; // @[util.scala:104:23] reg [4:0] clr_uop_2_mem_cmd; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_mem_cmd = clr_uop_2_mem_cmd; // @[util.scala:104:23] reg [1:0] clr_uop_2_mem_size; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_mem_size = clr_uop_2_mem_size; // @[util.scala:104:23] reg clr_uop_2_mem_signed; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_mem_signed = clr_uop_2_mem_signed; // @[util.scala:104:23] reg clr_uop_2_uses_ldq; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_uses_ldq = clr_uop_2_uses_ldq; // @[util.scala:104:23] reg clr_uop_2_uses_stq; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_uses_stq = clr_uop_2_uses_stq; // @[util.scala:104:23] reg clr_uop_2_is_unique; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_unique = clr_uop_2_is_unique; // @[util.scala:104:23] reg clr_uop_2_flush_on_commit; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_flush_on_commit = clr_uop_2_flush_on_commit; // @[util.scala:104:23] reg [2:0] clr_uop_2_csr_cmd; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_csr_cmd = clr_uop_2_csr_cmd; // @[util.scala:104:23] reg clr_uop_2_ldst_is_rs1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_ldst_is_rs1 = clr_uop_2_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] clr_uop_2_ldst; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_ldst = clr_uop_2_ldst; // @[util.scala:104:23] reg [5:0] clr_uop_2_lrs1; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_lrs1 = clr_uop_2_lrs1; // @[util.scala:104:23] reg [5:0] clr_uop_2_lrs2; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_lrs2 = clr_uop_2_lrs2; // @[util.scala:104:23] reg [5:0] clr_uop_2_lrs3; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_lrs3 = clr_uop_2_lrs3; // @[util.scala:104:23] reg [1:0] clr_uop_2_dst_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_dst_rtype = clr_uop_2_dst_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_2_lrs1_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_lrs1_rtype = clr_uop_2_lrs1_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_2_lrs2_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_lrs2_rtype = clr_uop_2_lrs2_rtype; // @[util.scala:104:23] reg clr_uop_2_frs3_en; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_frs3_en = clr_uop_2_frs3_en; // @[util.scala:104:23] reg clr_uop_2_fcn_dw; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fcn_dw = clr_uop_2_fcn_dw; // @[util.scala:104:23] reg [4:0] clr_uop_2_fcn_op; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_fcn_op = clr_uop_2_fcn_op; // @[util.scala:104:23] reg clr_uop_2_fp_val; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_val = clr_uop_2_fp_val; // @[util.scala:104:23] reg [2:0] clr_uop_2_fp_rm; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_fp_rm = clr_uop_2_fp_rm; // @[util.scala:104:23] reg [1:0] clr_uop_2_fp_typ; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_fp_typ = clr_uop_2_fp_typ; // @[util.scala:104:23] reg clr_uop_2_xcpt_pf_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_xcpt_pf_if = clr_uop_2_xcpt_pf_if; // @[util.scala:104:23] reg clr_uop_2_xcpt_ae_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_xcpt_ae_if = clr_uop_2_xcpt_ae_if; // @[util.scala:104:23] reg clr_uop_2_xcpt_ma_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_xcpt_ma_if = clr_uop_2_xcpt_ma_if; // @[util.scala:104:23] reg clr_uop_2_bp_debug_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_bp_debug_if = clr_uop_2_bp_debug_if; // @[util.scala:104:23] reg clr_uop_2_bp_xcpt_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_bp_xcpt_if = clr_uop_2_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] clr_uop_2_debug_fsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_debug_fsrc = clr_uop_2_debug_fsrc; // @[util.scala:104:23] reg [2:0] clr_uop_2_debug_tsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_debug_tsrc = clr_uop_2_debug_tsrc; // @[util.scala:104:23] wire [11:0] _clr_valid_1_T_5 = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_2_br_mask; // @[util.scala:126:51] wire _clr_valid_1_T_6 = |_clr_valid_1_T_5; // @[util.scala:126:{51,59}] wire _clr_valid_1_T_7 = _clr_valid_1_T_6 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _clr_valid_1_T_8 = ~_clr_valid_1_T_7; // @[util.scala:61:61] wire _clr_valid_1_T_9 = clr_valid_2 & _clr_valid_1_T_8; // @[lsu.scala:1084:24, :1088:{41,44}] reg clr_valid_1_1; // @[lsu.scala:1088:30] wire [11:0] _clr_uop_1_out_br_mask_T_3; // @[util.scala:93:25] wire [11:0] clr_uop_1_out_1_br_mask; // @[util.scala:104:23] wire [11:0] _clr_uop_1_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_1_out_br_mask_T_3 = clr_uop_2_br_mask & _clr_uop_1_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign clr_uop_1_out_1_br_mask = _clr_uop_1_out_br_mask_T_3; // @[util.scala:93:25, :104:23] reg [31:0] clr_uop_1_1_inst; // @[lsu.scala:1089:30] reg [31:0] clr_uop_1_1_debug_inst; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_rvc; // @[lsu.scala:1089:30] reg [39:0] clr_uop_1_1_debug_pc; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_0; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_1; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_2; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_3; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_0; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_1; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_2; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_3; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_4; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_5; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_6; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_7; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_8; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_9; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_issued; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_issued_partial_agen; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_issued_partial_dgen; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_iw_p1_speculative_child; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_iw_p2_speculative_child; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_p1_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_p2_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_p3_bypass_hint; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_dis_col_sel; // @[lsu.scala:1089:30] reg [11:0] clr_uop_1_1_br_mask; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_1_br_tag; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_1_br_type; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_sfb; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_fence; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_fencei; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_sfence; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_amo; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_eret; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_sys_pc2epc; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_rocc; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_mov; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_ftq_idx; // @[lsu.scala:1089:30] reg clr_uop_1_1_edge_inst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_pc_lob; // @[lsu.scala:1089:30] reg clr_uop_1_1_taken; // @[lsu.scala:1089:30] reg clr_uop_1_1_imm_rename; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_imm_sel; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_pimm; // @[lsu.scala:1089:30] reg [19:0] clr_uop_1_1_imm_packed; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_op1_sel; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_op2_sel; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ldst; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_wen; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ren1; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ren2; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ren3; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_swap12; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_swap23; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_fp_ctrl_typeTagIn; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_fp_ctrl_typeTagOut; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_fromint; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_toint; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_fastpipe; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_fma; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_div; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_sqrt; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_wflags; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_vec; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_rob_idx; // @[lsu.scala:1089:30] assign io_core_clr_bsy_1_bits_0 = clr_uop_1_1_rob_idx; // @[lsu.scala:211:7, :1089:30] reg [3:0] clr_uop_1_1_ldq_idx; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_1_stq_idx; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_rxq_idx; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_pdst; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_prs1; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_prs2; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_prs3; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_ppred; // @[lsu.scala:1089:30] reg clr_uop_1_1_prs1_busy; // @[lsu.scala:1089:30] reg clr_uop_1_1_prs2_busy; // @[lsu.scala:1089:30] reg clr_uop_1_1_prs3_busy; // @[lsu.scala:1089:30] reg clr_uop_1_1_ppred_busy; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_stale_pdst; // @[lsu.scala:1089:30] reg clr_uop_1_1_exception; // @[lsu.scala:1089:30] reg [63:0] clr_uop_1_1_exc_cause; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_mem_cmd; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_mem_size; // @[lsu.scala:1089:30] reg clr_uop_1_1_mem_signed; // @[lsu.scala:1089:30] reg clr_uop_1_1_uses_ldq; // @[lsu.scala:1089:30] reg clr_uop_1_1_uses_stq; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_unique; // @[lsu.scala:1089:30] reg clr_uop_1_1_flush_on_commit; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_csr_cmd; // @[lsu.scala:1089:30] reg clr_uop_1_1_ldst_is_rs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_ldst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_lrs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_lrs2; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_lrs3; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_dst_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_lrs1_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_lrs2_rtype; // @[lsu.scala:1089:30] reg clr_uop_1_1_frs3_en; // @[lsu.scala:1089:30] reg clr_uop_1_1_fcn_dw; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_fcn_op; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_val; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_fp_rm; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_fp_typ; // @[lsu.scala:1089:30] reg clr_uop_1_1_xcpt_pf_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_xcpt_ae_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_xcpt_ma_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_bp_debug_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_bp_xcpt_if; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_debug_fsrc; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_debug_tsrc; // @[lsu.scala:1089:30] wire [31:0] clr_uop_out_1_inst = s_uop_1_inst; // @[util.scala:104:23] wire [31:0] clr_uop_out_1_debug_inst = s_uop_1_debug_inst; // @[util.scala:104:23] wire clr_uop_out_1_is_rvc = s_uop_1_is_rvc; // @[util.scala:104:23] wire [39:0] clr_uop_out_1_debug_pc = s_uop_1_debug_pc; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_0 = s_uop_1_iq_type_0; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_1 = s_uop_1_iq_type_1; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_2 = s_uop_1_iq_type_2; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_3 = s_uop_1_iq_type_3; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_0 = s_uop_1_fu_code_0; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_1 = s_uop_1_fu_code_1; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_2 = s_uop_1_fu_code_2; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_3 = s_uop_1_fu_code_3; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_4 = s_uop_1_fu_code_4; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_5 = s_uop_1_fu_code_5; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_6 = s_uop_1_fu_code_6; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_7 = s_uop_1_fu_code_7; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_8 = s_uop_1_fu_code_8; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_9 = s_uop_1_fu_code_9; // @[util.scala:104:23] wire clr_uop_out_1_iw_issued = s_uop_1_iw_issued; // @[util.scala:104:23] wire clr_uop_out_1_iw_issued_partial_agen = s_uop_1_iw_issued_partial_agen; // @[util.scala:104:23] wire clr_uop_out_1_iw_issued_partial_dgen = s_uop_1_iw_issued_partial_dgen; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_iw_p1_speculative_child = s_uop_1_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_iw_p2_speculative_child = s_uop_1_iw_p2_speculative_child; // @[util.scala:104:23] wire clr_uop_out_1_iw_p1_bypass_hint = s_uop_1_iw_p1_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_1_iw_p2_bypass_hint = s_uop_1_iw_p2_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_1_iw_p3_bypass_hint = s_uop_1_iw_p3_bypass_hint; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_dis_col_sel = s_uop_1_dis_col_sel; // @[util.scala:104:23] wire [3:0] clr_uop_out_1_br_tag = s_uop_1_br_tag; // @[util.scala:104:23] wire [3:0] clr_uop_out_1_br_type = s_uop_1_br_type; // @[util.scala:104:23] wire clr_uop_out_1_is_sfb = s_uop_1_is_sfb; // @[util.scala:104:23] wire clr_uop_out_1_is_fence = s_uop_1_is_fence; // @[util.scala:104:23] wire clr_uop_out_1_is_fencei = s_uop_1_is_fencei; // @[util.scala:104:23] wire clr_uop_out_1_is_sfence = s_uop_1_is_sfence; // @[util.scala:104:23] wire clr_uop_out_1_is_amo = s_uop_1_is_amo; // @[util.scala:104:23] wire clr_uop_out_1_is_eret = s_uop_1_is_eret; // @[util.scala:104:23] wire clr_uop_out_1_is_sys_pc2epc = s_uop_1_is_sys_pc2epc; // @[util.scala:104:23] wire clr_uop_out_1_is_rocc = s_uop_1_is_rocc; // @[util.scala:104:23] wire clr_uop_out_1_is_mov = s_uop_1_is_mov; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_ftq_idx = s_uop_1_ftq_idx; // @[util.scala:104:23] wire clr_uop_out_1_edge_inst = s_uop_1_edge_inst; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_pc_lob = s_uop_1_pc_lob; // @[util.scala:104:23] wire clr_uop_out_1_taken = s_uop_1_taken; // @[util.scala:104:23] wire clr_uop_out_1_imm_rename = s_uop_1_imm_rename; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_imm_sel = s_uop_1_imm_sel; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_pimm = s_uop_1_pimm; // @[util.scala:104:23] wire [19:0] clr_uop_out_1_imm_packed = s_uop_1_imm_packed; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_op1_sel = s_uop_1_op1_sel; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_op2_sel = s_uop_1_op2_sel; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ldst = s_uop_1_fp_ctrl_ldst; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_wen = s_uop_1_fp_ctrl_wen; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ren1 = s_uop_1_fp_ctrl_ren1; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ren2 = s_uop_1_fp_ctrl_ren2; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ren3 = s_uop_1_fp_ctrl_ren3; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_swap12 = s_uop_1_fp_ctrl_swap12; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_swap23 = s_uop_1_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_fp_ctrl_typeTagIn = s_uop_1_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_fp_ctrl_typeTagOut = s_uop_1_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_fromint = s_uop_1_fp_ctrl_fromint; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_toint = s_uop_1_fp_ctrl_toint; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_fastpipe = s_uop_1_fp_ctrl_fastpipe; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_fma = s_uop_1_fp_ctrl_fma; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_div = s_uop_1_fp_ctrl_div; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_sqrt = s_uop_1_fp_ctrl_sqrt; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_wflags = s_uop_1_fp_ctrl_wflags; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_vec = s_uop_1_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_rob_idx = s_uop_1_rob_idx; // @[util.scala:104:23] wire [3:0] clr_uop_out_1_ldq_idx = s_uop_1_ldq_idx; // @[util.scala:104:23] wire [3:0] clr_uop_out_1_stq_idx = s_uop_1_stq_idx; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_rxq_idx = s_uop_1_rxq_idx; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_pdst = s_uop_1_pdst; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_prs1 = s_uop_1_prs1; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_prs2 = s_uop_1_prs2; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_prs3 = s_uop_1_prs3; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_ppred = s_uop_1_ppred; // @[util.scala:104:23] wire clr_uop_out_1_prs1_busy = s_uop_1_prs1_busy; // @[util.scala:104:23] wire clr_uop_out_1_prs2_busy = s_uop_1_prs2_busy; // @[util.scala:104:23] wire clr_uop_out_1_prs3_busy = s_uop_1_prs3_busy; // @[util.scala:104:23] wire clr_uop_out_1_ppred_busy = s_uop_1_ppred_busy; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_stale_pdst = s_uop_1_stale_pdst; // @[util.scala:104:23] wire clr_uop_out_1_exception = s_uop_1_exception; // @[util.scala:104:23] wire [63:0] clr_uop_out_1_exc_cause = s_uop_1_exc_cause; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_mem_cmd = s_uop_1_mem_cmd; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_mem_size = s_uop_1_mem_size; // @[util.scala:104:23] wire clr_uop_out_1_mem_signed = s_uop_1_mem_signed; // @[util.scala:104:23] wire clr_uop_out_1_uses_ldq = s_uop_1_uses_ldq; // @[util.scala:104:23] wire clr_uop_out_1_uses_stq = s_uop_1_uses_stq; // @[util.scala:104:23] wire clr_uop_out_1_is_unique = s_uop_1_is_unique; // @[util.scala:104:23] wire clr_uop_out_1_flush_on_commit = s_uop_1_flush_on_commit; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_csr_cmd = s_uop_1_csr_cmd; // @[util.scala:104:23] wire clr_uop_out_1_ldst_is_rs1 = s_uop_1_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_ldst = s_uop_1_ldst; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_lrs1 = s_uop_1_lrs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_lrs2 = s_uop_1_lrs2; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_lrs3 = s_uop_1_lrs3; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_dst_rtype = s_uop_1_dst_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_lrs1_rtype = s_uop_1_lrs1_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_lrs2_rtype = s_uop_1_lrs2_rtype; // @[util.scala:104:23] wire clr_uop_out_1_frs3_en = s_uop_1_frs3_en; // @[util.scala:104:23] wire clr_uop_out_1_fcn_dw = s_uop_1_fcn_dw; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_fcn_op = s_uop_1_fcn_op; // @[util.scala:104:23] wire clr_uop_out_1_fp_val = s_uop_1_fp_val; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_fp_rm = s_uop_1_fp_rm; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_fp_typ = s_uop_1_fp_typ; // @[util.scala:104:23] wire clr_uop_out_1_xcpt_pf_if = s_uop_1_xcpt_pf_if; // @[util.scala:104:23] wire clr_uop_out_1_xcpt_ae_if = s_uop_1_xcpt_ae_if; // @[util.scala:104:23] wire clr_uop_out_1_xcpt_ma_if = s_uop_1_xcpt_ma_if; // @[util.scala:104:23] wire clr_uop_out_1_bp_debug_if = s_uop_1_bp_debug_if; // @[util.scala:104:23] wire clr_uop_out_1_bp_xcpt_if = s_uop_1_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_debug_fsrc = s_uop_1_debug_fsrc; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_debug_tsrc = s_uop_1_debug_tsrc; // @[util.scala:104:23] wire [11:0] s_uop_1_br_mask; // @[lsu.scala:1093:25] assign s_uop_1_inst = _GEN_200[_T_236]; // @[util.scala:211:14] assign s_uop_1_debug_inst = _GEN_201[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_rvc = _GEN_202[_T_236]; // @[util.scala:211:14] assign s_uop_1_debug_pc = _GEN_203[_T_236]; // @[util.scala:211:14] assign s_uop_1_iq_type_0 = _GEN_204[_T_236]; // @[util.scala:211:14] assign s_uop_1_iq_type_1 = _GEN_205[_T_236]; // @[util.scala:211:14] assign s_uop_1_iq_type_2 = _GEN_206[_T_236]; // @[util.scala:211:14] assign s_uop_1_iq_type_3 = _GEN_207[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_0 = _GEN_208[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_1 = _GEN_209[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_2 = _GEN_210[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_3 = _GEN_211[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_4 = _GEN_212[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_5 = _GEN_213[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_6 = _GEN_214[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_7 = _GEN_215[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_8 = _GEN_216[_T_236]; // @[util.scala:211:14] assign s_uop_1_fu_code_9 = _GEN_217[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_issued = _GEN_218[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_issued_partial_agen = _GEN_219[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_issued_partial_dgen = _GEN_220[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_p1_speculative_child = _GEN_221[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_p2_speculative_child = _GEN_222[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_p1_bypass_hint = _GEN_223[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_p2_bypass_hint = _GEN_224[_T_236]; // @[util.scala:211:14] assign s_uop_1_iw_p3_bypass_hint = _GEN_225[_T_236]; // @[util.scala:211:14] assign s_uop_1_dis_col_sel = _GEN_226[_T_236]; // @[util.scala:211:14] assign s_uop_1_br_mask = _GEN_227[_T_236]; // @[util.scala:211:14] assign s_uop_1_br_tag = _GEN_228[_T_236]; // @[util.scala:211:14] assign s_uop_1_br_type = _GEN_229[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_sfb = _GEN_230[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_fence = _GEN_231[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_fencei = _GEN_232[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_sfence = _GEN_233[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_amo = _GEN_234[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_eret = _GEN_235[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_sys_pc2epc = _GEN_236[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_rocc = _GEN_237[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_mov = _GEN_238[_T_236]; // @[util.scala:211:14] assign s_uop_1_ftq_idx = _GEN_239[_T_236]; // @[util.scala:211:14] assign s_uop_1_edge_inst = _GEN_240[_T_236]; // @[util.scala:211:14] assign s_uop_1_pc_lob = _GEN_241[_T_236]; // @[util.scala:211:14] assign s_uop_1_taken = _GEN_242[_T_236]; // @[util.scala:211:14] assign s_uop_1_imm_rename = _GEN_243[_T_236]; // @[util.scala:211:14] assign s_uop_1_imm_sel = _GEN_244[_T_236]; // @[util.scala:211:14] assign s_uop_1_pimm = _GEN_245[_T_236]; // @[util.scala:211:14] assign s_uop_1_imm_packed = _GEN_246[_T_236]; // @[util.scala:211:14] assign s_uop_1_op1_sel = _GEN_247[_T_236]; // @[util.scala:211:14] assign s_uop_1_op2_sel = _GEN_248[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_ldst = _GEN_249[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_wen = _GEN_250[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_ren1 = _GEN_251[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_ren2 = _GEN_252[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_ren3 = _GEN_253[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_swap12 = _GEN_254[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_swap23 = _GEN_255[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_typeTagIn = _GEN_256[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_typeTagOut = _GEN_257[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_fromint = _GEN_258[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_toint = _GEN_259[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_fastpipe = _GEN_260[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_fma = _GEN_261[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_div = _GEN_262[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_sqrt = _GEN_263[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_wflags = _GEN_264[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_ctrl_vec = _GEN_265[_T_236]; // @[util.scala:211:14] assign s_uop_1_rob_idx = _GEN_266[_T_236]; // @[util.scala:211:14] assign s_uop_1_ldq_idx = _GEN_267[_T_236]; // @[util.scala:211:14] assign s_uop_1_stq_idx = _GEN_268[_T_236]; // @[util.scala:211:14] assign s_uop_1_rxq_idx = _GEN_269[_T_236]; // @[util.scala:211:14] assign s_uop_1_pdst = _GEN_270[_T_236]; // @[util.scala:211:14] assign s_uop_1_prs1 = _GEN_271[_T_236]; // @[util.scala:211:14] assign s_uop_1_prs2 = _GEN_272[_T_236]; // @[util.scala:211:14] assign s_uop_1_prs3 = _GEN_273[_T_236]; // @[util.scala:211:14] assign s_uop_1_ppred = _GEN_274[_T_236]; // @[util.scala:211:14] assign s_uop_1_prs1_busy = _GEN_275[_T_236]; // @[util.scala:211:14] assign s_uop_1_prs2_busy = _GEN_276[_T_236]; // @[util.scala:211:14] assign s_uop_1_prs3_busy = _GEN_277[_T_236]; // @[util.scala:211:14] assign s_uop_1_ppred_busy = _GEN_278[_T_236]; // @[util.scala:211:14] assign s_uop_1_stale_pdst = _GEN_279[_T_236]; // @[util.scala:211:14] assign s_uop_1_exception = _GEN_280[_T_236]; // @[util.scala:211:14] assign s_uop_1_exc_cause = _GEN_281[_T_236]; // @[util.scala:211:14] assign s_uop_1_mem_cmd = _GEN_282[_T_236]; // @[util.scala:211:14] assign s_uop_1_mem_size = _GEN_283[_T_236]; // @[util.scala:211:14] assign s_uop_1_mem_signed = _GEN_284[_T_236]; // @[util.scala:211:14] assign s_uop_1_uses_ldq = _GEN_285[_T_236]; // @[util.scala:211:14] assign s_uop_1_uses_stq = _GEN_286[_T_236]; // @[util.scala:211:14] assign s_uop_1_is_unique = _GEN_287[_T_236]; // @[util.scala:211:14] assign s_uop_1_flush_on_commit = _GEN_288[_T_236]; // @[util.scala:211:14] assign s_uop_1_csr_cmd = _GEN_289[_T_236]; // @[util.scala:211:14] assign s_uop_1_ldst_is_rs1 = _GEN_290[_T_236]; // @[util.scala:211:14] assign s_uop_1_ldst = _GEN_291[_T_236]; // @[util.scala:211:14] assign s_uop_1_lrs1 = _GEN_292[_T_236]; // @[util.scala:211:14] assign s_uop_1_lrs2 = _GEN_293[_T_236]; // @[util.scala:211:14] assign s_uop_1_lrs3 = _GEN_294[_T_236]; // @[util.scala:211:14] assign s_uop_1_dst_rtype = _GEN_295[_T_236]; // @[util.scala:211:14] assign s_uop_1_lrs1_rtype = _GEN_296[_T_236]; // @[util.scala:211:14] assign s_uop_1_lrs2_rtype = _GEN_297[_T_236]; // @[util.scala:211:14] assign s_uop_1_frs3_en = _GEN_298[_T_236]; // @[util.scala:211:14] assign s_uop_1_fcn_dw = _GEN_299[_T_236]; // @[util.scala:211:14] assign s_uop_1_fcn_op = _GEN_300[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_val = _GEN_301[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_rm = _GEN_302[_T_236]; // @[util.scala:211:14] assign s_uop_1_fp_typ = _GEN_303[_T_236]; // @[util.scala:211:14] assign s_uop_1_xcpt_pf_if = _GEN_304[_T_236]; // @[util.scala:211:14] assign s_uop_1_xcpt_ae_if = _GEN_305[_T_236]; // @[util.scala:211:14] assign s_uop_1_xcpt_ma_if = _GEN_306[_T_236]; // @[util.scala:211:14] assign s_uop_1_bp_debug_if = _GEN_307[_T_236]; // @[util.scala:211:14] assign s_uop_1_bp_xcpt_if = _GEN_308[_T_236]; // @[util.scala:211:14] assign s_uop_1_debug_fsrc = _GEN_309[_T_236]; // @[util.scala:211:14] assign s_uop_1_debug_tsrc = _GEN_310[_T_236]; // @[util.scala:211:14] wire [11:0] _clr_uop_out_br_mask_T_3; // @[util.scala:93:25] wire [11:0] clr_uop_out_1_br_mask; // @[util.scala:104:23] wire [11:0] _clr_uop_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_out_br_mask_T_3 = s_uop_1_br_mask & _clr_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign clr_uop_out_1_br_mask = _clr_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire [11:0] _io_core_clr_bsy_1_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_1_1_br_mask; // @[util.scala:126:51] wire _io_core_clr_bsy_1_valid_T_1 = |_io_core_clr_bsy_1_valid_T; // @[util.scala:126:{51,59}] wire _io_core_clr_bsy_1_valid_T_2 = _io_core_clr_bsy_1_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_clr_bsy_1_valid_T_3 = ~_io_core_clr_bsy_1_valid_T_2; // @[util.scala:61:61] assign _io_core_clr_bsy_1_valid_T_4 = clr_valid_1_1 & _io_core_clr_bsy_1_valid_T_3; // @[lsu.scala:1088:30, :1107:{45,48}] assign io_core_clr_bsy_1_valid_0 = _io_core_clr_bsy_1_valid_T_4; // @[lsu.scala:211:7, :1107:45] wire _GEN_391 = fired_store_agen_0 | fired_store_retry_0; // @[lsu.scala:321:49, :1122:57] wire _do_st_search_T; // @[lsu.scala:1122:57] assign _do_st_search_T = _GEN_391; // @[lsu.scala:1122:57] wire _lcam_addr_T; // @[lsu.scala:1133:58] assign _lcam_addr_T = _GEN_391; // @[lsu.scala:1122:57, :1133:58] wire _do_st_search_T_1 = ~mem_tlb_miss_0; // @[lsu.scala:1070:41, :1122:85] wire _do_st_search_T_2 = _do_st_search_T & _do_st_search_T_1; // @[lsu.scala:1122:{57,82,85}] wire do_st_search_0 = _do_st_search_T_2; // @[lsu.scala:321:49, :1122:82] wire _do_ld_search_T_1 = _do_ld_search_T | fired_load_retry_0; // @[lsu.scala:321:49, :1124:{57,84}] wire _do_ld_search_T_2 = ~mem_tlb_miss_0; // @[lsu.scala:1070:41, :1122:85, :1124:111] wire _do_ld_search_T_3 = _do_ld_search_T_1 & _do_ld_search_T_2; // @[lsu.scala:1124:{84,108,111}] wire _do_ld_search_T_4 = _do_ld_search_T_3 | fired_load_wakeup_0; // @[lsu.scala:321:49, :1124:{108,129}] wire do_ld_search_0 = _do_ld_search_T_4; // @[lsu.scala:321:49, :1124:129] wire _lcam_addr_T_1 = _lcam_addr_T | fired_load_agen_0; // @[lsu.scala:321:49, :1133:{58,82}] wire _lcam_addr_T_2 = _lcam_addr_T_1 | fired_load_agen_exec_0; // @[lsu.scala:321:49, :1133:{82,104}] reg [31:0] lcam_addr_REG; // @[lsu.scala:1134:45] reg [31:0] lcam_addr_REG_1; // @[lsu.scala:1135:67] wire [39:0] _lcam_addr_T_3 = fired_release_0 ? {8'h0, lcam_addr_REG_1} : mem_paddr_0; // @[lsu.scala:1045:37, :1072:41, :1135:{41,67}] wire [39:0] _lcam_addr_T_4 = _lcam_addr_T_2 ? {8'h0, lcam_addr_REG} : _lcam_addr_T_3; // @[lsu.scala:1133:{37,104}, :1134:45, :1135:41] wire [39:0] lcam_addr_0 = _lcam_addr_T_4; // @[lsu.scala:321:49, :1133:37] wire [31:0] _lcam_uop_T_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :1138:37] wire [31:0] _lcam_uop_T_debug_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_rvc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_rvc; // @[lsu.scala:321:49, :1138:37] wire [39:0] _lcam_uop_T_debug_pc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_0 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_2 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_3 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_0 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_2 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_3 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_4 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_5 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_6 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_7 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_8 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_9 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_issued = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_issued; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_issued_partial_agen = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_issued_partial_dgen = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_iw_p1_speculative_child = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iw_p1_speculative_child : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_iw_p2_speculative_child = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iw_p2_speculative_child : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_p1_bypass_hint = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_p2_bypass_hint = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_p3_bypass_hint = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_dis_col_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_dis_col_sel : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [11:0] _lcam_uop_T_br_mask = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_mask : 12'h0; // @[lsu.scala:321:49, :1138:37] wire [3:0] _lcam_uop_T_br_tag = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :1138:37] wire [3:0] _lcam_uop_T_br_type = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_sfb = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sfb; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_fence = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fence; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_fencei = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fencei; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_sfence = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sfence; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_amo = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_amo; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_eret = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_eret; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_sys_pc2epc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_rocc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_rocc; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_mov = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_mov; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_ftq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_edge_inst = do_ld_search_0 & mem_ldq_e_0_bits_uop_edge_inst; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_pc_lob = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_taken = do_ld_search_0 & mem_ldq_e_0_bits_uop_taken; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_imm_rename = do_ld_search_0 & mem_ldq_e_0_bits_uop_imm_rename; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_imm_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_pimm = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :1138:37] wire [19:0] _lcam_uop_T_imm_packed = do_ld_search_0 ? mem_ldq_e_0_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_op1_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_op2_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ldst = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_wen = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ren1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ren2 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ren3 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_swap12 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_swap23 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_fp_ctrl_typeTagIn = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_fp_ctrl_typeTagOut = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_fromint = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_toint = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_fastpipe = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_fma = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_div = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_sqrt = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_wflags = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_vec = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_rob_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rob_idx : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [3:0] _lcam_uop_T_ldq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldq_idx : 4'h0; // @[lsu.scala:321:49, :1138:37] wire [3:0] _lcam_uop_T_stq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stq_idx : 4'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_rxq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_prs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_prs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_prs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_ppred = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_prs1_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_prs2_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_prs3_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_ppred_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_stale_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_exception = do_ld_search_0 & mem_ldq_e_0_bits_uop_exception; // @[lsu.scala:321:49, :1138:37] wire [63:0] _lcam_uop_T_exc_cause = do_ld_search_0 ? mem_ldq_e_0_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_mem_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_mem_size = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_size : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_mem_signed = do_ld_search_0 & mem_ldq_e_0_bits_uop_mem_signed; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_uses_ldq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_uses_stq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_stq; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_unique = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_unique; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_flush_on_commit = do_ld_search_0 & mem_ldq_e_0_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_csr_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_ldst_is_rs1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_ldst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_lrs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_lrs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_lrs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_dst_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_lrs1_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_lrs2_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_frs3_en = do_ld_search_0 & mem_ldq_e_0_bits_uop_frs3_en; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fcn_dw = do_ld_search_0 & mem_ldq_e_0_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_fcn_op = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_val = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_val; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_fp_rm = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_fp_typ = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_xcpt_pf_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_xcpt_ae_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_xcpt_ma_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_bp_debug_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_bp_xcpt_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_debug_fsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_debug_tsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [31:0] _lcam_uop_T_1_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_inst : _lcam_uop_T_inst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [31:0] _lcam_uop_T_1_debug_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_inst : _lcam_uop_T_debug_inst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_rvc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_rvc : _lcam_uop_T_is_rvc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [39:0] _lcam_uop_T_1_debug_pc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_pc : _lcam_uop_T_debug_pc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_0 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_0 : _lcam_uop_T_iq_type_0; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_1 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_1 : _lcam_uop_T_iq_type_1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_2 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_2 : _lcam_uop_T_iq_type_2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_3 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_3 : _lcam_uop_T_iq_type_3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_0 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_0 : _lcam_uop_T_fu_code_0; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_1 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_1 : _lcam_uop_T_fu_code_1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_2 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_2 : _lcam_uop_T_fu_code_2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_3 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_3 : _lcam_uop_T_fu_code_3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_4 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_4 : _lcam_uop_T_fu_code_4; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_5 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_5 : _lcam_uop_T_fu_code_5; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_6 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_6 : _lcam_uop_T_fu_code_6; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_7 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_7 : _lcam_uop_T_fu_code_7; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_8 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_8 : _lcam_uop_T_fu_code_8; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_9 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_9 : _lcam_uop_T_fu_code_9; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_issued = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_issued : _lcam_uop_T_iw_issued; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_issued_partial_agen = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_issued_partial_agen : _lcam_uop_T_iw_issued_partial_agen; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_issued_partial_dgen = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_issued_partial_dgen : _lcam_uop_T_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_iw_p1_speculative_child = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p1_speculative_child : _lcam_uop_T_iw_p1_speculative_child; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_iw_p2_speculative_child = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p2_speculative_child : _lcam_uop_T_iw_p2_speculative_child; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_p1_bypass_hint = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p1_bypass_hint : _lcam_uop_T_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_p2_bypass_hint = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p2_bypass_hint : _lcam_uop_T_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_p3_bypass_hint = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p3_bypass_hint : _lcam_uop_T_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_dis_col_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_dis_col_sel : _lcam_uop_T_dis_col_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [11:0] _lcam_uop_T_1_br_mask = do_st_search_0 ? mem_stq_e_0_bits_uop_br_mask : _lcam_uop_T_br_mask; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [3:0] _lcam_uop_T_1_br_tag = do_st_search_0 ? mem_stq_e_0_bits_uop_br_tag : _lcam_uop_T_br_tag; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [3:0] _lcam_uop_T_1_br_type = do_st_search_0 ? mem_stq_e_0_bits_uop_br_type : _lcam_uop_T_br_type; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_sfb = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sfb : _lcam_uop_T_is_sfb; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_fence = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fence : _lcam_uop_T_is_fence; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_fencei = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fencei : _lcam_uop_T_is_fencei; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_sfence = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sfence : _lcam_uop_T_is_sfence; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_amo = do_st_search_0 ? mem_stq_e_0_bits_uop_is_amo : _lcam_uop_T_is_amo; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_eret = do_st_search_0 ? mem_stq_e_0_bits_uop_is_eret : _lcam_uop_T_is_eret; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_sys_pc2epc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sys_pc2epc : _lcam_uop_T_is_sys_pc2epc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_rocc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_rocc : _lcam_uop_T_is_rocc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_mov = do_st_search_0 ? mem_stq_e_0_bits_uop_is_mov : _lcam_uop_T_is_mov; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_ftq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ftq_idx : _lcam_uop_T_ftq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_edge_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_edge_inst : _lcam_uop_T_edge_inst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_pc_lob = do_st_search_0 ? mem_stq_e_0_bits_uop_pc_lob : _lcam_uop_T_pc_lob; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_taken = do_st_search_0 ? mem_stq_e_0_bits_uop_taken : _lcam_uop_T_taken; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_imm_rename = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_rename : _lcam_uop_T_imm_rename; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_imm_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_sel : _lcam_uop_T_imm_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_pimm = do_st_search_0 ? mem_stq_e_0_bits_uop_pimm : _lcam_uop_T_pimm; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [19:0] _lcam_uop_T_1_imm_packed = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_packed : _lcam_uop_T_imm_packed; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_op1_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_op1_sel : _lcam_uop_T_op1_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_op2_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_op2_sel : _lcam_uop_T_op2_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ldst = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ldst : _lcam_uop_T_fp_ctrl_ldst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_wen = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_wen : _lcam_uop_T_fp_ctrl_wen; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ren1 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ren1 : _lcam_uop_T_fp_ctrl_ren1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ren2 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ren2 : _lcam_uop_T_fp_ctrl_ren2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ren3 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ren3 : _lcam_uop_T_fp_ctrl_ren3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_swap12 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_swap12 : _lcam_uop_T_fp_ctrl_swap12; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_swap23 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_swap23 : _lcam_uop_T_fp_ctrl_swap23; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_fp_ctrl_typeTagIn = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_typeTagIn : _lcam_uop_T_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_fp_ctrl_typeTagOut = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_typeTagOut : _lcam_uop_T_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_fromint = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_fromint : _lcam_uop_T_fp_ctrl_fromint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_toint = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_toint : _lcam_uop_T_fp_ctrl_toint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_fastpipe = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_fastpipe : _lcam_uop_T_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_fma = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_fma : _lcam_uop_T_fp_ctrl_fma; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_div = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_div : _lcam_uop_T_fp_ctrl_div; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_sqrt = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_sqrt : _lcam_uop_T_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_wflags = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_wflags : _lcam_uop_T_fp_ctrl_wflags; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_vec = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_vec : _lcam_uop_T_fp_ctrl_vec; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_rob_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rob_idx : _lcam_uop_T_rob_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [3:0] _lcam_uop_T_1_ldq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ldq_idx : _lcam_uop_T_ldq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [3:0] _lcam_uop_T_1_stq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_stq_idx : _lcam_uop_T_stq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_rxq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rxq_idx : _lcam_uop_T_rxq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_pdst : _lcam_uop_T_pdst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_prs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1 : _lcam_uop_T_prs1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_prs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2 : _lcam_uop_T_prs2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_prs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3 : _lcam_uop_T_prs3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_ppred = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred : _lcam_uop_T_ppred; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_prs1_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1_busy : _lcam_uop_T_prs1_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_prs2_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2_busy : _lcam_uop_T_prs2_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_prs3_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3_busy : _lcam_uop_T_prs3_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_ppred_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred_busy : _lcam_uop_T_ppred_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_stale_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_stale_pdst : _lcam_uop_T_stale_pdst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_exception = do_st_search_0 ? mem_stq_e_0_bits_uop_exception : _lcam_uop_T_exception; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [63:0] _lcam_uop_T_1_exc_cause = do_st_search_0 ? mem_stq_e_0_bits_uop_exc_cause : _lcam_uop_T_exc_cause; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_mem_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_cmd : _lcam_uop_T_mem_cmd; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_mem_size = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_size : _lcam_uop_T_mem_size; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_mem_signed = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_signed : _lcam_uop_T_mem_signed; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_uses_ldq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_ldq : _lcam_uop_T_uses_ldq; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_uses_stq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_stq : _lcam_uop_T_uses_stq; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_unique = do_st_search_0 ? mem_stq_e_0_bits_uop_is_unique : _lcam_uop_T_is_unique; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_flush_on_commit = do_st_search_0 ? mem_stq_e_0_bits_uop_flush_on_commit : _lcam_uop_T_flush_on_commit; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_csr_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_csr_cmd : _lcam_uop_T_csr_cmd; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_ldst_is_rs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst_is_rs1 : _lcam_uop_T_ldst_is_rs1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_ldst = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst : _lcam_uop_T_ldst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_lrs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1 : _lcam_uop_T_lrs1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_lrs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2 : _lcam_uop_T_lrs2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_lrs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs3 : _lcam_uop_T_lrs3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_dst_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_dst_rtype : _lcam_uop_T_dst_rtype; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_lrs1_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1_rtype : _lcam_uop_T_lrs1_rtype; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_lrs2_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2_rtype : _lcam_uop_T_lrs2_rtype; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_frs3_en = do_st_search_0 ? mem_stq_e_0_bits_uop_frs3_en : _lcam_uop_T_frs3_en; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fcn_dw = do_st_search_0 ? mem_stq_e_0_bits_uop_fcn_dw : _lcam_uop_T_fcn_dw; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_fcn_op = do_st_search_0 ? mem_stq_e_0_bits_uop_fcn_op : _lcam_uop_T_fcn_op; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_val = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_val : _lcam_uop_T_fp_val; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_fp_rm = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_rm : _lcam_uop_T_fp_rm; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_fp_typ = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_typ : _lcam_uop_T_fp_typ; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_xcpt_pf_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_pf_if : _lcam_uop_T_xcpt_pf_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_xcpt_ae_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ae_if : _lcam_uop_T_xcpt_ae_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_xcpt_ma_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ma_if : _lcam_uop_T_xcpt_ma_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_bp_debug_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_debug_if : _lcam_uop_T_bp_debug_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_bp_xcpt_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_xcpt_if : _lcam_uop_T_bp_xcpt_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_debug_fsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_fsrc : _lcam_uop_T_debug_fsrc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_debug_tsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_tsrc : _lcam_uop_T_debug_tsrc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [31:0] lcam_uop_0_inst = _lcam_uop_T_1_inst; // @[lsu.scala:321:49, :1137:37] wire [31:0] lcam_uop_0_debug_inst = _lcam_uop_T_1_debug_inst; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_rvc = _lcam_uop_T_1_is_rvc; // @[lsu.scala:321:49, :1137:37] wire [39:0] lcam_uop_0_debug_pc = _lcam_uop_T_1_debug_pc; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_0 = _lcam_uop_T_1_iq_type_0; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_1 = _lcam_uop_T_1_iq_type_1; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_2 = _lcam_uop_T_1_iq_type_2; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_3 = _lcam_uop_T_1_iq_type_3; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_0 = _lcam_uop_T_1_fu_code_0; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_1 = _lcam_uop_T_1_fu_code_1; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_2 = _lcam_uop_T_1_fu_code_2; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_3 = _lcam_uop_T_1_fu_code_3; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_4 = _lcam_uop_T_1_fu_code_4; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_5 = _lcam_uop_T_1_fu_code_5; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_6 = _lcam_uop_T_1_fu_code_6; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_7 = _lcam_uop_T_1_fu_code_7; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_8 = _lcam_uop_T_1_fu_code_8; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_9 = _lcam_uop_T_1_fu_code_9; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_issued = _lcam_uop_T_1_iw_issued; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_issued_partial_agen = _lcam_uop_T_1_iw_issued_partial_agen; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_issued_partial_dgen = _lcam_uop_T_1_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_iw_p1_speculative_child = _lcam_uop_T_1_iw_p1_speculative_child; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_iw_p2_speculative_child = _lcam_uop_T_1_iw_p2_speculative_child; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_p1_bypass_hint = _lcam_uop_T_1_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_p2_bypass_hint = _lcam_uop_T_1_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_p3_bypass_hint = _lcam_uop_T_1_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_dis_col_sel = _lcam_uop_T_1_dis_col_sel; // @[lsu.scala:321:49, :1137:37] wire [11:0] lcam_uop_0_br_mask = _lcam_uop_T_1_br_mask; // @[lsu.scala:321:49, :1137:37] wire [3:0] lcam_uop_0_br_tag = _lcam_uop_T_1_br_tag; // @[lsu.scala:321:49, :1137:37] wire [3:0] lcam_uop_0_br_type = _lcam_uop_T_1_br_type; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_sfb = _lcam_uop_T_1_is_sfb; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_fence = _lcam_uop_T_1_is_fence; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_fencei = _lcam_uop_T_1_is_fencei; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_sfence = _lcam_uop_T_1_is_sfence; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_amo = _lcam_uop_T_1_is_amo; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_eret = _lcam_uop_T_1_is_eret; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_sys_pc2epc = _lcam_uop_T_1_is_sys_pc2epc; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_rocc = _lcam_uop_T_1_is_rocc; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_mov = _lcam_uop_T_1_is_mov; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_ftq_idx = _lcam_uop_T_1_ftq_idx; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_edge_inst = _lcam_uop_T_1_edge_inst; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_pc_lob = _lcam_uop_T_1_pc_lob; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_taken = _lcam_uop_T_1_taken; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_imm_rename = _lcam_uop_T_1_imm_rename; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_imm_sel = _lcam_uop_T_1_imm_sel; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_pimm = _lcam_uop_T_1_pimm; // @[lsu.scala:321:49, :1137:37] wire [19:0] lcam_uop_0_imm_packed = _lcam_uop_T_1_imm_packed; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_op1_sel = _lcam_uop_T_1_op1_sel; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_op2_sel = _lcam_uop_T_1_op2_sel; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ldst = _lcam_uop_T_1_fp_ctrl_ldst; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_wen = _lcam_uop_T_1_fp_ctrl_wen; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ren1 = _lcam_uop_T_1_fp_ctrl_ren1; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ren2 = _lcam_uop_T_1_fp_ctrl_ren2; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ren3 = _lcam_uop_T_1_fp_ctrl_ren3; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_swap12 = _lcam_uop_T_1_fp_ctrl_swap12; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_swap23 = _lcam_uop_T_1_fp_ctrl_swap23; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_fp_ctrl_typeTagIn = _lcam_uop_T_1_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_fp_ctrl_typeTagOut = _lcam_uop_T_1_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_fromint = _lcam_uop_T_1_fp_ctrl_fromint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_toint = _lcam_uop_T_1_fp_ctrl_toint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_fastpipe = _lcam_uop_T_1_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_fma = _lcam_uop_T_1_fp_ctrl_fma; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_div = _lcam_uop_T_1_fp_ctrl_div; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_sqrt = _lcam_uop_T_1_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_wflags = _lcam_uop_T_1_fp_ctrl_wflags; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_vec = _lcam_uop_T_1_fp_ctrl_vec; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_rob_idx = _lcam_uop_T_1_rob_idx; // @[lsu.scala:321:49, :1137:37] wire [3:0] lcam_uop_0_ldq_idx = _lcam_uop_T_1_ldq_idx; // @[lsu.scala:321:49, :1137:37] wire [3:0] lcam_uop_0_stq_idx = _lcam_uop_T_1_stq_idx; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_rxq_idx = _lcam_uop_T_1_rxq_idx; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_pdst = _lcam_uop_T_1_pdst; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_prs1 = _lcam_uop_T_1_prs1; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_prs2 = _lcam_uop_T_1_prs2; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_prs3 = _lcam_uop_T_1_prs3; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_ppred = _lcam_uop_T_1_ppred; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_prs1_busy = _lcam_uop_T_1_prs1_busy; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_prs2_busy = _lcam_uop_T_1_prs2_busy; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_prs3_busy = _lcam_uop_T_1_prs3_busy; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_ppred_busy = _lcam_uop_T_1_ppred_busy; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_stale_pdst = _lcam_uop_T_1_stale_pdst; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_exception = _lcam_uop_T_1_exception; // @[lsu.scala:321:49, :1137:37] wire [63:0] lcam_uop_0_exc_cause = _lcam_uop_T_1_exc_cause; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_mem_cmd = _lcam_uop_T_1_mem_cmd; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_mem_size = _lcam_uop_T_1_mem_size; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_mem_signed = _lcam_uop_T_1_mem_signed; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_uses_ldq = _lcam_uop_T_1_uses_ldq; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_uses_stq = _lcam_uop_T_1_uses_stq; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_unique = _lcam_uop_T_1_is_unique; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_flush_on_commit = _lcam_uop_T_1_flush_on_commit; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_csr_cmd = _lcam_uop_T_1_csr_cmd; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_ldst_is_rs1 = _lcam_uop_T_1_ldst_is_rs1; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_ldst = _lcam_uop_T_1_ldst; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_lrs1 = _lcam_uop_T_1_lrs1; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_lrs2 = _lcam_uop_T_1_lrs2; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_lrs3 = _lcam_uop_T_1_lrs3; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_dst_rtype = _lcam_uop_T_1_dst_rtype; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_lrs1_rtype = _lcam_uop_T_1_lrs1_rtype; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_lrs2_rtype = _lcam_uop_T_1_lrs2_rtype; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_frs3_en = _lcam_uop_T_1_frs3_en; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fcn_dw = _lcam_uop_T_1_fcn_dw; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_fcn_op = _lcam_uop_T_1_fcn_op; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_val = _lcam_uop_T_1_fp_val; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_fp_rm = _lcam_uop_T_1_fp_rm; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_fp_typ = _lcam_uop_T_1_fp_typ; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_xcpt_pf_if = _lcam_uop_T_1_xcpt_pf_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_xcpt_ae_if = _lcam_uop_T_1_xcpt_ae_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_xcpt_ma_if = _lcam_uop_T_1_xcpt_ma_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_bp_debug_if = _lcam_uop_T_1_bp_debug_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_bp_xcpt_if = _lcam_uop_T_1_bp_xcpt_if; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_debug_fsrc = _lcam_uop_T_1_debug_fsrc; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_debug_tsrc = _lcam_uop_T_1_debug_tsrc; // @[lsu.scala:321:49, :1137:37] wire [7:0] lcam_mask_mask; // @[lsu.scala:1951:22] wire [7:0] lcam_mask_0 = lcam_mask_mask; // @[lsu.scala:321:49, :1951:22] wire _lcam_mask_mask_T = lcam_uop_0_mem_size == 2'h0; // @[lsu.scala:321:49, :1953:26] wire [2:0] _lcam_mask_mask_T_1 = lcam_addr_0[2:0]; // @[lsu.scala:321:49, :1953:55] wire [14:0] _lcam_mask_mask_T_2 = 15'h1 << _lcam_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _lcam_mask_mask_T_3 = lcam_uop_0_mem_size == 2'h1; // @[lsu.scala:321:49, :1954:26] wire [1:0] _lcam_mask_mask_T_4 = lcam_addr_0[2:1]; // @[lsu.scala:321:49, :1954:56] wire [2:0] _lcam_mask_mask_T_5 = {_lcam_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _lcam_mask_mask_T_6 = 15'h3 << _lcam_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _lcam_mask_mask_T_7 = lcam_uop_0_mem_size == 2'h2; // @[lsu.scala:321:49, :1955:26] wire _lcam_mask_mask_T_8 = lcam_addr_0[2]; // @[lsu.scala:321:49, :1955:46] wire [7:0] _lcam_mask_mask_T_9 = _lcam_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _lcam_mask_mask_T_10 = &lcam_uop_0_mem_size; // @[lsu.scala:321:49, :1956:26] wire [7:0] _lcam_mask_mask_T_12 = _lcam_mask_mask_T_7 ? _lcam_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_13 = _lcam_mask_mask_T_3 ? _lcam_mask_mask_T_6 : {7'h0, _lcam_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_14 = _lcam_mask_mask_T ? _lcam_mask_mask_T_2 : _lcam_mask_mask_T_13; // @[Mux.scala:126:16] assign lcam_mask_mask = _lcam_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] reg [3:0] lcam_ldq_idx_REG; // @[lsu.scala:1146:58] reg [3:0] lcam_ldq_idx_REG_1; // @[lsu.scala:1147:58] wire [3:0] _lcam_ldq_idx_T_1 = fired_load_retry_0 ? lcam_ldq_idx_REG_1 : 4'h0; // @[lsu.scala:321:49, :1147:{26,58}] wire [3:0] _lcam_ldq_idx_T_2 = fired_load_wakeup_0 ? lcam_ldq_idx_REG : _lcam_ldq_idx_T_1; // @[lsu.scala:321:49, :1146:{26,58}, :1147:26] wire [3:0] _lcam_ldq_idx_T_3 = _lcam_ldq_idx_T ? mem_incoming_uop_0_ldq_idx : _lcam_ldq_idx_T_2; // @[lsu.scala:1053:37, :1144:{26,51}, :1146:26] wire [3:0] lcam_ldq_idx_0 = _lcam_ldq_idx_T_3; // @[lsu.scala:321:49, :1144:26] wire [3:0] _wb_ldst_forward_e_e_valid_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_uop_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_addr_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_addr_is_virtual_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_executed_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_succeeded_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_order_fail_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_observed_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_st_dep_mask_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_ld_byte_mask_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_forward_std_val_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_forward_stq_idx_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [3:0] _wb_ldst_forward_e_e_bits_debug_wb_data_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] reg [3:0] lcam_stq_idx_REG; // @[lsu.scala:1150:56] wire [3:0] _lcam_stq_idx_T = fired_store_retry_0 ? lcam_stq_idx_REG : 4'h0; // @[lsu.scala:321:49, :1150:{26,56}] wire [3:0] _lcam_stq_idx_T_1 = fired_store_agen_0 ? mem_incoming_uop_0_stq_idx : _lcam_stq_idx_T; // @[lsu.scala:321:49, :1053:37, :1149:26, :1150:26] wire [3:0] lcam_stq_idx_0 = _lcam_stq_idx_T_1; // @[lsu.scala:321:49, :1149:26] wire [15:0] _lcam_younger_load_mask_hi_mask_T = 16'h1 << lcam_ldq_idx_0; // @[OneHot.scala:58:35] wire [15:0] _lcam_younger_load_mask_hi_mask_T_1 = _lcam_younger_load_mask_hi_mask_T; // @[OneHot.scala:58:35] wire [15:0] _lcam_younger_load_mask_hi_mask_T_2 = _lcam_younger_load_mask_hi_mask_T_1; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_3 = {1'h0, _lcam_younger_load_mask_hi_mask_T_1[15:1]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_4 = {2'h0, _lcam_younger_load_mask_hi_mask_T_1[15:2]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_5 = {3'h0, _lcam_younger_load_mask_hi_mask_T_1[15:3]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_6 = {4'h0, _lcam_younger_load_mask_hi_mask_T_1[15:4]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_7 = {5'h0, _lcam_younger_load_mask_hi_mask_T_1[15:5]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_8 = {6'h0, _lcam_younger_load_mask_hi_mask_T_1[15:6]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_9 = {7'h0, _lcam_younger_load_mask_hi_mask_T_1[15:7]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_10 = {8'h0, _lcam_younger_load_mask_hi_mask_T_1[15:8]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_11 = {9'h0, _lcam_younger_load_mask_hi_mask_T_1[15:9]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_12 = {10'h0, _lcam_younger_load_mask_hi_mask_T_1[15:10]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_13 = {11'h0, _lcam_younger_load_mask_hi_mask_T_1[15:11]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_14 = {12'h0, _lcam_younger_load_mask_hi_mask_T_1[15:12]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_15 = {13'h0, _lcam_younger_load_mask_hi_mask_T_1[15:13]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_16 = {14'h0, _lcam_younger_load_mask_hi_mask_T_1[15:14]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_17 = {15'h0, _lcam_younger_load_mask_hi_mask_T_1[15]}; // @[util.scala:370:41, :383:29] wire [15:0] _lcam_younger_load_mask_hi_mask_T_18 = _lcam_younger_load_mask_hi_mask_T_2 | _lcam_younger_load_mask_hi_mask_T_3; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_19 = _lcam_younger_load_mask_hi_mask_T_18 | _lcam_younger_load_mask_hi_mask_T_4; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_20 = _lcam_younger_load_mask_hi_mask_T_19 | _lcam_younger_load_mask_hi_mask_T_5; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_21 = _lcam_younger_load_mask_hi_mask_T_20 | _lcam_younger_load_mask_hi_mask_T_6; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_22 = _lcam_younger_load_mask_hi_mask_T_21 | _lcam_younger_load_mask_hi_mask_T_7; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_23 = _lcam_younger_load_mask_hi_mask_T_22 | _lcam_younger_load_mask_hi_mask_T_8; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_24 = _lcam_younger_load_mask_hi_mask_T_23 | _lcam_younger_load_mask_hi_mask_T_9; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_25 = _lcam_younger_load_mask_hi_mask_T_24 | _lcam_younger_load_mask_hi_mask_T_10; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_26 = _lcam_younger_load_mask_hi_mask_T_25 | _lcam_younger_load_mask_hi_mask_T_11; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_27 = _lcam_younger_load_mask_hi_mask_T_26 | _lcam_younger_load_mask_hi_mask_T_12; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_28 = _lcam_younger_load_mask_hi_mask_T_27 | _lcam_younger_load_mask_hi_mask_T_13; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_29 = _lcam_younger_load_mask_hi_mask_T_28 | _lcam_younger_load_mask_hi_mask_T_14; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_30 = _lcam_younger_load_mask_hi_mask_T_29 | _lcam_younger_load_mask_hi_mask_T_15; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_31 = _lcam_younger_load_mask_hi_mask_T_30 | _lcam_younger_load_mask_hi_mask_T_16; // @[util.scala:383:{29,45}] wire [15:0] _lcam_younger_load_mask_hi_mask_T_32 = _lcam_younger_load_mask_hi_mask_T_31 | _lcam_younger_load_mask_hi_mask_T_17; // @[util.scala:383:{29,45}] wire [15:0] lcam_younger_load_mask_hi_mask = ~_lcam_younger_load_mask_hi_mask_T_32; // @[util.scala:370:19, :383:45] wire [15:0] _lcam_younger_load_mask_lo_mask_T = 16'h1 << ldq_head; // @[OneHot.scala:58:35] wire [15:0] _lcam_younger_load_mask_lo_mask_T_1 = _lcam_younger_load_mask_lo_mask_T; // @[OneHot.scala:58:35] wire [16:0] _lcam_younger_load_mask_lo_mask_T_2 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_3 = _lcam_younger_load_mask_lo_mask_T_2[15:0]; // @[util.scala:394:{30,37}] wire [16:0] _lcam_younger_load_mask_lo_mask_T_4 = {_lcam_younger_load_mask_lo_mask_T_1, 1'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_5 = _lcam_younger_load_mask_lo_mask_T_4[15:0]; // @[util.scala:394:{30,37}] wire [18:0] _lcam_younger_load_mask_lo_mask_T_6 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1, 2'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_7 = _lcam_younger_load_mask_lo_mask_T_6[15:0]; // @[util.scala:394:{30,37}] wire [18:0] _lcam_younger_load_mask_lo_mask_T_8 = {_lcam_younger_load_mask_lo_mask_T_1, 3'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_9 = _lcam_younger_load_mask_lo_mask_T_8[15:0]; // @[util.scala:394:{30,37}] wire [22:0] _lcam_younger_load_mask_lo_mask_T_10 = {3'h0, _lcam_younger_load_mask_lo_mask_T_1, 4'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_11 = _lcam_younger_load_mask_lo_mask_T_10[15:0]; // @[util.scala:394:{30,37}] wire [22:0] _lcam_younger_load_mask_lo_mask_T_12 = {2'h0, _lcam_younger_load_mask_lo_mask_T_1, 5'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_13 = _lcam_younger_load_mask_lo_mask_T_12[15:0]; // @[util.scala:394:{30,37}] wire [22:0] _lcam_younger_load_mask_lo_mask_T_14 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1, 6'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_15 = _lcam_younger_load_mask_lo_mask_T_14[15:0]; // @[util.scala:394:{30,37}] wire [22:0] _lcam_younger_load_mask_lo_mask_T_16 = {_lcam_younger_load_mask_lo_mask_T_1, 7'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_17 = _lcam_younger_load_mask_lo_mask_T_16[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_18 = {7'h0, _lcam_younger_load_mask_lo_mask_T_1, 8'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_19 = _lcam_younger_load_mask_lo_mask_T_18[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_20 = {6'h0, _lcam_younger_load_mask_lo_mask_T_1, 9'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_21 = _lcam_younger_load_mask_lo_mask_T_20[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_22 = {5'h0, _lcam_younger_load_mask_lo_mask_T_1, 10'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_23 = _lcam_younger_load_mask_lo_mask_T_22[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_24 = {4'h0, _lcam_younger_load_mask_lo_mask_T_1, 11'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_25 = _lcam_younger_load_mask_lo_mask_T_24[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_26 = {3'h0, _lcam_younger_load_mask_lo_mask_T_1, 12'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_27 = _lcam_younger_load_mask_lo_mask_T_26[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_28 = {2'h0, _lcam_younger_load_mask_lo_mask_T_1, 13'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_29 = _lcam_younger_load_mask_lo_mask_T_28[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_30 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1, 14'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_31 = _lcam_younger_load_mask_lo_mask_T_30[15:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_32 = {_lcam_younger_load_mask_lo_mask_T_1, 15'h0}; // @[util.scala:371:44, :394:30] wire [15:0] _lcam_younger_load_mask_lo_mask_T_33 = _lcam_younger_load_mask_lo_mask_T_32[15:0]; // @[util.scala:394:{30,37}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_34 = _lcam_younger_load_mask_lo_mask_T_3 | _lcam_younger_load_mask_lo_mask_T_5; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_35 = _lcam_younger_load_mask_lo_mask_T_34 | _lcam_younger_load_mask_lo_mask_T_7; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_36 = _lcam_younger_load_mask_lo_mask_T_35 | _lcam_younger_load_mask_lo_mask_T_9; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_37 = _lcam_younger_load_mask_lo_mask_T_36 | _lcam_younger_load_mask_lo_mask_T_11; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_38 = _lcam_younger_load_mask_lo_mask_T_37 | _lcam_younger_load_mask_lo_mask_T_13; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_39 = _lcam_younger_load_mask_lo_mask_T_38 | _lcam_younger_load_mask_lo_mask_T_15; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_40 = _lcam_younger_load_mask_lo_mask_T_39 | _lcam_younger_load_mask_lo_mask_T_17; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_41 = _lcam_younger_load_mask_lo_mask_T_40 | _lcam_younger_load_mask_lo_mask_T_19; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_42 = _lcam_younger_load_mask_lo_mask_T_41 | _lcam_younger_load_mask_lo_mask_T_21; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_43 = _lcam_younger_load_mask_lo_mask_T_42 | _lcam_younger_load_mask_lo_mask_T_23; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_44 = _lcam_younger_load_mask_lo_mask_T_43 | _lcam_younger_load_mask_lo_mask_T_25; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_45 = _lcam_younger_load_mask_lo_mask_T_44 | _lcam_younger_load_mask_lo_mask_T_27; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_46 = _lcam_younger_load_mask_lo_mask_T_45 | _lcam_younger_load_mask_lo_mask_T_29; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_47 = _lcam_younger_load_mask_lo_mask_T_46 | _lcam_younger_load_mask_lo_mask_T_31; // @[util.scala:394:{37,54}] wire [15:0] _lcam_younger_load_mask_lo_mask_T_48 = _lcam_younger_load_mask_lo_mask_T_47 | _lcam_younger_load_mask_lo_mask_T_33; // @[util.scala:394:{37,54}] wire [15:0] lcam_younger_load_mask_lo_mask = ~_lcam_younger_load_mask_lo_mask_T_48; // @[util.scala:371:19, :394:54] wire _lcam_younger_load_mask_T = lcam_ldq_idx_0 < ldq_head; // @[util.scala:372:11] wire [15:0] _lcam_younger_load_mask_T_1 = lcam_younger_load_mask_hi_mask & lcam_younger_load_mask_lo_mask; // @[util.scala:370:19, :371:19, :372:27] wire [15:0] _lcam_younger_load_mask_T_2 = lcam_younger_load_mask_hi_mask | lcam_younger_load_mask_lo_mask; // @[util.scala:370:19, :371:19, :372:46] wire [15:0] _lcam_younger_load_mask_T_3 = _lcam_younger_load_mask_T ? _lcam_younger_load_mask_T_1 : _lcam_younger_load_mask_T_2; // @[util.scala:372:{8,11,27,46}] wire [15:0] _lcam_younger_load_mask_T_4 = _lcam_younger_load_mask_T_3; // @[util.scala:372:{8,56}] wire [15:0] lcam_younger_load_mask_0 = _lcam_younger_load_mask_T_4; // @[util.scala:372:56] wire _can_forward_T_1 = _can_forward_T | fired_load_retry_0; // @[lsu.scala:321:49, :1154:{58,85}] wire _can_forward_T_2 = ~mem_tlb_uncacheable_0; // @[lsu.scala:1071:41, :1155:5] wire _can_forward_T_3 = ~mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:1056:37, :1156:5] wire _can_forward_T_4 = _can_forward_T_1 ? _can_forward_T_2 : _can_forward_T_3; // @[lsu.scala:1154:{38,85}, :1155:5, :1156:5] wire can_forward_0 = _can_forward_T_4; // @[lsu.scala:321:49, :1154:38] wire kill_forward_0; // @[lsu.scala:1159:30] wire [15:0] _ldst_addr_matches_0_T_2; // @[lsu.scala:1344:79] wire [15:0] ldst_addr_matches_0; // @[lsu.scala:1162:34] wire [15:0] _ldst_forward_matches_0_T_2; // @[lsu.scala:1345:82] wire [15:0] ldst_forward_matches_0; // @[lsu.scala:1164:34] wire [15:0] _stld_prs2_matches_0_T_3; // @[lsu.scala:1346:80] wire [15:0] stld_prs2_matches_0; // @[lsu.scala:1166:34] reg s1_executing_loads_0; // @[lsu.scala:1168:35] reg s1_executing_loads_1; // @[lsu.scala:1168:35] reg s1_executing_loads_2; // @[lsu.scala:1168:35] reg s1_executing_loads_3; // @[lsu.scala:1168:35] reg s1_executing_loads_4; // @[lsu.scala:1168:35] reg s1_executing_loads_5; // @[lsu.scala:1168:35] reg s1_executing_loads_6; // @[lsu.scala:1168:35] reg s1_executing_loads_7; // @[lsu.scala:1168:35] reg s1_executing_loads_8; // @[lsu.scala:1168:35] reg s1_executing_loads_9; // @[lsu.scala:1168:35] reg s1_executing_loads_10; // @[lsu.scala:1168:35] reg s1_executing_loads_11; // @[lsu.scala:1168:35] reg s1_executing_loads_12; // @[lsu.scala:1168:35] reg s1_executing_loads_13; // @[lsu.scala:1168:35] reg s1_executing_loads_14; // @[lsu.scala:1168:35] reg s1_executing_loads_15; // @[lsu.scala:1168:35] wire s1_set_execute_0; // @[lsu.scala:1169:36] wire s1_set_execute_1; // @[lsu.scala:1169:36] wire s1_set_execute_2; // @[lsu.scala:1169:36] wire s1_set_execute_3; // @[lsu.scala:1169:36] wire s1_set_execute_4; // @[lsu.scala:1169:36] wire s1_set_execute_5; // @[lsu.scala:1169:36] wire s1_set_execute_6; // @[lsu.scala:1169:36] wire s1_set_execute_7; // @[lsu.scala:1169:36] wire s1_set_execute_8; // @[lsu.scala:1169:36] wire s1_set_execute_9; // @[lsu.scala:1169:36] wire s1_set_execute_10; // @[lsu.scala:1169:36] wire s1_set_execute_11; // @[lsu.scala:1169:36] wire s1_set_execute_12; // @[lsu.scala:1169:36] wire s1_set_execute_13; // @[lsu.scala:1169:36] wire s1_set_execute_14; // @[lsu.scala:1169:36] wire s1_set_execute_15; // @[lsu.scala:1169:36] reg [15:0] wb_ldst_forward_matches_0; // @[lsu.scala:1171:41] wire _wb_ldst_forward_valid_0_T_11; // @[lsu.scala:1380:100] wire wb_ldst_forward_valid_0; // @[lsu.scala:1172:38] wire [31:0] wb_ldst_forward_e_out_uop_inst = wb_ldst_forward_e_e_bits_uop_inst; // @[util.scala:109:23] wire [31:0] wb_ldst_forward_e_out_uop_debug_inst = wb_ldst_forward_e_e_bits_uop_debug_inst; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_rvc = wb_ldst_forward_e_e_bits_uop_is_rvc; // @[util.scala:109:23] wire [39:0] wb_ldst_forward_e_out_uop_debug_pc = wb_ldst_forward_e_e_bits_uop_debug_pc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_0 = wb_ldst_forward_e_e_bits_uop_iq_type_0; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_1 = wb_ldst_forward_e_e_bits_uop_iq_type_1; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_2 = wb_ldst_forward_e_e_bits_uop_iq_type_2; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_3 = wb_ldst_forward_e_e_bits_uop_iq_type_3; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_0 = wb_ldst_forward_e_e_bits_uop_fu_code_0; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_1 = wb_ldst_forward_e_e_bits_uop_fu_code_1; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_2 = wb_ldst_forward_e_e_bits_uop_fu_code_2; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_3 = wb_ldst_forward_e_e_bits_uop_fu_code_3; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_4 = wb_ldst_forward_e_e_bits_uop_fu_code_4; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_5 = wb_ldst_forward_e_e_bits_uop_fu_code_5; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_6 = wb_ldst_forward_e_e_bits_uop_fu_code_6; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_7 = wb_ldst_forward_e_e_bits_uop_fu_code_7; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_8 = wb_ldst_forward_e_e_bits_uop_fu_code_8; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_9 = wb_ldst_forward_e_e_bits_uop_fu_code_9; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_issued = wb_ldst_forward_e_e_bits_uop_iw_issued; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_issued_partial_agen = wb_ldst_forward_e_e_bits_uop_iw_issued_partial_agen; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_issued_partial_dgen = wb_ldst_forward_e_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_iw_p1_speculative_child = wb_ldst_forward_e_e_bits_uop_iw_p1_speculative_child; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_iw_p2_speculative_child = wb_ldst_forward_e_e_bits_uop_iw_p2_speculative_child; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_p1_bypass_hint = wb_ldst_forward_e_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_p2_bypass_hint = wb_ldst_forward_e_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_p3_bypass_hint = wb_ldst_forward_e_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_dis_col_sel = wb_ldst_forward_e_e_bits_uop_dis_col_sel; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_uop_br_tag = wb_ldst_forward_e_e_bits_uop_br_tag; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_uop_br_type = wb_ldst_forward_e_e_bits_uop_br_type; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_sfb = wb_ldst_forward_e_e_bits_uop_is_sfb; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_fence = wb_ldst_forward_e_e_bits_uop_is_fence; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_fencei = wb_ldst_forward_e_e_bits_uop_is_fencei; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_sfence = wb_ldst_forward_e_e_bits_uop_is_sfence; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_amo = wb_ldst_forward_e_e_bits_uop_is_amo; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_eret = wb_ldst_forward_e_e_bits_uop_is_eret; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_sys_pc2epc = wb_ldst_forward_e_e_bits_uop_is_sys_pc2epc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_rocc = wb_ldst_forward_e_e_bits_uop_is_rocc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_mov = wb_ldst_forward_e_e_bits_uop_is_mov; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_ftq_idx = wb_ldst_forward_e_e_bits_uop_ftq_idx; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_edge_inst = wb_ldst_forward_e_e_bits_uop_edge_inst; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_pc_lob = wb_ldst_forward_e_e_bits_uop_pc_lob; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_taken = wb_ldst_forward_e_e_bits_uop_taken; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_imm_rename = wb_ldst_forward_e_e_bits_uop_imm_rename; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_imm_sel = wb_ldst_forward_e_e_bits_uop_imm_sel; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_pimm = wb_ldst_forward_e_e_bits_uop_pimm; // @[util.scala:109:23] wire [19:0] wb_ldst_forward_e_out_uop_imm_packed = wb_ldst_forward_e_e_bits_uop_imm_packed; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_op1_sel = wb_ldst_forward_e_e_bits_uop_op1_sel; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_op2_sel = wb_ldst_forward_e_e_bits_uop_op2_sel; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ldst = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ldst; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_wen = wb_ldst_forward_e_e_bits_uop_fp_ctrl_wen; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ren1 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren1; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ren2 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren2; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ren3 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren3; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_swap12 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap12; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_swap23 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap23; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_fp_ctrl_typeTagIn = wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_fp_ctrl_typeTagOut = wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_fromint = wb_ldst_forward_e_e_bits_uop_fp_ctrl_fromint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_toint = wb_ldst_forward_e_e_bits_uop_fp_ctrl_toint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_fastpipe = wb_ldst_forward_e_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_fma = wb_ldst_forward_e_e_bits_uop_fp_ctrl_fma; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_div = wb_ldst_forward_e_e_bits_uop_fp_ctrl_div; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_sqrt = wb_ldst_forward_e_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_wflags = wb_ldst_forward_e_e_bits_uop_fp_ctrl_wflags; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_vec = wb_ldst_forward_e_e_bits_uop_fp_ctrl_vec; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_rob_idx = wb_ldst_forward_e_e_bits_uop_rob_idx; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_uop_ldq_idx = wb_ldst_forward_e_e_bits_uop_ldq_idx; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_uop_stq_idx = wb_ldst_forward_e_e_bits_uop_stq_idx; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_rxq_idx = wb_ldst_forward_e_e_bits_uop_rxq_idx; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_pdst = wb_ldst_forward_e_e_bits_uop_pdst; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_prs1 = wb_ldst_forward_e_e_bits_uop_prs1; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_prs2 = wb_ldst_forward_e_e_bits_uop_prs2; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_prs3 = wb_ldst_forward_e_e_bits_uop_prs3; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_ppred = wb_ldst_forward_e_e_bits_uop_ppred; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_prs1_busy = wb_ldst_forward_e_e_bits_uop_prs1_busy; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_prs2_busy = wb_ldst_forward_e_e_bits_uop_prs2_busy; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_prs3_busy = wb_ldst_forward_e_e_bits_uop_prs3_busy; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_ppred_busy = wb_ldst_forward_e_e_bits_uop_ppred_busy; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_stale_pdst = wb_ldst_forward_e_e_bits_uop_stale_pdst; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_exception = wb_ldst_forward_e_e_bits_uop_exception; // @[util.scala:109:23] wire [63:0] wb_ldst_forward_e_out_uop_exc_cause = wb_ldst_forward_e_e_bits_uop_exc_cause; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_mem_cmd = wb_ldst_forward_e_e_bits_uop_mem_cmd; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_mem_size = wb_ldst_forward_e_e_bits_uop_mem_size; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_mem_signed = wb_ldst_forward_e_e_bits_uop_mem_signed; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_uses_ldq = wb_ldst_forward_e_e_bits_uop_uses_ldq; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_uses_stq = wb_ldst_forward_e_e_bits_uop_uses_stq; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_unique = wb_ldst_forward_e_e_bits_uop_is_unique; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_flush_on_commit = wb_ldst_forward_e_e_bits_uop_flush_on_commit; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_csr_cmd = wb_ldst_forward_e_e_bits_uop_csr_cmd; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_ldst_is_rs1 = wb_ldst_forward_e_e_bits_uop_ldst_is_rs1; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_ldst = wb_ldst_forward_e_e_bits_uop_ldst; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_lrs1 = wb_ldst_forward_e_e_bits_uop_lrs1; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_lrs2 = wb_ldst_forward_e_e_bits_uop_lrs2; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_lrs3 = wb_ldst_forward_e_e_bits_uop_lrs3; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_dst_rtype = wb_ldst_forward_e_e_bits_uop_dst_rtype; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_lrs1_rtype = wb_ldst_forward_e_e_bits_uop_lrs1_rtype; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_lrs2_rtype = wb_ldst_forward_e_e_bits_uop_lrs2_rtype; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_frs3_en = wb_ldst_forward_e_e_bits_uop_frs3_en; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fcn_dw = wb_ldst_forward_e_e_bits_uop_fcn_dw; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_fcn_op = wb_ldst_forward_e_e_bits_uop_fcn_op; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_val = wb_ldst_forward_e_e_bits_uop_fp_val; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_fp_rm = wb_ldst_forward_e_e_bits_uop_fp_rm; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_fp_typ = wb_ldst_forward_e_e_bits_uop_fp_typ; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_xcpt_pf_if = wb_ldst_forward_e_e_bits_uop_xcpt_pf_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_xcpt_ae_if = wb_ldst_forward_e_e_bits_uop_xcpt_ae_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_xcpt_ma_if = wb_ldst_forward_e_e_bits_uop_xcpt_ma_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_bp_debug_if = wb_ldst_forward_e_e_bits_uop_bp_debug_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_bp_xcpt_if = wb_ldst_forward_e_e_bits_uop_bp_xcpt_if; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_debug_fsrc = wb_ldst_forward_e_e_bits_uop_debug_fsrc; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_debug_tsrc = wb_ldst_forward_e_e_bits_uop_debug_tsrc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_addr_valid = wb_ldst_forward_e_e_bits_addr_valid; // @[util.scala:109:23] wire [39:0] wb_ldst_forward_e_out_addr_bits = wb_ldst_forward_e_e_bits_addr_bits; // @[util.scala:109:23] wire wb_ldst_forward_e_out_addr_is_virtual = wb_ldst_forward_e_e_bits_addr_is_virtual; // @[util.scala:109:23] wire wb_ldst_forward_e_out_addr_is_uncacheable = wb_ldst_forward_e_e_bits_addr_is_uncacheable; // @[util.scala:109:23] wire wb_ldst_forward_e_out_executed = wb_ldst_forward_e_e_bits_executed; // @[util.scala:109:23] wire wb_ldst_forward_e_out_succeeded = wb_ldst_forward_e_e_bits_succeeded; // @[util.scala:109:23] wire wb_ldst_forward_e_out_order_fail = wb_ldst_forward_e_e_bits_order_fail; // @[util.scala:109:23] wire wb_ldst_forward_e_out_observed = wb_ldst_forward_e_e_bits_observed; // @[util.scala:109:23] wire [15:0] wb_ldst_forward_e_out_st_dep_mask = wb_ldst_forward_e_e_bits_st_dep_mask; // @[util.scala:109:23] wire [7:0] wb_ldst_forward_e_out_ld_byte_mask = wb_ldst_forward_e_e_bits_ld_byte_mask; // @[util.scala:109:23] wire wb_ldst_forward_e_out_forward_std_val = wb_ldst_forward_e_e_bits_forward_std_val; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_forward_stq_idx = wb_ldst_forward_e_e_bits_forward_stq_idx; // @[util.scala:109:23] wire [63:0] wb_ldst_forward_e_out_debug_wb_data = wb_ldst_forward_e_e_bits_debug_wb_data; // @[util.scala:109:23] wire [11:0] wb_ldst_forward_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_valid; // @[lsu.scala:233:17] wire [3:0] _wb_ldst_forward_e_e_valid_T_1 = _wb_ldst_forward_e_e_valid_T; assign wb_ldst_forward_e_e_valid = _GEN_25[_wb_ldst_forward_e_e_valid_T_1]; // @[lsu.scala:233:17, :234:32, :387:15] wire [3:0] _wb_ldst_forward_e_e_bits_uop_T_1 = _wb_ldst_forward_e_e_bits_uop_T; assign wb_ldst_forward_e_e_bits_uop_inst = _GEN_76[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_inst = _GEN_77[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_rvc = _GEN_78[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_pc = _GEN_79[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_0 = _GEN_80[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_1 = _GEN_81[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_2 = _GEN_82[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_3 = _GEN_83[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_0 = _GEN_84[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_1 = _GEN_85[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_2 = _GEN_86[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_3 = _GEN_87[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_4 = _GEN_88[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_5 = _GEN_89[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_6 = _GEN_90[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_7 = _GEN_91[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_8 = _GEN_92[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_9 = _GEN_93[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_issued = _GEN_94[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_issued_partial_agen = _GEN_95[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_issued_partial_dgen = _GEN_96[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p1_speculative_child = _GEN_97[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p2_speculative_child = _GEN_98[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p1_bypass_hint = _GEN_99[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p2_bypass_hint = _GEN_100[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p3_bypass_hint = _GEN_101[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_dis_col_sel = _GEN_102[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_br_mask = _GEN_103[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_br_tag = _GEN_104[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_br_type = _GEN_105[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_sfb = _GEN_106[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_fence = _GEN_107[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_fencei = _GEN_108[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_sfence = _GEN_109[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_amo = _GEN_110[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_eret = _GEN_111[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_sys_pc2epc = _GEN_112[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_rocc = _GEN_113[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_mov = _GEN_114[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ftq_idx = _GEN_115[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_edge_inst = _GEN_116[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_pc_lob = _GEN_117[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_taken = _GEN_118[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_imm_rename = _GEN_119[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_imm_sel = _GEN_120[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_pimm = _GEN_121[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_imm_packed = _GEN_122[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_op1_sel = _GEN_123[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_op2_sel = _GEN_124[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ldst = _GEN_125[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_wen = _GEN_126[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren1 = _GEN_127[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren2 = _GEN_128[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren3 = _GEN_129[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap12 = _GEN_130[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap23 = _GEN_131[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_132[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_133[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_fromint = _GEN_134[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_toint = _GEN_135[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_136[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_fma = _GEN_137[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_div = _GEN_138[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_sqrt = _GEN_139[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_wflags = _GEN_140[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_vec = _GEN_141[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_rob_idx = _GEN_142[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ldq_idx = _GEN_143[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_stq_idx = _GEN_144[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_rxq_idx = _GEN_145[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_pdst = _GEN_146[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs1 = _GEN_147[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs2 = _GEN_148[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs3 = _GEN_149[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ppred = _GEN_150[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs1_busy = _GEN_151[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs2_busy = _GEN_152[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs3_busy = _GEN_153[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ppred_busy = _GEN_154[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_stale_pdst = _GEN_155[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_exception = _GEN_156[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_exc_cause = _GEN_157[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_mem_cmd = _GEN_158[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_mem_size = _GEN_159[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_mem_signed = _GEN_160[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_uses_ldq = _GEN_161[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_uses_stq = _GEN_162[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_unique = _GEN_163[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_flush_on_commit = _GEN_164[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_csr_cmd = _GEN_165[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ldst_is_rs1 = _GEN_166[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ldst = _GEN_167[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs1 = _GEN_168[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs2 = _GEN_169[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs3 = _GEN_170[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_dst_rtype = _GEN_171[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs1_rtype = _GEN_172[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs2_rtype = _GEN_173[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_frs3_en = _GEN_174[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fcn_dw = _GEN_175[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fcn_op = _GEN_176[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_val = _GEN_177[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_rm = _GEN_178[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_typ = _GEN_179[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_xcpt_pf_if = _GEN_180[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_xcpt_ae_if = _GEN_181[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_xcpt_ma_if = _GEN_182[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_bp_debug_if = _GEN_183[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_bp_xcpt_if = _GEN_184[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_fsrc = _GEN_185[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_tsrc = _GEN_186[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] wire [3:0] _wb_ldst_forward_e_e_bits_addr_T_1 = _wb_ldst_forward_e_e_bits_addr_T; assign wb_ldst_forward_e_e_bits_addr_valid = _GEN_187[_wb_ldst_forward_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] assign wb_ldst_forward_e_e_bits_addr_bits = _GEN_188[_wb_ldst_forward_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] wire [3:0] _wb_ldst_forward_e_e_bits_addr_is_virtual_T_1 = _wb_ldst_forward_e_e_bits_addr_is_virtual_T; assign wb_ldst_forward_e_e_bits_addr_is_virtual = _GEN_189[_wb_ldst_forward_e_e_bits_addr_is_virtual_T_1]; // @[lsu.scala:233:17, :237:32] wire [3:0] _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T_1 = _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T; assign wb_ldst_forward_e_e_bits_addr_is_uncacheable = _GEN_190[_wb_ldst_forward_e_e_bits_addr_is_uncacheable_T_1]; // @[lsu.scala:233:17, :238:32] wire [3:0] _wb_ldst_forward_e_e_bits_executed_T_1 = _wb_ldst_forward_e_e_bits_executed_T; assign wb_ldst_forward_e_e_bits_executed = _GEN_191[_wb_ldst_forward_e_e_bits_executed_T_1]; // @[lsu.scala:233:17, :239:32] wire [3:0] _wb_ldst_forward_e_e_bits_succeeded_T_1 = _wb_ldst_forward_e_e_bits_succeeded_T; assign wb_ldst_forward_e_e_bits_succeeded = _GEN_192[_wb_ldst_forward_e_e_bits_succeeded_T_1]; // @[lsu.scala:233:17, :240:32] wire [3:0] _wb_ldst_forward_e_e_bits_order_fail_T_1 = _wb_ldst_forward_e_e_bits_order_fail_T; assign wb_ldst_forward_e_e_bits_order_fail = _GEN_193[_wb_ldst_forward_e_e_bits_order_fail_T_1]; // @[lsu.scala:233:17, :241:32] wire [3:0] _wb_ldst_forward_e_e_bits_observed_T_1 = _wb_ldst_forward_e_e_bits_observed_T; assign wb_ldst_forward_e_e_bits_observed = _GEN_194[_wb_ldst_forward_e_e_bits_observed_T_1]; // @[lsu.scala:233:17, :242:32] wire [3:0] _wb_ldst_forward_e_e_bits_st_dep_mask_T_1 = _wb_ldst_forward_e_e_bits_st_dep_mask_T; assign wb_ldst_forward_e_e_bits_st_dep_mask = _GEN_195[_wb_ldst_forward_e_e_bits_st_dep_mask_T_1]; // @[lsu.scala:233:17, :243:32] wire [3:0] _wb_ldst_forward_e_e_bits_ld_byte_mask_T_1 = _wb_ldst_forward_e_e_bits_ld_byte_mask_T; assign wb_ldst_forward_e_e_bits_ld_byte_mask = _GEN_196[_wb_ldst_forward_e_e_bits_ld_byte_mask_T_1]; // @[lsu.scala:233:17, :244:32] wire [3:0] _wb_ldst_forward_e_e_bits_forward_std_val_T_1 = _wb_ldst_forward_e_e_bits_forward_std_val_T; assign wb_ldst_forward_e_e_bits_forward_std_val = _GEN_197[_wb_ldst_forward_e_e_bits_forward_std_val_T_1]; // @[lsu.scala:233:17, :245:32] wire [3:0] _wb_ldst_forward_e_e_bits_forward_stq_idx_T_1 = _wb_ldst_forward_e_e_bits_forward_stq_idx_T; assign wb_ldst_forward_e_e_bits_forward_stq_idx = _GEN_198[_wb_ldst_forward_e_e_bits_forward_stq_idx_T_1]; // @[lsu.scala:233:17, :246:32] wire [3:0] _wb_ldst_forward_e_e_bits_debug_wb_data_T_1 = _wb_ldst_forward_e_e_bits_debug_wb_data_T; assign wb_ldst_forward_e_e_bits_debug_wb_data = _GEN_199[_wb_ldst_forward_e_e_bits_debug_wb_data_T_1]; // @[lsu.scala:233:17, :247:32] wire [11:0] _wb_ldst_forward_e_out_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] wb_ldst_forward_e_out_uop_br_mask; // @[util.scala:109:23] wire [11:0] _wb_ldst_forward_e_out_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _wb_ldst_forward_e_out_uop_br_mask_T_1 = wb_ldst_forward_e_e_bits_uop_br_mask & _wb_ldst_forward_e_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign wb_ldst_forward_e_out_uop_br_mask = _wb_ldst_forward_e_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] reg [31:0] wb_ldst_forward_e_REG_uop_inst; // @[lsu.scala:1173:55] wire [31:0] wb_ldst_forward_e_0_uop_inst = wb_ldst_forward_e_REG_uop_inst; // @[lsu.scala:321:49, :1173:55] reg [31:0] wb_ldst_forward_e_REG_uop_debug_inst; // @[lsu.scala:1173:55] wire [31:0] wb_ldst_forward_e_0_uop_debug_inst = wb_ldst_forward_e_REG_uop_debug_inst; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_rvc; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_rvc = wb_ldst_forward_e_REG_uop_is_rvc; // @[lsu.scala:321:49, :1173:55] reg [39:0] wb_ldst_forward_e_REG_uop_debug_pc; // @[lsu.scala:1173:55] wire [39:0] wb_ldst_forward_e_0_uop_debug_pc = wb_ldst_forward_e_REG_uop_debug_pc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_0; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_0 = wb_ldst_forward_e_REG_uop_iq_type_0; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_1 = wb_ldst_forward_e_REG_uop_iq_type_1; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_2; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_2 = wb_ldst_forward_e_REG_uop_iq_type_2; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_3; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_3 = wb_ldst_forward_e_REG_uop_iq_type_3; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_0; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_0 = wb_ldst_forward_e_REG_uop_fu_code_0; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_1 = wb_ldst_forward_e_REG_uop_fu_code_1; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_2; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_2 = wb_ldst_forward_e_REG_uop_fu_code_2; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_3; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_3 = wb_ldst_forward_e_REG_uop_fu_code_3; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_4; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_4 = wb_ldst_forward_e_REG_uop_fu_code_4; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_5; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_5 = wb_ldst_forward_e_REG_uop_fu_code_5; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_6; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_6 = wb_ldst_forward_e_REG_uop_fu_code_6; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_7; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_7 = wb_ldst_forward_e_REG_uop_fu_code_7; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_8; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_8 = wb_ldst_forward_e_REG_uop_fu_code_8; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_9; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_9 = wb_ldst_forward_e_REG_uop_fu_code_9; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_issued; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_issued = wb_ldst_forward_e_REG_uop_iw_issued; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_issued_partial_agen; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_issued_partial_agen = wb_ldst_forward_e_REG_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_issued_partial_dgen; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_issued_partial_dgen = wb_ldst_forward_e_REG_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_iw_p1_speculative_child; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_iw_p1_speculative_child = wb_ldst_forward_e_REG_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_iw_p2_speculative_child; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_iw_p2_speculative_child = wb_ldst_forward_e_REG_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_p1_bypass_hint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_p1_bypass_hint = wb_ldst_forward_e_REG_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_p2_bypass_hint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_p2_bypass_hint = wb_ldst_forward_e_REG_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_p3_bypass_hint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_p3_bypass_hint = wb_ldst_forward_e_REG_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_dis_col_sel; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_dis_col_sel = wb_ldst_forward_e_REG_uop_dis_col_sel; // @[lsu.scala:321:49, :1173:55] reg [11:0] wb_ldst_forward_e_REG_uop_br_mask; // @[lsu.scala:1173:55] wire [11:0] wb_ldst_forward_e_0_uop_br_mask = wb_ldst_forward_e_REG_uop_br_mask; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_uop_br_tag; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_uop_br_tag = wb_ldst_forward_e_REG_uop_br_tag; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_uop_br_type; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_uop_br_type = wb_ldst_forward_e_REG_uop_br_type; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_sfb; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_sfb = wb_ldst_forward_e_REG_uop_is_sfb; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_fence; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_fence = wb_ldst_forward_e_REG_uop_is_fence; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_fencei; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_fencei = wb_ldst_forward_e_REG_uop_is_fencei; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_sfence; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_sfence = wb_ldst_forward_e_REG_uop_is_sfence; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_amo; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_amo = wb_ldst_forward_e_REG_uop_is_amo; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_eret; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_eret = wb_ldst_forward_e_REG_uop_is_eret; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_sys_pc2epc; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_sys_pc2epc = wb_ldst_forward_e_REG_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_rocc; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_rocc = wb_ldst_forward_e_REG_uop_is_rocc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_mov; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_mov = wb_ldst_forward_e_REG_uop_is_mov; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_ftq_idx; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_ftq_idx = wb_ldst_forward_e_REG_uop_ftq_idx; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_edge_inst; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_edge_inst = wb_ldst_forward_e_REG_uop_edge_inst; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_pc_lob; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_pc_lob = wb_ldst_forward_e_REG_uop_pc_lob; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_taken; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_taken = wb_ldst_forward_e_REG_uop_taken; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_imm_rename; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_imm_rename = wb_ldst_forward_e_REG_uop_imm_rename; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_imm_sel; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_imm_sel = wb_ldst_forward_e_REG_uop_imm_sel; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_pimm; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_pimm = wb_ldst_forward_e_REG_uop_pimm; // @[lsu.scala:321:49, :1173:55] reg [19:0] wb_ldst_forward_e_REG_uop_imm_packed; // @[lsu.scala:1173:55] wire [19:0] wb_ldst_forward_e_0_uop_imm_packed = wb_ldst_forward_e_REG_uop_imm_packed; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_op1_sel; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_op1_sel = wb_ldst_forward_e_REG_uop_op1_sel; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_op2_sel; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_op2_sel = wb_ldst_forward_e_REG_uop_op2_sel; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ldst; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ldst = wb_ldst_forward_e_REG_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_wen; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_wen = wb_ldst_forward_e_REG_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ren1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ren1 = wb_ldst_forward_e_REG_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ren2; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ren2 = wb_ldst_forward_e_REG_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ren3; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ren3 = wb_ldst_forward_e_REG_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_swap12; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_swap12 = wb_ldst_forward_e_REG_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_swap23; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_swap23 = wb_ldst_forward_e_REG_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_fp_ctrl_typeTagIn = wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_fp_ctrl_typeTagOut = wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_fromint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_fromint = wb_ldst_forward_e_REG_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_toint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_toint = wb_ldst_forward_e_REG_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_fastpipe; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_fastpipe = wb_ldst_forward_e_REG_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_fma; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_fma = wb_ldst_forward_e_REG_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_div; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_div = wb_ldst_forward_e_REG_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_sqrt; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_sqrt = wb_ldst_forward_e_REG_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_wflags; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_wflags = wb_ldst_forward_e_REG_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_vec; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_vec = wb_ldst_forward_e_REG_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_rob_idx; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_rob_idx = wb_ldst_forward_e_REG_uop_rob_idx; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_uop_ldq_idx; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_uop_ldq_idx = wb_ldst_forward_e_REG_uop_ldq_idx; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_uop_stq_idx; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_uop_stq_idx = wb_ldst_forward_e_REG_uop_stq_idx; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_rxq_idx; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_rxq_idx = wb_ldst_forward_e_REG_uop_rxq_idx; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_pdst; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_pdst = wb_ldst_forward_e_REG_uop_pdst; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_prs1; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_prs1 = wb_ldst_forward_e_REG_uop_prs1; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_prs2; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_prs2 = wb_ldst_forward_e_REG_uop_prs2; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_prs3; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_prs3 = wb_ldst_forward_e_REG_uop_prs3; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_ppred; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_ppred = wb_ldst_forward_e_REG_uop_ppred; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_prs1_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_prs1_busy = wb_ldst_forward_e_REG_uop_prs1_busy; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_prs2_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_prs2_busy = wb_ldst_forward_e_REG_uop_prs2_busy; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_prs3_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_prs3_busy = wb_ldst_forward_e_REG_uop_prs3_busy; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_ppred_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_ppred_busy = wb_ldst_forward_e_REG_uop_ppred_busy; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_stale_pdst; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_stale_pdst = wb_ldst_forward_e_REG_uop_stale_pdst; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_exception; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_exception = wb_ldst_forward_e_REG_uop_exception; // @[lsu.scala:321:49, :1173:55] reg [63:0] wb_ldst_forward_e_REG_uop_exc_cause; // @[lsu.scala:1173:55] wire [63:0] wb_ldst_forward_e_0_uop_exc_cause = wb_ldst_forward_e_REG_uop_exc_cause; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_mem_cmd; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_mem_cmd = wb_ldst_forward_e_REG_uop_mem_cmd; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_mem_size; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_mem_size = wb_ldst_forward_e_REG_uop_mem_size; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_mem_signed; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_mem_signed = wb_ldst_forward_e_REG_uop_mem_signed; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_uses_ldq; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_uses_ldq = wb_ldst_forward_e_REG_uop_uses_ldq; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_uses_stq; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_uses_stq = wb_ldst_forward_e_REG_uop_uses_stq; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_unique; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_unique = wb_ldst_forward_e_REG_uop_is_unique; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_flush_on_commit; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_flush_on_commit = wb_ldst_forward_e_REG_uop_flush_on_commit; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_csr_cmd; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_csr_cmd = wb_ldst_forward_e_REG_uop_csr_cmd; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_ldst_is_rs1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_ldst_is_rs1 = wb_ldst_forward_e_REG_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_ldst; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_ldst = wb_ldst_forward_e_REG_uop_ldst; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_lrs1; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_lrs1 = wb_ldst_forward_e_REG_uop_lrs1; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_lrs2; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_lrs2 = wb_ldst_forward_e_REG_uop_lrs2; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_lrs3; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_lrs3 = wb_ldst_forward_e_REG_uop_lrs3; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_dst_rtype; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_dst_rtype = wb_ldst_forward_e_REG_uop_dst_rtype; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_lrs1_rtype; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_lrs1_rtype = wb_ldst_forward_e_REG_uop_lrs1_rtype; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_lrs2_rtype; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_lrs2_rtype = wb_ldst_forward_e_REG_uop_lrs2_rtype; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_frs3_en; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_frs3_en = wb_ldst_forward_e_REG_uop_frs3_en; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fcn_dw; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fcn_dw = wb_ldst_forward_e_REG_uop_fcn_dw; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_fcn_op; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_fcn_op = wb_ldst_forward_e_REG_uop_fcn_op; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_val; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_val = wb_ldst_forward_e_REG_uop_fp_val; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_fp_rm; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_fp_rm = wb_ldst_forward_e_REG_uop_fp_rm; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_fp_typ; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_fp_typ = wb_ldst_forward_e_REG_uop_fp_typ; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_xcpt_pf_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_xcpt_pf_if = wb_ldst_forward_e_REG_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_xcpt_ae_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_xcpt_ae_if = wb_ldst_forward_e_REG_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_xcpt_ma_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_xcpt_ma_if = wb_ldst_forward_e_REG_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_bp_debug_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_bp_debug_if = wb_ldst_forward_e_REG_uop_bp_debug_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_bp_xcpt_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_bp_xcpt_if = wb_ldst_forward_e_REG_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_debug_fsrc; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_debug_fsrc = wb_ldst_forward_e_REG_uop_debug_fsrc; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_debug_tsrc; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_debug_tsrc = wb_ldst_forward_e_REG_uop_debug_tsrc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_addr_valid; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_addr_valid = wb_ldst_forward_e_REG_addr_valid; // @[lsu.scala:321:49, :1173:55] reg [39:0] wb_ldst_forward_e_REG_addr_bits; // @[lsu.scala:1173:55] wire [39:0] wb_ldst_forward_e_0_addr_bits = wb_ldst_forward_e_REG_addr_bits; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_addr_is_virtual; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_addr_is_virtual = wb_ldst_forward_e_REG_addr_is_virtual; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_addr_is_uncacheable; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_addr_is_uncacheable = wb_ldst_forward_e_REG_addr_is_uncacheable; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_executed; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_executed = wb_ldst_forward_e_REG_executed; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_succeeded; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_succeeded = wb_ldst_forward_e_REG_succeeded; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_order_fail; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_order_fail = wb_ldst_forward_e_REG_order_fail; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_observed; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_observed = wb_ldst_forward_e_REG_observed; // @[lsu.scala:321:49, :1173:55] reg [15:0] wb_ldst_forward_e_REG_st_dep_mask; // @[lsu.scala:1173:55] wire [15:0] wb_ldst_forward_e_0_st_dep_mask = wb_ldst_forward_e_REG_st_dep_mask; // @[lsu.scala:321:49, :1173:55] reg [7:0] wb_ldst_forward_e_REG_ld_byte_mask; // @[lsu.scala:1173:55] wire [7:0] wb_ldst_forward_e_0_ld_byte_mask = wb_ldst_forward_e_REG_ld_byte_mask; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_forward_std_val; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_forward_std_val = wb_ldst_forward_e_REG_forward_std_val; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_forward_stq_idx; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_forward_stq_idx = wb_ldst_forward_e_REG_forward_stq_idx; // @[lsu.scala:321:49, :1173:55] reg [63:0] wb_ldst_forward_e_REG_debug_wb_data; // @[lsu.scala:1173:55] wire [63:0] wb_ldst_forward_e_0_debug_wb_data = wb_ldst_forward_e_REG_debug_wb_data; // @[lsu.scala:321:49, :1173:55] wire [1:0] size_1 = wb_ldst_forward_e_0_uop_mem_size; // @[AMOALU.scala:11:18] reg [3:0] wb_ldst_forward_ldq_idx_0; // @[lsu.scala:1174:41] reg [39:0] wb_ldst_forward_ld_addr_0; // @[lsu.scala:1175:41] wire [3:0] wb_ldst_forward_stq_idx_0; // @[lsu.scala:1176:38] wire failed_load; // @[lsu.scala:1178:29] wire [33:0] _block_addr_matches_T = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_3 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_6 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_9 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_12 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_15 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_18 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_21 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_24 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_27 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_30 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_33 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_36 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_39 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_42 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_45 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_1 = ldq_addr_0_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_2 = _block_addr_matches_T == _block_addr_matches_T_1; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_0 = _block_addr_matches_T_2; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_4 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_8 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_12 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_16 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_20 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_24 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_28 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_32 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_36 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_40 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_44 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_48 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_52 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_56 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_60 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_1 = ldq_addr_0_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_2 = _dword_addr_matches_T == _dword_addr_matches_T_1; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_3 = block_addr_matches_0 & _dword_addr_matches_T_2; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_0 = _dword_addr_matches_T_3; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_392 = ldq_ld_byte_mask_0 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T; // @[lsu.scala:1197:46] assign _mask_match_T = _GEN_392; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T; // @[lsu.scala:1198:46] assign _mask_overlap_T = _GEN_392; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_1 = _mask_match_T == ldq_ld_byte_mask_0; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_0 = _mask_match_T_1; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_1 = |_mask_overlap_T; // @[lsu.scala:1198:{46,62}] wire mask_overlap_0 = _mask_overlap_T_1; // @[lsu.scala:321:49, :1198:62] wire _T_290 = ldq_executed_0 | ldq_succeeded_0; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _GEN_393 = {12'h0, lcam_stq_idx_0}; // @[lsu.scala:321:49, :1218:33] wire [15:0] _T_266 = ldq_st_dep_mask_0 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_270 = do_st_search_0 & ldq_valid_0 & ldq_addr_0_valid & _T_290 & ~ldq_addr_is_virtual_0 & _T_266[0] & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T = ldq_forward_stq_idx_0 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_1 = ldq_forward_stq_idx_0 < l_uop_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_2 = _forwarded_is_older_T ^ _forwarded_is_older_T_1; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_3 = lcam_stq_idx_0 < l_uop_stq_idx; // @[util.scala:364:78] wire forwarded_is_older = _forwarded_is_older_T_2 ^ _forwarded_is_older_T_3; // @[util.scala:364:{58,72,78}] wire _T_274 = ~ldq_forward_std_val_0 | ldq_forward_stq_idx_0 != lcam_stq_idx_0 & forwarded_is_older; // @[util.scala:364:72] wire _GEN_394 = _T_270 & _T_274; // @[lsu.scala:1178:29, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76] wire _T_280 = do_ld_search_0 & ldq_valid_0 & ldq_addr_0_valid & ~ldq_addr_is_virtual_0 & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older = lcam_younger_load_mask_0[0]; // @[lsu.scala:321:49, :1237:58] wire _T_299 = ldq_executed_0 & (ldq_succeeded_0 | ldq_will_succeed_0); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_395 = lcam_ldq_idx_0 == 4'h0; // @[lsu.scala:321:49, :1254:48] wire _GEN_396 = lcam_ldq_idx_0 == 4'h1; // @[lsu.scala:321:49, :1254:48] wire _GEN_397 = lcam_ldq_idx_0 == 4'h2; // @[lsu.scala:321:49, :1254:48] wire _GEN_398 = lcam_ldq_idx_0 == 4'h3; // @[lsu.scala:321:49, :1254:48] wire _GEN_399 = lcam_ldq_idx_0 == 4'h4; // @[lsu.scala:321:49, :1254:48] wire _GEN_400 = lcam_ldq_idx_0 == 4'h5; // @[lsu.scala:321:49, :1254:48] wire _GEN_401 = lcam_ldq_idx_0 == 4'h6; // @[lsu.scala:321:49, :1254:48] wire _GEN_402 = lcam_ldq_idx_0 == 4'h7; // @[lsu.scala:321:49, :1254:48] wire _GEN_403 = lcam_ldq_idx_0 == 4'h8; // @[lsu.scala:321:49, :1254:48] wire _GEN_404 = lcam_ldq_idx_0 == 4'h9; // @[lsu.scala:321:49, :1254:48] wire _GEN_405 = lcam_ldq_idx_0 == 4'hA; // @[lsu.scala:321:49, :1254:48] wire _GEN_406 = lcam_ldq_idx_0 == 4'hB; // @[lsu.scala:321:49, :1254:48] wire _GEN_407 = lcam_ldq_idx_0 == 4'hC; // @[lsu.scala:321:49, :1254:48] wire _GEN_408 = lcam_ldq_idx_0 == 4'hD; // @[lsu.scala:321:49, :1254:48] wire _GEN_409 = lcam_ldq_idx_0 == 4'hE; // @[lsu.scala:321:49, :1254:48] reg REG_1; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_4 = ldq_addr_1_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_5 = _block_addr_matches_T_3 == _block_addr_matches_T_4; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_1_0 = _block_addr_matches_T_5; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_5 = ldq_addr_1_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_6 = _dword_addr_matches_T_4 == _dword_addr_matches_T_5; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_7 = block_addr_matches_1_0 & _dword_addr_matches_T_6; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_1_0 = _dword_addr_matches_T_7; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_410 = ldq_ld_byte_mask_1 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_2; // @[lsu.scala:1197:46] assign _mask_match_T_2 = _GEN_410; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_2; // @[lsu.scala:1198:46] assign _mask_overlap_T_2 = _GEN_410; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_3 = _mask_match_T_2 == ldq_ld_byte_mask_1; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_1_0 = _mask_match_T_3; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_3 = |_mask_overlap_T_2; // @[lsu.scala:1198:{46,62}] wire mask_overlap_1_0 = _mask_overlap_T_3; // @[lsu.scala:321:49, :1198:62] wire _T_342 = ldq_executed_1 | ldq_succeeded_1; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_318 = ldq_st_dep_mask_1 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_4 = ldq_forward_stq_idx_1 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_5 = ldq_forward_stq_idx_1 < l_uop_1_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_6 = _forwarded_is_older_T_4 ^ _forwarded_is_older_T_5; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_7 = lcam_stq_idx_0 < l_uop_1_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_1 = _forwarded_is_older_T_6 ^ _forwarded_is_older_T_7; // @[util.scala:364:{58,72,78}] wire _GEN_411 = do_st_search_0 & ldq_valid_1 & ldq_addr_1_valid & _T_342 & ~ldq_addr_is_virtual_1 & _T_318[0] & dword_addr_matches_1_0 & mask_overlap_1_0 & (~ldq_forward_std_val_1 | ldq_forward_stq_idx_1 != lcam_stq_idx_0 & forwarded_is_older_1); // @[util.scala:364:72] wire _T_332 = do_ld_search_0 & ldq_valid_1 & ldq_addr_1_valid & ~ldq_addr_is_virtual_1 & dword_addr_matches_1_0 & mask_overlap_1_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_1 = lcam_younger_load_mask_0[1]; // @[lsu.scala:321:49, :1237:58] wire _T_351 = ldq_executed_1 & (ldq_succeeded_1 | ldq_will_succeed_1); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_412 = searcher_is_older_1 | _GEN_396; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_2; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_7 = ldq_addr_2_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_8 = _block_addr_matches_T_6 == _block_addr_matches_T_7; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_2_0 = _block_addr_matches_T_8; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_9 = ldq_addr_2_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_10 = _dword_addr_matches_T_8 == _dword_addr_matches_T_9; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_11 = block_addr_matches_2_0 & _dword_addr_matches_T_10; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_2_0 = _dword_addr_matches_T_11; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_413 = ldq_ld_byte_mask_2 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_4; // @[lsu.scala:1197:46] assign _mask_match_T_4 = _GEN_413; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_4; // @[lsu.scala:1198:46] assign _mask_overlap_T_4 = _GEN_413; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_5 = _mask_match_T_4 == ldq_ld_byte_mask_2; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_2_0 = _mask_match_T_5; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_5 = |_mask_overlap_T_4; // @[lsu.scala:1198:{46,62}] wire mask_overlap_2_0 = _mask_overlap_T_5; // @[lsu.scala:321:49, :1198:62] wire _T_394 = ldq_executed_2 | ldq_succeeded_2; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_370 = ldq_st_dep_mask_2 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_374 = do_st_search_0 & ldq_valid_2 & ldq_addr_2_valid & _T_394 & ~ldq_addr_is_virtual_2 & _T_370[0] & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_8 = ldq_forward_stq_idx_2 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_9 = ldq_forward_stq_idx_2 < l_uop_2_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_10 = _forwarded_is_older_T_8 ^ _forwarded_is_older_T_9; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_11 = lcam_stq_idx_0 < l_uop_2_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_2 = _forwarded_is_older_T_10 ^ _forwarded_is_older_T_11; // @[util.scala:364:{58,72,78}] wire _T_378 = ~ldq_forward_std_val_2 | ldq_forward_stq_idx_2 != lcam_stq_idx_0 & forwarded_is_older_2; // @[util.scala:364:72] wire _GEN_414 = _T_374 ? _T_378 | _GEN_411 | _GEN_394 : _GEN_411 | _GEN_394; // @[lsu.scala:394:59, :1178:29, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_384 = do_ld_search_0 & ldq_valid_2 & ldq_addr_2_valid & ~ldq_addr_is_virtual_2 & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_2 = lcam_younger_load_mask_0[2]; // @[lsu.scala:321:49, :1237:58] wire _T_403 = ldq_executed_2 & (ldq_succeeded_2 | ldq_will_succeed_2); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_415 = searcher_is_older_2 | _GEN_397; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_3; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_10 = ldq_addr_3_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_11 = _block_addr_matches_T_9 == _block_addr_matches_T_10; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_3_0 = _block_addr_matches_T_11; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_13 = ldq_addr_3_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_14 = _dword_addr_matches_T_12 == _dword_addr_matches_T_13; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_15 = block_addr_matches_3_0 & _dword_addr_matches_T_14; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_3_0 = _dword_addr_matches_T_15; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_416 = ldq_ld_byte_mask_3 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_6; // @[lsu.scala:1197:46] assign _mask_match_T_6 = _GEN_416; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_6; // @[lsu.scala:1198:46] assign _mask_overlap_T_6 = _GEN_416; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_7 = _mask_match_T_6 == ldq_ld_byte_mask_3; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_3_0 = _mask_match_T_7; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_7 = |_mask_overlap_T_6; // @[lsu.scala:1198:{46,62}] wire mask_overlap_3_0 = _mask_overlap_T_7; // @[lsu.scala:321:49, :1198:62] wire _T_446 = ldq_executed_3 | ldq_succeeded_3; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_422 = ldq_st_dep_mask_3 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_12 = ldq_forward_stq_idx_3 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_13 = ldq_forward_stq_idx_3 < l_uop_3_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_14 = _forwarded_is_older_T_12 ^ _forwarded_is_older_T_13; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_15 = lcam_stq_idx_0 < l_uop_3_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_3 = _forwarded_is_older_T_14 ^ _forwarded_is_older_T_15; // @[util.scala:364:{58,72,78}] wire _GEN_417 = do_st_search_0 & ldq_valid_3 & ldq_addr_3_valid & _T_446 & ~ldq_addr_is_virtual_3 & _T_422[0] & dword_addr_matches_3_0 & mask_overlap_3_0 & (~ldq_forward_std_val_3 | ldq_forward_stq_idx_3 != lcam_stq_idx_0 & forwarded_is_older_3); // @[util.scala:364:72] wire _T_436 = do_ld_search_0 & ldq_valid_3 & ldq_addr_3_valid & ~ldq_addr_is_virtual_3 & dword_addr_matches_3_0 & mask_overlap_3_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_3 = lcam_younger_load_mask_0[3]; // @[lsu.scala:321:49, :1237:58] wire _T_455 = ldq_executed_3 & (ldq_succeeded_3 | ldq_will_succeed_3); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_418 = searcher_is_older_3 | _GEN_398; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_4; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_13 = ldq_addr_4_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_14 = _block_addr_matches_T_12 == _block_addr_matches_T_13; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_4_0 = _block_addr_matches_T_14; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_17 = ldq_addr_4_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_18 = _dword_addr_matches_T_16 == _dword_addr_matches_T_17; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_19 = block_addr_matches_4_0 & _dword_addr_matches_T_18; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_4_0 = _dword_addr_matches_T_19; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_419 = ldq_ld_byte_mask_4 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_8; // @[lsu.scala:1197:46] assign _mask_match_T_8 = _GEN_419; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_8; // @[lsu.scala:1198:46] assign _mask_overlap_T_8 = _GEN_419; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_9 = _mask_match_T_8 == ldq_ld_byte_mask_4; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_4_0 = _mask_match_T_9; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_9 = |_mask_overlap_T_8; // @[lsu.scala:1198:{46,62}] wire mask_overlap_4_0 = _mask_overlap_T_9; // @[lsu.scala:321:49, :1198:62] wire _T_498 = ldq_executed_4 | ldq_succeeded_4; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_474 = ldq_st_dep_mask_4 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_478 = do_st_search_0 & ldq_valid_4 & ldq_addr_4_valid & _T_498 & ~ldq_addr_is_virtual_4 & _T_474[0] & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_16 = ldq_forward_stq_idx_4 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_17 = ldq_forward_stq_idx_4 < l_uop_4_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_18 = _forwarded_is_older_T_16 ^ _forwarded_is_older_T_17; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_19 = lcam_stq_idx_0 < l_uop_4_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_4 = _forwarded_is_older_T_18 ^ _forwarded_is_older_T_19; // @[util.scala:364:{58,72,78}] wire _T_482 = ~ldq_forward_std_val_4 | ldq_forward_stq_idx_4 != lcam_stq_idx_0 & forwarded_is_older_4; // @[util.scala:364:72] wire _GEN_420 = _T_478 ? _T_482 | _GEN_417 | _GEN_414 : _GEN_417 | _GEN_414; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_488 = do_ld_search_0 & ldq_valid_4 & ldq_addr_4_valid & ~ldq_addr_is_virtual_4 & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_4 = lcam_younger_load_mask_0[4]; // @[lsu.scala:321:49, :1237:58] wire _T_507 = ldq_executed_4 & (ldq_succeeded_4 | ldq_will_succeed_4); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_421 = searcher_is_older_4 | _GEN_399; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_5; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_16 = ldq_addr_5_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_17 = _block_addr_matches_T_15 == _block_addr_matches_T_16; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_5_0 = _block_addr_matches_T_17; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_21 = ldq_addr_5_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_22 = _dword_addr_matches_T_20 == _dword_addr_matches_T_21; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_23 = block_addr_matches_5_0 & _dword_addr_matches_T_22; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_5_0 = _dword_addr_matches_T_23; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_422 = ldq_ld_byte_mask_5 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_10; // @[lsu.scala:1197:46] assign _mask_match_T_10 = _GEN_422; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_10; // @[lsu.scala:1198:46] assign _mask_overlap_T_10 = _GEN_422; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_11 = _mask_match_T_10 == ldq_ld_byte_mask_5; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_5_0 = _mask_match_T_11; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_11 = |_mask_overlap_T_10; // @[lsu.scala:1198:{46,62}] wire mask_overlap_5_0 = _mask_overlap_T_11; // @[lsu.scala:321:49, :1198:62] wire _T_550 = ldq_executed_5 | ldq_succeeded_5; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_526 = ldq_st_dep_mask_5 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_20 = ldq_forward_stq_idx_5 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_21 = ldq_forward_stq_idx_5 < l_uop_5_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_22 = _forwarded_is_older_T_20 ^ _forwarded_is_older_T_21; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_23 = lcam_stq_idx_0 < l_uop_5_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_5 = _forwarded_is_older_T_22 ^ _forwarded_is_older_T_23; // @[util.scala:364:{58,72,78}] wire _GEN_423 = do_st_search_0 & ldq_valid_5 & ldq_addr_5_valid & _T_550 & ~ldq_addr_is_virtual_5 & _T_526[0] & dword_addr_matches_5_0 & mask_overlap_5_0 & (~ldq_forward_std_val_5 | ldq_forward_stq_idx_5 != lcam_stq_idx_0 & forwarded_is_older_5); // @[util.scala:364:72] wire _T_540 = do_ld_search_0 & ldq_valid_5 & ldq_addr_5_valid & ~ldq_addr_is_virtual_5 & dword_addr_matches_5_0 & mask_overlap_5_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_5 = lcam_younger_load_mask_0[5]; // @[lsu.scala:321:49, :1237:58] wire _T_559 = ldq_executed_5 & (ldq_succeeded_5 | ldq_will_succeed_5); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_424 = searcher_is_older_5 | _GEN_400; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_6; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_19 = ldq_addr_6_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_20 = _block_addr_matches_T_18 == _block_addr_matches_T_19; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_6_0 = _block_addr_matches_T_20; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_25 = ldq_addr_6_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_26 = _dword_addr_matches_T_24 == _dword_addr_matches_T_25; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_27 = block_addr_matches_6_0 & _dword_addr_matches_T_26; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_6_0 = _dword_addr_matches_T_27; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_425 = ldq_ld_byte_mask_6 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_12; // @[lsu.scala:1197:46] assign _mask_match_T_12 = _GEN_425; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_12; // @[lsu.scala:1198:46] assign _mask_overlap_T_12 = _GEN_425; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_13 = _mask_match_T_12 == ldq_ld_byte_mask_6; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_6_0 = _mask_match_T_13; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_13 = |_mask_overlap_T_12; // @[lsu.scala:1198:{46,62}] wire mask_overlap_6_0 = _mask_overlap_T_13; // @[lsu.scala:321:49, :1198:62] wire _T_602 = ldq_executed_6 | ldq_succeeded_6; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_578 = ldq_st_dep_mask_6 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_582 = do_st_search_0 & ldq_valid_6 & ldq_addr_6_valid & _T_602 & ~ldq_addr_is_virtual_6 & _T_578[0] & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_24 = ldq_forward_stq_idx_6 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_25 = ldq_forward_stq_idx_6 < l_uop_6_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_26 = _forwarded_is_older_T_24 ^ _forwarded_is_older_T_25; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_27 = lcam_stq_idx_0 < l_uop_6_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_6 = _forwarded_is_older_T_26 ^ _forwarded_is_older_T_27; // @[util.scala:364:{58,72,78}] wire _T_586 = ~ldq_forward_std_val_6 | ldq_forward_stq_idx_6 != lcam_stq_idx_0 & forwarded_is_older_6; // @[util.scala:364:72] wire _GEN_426 = _T_582 ? _T_586 | _GEN_423 | _GEN_420 : _GEN_423 | _GEN_420; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_592 = do_ld_search_0 & ldq_valid_6 & ldq_addr_6_valid & ~ldq_addr_is_virtual_6 & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_6 = lcam_younger_load_mask_0[6]; // @[lsu.scala:321:49, :1237:58] wire _T_611 = ldq_executed_6 & (ldq_succeeded_6 | ldq_will_succeed_6); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_427 = searcher_is_older_6 | _GEN_401; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_7; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_22 = ldq_addr_7_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_23 = _block_addr_matches_T_21 == _block_addr_matches_T_22; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_7_0 = _block_addr_matches_T_23; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_29 = ldq_addr_7_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_30 = _dword_addr_matches_T_28 == _dword_addr_matches_T_29; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_31 = block_addr_matches_7_0 & _dword_addr_matches_T_30; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_7_0 = _dword_addr_matches_T_31; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_428 = ldq_ld_byte_mask_7 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_14; // @[lsu.scala:1197:46] assign _mask_match_T_14 = _GEN_428; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_14; // @[lsu.scala:1198:46] assign _mask_overlap_T_14 = _GEN_428; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_15 = _mask_match_T_14 == ldq_ld_byte_mask_7; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_7_0 = _mask_match_T_15; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_15 = |_mask_overlap_T_14; // @[lsu.scala:1198:{46,62}] wire mask_overlap_7_0 = _mask_overlap_T_15; // @[lsu.scala:321:49, :1198:62] wire _T_654 = ldq_executed_7 | ldq_succeeded_7; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_630 = ldq_st_dep_mask_7 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_28 = ldq_forward_stq_idx_7 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_29 = ldq_forward_stq_idx_7 < l_uop_7_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_30 = _forwarded_is_older_T_28 ^ _forwarded_is_older_T_29; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_31 = lcam_stq_idx_0 < l_uop_7_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_7 = _forwarded_is_older_T_30 ^ _forwarded_is_older_T_31; // @[util.scala:364:{58,72,78}] wire _GEN_429 = do_st_search_0 & ldq_valid_7 & ldq_addr_7_valid & _T_654 & ~ldq_addr_is_virtual_7 & _T_630[0] & dword_addr_matches_7_0 & mask_overlap_7_0 & (~ldq_forward_std_val_7 | ldq_forward_stq_idx_7 != lcam_stq_idx_0 & forwarded_is_older_7); // @[util.scala:364:72] wire _T_644 = do_ld_search_0 & ldq_valid_7 & ldq_addr_7_valid & ~ldq_addr_is_virtual_7 & dword_addr_matches_7_0 & mask_overlap_7_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_7 = lcam_younger_load_mask_0[7]; // @[lsu.scala:321:49, :1237:58] wire _T_663 = ldq_executed_7 & (ldq_succeeded_7 | ldq_will_succeed_7); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_430 = searcher_is_older_7 | _GEN_402; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_8; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_25 = ldq_addr_8_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_26 = _block_addr_matches_T_24 == _block_addr_matches_T_25; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_8_0 = _block_addr_matches_T_26; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_33 = ldq_addr_8_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_34 = _dword_addr_matches_T_32 == _dword_addr_matches_T_33; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_35 = block_addr_matches_8_0 & _dword_addr_matches_T_34; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_8_0 = _dword_addr_matches_T_35; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_431 = ldq_ld_byte_mask_8 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_16; // @[lsu.scala:1197:46] assign _mask_match_T_16 = _GEN_431; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_16; // @[lsu.scala:1198:46] assign _mask_overlap_T_16 = _GEN_431; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_17 = _mask_match_T_16 == ldq_ld_byte_mask_8; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_8_0 = _mask_match_T_17; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_17 = |_mask_overlap_T_16; // @[lsu.scala:1198:{46,62}] wire mask_overlap_8_0 = _mask_overlap_T_17; // @[lsu.scala:321:49, :1198:62] wire _T_706 = ldq_executed_8 | ldq_succeeded_8; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_682 = ldq_st_dep_mask_8 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_686 = do_st_search_0 & ldq_valid_8 & ldq_addr_8_valid & _T_706 & ~ldq_addr_is_virtual_8 & _T_682[0] & dword_addr_matches_8_0 & mask_overlap_8_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_32 = ldq_forward_stq_idx_8 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_33 = ldq_forward_stq_idx_8 < l_uop_8_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_34 = _forwarded_is_older_T_32 ^ _forwarded_is_older_T_33; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_35 = lcam_stq_idx_0 < l_uop_8_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_8 = _forwarded_is_older_T_34 ^ _forwarded_is_older_T_35; // @[util.scala:364:{58,72,78}] wire _T_690 = ~ldq_forward_std_val_8 | ldq_forward_stq_idx_8 != lcam_stq_idx_0 & forwarded_is_older_8; // @[util.scala:364:72] wire _GEN_432 = _T_686 ? _T_690 | _GEN_429 | _GEN_426 : _GEN_429 | _GEN_426; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_696 = do_ld_search_0 & ldq_valid_8 & ldq_addr_8_valid & ~ldq_addr_is_virtual_8 & dword_addr_matches_8_0 & mask_overlap_8_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_8 = lcam_younger_load_mask_0[8]; // @[lsu.scala:321:49, :1237:58] wire _T_715 = ldq_executed_8 & (ldq_succeeded_8 | ldq_will_succeed_8); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_433 = searcher_is_older_8 | _GEN_403; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_9; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_28 = ldq_addr_9_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_29 = _block_addr_matches_T_27 == _block_addr_matches_T_28; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_9_0 = _block_addr_matches_T_29; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_37 = ldq_addr_9_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_38 = _dword_addr_matches_T_36 == _dword_addr_matches_T_37; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_39 = block_addr_matches_9_0 & _dword_addr_matches_T_38; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_9_0 = _dword_addr_matches_T_39; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_434 = ldq_ld_byte_mask_9 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_18; // @[lsu.scala:1197:46] assign _mask_match_T_18 = _GEN_434; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_18; // @[lsu.scala:1198:46] assign _mask_overlap_T_18 = _GEN_434; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_19 = _mask_match_T_18 == ldq_ld_byte_mask_9; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_9_0 = _mask_match_T_19; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_19 = |_mask_overlap_T_18; // @[lsu.scala:1198:{46,62}] wire mask_overlap_9_0 = _mask_overlap_T_19; // @[lsu.scala:321:49, :1198:62] wire _T_758 = ldq_executed_9 | ldq_succeeded_9; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_734 = ldq_st_dep_mask_9 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_36 = ldq_forward_stq_idx_9 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_37 = ldq_forward_stq_idx_9 < l_uop_9_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_38 = _forwarded_is_older_T_36 ^ _forwarded_is_older_T_37; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_39 = lcam_stq_idx_0 < l_uop_9_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_9 = _forwarded_is_older_T_38 ^ _forwarded_is_older_T_39; // @[util.scala:364:{58,72,78}] wire _GEN_435 = do_st_search_0 & ldq_valid_9 & ldq_addr_9_valid & _T_758 & ~ldq_addr_is_virtual_9 & _T_734[0] & dword_addr_matches_9_0 & mask_overlap_9_0 & (~ldq_forward_std_val_9 | ldq_forward_stq_idx_9 != lcam_stq_idx_0 & forwarded_is_older_9); // @[util.scala:364:72] wire _T_748 = do_ld_search_0 & ldq_valid_9 & ldq_addr_9_valid & ~ldq_addr_is_virtual_9 & dword_addr_matches_9_0 & mask_overlap_9_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_9 = lcam_younger_load_mask_0[9]; // @[lsu.scala:321:49, :1237:58] wire _T_767 = ldq_executed_9 & (ldq_succeeded_9 | ldq_will_succeed_9); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_436 = searcher_is_older_9 | _GEN_404; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_10; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_31 = ldq_addr_10_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_32 = _block_addr_matches_T_30 == _block_addr_matches_T_31; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_10_0 = _block_addr_matches_T_32; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_41 = ldq_addr_10_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_42 = _dword_addr_matches_T_40 == _dword_addr_matches_T_41; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_43 = block_addr_matches_10_0 & _dword_addr_matches_T_42; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_10_0 = _dword_addr_matches_T_43; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_437 = ldq_ld_byte_mask_10 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_20; // @[lsu.scala:1197:46] assign _mask_match_T_20 = _GEN_437; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_20; // @[lsu.scala:1198:46] assign _mask_overlap_T_20 = _GEN_437; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_21 = _mask_match_T_20 == ldq_ld_byte_mask_10; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_10_0 = _mask_match_T_21; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_21 = |_mask_overlap_T_20; // @[lsu.scala:1198:{46,62}] wire mask_overlap_10_0 = _mask_overlap_T_21; // @[lsu.scala:321:49, :1198:62] wire _T_810 = ldq_executed_10 | ldq_succeeded_10; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_786 = ldq_st_dep_mask_10 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_790 = do_st_search_0 & ldq_valid_10 & ldq_addr_10_valid & _T_810 & ~ldq_addr_is_virtual_10 & _T_786[0] & dword_addr_matches_10_0 & mask_overlap_10_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_40 = ldq_forward_stq_idx_10 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_41 = ldq_forward_stq_idx_10 < l_uop_10_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_42 = _forwarded_is_older_T_40 ^ _forwarded_is_older_T_41; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_43 = lcam_stq_idx_0 < l_uop_10_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_10 = _forwarded_is_older_T_42 ^ _forwarded_is_older_T_43; // @[util.scala:364:{58,72,78}] wire _T_794 = ~ldq_forward_std_val_10 | ldq_forward_stq_idx_10 != lcam_stq_idx_0 & forwarded_is_older_10; // @[util.scala:364:72] wire _GEN_438 = _T_790 ? _T_794 | _GEN_435 | _GEN_432 : _GEN_435 | _GEN_432; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_800 = do_ld_search_0 & ldq_valid_10 & ldq_addr_10_valid & ~ldq_addr_is_virtual_10 & dword_addr_matches_10_0 & mask_overlap_10_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_10 = lcam_younger_load_mask_0[10]; // @[lsu.scala:321:49, :1237:58] wire _T_819 = ldq_executed_10 & (ldq_succeeded_10 | ldq_will_succeed_10); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_439 = searcher_is_older_10 | _GEN_405; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_11; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_34 = ldq_addr_11_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_35 = _block_addr_matches_T_33 == _block_addr_matches_T_34; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_11_0 = _block_addr_matches_T_35; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_45 = ldq_addr_11_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_46 = _dword_addr_matches_T_44 == _dword_addr_matches_T_45; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_47 = block_addr_matches_11_0 & _dword_addr_matches_T_46; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_11_0 = _dword_addr_matches_T_47; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_440 = ldq_ld_byte_mask_11 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_22; // @[lsu.scala:1197:46] assign _mask_match_T_22 = _GEN_440; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_22; // @[lsu.scala:1198:46] assign _mask_overlap_T_22 = _GEN_440; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_23 = _mask_match_T_22 == ldq_ld_byte_mask_11; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_11_0 = _mask_match_T_23; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_23 = |_mask_overlap_T_22; // @[lsu.scala:1198:{46,62}] wire mask_overlap_11_0 = _mask_overlap_T_23; // @[lsu.scala:321:49, :1198:62] wire _T_862 = ldq_executed_11 | ldq_succeeded_11; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_838 = ldq_st_dep_mask_11 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_44 = ldq_forward_stq_idx_11 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_45 = ldq_forward_stq_idx_11 < l_uop_11_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_46 = _forwarded_is_older_T_44 ^ _forwarded_is_older_T_45; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_47 = lcam_stq_idx_0 < l_uop_11_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_11 = _forwarded_is_older_T_46 ^ _forwarded_is_older_T_47; // @[util.scala:364:{58,72,78}] wire _GEN_441 = do_st_search_0 & ldq_valid_11 & ldq_addr_11_valid & _T_862 & ~ldq_addr_is_virtual_11 & _T_838[0] & dword_addr_matches_11_0 & mask_overlap_11_0 & (~ldq_forward_std_val_11 | ldq_forward_stq_idx_11 != lcam_stq_idx_0 & forwarded_is_older_11); // @[util.scala:364:72] wire _T_852 = do_ld_search_0 & ldq_valid_11 & ldq_addr_11_valid & ~ldq_addr_is_virtual_11 & dword_addr_matches_11_0 & mask_overlap_11_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_11 = lcam_younger_load_mask_0[11]; // @[lsu.scala:321:49, :1237:58] wire _T_871 = ldq_executed_11 & (ldq_succeeded_11 | ldq_will_succeed_11); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_442 = searcher_is_older_11 | _GEN_406; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_12; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_37 = ldq_addr_12_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_38 = _block_addr_matches_T_36 == _block_addr_matches_T_37; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_12_0 = _block_addr_matches_T_38; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_49 = ldq_addr_12_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_50 = _dword_addr_matches_T_48 == _dword_addr_matches_T_49; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_51 = block_addr_matches_12_0 & _dword_addr_matches_T_50; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_12_0 = _dword_addr_matches_T_51; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_443 = ldq_ld_byte_mask_12 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_24; // @[lsu.scala:1197:46] assign _mask_match_T_24 = _GEN_443; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_24; // @[lsu.scala:1198:46] assign _mask_overlap_T_24 = _GEN_443; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_25 = _mask_match_T_24 == ldq_ld_byte_mask_12; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_12_0 = _mask_match_T_25; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_25 = |_mask_overlap_T_24; // @[lsu.scala:1198:{46,62}] wire mask_overlap_12_0 = _mask_overlap_T_25; // @[lsu.scala:321:49, :1198:62] wire _T_914 = ldq_executed_12 | ldq_succeeded_12; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_890 = ldq_st_dep_mask_12 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_894 = do_st_search_0 & ldq_valid_12 & ldq_addr_12_valid & _T_914 & ~ldq_addr_is_virtual_12 & _T_890[0] & dword_addr_matches_12_0 & mask_overlap_12_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_48 = ldq_forward_stq_idx_12 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_49 = ldq_forward_stq_idx_12 < l_uop_12_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_50 = _forwarded_is_older_T_48 ^ _forwarded_is_older_T_49; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_51 = lcam_stq_idx_0 < l_uop_12_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_12 = _forwarded_is_older_T_50 ^ _forwarded_is_older_T_51; // @[util.scala:364:{58,72,78}] wire _T_898 = ~ldq_forward_std_val_12 | ldq_forward_stq_idx_12 != lcam_stq_idx_0 & forwarded_is_older_12; // @[util.scala:364:72] wire _GEN_444 = _T_894 ? _T_898 | _GEN_441 | _GEN_438 : _GEN_441 | _GEN_438; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_904 = do_ld_search_0 & ldq_valid_12 & ldq_addr_12_valid & ~ldq_addr_is_virtual_12 & dword_addr_matches_12_0 & mask_overlap_12_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_12 = lcam_younger_load_mask_0[12]; // @[lsu.scala:321:49, :1237:58] wire _T_923 = ldq_executed_12 & (ldq_succeeded_12 | ldq_will_succeed_12); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_445 = searcher_is_older_12 | _GEN_407; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_13; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_40 = ldq_addr_13_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_41 = _block_addr_matches_T_39 == _block_addr_matches_T_40; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_13_0 = _block_addr_matches_T_41; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_53 = ldq_addr_13_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_54 = _dword_addr_matches_T_52 == _dword_addr_matches_T_53; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_55 = block_addr_matches_13_0 & _dword_addr_matches_T_54; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_13_0 = _dword_addr_matches_T_55; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_446 = ldq_ld_byte_mask_13 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_26; // @[lsu.scala:1197:46] assign _mask_match_T_26 = _GEN_446; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_26; // @[lsu.scala:1198:46] assign _mask_overlap_T_26 = _GEN_446; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_27 = _mask_match_T_26 == ldq_ld_byte_mask_13; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_13_0 = _mask_match_T_27; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_27 = |_mask_overlap_T_26; // @[lsu.scala:1198:{46,62}] wire mask_overlap_13_0 = _mask_overlap_T_27; // @[lsu.scala:321:49, :1198:62] wire _T_966 = ldq_executed_13 | ldq_succeeded_13; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_942 = ldq_st_dep_mask_13 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_52 = ldq_forward_stq_idx_13 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_53 = ldq_forward_stq_idx_13 < l_uop_13_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_54 = _forwarded_is_older_T_52 ^ _forwarded_is_older_T_53; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_55 = lcam_stq_idx_0 < l_uop_13_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_13 = _forwarded_is_older_T_54 ^ _forwarded_is_older_T_55; // @[util.scala:364:{58,72,78}] wire _GEN_447 = do_st_search_0 & ldq_valid_13 & ldq_addr_13_valid & _T_966 & ~ldq_addr_is_virtual_13 & _T_942[0] & dword_addr_matches_13_0 & mask_overlap_13_0 & (~ldq_forward_std_val_13 | ldq_forward_stq_idx_13 != lcam_stq_idx_0 & forwarded_is_older_13); // @[util.scala:364:72] wire _T_956 = do_ld_search_0 & ldq_valid_13 & ldq_addr_13_valid & ~ldq_addr_is_virtual_13 & dword_addr_matches_13_0 & mask_overlap_13_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_13 = lcam_younger_load_mask_0[13]; // @[lsu.scala:321:49, :1237:58] wire _T_975 = ldq_executed_13 & (ldq_succeeded_13 | ldq_will_succeed_13); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_448 = searcher_is_older_13 | _GEN_408; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_14; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_43 = ldq_addr_14_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_44 = _block_addr_matches_T_42 == _block_addr_matches_T_43; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_14_0 = _block_addr_matches_T_44; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_57 = ldq_addr_14_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_58 = _dword_addr_matches_T_56 == _dword_addr_matches_T_57; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_59 = block_addr_matches_14_0 & _dword_addr_matches_T_58; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_14_0 = _dword_addr_matches_T_59; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_449 = ldq_ld_byte_mask_14 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_28; // @[lsu.scala:1197:46] assign _mask_match_T_28 = _GEN_449; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_28; // @[lsu.scala:1198:46] assign _mask_overlap_T_28 = _GEN_449; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_29 = _mask_match_T_28 == ldq_ld_byte_mask_14; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_14_0 = _mask_match_T_29; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_29 = |_mask_overlap_T_28; // @[lsu.scala:1198:{46,62}] wire mask_overlap_14_0 = _mask_overlap_T_29; // @[lsu.scala:321:49, :1198:62] wire _T_1018 = ldq_executed_14 | ldq_succeeded_14; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_994 = ldq_st_dep_mask_14 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _T_998 = do_st_search_0 & ldq_valid_14 & ldq_addr_14_valid & _T_1018 & ~ldq_addr_is_virtual_14 & _T_994[0] & dword_addr_matches_14_0 & mask_overlap_14_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_56 = ldq_forward_stq_idx_14 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_57 = ldq_forward_stq_idx_14 < l_uop_14_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_58 = _forwarded_is_older_T_56 ^ _forwarded_is_older_T_57; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_59 = lcam_stq_idx_0 < l_uop_14_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_14 = _forwarded_is_older_T_58 ^ _forwarded_is_older_T_59; // @[util.scala:364:{58,72,78}] wire _T_1002 = ~ldq_forward_std_val_14 | ldq_forward_stq_idx_14 != lcam_stq_idx_0 & forwarded_is_older_14; // @[util.scala:364:72] wire _T_1008 = do_ld_search_0 & ldq_valid_14 & ldq_addr_14_valid & ~ldq_addr_is_virtual_14 & dword_addr_matches_14_0 & mask_overlap_14_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_14 = lcam_younger_load_mask_0[14]; // @[lsu.scala:321:49, :1237:58] wire _T_1027 = ldq_executed_14 & (ldq_succeeded_14 | ldq_will_succeed_14); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_450 = searcher_is_older_14 | _GEN_409; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] wire _GEN_451 = (~_T_1008 | _GEN_450 | ~(~_T_1027 & (&lcam_ldq_idx_0))) & (~_T_956 | _GEN_448 | ~(~_T_975 & (&lcam_ldq_idx_0))) & (~_T_904 | _GEN_445 | ~(~_T_923 & (&lcam_ldq_idx_0))) & (~_T_852 | _GEN_442 | ~(~_T_871 & (&lcam_ldq_idx_0))) & (~_T_800 | _GEN_439 | ~(~_T_819 & (&lcam_ldq_idx_0))) & (~_T_748 | _GEN_436 | ~(~_T_767 & (&lcam_ldq_idx_0))) & (~_T_696 | _GEN_433 | ~(~_T_715 & (&lcam_ldq_idx_0))) & (~_T_644 | _GEN_430 | ~(~_T_663 & (&lcam_ldq_idx_0))) & (~_T_592 | _GEN_427 | ~(~_T_611 & (&lcam_ldq_idx_0))) & (~_T_540 | _GEN_424 | ~(~_T_559 & (&lcam_ldq_idx_0))) & (~_T_488 | _GEN_421 | ~(~_T_507 & (&lcam_ldq_idx_0))) & (~_T_436 | _GEN_418 | ~(~_T_455 & (&lcam_ldq_idx_0))) & (~_T_384 | _GEN_415 | ~(~_T_403 & (&lcam_ldq_idx_0))) & (~_T_332 | _GEN_412 | ~(~_T_351 & (&lcam_ldq_idx_0))) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & (&lcam_ldq_idx_0))) & s1_executing_loads_15; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] reg REG_15; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_46 = ldq_addr_15_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_47 = _block_addr_matches_T_45 == _block_addr_matches_T_46; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_15_0 = _block_addr_matches_T_47; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_61 = ldq_addr_15_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_62 = _dword_addr_matches_T_60 == _dword_addr_matches_T_61; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_63 = block_addr_matches_15_0 & _dword_addr_matches_T_62; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_15_0 = _dword_addr_matches_T_63; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_452 = ldq_ld_byte_mask_15 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_30; // @[lsu.scala:1197:46] assign _mask_match_T_30 = _GEN_452; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_30; // @[lsu.scala:1198:46] assign _mask_overlap_T_30 = _GEN_452; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_31 = _mask_match_T_30 == ldq_ld_byte_mask_15; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_15_0 = _mask_match_T_31; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_31 = |_mask_overlap_T_30; // @[lsu.scala:1198:{46,62}] wire mask_overlap_15_0 = _mask_overlap_T_31; // @[lsu.scala:321:49, :1198:62] wire _T_1070 = ldq_executed_15 | ldq_succeeded_15; // @[lsu.scala:223:36, :224:36, :1216:32] wire [15:0] _T_1046 = ldq_st_dep_mask_15 >> _GEN_393; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_60 = ldq_forward_stq_idx_15 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_61 = ldq_forward_stq_idx_15 < l_uop_15_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_62 = _forwarded_is_older_T_60 ^ _forwarded_is_older_T_61; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_63 = lcam_stq_idx_0 < l_uop_15_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_15 = _forwarded_is_older_T_62 ^ _forwarded_is_older_T_63; // @[util.scala:364:{58,72,78}] wire _GEN_453 = do_st_search_0 & ldq_valid_15 & ldq_addr_15_valid & _T_1070 & ~ldq_addr_is_virtual_15 & _T_1046[0] & dword_addr_matches_15_0 & mask_overlap_15_0 & (~ldq_forward_std_val_15 | ldq_forward_stq_idx_15 != lcam_stq_idx_0 & forwarded_is_older_15); // @[util.scala:364:72] wire _T_1060 = do_ld_search_0 & ldq_valid_15 & ldq_addr_15_valid & ~ldq_addr_is_virtual_15 & dword_addr_matches_15_0 & mask_overlap_15_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_15 = lcam_younger_load_mask_0[15]; // @[lsu.scala:321:49, :1237:58] wire _T_1079 = ldq_executed_15 & (ldq_succeeded_15 | ldq_will_succeed_15); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_454 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_395)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_395)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_395)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_395)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_395)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_395)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_395)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_395)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_395)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_395)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_395)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_395)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_395)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_395)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_395)) & s1_executing_loads_0; // @[lsu.scala:321:49, :1168:35, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_455 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_396)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_396)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_396)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_396)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_396)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_396)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_396)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_396)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_396)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_396)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_396)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_396)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_396)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_396)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_396)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_396)) & s1_executing_loads_1; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_456 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_397)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_397)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_397)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_397)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_397)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_397)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_397)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_397)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_397)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_397)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_397)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_397)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_397)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_397)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_397)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_397)) & s1_executing_loads_2; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_457 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_398)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_398)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_398)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_398)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_398)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_398)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_398)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_398)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_398)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_398)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_398)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_398)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_398)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_398)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_398)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_398)) & s1_executing_loads_3; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_458 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_399)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_399)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_399)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_399)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_399)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_399)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_399)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_399)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_399)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_399)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_399)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_399)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_399)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_399)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_399)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_399)) & s1_executing_loads_4; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_459 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_400)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_400)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_400)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_400)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_400)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_400)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_400)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_400)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_400)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_400)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_400)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_400)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_400)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_400)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_400)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_400)) & s1_executing_loads_5; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_460 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_401)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_401)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_401)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_401)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_401)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_401)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_401)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_401)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_401)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_401)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_401)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_401)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_401)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_401)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_401)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_401)) & s1_executing_loads_6; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_461 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_402)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_402)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_402)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_402)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_402)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_402)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_402)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_402)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_402)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_402)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_402)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_402)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_402)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_402)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_402)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_402)) & s1_executing_loads_7; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_462 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_403)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_403)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_403)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_403)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_403)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_403)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_403)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_403)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_403)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_403)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_403)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_403)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_403)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_403)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_403)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_403)) & s1_executing_loads_8; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_463 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_404)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_404)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_404)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_404)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_404)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_404)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_404)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_404)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_404)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_404)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_404)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_404)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_404)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_404)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_404)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_404)) & s1_executing_loads_9; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_464 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_405)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_405)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_405)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_405)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_405)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_405)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_405)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_405)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_405)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_405)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_405)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_405)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_405)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_405)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_405)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_405)) & s1_executing_loads_10; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_465 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_406)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_406)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_406)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_406)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_406)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_406)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_406)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_406)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_406)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_406)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_406)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_406)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_406)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_406)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_406)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_406)) & s1_executing_loads_11; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_466 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_407)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_407)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_407)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_407)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_407)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_407)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_407)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_407)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_407)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_407)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_407)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_407)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_407)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_407)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_407)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_407)) & s1_executing_loads_12; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_467 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_408)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_408)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_408)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_408)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_408)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_408)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_408)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_408)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_408)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_408)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_408)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_408)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_408)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_408)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_408)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_408)) & s1_executing_loads_13; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_468 = (~_T_1060 | searcher_is_older_15 | ~(~(&lcam_ldq_idx_0) & ~_T_1079 & _GEN_409)) & (~_T_1008 | _GEN_450 | ~(~_T_1027 & _GEN_409)) & (~_T_956 | _GEN_448 | ~(~_T_975 & _GEN_409)) & (~_T_904 | _GEN_445 | ~(~_T_923 & _GEN_409)) & (~_T_852 | _GEN_442 | ~(~_T_871 & _GEN_409)) & (~_T_800 | _GEN_439 | ~(~_T_819 & _GEN_409)) & (~_T_748 | _GEN_436 | ~(~_T_767 & _GEN_409)) & (~_T_696 | _GEN_433 | ~(~_T_715 & _GEN_409)) & (~_T_644 | _GEN_430 | ~(~_T_663 & _GEN_409)) & (~_T_592 | _GEN_427 | ~(~_T_611 & _GEN_409)) & (~_T_540 | _GEN_424 | ~(~_T_559 & _GEN_409)) & (~_T_488 | _GEN_421 | ~(~_T_507 & _GEN_409)) & (~_T_436 | _GEN_418 | ~(~_T_455 & _GEN_409)) & (~_T_384 | _GEN_415 | ~(~_T_403 & _GEN_409)) & (~_T_332 | _GEN_412 | ~(~_T_351 & _GEN_409)) & (~_T_280 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_299 & _GEN_409)) & s1_executing_loads_14; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] reg REG_16; // @[lsu.scala:1255:26] wire _GEN_469 = _T_1060 & ~searcher_is_older_15 & ~(&lcam_ldq_idx_0) & ~_T_1079 & REG_16 & ~fired_load_agen_0 | _T_1008 & ~_GEN_450 & ~_T_1027 & REG_15 & ~fired_load_agen_0 | _T_956 & ~_GEN_448 & ~_T_975 & REG_14 & ~fired_load_agen_0 | _T_904 & ~_GEN_445 & ~_T_923 & REG_13 & ~fired_load_agen_0 | _T_852 & ~_GEN_442 & ~_T_871 & REG_12 & ~fired_load_agen_0 | _T_800 & ~_GEN_439 & ~_T_819 & REG_11 & ~fired_load_agen_0 | _T_748 & ~_GEN_436 & ~_T_767 & REG_10 & ~fired_load_agen_0 | _T_696 & ~_GEN_433 & ~_T_715 & REG_9 & ~fired_load_agen_0 | _T_644 & ~_GEN_430 & ~_T_663 & REG_8 & ~fired_load_agen_0 | _T_592 & ~_GEN_427 & ~_T_611 & REG_7 & ~fired_load_agen_0 | _T_540 & ~_GEN_424 & ~_T_559 & REG_6 & ~fired_load_agen_0 | _T_488 & ~_GEN_421 & ~_T_507 & REG_5 & ~fired_load_agen_0 | _T_436 & ~_GEN_418 & ~_T_455 & REG_4 & ~fired_load_agen_0 | _T_384 & ~_GEN_415 & ~_T_403 & REG_3 & ~fired_load_agen_0 | _T_332 & ~_GEN_412 & ~_T_351 & REG_2 & ~fired_load_agen_0 | _T_280 & ~searcher_is_older & (|lcam_ldq_idx_0) & ~_T_299 & REG_1 & ~fired_load_agen_0 | io_dmem_s1_kill_0_REG; // @[lsu.scala:321:49, :893:{24,34}, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48, :1255:{26,61,64,85}, :1256:48] wire _GEN_470 = _T_1060 & ~searcher_is_older_15 & ~(&lcam_ldq_idx_0) & ~_T_1079 | _T_1008 & ~_GEN_450 & ~_T_1027 | _T_956 & ~_GEN_448 & ~_T_975 | _T_904 & ~_GEN_445 & ~_T_923 | _T_852 & ~_GEN_442 & ~_T_871 | _T_800 & ~_GEN_439 & ~_T_819 | _T_748 & ~_GEN_436 & ~_T_767 | _T_696 & ~_GEN_433 & ~_T_715 | _T_644 & ~_GEN_430 & ~_T_663 | _T_592 & ~_GEN_427 & ~_T_611 | _T_540 & ~_GEN_424 & ~_T_559 | _T_488 & ~_GEN_421 & ~_T_507 | _T_436 & ~_GEN_418 & ~_T_455 | _T_384 & ~_GEN_415 & ~_T_403 | _T_332 & ~_GEN_412 & ~_T_351 | _T_280 & ~searcher_is_older & (|lcam_ldq_idx_0) & ~_T_299; // @[lsu.scala:321:49, :893:24, :1159:30, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48, :1258:48] wire [36:0] _nack_dword_addr_matches_T = lcam_addr_0[39:3]; // @[lsu.scala:321:49, :1270:51] wire [36:0] _forward_dword_addr_matches_T = lcam_addr_0[39:3]; // @[lsu.scala:321:49, :1270:51, :1289:54] wire [36:0] _nack_dword_addr_matches_T_1 = io_dmem_nack_0_bits_addr_0[39:3]; // @[lsu.scala:211:7, :1270:89] wire nack_dword_addr_matches = _nack_dword_addr_matches_T == _nack_dword_addr_matches_T_1; // @[lsu.scala:1270:{51,57,89}] wire [7:0] nack_mask; // @[lsu.scala:1951:22] wire _nack_mask_mask_T = io_dmem_nack_0_bits_uop_mem_size_0 == 2'h0; // @[lsu.scala:211:7, :1953:26] wire [2:0] _nack_mask_mask_T_1 = io_dmem_nack_0_bits_addr_0[2:0]; // @[lsu.scala:211:7, :1953:55] wire [14:0] _nack_mask_mask_T_2 = 15'h1 << _nack_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _nack_mask_mask_T_3 = io_dmem_nack_0_bits_uop_mem_size_0 == 2'h1; // @[lsu.scala:211:7, :1954:26] wire [1:0] _nack_mask_mask_T_4 = io_dmem_nack_0_bits_addr_0[2:1]; // @[lsu.scala:211:7, :1954:56] wire [2:0] _nack_mask_mask_T_5 = {_nack_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _nack_mask_mask_T_6 = 15'h3 << _nack_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _nack_mask_mask_T_7 = io_dmem_nack_0_bits_uop_mem_size_0 == 2'h2; // @[lsu.scala:211:7, :1955:26] wire _nack_mask_mask_T_8 = io_dmem_nack_0_bits_addr_0[2]; // @[lsu.scala:211:7, :1955:46] wire [7:0] _nack_mask_mask_T_9 = _nack_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _nack_mask_mask_T_10 = &io_dmem_nack_0_bits_uop_mem_size_0; // @[lsu.scala:211:7, :1956:26] wire [7:0] _nack_mask_mask_T_12 = _nack_mask_mask_T_7 ? _nack_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _nack_mask_mask_T_13 = _nack_mask_mask_T_3 ? _nack_mask_mask_T_6 : {7'h0, _nack_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _nack_mask_mask_T_14 = _nack_mask_mask_T ? _nack_mask_mask_T_2 : _nack_mask_mask_T_13; // @[Mux.scala:126:16] assign nack_mask = _nack_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire [7:0] _nack_mask_overlap_T = nack_mask & lcam_mask_0; // @[lsu.scala:321:49, :1272:42, :1951:22] wire nack_mask_overlap = |_nack_mask_overlap_T; // @[lsu.scala:1272:{42,58}] wire _T_1096 = do_ld_search_0 & io_dmem_nack_0_valid_0 & io_dmem_nack_0_bits_uop_uses_ldq_0 & nack_dword_addr_matches & nack_mask_overlap & (io_dmem_nack_0_bits_uop_ldq_idx_0 < lcam_ldq_idx_0 ^ io_dmem_nack_0_bits_uop_ldq_idx_0 < ldq_head ^ _lcam_younger_load_mask_T); // @[util.scala:364:{52,58,64,72}, :372:11] wire _GEN_471 = _T_1096 & _GEN_395; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_472 = _T_1096 & _GEN_396; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_473 = _T_1096 & _GEN_397; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_474 = _T_1096 & _GEN_398; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_475 = _T_1096 & _GEN_399; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_476 = _T_1096 & _GEN_400; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_477 = _T_1096 & _GEN_401; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_478 = _T_1096 & _GEN_402; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_479 = _T_1096 & _GEN_403; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_480 = _T_1096 & _GEN_404; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_481 = _T_1096 & _GEN_405; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_482 = _T_1096 & _GEN_406; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_483 = _T_1096 & _GEN_407; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_484 = _T_1096 & _GEN_408; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_485 = _T_1096 & _GEN_409; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_486 = _T_1096 & (&lcam_ldq_idx_0); // @[lsu.scala:321:49, :1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] reg REG_17; // @[lsu.scala:1280:22] wire _GEN_487 = _T_1096 & REG_17 & ~fired_load_agen_0; // @[lsu.scala:321:49, :1235:37, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1280:{22,57,60,81}, :1281:30] wire [36:0] _forward_dword_addr_matches_T_1 = wb_ldst_forward_ld_addr_0[39:3]; // @[lsu.scala:1175:41, :1289:91] wire forward_dword_addr_matches = _forward_dword_addr_matches_T == _forward_dword_addr_matches_T_1; // @[lsu.scala:1289:{54,59,91}] wire [7:0] forward_mask; // @[lsu.scala:1951:22] wire _forward_mask_mask_T = wb_ldst_forward_e_0_uop_mem_size == 2'h0; // @[lsu.scala:321:49, :1953:26] wire [2:0] _forward_mask_mask_T_1 = wb_ldst_forward_ld_addr_0[2:0]; // @[lsu.scala:1175:41, :1953:55] wire [14:0] _forward_mask_mask_T_2 = 15'h1 << _forward_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _forward_mask_mask_T_3 = wb_ldst_forward_e_0_uop_mem_size == 2'h1; // @[lsu.scala:321:49, :1954:26] wire [1:0] _forward_mask_mask_T_4 = wb_ldst_forward_ld_addr_0[2:1]; // @[lsu.scala:1175:41, :1954:56] wire [2:0] _forward_mask_mask_T_5 = {_forward_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _forward_mask_mask_T_6 = 15'h3 << _forward_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _forward_mask_mask_T_7 = wb_ldst_forward_e_0_uop_mem_size == 2'h2; // @[lsu.scala:321:49, :1955:26] wire _forward_mask_mask_T_8 = wb_ldst_forward_ld_addr_0[2]; // @[lsu.scala:1175:41, :1955:46] wire _iresp_0_bits_data_shifted_T = wb_ldst_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _fresp_0_bits_data_shifted_T = wb_ldst_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _ldq_debug_wb_data_shifted_T = wb_ldst_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire [7:0] _forward_mask_mask_T_9 = _forward_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _forward_mask_mask_T_10 = &wb_ldst_forward_e_0_uop_mem_size; // @[lsu.scala:321:49, :1956:26] wire [7:0] _forward_mask_mask_T_12 = _forward_mask_mask_T_7 ? _forward_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _forward_mask_mask_T_13 = _forward_mask_mask_T_3 ? _forward_mask_mask_T_6 : {7'h0, _forward_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _forward_mask_mask_T_14 = _forward_mask_mask_T ? _forward_mask_mask_T_2 : _forward_mask_mask_T_13; // @[Mux.scala:126:16] assign forward_mask = _forward_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire [7:0] _forward_mask_overlap_T = forward_mask & lcam_mask_0; // @[lsu.scala:321:49, :1291:48, :1951:22] wire forward_mask_overlap = |_forward_mask_overlap_T; // @[lsu.scala:1291:{48,64}] wire _T_1112 = do_ld_search_0 & wb_ldst_forward_valid_0 & forward_dword_addr_matches & forward_mask_overlap & wb_ldst_forward_e_0_observed & (lcam_ldq_idx_0 < wb_ldst_forward_ldq_idx_0 ^ _lcam_younger_load_mask_T ^ wb_ldst_forward_ldq_idx_0 < ldq_head); // @[util.scala:364:{52,58,72,78}, :372:11] wire _GEN_488 = wb_ldst_forward_ldq_idx_0 == 4'h0; // @[lsu.scala:1174:41, :1298:53] wire _GEN_489 = wb_ldst_forward_ldq_idx_0 == 4'h1; // @[lsu.scala:1174:41, :1298:53] wire _GEN_490 = wb_ldst_forward_ldq_idx_0 == 4'h2; // @[lsu.scala:1174:41, :1298:53] wire _GEN_491 = wb_ldst_forward_ldq_idx_0 == 4'h3; // @[lsu.scala:1174:41, :1298:53] wire _GEN_492 = wb_ldst_forward_ldq_idx_0 == 4'h4; // @[lsu.scala:1174:41, :1298:53] wire _GEN_493 = wb_ldst_forward_ldq_idx_0 == 4'h5; // @[lsu.scala:1174:41, :1298:53] wire _GEN_494 = wb_ldst_forward_ldq_idx_0 == 4'h6; // @[lsu.scala:1174:41, :1298:53] wire _GEN_495 = wb_ldst_forward_ldq_idx_0 == 4'h7; // @[lsu.scala:1174:41, :1298:53] wire _GEN_496 = wb_ldst_forward_ldq_idx_0 == 4'h8; // @[lsu.scala:1174:41, :1298:53] wire _GEN_497 = wb_ldst_forward_ldq_idx_0 == 4'h9; // @[lsu.scala:1174:41, :1298:53] wire _GEN_498 = wb_ldst_forward_ldq_idx_0 == 4'hA; // @[lsu.scala:1174:41, :1298:53] wire _GEN_499 = wb_ldst_forward_ldq_idx_0 == 4'hB; // @[lsu.scala:1174:41, :1298:53] wire _GEN_500 = wb_ldst_forward_ldq_idx_0 == 4'hC; // @[lsu.scala:1174:41, :1298:53] wire _GEN_501 = wb_ldst_forward_ldq_idx_0 == 4'hD; // @[lsu.scala:1174:41, :1298:53] wire _GEN_502 = wb_ldst_forward_ldq_idx_0 == 4'hE; // @[lsu.scala:1174:41, :1298:53] wire _forwarded_is_older_T_64 = wb_ldst_forward_stq_idx_0 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_65 = wb_ldst_forward_stq_idx_0 < wb_ldst_forward_e_0_uop_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_66 = _forwarded_is_older_T_64 ^ _forwarded_is_older_T_65; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_67 = lcam_stq_idx_0 < wb_ldst_forward_e_0_uop_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_16 = _forwarded_is_older_T_66 ^ _forwarded_is_older_T_67; // @[util.scala:364:{58,72,78}] wire [15:0] _T_1118 = wb_ldst_forward_e_0_st_dep_mask >> _GEN_393; // @[lsu.scala:321:49, :1218:33, :1308:46] wire _T_1121 = do_st_search_0 & wb_ldst_forward_valid_0 & forward_dword_addr_matches & forward_mask_overlap & _T_1118[0] & forwarded_is_older_16; // @[util.scala:364:72] assign failed_load = _T_1121 | _T_1112 | _GEN_453 | (_T_998 ? _T_1002 | _GEN_447 | _GEN_444 : _GEN_447 | _GEN_444); // @[lsu.scala:394:59, :1178:29, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23, :1292:47, :1293:47, :1294:47, :1295:47, :1296:47, :1297:78, :1299:21, :1304:64, :1305:64, :1306:64, :1307:64, :1308:64, :1309:33, :1311:21] wire _addr_matches_0_0_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_1_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_2_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_3_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_4_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_5_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_6_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_7_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_8_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_9_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_10_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_11_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_12_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_13_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_14_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_15_T_1; // @[lsu.scala:1334:53] wire addr_matches_0_0; // @[lsu.scala:1316:29] wire addr_matches_0_1; // @[lsu.scala:1316:29] wire addr_matches_0_2; // @[lsu.scala:1316:29] wire addr_matches_0_3; // @[lsu.scala:1316:29] wire addr_matches_0_4; // @[lsu.scala:1316:29] wire addr_matches_0_5; // @[lsu.scala:1316:29] wire addr_matches_0_6; // @[lsu.scala:1316:29] wire addr_matches_0_7; // @[lsu.scala:1316:29] wire addr_matches_0_8; // @[lsu.scala:1316:29] wire addr_matches_0_9; // @[lsu.scala:1316:29] wire addr_matches_0_10; // @[lsu.scala:1316:29] wire addr_matches_0_11; // @[lsu.scala:1316:29] wire addr_matches_0_12; // @[lsu.scala:1316:29] wire addr_matches_0_13; // @[lsu.scala:1316:29] wire addr_matches_0_14; // @[lsu.scala:1316:29] wire addr_matches_0_15; // @[lsu.scala:1316:29] wire _forward_matches_0_0_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_1_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_2_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_3_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_4_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_5_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_6_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_7_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_8_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_9_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_10_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_11_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_12_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_13_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_14_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_15_T_2; // @[lsu.scala:1335:67] wire forward_matches_0_0; // @[lsu.scala:1317:29] wire forward_matches_0_1; // @[lsu.scala:1317:29] wire forward_matches_0_2; // @[lsu.scala:1317:29] wire forward_matches_0_3; // @[lsu.scala:1317:29] wire forward_matches_0_4; // @[lsu.scala:1317:29] wire forward_matches_0_5; // @[lsu.scala:1317:29] wire forward_matches_0_6; // @[lsu.scala:1317:29] wire forward_matches_0_7; // @[lsu.scala:1317:29] wire forward_matches_0_8; // @[lsu.scala:1317:29] wire forward_matches_0_9; // @[lsu.scala:1317:29] wire forward_matches_0_10; // @[lsu.scala:1317:29] wire forward_matches_0_11; // @[lsu.scala:1317:29] wire forward_matches_0_12; // @[lsu.scala:1317:29] wire forward_matches_0_13; // @[lsu.scala:1317:29] wire forward_matches_0_14; // @[lsu.scala:1317:29] wire forward_matches_0_15; // @[lsu.scala:1317:29] wire _prs2_matches_0_0_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_1_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_2_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_3_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_4_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_5_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_6_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_7_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_8_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_9_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_10_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_11_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_12_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_13_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_14_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_15_T_3; // @[lsu.scala:1338:58] wire prs2_matches_0_0; // @[lsu.scala:1318:29] wire prs2_matches_0_1; // @[lsu.scala:1318:29] wire prs2_matches_0_2; // @[lsu.scala:1318:29] wire prs2_matches_0_3; // @[lsu.scala:1318:29] wire prs2_matches_0_4; // @[lsu.scala:1318:29] wire prs2_matches_0_5; // @[lsu.scala:1318:29] wire prs2_matches_0_6; // @[lsu.scala:1318:29] wire prs2_matches_0_7; // @[lsu.scala:1318:29] wire prs2_matches_0_8; // @[lsu.scala:1318:29] wire prs2_matches_0_9; // @[lsu.scala:1318:29] wire prs2_matches_0_10; // @[lsu.scala:1318:29] wire prs2_matches_0_11; // @[lsu.scala:1318:29] wire prs2_matches_0_12; // @[lsu.scala:1318:29] wire prs2_matches_0_13; // @[lsu.scala:1318:29] wire prs2_matches_0_14; // @[lsu.scala:1318:29] wire prs2_matches_0_15; // @[lsu.scala:1318:29] wire [7:0] write_mask; // @[lsu.scala:1951:22] wire _write_mask_mask_T = s_uop_2_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_1 = stq_addr_0_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_2 = 15'h1 << _write_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_3 = s_uop_2_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_4 = stq_addr_0_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_5 = {_write_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_6 = 15'h3 << _write_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_7 = s_uop_2_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_8 = stq_addr_0_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_9 = _write_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_10 = &s_uop_2_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_12 = _write_mask_mask_T_7 ? _write_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_13 = _write_mask_mask_T_3 ? _write_mask_mask_T_6 : {7'h0, _write_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_14 = _write_mask_mask_T ? _write_mask_mask_T_2 : _write_mask_mask_T_13; // @[Mux.scala:126:16] assign write_mask = _write_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_64 = ~s_uop_2_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_65 = stq_addr_0_valid & _dword_addr_matches_T_64; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_66 = ~stq_addr_is_virtual_0; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_67 = _dword_addr_matches_T_65 & _dword_addr_matches_T_66; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_68 = stq_addr_0_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire [28:0] _dword_addr_matches_T_69 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_76 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_83 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_90 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_97 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_104 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_111 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_118 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_125 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_132 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_139 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_146 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_153 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_160 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_167 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_174 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire _dword_addr_matches_T_70 = _dword_addr_matches_T_68 == _dword_addr_matches_T_69; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_16 = _dword_addr_matches_T_67 & _dword_addr_matches_T_70; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union = lcam_mask_0 & write_mask; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_0_T = |mask_union; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_0_T_1 = _addr_matches_0_0_T & dword_addr_matches_16; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_0 = _addr_matches_0_0_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_0_T = addr_matches_0_0 & stq_data_0_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_0_T_1 = mask_union == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_0_T_2 = _forward_matches_0_0_T & _forward_matches_0_0_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_0 = _forward_matches_0_0_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_0_T = s_uop_2_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_0_T_1 = s_uop_2_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_0_T_2 = _prs2_matches_0_0_T & _prs2_matches_0_0_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_0_T_3 = _prs2_matches_0_0_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_0 = _prs2_matches_0_0_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_1; // @[lsu.scala:1951:22] wire _write_mask_mask_T_15 = s_uop_3_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_16 = stq_addr_1_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_17 = 15'h1 << _write_mask_mask_T_16; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_18 = s_uop_3_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_19 = stq_addr_1_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_20 = {_write_mask_mask_T_19, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_21 = 15'h3 << _write_mask_mask_T_20; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_22 = s_uop_3_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_23 = stq_addr_1_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_24 = _write_mask_mask_T_23 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_25 = &s_uop_3_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_27 = _write_mask_mask_T_22 ? _write_mask_mask_T_24 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_28 = _write_mask_mask_T_18 ? _write_mask_mask_T_21 : {7'h0, _write_mask_mask_T_27}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_29 = _write_mask_mask_T_15 ? _write_mask_mask_T_17 : _write_mask_mask_T_28; // @[Mux.scala:126:16] assign write_mask_1 = _write_mask_mask_T_29[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_71 = ~s_uop_3_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_72 = stq_addr_1_valid & _dword_addr_matches_T_71; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_73 = ~stq_addr_is_virtual_1; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_74 = _dword_addr_matches_T_72 & _dword_addr_matches_T_73; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_75 = stq_addr_1_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_77 = _dword_addr_matches_T_75 == _dword_addr_matches_T_76; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_17 = _dword_addr_matches_T_74 & _dword_addr_matches_T_77; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_1 = lcam_mask_0 & write_mask_1; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_1_T = |mask_union_1; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_1_T_1 = _addr_matches_0_1_T & dword_addr_matches_17; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_1 = _addr_matches_0_1_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_1_T = addr_matches_0_1 & stq_data_1_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_1_T_1 = mask_union_1 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_1_T_2 = _forward_matches_0_1_T & _forward_matches_0_1_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_1 = _forward_matches_0_1_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_1_T = s_uop_3_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_1_T_1 = s_uop_3_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_1_T_2 = _prs2_matches_0_1_T & _prs2_matches_0_1_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_1_T_3 = _prs2_matches_0_1_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_1 = _prs2_matches_0_1_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_2; // @[lsu.scala:1951:22] wire _write_mask_mask_T_30 = s_uop_4_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_31 = stq_addr_2_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_32 = 15'h1 << _write_mask_mask_T_31; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_33 = s_uop_4_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_34 = stq_addr_2_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_35 = {_write_mask_mask_T_34, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_36 = 15'h3 << _write_mask_mask_T_35; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_37 = s_uop_4_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_38 = stq_addr_2_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_39 = _write_mask_mask_T_38 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_40 = &s_uop_4_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_42 = _write_mask_mask_T_37 ? _write_mask_mask_T_39 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_43 = _write_mask_mask_T_33 ? _write_mask_mask_T_36 : {7'h0, _write_mask_mask_T_42}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_44 = _write_mask_mask_T_30 ? _write_mask_mask_T_32 : _write_mask_mask_T_43; // @[Mux.scala:126:16] assign write_mask_2 = _write_mask_mask_T_44[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_78 = ~s_uop_4_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_79 = stq_addr_2_valid & _dword_addr_matches_T_78; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_80 = ~stq_addr_is_virtual_2; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_81 = _dword_addr_matches_T_79 & _dword_addr_matches_T_80; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_82 = stq_addr_2_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_84 = _dword_addr_matches_T_82 == _dword_addr_matches_T_83; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_18 = _dword_addr_matches_T_81 & _dword_addr_matches_T_84; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_2 = lcam_mask_0 & write_mask_2; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_2_T = |mask_union_2; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_2_T_1 = _addr_matches_0_2_T & dword_addr_matches_18; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_2 = _addr_matches_0_2_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_2_T = addr_matches_0_2 & stq_data_2_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_2_T_1 = mask_union_2 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_2_T_2 = _forward_matches_0_2_T & _forward_matches_0_2_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_2 = _forward_matches_0_2_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_2_T = s_uop_4_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_2_T_1 = s_uop_4_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_2_T_2 = _prs2_matches_0_2_T & _prs2_matches_0_2_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_2_T_3 = _prs2_matches_0_2_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_2 = _prs2_matches_0_2_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_3; // @[lsu.scala:1951:22] wire _write_mask_mask_T_45 = s_uop_5_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_46 = stq_addr_3_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_47 = 15'h1 << _write_mask_mask_T_46; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_48 = s_uop_5_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_49 = stq_addr_3_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_50 = {_write_mask_mask_T_49, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_51 = 15'h3 << _write_mask_mask_T_50; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_52 = s_uop_5_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_53 = stq_addr_3_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_54 = _write_mask_mask_T_53 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_55 = &s_uop_5_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_57 = _write_mask_mask_T_52 ? _write_mask_mask_T_54 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_58 = _write_mask_mask_T_48 ? _write_mask_mask_T_51 : {7'h0, _write_mask_mask_T_57}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_59 = _write_mask_mask_T_45 ? _write_mask_mask_T_47 : _write_mask_mask_T_58; // @[Mux.scala:126:16] assign write_mask_3 = _write_mask_mask_T_59[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_85 = ~s_uop_5_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_86 = stq_addr_3_valid & _dword_addr_matches_T_85; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_87 = ~stq_addr_is_virtual_3; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_88 = _dword_addr_matches_T_86 & _dword_addr_matches_T_87; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_89 = stq_addr_3_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_91 = _dword_addr_matches_T_89 == _dword_addr_matches_T_90; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_19 = _dword_addr_matches_T_88 & _dword_addr_matches_T_91; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_3 = lcam_mask_0 & write_mask_3; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_3_T = |mask_union_3; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_3_T_1 = _addr_matches_0_3_T & dword_addr_matches_19; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_3 = _addr_matches_0_3_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_3_T = addr_matches_0_3 & stq_data_3_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_3_T_1 = mask_union_3 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_3_T_2 = _forward_matches_0_3_T & _forward_matches_0_3_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_3 = _forward_matches_0_3_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_3_T = s_uop_5_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_3_T_1 = s_uop_5_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_3_T_2 = _prs2_matches_0_3_T & _prs2_matches_0_3_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_3_T_3 = _prs2_matches_0_3_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_3 = _prs2_matches_0_3_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_4; // @[lsu.scala:1951:22] wire _write_mask_mask_T_60 = s_uop_6_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_61 = stq_addr_4_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_62 = 15'h1 << _write_mask_mask_T_61; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_63 = s_uop_6_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_64 = stq_addr_4_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_65 = {_write_mask_mask_T_64, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_66 = 15'h3 << _write_mask_mask_T_65; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_67 = s_uop_6_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_68 = stq_addr_4_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_69 = _write_mask_mask_T_68 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_70 = &s_uop_6_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_72 = _write_mask_mask_T_67 ? _write_mask_mask_T_69 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_73 = _write_mask_mask_T_63 ? _write_mask_mask_T_66 : {7'h0, _write_mask_mask_T_72}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_74 = _write_mask_mask_T_60 ? _write_mask_mask_T_62 : _write_mask_mask_T_73; // @[Mux.scala:126:16] assign write_mask_4 = _write_mask_mask_T_74[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_92 = ~s_uop_6_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_93 = stq_addr_4_valid & _dword_addr_matches_T_92; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_94 = ~stq_addr_is_virtual_4; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_95 = _dword_addr_matches_T_93 & _dword_addr_matches_T_94; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_96 = stq_addr_4_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_98 = _dword_addr_matches_T_96 == _dword_addr_matches_T_97; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_20 = _dword_addr_matches_T_95 & _dword_addr_matches_T_98; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_4 = lcam_mask_0 & write_mask_4; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_4_T = |mask_union_4; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_4_T_1 = _addr_matches_0_4_T & dword_addr_matches_20; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_4 = _addr_matches_0_4_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_4_T = addr_matches_0_4 & stq_data_4_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_4_T_1 = mask_union_4 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_4_T_2 = _forward_matches_0_4_T & _forward_matches_0_4_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_4 = _forward_matches_0_4_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_4_T = s_uop_6_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_4_T_1 = s_uop_6_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_4_T_2 = _prs2_matches_0_4_T & _prs2_matches_0_4_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_4_T_3 = _prs2_matches_0_4_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_4 = _prs2_matches_0_4_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_5; // @[lsu.scala:1951:22] wire _write_mask_mask_T_75 = s_uop_7_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_76 = stq_addr_5_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_77 = 15'h1 << _write_mask_mask_T_76; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_78 = s_uop_7_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_79 = stq_addr_5_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_80 = {_write_mask_mask_T_79, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_81 = 15'h3 << _write_mask_mask_T_80; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_82 = s_uop_7_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_83 = stq_addr_5_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_84 = _write_mask_mask_T_83 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_85 = &s_uop_7_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_87 = _write_mask_mask_T_82 ? _write_mask_mask_T_84 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_88 = _write_mask_mask_T_78 ? _write_mask_mask_T_81 : {7'h0, _write_mask_mask_T_87}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_89 = _write_mask_mask_T_75 ? _write_mask_mask_T_77 : _write_mask_mask_T_88; // @[Mux.scala:126:16] assign write_mask_5 = _write_mask_mask_T_89[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_99 = ~s_uop_7_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_100 = stq_addr_5_valid & _dword_addr_matches_T_99; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_101 = ~stq_addr_is_virtual_5; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_102 = _dword_addr_matches_T_100 & _dword_addr_matches_T_101; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_103 = stq_addr_5_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_105 = _dword_addr_matches_T_103 == _dword_addr_matches_T_104; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_21 = _dword_addr_matches_T_102 & _dword_addr_matches_T_105; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_5 = lcam_mask_0 & write_mask_5; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_5_T = |mask_union_5; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_5_T_1 = _addr_matches_0_5_T & dword_addr_matches_21; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_5 = _addr_matches_0_5_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_5_T = addr_matches_0_5 & stq_data_5_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_5_T_1 = mask_union_5 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_5_T_2 = _forward_matches_0_5_T & _forward_matches_0_5_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_5 = _forward_matches_0_5_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_5_T = s_uop_7_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_5_T_1 = s_uop_7_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_5_T_2 = _prs2_matches_0_5_T & _prs2_matches_0_5_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_5_T_3 = _prs2_matches_0_5_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_5 = _prs2_matches_0_5_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_6; // @[lsu.scala:1951:22] wire _write_mask_mask_T_90 = s_uop_8_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_91 = stq_addr_6_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_92 = 15'h1 << _write_mask_mask_T_91; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_93 = s_uop_8_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_94 = stq_addr_6_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_95 = {_write_mask_mask_T_94, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_96 = 15'h3 << _write_mask_mask_T_95; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_97 = s_uop_8_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_98 = stq_addr_6_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_99 = _write_mask_mask_T_98 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_100 = &s_uop_8_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_102 = _write_mask_mask_T_97 ? _write_mask_mask_T_99 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_103 = _write_mask_mask_T_93 ? _write_mask_mask_T_96 : {7'h0, _write_mask_mask_T_102}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_104 = _write_mask_mask_T_90 ? _write_mask_mask_T_92 : _write_mask_mask_T_103; // @[Mux.scala:126:16] assign write_mask_6 = _write_mask_mask_T_104[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_106 = ~s_uop_8_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_107 = stq_addr_6_valid & _dword_addr_matches_T_106; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_108 = ~stq_addr_is_virtual_6; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_109 = _dword_addr_matches_T_107 & _dword_addr_matches_T_108; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_110 = stq_addr_6_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_112 = _dword_addr_matches_T_110 == _dword_addr_matches_T_111; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_22 = _dword_addr_matches_T_109 & _dword_addr_matches_T_112; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_6 = lcam_mask_0 & write_mask_6; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_6_T = |mask_union_6; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_6_T_1 = _addr_matches_0_6_T & dword_addr_matches_22; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_6 = _addr_matches_0_6_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_6_T = addr_matches_0_6 & stq_data_6_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_6_T_1 = mask_union_6 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_6_T_2 = _forward_matches_0_6_T & _forward_matches_0_6_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_6 = _forward_matches_0_6_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_6_T = s_uop_8_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_6_T_1 = s_uop_8_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_6_T_2 = _prs2_matches_0_6_T & _prs2_matches_0_6_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_6_T_3 = _prs2_matches_0_6_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_6 = _prs2_matches_0_6_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_7; // @[lsu.scala:1951:22] wire _write_mask_mask_T_105 = s_uop_9_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_106 = stq_addr_7_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_107 = 15'h1 << _write_mask_mask_T_106; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_108 = s_uop_9_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_109 = stq_addr_7_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_110 = {_write_mask_mask_T_109, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_111 = 15'h3 << _write_mask_mask_T_110; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_112 = s_uop_9_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_113 = stq_addr_7_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_114 = _write_mask_mask_T_113 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_115 = &s_uop_9_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_117 = _write_mask_mask_T_112 ? _write_mask_mask_T_114 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_118 = _write_mask_mask_T_108 ? _write_mask_mask_T_111 : {7'h0, _write_mask_mask_T_117}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_119 = _write_mask_mask_T_105 ? _write_mask_mask_T_107 : _write_mask_mask_T_118; // @[Mux.scala:126:16] assign write_mask_7 = _write_mask_mask_T_119[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_113 = ~s_uop_9_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_114 = stq_addr_7_valid & _dword_addr_matches_T_113; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_115 = ~stq_addr_is_virtual_7; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_116 = _dword_addr_matches_T_114 & _dword_addr_matches_T_115; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_117 = stq_addr_7_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_119 = _dword_addr_matches_T_117 == _dword_addr_matches_T_118; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_23 = _dword_addr_matches_T_116 & _dword_addr_matches_T_119; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_7 = lcam_mask_0 & write_mask_7; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_7_T = |mask_union_7; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_7_T_1 = _addr_matches_0_7_T & dword_addr_matches_23; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_7 = _addr_matches_0_7_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_7_T = addr_matches_0_7 & stq_data_7_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_7_T_1 = mask_union_7 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_7_T_2 = _forward_matches_0_7_T & _forward_matches_0_7_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_7 = _forward_matches_0_7_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_7_T = s_uop_9_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_7_T_1 = s_uop_9_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_7_T_2 = _prs2_matches_0_7_T & _prs2_matches_0_7_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_7_T_3 = _prs2_matches_0_7_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_7 = _prs2_matches_0_7_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_8; // @[lsu.scala:1951:22] wire _write_mask_mask_T_120 = s_uop_10_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_121 = stq_addr_8_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_122 = 15'h1 << _write_mask_mask_T_121; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_123 = s_uop_10_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_124 = stq_addr_8_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_125 = {_write_mask_mask_T_124, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_126 = 15'h3 << _write_mask_mask_T_125; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_127 = s_uop_10_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_128 = stq_addr_8_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_129 = _write_mask_mask_T_128 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_130 = &s_uop_10_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_132 = _write_mask_mask_T_127 ? _write_mask_mask_T_129 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_133 = _write_mask_mask_T_123 ? _write_mask_mask_T_126 : {7'h0, _write_mask_mask_T_132}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_134 = _write_mask_mask_T_120 ? _write_mask_mask_T_122 : _write_mask_mask_T_133; // @[Mux.scala:126:16] assign write_mask_8 = _write_mask_mask_T_134[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_120 = ~s_uop_10_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_121 = stq_addr_8_valid & _dword_addr_matches_T_120; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_122 = ~stq_addr_is_virtual_8; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_123 = _dword_addr_matches_T_121 & _dword_addr_matches_T_122; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_124 = stq_addr_8_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_126 = _dword_addr_matches_T_124 == _dword_addr_matches_T_125; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_24 = _dword_addr_matches_T_123 & _dword_addr_matches_T_126; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_8 = lcam_mask_0 & write_mask_8; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_8_T = |mask_union_8; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_8_T_1 = _addr_matches_0_8_T & dword_addr_matches_24; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_8 = _addr_matches_0_8_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_8_T = addr_matches_0_8 & stq_data_8_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_8_T_1 = mask_union_8 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_8_T_2 = _forward_matches_0_8_T & _forward_matches_0_8_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_8 = _forward_matches_0_8_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_8_T = s_uop_10_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_8_T_1 = s_uop_10_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_8_T_2 = _prs2_matches_0_8_T & _prs2_matches_0_8_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_8_T_3 = _prs2_matches_0_8_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_8 = _prs2_matches_0_8_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_9; // @[lsu.scala:1951:22] wire _write_mask_mask_T_135 = s_uop_11_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_136 = stq_addr_9_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_137 = 15'h1 << _write_mask_mask_T_136; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_138 = s_uop_11_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_139 = stq_addr_9_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_140 = {_write_mask_mask_T_139, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_141 = 15'h3 << _write_mask_mask_T_140; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_142 = s_uop_11_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_143 = stq_addr_9_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_144 = _write_mask_mask_T_143 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_145 = &s_uop_11_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_147 = _write_mask_mask_T_142 ? _write_mask_mask_T_144 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_148 = _write_mask_mask_T_138 ? _write_mask_mask_T_141 : {7'h0, _write_mask_mask_T_147}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_149 = _write_mask_mask_T_135 ? _write_mask_mask_T_137 : _write_mask_mask_T_148; // @[Mux.scala:126:16] assign write_mask_9 = _write_mask_mask_T_149[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_127 = ~s_uop_11_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_128 = stq_addr_9_valid & _dword_addr_matches_T_127; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_129 = ~stq_addr_is_virtual_9; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_130 = _dword_addr_matches_T_128 & _dword_addr_matches_T_129; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_131 = stq_addr_9_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_133 = _dword_addr_matches_T_131 == _dword_addr_matches_T_132; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_25 = _dword_addr_matches_T_130 & _dword_addr_matches_T_133; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_9 = lcam_mask_0 & write_mask_9; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_9_T = |mask_union_9; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_9_T_1 = _addr_matches_0_9_T & dword_addr_matches_25; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_9 = _addr_matches_0_9_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_9_T = addr_matches_0_9 & stq_data_9_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_9_T_1 = mask_union_9 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_9_T_2 = _forward_matches_0_9_T & _forward_matches_0_9_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_9 = _forward_matches_0_9_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_9_T = s_uop_11_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_9_T_1 = s_uop_11_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_9_T_2 = _prs2_matches_0_9_T & _prs2_matches_0_9_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_9_T_3 = _prs2_matches_0_9_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_9 = _prs2_matches_0_9_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_10; // @[lsu.scala:1951:22] wire _write_mask_mask_T_150 = s_uop_12_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_151 = stq_addr_10_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_152 = 15'h1 << _write_mask_mask_T_151; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_153 = s_uop_12_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_154 = stq_addr_10_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_155 = {_write_mask_mask_T_154, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_156 = 15'h3 << _write_mask_mask_T_155; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_157 = s_uop_12_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_158 = stq_addr_10_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_159 = _write_mask_mask_T_158 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_160 = &s_uop_12_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_162 = _write_mask_mask_T_157 ? _write_mask_mask_T_159 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_163 = _write_mask_mask_T_153 ? _write_mask_mask_T_156 : {7'h0, _write_mask_mask_T_162}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_164 = _write_mask_mask_T_150 ? _write_mask_mask_T_152 : _write_mask_mask_T_163; // @[Mux.scala:126:16] assign write_mask_10 = _write_mask_mask_T_164[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_134 = ~s_uop_12_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_135 = stq_addr_10_valid & _dword_addr_matches_T_134; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_136 = ~stq_addr_is_virtual_10; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_137 = _dword_addr_matches_T_135 & _dword_addr_matches_T_136; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_138 = stq_addr_10_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_140 = _dword_addr_matches_T_138 == _dword_addr_matches_T_139; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_26 = _dword_addr_matches_T_137 & _dword_addr_matches_T_140; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_10 = lcam_mask_0 & write_mask_10; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_10_T = |mask_union_10; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_10_T_1 = _addr_matches_0_10_T & dword_addr_matches_26; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_10 = _addr_matches_0_10_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_10_T = addr_matches_0_10 & stq_data_10_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_10_T_1 = mask_union_10 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_10_T_2 = _forward_matches_0_10_T & _forward_matches_0_10_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_10 = _forward_matches_0_10_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_10_T = s_uop_12_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_10_T_1 = s_uop_12_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_10_T_2 = _prs2_matches_0_10_T & _prs2_matches_0_10_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_10_T_3 = _prs2_matches_0_10_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_10 = _prs2_matches_0_10_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_11; // @[lsu.scala:1951:22] wire _write_mask_mask_T_165 = s_uop_13_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_166 = stq_addr_11_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_167 = 15'h1 << _write_mask_mask_T_166; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_168 = s_uop_13_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_169 = stq_addr_11_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_170 = {_write_mask_mask_T_169, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_171 = 15'h3 << _write_mask_mask_T_170; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_172 = s_uop_13_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_173 = stq_addr_11_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_174 = _write_mask_mask_T_173 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_175 = &s_uop_13_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_177 = _write_mask_mask_T_172 ? _write_mask_mask_T_174 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_178 = _write_mask_mask_T_168 ? _write_mask_mask_T_171 : {7'h0, _write_mask_mask_T_177}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_179 = _write_mask_mask_T_165 ? _write_mask_mask_T_167 : _write_mask_mask_T_178; // @[Mux.scala:126:16] assign write_mask_11 = _write_mask_mask_T_179[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_141 = ~s_uop_13_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_142 = stq_addr_11_valid & _dword_addr_matches_T_141; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_143 = ~stq_addr_is_virtual_11; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_144 = _dword_addr_matches_T_142 & _dword_addr_matches_T_143; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_145 = stq_addr_11_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_147 = _dword_addr_matches_T_145 == _dword_addr_matches_T_146; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_27 = _dword_addr_matches_T_144 & _dword_addr_matches_T_147; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_11 = lcam_mask_0 & write_mask_11; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_11_T = |mask_union_11; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_11_T_1 = _addr_matches_0_11_T & dword_addr_matches_27; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_11 = _addr_matches_0_11_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_11_T = addr_matches_0_11 & stq_data_11_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_11_T_1 = mask_union_11 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_11_T_2 = _forward_matches_0_11_T & _forward_matches_0_11_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_11 = _forward_matches_0_11_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_11_T = s_uop_13_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_11_T_1 = s_uop_13_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_11_T_2 = _prs2_matches_0_11_T & _prs2_matches_0_11_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_11_T_3 = _prs2_matches_0_11_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_11 = _prs2_matches_0_11_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_12; // @[lsu.scala:1951:22] wire _write_mask_mask_T_180 = s_uop_14_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_181 = stq_addr_12_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_182 = 15'h1 << _write_mask_mask_T_181; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_183 = s_uop_14_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_184 = stq_addr_12_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_185 = {_write_mask_mask_T_184, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_186 = 15'h3 << _write_mask_mask_T_185; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_187 = s_uop_14_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_188 = stq_addr_12_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_189 = _write_mask_mask_T_188 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_190 = &s_uop_14_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_192 = _write_mask_mask_T_187 ? _write_mask_mask_T_189 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_193 = _write_mask_mask_T_183 ? _write_mask_mask_T_186 : {7'h0, _write_mask_mask_T_192}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_194 = _write_mask_mask_T_180 ? _write_mask_mask_T_182 : _write_mask_mask_T_193; // @[Mux.scala:126:16] assign write_mask_12 = _write_mask_mask_T_194[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_148 = ~s_uop_14_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_149 = stq_addr_12_valid & _dword_addr_matches_T_148; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_150 = ~stq_addr_is_virtual_12; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_151 = _dword_addr_matches_T_149 & _dword_addr_matches_T_150; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_152 = stq_addr_12_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_154 = _dword_addr_matches_T_152 == _dword_addr_matches_T_153; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_28 = _dword_addr_matches_T_151 & _dword_addr_matches_T_154; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_12 = lcam_mask_0 & write_mask_12; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_12_T = |mask_union_12; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_12_T_1 = _addr_matches_0_12_T & dword_addr_matches_28; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_12 = _addr_matches_0_12_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_12_T = addr_matches_0_12 & stq_data_12_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_12_T_1 = mask_union_12 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_12_T_2 = _forward_matches_0_12_T & _forward_matches_0_12_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_12 = _forward_matches_0_12_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_12_T = s_uop_14_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_12_T_1 = s_uop_14_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_12_T_2 = _prs2_matches_0_12_T & _prs2_matches_0_12_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_12_T_3 = _prs2_matches_0_12_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_12 = _prs2_matches_0_12_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_13; // @[lsu.scala:1951:22] wire _write_mask_mask_T_195 = s_uop_15_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_196 = stq_addr_13_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_197 = 15'h1 << _write_mask_mask_T_196; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_198 = s_uop_15_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_199 = stq_addr_13_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_200 = {_write_mask_mask_T_199, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_201 = 15'h3 << _write_mask_mask_T_200; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_202 = s_uop_15_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_203 = stq_addr_13_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_204 = _write_mask_mask_T_203 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_205 = &s_uop_15_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_207 = _write_mask_mask_T_202 ? _write_mask_mask_T_204 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_208 = _write_mask_mask_T_198 ? _write_mask_mask_T_201 : {7'h0, _write_mask_mask_T_207}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_209 = _write_mask_mask_T_195 ? _write_mask_mask_T_197 : _write_mask_mask_T_208; // @[Mux.scala:126:16] assign write_mask_13 = _write_mask_mask_T_209[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_155 = ~s_uop_15_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_156 = stq_addr_13_valid & _dword_addr_matches_T_155; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_157 = ~stq_addr_is_virtual_13; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_158 = _dword_addr_matches_T_156 & _dword_addr_matches_T_157; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_159 = stq_addr_13_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_161 = _dword_addr_matches_T_159 == _dword_addr_matches_T_160; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_29 = _dword_addr_matches_T_158 & _dword_addr_matches_T_161; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_13 = lcam_mask_0 & write_mask_13; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_13_T = |mask_union_13; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_13_T_1 = _addr_matches_0_13_T & dword_addr_matches_29; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_13 = _addr_matches_0_13_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_13_T = addr_matches_0_13 & stq_data_13_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_13_T_1 = mask_union_13 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_13_T_2 = _forward_matches_0_13_T & _forward_matches_0_13_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_13 = _forward_matches_0_13_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_13_T = s_uop_15_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_13_T_1 = s_uop_15_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_13_T_2 = _prs2_matches_0_13_T & _prs2_matches_0_13_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_13_T_3 = _prs2_matches_0_13_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_13 = _prs2_matches_0_13_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_14; // @[lsu.scala:1951:22] wire _write_mask_mask_T_210 = s_uop_16_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_211 = stq_addr_14_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_212 = 15'h1 << _write_mask_mask_T_211; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_213 = s_uop_16_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_214 = stq_addr_14_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_215 = {_write_mask_mask_T_214, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_216 = 15'h3 << _write_mask_mask_T_215; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_217 = s_uop_16_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_218 = stq_addr_14_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_219 = _write_mask_mask_T_218 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_220 = &s_uop_16_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_222 = _write_mask_mask_T_217 ? _write_mask_mask_T_219 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_223 = _write_mask_mask_T_213 ? _write_mask_mask_T_216 : {7'h0, _write_mask_mask_T_222}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_224 = _write_mask_mask_T_210 ? _write_mask_mask_T_212 : _write_mask_mask_T_223; // @[Mux.scala:126:16] assign write_mask_14 = _write_mask_mask_T_224[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_162 = ~s_uop_16_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_163 = stq_addr_14_valid & _dword_addr_matches_T_162; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_164 = ~stq_addr_is_virtual_14; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_165 = _dword_addr_matches_T_163 & _dword_addr_matches_T_164; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_166 = stq_addr_14_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_168 = _dword_addr_matches_T_166 == _dword_addr_matches_T_167; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_30 = _dword_addr_matches_T_165 & _dword_addr_matches_T_168; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_14 = lcam_mask_0 & write_mask_14; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_14_T = |mask_union_14; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_14_T_1 = _addr_matches_0_14_T & dword_addr_matches_30; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_14 = _addr_matches_0_14_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_14_T = addr_matches_0_14 & stq_data_14_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_14_T_1 = mask_union_14 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_14_T_2 = _forward_matches_0_14_T & _forward_matches_0_14_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_14 = _forward_matches_0_14_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_14_T = s_uop_16_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_14_T_1 = s_uop_16_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_14_T_2 = _prs2_matches_0_14_T & _prs2_matches_0_14_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_14_T_3 = _prs2_matches_0_14_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_14 = _prs2_matches_0_14_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_15; // @[lsu.scala:1951:22] wire _write_mask_mask_T_225 = s_uop_17_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_226 = stq_addr_15_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_227 = 15'h1 << _write_mask_mask_T_226; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_228 = s_uop_17_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_229 = stq_addr_15_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_230 = {_write_mask_mask_T_229, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_231 = 15'h3 << _write_mask_mask_T_230; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_232 = s_uop_17_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_233 = stq_addr_15_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_234 = _write_mask_mask_T_233 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_235 = &s_uop_17_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_237 = _write_mask_mask_T_232 ? _write_mask_mask_T_234 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_238 = _write_mask_mask_T_228 ? _write_mask_mask_T_231 : {7'h0, _write_mask_mask_T_237}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_239 = _write_mask_mask_T_225 ? _write_mask_mask_T_227 : _write_mask_mask_T_238; // @[Mux.scala:126:16] assign write_mask_15 = _write_mask_mask_T_239[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_169 = ~s_uop_17_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_170 = stq_addr_15_valid & _dword_addr_matches_T_169; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_171 = ~stq_addr_is_virtual_15; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_172 = _dword_addr_matches_T_170 & _dword_addr_matches_T_171; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_173 = stq_addr_15_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_175 = _dword_addr_matches_T_173 == _dword_addr_matches_T_174; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_31 = _dword_addr_matches_T_172 & _dword_addr_matches_T_175; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_15 = lcam_mask_0 & write_mask_15; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_15_T = |mask_union_15; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_15_T_1 = _addr_matches_0_15_T & dword_addr_matches_31; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_15 = _addr_matches_0_15_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_15_T = addr_matches_0_15 & stq_data_15_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_15_T_1 = mask_union_15 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_15_T_2 = _forward_matches_0_15_T & _forward_matches_0_15_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_15 = _forward_matches_0_15_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_15_T = s_uop_17_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_15_T_1 = s_uop_17_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_15_T_2 = _prs2_matches_0_15_T & _prs2_matches_0_15_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_15_T_3 = _prs2_matches_0_15_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_15 = _prs2_matches_0_15_T_3; // @[lsu.scala:1318:29, :1338:58] wire [3:0] fast_stq_valids_lo_lo = {fast_stq_valids_lo_lo_hi, fast_stq_valids_lo_lo_lo}; // @[lsu.scala:1342:35] wire [3:0] fast_stq_valids_lo_hi = {fast_stq_valids_lo_hi_hi, fast_stq_valids_lo_hi_lo}; // @[lsu.scala:1342:35] wire [7:0] fast_stq_valids_lo = {fast_stq_valids_lo_hi, fast_stq_valids_lo_lo}; // @[lsu.scala:1342:35] wire [3:0] fast_stq_valids_hi_lo = {fast_stq_valids_hi_lo_hi, fast_stq_valids_hi_lo_lo}; // @[lsu.scala:1342:35] wire [3:0] fast_stq_valids_hi_hi = {fast_stq_valids_hi_hi_hi, fast_stq_valids_hi_hi_lo}; // @[lsu.scala:1342:35] wire [7:0] fast_stq_valids_hi = {fast_stq_valids_hi_hi, fast_stq_valids_hi_lo}; // @[lsu.scala:1342:35] wire [15:0] fast_stq_valids = {fast_stq_valids_hi, fast_stq_valids_lo}; // @[lsu.scala:1342:35] wire [1:0] ldst_addr_matches_0_lo_lo_lo = {addr_matches_0_1, addr_matches_0_0}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_lo_lo_hi = {addr_matches_0_3, addr_matches_0_2}; // @[lsu.scala:1316:29, :1344:49] wire [3:0] ldst_addr_matches_0_lo_lo = {ldst_addr_matches_0_lo_lo_hi, ldst_addr_matches_0_lo_lo_lo}; // @[lsu.scala:1344:49] wire [1:0] ldst_addr_matches_0_lo_hi_lo = {addr_matches_0_5, addr_matches_0_4}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_lo_hi_hi = {addr_matches_0_7, addr_matches_0_6}; // @[lsu.scala:1316:29, :1344:49] wire [3:0] ldst_addr_matches_0_lo_hi = {ldst_addr_matches_0_lo_hi_hi, ldst_addr_matches_0_lo_hi_lo}; // @[lsu.scala:1344:49] wire [7:0] ldst_addr_matches_0_lo = {ldst_addr_matches_0_lo_hi, ldst_addr_matches_0_lo_lo}; // @[lsu.scala:1344:49] wire [1:0] ldst_addr_matches_0_hi_lo_lo = {addr_matches_0_9, addr_matches_0_8}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_hi_lo_hi = {addr_matches_0_11, addr_matches_0_10}; // @[lsu.scala:1316:29, :1344:49] wire [3:0] ldst_addr_matches_0_hi_lo = {ldst_addr_matches_0_hi_lo_hi, ldst_addr_matches_0_hi_lo_lo}; // @[lsu.scala:1344:49] wire [1:0] ldst_addr_matches_0_hi_hi_lo = {addr_matches_0_13, addr_matches_0_12}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_hi_hi_hi = {addr_matches_0_15, addr_matches_0_14}; // @[lsu.scala:1316:29, :1344:49] wire [3:0] ldst_addr_matches_0_hi_hi = {ldst_addr_matches_0_hi_hi_hi, ldst_addr_matches_0_hi_hi_lo}; // @[lsu.scala:1344:49] wire [7:0] ldst_addr_matches_0_hi = {ldst_addr_matches_0_hi_hi, ldst_addr_matches_0_hi_lo}; // @[lsu.scala:1344:49] wire [15:0] _ldst_addr_matches_0_T = {ldst_addr_matches_0_hi, ldst_addr_matches_0_lo}; // @[lsu.scala:1344:49] wire [15:0] _ldst_addr_matches_0_T_1 = _ldst_addr_matches_0_T & lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1344:{49,56}] assign _ldst_addr_matches_0_T_2 = _ldst_addr_matches_0_T_1 & fast_stq_valids; // @[lsu.scala:1342:35, :1344:{56,79}] assign ldst_addr_matches_0 = _ldst_addr_matches_0_T_2; // @[lsu.scala:1162:34, :1344:79] wire [1:0] ldst_forward_matches_0_lo_lo_lo = {forward_matches_0_1, forward_matches_0_0}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_lo_lo_hi = {forward_matches_0_3, forward_matches_0_2}; // @[lsu.scala:1317:29, :1345:52] wire [3:0] ldst_forward_matches_0_lo_lo = {ldst_forward_matches_0_lo_lo_hi, ldst_forward_matches_0_lo_lo_lo}; // @[lsu.scala:1345:52] wire [1:0] ldst_forward_matches_0_lo_hi_lo = {forward_matches_0_5, forward_matches_0_4}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_lo_hi_hi = {forward_matches_0_7, forward_matches_0_6}; // @[lsu.scala:1317:29, :1345:52] wire [3:0] ldst_forward_matches_0_lo_hi = {ldst_forward_matches_0_lo_hi_hi, ldst_forward_matches_0_lo_hi_lo}; // @[lsu.scala:1345:52] wire [7:0] ldst_forward_matches_0_lo = {ldst_forward_matches_0_lo_hi, ldst_forward_matches_0_lo_lo}; // @[lsu.scala:1345:52] wire [1:0] ldst_forward_matches_0_hi_lo_lo = {forward_matches_0_9, forward_matches_0_8}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_hi_lo_hi = {forward_matches_0_11, forward_matches_0_10}; // @[lsu.scala:1317:29, :1345:52] wire [3:0] ldst_forward_matches_0_hi_lo = {ldst_forward_matches_0_hi_lo_hi, ldst_forward_matches_0_hi_lo_lo}; // @[lsu.scala:1345:52] wire [1:0] ldst_forward_matches_0_hi_hi_lo = {forward_matches_0_13, forward_matches_0_12}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_hi_hi_hi = {forward_matches_0_15, forward_matches_0_14}; // @[lsu.scala:1317:29, :1345:52] wire [3:0] ldst_forward_matches_0_hi_hi = {ldst_forward_matches_0_hi_hi_hi, ldst_forward_matches_0_hi_hi_lo}; // @[lsu.scala:1345:52] wire [7:0] ldst_forward_matches_0_hi = {ldst_forward_matches_0_hi_hi, ldst_forward_matches_0_hi_lo}; // @[lsu.scala:1345:52] wire [15:0] _ldst_forward_matches_0_T = {ldst_forward_matches_0_hi, ldst_forward_matches_0_lo}; // @[lsu.scala:1345:52] wire [15:0] _ldst_forward_matches_0_T_1 = _ldst_forward_matches_0_T & lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1345:{52,59}] assign _ldst_forward_matches_0_T_2 = _ldst_forward_matches_0_T_1 & fast_stq_valids; // @[lsu.scala:1342:35, :1345:{59,82}] assign ldst_forward_matches_0 = _ldst_forward_matches_0_T_2; // @[lsu.scala:1164:34, :1345:82] wire [1:0] stld_prs2_matches_0_lo_lo_lo = {prs2_matches_0_1, prs2_matches_0_0}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_lo_lo_hi = {prs2_matches_0_3, prs2_matches_0_2}; // @[lsu.scala:1318:29, :1346:49] wire [3:0] stld_prs2_matches_0_lo_lo = {stld_prs2_matches_0_lo_lo_hi, stld_prs2_matches_0_lo_lo_lo}; // @[lsu.scala:1346:49] wire [1:0] stld_prs2_matches_0_lo_hi_lo = {prs2_matches_0_5, prs2_matches_0_4}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_lo_hi_hi = {prs2_matches_0_7, prs2_matches_0_6}; // @[lsu.scala:1318:29, :1346:49] wire [3:0] stld_prs2_matches_0_lo_hi = {stld_prs2_matches_0_lo_hi_hi, stld_prs2_matches_0_lo_hi_lo}; // @[lsu.scala:1346:49] wire [7:0] stld_prs2_matches_0_lo = {stld_prs2_matches_0_lo_hi, stld_prs2_matches_0_lo_lo}; // @[lsu.scala:1346:49] wire [1:0] stld_prs2_matches_0_hi_lo_lo = {prs2_matches_0_9, prs2_matches_0_8}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_hi_lo_hi = {prs2_matches_0_11, prs2_matches_0_10}; // @[lsu.scala:1318:29, :1346:49] wire [3:0] stld_prs2_matches_0_hi_lo = {stld_prs2_matches_0_hi_lo_hi, stld_prs2_matches_0_hi_lo_lo}; // @[lsu.scala:1346:49] wire [1:0] stld_prs2_matches_0_hi_hi_lo = {prs2_matches_0_13, prs2_matches_0_12}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_hi_hi_hi = {prs2_matches_0_15, prs2_matches_0_14}; // @[lsu.scala:1318:29, :1346:49] wire [3:0] stld_prs2_matches_0_hi_hi = {stld_prs2_matches_0_hi_hi_hi, stld_prs2_matches_0_hi_hi_lo}; // @[lsu.scala:1346:49] wire [7:0] stld_prs2_matches_0_hi = {stld_prs2_matches_0_hi_hi, stld_prs2_matches_0_hi_lo}; // @[lsu.scala:1346:49] wire [15:0] _stld_prs2_matches_0_T = {stld_prs2_matches_0_hi, stld_prs2_matches_0_lo}; // @[lsu.scala:1346:49] wire [15:0] _stld_prs2_matches_0_T_1 = ~lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1346:58] wire [15:0] _stld_prs2_matches_0_T_2 = _stld_prs2_matches_0_T & _stld_prs2_matches_0_T_1; // @[lsu.scala:1346:{49,56,58}] assign _stld_prs2_matches_0_T_3 = _stld_prs2_matches_0_T_2 & fast_stq_valids; // @[lsu.scala:1342:35, :1346:{56,80}] assign stld_prs2_matches_0 = _stld_prs2_matches_0_T_3; // @[lsu.scala:1166:34, :1346:80] wire _stq_amos_T = stq_uop_0_is_fence | stq_uop_0_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_0 = _stq_amos_T; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_1 = stq_uop_1_is_fence | stq_uop_1_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_1 = _stq_amos_T_1; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_2 = stq_uop_2_is_fence | stq_uop_2_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_2 = _stq_amos_T_2; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_3 = stq_uop_3_is_fence | stq_uop_3_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_3 = _stq_amos_T_3; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_4 = stq_uop_4_is_fence | stq_uop_4_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_4 = _stq_amos_T_4; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_5 = stq_uop_5_is_fence | stq_uop_5_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_5 = _stq_amos_T_5; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_6 = stq_uop_6_is_fence | stq_uop_6_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_6 = _stq_amos_T_6; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_7 = stq_uop_7_is_fence | stq_uop_7_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_7 = _stq_amos_T_7; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_8 = stq_uop_8_is_fence | stq_uop_8_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_8 = _stq_amos_T_8; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_9 = stq_uop_9_is_fence | stq_uop_9_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_9 = _stq_amos_T_9; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_10 = stq_uop_10_is_fence | stq_uop_10_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_10 = _stq_amos_T_10; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_11 = stq_uop_11_is_fence | stq_uop_11_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_11 = _stq_amos_T_11; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_12 = stq_uop_12_is_fence | stq_uop_12_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_12 = _stq_amos_T_12; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_13 = stq_uop_13_is_fence | stq_uop_13_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_13 = _stq_amos_T_13; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_14 = stq_uop_14_is_fence | stq_uop_14_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_14 = _stq_amos_T_14; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_15 = stq_uop_15_is_fence | stq_uop_15_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_15 = _stq_amos_T_15; // @[lsu.scala:1349:{25,54}] wire [1:0] has_older_amo_lo_lo_lo = {stq_amos_1, stq_amos_0}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_lo_lo_hi = {stq_amos_3, stq_amos_2}; // @[lsu.scala:1349:25, :1351:35] wire [3:0] has_older_amo_lo_lo = {has_older_amo_lo_lo_hi, has_older_amo_lo_lo_lo}; // @[lsu.scala:1351:35] wire [1:0] has_older_amo_lo_hi_lo = {stq_amos_5, stq_amos_4}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_lo_hi_hi = {stq_amos_7, stq_amos_6}; // @[lsu.scala:1349:25, :1351:35] wire [3:0] has_older_amo_lo_hi = {has_older_amo_lo_hi_hi, has_older_amo_lo_hi_lo}; // @[lsu.scala:1351:35] wire [7:0] has_older_amo_lo = {has_older_amo_lo_hi, has_older_amo_lo_lo}; // @[lsu.scala:1351:35] wire [1:0] has_older_amo_hi_lo_lo = {stq_amos_9, stq_amos_8}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_hi_lo_hi = {stq_amos_11, stq_amos_10}; // @[lsu.scala:1349:25, :1351:35] wire [3:0] has_older_amo_hi_lo = {has_older_amo_hi_lo_hi, has_older_amo_hi_lo_lo}; // @[lsu.scala:1351:35] wire [1:0] has_older_amo_hi_hi_lo = {stq_amos_13, stq_amos_12}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_hi_hi_hi = {stq_amos_15, stq_amos_14}; // @[lsu.scala:1349:25, :1351:35] wire [3:0] has_older_amo_hi_hi = {has_older_amo_hi_hi_hi, has_older_amo_hi_hi_lo}; // @[lsu.scala:1351:35] wire [7:0] has_older_amo_hi = {has_older_amo_hi_hi, has_older_amo_hi_lo}; // @[lsu.scala:1351:35] wire [15:0] _has_older_amo_T = {has_older_amo_hi, has_older_amo_lo}; // @[lsu.scala:1351:35] wire [15:0] _has_older_amo_T_1 = _has_older_amo_T & lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1351:{35,42}] wire has_older_amo = |_has_older_amo_T_1; // @[lsu.scala:1351:{42,65}] wire _T_1126 = do_ld_search_0 & (|{has_older_amo, ldst_addr_matches_0}); // @[lsu.scala:321:49, :1162:34, :1351:65, :1352:{27,45,70}] reg REG_18; // @[lsu.scala:1353:20] assign io_dmem_s1_kill_0_0 = _T_1126 ? REG_18 & ~fired_load_agen_0 | _GEN_487 | _GEN_469 : _GEN_487 | _GEN_469; // @[lsu.scala:211:7, :321:49, :893:24, :1235:37, :1239:34, :1278:84, :1280:{57,81}, :1281:30, :1352:{27,81}, :1353:{20,55,58,79}, :1354:42] assign s1_set_execute_0 = _T_1126 ? ~(_GEN_395 | _GEN_471) & _GEN_454 : ~_GEN_471 & _GEN_454; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_1 = _T_1126 ? ~(_GEN_396 | _GEN_472) & _GEN_455 : ~_GEN_472 & _GEN_455; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_2 = _T_1126 ? ~(_GEN_397 | _GEN_473) & _GEN_456 : ~_GEN_473 & _GEN_456; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_3 = _T_1126 ? ~(_GEN_398 | _GEN_474) & _GEN_457 : ~_GEN_474 & _GEN_457; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_4 = _T_1126 ? ~(_GEN_399 | _GEN_475) & _GEN_458 : ~_GEN_475 & _GEN_458; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_5 = _T_1126 ? ~(_GEN_400 | _GEN_476) & _GEN_459 : ~_GEN_476 & _GEN_459; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_6 = _T_1126 ? ~(_GEN_401 | _GEN_477) & _GEN_460 : ~_GEN_477 & _GEN_460; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_7 = _T_1126 ? ~(_GEN_402 | _GEN_478) & _GEN_461 : ~_GEN_478 & _GEN_461; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_8 = _T_1126 ? ~(_GEN_403 | _GEN_479) & _GEN_462 : ~_GEN_479 & _GEN_462; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_9 = _T_1126 ? ~(_GEN_404 | _GEN_480) & _GEN_463 : ~_GEN_480 & _GEN_463; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_10 = _T_1126 ? ~(_GEN_405 | _GEN_481) & _GEN_464 : ~_GEN_481 & _GEN_464; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_11 = _T_1126 ? ~(_GEN_406 | _GEN_482) & _GEN_465 : ~_GEN_482 & _GEN_465; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_12 = _T_1126 ? ~(_GEN_407 | _GEN_483) & _GEN_466 : ~_GEN_483 & _GEN_466; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_13 = _T_1126 ? ~(_GEN_408 | _GEN_484) & _GEN_467 : ~_GEN_484 & _GEN_467; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_14 = _T_1126 ? ~(_GEN_409 | _GEN_485) & _GEN_468 : ~_GEN_485 & _GEN_468; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_15 = _T_1126 ? ~((&lcam_ldq_idx_0) | _GEN_486) & _GEN_451 : ~_GEN_486 & _GEN_451; // @[lsu.scala:321:49, :1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign kill_forward_0 = _T_1126 ? has_older_amo | _T_1096 | _GEN_470 : _T_1096 | _GEN_470; // @[lsu.scala:1159:30, :1235:37, :1239:34, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1283:25, :1351:65, :1352:{27,81}, :1357:28, :1358:25] wire _wb_ldst_forward_valid_0_T = _logic_io_found_idx == _logic_1_io_found_idx; // @[lsu.scala:1377:55, :1965:23] wire _wb_ldst_forward_valid_0_T_1 = _wb_ldst_forward_valid_0_T & _logic_io_found; // @[lsu.scala:1377:{55,100}, :1965:23] wire _wb_ldst_forward_valid_0_T_2 = _wb_ldst_forward_valid_0_T_1 & _logic_1_io_found; // @[lsu.scala:1377:100, :1378:100, :1965:23] wire _wb_ldst_forward_valid_0_T_3 = ~kill_forward_0; // @[lsu.scala:1159:30, :1380:63] wire _wb_ldst_forward_valid_0_T_4 = can_forward_0 & _wb_ldst_forward_valid_0_T_3; // @[lsu.scala:321:49, :1380:{60,63}] wire _wb_ldst_forward_valid_0_T_5 = _wb_ldst_forward_valid_0_T_4 & do_ld_search_0; // @[lsu.scala:321:49, :1380:{60,80}] reg wb_ldst_forward_valid_0_REG; // @[lsu.scala:1380:44] wire _wb_ldst_forward_valid_0_T_6 = _wb_ldst_forward_valid_0_T_2 & wb_ldst_forward_valid_0_REG; // @[lsu.scala:1378:100, :1379:100, :1380:44] wire [11:0] _wb_ldst_forward_valid_0_T_7 = io_core_brupdate_b1_mispredict_mask_0 & lcam_uop_0_br_mask; // @[util.scala:126:51] wire _wb_ldst_forward_valid_0_T_8 = |_wb_ldst_forward_valid_0_T_7; // @[util.scala:126:{51,59}] wire _wb_ldst_forward_valid_0_T_9 = _wb_ldst_forward_valid_0_T_8 | io_core_exception_0; // @[util.scala:61:61, :126:59] reg wb_ldst_forward_valid_0_REG_1; // @[lsu.scala:1381:45] wire _wb_ldst_forward_valid_0_T_10 = ~wb_ldst_forward_valid_0_REG_1; // @[lsu.scala:1381:{37,45}] assign _wb_ldst_forward_valid_0_T_11 = _wb_ldst_forward_valid_0_T_6 & _wb_ldst_forward_valid_0_T_10; // @[lsu.scala:1379:100, :1380:100, :1381:37] assign wb_ldst_forward_valid_0 = _wb_ldst_forward_valid_0_T_11; // @[lsu.scala:1172:38, :1380:100] reg REG_19; // @[lsu.scala:1394:18] reg [3:0] store_blocked_counter; // @[lsu.scala:1399:36] wire _store_blocked_counter_T = &store_blocked_counter; // @[lsu.scala:1399:36, :1403:58] wire [4:0] _store_blocked_counter_T_1 = {1'h0, store_blocked_counter} + 5'h1; // @[lsu.scala:1399:36, :1403:96] wire [3:0] _store_blocked_counter_T_2 = _store_blocked_counter_T_1[3:0]; // @[lsu.scala:1403:96] wire [3:0] _store_blocked_counter_T_3 = _store_blocked_counter_T ? 4'hF : _store_blocked_counter_T_2; // @[lsu.scala:1403:{35,58,96}] assign block_load_wakeup = (&store_blocked_counter) | REG_19 & ~wb_ldst_forward_valid_0; // @[lsu.scala:623:35, :1172:38, :1394:{18,49,52,79}, :1399:36, :1405:{33,43}, :1406:25] wire _mem_stld_forward_stq_idx_T = stld_prs2_matches_0[0]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_1 = stld_prs2_matches_0[1]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_2 = stld_prs2_matches_0[2]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_3 = stld_prs2_matches_0[3]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_4 = stld_prs2_matches_0[4]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_5 = stld_prs2_matches_0[5]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_6 = stld_prs2_matches_0[6]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_7 = stld_prs2_matches_0[7]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_8 = stld_prs2_matches_0[8]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_9 = stld_prs2_matches_0[9]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_10 = stld_prs2_matches_0[10]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_11 = stld_prs2_matches_0[11]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_12 = stld_prs2_matches_0[12]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_13 = stld_prs2_matches_0[13]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_14 = stld_prs2_matches_0[14]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_15 = stld_prs2_matches_0[15]; // @[lsu.scala:1166:34, :1412:88] wire mem_stld_forward_stq_idx_temp_vec_15 = _mem_stld_forward_stq_idx_T_15; // @[util.scala:352:65] wire _mem_stld_forward_stq_idx_temp_vec_T = lcam_uop_0_stq_idx == 4'h0; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_0 = _mem_stld_forward_stq_idx_T & _mem_stld_forward_stq_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_1 = lcam_uop_0_stq_idx < 4'h2; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_1 = _mem_stld_forward_stq_idx_T_1 & _mem_stld_forward_stq_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_2 = lcam_uop_0_stq_idx < 4'h3; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_2 = _mem_stld_forward_stq_idx_T_2 & _mem_stld_forward_stq_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_3 = lcam_uop_0_stq_idx < 4'h4; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_3 = _mem_stld_forward_stq_idx_T_3 & _mem_stld_forward_stq_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_4 = lcam_uop_0_stq_idx < 4'h5; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_4 = _mem_stld_forward_stq_idx_T_4 & _mem_stld_forward_stq_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_5 = lcam_uop_0_stq_idx < 4'h6; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_5 = _mem_stld_forward_stq_idx_T_5 & _mem_stld_forward_stq_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_6 = lcam_uop_0_stq_idx < 4'h7; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_6 = _mem_stld_forward_stq_idx_T_6 & _mem_stld_forward_stq_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_7 = ~(lcam_uop_0_stq_idx[3]); // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_7 = _mem_stld_forward_stq_idx_T_7 & _mem_stld_forward_stq_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_8 = lcam_uop_0_stq_idx < 4'h9; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_8 = _mem_stld_forward_stq_idx_T_8 & _mem_stld_forward_stq_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_9 = lcam_uop_0_stq_idx < 4'hA; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_9 = _mem_stld_forward_stq_idx_T_9 & _mem_stld_forward_stq_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_10 = lcam_uop_0_stq_idx < 4'hB; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_10 = _mem_stld_forward_stq_idx_T_10 & _mem_stld_forward_stq_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_11 = lcam_uop_0_stq_idx[3:2] != 2'h3; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_11 = _mem_stld_forward_stq_idx_T_11 & _mem_stld_forward_stq_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_12 = lcam_uop_0_stq_idx < 4'hD; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_12 = _mem_stld_forward_stq_idx_T_12 & _mem_stld_forward_stq_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_13 = lcam_uop_0_stq_idx[3:1] != 3'h7; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_13 = _mem_stld_forward_stq_idx_T_13 & _mem_stld_forward_stq_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_14 = lcam_uop_0_stq_idx != 4'hF; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_14 = _mem_stld_forward_stq_idx_T_14 & _mem_stld_forward_stq_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire [4:0] _mem_stld_forward_stq_idx_idx_T = {4'hF, ~_mem_stld_forward_stq_idx_T_14}; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_1 = _mem_stld_forward_stq_idx_T_13 ? 5'h1D : _mem_stld_forward_stq_idx_idx_T; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_2 = _mem_stld_forward_stq_idx_T_12 ? 5'h1C : _mem_stld_forward_stq_idx_idx_T_1; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_3 = _mem_stld_forward_stq_idx_T_11 ? 5'h1B : _mem_stld_forward_stq_idx_idx_T_2; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_4 = _mem_stld_forward_stq_idx_T_10 ? 5'h1A : _mem_stld_forward_stq_idx_idx_T_3; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_5 = _mem_stld_forward_stq_idx_T_9 ? 5'h19 : _mem_stld_forward_stq_idx_idx_T_4; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_6 = _mem_stld_forward_stq_idx_T_8 ? 5'h18 : _mem_stld_forward_stq_idx_idx_T_5; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_7 = _mem_stld_forward_stq_idx_T_7 ? 5'h17 : _mem_stld_forward_stq_idx_idx_T_6; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_8 = _mem_stld_forward_stq_idx_T_6 ? 5'h16 : _mem_stld_forward_stq_idx_idx_T_7; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_9 = _mem_stld_forward_stq_idx_T_5 ? 5'h15 : _mem_stld_forward_stq_idx_idx_T_8; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_10 = _mem_stld_forward_stq_idx_T_4 ? 5'h14 : _mem_stld_forward_stq_idx_idx_T_9; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_11 = _mem_stld_forward_stq_idx_T_3 ? 5'h13 : _mem_stld_forward_stq_idx_idx_T_10; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_12 = _mem_stld_forward_stq_idx_T_2 ? 5'h12 : _mem_stld_forward_stq_idx_idx_T_11; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_13 = _mem_stld_forward_stq_idx_T_1 ? 5'h11 : _mem_stld_forward_stq_idx_idx_T_12; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_14 = _mem_stld_forward_stq_idx_T ? 5'h10 : _mem_stld_forward_stq_idx_idx_T_13; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_15 = mem_stld_forward_stq_idx_temp_vec_15 ? 5'hF : _mem_stld_forward_stq_idx_idx_T_14; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_16 = mem_stld_forward_stq_idx_temp_vec_14 ? 5'hE : _mem_stld_forward_stq_idx_idx_T_15; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_17 = mem_stld_forward_stq_idx_temp_vec_13 ? 5'hD : _mem_stld_forward_stq_idx_idx_T_16; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_18 = mem_stld_forward_stq_idx_temp_vec_12 ? 5'hC : _mem_stld_forward_stq_idx_idx_T_17; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_19 = mem_stld_forward_stq_idx_temp_vec_11 ? 5'hB : _mem_stld_forward_stq_idx_idx_T_18; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_20 = mem_stld_forward_stq_idx_temp_vec_10 ? 5'hA : _mem_stld_forward_stq_idx_idx_T_19; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_21 = mem_stld_forward_stq_idx_temp_vec_9 ? 5'h9 : _mem_stld_forward_stq_idx_idx_T_20; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_22 = mem_stld_forward_stq_idx_temp_vec_8 ? 5'h8 : _mem_stld_forward_stq_idx_idx_T_21; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_23 = mem_stld_forward_stq_idx_temp_vec_7 ? 5'h7 : _mem_stld_forward_stq_idx_idx_T_22; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_24 = mem_stld_forward_stq_idx_temp_vec_6 ? 5'h6 : _mem_stld_forward_stq_idx_idx_T_23; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_25 = mem_stld_forward_stq_idx_temp_vec_5 ? 5'h5 : _mem_stld_forward_stq_idx_idx_T_24; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_26 = mem_stld_forward_stq_idx_temp_vec_4 ? 5'h4 : _mem_stld_forward_stq_idx_idx_T_25; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_27 = mem_stld_forward_stq_idx_temp_vec_3 ? 5'h3 : _mem_stld_forward_stq_idx_idx_T_26; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_28 = mem_stld_forward_stq_idx_temp_vec_2 ? 5'h2 : _mem_stld_forward_stq_idx_idx_T_27; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_idx_T_29 = mem_stld_forward_stq_idx_temp_vec_1 ? 5'h1 : _mem_stld_forward_stq_idx_idx_T_28; // @[Mux.scala:50:70] wire [4:0] mem_stld_forward_stq_idx_idx = mem_stld_forward_stq_idx_temp_vec_0 ? 5'h0 : _mem_stld_forward_stq_idx_idx_T_29; // @[Mux.scala:50:70] wire [3:0] _mem_stld_forward_stq_idx_T_16 = mem_stld_forward_stq_idx_idx[3:0]; // @[Mux.scala:50:70] wire [3:0] mem_stld_forward_stq_idx_0 = _mem_stld_forward_stq_idx_T_16; // @[util.scala:354:8] wire [15:0] _mem_stld_forward_valid_T = stld_prs2_matches_0 >> mem_stld_forward_stq_idx_0; // @[lsu.scala:321:49, :1166:34, :1413:87] wire _mem_stld_forward_valid_T_1 = _mem_stld_forward_valid_T[0]; // @[lsu.scala:1413:87] wire _mem_stld_forward_valid_T_2 = do_ld_search_0 & _mem_stld_forward_valid_T_1; // @[lsu.scala:321:49, :1413:{64,87}] wire mem_stld_forward_valid_0 = _mem_stld_forward_valid_T_2; // @[lsu.scala:321:49, :1413:64] reg io_core_clr_unsafe_0_valid_REG; // @[lsu.scala:1421:14] wire _io_core_clr_unsafe_0_valid_T = ~io_dmem_nack_0_valid_0; // @[lsu.scala:211:7, :1422:8] wire _io_core_clr_unsafe_0_valid_T_1 = ~fired_load_agen_0; // @[lsu.scala:321:49, :1422:61] wire _io_core_clr_unsafe_0_valid_T_2 = do_ld_search_0 & _io_core_clr_unsafe_0_valid_T_1; // @[lsu.scala:321:49, :1422:{58,61}] wire _io_core_clr_unsafe_0_valid_T_3 = ~io_dmem_s1_kill_0_0; // @[lsu.scala:211:7, :1422:84] wire _io_core_clr_unsafe_0_valid_T_4 = _io_core_clr_unsafe_0_valid_T_2 & _io_core_clr_unsafe_0_valid_T_3; // @[lsu.scala:1422:{58,81,84}] reg io_core_clr_unsafe_0_valid_REG_1; // @[lsu.scala:1422:114] wire _io_core_clr_unsafe_0_valid_T_5 = _io_core_clr_unsafe_0_valid_T_4 & io_core_clr_unsafe_0_valid_REG_1; // @[lsu.scala:1422:{81,104,114}] reg io_core_clr_unsafe_0_valid_REG_2; // @[lsu.scala:1422:41] wire _io_core_clr_unsafe_0_valid_T_6 = _io_core_clr_unsafe_0_valid_T & io_core_clr_unsafe_0_valid_REG_2; // @[lsu.scala:1422:{8,31,41}] wire _io_core_clr_unsafe_0_valid_T_7 = io_core_clr_unsafe_0_valid_REG | _io_core_clr_unsafe_0_valid_T_6; // @[lsu.scala:1421:{14,32}, :1422:31] reg io_core_clr_unsafe_0_valid_REG_3; // @[lsu.scala:1423:18] wire _io_core_clr_unsafe_0_valid_T_8 = ~io_core_clr_unsafe_0_valid_REG_3; // @[lsu.scala:1423:{10,18}] assign _io_core_clr_unsafe_0_valid_T_9 = _io_core_clr_unsafe_0_valid_T_7 & _io_core_clr_unsafe_0_valid_T_8; // @[lsu.scala:1421:32, :1423:{7,10}] assign io_core_clr_unsafe_0_valid_0 = _io_core_clr_unsafe_0_valid_T_9; // @[lsu.scala:211:7, :1423:7] reg [5:0] io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:1424:43] assign io_core_clr_unsafe_0_bits_0 = io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:211:7, :1424:43] wire _l_idx_T = ldq_valid_0 & ldq_order_fail_0; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_1 = ldq_valid_1 & ldq_order_fail_1; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_2 = ldq_valid_2 & ldq_order_fail_2; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_3 = ldq_valid_3 & ldq_order_fail_3; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_4 = ldq_valid_4 & ldq_order_fail_4; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_5 = ldq_valid_5 & ldq_order_fail_5; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_6 = ldq_valid_6 & ldq_order_fail_6; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_7 = ldq_valid_7 & ldq_order_fail_7; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_8 = ldq_valid_8 & ldq_order_fail_8; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_9 = ldq_valid_9 & ldq_order_fail_9; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_10 = ldq_valid_10 & ldq_order_fail_10; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_11 = ldq_valid_11 & ldq_order_fail_11; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_12 = ldq_valid_12 & ldq_order_fail_12; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_13 = ldq_valid_13 & ldq_order_fail_13; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_14 = ldq_valid_14 & ldq_order_fail_14; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_15 = ldq_valid_15 & ldq_order_fail_15; // @[lsu.scala:218:36, :225:36, :1429:82] wire l_idx_temp_vec_15 = _l_idx_T_15; // @[util.scala:352:65] wire l_idx_temp_vec_0 = _l_idx_T & _l_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_1 = _l_idx_T_1 & _l_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_2 = _l_idx_T_2 & _l_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_3 = _l_idx_T_3 & _l_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_4 = _l_idx_T_4 & _l_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_5 = _l_idx_T_5 & _l_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_6 = _l_idx_T_6 & _l_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _l_idx_temp_vec_T_7 = ~(ldq_head[3]); // @[util.scala:352:72] wire l_idx_temp_vec_7 = _l_idx_T_7 & _l_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_8 = _l_idx_T_8 & _l_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_9 = _l_idx_T_9 & _l_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_10 = _l_idx_T_10 & _l_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_11 = _l_idx_T_11 & _l_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_12 = _l_idx_T_12 & _l_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_13 = _l_idx_T_13 & _l_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_14 = _l_idx_T_14 & _l_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire [4:0] _l_idx_idx_T = {4'hF, ~_l_idx_T_14}; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_1 = _l_idx_T_13 ? 5'h1D : _l_idx_idx_T; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_2 = _l_idx_T_12 ? 5'h1C : _l_idx_idx_T_1; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_3 = _l_idx_T_11 ? 5'h1B : _l_idx_idx_T_2; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_4 = _l_idx_T_10 ? 5'h1A : _l_idx_idx_T_3; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_5 = _l_idx_T_9 ? 5'h19 : _l_idx_idx_T_4; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_6 = _l_idx_T_8 ? 5'h18 : _l_idx_idx_T_5; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_7 = _l_idx_T_7 ? 5'h17 : _l_idx_idx_T_6; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_8 = _l_idx_T_6 ? 5'h16 : _l_idx_idx_T_7; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_9 = _l_idx_T_5 ? 5'h15 : _l_idx_idx_T_8; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_10 = _l_idx_T_4 ? 5'h14 : _l_idx_idx_T_9; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_11 = _l_idx_T_3 ? 5'h13 : _l_idx_idx_T_10; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_12 = _l_idx_T_2 ? 5'h12 : _l_idx_idx_T_11; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_13 = _l_idx_T_1 ? 5'h11 : _l_idx_idx_T_12; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_14 = _l_idx_T ? 5'h10 : _l_idx_idx_T_13; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_15 = l_idx_temp_vec_15 ? 5'hF : _l_idx_idx_T_14; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_16 = l_idx_temp_vec_14 ? 5'hE : _l_idx_idx_T_15; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_17 = l_idx_temp_vec_13 ? 5'hD : _l_idx_idx_T_16; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_18 = l_idx_temp_vec_12 ? 5'hC : _l_idx_idx_T_17; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_19 = l_idx_temp_vec_11 ? 5'hB : _l_idx_idx_T_18; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_20 = l_idx_temp_vec_10 ? 5'hA : _l_idx_idx_T_19; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_21 = l_idx_temp_vec_9 ? 5'h9 : _l_idx_idx_T_20; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_22 = l_idx_temp_vec_8 ? 5'h8 : _l_idx_idx_T_21; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_23 = l_idx_temp_vec_7 ? 5'h7 : _l_idx_idx_T_22; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_24 = l_idx_temp_vec_6 ? 5'h6 : _l_idx_idx_T_23; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_25 = l_idx_temp_vec_5 ? 5'h5 : _l_idx_idx_T_24; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_26 = l_idx_temp_vec_4 ? 5'h4 : _l_idx_idx_T_25; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_27 = l_idx_temp_vec_3 ? 5'h3 : _l_idx_idx_T_26; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_28 = l_idx_temp_vec_2 ? 5'h2 : _l_idx_idx_T_27; // @[Mux.scala:50:70] wire [4:0] _l_idx_idx_T_29 = l_idx_temp_vec_1 ? 5'h1 : _l_idx_idx_T_28; // @[Mux.scala:50:70] wire [4:0] l_idx_idx = l_idx_temp_vec_0 ? 5'h0 : _l_idx_idx_T_29; // @[Mux.scala:50:70] wire [3:0] l_idx = l_idx_idx[3:0]; // @[Mux.scala:50:70] reg r_xcpt_valid; // @[lsu.scala:1434:29] reg [31:0] r_xcpt_uop_inst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_inst_0 = r_xcpt_uop_inst; // @[lsu.scala:211:7, :1435:25] reg [31:0] r_xcpt_uop_debug_inst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_inst_0 = r_xcpt_uop_debug_inst; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_rvc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_rvc_0 = r_xcpt_uop_is_rvc; // @[lsu.scala:211:7, :1435:25] reg [39:0] r_xcpt_uop_debug_pc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_pc_0 = r_xcpt_uop_debug_pc; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_0; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_0_0 = r_xcpt_uop_iq_type_0; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_1_0 = r_xcpt_uop_iq_type_1; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_2_0 = r_xcpt_uop_iq_type_2; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_3_0 = r_xcpt_uop_iq_type_3; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_0; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_0_0 = r_xcpt_uop_fu_code_0; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_1_0 = r_xcpt_uop_fu_code_1; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_2_0 = r_xcpt_uop_fu_code_2; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_3_0 = r_xcpt_uop_fu_code_3; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_4; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_4_0 = r_xcpt_uop_fu_code_4; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_5; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_5_0 = r_xcpt_uop_fu_code_5; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_6; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_6_0 = r_xcpt_uop_fu_code_6; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_7; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_7_0 = r_xcpt_uop_fu_code_7; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_8; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_8_0 = r_xcpt_uop_fu_code_8; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_9; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_9_0 = r_xcpt_uop_fu_code_9; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_issued; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_issued_0 = r_xcpt_uop_iw_issued; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_issued_partial_agen_0 = r_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_issued_partial_dgen_0 = r_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p1_speculative_child_0 = r_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p2_speculative_child_0 = r_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p1_bypass_hint_0 = r_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p2_bypass_hint_0 = r_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p3_bypass_hint_0 = r_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_dis_col_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_dis_col_sel_0 = r_xcpt_uop_dis_col_sel; // @[lsu.scala:211:7, :1435:25] reg [11:0] r_xcpt_uop_br_mask; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_br_mask_0 = r_xcpt_uop_br_mask; // @[lsu.scala:211:7, :1435:25] reg [3:0] r_xcpt_uop_br_tag; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_br_tag_0 = r_xcpt_uop_br_tag; // @[lsu.scala:211:7, :1435:25] reg [3:0] r_xcpt_uop_br_type; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_br_type_0 = r_xcpt_uop_br_type; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_sfb; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_sfb_0 = r_xcpt_uop_is_sfb; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_fence; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_fence_0 = r_xcpt_uop_is_fence; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_fencei; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_fencei_0 = r_xcpt_uop_is_fencei; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_sfence; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_sfence_0 = r_xcpt_uop_is_sfence; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_amo; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_amo_0 = r_xcpt_uop_is_amo; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_eret; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_eret_0 = r_xcpt_uop_is_eret; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_sys_pc2epc_0 = r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_rocc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_rocc_0 = r_xcpt_uop_is_rocc; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_mov; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_mov_0 = r_xcpt_uop_is_mov; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_ftq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ftq_idx_0 = r_xcpt_uop_ftq_idx; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_edge_inst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_edge_inst_0 = r_xcpt_uop_edge_inst; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_pc_lob; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_pc_lob_0 = r_xcpt_uop_pc_lob; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_taken; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_taken_0 = r_xcpt_uop_taken; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_imm_rename; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_imm_rename_0 = r_xcpt_uop_imm_rename; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_imm_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_imm_sel_0 = r_xcpt_uop_imm_sel; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_pimm; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_pimm_0 = r_xcpt_uop_pimm; // @[lsu.scala:211:7, :1435:25] reg [19:0] r_xcpt_uop_imm_packed; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_imm_packed_0 = r_xcpt_uop_imm_packed; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_op1_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_op1_sel_0 = r_xcpt_uop_op1_sel; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_op2_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_op2_sel_0 = r_xcpt_uop_op2_sel; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ldst_0 = r_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_wen_0 = r_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ren1_0 = r_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ren2_0 = r_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ren3_0 = r_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_swap12_0 = r_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_swap23_0 = r_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn_0 = r_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut_0 = r_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_fromint_0 = r_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_toint_0 = r_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_fastpipe_0 = r_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_fma_0 = r_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_div; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_div_0 = r_xcpt_uop_fp_ctrl_div; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_sqrt_0 = r_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_wflags_0 = r_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_vec_0 = r_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_rob_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_rob_idx_0 = r_xcpt_uop_rob_idx; // @[lsu.scala:211:7, :1435:25] reg [3:0] r_xcpt_uop_ldq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ldq_idx_0 = r_xcpt_uop_ldq_idx; // @[lsu.scala:211:7, :1435:25] reg [3:0] r_xcpt_uop_stq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_stq_idx_0 = r_xcpt_uop_stq_idx; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_rxq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_rxq_idx_0 = r_xcpt_uop_rxq_idx; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_pdst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_pdst_0 = r_xcpt_uop_pdst; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_prs1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs1_0 = r_xcpt_uop_prs1; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_prs2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs2_0 = r_xcpt_uop_prs2; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_prs3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs3_0 = r_xcpt_uop_prs3; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_ppred; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ppred_0 = r_xcpt_uop_ppred; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_prs1_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs1_busy_0 = r_xcpt_uop_prs1_busy; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_prs2_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs2_busy_0 = r_xcpt_uop_prs2_busy; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_prs3_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs3_busy_0 = r_xcpt_uop_prs3_busy; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_ppred_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ppred_busy_0 = r_xcpt_uop_ppred_busy; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_stale_pdst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_stale_pdst_0 = r_xcpt_uop_stale_pdst; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_exception; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_exception_0 = r_xcpt_uop_exception; // @[lsu.scala:211:7, :1435:25] reg [63:0] r_xcpt_uop_exc_cause; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_exc_cause_0 = r_xcpt_uop_exc_cause; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_mem_cmd; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_mem_cmd_0 = r_xcpt_uop_mem_cmd; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_mem_size; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_mem_size_0 = r_xcpt_uop_mem_size; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_mem_signed; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_mem_signed_0 = r_xcpt_uop_mem_signed; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_uses_ldq; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_uses_ldq_0 = r_xcpt_uop_uses_ldq; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_uses_stq; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_uses_stq_0 = r_xcpt_uop_uses_stq; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_unique; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_unique_0 = r_xcpt_uop_is_unique; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_flush_on_commit; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_flush_on_commit_0 = r_xcpt_uop_flush_on_commit; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_csr_cmd; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_csr_cmd_0 = r_xcpt_uop_csr_cmd; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ldst_is_rs1_0 = r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_ldst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ldst_0 = r_xcpt_uop_ldst; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_lrs1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs1_0 = r_xcpt_uop_lrs1; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_lrs2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs2_0 = r_xcpt_uop_lrs2; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_lrs3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs3_0 = r_xcpt_uop_lrs3; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_dst_rtype; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_dst_rtype_0 = r_xcpt_uop_dst_rtype; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_lrs1_rtype; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs1_rtype_0 = r_xcpt_uop_lrs1_rtype; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_lrs2_rtype; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs2_rtype_0 = r_xcpt_uop_lrs2_rtype; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_frs3_en; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_frs3_en_0 = r_xcpt_uop_frs3_en; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fcn_dw; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fcn_dw_0 = r_xcpt_uop_fcn_dw; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_fcn_op; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fcn_op_0 = r_xcpt_uop_fcn_op; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_val; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_val_0 = r_xcpt_uop_fp_val; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_fp_rm; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_rm_0 = r_xcpt_uop_fp_rm; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_fp_typ; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_typ_0 = r_xcpt_uop_fp_typ; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_xcpt_pf_if_0 = r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_xcpt_ae_if_0 = r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_xcpt_ma_if_0 = r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_bp_debug_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_bp_debug_if_0 = r_xcpt_uop_bp_debug_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_bp_xcpt_if_0 = r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_debug_fsrc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_fsrc_0 = r_xcpt_uop_debug_fsrc; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_debug_tsrc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_tsrc_0 = r_xcpt_uop_debug_tsrc; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_cause; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_cause_0 = r_xcpt_cause; // @[lsu.scala:211:7, :1435:25] reg [39:0] r_xcpt_badvaddr; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_badvaddr_0 = r_xcpt_badvaddr; // @[lsu.scala:211:7, :1435:25] wire [1:0] ld_xcpt_valid_lo_lo_lo = {ldq_order_fail_1, ldq_order_fail_0}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_lo_lo_hi = {ldq_order_fail_3, ldq_order_fail_2}; // @[lsu.scala:225:36, :1437:39] wire [3:0] ld_xcpt_valid_lo_lo = {ld_xcpt_valid_lo_lo_hi, ld_xcpt_valid_lo_lo_lo}; // @[lsu.scala:1437:39] wire [1:0] ld_xcpt_valid_lo_hi_lo = {ldq_order_fail_5, ldq_order_fail_4}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_lo_hi_hi = {ldq_order_fail_7, ldq_order_fail_6}; // @[lsu.scala:225:36, :1437:39] wire [3:0] ld_xcpt_valid_lo_hi = {ld_xcpt_valid_lo_hi_hi, ld_xcpt_valid_lo_hi_lo}; // @[lsu.scala:1437:39] wire [7:0] ld_xcpt_valid_lo = {ld_xcpt_valid_lo_hi, ld_xcpt_valid_lo_lo}; // @[lsu.scala:1437:39] wire [1:0] ld_xcpt_valid_hi_lo_lo = {ldq_order_fail_9, ldq_order_fail_8}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_hi_lo_hi = {ldq_order_fail_11, ldq_order_fail_10}; // @[lsu.scala:225:36, :1437:39] wire [3:0] ld_xcpt_valid_hi_lo = {ld_xcpt_valid_hi_lo_hi, ld_xcpt_valid_hi_lo_lo}; // @[lsu.scala:1437:39] wire [1:0] ld_xcpt_valid_hi_hi_lo = {ldq_order_fail_13, ldq_order_fail_12}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_hi_hi_hi = {ldq_order_fail_15, ldq_order_fail_14}; // @[lsu.scala:225:36, :1437:39] wire [3:0] ld_xcpt_valid_hi_hi = {ld_xcpt_valid_hi_hi_hi, ld_xcpt_valid_hi_hi_lo}; // @[lsu.scala:1437:39] wire [7:0] ld_xcpt_valid_hi = {ld_xcpt_valid_hi_hi, ld_xcpt_valid_hi_lo}; // @[lsu.scala:1437:39] wire [15:0] _ld_xcpt_valid_T = {ld_xcpt_valid_hi, ld_xcpt_valid_lo}; // @[lsu.scala:1437:39] wire [3:0] ld_xcpt_valid_lo_lo_1 = {ld_xcpt_valid_lo_lo_hi_1, ld_xcpt_valid_lo_lo_lo_1}; // @[lsu.scala:1437:58] wire [3:0] ld_xcpt_valid_lo_hi_1 = {ld_xcpt_valid_lo_hi_hi_1, ld_xcpt_valid_lo_hi_lo_1}; // @[lsu.scala:1437:58] wire [7:0] ld_xcpt_valid_lo_1 = {ld_xcpt_valid_lo_hi_1, ld_xcpt_valid_lo_lo_1}; // @[lsu.scala:1437:58] wire [3:0] ld_xcpt_valid_hi_lo_1 = {ld_xcpt_valid_hi_lo_hi_1, ld_xcpt_valid_hi_lo_lo_1}; // @[lsu.scala:1437:58] wire [3:0] ld_xcpt_valid_hi_hi_1 = {ld_xcpt_valid_hi_hi_hi_1, ld_xcpt_valid_hi_hi_lo_1}; // @[lsu.scala:1437:58] wire [7:0] ld_xcpt_valid_hi_1 = {ld_xcpt_valid_hi_hi_1, ld_xcpt_valid_hi_lo_1}; // @[lsu.scala:1437:58] wire [15:0] _ld_xcpt_valid_T_1 = {ld_xcpt_valid_hi_1, ld_xcpt_valid_lo_1}; // @[lsu.scala:1437:58] wire [15:0] _ld_xcpt_valid_T_2 = _ld_xcpt_valid_T & _ld_xcpt_valid_T_1; // @[lsu.scala:1437:{39,46,58}] wire ld_xcpt_valid = |_ld_xcpt_valid_T_2; // @[lsu.scala:1437:{46,66}] wire [5:0] _ld_xcpt_uop_T_1 = {2'h0, l_idx} - 6'h10; // @[util.scala:354:8] wire [4:0] _ld_xcpt_uop_T_2 = _ld_xcpt_uop_T_1[4:0]; // @[lsu.scala:1438:76] wire [4:0] _ld_xcpt_uop_T_3 = {1'h0, l_idx}; // @[util.scala:354:8] wire [3:0] _ld_xcpt_uop_T_4 = _ld_xcpt_uop_T_3[3:0]; // @[lsu.scala:1438:43] wire ld_xcpt_uop_iq_type_0; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iq_type_1; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iq_type_2; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iq_type_3; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_0; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_1; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_2; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_3; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_4; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_5; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_6; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_7; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_8; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_9; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_div; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:1438:31] wire [31:0] ld_xcpt_uop_inst; // @[lsu.scala:1438:31] wire [31:0] ld_xcpt_uop_debug_inst; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_rvc; // @[lsu.scala:1438:31] wire [39:0] ld_xcpt_uop_debug_pc; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_issued; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_dis_col_sel; // @[lsu.scala:1438:31] wire [11:0] ld_xcpt_uop_br_mask; // @[lsu.scala:1438:31] wire [3:0] ld_xcpt_uop_br_tag; // @[lsu.scala:1438:31] wire [3:0] ld_xcpt_uop_br_type; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_sfb; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_fence; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_fencei; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_sfence; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_amo; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_eret; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_rocc; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_mov; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_ftq_idx; // @[lsu.scala:1438:31] wire ld_xcpt_uop_edge_inst; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_pc_lob; // @[lsu.scala:1438:31] wire ld_xcpt_uop_taken; // @[lsu.scala:1438:31] wire ld_xcpt_uop_imm_rename; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_imm_sel; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_pimm; // @[lsu.scala:1438:31] wire [19:0] ld_xcpt_uop_imm_packed; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_op1_sel; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_op2_sel; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_rob_idx; // @[lsu.scala:1438:31] wire [3:0] ld_xcpt_uop_ldq_idx; // @[lsu.scala:1438:31] wire [3:0] ld_xcpt_uop_stq_idx; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_rxq_idx; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_pdst; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_prs1; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_prs2; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_prs3; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_ppred; // @[lsu.scala:1438:31] wire ld_xcpt_uop_prs1_busy; // @[lsu.scala:1438:31] wire ld_xcpt_uop_prs2_busy; // @[lsu.scala:1438:31] wire ld_xcpt_uop_prs3_busy; // @[lsu.scala:1438:31] wire ld_xcpt_uop_ppred_busy; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_stale_pdst; // @[lsu.scala:1438:31] wire ld_xcpt_uop_exception; // @[lsu.scala:1438:31] wire [63:0] ld_xcpt_uop_exc_cause; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_mem_cmd; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_mem_size; // @[lsu.scala:1438:31] wire ld_xcpt_uop_mem_signed; // @[lsu.scala:1438:31] wire ld_xcpt_uop_uses_ldq; // @[lsu.scala:1438:31] wire ld_xcpt_uop_uses_stq; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_unique; // @[lsu.scala:1438:31] wire ld_xcpt_uop_flush_on_commit; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_csr_cmd; // @[lsu.scala:1438:31] wire ld_xcpt_uop_ldst_is_rs1; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_ldst; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_lrs1; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_lrs2; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_lrs3; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_dst_rtype; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_lrs1_rtype; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_lrs2_rtype; // @[lsu.scala:1438:31] wire ld_xcpt_uop_frs3_en; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fcn_dw; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_fcn_op; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_val; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_fp_rm; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_fp_typ; // @[lsu.scala:1438:31] wire ld_xcpt_uop_xcpt_pf_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_xcpt_ae_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_xcpt_ma_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_bp_debug_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_bp_xcpt_if; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_debug_fsrc; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_debug_tsrc; // @[lsu.scala:1438:31] assign ld_xcpt_uop_inst = _GEN_76[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_debug_inst = _GEN_77[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_rvc = _GEN_78[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_debug_pc = _GEN_79[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iq_type_0 = _GEN_80[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iq_type_1 = _GEN_81[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iq_type_2 = _GEN_82[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iq_type_3 = _GEN_83[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_0 = _GEN_84[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_1 = _GEN_85[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_2 = _GEN_86[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_3 = _GEN_87[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_4 = _GEN_88[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_5 = _GEN_89[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_6 = _GEN_90[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_7 = _GEN_91[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_8 = _GEN_92[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fu_code_9 = _GEN_93[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_issued = _GEN_94[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_issued_partial_agen = _GEN_95[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_issued_partial_dgen = _GEN_96[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_p1_speculative_child = _GEN_97[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_p2_speculative_child = _GEN_98[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_p1_bypass_hint = _GEN_99[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_p2_bypass_hint = _GEN_100[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_iw_p3_bypass_hint = _GEN_101[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_dis_col_sel = _GEN_102[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_br_mask = _GEN_103[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_br_tag = _GEN_104[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_br_type = _GEN_105[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_sfb = _GEN_106[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_fence = _GEN_107[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_fencei = _GEN_108[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_sfence = _GEN_109[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_amo = _GEN_110[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_eret = _GEN_111[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_sys_pc2epc = _GEN_112[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_rocc = _GEN_113[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_mov = _GEN_114[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_ftq_idx = _GEN_115[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_edge_inst = _GEN_116[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_pc_lob = _GEN_117[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_taken = _GEN_118[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_imm_rename = _GEN_119[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_imm_sel = _GEN_120[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_pimm = _GEN_121[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_imm_packed = _GEN_122[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_op1_sel = _GEN_123[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_op2_sel = _GEN_124[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_ldst = _GEN_125[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_wen = _GEN_126[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_ren1 = _GEN_127[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_ren2 = _GEN_128[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_ren3 = _GEN_129[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_swap12 = _GEN_130[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_swap23 = _GEN_131[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_typeTagIn = _GEN_132[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_typeTagOut = _GEN_133[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_fromint = _GEN_134[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_toint = _GEN_135[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_fastpipe = _GEN_136[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_fma = _GEN_137[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_div = _GEN_138[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_sqrt = _GEN_139[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_wflags = _GEN_140[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_ctrl_vec = _GEN_141[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_rob_idx = _GEN_142[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_ldq_idx = _GEN_143[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_stq_idx = _GEN_144[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_rxq_idx = _GEN_145[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_pdst = _GEN_146[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_prs1 = _GEN_147[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_prs2 = _GEN_148[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_prs3 = _GEN_149[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_ppred = _GEN_150[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_prs1_busy = _GEN_151[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_prs2_busy = _GEN_152[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_prs3_busy = _GEN_153[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_ppred_busy = _GEN_154[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_stale_pdst = _GEN_155[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_exception = _GEN_156[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_exc_cause = _GEN_157[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_mem_cmd = _GEN_158[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_mem_size = _GEN_159[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_mem_signed = _GEN_160[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_uses_ldq = _GEN_161[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_uses_stq = _GEN_162[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_is_unique = _GEN_163[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_flush_on_commit = _GEN_164[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_csr_cmd = _GEN_165[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_ldst_is_rs1 = _GEN_166[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_ldst = _GEN_167[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_lrs1 = _GEN_168[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_lrs2 = _GEN_169[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_lrs3 = _GEN_170[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_dst_rtype = _GEN_171[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_lrs1_rtype = _GEN_172[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_lrs2_rtype = _GEN_173[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_frs3_en = _GEN_174[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fcn_dw = _GEN_175[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fcn_op = _GEN_176[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_val = _GEN_177[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_rm = _GEN_178[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_fp_typ = _GEN_179[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_xcpt_pf_if = _GEN_180[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_xcpt_ae_if = _GEN_181[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_xcpt_ma_if = _GEN_182[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_bp_debug_if = _GEN_183[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_bp_xcpt_if = _GEN_184[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_debug_fsrc = _GEN_185[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] assign ld_xcpt_uop_debug_tsrc = _GEN_186[_ld_xcpt_uop_T_4]; // @[lsu.scala:235:32, :1438:31] wire _use_mem_xcpt_T = mem_xcpt_uop_rob_idx < ld_xcpt_uop_rob_idx; // @[util.scala:364:52] wire _use_mem_xcpt_T_1 = mem_xcpt_uop_rob_idx < io_core_rob_head_idx_0; // @[util.scala:364:64] wire _use_mem_xcpt_T_2 = _use_mem_xcpt_T ^ _use_mem_xcpt_T_1; // @[util.scala:364:{52,58,64}] wire _use_mem_xcpt_T_3 = ld_xcpt_uop_rob_idx < io_core_rob_head_idx_0; // @[util.scala:364:78] wire _use_mem_xcpt_T_4 = _use_mem_xcpt_T_2 ^ _use_mem_xcpt_T_3; // @[util.scala:364:{58,72,78}] wire _use_mem_xcpt_T_5 = mem_xcpt_valid & _use_mem_xcpt_T_4; // @[util.scala:364:72] wire _use_mem_xcpt_T_6 = ~ld_xcpt_valid; // @[lsu.scala:1437:66, :1440:118] wire use_mem_xcpt = _use_mem_xcpt_T_5 | _use_mem_xcpt_T_6; // @[lsu.scala:1440:{38,115,118}] wire [31:0] xcpt_uop_inst = use_mem_xcpt ? mem_xcpt_uop_inst : ld_xcpt_uop_inst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [31:0] xcpt_uop_debug_inst = use_mem_xcpt ? mem_xcpt_uop_debug_inst : ld_xcpt_uop_debug_inst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_rvc = use_mem_xcpt ? mem_xcpt_uop_is_rvc : ld_xcpt_uop_is_rvc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [39:0] xcpt_uop_debug_pc = use_mem_xcpt ? mem_xcpt_uop_debug_pc : ld_xcpt_uop_debug_pc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_0 = use_mem_xcpt ? mem_xcpt_uop_iq_type_0 : ld_xcpt_uop_iq_type_0; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_1 = use_mem_xcpt ? mem_xcpt_uop_iq_type_1 : ld_xcpt_uop_iq_type_1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_2 = use_mem_xcpt ? mem_xcpt_uop_iq_type_2 : ld_xcpt_uop_iq_type_2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_3 = use_mem_xcpt ? mem_xcpt_uop_iq_type_3 : ld_xcpt_uop_iq_type_3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_0 = use_mem_xcpt ? mem_xcpt_uop_fu_code_0 : ld_xcpt_uop_fu_code_0; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_1 = use_mem_xcpt ? mem_xcpt_uop_fu_code_1 : ld_xcpt_uop_fu_code_1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_2 = use_mem_xcpt ? mem_xcpt_uop_fu_code_2 : ld_xcpt_uop_fu_code_2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_3 = use_mem_xcpt ? mem_xcpt_uop_fu_code_3 : ld_xcpt_uop_fu_code_3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_4 = use_mem_xcpt ? mem_xcpt_uop_fu_code_4 : ld_xcpt_uop_fu_code_4; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_5 = use_mem_xcpt ? mem_xcpt_uop_fu_code_5 : ld_xcpt_uop_fu_code_5; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_6 = use_mem_xcpt ? mem_xcpt_uop_fu_code_6 : ld_xcpt_uop_fu_code_6; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_7 = use_mem_xcpt ? mem_xcpt_uop_fu_code_7 : ld_xcpt_uop_fu_code_7; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_8 = use_mem_xcpt ? mem_xcpt_uop_fu_code_8 : ld_xcpt_uop_fu_code_8; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_9 = use_mem_xcpt ? mem_xcpt_uop_fu_code_9 : ld_xcpt_uop_fu_code_9; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_issued = use_mem_xcpt ? mem_xcpt_uop_iw_issued : ld_xcpt_uop_iw_issued; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_issued_partial_agen = use_mem_xcpt ? mem_xcpt_uop_iw_issued_partial_agen : ld_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_issued_partial_dgen = use_mem_xcpt ? mem_xcpt_uop_iw_issued_partial_dgen : ld_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_iw_p1_speculative_child = use_mem_xcpt ? mem_xcpt_uop_iw_p1_speculative_child : ld_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_iw_p2_speculative_child = use_mem_xcpt ? mem_xcpt_uop_iw_p2_speculative_child : ld_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_p1_bypass_hint = use_mem_xcpt ? mem_xcpt_uop_iw_p1_bypass_hint : ld_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_p2_bypass_hint = use_mem_xcpt ? mem_xcpt_uop_iw_p2_bypass_hint : ld_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_p3_bypass_hint = use_mem_xcpt ? mem_xcpt_uop_iw_p3_bypass_hint : ld_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_dis_col_sel = use_mem_xcpt ? mem_xcpt_uop_dis_col_sel : ld_xcpt_uop_dis_col_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [11:0] xcpt_uop_br_mask = use_mem_xcpt ? mem_xcpt_uop_br_mask : ld_xcpt_uop_br_mask; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [3:0] xcpt_uop_br_tag = use_mem_xcpt ? mem_xcpt_uop_br_tag : ld_xcpt_uop_br_tag; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [3:0] xcpt_uop_br_type = use_mem_xcpt ? mem_xcpt_uop_br_type : ld_xcpt_uop_br_type; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_sfb = use_mem_xcpt ? mem_xcpt_uop_is_sfb : ld_xcpt_uop_is_sfb; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_fence = use_mem_xcpt ? mem_xcpt_uop_is_fence : ld_xcpt_uop_is_fence; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_fencei = use_mem_xcpt ? mem_xcpt_uop_is_fencei : ld_xcpt_uop_is_fencei; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_sfence = use_mem_xcpt ? mem_xcpt_uop_is_sfence : ld_xcpt_uop_is_sfence; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_amo = use_mem_xcpt ? mem_xcpt_uop_is_amo : ld_xcpt_uop_is_amo; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_eret = use_mem_xcpt ? mem_xcpt_uop_is_eret : ld_xcpt_uop_is_eret; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_sys_pc2epc = use_mem_xcpt ? mem_xcpt_uop_is_sys_pc2epc : ld_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_rocc = use_mem_xcpt ? mem_xcpt_uop_is_rocc : ld_xcpt_uop_is_rocc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_mov = use_mem_xcpt ? mem_xcpt_uop_is_mov : ld_xcpt_uop_is_mov; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_ftq_idx = use_mem_xcpt ? mem_xcpt_uop_ftq_idx : ld_xcpt_uop_ftq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_edge_inst = use_mem_xcpt ? mem_xcpt_uop_edge_inst : ld_xcpt_uop_edge_inst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_pc_lob = use_mem_xcpt ? mem_xcpt_uop_pc_lob : ld_xcpt_uop_pc_lob; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_taken = use_mem_xcpt ? mem_xcpt_uop_taken : ld_xcpt_uop_taken; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_imm_rename = use_mem_xcpt ? mem_xcpt_uop_imm_rename : ld_xcpt_uop_imm_rename; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_imm_sel = use_mem_xcpt ? mem_xcpt_uop_imm_sel : ld_xcpt_uop_imm_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_pimm = use_mem_xcpt ? mem_xcpt_uop_pimm : ld_xcpt_uop_pimm; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [19:0] xcpt_uop_imm_packed = use_mem_xcpt ? mem_xcpt_uop_imm_packed : ld_xcpt_uop_imm_packed; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_op1_sel = use_mem_xcpt ? mem_xcpt_uop_op1_sel : ld_xcpt_uop_op1_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_op2_sel = use_mem_xcpt ? mem_xcpt_uop_op2_sel : ld_xcpt_uop_op2_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ldst = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ldst : ld_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_wen = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_wen : ld_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ren1 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ren1 : ld_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ren2 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ren2 : ld_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ren3 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ren3 : ld_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_swap12 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_swap12 : ld_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_swap23 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_swap23 : ld_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_fp_ctrl_typeTagIn = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_typeTagIn : ld_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_fp_ctrl_typeTagOut = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_typeTagOut : ld_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_fromint = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_fromint : ld_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_toint = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_toint : ld_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_fastpipe = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_fastpipe : ld_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_fma = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_fma : ld_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_div = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_div : ld_xcpt_uop_fp_ctrl_div; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_sqrt = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_sqrt : ld_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_wflags = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_wflags : ld_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_vec = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_vec : ld_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_rob_idx = use_mem_xcpt ? mem_xcpt_uop_rob_idx : ld_xcpt_uop_rob_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [3:0] xcpt_uop_ldq_idx = use_mem_xcpt ? mem_xcpt_uop_ldq_idx : ld_xcpt_uop_ldq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [3:0] xcpt_uop_stq_idx = use_mem_xcpt ? mem_xcpt_uop_stq_idx : ld_xcpt_uop_stq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_rxq_idx = use_mem_xcpt ? mem_xcpt_uop_rxq_idx : ld_xcpt_uop_rxq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_pdst = use_mem_xcpt ? mem_xcpt_uop_pdst : ld_xcpt_uop_pdst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_prs1 = use_mem_xcpt ? mem_xcpt_uop_prs1 : ld_xcpt_uop_prs1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_prs2 = use_mem_xcpt ? mem_xcpt_uop_prs2 : ld_xcpt_uop_prs2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_prs3 = use_mem_xcpt ? mem_xcpt_uop_prs3 : ld_xcpt_uop_prs3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_ppred = use_mem_xcpt ? mem_xcpt_uop_ppred : ld_xcpt_uop_ppred; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_prs1_busy = use_mem_xcpt ? mem_xcpt_uop_prs1_busy : ld_xcpt_uop_prs1_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_prs2_busy = use_mem_xcpt ? mem_xcpt_uop_prs2_busy : ld_xcpt_uop_prs2_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_prs3_busy = use_mem_xcpt ? mem_xcpt_uop_prs3_busy : ld_xcpt_uop_prs3_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_ppred_busy = use_mem_xcpt ? mem_xcpt_uop_ppred_busy : ld_xcpt_uop_ppred_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_stale_pdst = use_mem_xcpt ? mem_xcpt_uop_stale_pdst : ld_xcpt_uop_stale_pdst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_exception = use_mem_xcpt ? mem_xcpt_uop_exception : ld_xcpt_uop_exception; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [63:0] xcpt_uop_exc_cause = use_mem_xcpt ? mem_xcpt_uop_exc_cause : ld_xcpt_uop_exc_cause; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_mem_cmd = use_mem_xcpt ? mem_xcpt_uop_mem_cmd : ld_xcpt_uop_mem_cmd; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_mem_size = use_mem_xcpt ? mem_xcpt_uop_mem_size : ld_xcpt_uop_mem_size; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_mem_signed = use_mem_xcpt ? mem_xcpt_uop_mem_signed : ld_xcpt_uop_mem_signed; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_uses_ldq = use_mem_xcpt ? mem_xcpt_uop_uses_ldq : ld_xcpt_uop_uses_ldq; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_uses_stq = use_mem_xcpt ? mem_xcpt_uop_uses_stq : ld_xcpt_uop_uses_stq; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_unique = use_mem_xcpt ? mem_xcpt_uop_is_unique : ld_xcpt_uop_is_unique; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_flush_on_commit = use_mem_xcpt ? mem_xcpt_uop_flush_on_commit : ld_xcpt_uop_flush_on_commit; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_csr_cmd = use_mem_xcpt ? mem_xcpt_uop_csr_cmd : ld_xcpt_uop_csr_cmd; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_ldst_is_rs1 = use_mem_xcpt ? mem_xcpt_uop_ldst_is_rs1 : ld_xcpt_uop_ldst_is_rs1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_ldst = use_mem_xcpt ? mem_xcpt_uop_ldst : ld_xcpt_uop_ldst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_lrs1 = use_mem_xcpt ? mem_xcpt_uop_lrs1 : ld_xcpt_uop_lrs1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_lrs2 = use_mem_xcpt ? mem_xcpt_uop_lrs2 : ld_xcpt_uop_lrs2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_lrs3 = use_mem_xcpt ? mem_xcpt_uop_lrs3 : ld_xcpt_uop_lrs3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_dst_rtype = use_mem_xcpt ? mem_xcpt_uop_dst_rtype : ld_xcpt_uop_dst_rtype; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_lrs1_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs1_rtype : ld_xcpt_uop_lrs1_rtype; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_lrs2_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs2_rtype : ld_xcpt_uop_lrs2_rtype; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_frs3_en = use_mem_xcpt ? mem_xcpt_uop_frs3_en : ld_xcpt_uop_frs3_en; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fcn_dw = use_mem_xcpt ? mem_xcpt_uop_fcn_dw : ld_xcpt_uop_fcn_dw; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_fcn_op = use_mem_xcpt ? mem_xcpt_uop_fcn_op : ld_xcpt_uop_fcn_op; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_val = use_mem_xcpt ? mem_xcpt_uop_fp_val : ld_xcpt_uop_fp_val; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_fp_rm = use_mem_xcpt ? mem_xcpt_uop_fp_rm : ld_xcpt_uop_fp_rm; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_fp_typ = use_mem_xcpt ? mem_xcpt_uop_fp_typ : ld_xcpt_uop_fp_typ; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_xcpt_pf_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_pf_if : ld_xcpt_uop_xcpt_pf_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_xcpt_ae_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ae_if : ld_xcpt_uop_xcpt_ae_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_xcpt_ma_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ma_if : ld_xcpt_uop_xcpt_ma_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_bp_debug_if = use_mem_xcpt ? mem_xcpt_uop_bp_debug_if : ld_xcpt_uop_bp_debug_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_bp_xcpt_if = use_mem_xcpt ? mem_xcpt_uop_bp_xcpt_if : ld_xcpt_uop_bp_xcpt_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_debug_fsrc = use_mem_xcpt ? mem_xcpt_uop_debug_fsrc : ld_xcpt_uop_debug_fsrc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_debug_tsrc = use_mem_xcpt ? mem_xcpt_uop_debug_tsrc : ld_xcpt_uop_debug_tsrc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire _r_xcpt_valid_T = ld_xcpt_valid | mem_xcpt_valid; // @[lsu.scala:457:29, :1437:66, :1444:34] wire [11:0] _r_xcpt_valid_T_1 = io_core_brupdate_b1_mispredict_mask_0 & xcpt_uop_br_mask; // @[util.scala:126:51] wire _r_xcpt_valid_T_2 = |_r_xcpt_valid_T_1; // @[util.scala:126:{51,59}] wire _r_xcpt_valid_T_3 = _r_xcpt_valid_T_2 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _r_xcpt_valid_T_4 = ~_r_xcpt_valid_T_3; // @[util.scala:61:61] wire _r_xcpt_valid_T_5 = _r_xcpt_valid_T & _r_xcpt_valid_T_4; // @[lsu.scala:1444:{34,53,56}] wire [11:0] _r_xcpt_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] wire [11:0] _r_xcpt_uop_br_mask_T_1 = xcpt_uop_br_mask & _r_xcpt_uop_br_mask_T; // @[util.scala:93:{25,27}] wire [4:0] _r_xcpt_cause_T = use_mem_xcpt ? {1'h0, mem_xcpt_cause} : 5'h10; // @[lsu.scala:458:29, :1440:115, :1447:28] wire [11:0] _io_core_lxcpt_valid_T = io_core_brupdate_b1_mispredict_mask_0 & r_xcpt_uop_br_mask; // @[util.scala:126:51] wire _io_core_lxcpt_valid_T_1 = |_io_core_lxcpt_valid_T; // @[util.scala:126:{51,59}] wire _io_core_lxcpt_valid_T_2 = _io_core_lxcpt_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_lxcpt_valid_T_3 = ~_io_core_lxcpt_valid_T_2; // @[util.scala:61:61] assign _io_core_lxcpt_valid_T_4 = r_xcpt_valid & _io_core_lxcpt_valid_T_3; // @[lsu.scala:1434:29, :1450:{39,42}] assign io_core_lxcpt_valid_0 = _io_core_lxcpt_valid_T_4; // @[lsu.scala:211:7, :1450:39] reg wakeupArbs_0_io_in_1_valid_REG; // @[lsu.scala:1458:47] wire _wakeupArbs_0_io_in_1_valid_T = fired_load_agen_exec_0 & wakeupArbs_0_io_in_1_valid_REG; // @[lsu.scala:321:49, :1457:69, :1458:47] wire _wakeupArbs_0_io_in_1_valid_T_2 = _wakeupArbs_0_io_in_1_valid_T; // @[lsu.scala:1457:69, :1458:69] wire _wakeupArbs_0_io_in_1_valid_T_3 = ~mem_incoming_uop_0_fp_val; // @[lsu.scala:1053:37, :1460:40] wire _wakeupArbs_0_io_in_1_valid_T_4 = _wakeupArbs_0_io_in_1_valid_T_2 & _wakeupArbs_0_io_in_1_valid_T_3; // @[lsu.scala:1458:69, :1459:69, :1460:40] wire [31:0] io_core_iresp_0_out_bits_uop_inst = iresp_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] io_core_iresp_0_out_bits_uop_debug_inst = iresp_0_bits_uop_debug_inst; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_rvc = iresp_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] io_core_iresp_0_out_bits_uop_debug_pc = iresp_0_bits_uop_debug_pc; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_0 = iresp_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_1 = iresp_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_2 = iresp_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_3 = iresp_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_0 = iresp_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_1 = iresp_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_2 = iresp_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_3 = iresp_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_4 = iresp_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_5 = iresp_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_6 = iresp_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_7 = iresp_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_8 = iresp_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_9 = iresp_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_issued = iresp_0_bits_uop_iw_issued; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_issued_partial_agen = iresp_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_issued_partial_dgen = iresp_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_iw_p1_speculative_child = iresp_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_iw_p2_speculative_child = iresp_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_p1_bypass_hint = iresp_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_p2_bypass_hint = iresp_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_p3_bypass_hint = iresp_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_dis_col_sel = iresp_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] io_core_iresp_0_out_bits_uop_br_tag = iresp_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] io_core_iresp_0_out_bits_uop_br_type = iresp_0_bits_uop_br_type; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_sfb = iresp_0_bits_uop_is_sfb; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_fence = iresp_0_bits_uop_is_fence; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_fencei = iresp_0_bits_uop_is_fencei; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_sfence = iresp_0_bits_uop_is_sfence; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_amo = iresp_0_bits_uop_is_amo; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_eret = iresp_0_bits_uop_is_eret; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_sys_pc2epc = iresp_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_rocc = iresp_0_bits_uop_is_rocc; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_mov = iresp_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_ftq_idx = iresp_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_edge_inst = iresp_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_pc_lob = iresp_0_bits_uop_pc_lob; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_taken = iresp_0_bits_uop_taken; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_imm_rename = iresp_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_imm_sel = iresp_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_pimm = iresp_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] io_core_iresp_0_out_bits_uop_imm_packed = iresp_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_op1_sel = iresp_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_op2_sel = iresp_0_bits_uop_op2_sel; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ldst = iresp_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_wen = iresp_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ren1 = iresp_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ren2 = iresp_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ren3 = iresp_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_swap12 = iresp_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_swap23 = iresp_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_fp_ctrl_typeTagIn = iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_fp_ctrl_typeTagOut = iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_fromint = iresp_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_toint = iresp_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_fastpipe = iresp_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_fma = iresp_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_div = iresp_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_sqrt = iresp_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_wflags = iresp_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_vec = iresp_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_rob_idx = iresp_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] io_core_iresp_0_out_bits_uop_ldq_idx = iresp_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] io_core_iresp_0_out_bits_uop_stq_idx = iresp_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_rxq_idx = iresp_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_pdst = iresp_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_prs1 = iresp_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_prs2 = iresp_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_prs3 = iresp_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_ppred = iresp_0_bits_uop_ppred; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_prs1_busy = iresp_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_prs2_busy = iresp_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_prs3_busy = iresp_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_ppred_busy = iresp_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_stale_pdst = iresp_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_exception = iresp_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] io_core_iresp_0_out_bits_uop_exc_cause = iresp_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_mem_cmd = iresp_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_mem_size = iresp_0_bits_uop_mem_size; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_mem_signed = iresp_0_bits_uop_mem_signed; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_uses_ldq = iresp_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_uses_stq = iresp_0_bits_uop_uses_stq; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_unique = iresp_0_bits_uop_is_unique; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_flush_on_commit = iresp_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_csr_cmd = iresp_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_ldst_is_rs1 = iresp_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_ldst = iresp_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_lrs1 = iresp_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_lrs2 = iresp_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_lrs3 = iresp_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_dst_rtype = iresp_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_lrs1_rtype = iresp_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_lrs2_rtype = iresp_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_frs3_en = iresp_0_bits_uop_frs3_en; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fcn_dw = iresp_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_fcn_op = iresp_0_bits_uop_fcn_op; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_val = iresp_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_fp_rm = iresp_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_fp_typ = iresp_0_bits_uop_fp_typ; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_xcpt_pf_if = iresp_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_xcpt_ae_if = iresp_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_xcpt_ma_if = iresp_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_bp_debug_if = iresp_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_bp_xcpt_if = iresp_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_debug_fsrc = iresp_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_debug_tsrc = iresp_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire [63:0] io_core_iresp_0_out_bits_data = iresp_0_bits_data; // @[util.scala:114:23] wire [11:0] iresp_0_bits_uop_br_mask; // @[lsu.scala:1477:19] wire iresp_0_valid; // @[lsu.scala:1477:19] assign io_core_fresp_0_valid_0 = fresp_0_valid; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_inst_0 = fresp_0_bits_uop_inst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_inst_0 = fresp_0_bits_uop_debug_inst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_rvc_0 = fresp_0_bits_uop_is_rvc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_pc_0 = fresp_0_bits_uop_debug_pc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_0_0 = fresp_0_bits_uop_iq_type_0; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_1_0 = fresp_0_bits_uop_iq_type_1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_2_0 = fresp_0_bits_uop_iq_type_2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_3_0 = fresp_0_bits_uop_iq_type_3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_0_0 = fresp_0_bits_uop_fu_code_0; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_1_0 = fresp_0_bits_uop_fu_code_1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_2_0 = fresp_0_bits_uop_fu_code_2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_3_0 = fresp_0_bits_uop_fu_code_3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_4_0 = fresp_0_bits_uop_fu_code_4; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_5_0 = fresp_0_bits_uop_fu_code_5; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_6_0 = fresp_0_bits_uop_fu_code_6; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_7_0 = fresp_0_bits_uop_fu_code_7; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_8_0 = fresp_0_bits_uop_fu_code_8; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_9_0 = fresp_0_bits_uop_fu_code_9; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_issued_0 = fresp_0_bits_uop_iw_issued; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_issued_partial_agen_0 = fresp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_issued_partial_dgen_0 = fresp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p1_speculative_child_0 = fresp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p2_speculative_child_0 = fresp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p1_bypass_hint_0 = fresp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p2_bypass_hint_0 = fresp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p3_bypass_hint_0 = fresp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_dis_col_sel_0 = fresp_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_br_mask_0 = fresp_0_bits_uop_br_mask; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_br_tag_0 = fresp_0_bits_uop_br_tag; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_br_type_0 = fresp_0_bits_uop_br_type; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_sfb_0 = fresp_0_bits_uop_is_sfb; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_fence_0 = fresp_0_bits_uop_is_fence; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_fencei_0 = fresp_0_bits_uop_is_fencei; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_sfence_0 = fresp_0_bits_uop_is_sfence; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_amo_0 = fresp_0_bits_uop_is_amo; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_eret_0 = fresp_0_bits_uop_is_eret; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_sys_pc2epc_0 = fresp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_rocc_0 = fresp_0_bits_uop_is_rocc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_mov_0 = fresp_0_bits_uop_is_mov; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ftq_idx_0 = fresp_0_bits_uop_ftq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_edge_inst_0 = fresp_0_bits_uop_edge_inst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_pc_lob_0 = fresp_0_bits_uop_pc_lob; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_taken_0 = fresp_0_bits_uop_taken; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_imm_rename_0 = fresp_0_bits_uop_imm_rename; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_imm_sel_0 = fresp_0_bits_uop_imm_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_pimm_0 = fresp_0_bits_uop_pimm; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_imm_packed_0 = fresp_0_bits_uop_imm_packed; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_op1_sel_0 = fresp_0_bits_uop_op1_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_op2_sel_0 = fresp_0_bits_uop_op2_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ldst_0 = fresp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_wen_0 = fresp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ren1_0 = fresp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ren2_0 = fresp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ren3_0 = fresp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_swap12_0 = fresp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_swap23_0 = fresp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn_0 = fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut_0 = fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_fromint_0 = fresp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_toint_0 = fresp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_fastpipe_0 = fresp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_fma_0 = fresp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_div_0 = fresp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_sqrt_0 = fresp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_wflags_0 = fresp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_vec_0 = fresp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_rob_idx_0 = fresp_0_bits_uop_rob_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ldq_idx_0 = fresp_0_bits_uop_ldq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_stq_idx_0 = fresp_0_bits_uop_stq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_rxq_idx_0 = fresp_0_bits_uop_rxq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_pdst_0 = fresp_0_bits_uop_pdst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs1_0 = fresp_0_bits_uop_prs1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs2_0 = fresp_0_bits_uop_prs2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs3_0 = fresp_0_bits_uop_prs3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ppred_0 = fresp_0_bits_uop_ppred; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs1_busy_0 = fresp_0_bits_uop_prs1_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs2_busy_0 = fresp_0_bits_uop_prs2_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs3_busy_0 = fresp_0_bits_uop_prs3_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ppred_busy_0 = fresp_0_bits_uop_ppred_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_stale_pdst_0 = fresp_0_bits_uop_stale_pdst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_exception_0 = fresp_0_bits_uop_exception; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_exc_cause_0 = fresp_0_bits_uop_exc_cause; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_mem_cmd_0 = fresp_0_bits_uop_mem_cmd; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_mem_size_0 = fresp_0_bits_uop_mem_size; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_mem_signed_0 = fresp_0_bits_uop_mem_signed; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_uses_ldq_0 = fresp_0_bits_uop_uses_ldq; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_uses_stq_0 = fresp_0_bits_uop_uses_stq; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_unique_0 = fresp_0_bits_uop_is_unique; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_flush_on_commit_0 = fresp_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_csr_cmd_0 = fresp_0_bits_uop_csr_cmd; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ldst_is_rs1_0 = fresp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ldst_0 = fresp_0_bits_uop_ldst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs1_0 = fresp_0_bits_uop_lrs1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs2_0 = fresp_0_bits_uop_lrs2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs3_0 = fresp_0_bits_uop_lrs3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_dst_rtype_0 = fresp_0_bits_uop_dst_rtype; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs1_rtype_0 = fresp_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs2_rtype_0 = fresp_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_frs3_en_0 = fresp_0_bits_uop_frs3_en; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fcn_dw_0 = fresp_0_bits_uop_fcn_dw; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fcn_op_0 = fresp_0_bits_uop_fcn_op; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_val_0 = fresp_0_bits_uop_fp_val; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_rm_0 = fresp_0_bits_uop_fp_rm; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_typ_0 = fresp_0_bits_uop_fp_typ; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_xcpt_pf_if_0 = fresp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_xcpt_ae_if_0 = fresp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_xcpt_ma_if_0 = fresp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_bp_debug_if_0 = fresp_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_bp_xcpt_if_0 = fresp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_fsrc_0 = fresp_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_tsrc_0 = fresp_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_data_0 = fresp_0_bits_data; // @[lsu.scala:211:7, :1478:19] wire _io_core_iresp_0_out_valid_T_4; // @[util.scala:116:31] wire [11:0] _io_core_iresp_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] io_core_iresp_0_out_bits_uop_br_mask; // @[util.scala:114:23] wire io_core_iresp_0_out_valid; // @[util.scala:114:23] wire [11:0] _io_core_iresp_0_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _io_core_iresp_0_out_bits_uop_br_mask_T_1 = iresp_0_bits_uop_br_mask & _io_core_iresp_0_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign io_core_iresp_0_out_bits_uop_br_mask = _io_core_iresp_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [11:0] _io_core_iresp_0_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & iresp_0_bits_uop_br_mask; // @[util.scala:126:51] wire _io_core_iresp_0_out_valid_T_1 = |_io_core_iresp_0_out_valid_T; // @[util.scala:126:{51,59}] wire _io_core_iresp_0_out_valid_T_2 = _io_core_iresp_0_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_iresp_0_out_valid_T_3 = ~_io_core_iresp_0_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _io_core_iresp_0_out_valid_T_4 = iresp_0_valid & _io_core_iresp_0_out_valid_T_3; // @[util.scala:116:{31,34}] assign io_core_iresp_0_out_valid = _io_core_iresp_0_out_valid_T_4; // @[util.scala:114:23, :116:31] reg io_core_iresp_0_REG_valid; // @[lsu.scala:1485:70] assign io_core_iresp_0_valid_0 = io_core_iresp_0_REG_valid; // @[lsu.scala:211:7, :1485:70] reg [31:0] io_core_iresp_0_REG_bits_uop_inst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_inst_0 = io_core_iresp_0_REG_bits_uop_inst; // @[lsu.scala:211:7, :1485:70] reg [31:0] io_core_iresp_0_REG_bits_uop_debug_inst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_inst_0 = io_core_iresp_0_REG_bits_uop_debug_inst; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_rvc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_rvc_0 = io_core_iresp_0_REG_bits_uop_is_rvc; // @[lsu.scala:211:7, :1485:70] reg [39:0] io_core_iresp_0_REG_bits_uop_debug_pc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_pc_0 = io_core_iresp_0_REG_bits_uop_debug_pc; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_0; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_0_0 = io_core_iresp_0_REG_bits_uop_iq_type_0; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_1_0 = io_core_iresp_0_REG_bits_uop_iq_type_1; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_2_0 = io_core_iresp_0_REG_bits_uop_iq_type_2; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_3_0 = io_core_iresp_0_REG_bits_uop_iq_type_3; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_0; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_0_0 = io_core_iresp_0_REG_bits_uop_fu_code_0; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_1_0 = io_core_iresp_0_REG_bits_uop_fu_code_1; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_2_0 = io_core_iresp_0_REG_bits_uop_fu_code_2; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_3_0 = io_core_iresp_0_REG_bits_uop_fu_code_3; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_4; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_4_0 = io_core_iresp_0_REG_bits_uop_fu_code_4; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_5; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_5_0 = io_core_iresp_0_REG_bits_uop_fu_code_5; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_6; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_6_0 = io_core_iresp_0_REG_bits_uop_fu_code_6; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_7; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_7_0 = io_core_iresp_0_REG_bits_uop_fu_code_7; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_8; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_8_0 = io_core_iresp_0_REG_bits_uop_fu_code_8; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_9; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_9_0 = io_core_iresp_0_REG_bits_uop_fu_code_9; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_issued; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_issued_0 = io_core_iresp_0_REG_bits_uop_iw_issued; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_issued_partial_agen_0 = io_core_iresp_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_issued_partial_dgen_0 = io_core_iresp_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p1_speculative_child_0 = io_core_iresp_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p2_speculative_child_0 = io_core_iresp_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p1_bypass_hint_0 = io_core_iresp_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p2_bypass_hint_0 = io_core_iresp_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p3_bypass_hint_0 = io_core_iresp_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_dis_col_sel_0 = io_core_iresp_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:211:7, :1485:70] reg [11:0] io_core_iresp_0_REG_bits_uop_br_mask; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_br_mask_0 = io_core_iresp_0_REG_bits_uop_br_mask; // @[lsu.scala:211:7, :1485:70] reg [3:0] io_core_iresp_0_REG_bits_uop_br_tag; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_br_tag_0 = io_core_iresp_0_REG_bits_uop_br_tag; // @[lsu.scala:211:7, :1485:70] reg [3:0] io_core_iresp_0_REG_bits_uop_br_type; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_br_type_0 = io_core_iresp_0_REG_bits_uop_br_type; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_sfb; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_sfb_0 = io_core_iresp_0_REG_bits_uop_is_sfb; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_fence; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_fence_0 = io_core_iresp_0_REG_bits_uop_is_fence; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_fencei; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_fencei_0 = io_core_iresp_0_REG_bits_uop_is_fencei; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_sfence; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_sfence_0 = io_core_iresp_0_REG_bits_uop_is_sfence; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_amo; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_amo_0 = io_core_iresp_0_REG_bits_uop_is_amo; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_eret; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_eret_0 = io_core_iresp_0_REG_bits_uop_is_eret; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_sys_pc2epc_0 = io_core_iresp_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_rocc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_rocc_0 = io_core_iresp_0_REG_bits_uop_is_rocc; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_mov; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_mov_0 = io_core_iresp_0_REG_bits_uop_is_mov; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_ftq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ftq_idx_0 = io_core_iresp_0_REG_bits_uop_ftq_idx; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_edge_inst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_edge_inst_0 = io_core_iresp_0_REG_bits_uop_edge_inst; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_pc_lob; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_pc_lob_0 = io_core_iresp_0_REG_bits_uop_pc_lob; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_taken; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_taken_0 = io_core_iresp_0_REG_bits_uop_taken; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_imm_rename; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_imm_rename_0 = io_core_iresp_0_REG_bits_uop_imm_rename; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_imm_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_imm_sel_0 = io_core_iresp_0_REG_bits_uop_imm_sel; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_pimm; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_pimm_0 = io_core_iresp_0_REG_bits_uop_pimm; // @[lsu.scala:211:7, :1485:70] reg [19:0] io_core_iresp_0_REG_bits_uop_imm_packed; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_imm_packed_0 = io_core_iresp_0_REG_bits_uop_imm_packed; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_op1_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_op1_sel_0 = io_core_iresp_0_REG_bits_uop_op1_sel; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_op2_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_op2_sel_0 = io_core_iresp_0_REG_bits_uop_op2_sel; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ldst_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_wen_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ren1_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ren2_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ren3_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_swap12_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_swap23_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_fromint_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_toint_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_fastpipe_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_fma_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_div_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_sqrt_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_wflags_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_vec_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_rob_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_rob_idx_0 = io_core_iresp_0_REG_bits_uop_rob_idx; // @[lsu.scala:211:7, :1485:70] reg [3:0] io_core_iresp_0_REG_bits_uop_ldq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ldq_idx_0 = io_core_iresp_0_REG_bits_uop_ldq_idx; // @[lsu.scala:211:7, :1485:70] reg [3:0] io_core_iresp_0_REG_bits_uop_stq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_stq_idx_0 = io_core_iresp_0_REG_bits_uop_stq_idx; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_rxq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_rxq_idx_0 = io_core_iresp_0_REG_bits_uop_rxq_idx; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_pdst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_pdst_0 = io_core_iresp_0_REG_bits_uop_pdst; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_prs1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs1_0 = io_core_iresp_0_REG_bits_uop_prs1; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_prs2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs2_0 = io_core_iresp_0_REG_bits_uop_prs2; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_prs3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs3_0 = io_core_iresp_0_REG_bits_uop_prs3; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_ppred; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ppred_0 = io_core_iresp_0_REG_bits_uop_ppred; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_prs1_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs1_busy_0 = io_core_iresp_0_REG_bits_uop_prs1_busy; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_prs2_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs2_busy_0 = io_core_iresp_0_REG_bits_uop_prs2_busy; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_prs3_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs3_busy_0 = io_core_iresp_0_REG_bits_uop_prs3_busy; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_ppred_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ppred_busy_0 = io_core_iresp_0_REG_bits_uop_ppred_busy; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_stale_pdst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_stale_pdst_0 = io_core_iresp_0_REG_bits_uop_stale_pdst; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_exception; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_exception_0 = io_core_iresp_0_REG_bits_uop_exception; // @[lsu.scala:211:7, :1485:70] reg [63:0] io_core_iresp_0_REG_bits_uop_exc_cause; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_exc_cause_0 = io_core_iresp_0_REG_bits_uop_exc_cause; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_mem_cmd; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_mem_cmd_0 = io_core_iresp_0_REG_bits_uop_mem_cmd; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_mem_size; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_mem_size_0 = io_core_iresp_0_REG_bits_uop_mem_size; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_mem_signed; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_mem_signed_0 = io_core_iresp_0_REG_bits_uop_mem_signed; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_uses_ldq; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_uses_ldq_0 = io_core_iresp_0_REG_bits_uop_uses_ldq; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_uses_stq; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_uses_stq_0 = io_core_iresp_0_REG_bits_uop_uses_stq; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_unique; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_unique_0 = io_core_iresp_0_REG_bits_uop_is_unique; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_flush_on_commit_0 = io_core_iresp_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_csr_cmd; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_csr_cmd_0 = io_core_iresp_0_REG_bits_uop_csr_cmd; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ldst_is_rs1_0 = io_core_iresp_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_ldst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ldst_0 = io_core_iresp_0_REG_bits_uop_ldst; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_lrs1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs1_0 = io_core_iresp_0_REG_bits_uop_lrs1; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_lrs2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs2_0 = io_core_iresp_0_REG_bits_uop_lrs2; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_lrs3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs3_0 = io_core_iresp_0_REG_bits_uop_lrs3; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_dst_rtype; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_dst_rtype_0 = io_core_iresp_0_REG_bits_uop_dst_rtype; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs1_rtype_0 = io_core_iresp_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs2_rtype_0 = io_core_iresp_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_frs3_en; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_frs3_en_0 = io_core_iresp_0_REG_bits_uop_frs3_en; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fcn_dw; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fcn_dw_0 = io_core_iresp_0_REG_bits_uop_fcn_dw; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_fcn_op; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fcn_op_0 = io_core_iresp_0_REG_bits_uop_fcn_op; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_val; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_val_0 = io_core_iresp_0_REG_bits_uop_fp_val; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_fp_rm; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_rm_0 = io_core_iresp_0_REG_bits_uop_fp_rm; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_fp_typ; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_typ_0 = io_core_iresp_0_REG_bits_uop_fp_typ; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_xcpt_pf_if_0 = io_core_iresp_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_xcpt_ae_if_0 = io_core_iresp_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_xcpt_ma_if_0 = io_core_iresp_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_bp_debug_if_0 = io_core_iresp_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_bp_xcpt_if_0 = io_core_iresp_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_fsrc_0 = io_core_iresp_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_tsrc_0 = io_core_iresp_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:211:7, :1485:70] reg [63:0] io_core_iresp_0_REG_bits_data; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_data_0 = io_core_iresp_0_REG_bits_data; // @[lsu.scala:211:7, :1485:70] wire wb_spec_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1491:29] wire [31:0] wb_spec_wakeups_0_bits_uop_inst; // @[lsu.scala:1491:29] wire [31:0] wb_spec_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1491:29] wire [39:0] wb_spec_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1491:29] wire [11:0] wb_spec_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1491:29] wire [3:0] wb_spec_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1491:29] wire [3:0] wb_spec_wakeups_0_bits_uop_br_type; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_taken; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_pimm; // @[lsu.scala:1491:29] wire [19:0] wb_spec_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1491:29] wire [3:0] wb_spec_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1491:29] wire [3:0] wb_spec_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_pdst; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_prs1; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_prs2; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_prs3; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_ppred; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_exception; // @[lsu.scala:1491:29] wire [63:0] wb_spec_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_ldst; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_valid; // @[lsu.scala:1491:29] wire spec_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1492:26] wire [31:0] spec_wakeups_0_bits_uop_inst; // @[lsu.scala:1492:26] wire [31:0] spec_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1492:26] wire [39:0] spec_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1492:26] wire [11:0] spec_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1492:26] wire [3:0] spec_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1492:26] wire [3:0] spec_wakeups_0_bits_uop_br_type; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_taken; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_pimm; // @[lsu.scala:1492:26] wire [19:0] spec_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1492:26] wire [3:0] spec_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1492:26] wire [3:0] spec_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_pdst; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_prs1; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_prs2; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_prs3; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_ppred; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_exception; // @[lsu.scala:1492:26] wire [63:0] spec_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_ldst; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_bypassable; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_speculative_mask; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_rebusy; // @[lsu.scala:1492:26] wire spec_wakeups_0_valid; // @[lsu.scala:1492:26] wire [31:0] slow_wakeups_0_out_bits_uop_inst = wb_slow_wakeups_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] slow_wakeups_0_out_bits_uop_debug_inst = wb_slow_wakeups_0_bits_uop_debug_inst; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_rvc = wb_slow_wakeups_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] slow_wakeups_0_out_bits_uop_debug_pc = wb_slow_wakeups_0_bits_uop_debug_pc; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_0 = wb_slow_wakeups_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_1 = wb_slow_wakeups_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_2 = wb_slow_wakeups_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_3 = wb_slow_wakeups_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_0 = wb_slow_wakeups_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_1 = wb_slow_wakeups_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_2 = wb_slow_wakeups_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_3 = wb_slow_wakeups_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_4 = wb_slow_wakeups_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_5 = wb_slow_wakeups_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_6 = wb_slow_wakeups_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_7 = wb_slow_wakeups_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_8 = wb_slow_wakeups_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_9 = wb_slow_wakeups_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_issued = wb_slow_wakeups_0_bits_uop_iw_issued; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_issued_partial_agen = wb_slow_wakeups_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_issued_partial_dgen = wb_slow_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_iw_p1_speculative_child = wb_slow_wakeups_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_iw_p2_speculative_child = wb_slow_wakeups_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_p1_bypass_hint = wb_slow_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_p2_bypass_hint = wb_slow_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_p3_bypass_hint = wb_slow_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_dis_col_sel = wb_slow_wakeups_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] slow_wakeups_0_out_bits_uop_br_tag = wb_slow_wakeups_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] slow_wakeups_0_out_bits_uop_br_type = wb_slow_wakeups_0_bits_uop_br_type; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_sfb = wb_slow_wakeups_0_bits_uop_is_sfb; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_fence = wb_slow_wakeups_0_bits_uop_is_fence; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_fencei = wb_slow_wakeups_0_bits_uop_is_fencei; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_sfence = wb_slow_wakeups_0_bits_uop_is_sfence; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_amo = wb_slow_wakeups_0_bits_uop_is_amo; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_eret = wb_slow_wakeups_0_bits_uop_is_eret; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_sys_pc2epc = wb_slow_wakeups_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_rocc = wb_slow_wakeups_0_bits_uop_is_rocc; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_mov = wb_slow_wakeups_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_ftq_idx = wb_slow_wakeups_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_edge_inst = wb_slow_wakeups_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_pc_lob = wb_slow_wakeups_0_bits_uop_pc_lob; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_taken = wb_slow_wakeups_0_bits_uop_taken; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_imm_rename = wb_slow_wakeups_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_imm_sel = wb_slow_wakeups_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_pimm = wb_slow_wakeups_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] slow_wakeups_0_out_bits_uop_imm_packed = wb_slow_wakeups_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_op1_sel = wb_slow_wakeups_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_op2_sel = wb_slow_wakeups_0_bits_uop_op2_sel; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ldst = wb_slow_wakeups_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_wen = wb_slow_wakeups_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ren1 = wb_slow_wakeups_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ren2 = wb_slow_wakeups_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ren3 = wb_slow_wakeups_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_swap12 = wb_slow_wakeups_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_swap23 = wb_slow_wakeups_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_fp_ctrl_typeTagIn = wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_fp_ctrl_typeTagOut = wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_fromint = wb_slow_wakeups_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_toint = wb_slow_wakeups_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_fastpipe = wb_slow_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_fma = wb_slow_wakeups_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_div = wb_slow_wakeups_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_sqrt = wb_slow_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_wflags = wb_slow_wakeups_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_vec = wb_slow_wakeups_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_rob_idx = wb_slow_wakeups_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [3:0] slow_wakeups_0_out_bits_uop_ldq_idx = wb_slow_wakeups_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [3:0] slow_wakeups_0_out_bits_uop_stq_idx = wb_slow_wakeups_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_rxq_idx = wb_slow_wakeups_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_pdst = wb_slow_wakeups_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_prs1 = wb_slow_wakeups_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_prs2 = wb_slow_wakeups_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_prs3 = wb_slow_wakeups_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_ppred = wb_slow_wakeups_0_bits_uop_ppred; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_prs1_busy = wb_slow_wakeups_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_prs2_busy = wb_slow_wakeups_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_prs3_busy = wb_slow_wakeups_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_ppred_busy = wb_slow_wakeups_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_stale_pdst = wb_slow_wakeups_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_exception = wb_slow_wakeups_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] slow_wakeups_0_out_bits_uop_exc_cause = wb_slow_wakeups_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_mem_cmd = wb_slow_wakeups_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_mem_size = wb_slow_wakeups_0_bits_uop_mem_size; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_mem_signed = wb_slow_wakeups_0_bits_uop_mem_signed; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_uses_ldq = wb_slow_wakeups_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_uses_stq = wb_slow_wakeups_0_bits_uop_uses_stq; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_unique = wb_slow_wakeups_0_bits_uop_is_unique; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_flush_on_commit = wb_slow_wakeups_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_csr_cmd = wb_slow_wakeups_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_ldst_is_rs1 = wb_slow_wakeups_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_ldst = wb_slow_wakeups_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_lrs1 = wb_slow_wakeups_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_lrs2 = wb_slow_wakeups_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_lrs3 = wb_slow_wakeups_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_dst_rtype = wb_slow_wakeups_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_lrs1_rtype = wb_slow_wakeups_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_lrs2_rtype = wb_slow_wakeups_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_frs3_en = wb_slow_wakeups_0_bits_uop_frs3_en; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fcn_dw = wb_slow_wakeups_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_fcn_op = wb_slow_wakeups_0_bits_uop_fcn_op; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_val = wb_slow_wakeups_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_fp_rm = wb_slow_wakeups_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_fp_typ = wb_slow_wakeups_0_bits_uop_fp_typ; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_xcpt_pf_if = wb_slow_wakeups_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_xcpt_ae_if = wb_slow_wakeups_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_xcpt_ma_if = wb_slow_wakeups_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_bp_debug_if = wb_slow_wakeups_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_bp_xcpt_if = wb_slow_wakeups_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_debug_fsrc = wb_slow_wakeups_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_debug_tsrc = wb_slow_wakeups_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire [11:0] wb_slow_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_valid; // @[lsu.scala:1494:29] wire slow_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1495:26] wire [31:0] slow_wakeups_0_bits_uop_inst; // @[lsu.scala:1495:26] wire [31:0] slow_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1495:26] wire [39:0] slow_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1495:26] wire [11:0] slow_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1495:26] wire [3:0] slow_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1495:26] wire [3:0] slow_wakeups_0_bits_uop_br_type; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_taken; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_pimm; // @[lsu.scala:1495:26] wire [19:0] slow_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1495:26] wire [3:0] slow_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1495:26] wire [3:0] slow_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_pdst; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_prs1; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_prs2; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_prs3; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_ppred; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_exception; // @[lsu.scala:1495:26] wire [63:0] slow_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_ldst; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1495:26] wire dmem_resp_fired_0; // @[lsu.scala:1497:33] reg w1_valid; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_valid = w1_valid; // @[lsu.scala:1491:29, :1499:17] reg [31:0] w1_bits_uop_inst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_inst = w1_bits_uop_inst; // @[lsu.scala:1491:29, :1499:17] wire [31:0] w2_bits_out_uop_inst = w1_bits_uop_inst; // @[util.scala:109:23] reg [31:0] w1_bits_uop_debug_inst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_inst = w1_bits_uop_debug_inst; // @[lsu.scala:1491:29, :1499:17] wire [31:0] w2_bits_out_uop_debug_inst = w1_bits_uop_debug_inst; // @[util.scala:109:23] reg w1_bits_uop_is_rvc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_rvc = w1_bits_uop_is_rvc; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_rvc = w1_bits_uop_is_rvc; // @[util.scala:109:23] reg [39:0] w1_bits_uop_debug_pc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_pc = w1_bits_uop_debug_pc; // @[lsu.scala:1491:29, :1499:17] wire [39:0] w2_bits_out_uop_debug_pc = w1_bits_uop_debug_pc; // @[util.scala:109:23] reg w1_bits_uop_iq_type_0; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_0 = w1_bits_uop_iq_type_0; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_0 = w1_bits_uop_iq_type_0; // @[util.scala:109:23] reg w1_bits_uop_iq_type_1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_1 = w1_bits_uop_iq_type_1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_1 = w1_bits_uop_iq_type_1; // @[util.scala:109:23] reg w1_bits_uop_iq_type_2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_2 = w1_bits_uop_iq_type_2; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_2 = w1_bits_uop_iq_type_2; // @[util.scala:109:23] reg w1_bits_uop_iq_type_3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_3 = w1_bits_uop_iq_type_3; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_3 = w1_bits_uop_iq_type_3; // @[util.scala:109:23] reg w1_bits_uop_fu_code_0; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_0 = w1_bits_uop_fu_code_0; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_0 = w1_bits_uop_fu_code_0; // @[util.scala:109:23] reg w1_bits_uop_fu_code_1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_1 = w1_bits_uop_fu_code_1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_1 = w1_bits_uop_fu_code_1; // @[util.scala:109:23] reg w1_bits_uop_fu_code_2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_2 = w1_bits_uop_fu_code_2; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_2 = w1_bits_uop_fu_code_2; // @[util.scala:109:23] reg w1_bits_uop_fu_code_3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_3 = w1_bits_uop_fu_code_3; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_3 = w1_bits_uop_fu_code_3; // @[util.scala:109:23] reg w1_bits_uop_fu_code_4; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_4 = w1_bits_uop_fu_code_4; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_4 = w1_bits_uop_fu_code_4; // @[util.scala:109:23] reg w1_bits_uop_fu_code_5; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_5 = w1_bits_uop_fu_code_5; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_5 = w1_bits_uop_fu_code_5; // @[util.scala:109:23] reg w1_bits_uop_fu_code_6; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_6 = w1_bits_uop_fu_code_6; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_6 = w1_bits_uop_fu_code_6; // @[util.scala:109:23] reg w1_bits_uop_fu_code_7; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_7 = w1_bits_uop_fu_code_7; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_7 = w1_bits_uop_fu_code_7; // @[util.scala:109:23] reg w1_bits_uop_fu_code_8; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_8 = w1_bits_uop_fu_code_8; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_8 = w1_bits_uop_fu_code_8; // @[util.scala:109:23] reg w1_bits_uop_fu_code_9; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_9 = w1_bits_uop_fu_code_9; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_9 = w1_bits_uop_fu_code_9; // @[util.scala:109:23] reg w1_bits_uop_iw_issued; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_issued = w1_bits_uop_iw_issued; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_issued = w1_bits_uop_iw_issued; // @[util.scala:109:23] reg w1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_issued_partial_agen = w1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_issued_partial_agen = w1_bits_uop_iw_issued_partial_agen; // @[util.scala:109:23] reg w1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_issued_partial_dgen = w1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_issued_partial_dgen = w1_bits_uop_iw_issued_partial_dgen; // @[util.scala:109:23] reg [1:0] w1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p1_speculative_child = w1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_iw_p1_speculative_child = w1_bits_uop_iw_p1_speculative_child; // @[util.scala:109:23] reg [1:0] w1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p2_speculative_child = w1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_iw_p2_speculative_child = w1_bits_uop_iw_p2_speculative_child; // @[util.scala:109:23] reg w1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p1_bypass_hint = w1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_p1_bypass_hint = w1_bits_uop_iw_p1_bypass_hint; // @[util.scala:109:23] reg w1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p2_bypass_hint = w1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_p2_bypass_hint = w1_bits_uop_iw_p2_bypass_hint; // @[util.scala:109:23] reg w1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p3_bypass_hint = w1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_p3_bypass_hint = w1_bits_uop_iw_p3_bypass_hint; // @[util.scala:109:23] reg [1:0] w1_bits_uop_dis_col_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_dis_col_sel = w1_bits_uop_dis_col_sel; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_dis_col_sel = w1_bits_uop_dis_col_sel; // @[util.scala:109:23] reg [11:0] w1_bits_uop_br_mask; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_br_mask = w1_bits_uop_br_mask; // @[lsu.scala:1491:29, :1499:17] reg [3:0] w1_bits_uop_br_tag; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_br_tag = w1_bits_uop_br_tag; // @[lsu.scala:1491:29, :1499:17] wire [3:0] w2_bits_out_uop_br_tag = w1_bits_uop_br_tag; // @[util.scala:109:23] reg [3:0] w1_bits_uop_br_type; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_br_type = w1_bits_uop_br_type; // @[lsu.scala:1491:29, :1499:17] wire [3:0] w2_bits_out_uop_br_type = w1_bits_uop_br_type; // @[util.scala:109:23] reg w1_bits_uop_is_sfb; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_sfb = w1_bits_uop_is_sfb; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_sfb = w1_bits_uop_is_sfb; // @[util.scala:109:23] reg w1_bits_uop_is_fence; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_fence = w1_bits_uop_is_fence; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_fence = w1_bits_uop_is_fence; // @[util.scala:109:23] reg w1_bits_uop_is_fencei; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_fencei = w1_bits_uop_is_fencei; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_fencei = w1_bits_uop_is_fencei; // @[util.scala:109:23] reg w1_bits_uop_is_sfence; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_sfence = w1_bits_uop_is_sfence; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_sfence = w1_bits_uop_is_sfence; // @[util.scala:109:23] reg w1_bits_uop_is_amo; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_amo = w1_bits_uop_is_amo; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_amo = w1_bits_uop_is_amo; // @[util.scala:109:23] reg w1_bits_uop_is_eret; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_eret = w1_bits_uop_is_eret; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_eret = w1_bits_uop_is_eret; // @[util.scala:109:23] reg w1_bits_uop_is_sys_pc2epc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_sys_pc2epc = w1_bits_uop_is_sys_pc2epc; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_sys_pc2epc = w1_bits_uop_is_sys_pc2epc; // @[util.scala:109:23] reg w1_bits_uop_is_rocc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_rocc = w1_bits_uop_is_rocc; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_rocc = w1_bits_uop_is_rocc; // @[util.scala:109:23] reg w1_bits_uop_is_mov; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_mov = w1_bits_uop_is_mov; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_mov = w1_bits_uop_is_mov; // @[util.scala:109:23] reg [4:0] w1_bits_uop_ftq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ftq_idx = w1_bits_uop_ftq_idx; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_ftq_idx = w1_bits_uop_ftq_idx; // @[util.scala:109:23] reg w1_bits_uop_edge_inst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_edge_inst = w1_bits_uop_edge_inst; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_edge_inst = w1_bits_uop_edge_inst; // @[util.scala:109:23] reg [5:0] w1_bits_uop_pc_lob; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_pc_lob = w1_bits_uop_pc_lob; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_pc_lob = w1_bits_uop_pc_lob; // @[util.scala:109:23] reg w1_bits_uop_taken; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_taken = w1_bits_uop_taken; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_taken = w1_bits_uop_taken; // @[util.scala:109:23] reg w1_bits_uop_imm_rename; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_imm_rename = w1_bits_uop_imm_rename; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_imm_rename = w1_bits_uop_imm_rename; // @[util.scala:109:23] reg [2:0] w1_bits_uop_imm_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_imm_sel = w1_bits_uop_imm_sel; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_imm_sel = w1_bits_uop_imm_sel; // @[util.scala:109:23] reg [4:0] w1_bits_uop_pimm; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_pimm = w1_bits_uop_pimm; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_pimm = w1_bits_uop_pimm; // @[util.scala:109:23] reg [19:0] w1_bits_uop_imm_packed; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_imm_packed = w1_bits_uop_imm_packed; // @[lsu.scala:1491:29, :1499:17] wire [19:0] w2_bits_out_uop_imm_packed = w1_bits_uop_imm_packed; // @[util.scala:109:23] reg [1:0] w1_bits_uop_op1_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_op1_sel = w1_bits_uop_op1_sel; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_op1_sel = w1_bits_uop_op1_sel; // @[util.scala:109:23] reg [2:0] w1_bits_uop_op2_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_op2_sel = w1_bits_uop_op2_sel; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_op2_sel = w1_bits_uop_op2_sel; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ldst = w1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ldst = w1_bits_uop_fp_ctrl_ldst; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_wen; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_wen = w1_bits_uop_fp_ctrl_wen; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_wen = w1_bits_uop_fp_ctrl_wen; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ren1 = w1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ren1 = w1_bits_uop_fp_ctrl_ren1; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ren2 = w1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ren2 = w1_bits_uop_fp_ctrl_ren2; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ren3 = w1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ren3 = w1_bits_uop_fp_ctrl_ren3; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_swap12 = w1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_swap12 = w1_bits_uop_fp_ctrl_swap12; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_swap23 = w1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_swap23 = w1_bits_uop_fp_ctrl_swap23; // @[util.scala:109:23] reg [1:0] w1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn = w1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_fp_ctrl_typeTagIn = w1_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23] reg [1:0] w1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut = w1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_fp_ctrl_typeTagOut = w1_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_fromint = w1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_fromint = w1_bits_uop_fp_ctrl_fromint; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_toint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_toint = w1_bits_uop_fp_ctrl_toint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_toint = w1_bits_uop_fp_ctrl_toint; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_fastpipe = w1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_fastpipe = w1_bits_uop_fp_ctrl_fastpipe; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_fma; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_fma = w1_bits_uop_fp_ctrl_fma; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_fma = w1_bits_uop_fp_ctrl_fma; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_div; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_div = w1_bits_uop_fp_ctrl_div; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_div = w1_bits_uop_fp_ctrl_div; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_sqrt = w1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_sqrt = w1_bits_uop_fp_ctrl_sqrt; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_wflags = w1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_wflags = w1_bits_uop_fp_ctrl_wflags; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_vec; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_vec = w1_bits_uop_fp_ctrl_vec; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_vec = w1_bits_uop_fp_ctrl_vec; // @[util.scala:109:23] reg [5:0] w1_bits_uop_rob_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_rob_idx = w1_bits_uop_rob_idx; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_rob_idx = w1_bits_uop_rob_idx; // @[util.scala:109:23] reg [3:0] w1_bits_uop_ldq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ldq_idx = w1_bits_uop_ldq_idx; // @[lsu.scala:1491:29, :1499:17] wire [3:0] w2_bits_out_uop_ldq_idx = w1_bits_uop_ldq_idx; // @[util.scala:109:23] reg [3:0] w1_bits_uop_stq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_stq_idx = w1_bits_uop_stq_idx; // @[lsu.scala:1491:29, :1499:17] wire [3:0] w2_bits_out_uop_stq_idx = w1_bits_uop_stq_idx; // @[util.scala:109:23] reg [1:0] w1_bits_uop_rxq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_rxq_idx = w1_bits_uop_rxq_idx; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_rxq_idx = w1_bits_uop_rxq_idx; // @[util.scala:109:23] reg [6:0] w1_bits_uop_pdst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_pdst = w1_bits_uop_pdst; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_pdst = w1_bits_uop_pdst; // @[util.scala:109:23] reg [6:0] w1_bits_uop_prs1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs1 = w1_bits_uop_prs1; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_prs1 = w1_bits_uop_prs1; // @[util.scala:109:23] reg [6:0] w1_bits_uop_prs2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs2 = w1_bits_uop_prs2; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_prs2 = w1_bits_uop_prs2; // @[util.scala:109:23] reg [6:0] w1_bits_uop_prs3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs3 = w1_bits_uop_prs3; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_prs3 = w1_bits_uop_prs3; // @[util.scala:109:23] reg [4:0] w1_bits_uop_ppred; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ppred = w1_bits_uop_ppred; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_ppred = w1_bits_uop_ppred; // @[util.scala:109:23] reg w1_bits_uop_prs1_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs1_busy = w1_bits_uop_prs1_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_prs1_busy = w1_bits_uop_prs1_busy; // @[util.scala:109:23] reg w1_bits_uop_prs2_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs2_busy = w1_bits_uop_prs2_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_prs2_busy = w1_bits_uop_prs2_busy; // @[util.scala:109:23] reg w1_bits_uop_prs3_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs3_busy = w1_bits_uop_prs3_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_prs3_busy = w1_bits_uop_prs3_busy; // @[util.scala:109:23] reg w1_bits_uop_ppred_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ppred_busy = w1_bits_uop_ppred_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_ppred_busy = w1_bits_uop_ppred_busy; // @[util.scala:109:23] reg [6:0] w1_bits_uop_stale_pdst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_stale_pdst = w1_bits_uop_stale_pdst; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_stale_pdst = w1_bits_uop_stale_pdst; // @[util.scala:109:23] reg w1_bits_uop_exception; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_exception = w1_bits_uop_exception; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_exception = w1_bits_uop_exception; // @[util.scala:109:23] reg [63:0] w1_bits_uop_exc_cause; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_exc_cause = w1_bits_uop_exc_cause; // @[lsu.scala:1491:29, :1499:17] wire [63:0] w2_bits_out_uop_exc_cause = w1_bits_uop_exc_cause; // @[util.scala:109:23] reg [4:0] w1_bits_uop_mem_cmd; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_mem_cmd = w1_bits_uop_mem_cmd; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_mem_cmd = w1_bits_uop_mem_cmd; // @[util.scala:109:23] reg [1:0] w1_bits_uop_mem_size; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_mem_size = w1_bits_uop_mem_size; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_mem_size = w1_bits_uop_mem_size; // @[util.scala:109:23] reg w1_bits_uop_mem_signed; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_mem_signed = w1_bits_uop_mem_signed; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_mem_signed = w1_bits_uop_mem_signed; // @[util.scala:109:23] reg w1_bits_uop_uses_ldq; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_uses_ldq = w1_bits_uop_uses_ldq; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_uses_ldq = w1_bits_uop_uses_ldq; // @[util.scala:109:23] reg w1_bits_uop_uses_stq; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_uses_stq = w1_bits_uop_uses_stq; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_uses_stq = w1_bits_uop_uses_stq; // @[util.scala:109:23] reg w1_bits_uop_is_unique; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_unique = w1_bits_uop_is_unique; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_unique = w1_bits_uop_is_unique; // @[util.scala:109:23] reg w1_bits_uop_flush_on_commit; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_flush_on_commit = w1_bits_uop_flush_on_commit; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_flush_on_commit = w1_bits_uop_flush_on_commit; // @[util.scala:109:23] reg [2:0] w1_bits_uop_csr_cmd; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_csr_cmd = w1_bits_uop_csr_cmd; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_csr_cmd = w1_bits_uop_csr_cmd; // @[util.scala:109:23] reg w1_bits_uop_ldst_is_rs1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ldst_is_rs1 = w1_bits_uop_ldst_is_rs1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_ldst_is_rs1 = w1_bits_uop_ldst_is_rs1; // @[util.scala:109:23] reg [5:0] w1_bits_uop_ldst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ldst = w1_bits_uop_ldst; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_ldst = w1_bits_uop_ldst; // @[util.scala:109:23] reg [5:0] w1_bits_uop_lrs1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs1 = w1_bits_uop_lrs1; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_lrs1 = w1_bits_uop_lrs1; // @[util.scala:109:23] reg [5:0] w1_bits_uop_lrs2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs2 = w1_bits_uop_lrs2; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_lrs2 = w1_bits_uop_lrs2; // @[util.scala:109:23] reg [5:0] w1_bits_uop_lrs3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs3 = w1_bits_uop_lrs3; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_lrs3 = w1_bits_uop_lrs3; // @[util.scala:109:23] reg [1:0] w1_bits_uop_dst_rtype; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_dst_rtype = w1_bits_uop_dst_rtype; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_dst_rtype = w1_bits_uop_dst_rtype; // @[util.scala:109:23] reg [1:0] w1_bits_uop_lrs1_rtype; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs1_rtype = w1_bits_uop_lrs1_rtype; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_lrs1_rtype = w1_bits_uop_lrs1_rtype; // @[util.scala:109:23] reg [1:0] w1_bits_uop_lrs2_rtype; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs2_rtype = w1_bits_uop_lrs2_rtype; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_lrs2_rtype = w1_bits_uop_lrs2_rtype; // @[util.scala:109:23] reg w1_bits_uop_frs3_en; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_frs3_en = w1_bits_uop_frs3_en; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_frs3_en = w1_bits_uop_frs3_en; // @[util.scala:109:23] reg w1_bits_uop_fcn_dw; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fcn_dw = w1_bits_uop_fcn_dw; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fcn_dw = w1_bits_uop_fcn_dw; // @[util.scala:109:23] reg [4:0] w1_bits_uop_fcn_op; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fcn_op = w1_bits_uop_fcn_op; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_fcn_op = w1_bits_uop_fcn_op; // @[util.scala:109:23] reg w1_bits_uop_fp_val; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_val = w1_bits_uop_fp_val; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_val = w1_bits_uop_fp_val; // @[util.scala:109:23] reg [2:0] w1_bits_uop_fp_rm; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_rm = w1_bits_uop_fp_rm; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_fp_rm = w1_bits_uop_fp_rm; // @[util.scala:109:23] reg [1:0] w1_bits_uop_fp_typ; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_typ = w1_bits_uop_fp_typ; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_fp_typ = w1_bits_uop_fp_typ; // @[util.scala:109:23] reg w1_bits_uop_xcpt_pf_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_xcpt_pf_if = w1_bits_uop_xcpt_pf_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_xcpt_pf_if = w1_bits_uop_xcpt_pf_if; // @[util.scala:109:23] reg w1_bits_uop_xcpt_ae_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_xcpt_ae_if = w1_bits_uop_xcpt_ae_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_xcpt_ae_if = w1_bits_uop_xcpt_ae_if; // @[util.scala:109:23] reg w1_bits_uop_xcpt_ma_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_xcpt_ma_if = w1_bits_uop_xcpt_ma_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_xcpt_ma_if = w1_bits_uop_xcpt_ma_if; // @[util.scala:109:23] reg w1_bits_uop_bp_debug_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_bp_debug_if = w1_bits_uop_bp_debug_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_bp_debug_if = w1_bits_uop_bp_debug_if; // @[util.scala:109:23] reg w1_bits_uop_bp_xcpt_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_bp_xcpt_if = w1_bits_uop_bp_xcpt_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_bp_xcpt_if = w1_bits_uop_bp_xcpt_if; // @[util.scala:109:23] reg [2:0] w1_bits_uop_debug_fsrc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_fsrc = w1_bits_uop_debug_fsrc; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_debug_fsrc = w1_bits_uop_debug_fsrc; // @[util.scala:109:23] reg [2:0] w1_bits_uop_debug_tsrc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_tsrc = w1_bits_uop_debug_tsrc; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_debug_tsrc = w1_bits_uop_debug_tsrc; // @[util.scala:109:23] wire _w1_valid_T = _wakeupArbs_0_io_in_1_ready & _wakeupArbs_0_io_in_1_valid_T_4; // @[Decoupled.scala:51:35] wire [11:0] _w1_valid_T_1 = io_core_brupdate_b1_mispredict_mask_0 & mem_incoming_uop_0_br_mask; // @[util.scala:126:51] wire _w1_valid_T_2 = |_w1_valid_T_1; // @[util.scala:126:{51,59}] wire _w1_valid_T_3 = _w1_valid_T_2 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _w1_valid_T_4 = ~_w1_valid_T_3; // @[util.scala:61:61] wire _w1_valid_T_5 = _w1_valid_T & _w1_valid_T_4; // @[Decoupled.scala:51:35] wire [11:0] _w1_bits_out_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] w1_bits_out_uop_br_mask; // @[util.scala:109:23] wire [11:0] _w1_bits_out_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _w1_bits_out_uop_br_mask_T_1 = mem_incoming_uop_0_br_mask & _w1_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign w1_bits_out_uop_br_mask = _w1_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] reg w2_valid; // @[lsu.scala:1503:17] assign spec_wakeups_0_valid = w2_valid; // @[lsu.scala:1492:26, :1503:17] reg [31:0] w2_bits_uop_inst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_inst = w2_bits_uop_inst; // @[lsu.scala:1492:26, :1503:17] reg [31:0] w2_bits_uop_debug_inst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_inst = w2_bits_uop_debug_inst; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_rvc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_rvc = w2_bits_uop_is_rvc; // @[lsu.scala:1492:26, :1503:17] reg [39:0] w2_bits_uop_debug_pc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_pc = w2_bits_uop_debug_pc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_0; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_0 = w2_bits_uop_iq_type_0; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_1 = w2_bits_uop_iq_type_1; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_2 = w2_bits_uop_iq_type_2; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_3 = w2_bits_uop_iq_type_3; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_0; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_0 = w2_bits_uop_fu_code_0; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_1 = w2_bits_uop_fu_code_1; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_2 = w2_bits_uop_fu_code_2; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_3 = w2_bits_uop_fu_code_3; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_4; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_4 = w2_bits_uop_fu_code_4; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_5; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_5 = w2_bits_uop_fu_code_5; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_6; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_6 = w2_bits_uop_fu_code_6; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_7; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_7 = w2_bits_uop_fu_code_7; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_8; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_8 = w2_bits_uop_fu_code_8; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_9; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_9 = w2_bits_uop_fu_code_9; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_issued; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_issued = w2_bits_uop_iw_issued; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_issued_partial_agen = w2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_issued_partial_dgen = w2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p1_speculative_child = w2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p2_speculative_child = w2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p1_bypass_hint = w2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p2_bypass_hint = w2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p3_bypass_hint = w2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_dis_col_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_dis_col_sel = w2_bits_uop_dis_col_sel; // @[lsu.scala:1492:26, :1503:17] reg [11:0] w2_bits_uop_br_mask; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_br_mask = w2_bits_uop_br_mask; // @[lsu.scala:1492:26, :1503:17] reg [3:0] w2_bits_uop_br_tag; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_br_tag = w2_bits_uop_br_tag; // @[lsu.scala:1492:26, :1503:17] reg [3:0] w2_bits_uop_br_type; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_br_type = w2_bits_uop_br_type; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_sfb; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_sfb = w2_bits_uop_is_sfb; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_fence; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_fence = w2_bits_uop_is_fence; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_fencei; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_fencei = w2_bits_uop_is_fencei; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_sfence; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_sfence = w2_bits_uop_is_sfence; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_amo; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_amo = w2_bits_uop_is_amo; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_eret; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_eret = w2_bits_uop_is_eret; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_sys_pc2epc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_sys_pc2epc = w2_bits_uop_is_sys_pc2epc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_rocc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_rocc = w2_bits_uop_is_rocc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_mov; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_mov = w2_bits_uop_is_mov; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_ftq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ftq_idx = w2_bits_uop_ftq_idx; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_edge_inst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_edge_inst = w2_bits_uop_edge_inst; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_pc_lob; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_pc_lob = w2_bits_uop_pc_lob; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_taken; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_taken = w2_bits_uop_taken; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_imm_rename; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_imm_rename = w2_bits_uop_imm_rename; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_imm_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_imm_sel = w2_bits_uop_imm_sel; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_pimm; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_pimm = w2_bits_uop_pimm; // @[lsu.scala:1492:26, :1503:17] reg [19:0] w2_bits_uop_imm_packed; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_imm_packed = w2_bits_uop_imm_packed; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_op1_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_op1_sel = w2_bits_uop_op1_sel; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_op2_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_op2_sel = w2_bits_uop_op2_sel; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ldst = w2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_wen; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_wen = w2_bits_uop_fp_ctrl_wen; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ren1 = w2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ren2 = w2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ren3 = w2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_swap12 = w2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_swap23 = w2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn = w2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut = w2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_fromint = w2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_toint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_toint = w2_bits_uop_fp_ctrl_toint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_fastpipe = w2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_fma; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_fma = w2_bits_uop_fp_ctrl_fma; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_div; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_div = w2_bits_uop_fp_ctrl_div; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_sqrt = w2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_wflags = w2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_vec; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_vec = w2_bits_uop_fp_ctrl_vec; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_rob_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_rob_idx = w2_bits_uop_rob_idx; // @[lsu.scala:1492:26, :1503:17] reg [3:0] w2_bits_uop_ldq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ldq_idx = w2_bits_uop_ldq_idx; // @[lsu.scala:1492:26, :1503:17] reg [3:0] w2_bits_uop_stq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_stq_idx = w2_bits_uop_stq_idx; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_rxq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_rxq_idx = w2_bits_uop_rxq_idx; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_pdst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_pdst = w2_bits_uop_pdst; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_prs1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs1 = w2_bits_uop_prs1; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_prs2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs2 = w2_bits_uop_prs2; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_prs3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs3 = w2_bits_uop_prs3; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_ppred; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ppred = w2_bits_uop_ppred; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_prs1_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs1_busy = w2_bits_uop_prs1_busy; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_prs2_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs2_busy = w2_bits_uop_prs2_busy; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_prs3_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs3_busy = w2_bits_uop_prs3_busy; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_ppred_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ppred_busy = w2_bits_uop_ppred_busy; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_stale_pdst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_stale_pdst = w2_bits_uop_stale_pdst; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_exception; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_exception = w2_bits_uop_exception; // @[lsu.scala:1492:26, :1503:17] reg [63:0] w2_bits_uop_exc_cause; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_exc_cause = w2_bits_uop_exc_cause; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_mem_cmd; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_mem_cmd = w2_bits_uop_mem_cmd; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_mem_size; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_mem_size = w2_bits_uop_mem_size; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_mem_signed; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_mem_signed = w2_bits_uop_mem_signed; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_uses_ldq; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_uses_ldq = w2_bits_uop_uses_ldq; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_uses_stq; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_uses_stq = w2_bits_uop_uses_stq; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_unique; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_unique = w2_bits_uop_is_unique; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_flush_on_commit; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_flush_on_commit = w2_bits_uop_flush_on_commit; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_csr_cmd; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_csr_cmd = w2_bits_uop_csr_cmd; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_ldst_is_rs1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ldst_is_rs1 = w2_bits_uop_ldst_is_rs1; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_ldst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ldst = w2_bits_uop_ldst; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_lrs1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs1 = w2_bits_uop_lrs1; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_lrs2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs2 = w2_bits_uop_lrs2; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_lrs3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs3 = w2_bits_uop_lrs3; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_dst_rtype; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_dst_rtype = w2_bits_uop_dst_rtype; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_lrs1_rtype; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs1_rtype = w2_bits_uop_lrs1_rtype; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_lrs2_rtype; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs2_rtype = w2_bits_uop_lrs2_rtype; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_frs3_en; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_frs3_en = w2_bits_uop_frs3_en; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fcn_dw; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fcn_dw = w2_bits_uop_fcn_dw; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_fcn_op; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fcn_op = w2_bits_uop_fcn_op; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_val; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_val = w2_bits_uop_fp_val; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_fp_rm; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_rm = w2_bits_uop_fp_rm; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_fp_typ; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_typ = w2_bits_uop_fp_typ; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_xcpt_pf_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_xcpt_pf_if = w2_bits_uop_xcpt_pf_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_xcpt_ae_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_xcpt_ae_if = w2_bits_uop_xcpt_ae_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_xcpt_ma_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_xcpt_ma_if = w2_bits_uop_xcpt_ma_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_bp_debug_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_bp_debug_if = w2_bits_uop_bp_debug_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_bp_xcpt_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_bp_xcpt_if = w2_bits_uop_bp_xcpt_if; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_debug_fsrc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_fsrc = w2_bits_uop_debug_fsrc; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_debug_tsrc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_tsrc = w2_bits_uop_debug_tsrc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_bypassable; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_bypassable = w2_bits_bypassable; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_speculative_mask; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_speculative_mask = w2_bits_speculative_mask; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_rebusy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_rebusy = w2_bits_rebusy; // @[lsu.scala:1492:26, :1503:17] wire [11:0] _w2_valid_T = io_core_brupdate_b1_mispredict_mask_0 & w1_bits_uop_br_mask; // @[util.scala:126:51] wire _w2_valid_T_1 = |_w2_valid_T; // @[util.scala:126:{51,59}] wire _w2_valid_T_2 = _w2_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _w2_valid_T_3 = ~_w2_valid_T_2; // @[util.scala:61:61] wire _w2_valid_T_4 = w1_valid & _w2_valid_T_3; // @[lsu.scala:1499:17, :1504:{26,29}] wire [11:0] _w2_bits_out_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] w2_bits_out_uop_br_mask; // @[util.scala:109:23] wire [11:0] _w2_bits_out_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _w2_bits_out_uop_br_mask_T_1 = w1_bits_uop_br_mask & _w2_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign w2_bits_out_uop_br_mask = _w2_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] wire _GEN_503 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0; // @[lsu.scala:211:7, :1520:44] wire _GEN_504 = _GEN_503 & io_dmem_nack_0_bits_uop_uses_ldq_0 & ~reset; // @[lsu.scala:211:7, :1520:44, :1522:55, :1523:15] wire _T_1159 = io_dmem_nack_0_bits_uop_stq_idx_0 < stq_execute_head ^ io_dmem_nack_0_bits_uop_stq_idx_0 < stq_head ^ stq_execute_head < stq_head; // @[util.scala:364:{52,58,64,72,78}] wire _GEN_505 = io_dmem_nack_0_bits_is_hella_0 | io_dmem_nack_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7, :895:40, :1520:44, :1522:55, :1527:86] assign stq_execute_queue_flush = io_dmem_nack_0_valid_0 & ~_GEN_505 & _T_1159 | ~_GEN_385 & _T_1139 & ~dmem_req_fire_0; // @[util.scala:364:{58,72}] wire _resp_T = ~io_dmem_resp_0_valid_0; // @[lsu.scala:211:7, :1534:20] wire _resp_T_1 = _resp_T; // @[lsu.scala:1534:{20,43}] wire [31:0] resp_uop_inst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_inst_0 : io_dmem_resp_0_bits_uop_inst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [31:0] resp_uop_debug_inst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_inst_0 : io_dmem_resp_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_rvc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_rvc_0 : io_dmem_resp_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [39:0] resp_uop_debug_pc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_pc_0 : io_dmem_resp_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_0 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_0_0 : io_dmem_resp_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_1_0 : io_dmem_resp_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_2_0 : io_dmem_resp_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_3_0 : io_dmem_resp_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_0 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_0_0 : io_dmem_resp_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_1_0 : io_dmem_resp_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_2_0 : io_dmem_resp_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_3_0 : io_dmem_resp_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_4 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_4_0 : io_dmem_resp_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_5 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_5_0 : io_dmem_resp_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_6 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_6_0 : io_dmem_resp_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_7 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_7_0 : io_dmem_resp_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_8 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_8_0 : io_dmem_resp_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_9 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_9_0 : io_dmem_resp_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_issued = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_issued_0 : io_dmem_resp_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_issued_partial_agen = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_issued_partial_agen_0 : io_dmem_resp_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_issued_partial_dgen = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen_0 : io_dmem_resp_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_iw_p1_speculative_child = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p1_speculative_child_0 : io_dmem_resp_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_iw_p2_speculative_child = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p2_speculative_child_0 : io_dmem_resp_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_p1_bypass_hint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint_0 : io_dmem_resp_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_p2_bypass_hint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint_0 : io_dmem_resp_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_p3_bypass_hint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint_0 : io_dmem_resp_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_dis_col_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_dis_col_sel_0 : io_dmem_resp_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [11:0] resp_uop_br_mask = _resp_T_1 ? io_dmem_ll_resp_bits_uop_br_mask_0 : io_dmem_resp_0_bits_uop_br_mask_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [3:0] resp_uop_br_tag = _resp_T_1 ? io_dmem_ll_resp_bits_uop_br_tag_0 : io_dmem_resp_0_bits_uop_br_tag_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [3:0] resp_uop_br_type = _resp_T_1 ? io_dmem_ll_resp_bits_uop_br_type_0 : io_dmem_resp_0_bits_uop_br_type_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_sfb = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_sfb_0 : io_dmem_resp_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_fence = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_fence_0 : io_dmem_resp_0_bits_uop_is_fence_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_fencei = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_fencei_0 : io_dmem_resp_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_sfence = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_sfence_0 : io_dmem_resp_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_amo = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_amo_0 : io_dmem_resp_0_bits_uop_is_amo_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_eret = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_eret_0 : io_dmem_resp_0_bits_uop_is_eret_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_sys_pc2epc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_sys_pc2epc_0 : io_dmem_resp_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_rocc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_rocc_0 : io_dmem_resp_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_mov = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_mov_0 : io_dmem_resp_0_bits_uop_is_mov_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_ftq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ftq_idx_0 : io_dmem_resp_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_edge_inst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_edge_inst_0 : io_dmem_resp_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_pc_lob = _resp_T_1 ? io_dmem_ll_resp_bits_uop_pc_lob_0 : io_dmem_resp_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_taken = _resp_T_1 ? io_dmem_ll_resp_bits_uop_taken_0 : io_dmem_resp_0_bits_uop_taken_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_imm_rename = _resp_T_1 ? io_dmem_ll_resp_bits_uop_imm_rename_0 : io_dmem_resp_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_imm_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_imm_sel_0 : io_dmem_resp_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_pimm = _resp_T_1 ? io_dmem_ll_resp_bits_uop_pimm_0 : io_dmem_resp_0_bits_uop_pimm_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [19:0] resp_uop_imm_packed = _resp_T_1 ? io_dmem_ll_resp_bits_uop_imm_packed_0 : io_dmem_resp_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_op1_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_op1_sel_0 : io_dmem_resp_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_op2_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_op2_sel_0 : io_dmem_resp_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ldst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ldst_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_wen = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_wen_0 : io_dmem_resp_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ren1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ren1_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ren2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ren2_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ren3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ren3_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_swap12 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_swap12_0 : io_dmem_resp_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_swap23 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_swap23_0 : io_dmem_resp_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_fp_ctrl_typeTagIn = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn_0 : io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_fp_ctrl_typeTagOut = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut_0 : io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_fromint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_fromint_0 : io_dmem_resp_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_toint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_toint_0 : io_dmem_resp_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_fastpipe = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe_0 : io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_fma = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_fma_0 : io_dmem_resp_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_div = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_div_0 : io_dmem_resp_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_sqrt = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt_0 : io_dmem_resp_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_wflags = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_wflags_0 : io_dmem_resp_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_vec = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_vec_0 : io_dmem_resp_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_rob_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_rob_idx_0 : io_dmem_resp_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [3:0] resp_uop_ldq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ldq_idx_0 : io_dmem_resp_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [3:0] resp_uop_stq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_stq_idx_0 : io_dmem_resp_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_rxq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_rxq_idx_0 : io_dmem_resp_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_pdst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_pdst_0 : io_dmem_resp_0_bits_uop_pdst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_prs1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs1_0 : io_dmem_resp_0_bits_uop_prs1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_prs2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs2_0 : io_dmem_resp_0_bits_uop_prs2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_prs3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs3_0 : io_dmem_resp_0_bits_uop_prs3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_ppred = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ppred_0 : io_dmem_resp_0_bits_uop_ppred_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_prs1_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs1_busy_0 : io_dmem_resp_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_prs2_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs2_busy_0 : io_dmem_resp_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_prs3_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs3_busy_0 : io_dmem_resp_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_ppred_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ppred_busy_0 : io_dmem_resp_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_stale_pdst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_stale_pdst_0 : io_dmem_resp_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_exception = _resp_T_1 ? io_dmem_ll_resp_bits_uop_exception_0 : io_dmem_resp_0_bits_uop_exception_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [63:0] resp_uop_exc_cause = _resp_T_1 ? io_dmem_ll_resp_bits_uop_exc_cause_0 : io_dmem_resp_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_mem_cmd = _resp_T_1 ? io_dmem_ll_resp_bits_uop_mem_cmd_0 : io_dmem_resp_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_mem_size = _resp_T_1 ? io_dmem_ll_resp_bits_uop_mem_size_0 : io_dmem_resp_0_bits_uop_mem_size_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_mem_signed = _resp_T_1 ? io_dmem_ll_resp_bits_uop_mem_signed_0 : io_dmem_resp_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_uses_ldq = _resp_T_1 ? io_dmem_ll_resp_bits_uop_uses_ldq_0 : io_dmem_resp_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_uses_stq = _resp_T_1 ? io_dmem_ll_resp_bits_uop_uses_stq_0 : io_dmem_resp_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_unique = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_unique_0 : io_dmem_resp_0_bits_uop_is_unique_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_flush_on_commit = _resp_T_1 ? io_dmem_ll_resp_bits_uop_flush_on_commit_0 : io_dmem_resp_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_csr_cmd = _resp_T_1 ? io_dmem_ll_resp_bits_uop_csr_cmd_0 : io_dmem_resp_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_ldst_is_rs1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ldst_is_rs1_0 : io_dmem_resp_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_ldst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ldst_0 : io_dmem_resp_0_bits_uop_ldst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_lrs1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs1_0 : io_dmem_resp_0_bits_uop_lrs1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_lrs2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs2_0 : io_dmem_resp_0_bits_uop_lrs2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_lrs3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs3_0 : io_dmem_resp_0_bits_uop_lrs3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_dst_rtype = _resp_T_1 ? io_dmem_ll_resp_bits_uop_dst_rtype_0 : io_dmem_resp_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_lrs1_rtype = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs1_rtype_0 : io_dmem_resp_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_lrs2_rtype = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs2_rtype_0 : io_dmem_resp_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_frs3_en = _resp_T_1 ? io_dmem_ll_resp_bits_uop_frs3_en_0 : io_dmem_resp_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fcn_dw = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fcn_dw_0 : io_dmem_resp_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_fcn_op = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fcn_op_0 : io_dmem_resp_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_val = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_val_0 : io_dmem_resp_0_bits_uop_fp_val_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_fp_rm = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_rm_0 : io_dmem_resp_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_fp_typ = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_typ_0 : io_dmem_resp_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_xcpt_pf_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_xcpt_pf_if_0 : io_dmem_resp_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_xcpt_ae_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_xcpt_ae_if_0 : io_dmem_resp_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_xcpt_ma_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_xcpt_ma_if_0 : io_dmem_resp_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_bp_debug_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_bp_debug_if_0 : io_dmem_resp_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_bp_xcpt_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_bp_xcpt_if_0 : io_dmem_resp_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_debug_fsrc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_fsrc_0 : io_dmem_resp_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_debug_tsrc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_tsrc_0 : io_dmem_resp_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [63:0] resp_data = _resp_T_1 ? io_dmem_ll_resp_bits_data_0 : io_dmem_resp_0_bits_data_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_is_hella = _resp_T_1 ? io_dmem_ll_resp_bits_is_hella_0 : io_dmem_resp_0_bits_is_hella_0; // @[lsu.scala:211:7, :1534:{19,43}] wire _io_dmem_ll_resp_ready_T = ~io_dmem_resp_0_valid_0; // @[lsu.scala:211:7, :1534:20, :1537:32] wire _io_dmem_ll_resp_ready_T_1 = ~wb_spec_wakeups_0_valid; // @[lsu.scala:1491:29, :1537:58] assign _io_dmem_ll_resp_ready_T_2 = _io_dmem_ll_resp_ready_T & _io_dmem_ll_resp_ready_T_1; // @[lsu.scala:1537:{32,55,58}] assign io_dmem_ll_resp_ready_0 = _io_dmem_ll_resp_ready_T_2; // @[lsu.scala:211:7, :1537:55] wire _T_1507 = io_dmem_ll_resp_ready_0 & io_dmem_ll_resp_valid_0; // @[Decoupled.scala:51:35] wire _T_1162 = io_dmem_resp_0_valid_0 | _T_1507; // @[Decoupled.scala:51:35] wire _GEN_506 = _T_1162 & resp_uop_uses_ldq; // @[lsu.scala:1534:19, :1539:33, :1540:32] wire uop_iq_type_0; // @[lsu.scala:1543:27] wire uop_iq_type_1; // @[lsu.scala:1543:27] wire uop_iq_type_2; // @[lsu.scala:1543:27] wire uop_iq_type_3; // @[lsu.scala:1543:27] wire uop_fu_code_0; // @[lsu.scala:1543:27] wire uop_fu_code_1; // @[lsu.scala:1543:27] wire uop_fu_code_2; // @[lsu.scala:1543:27] wire uop_fu_code_3; // @[lsu.scala:1543:27] wire uop_fu_code_4; // @[lsu.scala:1543:27] wire uop_fu_code_5; // @[lsu.scala:1543:27] wire uop_fu_code_6; // @[lsu.scala:1543:27] wire uop_fu_code_7; // @[lsu.scala:1543:27] wire uop_fu_code_8; // @[lsu.scala:1543:27] wire uop_fu_code_9; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ldst; // @[lsu.scala:1543:27] wire uop_fp_ctrl_wen; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ren1; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ren2; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ren3; // @[lsu.scala:1543:27] wire uop_fp_ctrl_swap12; // @[lsu.scala:1543:27] wire uop_fp_ctrl_swap23; // @[lsu.scala:1543:27] wire [1:0] uop_fp_ctrl_typeTagIn; // @[lsu.scala:1543:27] wire [1:0] uop_fp_ctrl_typeTagOut; // @[lsu.scala:1543:27] wire uop_fp_ctrl_fromint; // @[lsu.scala:1543:27] wire uop_fp_ctrl_toint; // @[lsu.scala:1543:27] wire uop_fp_ctrl_fastpipe; // @[lsu.scala:1543:27] wire uop_fp_ctrl_fma; // @[lsu.scala:1543:27] wire uop_fp_ctrl_div; // @[lsu.scala:1543:27] wire uop_fp_ctrl_sqrt; // @[lsu.scala:1543:27] wire uop_fp_ctrl_wflags; // @[lsu.scala:1543:27] wire uop_fp_ctrl_vec; // @[lsu.scala:1543:27] wire [31:0] uop_inst; // @[lsu.scala:1543:27] wire [31:0] uop_debug_inst; // @[lsu.scala:1543:27] wire uop_is_rvc; // @[lsu.scala:1543:27] wire [39:0] uop_debug_pc; // @[lsu.scala:1543:27] wire uop_iw_issued; // @[lsu.scala:1543:27] wire uop_iw_issued_partial_agen; // @[lsu.scala:1543:27] wire uop_iw_issued_partial_dgen; // @[lsu.scala:1543:27] wire [1:0] uop_iw_p1_speculative_child; // @[lsu.scala:1543:27] wire [1:0] uop_iw_p2_speculative_child; // @[lsu.scala:1543:27] wire uop_iw_p1_bypass_hint; // @[lsu.scala:1543:27] wire uop_iw_p2_bypass_hint; // @[lsu.scala:1543:27] wire uop_iw_p3_bypass_hint; // @[lsu.scala:1543:27] wire [1:0] uop_dis_col_sel; // @[lsu.scala:1543:27] wire [11:0] uop_br_mask; // @[lsu.scala:1543:27] wire [3:0] uop_br_tag; // @[lsu.scala:1543:27] wire [3:0] uop_br_type; // @[lsu.scala:1543:27] wire uop_is_sfb; // @[lsu.scala:1543:27] wire uop_is_fence; // @[lsu.scala:1543:27] wire uop_is_fencei; // @[lsu.scala:1543:27] wire uop_is_sfence; // @[lsu.scala:1543:27] wire uop_is_amo; // @[lsu.scala:1543:27] wire uop_is_eret; // @[lsu.scala:1543:27] wire uop_is_sys_pc2epc; // @[lsu.scala:1543:27] wire uop_is_rocc; // @[lsu.scala:1543:27] wire uop_is_mov; // @[lsu.scala:1543:27] wire [4:0] uop_ftq_idx; // @[lsu.scala:1543:27] wire uop_edge_inst; // @[lsu.scala:1543:27] wire [5:0] uop_pc_lob; // @[lsu.scala:1543:27] wire uop_taken; // @[lsu.scala:1543:27] wire uop_imm_rename; // @[lsu.scala:1543:27] wire [2:0] uop_imm_sel; // @[lsu.scala:1543:27] wire [4:0] uop_pimm; // @[lsu.scala:1543:27] wire [19:0] uop_imm_packed; // @[lsu.scala:1543:27] wire [1:0] uop_op1_sel; // @[lsu.scala:1543:27] wire [2:0] uop_op2_sel; // @[lsu.scala:1543:27] wire [5:0] uop_rob_idx; // @[lsu.scala:1543:27] wire [3:0] uop_ldq_idx; // @[lsu.scala:1543:27] wire [3:0] uop_stq_idx; // @[lsu.scala:1543:27] wire [1:0] uop_rxq_idx; // @[lsu.scala:1543:27] wire [6:0] uop_pdst; // @[lsu.scala:1543:27] wire [6:0] uop_prs1; // @[lsu.scala:1543:27] wire [6:0] uop_prs2; // @[lsu.scala:1543:27] wire [6:0] uop_prs3; // @[lsu.scala:1543:27] wire [4:0] uop_ppred; // @[lsu.scala:1543:27] wire uop_prs1_busy; // @[lsu.scala:1543:27] wire uop_prs2_busy; // @[lsu.scala:1543:27] wire uop_prs3_busy; // @[lsu.scala:1543:27] wire uop_ppred_busy; // @[lsu.scala:1543:27] wire [6:0] uop_stale_pdst; // @[lsu.scala:1543:27] wire uop_exception; // @[lsu.scala:1543:27] wire [63:0] uop_exc_cause; // @[lsu.scala:1543:27] wire [4:0] uop_mem_cmd; // @[lsu.scala:1543:27] wire [1:0] uop_mem_size; // @[lsu.scala:1543:27] wire uop_mem_signed; // @[lsu.scala:1543:27] wire uop_uses_ldq; // @[lsu.scala:1543:27] wire uop_uses_stq; // @[lsu.scala:1543:27] wire uop_is_unique; // @[lsu.scala:1543:27] wire uop_flush_on_commit; // @[lsu.scala:1543:27] wire [2:0] uop_csr_cmd; // @[lsu.scala:1543:27] wire uop_ldst_is_rs1; // @[lsu.scala:1543:27] wire [5:0] uop_ldst; // @[lsu.scala:1543:27] wire [5:0] uop_lrs1; // @[lsu.scala:1543:27] wire [5:0] uop_lrs2; // @[lsu.scala:1543:27] wire [5:0] uop_lrs3; // @[lsu.scala:1543:27] wire [1:0] uop_dst_rtype; // @[lsu.scala:1543:27] wire [1:0] uop_lrs1_rtype; // @[lsu.scala:1543:27] wire [1:0] uop_lrs2_rtype; // @[lsu.scala:1543:27] wire uop_frs3_en; // @[lsu.scala:1543:27] wire uop_fcn_dw; // @[lsu.scala:1543:27] wire [4:0] uop_fcn_op; // @[lsu.scala:1543:27] wire uop_fp_val; // @[lsu.scala:1543:27] wire [2:0] uop_fp_rm; // @[lsu.scala:1543:27] wire [1:0] uop_fp_typ; // @[lsu.scala:1543:27] wire uop_xcpt_pf_if; // @[lsu.scala:1543:27] wire uop_xcpt_ae_if; // @[lsu.scala:1543:27] wire uop_xcpt_ma_if; // @[lsu.scala:1543:27] wire uop_bp_debug_if; // @[lsu.scala:1543:27] wire uop_bp_xcpt_if; // @[lsu.scala:1543:27] wire [2:0] uop_debug_fsrc; // @[lsu.scala:1543:27] wire [2:0] uop_debug_tsrc; // @[lsu.scala:1543:27] assign uop_inst = _GEN_76[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_inst = _GEN_77[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_rvc = _GEN_78[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_pc = _GEN_79[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_0 = _GEN_80[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_1 = _GEN_81[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_2 = _GEN_82[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_3 = _GEN_83[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_0 = _GEN_84[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_1 = _GEN_85[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_2 = _GEN_86[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_3 = _GEN_87[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_4 = _GEN_88[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_5 = _GEN_89[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_6 = _GEN_90[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_7 = _GEN_91[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_8 = _GEN_92[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_9 = _GEN_93[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_issued = _GEN_94[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_issued_partial_agen = _GEN_95[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_issued_partial_dgen = _GEN_96[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p1_speculative_child = _GEN_97[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p2_speculative_child = _GEN_98[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p1_bypass_hint = _GEN_99[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p2_bypass_hint = _GEN_100[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p3_bypass_hint = _GEN_101[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_dis_col_sel = _GEN_102[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_br_mask = _GEN_103[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_br_tag = _GEN_104[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_br_type = _GEN_105[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_sfb = _GEN_106[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_fence = _GEN_107[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_fencei = _GEN_108[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_sfence = _GEN_109[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_amo = _GEN_110[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_eret = _GEN_111[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_sys_pc2epc = _GEN_112[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_rocc = _GEN_113[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_mov = _GEN_114[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ftq_idx = _GEN_115[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_edge_inst = _GEN_116[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_pc_lob = _GEN_117[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_taken = _GEN_118[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_imm_rename = _GEN_119[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_imm_sel = _GEN_120[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_pimm = _GEN_121[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_imm_packed = _GEN_122[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_op1_sel = _GEN_123[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_op2_sel = _GEN_124[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ldst = _GEN_125[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_wen = _GEN_126[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ren1 = _GEN_127[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ren2 = _GEN_128[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ren3 = _GEN_129[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_swap12 = _GEN_130[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_swap23 = _GEN_131[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_typeTagIn = _GEN_132[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_typeTagOut = _GEN_133[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_fromint = _GEN_134[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_toint = _GEN_135[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_fastpipe = _GEN_136[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_fma = _GEN_137[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_div = _GEN_138[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_sqrt = _GEN_139[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_wflags = _GEN_140[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_vec = _GEN_141[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_rob_idx = _GEN_142[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ldq_idx = _GEN_143[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_stq_idx = _GEN_144[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_rxq_idx = _GEN_145[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_pdst = _GEN_146[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs1 = _GEN_147[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs2 = _GEN_148[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs3 = _GEN_149[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ppred = _GEN_150[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs1_busy = _GEN_151[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs2_busy = _GEN_152[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs3_busy = _GEN_153[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ppred_busy = _GEN_154[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_stale_pdst = _GEN_155[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_exception = _GEN_156[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_exc_cause = _GEN_157[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_mem_cmd = _GEN_158[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_mem_size = _GEN_159[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_mem_signed = _GEN_160[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_uses_ldq = _GEN_161[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_uses_stq = _GEN_162[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_unique = _GEN_163[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_flush_on_commit = _GEN_164[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_csr_cmd = _GEN_165[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ldst_is_rs1 = _GEN_166[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ldst = _GEN_167[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs1 = _GEN_168[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs2 = _GEN_169[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs3 = _GEN_170[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_dst_rtype = _GEN_171[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs1_rtype = _GEN_172[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs2_rtype = _GEN_173[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_frs3_en = _GEN_174[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fcn_dw = _GEN_175[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fcn_op = _GEN_176[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_val = _GEN_177[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_rm = _GEN_178[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_typ = _GEN_179[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_xcpt_pf_if = _GEN_180[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_xcpt_ae_if = _GEN_181[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_xcpt_ma_if = _GEN_182[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_bp_debug_if = _GEN_183[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_bp_xcpt_if = _GEN_184[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_fsrc = _GEN_185[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_tsrc = _GEN_186[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] wire send_iresp = uop_dst_rtype == 2'h0; // @[lsu.scala:1543:27, :1544:40] wire send_fresp = uop_dst_rtype == 2'h1; // @[lsu.scala:1543:27, :1545:40] wire _ldq_will_succeed_T = iresp_0_valid | fresp_0_valid; // @[lsu.scala:1477:19, :1478:19, :1560:54] wire _GEN_507 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h0; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_508 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h1; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_509 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h2; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_510 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h3; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_511 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h4; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_512 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h5; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_513 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h6; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_514 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h7; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_515 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h8; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_516 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'h9; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_517 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'hA; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_518 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'hB; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_519 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'hC; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_520 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'hD; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_521 = _T_1162 & resp_uop_uses_ldq & resp_uop_ldq_idx == 4'hE; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_522 = _T_1162 & resp_uop_uses_ldq & (&resp_uop_ldq_idx); // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] assign dmem_resp_fired_0 = _T_1162 & (resp_uop_uses_stq | resp_uop_uses_ldq); // @[lsu.scala:1497:33, :1534:19, :1539:{33,83}, :1540:32, :1558:28, :1571:7, :1574:28] wire _GEN_523 = _T_1162 & (resp_uop_uses_stq | resp_uop_uses_ldq & send_iresp); // @[lsu.scala:1481:20, :1534:19, :1539:{33,83}, :1540:32, :1544:40, :1549:28, :1571:7, :1575:28] wire _T_1176 = dmem_resp_fired_0 & wb_ldst_forward_valid_0; // @[lsu.scala:1172:38, :1497:33, :1594:30] wire _T_1178 = ~dmem_resp_fired_0 & wb_ldst_forward_valid_0; // @[lsu.scala:1172:38, :1497:33, :1598:{18,38}] wire [1:0] size; // @[AMOALU.scala:11:18] assign size = _GEN_283[wb_ldst_forward_stq_idx_0]; // @[AMOALU.scala:11:18, :12:8] wire [3:0][63:0] _GEN_524 = {{_GEN_315[wb_ldst_forward_stq_idx_0]}, {{2{_GEN_315[wb_ldst_forward_stq_idx_0][31:0]}}}, {{2{{2{_GEN_315[wb_ldst_forward_stq_idx_0][15:0]}}}}}, {{2{{2{{2{_GEN_315[wb_ldst_forward_stq_idx_0][7:0]}}}}}}}}; // @[AMOALU.scala:29:{13,19,32,69}] wire _GEN_525 = wb_ldst_forward_e_0_uop_dst_rtype == 2'h0; // @[lsu.scala:321:49, :1612:60] wire _wb_slow_wakeups_0_valid_T; // @[lsu.scala:1612:60] assign _wb_slow_wakeups_0_valid_T = _GEN_525; // @[lsu.scala:1612:60] wire _iresp_0_valid_T; // @[lsu.scala:1618:48] assign _iresp_0_valid_T = _GEN_525; // @[lsu.scala:1612:60, :1618:48] wire _GEN_526 = _T_1176 | ~_T_1178; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1598:38, :1599:5] assign wb_slow_wakeups_0_valid = _GEN_526 ? _GEN_523 : _wb_slow_wakeups_0_valid_T; // @[lsu.scala:1481:20, :1494:29, :1539:83, :1571:7, :1595:5, :1599:5, :1612:60] wire [31:0] _GEN_527 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_200[resp_uop_stq_idx] : uop_inst) : wb_ldst_forward_e_0_uop_inst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_inst = _GEN_527; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_inst = _GEN_527; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [31:0] _GEN_528 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_201[resp_uop_stq_idx] : uop_debug_inst) : wb_ldst_forward_e_0_uop_debug_inst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_inst = _GEN_528; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_inst = _GEN_528; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_529 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_202[resp_uop_stq_idx] : uop_is_rvc) : wb_ldst_forward_e_0_uop_is_rvc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_rvc = _GEN_529; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_rvc = _GEN_529; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [39:0] _GEN_530 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_203[resp_uop_stq_idx] : uop_debug_pc) : wb_ldst_forward_e_0_uop_debug_pc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_pc = _GEN_530; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_pc = _GEN_530; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_531 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_204[resp_uop_stq_idx] : uop_iq_type_0) : wb_ldst_forward_e_0_uop_iq_type_0; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_0 = _GEN_531; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_0 = _GEN_531; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_532 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_205[resp_uop_stq_idx] : uop_iq_type_1) : wb_ldst_forward_e_0_uop_iq_type_1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_1 = _GEN_532; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_1 = _GEN_532; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_533 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_206[resp_uop_stq_idx] : uop_iq_type_2) : wb_ldst_forward_e_0_uop_iq_type_2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_2 = _GEN_533; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_2 = _GEN_533; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_534 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_207[resp_uop_stq_idx] : uop_iq_type_3) : wb_ldst_forward_e_0_uop_iq_type_3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_3 = _GEN_534; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_3 = _GEN_534; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_535 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_208[resp_uop_stq_idx] : uop_fu_code_0) : wb_ldst_forward_e_0_uop_fu_code_0; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_0 = _GEN_535; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_0 = _GEN_535; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_536 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_209[resp_uop_stq_idx] : uop_fu_code_1) : wb_ldst_forward_e_0_uop_fu_code_1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_1 = _GEN_536; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_1 = _GEN_536; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_537 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_210[resp_uop_stq_idx] : uop_fu_code_2) : wb_ldst_forward_e_0_uop_fu_code_2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_2 = _GEN_537; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_2 = _GEN_537; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_538 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_211[resp_uop_stq_idx] : uop_fu_code_3) : wb_ldst_forward_e_0_uop_fu_code_3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_3 = _GEN_538; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_3 = _GEN_538; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_539 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_212[resp_uop_stq_idx] : uop_fu_code_4) : wb_ldst_forward_e_0_uop_fu_code_4; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_4 = _GEN_539; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_4 = _GEN_539; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_540 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_213[resp_uop_stq_idx] : uop_fu_code_5) : wb_ldst_forward_e_0_uop_fu_code_5; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_5 = _GEN_540; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_5 = _GEN_540; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_541 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_214[resp_uop_stq_idx] : uop_fu_code_6) : wb_ldst_forward_e_0_uop_fu_code_6; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_6 = _GEN_541; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_6 = _GEN_541; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_542 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_215[resp_uop_stq_idx] : uop_fu_code_7) : wb_ldst_forward_e_0_uop_fu_code_7; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_7 = _GEN_542; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_7 = _GEN_542; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_543 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_216[resp_uop_stq_idx] : uop_fu_code_8) : wb_ldst_forward_e_0_uop_fu_code_8; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_8 = _GEN_543; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_8 = _GEN_543; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_544 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_217[resp_uop_stq_idx] : uop_fu_code_9) : wb_ldst_forward_e_0_uop_fu_code_9; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_9 = _GEN_544; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_9 = _GEN_544; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_545 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_218[resp_uop_stq_idx] : uop_iw_issued) : wb_ldst_forward_e_0_uop_iw_issued; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_issued = _GEN_545; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_issued = _GEN_545; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_546 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_219[resp_uop_stq_idx] : uop_iw_issued_partial_agen) : wb_ldst_forward_e_0_uop_iw_issued_partial_agen; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_issued_partial_agen = _GEN_546; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_issued_partial_agen = _GEN_546; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_547 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_220[resp_uop_stq_idx] : uop_iw_issued_partial_dgen) : wb_ldst_forward_e_0_uop_iw_issued_partial_dgen; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_issued_partial_dgen = _GEN_547; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_issued_partial_dgen = _GEN_547; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_548 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_221[resp_uop_stq_idx] : uop_iw_p1_speculative_child) : wb_ldst_forward_e_0_uop_iw_p1_speculative_child; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p1_speculative_child = _GEN_548; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p1_speculative_child = _GEN_548; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_549 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_222[resp_uop_stq_idx] : uop_iw_p2_speculative_child) : wb_ldst_forward_e_0_uop_iw_p2_speculative_child; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p2_speculative_child = _GEN_549; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p2_speculative_child = _GEN_549; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_550 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_223[resp_uop_stq_idx] : uop_iw_p1_bypass_hint) : wb_ldst_forward_e_0_uop_iw_p1_bypass_hint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p1_bypass_hint = _GEN_550; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p1_bypass_hint = _GEN_550; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_551 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_224[resp_uop_stq_idx] : uop_iw_p2_bypass_hint) : wb_ldst_forward_e_0_uop_iw_p2_bypass_hint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p2_bypass_hint = _GEN_551; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p2_bypass_hint = _GEN_551; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_552 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_225[resp_uop_stq_idx] : uop_iw_p3_bypass_hint) : wb_ldst_forward_e_0_uop_iw_p3_bypass_hint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p3_bypass_hint = _GEN_552; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p3_bypass_hint = _GEN_552; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_553 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_226[resp_uop_stq_idx] : uop_dis_col_sel) : wb_ldst_forward_e_0_uop_dis_col_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_dis_col_sel = _GEN_553; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_dis_col_sel = _GEN_553; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [11:0] _GEN_554 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_227[resp_uop_stq_idx] : uop_br_mask) : wb_ldst_forward_e_0_uop_br_mask; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_br_mask = _GEN_554; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_br_mask = _GEN_554; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [3:0] _GEN_555 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_228[resp_uop_stq_idx] : uop_br_tag) : wb_ldst_forward_e_0_uop_br_tag; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_br_tag = _GEN_555; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_br_tag = _GEN_555; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [3:0] _GEN_556 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_229[resp_uop_stq_idx] : uop_br_type) : wb_ldst_forward_e_0_uop_br_type; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_br_type = _GEN_556; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_br_type = _GEN_556; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_557 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_230[resp_uop_stq_idx] : uop_is_sfb) : wb_ldst_forward_e_0_uop_is_sfb; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_sfb = _GEN_557; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_sfb = _GEN_557; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_558 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_231[resp_uop_stq_idx] : uop_is_fence) : wb_ldst_forward_e_0_uop_is_fence; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_fence = _GEN_558; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_fence = _GEN_558; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_559 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_232[resp_uop_stq_idx] : uop_is_fencei) : wb_ldst_forward_e_0_uop_is_fencei; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_fencei = _GEN_559; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_fencei = _GEN_559; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_560 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_233[resp_uop_stq_idx] : uop_is_sfence) : wb_ldst_forward_e_0_uop_is_sfence; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_sfence = _GEN_560; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_sfence = _GEN_560; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_561 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_234[resp_uop_stq_idx] : uop_is_amo) : wb_ldst_forward_e_0_uop_is_amo; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_amo = _GEN_561; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_amo = _GEN_561; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_562 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_235[resp_uop_stq_idx] : uop_is_eret) : wb_ldst_forward_e_0_uop_is_eret; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_eret = _GEN_562; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_eret = _GEN_562; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_563 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_236[resp_uop_stq_idx] : uop_is_sys_pc2epc) : wb_ldst_forward_e_0_uop_is_sys_pc2epc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_sys_pc2epc = _GEN_563; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_sys_pc2epc = _GEN_563; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_564 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_237[resp_uop_stq_idx] : uop_is_rocc) : wb_ldst_forward_e_0_uop_is_rocc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_rocc = _GEN_564; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_rocc = _GEN_564; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_565 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_238[resp_uop_stq_idx] : uop_is_mov) : wb_ldst_forward_e_0_uop_is_mov; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_mov = _GEN_565; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_mov = _GEN_565; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_566 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_239[resp_uop_stq_idx] : uop_ftq_idx) : wb_ldst_forward_e_0_uop_ftq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ftq_idx = _GEN_566; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ftq_idx = _GEN_566; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_567 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_240[resp_uop_stq_idx] : uop_edge_inst) : wb_ldst_forward_e_0_uop_edge_inst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_edge_inst = _GEN_567; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_edge_inst = _GEN_567; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_568 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_241[resp_uop_stq_idx] : uop_pc_lob) : wb_ldst_forward_e_0_uop_pc_lob; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_pc_lob = _GEN_568; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_pc_lob = _GEN_568; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_569 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_242[resp_uop_stq_idx] : uop_taken) : wb_ldst_forward_e_0_uop_taken; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_taken = _GEN_569; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_taken = _GEN_569; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_570 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_243[resp_uop_stq_idx] : uop_imm_rename) : wb_ldst_forward_e_0_uop_imm_rename; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_imm_rename = _GEN_570; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_imm_rename = _GEN_570; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_571 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_244[resp_uop_stq_idx] : uop_imm_sel) : wb_ldst_forward_e_0_uop_imm_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_imm_sel = _GEN_571; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_imm_sel = _GEN_571; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_572 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_245[resp_uop_stq_idx] : uop_pimm) : wb_ldst_forward_e_0_uop_pimm; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_pimm = _GEN_572; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_pimm = _GEN_572; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [19:0] _GEN_573 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_246[resp_uop_stq_idx] : uop_imm_packed) : wb_ldst_forward_e_0_uop_imm_packed; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_imm_packed = _GEN_573; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_imm_packed = _GEN_573; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_574 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_247[resp_uop_stq_idx] : uop_op1_sel) : wb_ldst_forward_e_0_uop_op1_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_op1_sel = _GEN_574; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_op1_sel = _GEN_574; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_575 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_248[resp_uop_stq_idx] : uop_op2_sel) : wb_ldst_forward_e_0_uop_op2_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_op2_sel = _GEN_575; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_op2_sel = _GEN_575; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_576 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_249[resp_uop_stq_idx] : uop_fp_ctrl_ldst) : wb_ldst_forward_e_0_uop_fp_ctrl_ldst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ldst = _GEN_576; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ldst = _GEN_576; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_577 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_250[resp_uop_stq_idx] : uop_fp_ctrl_wen) : wb_ldst_forward_e_0_uop_fp_ctrl_wen; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_wen = _GEN_577; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_wen = _GEN_577; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_578 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_251[resp_uop_stq_idx] : uop_fp_ctrl_ren1) : wb_ldst_forward_e_0_uop_fp_ctrl_ren1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ren1 = _GEN_578; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ren1 = _GEN_578; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_579 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_252[resp_uop_stq_idx] : uop_fp_ctrl_ren2) : wb_ldst_forward_e_0_uop_fp_ctrl_ren2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ren2 = _GEN_579; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ren2 = _GEN_579; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_580 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_253[resp_uop_stq_idx] : uop_fp_ctrl_ren3) : wb_ldst_forward_e_0_uop_fp_ctrl_ren3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ren3 = _GEN_580; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ren3 = _GEN_580; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_581 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_254[resp_uop_stq_idx] : uop_fp_ctrl_swap12) : wb_ldst_forward_e_0_uop_fp_ctrl_swap12; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_swap12 = _GEN_581; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_swap12 = _GEN_581; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_582 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_255[resp_uop_stq_idx] : uop_fp_ctrl_swap23) : wb_ldst_forward_e_0_uop_fp_ctrl_swap23; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_swap23 = _GEN_582; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_swap23 = _GEN_582; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_583 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_256[resp_uop_stq_idx] : uop_fp_ctrl_typeTagIn) : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagIn; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_typeTagIn = _GEN_583; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn = _GEN_583; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_584 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_257[resp_uop_stq_idx] : uop_fp_ctrl_typeTagOut) : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagOut; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_typeTagOut = _GEN_584; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut = _GEN_584; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_585 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_258[resp_uop_stq_idx] : uop_fp_ctrl_fromint) : wb_ldst_forward_e_0_uop_fp_ctrl_fromint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_fromint = _GEN_585; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_fromint = _GEN_585; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_586 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_259[resp_uop_stq_idx] : uop_fp_ctrl_toint) : wb_ldst_forward_e_0_uop_fp_ctrl_toint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_toint = _GEN_586; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_toint = _GEN_586; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_587 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_260[resp_uop_stq_idx] : uop_fp_ctrl_fastpipe) : wb_ldst_forward_e_0_uop_fp_ctrl_fastpipe; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_fastpipe = _GEN_587; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_fastpipe = _GEN_587; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_588 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_261[resp_uop_stq_idx] : uop_fp_ctrl_fma) : wb_ldst_forward_e_0_uop_fp_ctrl_fma; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_fma = _GEN_588; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_fma = _GEN_588; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_589 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_262[resp_uop_stq_idx] : uop_fp_ctrl_div) : wb_ldst_forward_e_0_uop_fp_ctrl_div; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_div = _GEN_589; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_div = _GEN_589; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_590 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_263[resp_uop_stq_idx] : uop_fp_ctrl_sqrt) : wb_ldst_forward_e_0_uop_fp_ctrl_sqrt; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_sqrt = _GEN_590; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_sqrt = _GEN_590; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_591 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_264[resp_uop_stq_idx] : uop_fp_ctrl_wflags) : wb_ldst_forward_e_0_uop_fp_ctrl_wflags; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_wflags = _GEN_591; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_wflags = _GEN_591; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_592 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_265[resp_uop_stq_idx] : uop_fp_ctrl_vec) : wb_ldst_forward_e_0_uop_fp_ctrl_vec; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_vec = _GEN_592; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_vec = _GEN_592; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_593 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_266[resp_uop_stq_idx] : uop_rob_idx) : wb_ldst_forward_e_0_uop_rob_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_rob_idx = _GEN_593; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_rob_idx = _GEN_593; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [3:0] _GEN_594 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_267[resp_uop_stq_idx] : uop_ldq_idx) : wb_ldst_forward_e_0_uop_ldq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ldq_idx = _GEN_594; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ldq_idx = _GEN_594; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [3:0] _GEN_595 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_268[resp_uop_stq_idx] : uop_stq_idx) : wb_ldst_forward_e_0_uop_stq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_stq_idx = _GEN_595; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_stq_idx = _GEN_595; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_596 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_269[resp_uop_stq_idx] : uop_rxq_idx) : wb_ldst_forward_e_0_uop_rxq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_rxq_idx = _GEN_596; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_rxq_idx = _GEN_596; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_597 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_270[resp_uop_stq_idx] : uop_pdst) : wb_ldst_forward_e_0_uop_pdst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_pdst = _GEN_597; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_pdst = _GEN_597; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_598 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_271[resp_uop_stq_idx] : uop_prs1) : wb_ldst_forward_e_0_uop_prs1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs1 = _GEN_598; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs1 = _GEN_598; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_599 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_272[resp_uop_stq_idx] : uop_prs2) : wb_ldst_forward_e_0_uop_prs2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs2 = _GEN_599; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs2 = _GEN_599; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_600 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_273[resp_uop_stq_idx] : uop_prs3) : wb_ldst_forward_e_0_uop_prs3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs3 = _GEN_600; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs3 = _GEN_600; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_601 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_274[resp_uop_stq_idx] : uop_ppred) : wb_ldst_forward_e_0_uop_ppred; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ppred = _GEN_601; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ppred = _GEN_601; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_602 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_275[resp_uop_stq_idx] : uop_prs1_busy) : wb_ldst_forward_e_0_uop_prs1_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs1_busy = _GEN_602; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs1_busy = _GEN_602; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_603 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_276[resp_uop_stq_idx] : uop_prs2_busy) : wb_ldst_forward_e_0_uop_prs2_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs2_busy = _GEN_603; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs2_busy = _GEN_603; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_604 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_277[resp_uop_stq_idx] : uop_prs3_busy) : wb_ldst_forward_e_0_uop_prs3_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs3_busy = _GEN_604; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs3_busy = _GEN_604; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_605 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_278[resp_uop_stq_idx] : uop_ppred_busy) : wb_ldst_forward_e_0_uop_ppred_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ppred_busy = _GEN_605; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ppred_busy = _GEN_605; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_606 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_279[resp_uop_stq_idx] : uop_stale_pdst) : wb_ldst_forward_e_0_uop_stale_pdst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_stale_pdst = _GEN_606; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_stale_pdst = _GEN_606; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_607 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_280[resp_uop_stq_idx] : uop_exception) : wb_ldst_forward_e_0_uop_exception; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_exception = _GEN_607; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_exception = _GEN_607; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [63:0] _GEN_608 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_281[resp_uop_stq_idx] : uop_exc_cause) : wb_ldst_forward_e_0_uop_exc_cause; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_exc_cause = _GEN_608; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_exc_cause = _GEN_608; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_609 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_282[resp_uop_stq_idx] : uop_mem_cmd) : wb_ldst_forward_e_0_uop_mem_cmd; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_mem_cmd = _GEN_609; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_mem_cmd = _GEN_609; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_610 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_283[resp_uop_stq_idx] : uop_mem_size) : wb_ldst_forward_e_0_uop_mem_size; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_mem_size = _GEN_610; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_mem_size = _GEN_610; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_611 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_284[resp_uop_stq_idx] : uop_mem_signed) : wb_ldst_forward_e_0_uop_mem_signed; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_mem_signed = _GEN_611; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_mem_signed = _GEN_611; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_612 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_285[resp_uop_stq_idx] : uop_uses_ldq) : wb_ldst_forward_e_0_uop_uses_ldq; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_uses_ldq = _GEN_612; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_uses_ldq = _GEN_612; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_613 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_286[resp_uop_stq_idx] : uop_uses_stq) : wb_ldst_forward_e_0_uop_uses_stq; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_uses_stq = _GEN_613; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_uses_stq = _GEN_613; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_614 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_287[resp_uop_stq_idx] : uop_is_unique) : wb_ldst_forward_e_0_uop_is_unique; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_unique = _GEN_614; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_unique = _GEN_614; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_615 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_288[resp_uop_stq_idx] : uop_flush_on_commit) : wb_ldst_forward_e_0_uop_flush_on_commit; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_flush_on_commit = _GEN_615; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_flush_on_commit = _GEN_615; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_616 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_289[resp_uop_stq_idx] : uop_csr_cmd) : wb_ldst_forward_e_0_uop_csr_cmd; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_csr_cmd = _GEN_616; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_csr_cmd = _GEN_616; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_617 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_290[resp_uop_stq_idx] : uop_ldst_is_rs1) : wb_ldst_forward_e_0_uop_ldst_is_rs1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ldst_is_rs1 = _GEN_617; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ldst_is_rs1 = _GEN_617; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_618 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_291[resp_uop_stq_idx] : uop_ldst) : wb_ldst_forward_e_0_uop_ldst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ldst = _GEN_618; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ldst = _GEN_618; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_619 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_292[resp_uop_stq_idx] : uop_lrs1) : wb_ldst_forward_e_0_uop_lrs1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs1 = _GEN_619; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs1 = _GEN_619; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_620 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_293[resp_uop_stq_idx] : uop_lrs2) : wb_ldst_forward_e_0_uop_lrs2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs2 = _GEN_620; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs2 = _GEN_620; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_621 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_294[resp_uop_stq_idx] : uop_lrs3) : wb_ldst_forward_e_0_uop_lrs3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs3 = _GEN_621; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs3 = _GEN_621; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_622 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_295[resp_uop_stq_idx] : uop_dst_rtype) : wb_ldst_forward_e_0_uop_dst_rtype; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_dst_rtype = _GEN_622; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_dst_rtype = _GEN_622; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_623 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_296[resp_uop_stq_idx] : uop_lrs1_rtype) : wb_ldst_forward_e_0_uop_lrs1_rtype; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs1_rtype = _GEN_623; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs1_rtype = _GEN_623; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_624 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_297[resp_uop_stq_idx] : uop_lrs2_rtype) : wb_ldst_forward_e_0_uop_lrs2_rtype; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs2_rtype = _GEN_624; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs2_rtype = _GEN_624; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_625 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_298[resp_uop_stq_idx] : uop_frs3_en) : wb_ldst_forward_e_0_uop_frs3_en; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_frs3_en = _GEN_625; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_frs3_en = _GEN_625; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_626 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_299[resp_uop_stq_idx] : uop_fcn_dw) : wb_ldst_forward_e_0_uop_fcn_dw; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fcn_dw = _GEN_626; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fcn_dw = _GEN_626; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_627 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_300[resp_uop_stq_idx] : uop_fcn_op) : wb_ldst_forward_e_0_uop_fcn_op; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fcn_op = _GEN_627; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fcn_op = _GEN_627; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_628 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_301[resp_uop_stq_idx] : uop_fp_val) : wb_ldst_forward_e_0_uop_fp_val; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_val = _GEN_628; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_val = _GEN_628; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_629 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_302[resp_uop_stq_idx] : uop_fp_rm) : wb_ldst_forward_e_0_uop_fp_rm; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_rm = _GEN_629; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_rm = _GEN_629; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_630 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_303[resp_uop_stq_idx] : uop_fp_typ) : wb_ldst_forward_e_0_uop_fp_typ; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_typ = _GEN_630; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_typ = _GEN_630; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_631 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_304[resp_uop_stq_idx] : uop_xcpt_pf_if) : wb_ldst_forward_e_0_uop_xcpt_pf_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_xcpt_pf_if = _GEN_631; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_xcpt_pf_if = _GEN_631; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_632 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_305[resp_uop_stq_idx] : uop_xcpt_ae_if) : wb_ldst_forward_e_0_uop_xcpt_ae_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_xcpt_ae_if = _GEN_632; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_xcpt_ae_if = _GEN_632; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_633 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_306[resp_uop_stq_idx] : uop_xcpt_ma_if) : wb_ldst_forward_e_0_uop_xcpt_ma_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_xcpt_ma_if = _GEN_633; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_xcpt_ma_if = _GEN_633; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_634 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_307[resp_uop_stq_idx] : uop_bp_debug_if) : wb_ldst_forward_e_0_uop_bp_debug_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_bp_debug_if = _GEN_634; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_bp_debug_if = _GEN_634; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_635 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_308[resp_uop_stq_idx] : uop_bp_xcpt_if) : wb_ldst_forward_e_0_uop_bp_xcpt_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_bp_xcpt_if = _GEN_635; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_bp_xcpt_if = _GEN_635; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_636 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_309[resp_uop_stq_idx] : uop_debug_fsrc) : wb_ldst_forward_e_0_uop_debug_fsrc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_fsrc = _GEN_636; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_fsrc = _GEN_636; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_637 = _GEN_526 ? (resp_uop_uses_stq ? _GEN_310[resp_uop_stq_idx] : uop_debug_tsrc) : wb_ldst_forward_e_0_uop_debug_tsrc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_tsrc = _GEN_637; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_tsrc = _GEN_637; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] assign iresp_0_valid = _GEN_526 ? _GEN_523 : _iresp_0_valid_T; // @[lsu.scala:1477:19, :1481:20, :1539:83, :1571:7, :1595:5, :1599:5, :1618:48] wire _fresp_0_valid_T = wb_ldst_forward_e_0_uop_dst_rtype == 2'h1; // @[lsu.scala:321:49, :1619:48] assign fresp_0_valid = _GEN_526 ? _GEN_506 & send_fresp : _fresp_0_valid_T; // @[lsu.scala:1478:19, :1483:20, :1539:83, :1540:32, :1545:40, :1554:28, :1595:5, :1599:5, :1619:48] assign fresp_0_bits_uop_inst = _GEN_526 ? uop_inst : wb_ldst_forward_e_0_uop_inst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_inst = _GEN_526 ? uop_debug_inst : wb_ldst_forward_e_0_uop_debug_inst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_rvc = _GEN_526 ? uop_is_rvc : wb_ldst_forward_e_0_uop_is_rvc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_pc = _GEN_526 ? uop_debug_pc : wb_ldst_forward_e_0_uop_debug_pc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_0 = _GEN_526 ? uop_iq_type_0 : wb_ldst_forward_e_0_uop_iq_type_0; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_1 = _GEN_526 ? uop_iq_type_1 : wb_ldst_forward_e_0_uop_iq_type_1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_2 = _GEN_526 ? uop_iq_type_2 : wb_ldst_forward_e_0_uop_iq_type_2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_3 = _GEN_526 ? uop_iq_type_3 : wb_ldst_forward_e_0_uop_iq_type_3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_0 = _GEN_526 ? uop_fu_code_0 : wb_ldst_forward_e_0_uop_fu_code_0; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_1 = _GEN_526 ? uop_fu_code_1 : wb_ldst_forward_e_0_uop_fu_code_1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_2 = _GEN_526 ? uop_fu_code_2 : wb_ldst_forward_e_0_uop_fu_code_2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_3 = _GEN_526 ? uop_fu_code_3 : wb_ldst_forward_e_0_uop_fu_code_3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_4 = _GEN_526 ? uop_fu_code_4 : wb_ldst_forward_e_0_uop_fu_code_4; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_5 = _GEN_526 ? uop_fu_code_5 : wb_ldst_forward_e_0_uop_fu_code_5; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_6 = _GEN_526 ? uop_fu_code_6 : wb_ldst_forward_e_0_uop_fu_code_6; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_7 = _GEN_526 ? uop_fu_code_7 : wb_ldst_forward_e_0_uop_fu_code_7; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_8 = _GEN_526 ? uop_fu_code_8 : wb_ldst_forward_e_0_uop_fu_code_8; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_9 = _GEN_526 ? uop_fu_code_9 : wb_ldst_forward_e_0_uop_fu_code_9; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_issued = _GEN_526 ? uop_iw_issued : wb_ldst_forward_e_0_uop_iw_issued; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_issued_partial_agen = _GEN_526 ? uop_iw_issued_partial_agen : wb_ldst_forward_e_0_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_issued_partial_dgen = _GEN_526 ? uop_iw_issued_partial_dgen : wb_ldst_forward_e_0_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p1_speculative_child = _GEN_526 ? uop_iw_p1_speculative_child : wb_ldst_forward_e_0_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p2_speculative_child = _GEN_526 ? uop_iw_p2_speculative_child : wb_ldst_forward_e_0_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p1_bypass_hint = _GEN_526 ? uop_iw_p1_bypass_hint : wb_ldst_forward_e_0_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p2_bypass_hint = _GEN_526 ? uop_iw_p2_bypass_hint : wb_ldst_forward_e_0_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p3_bypass_hint = _GEN_526 ? uop_iw_p3_bypass_hint : wb_ldst_forward_e_0_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_dis_col_sel = _GEN_526 ? uop_dis_col_sel : wb_ldst_forward_e_0_uop_dis_col_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_br_mask = _GEN_526 ? uop_br_mask : wb_ldst_forward_e_0_uop_br_mask; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_br_tag = _GEN_526 ? uop_br_tag : wb_ldst_forward_e_0_uop_br_tag; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_br_type = _GEN_526 ? uop_br_type : wb_ldst_forward_e_0_uop_br_type; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_sfb = _GEN_526 ? uop_is_sfb : wb_ldst_forward_e_0_uop_is_sfb; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_fence = _GEN_526 ? uop_is_fence : wb_ldst_forward_e_0_uop_is_fence; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_fencei = _GEN_526 ? uop_is_fencei : wb_ldst_forward_e_0_uop_is_fencei; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_sfence = _GEN_526 ? uop_is_sfence : wb_ldst_forward_e_0_uop_is_sfence; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_amo = _GEN_526 ? uop_is_amo : wb_ldst_forward_e_0_uop_is_amo; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_eret = _GEN_526 ? uop_is_eret : wb_ldst_forward_e_0_uop_is_eret; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_sys_pc2epc = _GEN_526 ? uop_is_sys_pc2epc : wb_ldst_forward_e_0_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_rocc = _GEN_526 ? uop_is_rocc : wb_ldst_forward_e_0_uop_is_rocc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_mov = _GEN_526 ? uop_is_mov : wb_ldst_forward_e_0_uop_is_mov; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ftq_idx = _GEN_526 ? uop_ftq_idx : wb_ldst_forward_e_0_uop_ftq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_edge_inst = _GEN_526 ? uop_edge_inst : wb_ldst_forward_e_0_uop_edge_inst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_pc_lob = _GEN_526 ? uop_pc_lob : wb_ldst_forward_e_0_uop_pc_lob; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_taken = _GEN_526 ? uop_taken : wb_ldst_forward_e_0_uop_taken; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_imm_rename = _GEN_526 ? uop_imm_rename : wb_ldst_forward_e_0_uop_imm_rename; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_imm_sel = _GEN_526 ? uop_imm_sel : wb_ldst_forward_e_0_uop_imm_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_pimm = _GEN_526 ? uop_pimm : wb_ldst_forward_e_0_uop_pimm; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_imm_packed = _GEN_526 ? uop_imm_packed : wb_ldst_forward_e_0_uop_imm_packed; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_op1_sel = _GEN_526 ? uop_op1_sel : wb_ldst_forward_e_0_uop_op1_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_op2_sel = _GEN_526 ? uop_op2_sel : wb_ldst_forward_e_0_uop_op2_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ldst = _GEN_526 ? uop_fp_ctrl_ldst : wb_ldst_forward_e_0_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_wen = _GEN_526 ? uop_fp_ctrl_wen : wb_ldst_forward_e_0_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ren1 = _GEN_526 ? uop_fp_ctrl_ren1 : wb_ldst_forward_e_0_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ren2 = _GEN_526 ? uop_fp_ctrl_ren2 : wb_ldst_forward_e_0_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ren3 = _GEN_526 ? uop_fp_ctrl_ren3 : wb_ldst_forward_e_0_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_swap12 = _GEN_526 ? uop_fp_ctrl_swap12 : wb_ldst_forward_e_0_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_swap23 = _GEN_526 ? uop_fp_ctrl_swap23 : wb_ldst_forward_e_0_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_typeTagIn = _GEN_526 ? uop_fp_ctrl_typeTagIn : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_typeTagOut = _GEN_526 ? uop_fp_ctrl_typeTagOut : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_fromint = _GEN_526 ? uop_fp_ctrl_fromint : wb_ldst_forward_e_0_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_toint = _GEN_526 ? uop_fp_ctrl_toint : wb_ldst_forward_e_0_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_fastpipe = _GEN_526 ? uop_fp_ctrl_fastpipe : wb_ldst_forward_e_0_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_fma = _GEN_526 ? uop_fp_ctrl_fma : wb_ldst_forward_e_0_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_div = _GEN_526 ? uop_fp_ctrl_div : wb_ldst_forward_e_0_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_sqrt = _GEN_526 ? uop_fp_ctrl_sqrt : wb_ldst_forward_e_0_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_wflags = _GEN_526 ? uop_fp_ctrl_wflags : wb_ldst_forward_e_0_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_vec = _GEN_526 ? uop_fp_ctrl_vec : wb_ldst_forward_e_0_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_rob_idx = _GEN_526 ? uop_rob_idx : wb_ldst_forward_e_0_uop_rob_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ldq_idx = _GEN_526 ? uop_ldq_idx : wb_ldst_forward_e_0_uop_ldq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_stq_idx = _GEN_526 ? uop_stq_idx : wb_ldst_forward_e_0_uop_stq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_rxq_idx = _GEN_526 ? uop_rxq_idx : wb_ldst_forward_e_0_uop_rxq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_pdst = _GEN_526 ? uop_pdst : wb_ldst_forward_e_0_uop_pdst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs1 = _GEN_526 ? uop_prs1 : wb_ldst_forward_e_0_uop_prs1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs2 = _GEN_526 ? uop_prs2 : wb_ldst_forward_e_0_uop_prs2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs3 = _GEN_526 ? uop_prs3 : wb_ldst_forward_e_0_uop_prs3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ppred = _GEN_526 ? uop_ppred : wb_ldst_forward_e_0_uop_ppred; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs1_busy = _GEN_526 ? uop_prs1_busy : wb_ldst_forward_e_0_uop_prs1_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs2_busy = _GEN_526 ? uop_prs2_busy : wb_ldst_forward_e_0_uop_prs2_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs3_busy = _GEN_526 ? uop_prs3_busy : wb_ldst_forward_e_0_uop_prs3_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ppred_busy = _GEN_526 ? uop_ppred_busy : wb_ldst_forward_e_0_uop_ppred_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_stale_pdst = _GEN_526 ? uop_stale_pdst : wb_ldst_forward_e_0_uop_stale_pdst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_exception = _GEN_526 ? uop_exception : wb_ldst_forward_e_0_uop_exception; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_exc_cause = _GEN_526 ? uop_exc_cause : wb_ldst_forward_e_0_uop_exc_cause; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_mem_cmd = _GEN_526 ? uop_mem_cmd : wb_ldst_forward_e_0_uop_mem_cmd; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_mem_size = _GEN_526 ? uop_mem_size : wb_ldst_forward_e_0_uop_mem_size; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_mem_signed = _GEN_526 ? uop_mem_signed : wb_ldst_forward_e_0_uop_mem_signed; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_uses_ldq = _GEN_526 ? uop_uses_ldq : wb_ldst_forward_e_0_uop_uses_ldq; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_uses_stq = _GEN_526 ? uop_uses_stq : wb_ldst_forward_e_0_uop_uses_stq; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_unique = _GEN_526 ? uop_is_unique : wb_ldst_forward_e_0_uop_is_unique; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_flush_on_commit = _GEN_526 ? uop_flush_on_commit : wb_ldst_forward_e_0_uop_flush_on_commit; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_csr_cmd = _GEN_526 ? uop_csr_cmd : wb_ldst_forward_e_0_uop_csr_cmd; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ldst_is_rs1 = _GEN_526 ? uop_ldst_is_rs1 : wb_ldst_forward_e_0_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ldst = _GEN_526 ? uop_ldst : wb_ldst_forward_e_0_uop_ldst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs1 = _GEN_526 ? uop_lrs1 : wb_ldst_forward_e_0_uop_lrs1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs2 = _GEN_526 ? uop_lrs2 : wb_ldst_forward_e_0_uop_lrs2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs3 = _GEN_526 ? uop_lrs3 : wb_ldst_forward_e_0_uop_lrs3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_dst_rtype = _GEN_526 ? uop_dst_rtype : wb_ldst_forward_e_0_uop_dst_rtype; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs1_rtype = _GEN_526 ? uop_lrs1_rtype : wb_ldst_forward_e_0_uop_lrs1_rtype; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs2_rtype = _GEN_526 ? uop_lrs2_rtype : wb_ldst_forward_e_0_uop_lrs2_rtype; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_frs3_en = _GEN_526 ? uop_frs3_en : wb_ldst_forward_e_0_uop_frs3_en; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fcn_dw = _GEN_526 ? uop_fcn_dw : wb_ldst_forward_e_0_uop_fcn_dw; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fcn_op = _GEN_526 ? uop_fcn_op : wb_ldst_forward_e_0_uop_fcn_op; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_val = _GEN_526 ? uop_fp_val : wb_ldst_forward_e_0_uop_fp_val; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_rm = _GEN_526 ? uop_fp_rm : wb_ldst_forward_e_0_uop_fp_rm; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_typ = _GEN_526 ? uop_fp_typ : wb_ldst_forward_e_0_uop_fp_typ; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_xcpt_pf_if = _GEN_526 ? uop_xcpt_pf_if : wb_ldst_forward_e_0_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_xcpt_ae_if = _GEN_526 ? uop_xcpt_ae_if : wb_ldst_forward_e_0_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_xcpt_ma_if = _GEN_526 ? uop_xcpt_ma_if : wb_ldst_forward_e_0_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_bp_debug_if = _GEN_526 ? uop_bp_debug_if : wb_ldst_forward_e_0_uop_bp_debug_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_bp_xcpt_if = _GEN_526 ? uop_bp_xcpt_if : wb_ldst_forward_e_0_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_fsrc = _GEN_526 ? uop_debug_fsrc : wb_ldst_forward_e_0_uop_debug_fsrc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_tsrc = _GEN_526 ? uop_debug_tsrc : wb_ldst_forward_e_0_uop_debug_tsrc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] wire [31:0] _iresp_0_bits_data_shifted_T_1 = _GEN_524[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _iresp_0_bits_data_T_5 = _GEN_524[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _fresp_0_bits_data_shifted_T_1 = _GEN_524[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _fresp_0_bits_data_T_5 = _GEN_524[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _ldq_debug_wb_data_shifted_T_1 = _GEN_524[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _ldq_debug_wb_data_T_5 = _GEN_524[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _iresp_0_bits_data_shifted_T_2 = _GEN_524[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _fresp_0_bits_data_shifted_T_2 = _GEN_524[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _ldq_debug_wb_data_shifted_T_2 = _GEN_524[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] iresp_0_bits_data_shifted = _iresp_0_bits_data_shifted_T ? _iresp_0_bits_data_shifted_T_1 : _iresp_0_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] iresp_0_bits_data_zeroed = iresp_0_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _GEN_638 = size_1 == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _iresp_0_bits_data_T; // @[AMOALU.scala:45:26] assign _iresp_0_bits_data_T = _GEN_638; // @[AMOALU.scala:45:26] wire _fresp_0_bits_data_T; // @[AMOALU.scala:45:26] assign _fresp_0_bits_data_T = _GEN_638; // @[AMOALU.scala:45:26] wire _ldq_debug_wb_data_T; // @[AMOALU.scala:45:26] assign _ldq_debug_wb_data_T = _GEN_638; // @[AMOALU.scala:45:26] wire _iresp_0_bits_data_T_1 = _iresp_0_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _iresp_0_bits_data_T_2 = iresp_0_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _iresp_0_bits_data_T_3 = wb_ldst_forward_e_0_uop_mem_signed & _iresp_0_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _iresp_0_bits_data_T_4 = {32{_iresp_0_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _iresp_0_bits_data_T_6 = _iresp_0_bits_data_T_1 ? _iresp_0_bits_data_T_4 : _iresp_0_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _iresp_0_bits_data_T_7 = {_iresp_0_bits_data_T_6, iresp_0_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _iresp_0_bits_data_shifted_T_3 = wb_ldst_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _fresp_0_bits_data_shifted_T_3 = wb_ldst_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _ldq_debug_wb_data_shifted_T_3 = wb_ldst_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire [15:0] _iresp_0_bits_data_shifted_T_4 = _iresp_0_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _iresp_0_bits_data_shifted_T_5 = _iresp_0_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] iresp_0_bits_data_shifted_1 = _iresp_0_bits_data_shifted_T_3 ? _iresp_0_bits_data_shifted_T_4 : _iresp_0_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] iresp_0_bits_data_zeroed_1 = iresp_0_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _GEN_639 = size_1 == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _iresp_0_bits_data_T_8; // @[AMOALU.scala:45:26] assign _iresp_0_bits_data_T_8 = _GEN_639; // @[AMOALU.scala:45:26] wire _fresp_0_bits_data_T_8; // @[AMOALU.scala:45:26] assign _fresp_0_bits_data_T_8 = _GEN_639; // @[AMOALU.scala:45:26] wire _ldq_debug_wb_data_T_8; // @[AMOALU.scala:45:26] assign _ldq_debug_wb_data_T_8 = _GEN_639; // @[AMOALU.scala:45:26] wire _iresp_0_bits_data_T_9 = _iresp_0_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _iresp_0_bits_data_T_10 = iresp_0_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _iresp_0_bits_data_T_11 = wb_ldst_forward_e_0_uop_mem_signed & _iresp_0_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _iresp_0_bits_data_T_12 = {48{_iresp_0_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _iresp_0_bits_data_T_13 = _iresp_0_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _iresp_0_bits_data_T_14 = _iresp_0_bits_data_T_9 ? _iresp_0_bits_data_T_12 : _iresp_0_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _iresp_0_bits_data_T_15 = {_iresp_0_bits_data_T_14, iresp_0_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _iresp_0_bits_data_shifted_T_6 = wb_ldst_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _fresp_0_bits_data_shifted_T_6 = wb_ldst_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _ldq_debug_wb_data_shifted_T_6 = wb_ldst_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire [7:0] _iresp_0_bits_data_shifted_T_7 = _iresp_0_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _iresp_0_bits_data_shifted_T_8 = _iresp_0_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] iresp_0_bits_data_shifted_2 = _iresp_0_bits_data_shifted_T_6 ? _iresp_0_bits_data_shifted_T_7 : _iresp_0_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] iresp_0_bits_data_zeroed_2 = iresp_0_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _GEN_640 = size_1 == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _iresp_0_bits_data_T_16; // @[AMOALU.scala:45:26] assign _iresp_0_bits_data_T_16 = _GEN_640; // @[AMOALU.scala:45:26] wire _fresp_0_bits_data_T_16; // @[AMOALU.scala:45:26] assign _fresp_0_bits_data_T_16 = _GEN_640; // @[AMOALU.scala:45:26] wire _ldq_debug_wb_data_T_16; // @[AMOALU.scala:45:26] assign _ldq_debug_wb_data_T_16 = _GEN_640; // @[AMOALU.scala:45:26] wire _iresp_0_bits_data_T_17 = _iresp_0_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _iresp_0_bits_data_T_18 = iresp_0_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _iresp_0_bits_data_T_19 = wb_ldst_forward_e_0_uop_mem_signed & _iresp_0_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _iresp_0_bits_data_T_20 = {56{_iresp_0_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _iresp_0_bits_data_T_21 = _iresp_0_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _iresp_0_bits_data_T_22 = _iresp_0_bits_data_T_17 ? _iresp_0_bits_data_T_20 : _iresp_0_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _iresp_0_bits_data_T_23 = {_iresp_0_bits_data_T_22, iresp_0_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign iresp_0_bits_data = _GEN_526 ? resp_data : _iresp_0_bits_data_T_23; // @[AMOALU.scala:45:16] wire [31:0] fresp_0_bits_data_shifted = _fresp_0_bits_data_shifted_T ? _fresp_0_bits_data_shifted_T_1 : _fresp_0_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] fresp_0_bits_data_zeroed = fresp_0_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _fresp_0_bits_data_T_1 = _fresp_0_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _fresp_0_bits_data_T_2 = fresp_0_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _fresp_0_bits_data_T_3 = wb_ldst_forward_e_0_uop_mem_signed & _fresp_0_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _fresp_0_bits_data_T_4 = {32{_fresp_0_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _fresp_0_bits_data_T_6 = _fresp_0_bits_data_T_1 ? _fresp_0_bits_data_T_4 : _fresp_0_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _fresp_0_bits_data_T_7 = {_fresp_0_bits_data_T_6, fresp_0_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _fresp_0_bits_data_shifted_T_4 = _fresp_0_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _fresp_0_bits_data_shifted_T_5 = _fresp_0_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] fresp_0_bits_data_shifted_1 = _fresp_0_bits_data_shifted_T_3 ? _fresp_0_bits_data_shifted_T_4 : _fresp_0_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] fresp_0_bits_data_zeroed_1 = fresp_0_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _fresp_0_bits_data_T_9 = _fresp_0_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _fresp_0_bits_data_T_10 = fresp_0_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _fresp_0_bits_data_T_11 = wb_ldst_forward_e_0_uop_mem_signed & _fresp_0_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _fresp_0_bits_data_T_12 = {48{_fresp_0_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _fresp_0_bits_data_T_13 = _fresp_0_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _fresp_0_bits_data_T_14 = _fresp_0_bits_data_T_9 ? _fresp_0_bits_data_T_12 : _fresp_0_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _fresp_0_bits_data_T_15 = {_fresp_0_bits_data_T_14, fresp_0_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _fresp_0_bits_data_shifted_T_7 = _fresp_0_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _fresp_0_bits_data_shifted_T_8 = _fresp_0_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] fresp_0_bits_data_shifted_2 = _fresp_0_bits_data_shifted_T_6 ? _fresp_0_bits_data_shifted_T_7 : _fresp_0_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] fresp_0_bits_data_zeroed_2 = fresp_0_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _fresp_0_bits_data_T_17 = _fresp_0_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _fresp_0_bits_data_T_18 = fresp_0_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _fresp_0_bits_data_T_19 = wb_ldst_forward_e_0_uop_mem_signed & _fresp_0_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _fresp_0_bits_data_T_20 = {56{_fresp_0_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _fresp_0_bits_data_T_21 = _fresp_0_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _fresp_0_bits_data_T_22 = _fresp_0_bits_data_T_17 ? _fresp_0_bits_data_T_20 : _fresp_0_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _fresp_0_bits_data_T_23 = {_fresp_0_bits_data_T_22, fresp_0_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign fresp_0_bits_data = _GEN_526 ? resp_data : _fresp_0_bits_data_T_23; // @[AMOALU.scala:45:16] wire _GEN_641 = _T_1178 & _GEN_488; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_642 = ~_T_1176 & _GEN_641; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_0 = _GEN_642 | (_GEN_507 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_60 & ldq_succeeded_0 : ~_GEN_28 & ldq_succeeded_0); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_643 = _T_1178 & _GEN_489; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_644 = ~_T_1176 & _GEN_643; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_1 = _GEN_644 | (_GEN_508 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_61 & ldq_succeeded_1 : ~_GEN_29 & ldq_succeeded_1); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_645 = _T_1178 & _GEN_490; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_646 = ~_T_1176 & _GEN_645; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_2 = _GEN_646 | (_GEN_509 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_62 & ldq_succeeded_2 : ~_GEN_30 & ldq_succeeded_2); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_647 = _T_1178 & _GEN_491; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_648 = ~_T_1176 & _GEN_647; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_3 = _GEN_648 | (_GEN_510 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_63 & ldq_succeeded_3 : ~_GEN_31 & ldq_succeeded_3); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_649 = _T_1178 & _GEN_492; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_650 = ~_T_1176 & _GEN_649; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_4 = _GEN_650 | (_GEN_511 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_64 & ldq_succeeded_4 : ~_GEN_32 & ldq_succeeded_4); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_651 = _T_1178 & _GEN_493; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_652 = ~_T_1176 & _GEN_651; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_5 = _GEN_652 | (_GEN_512 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_65 & ldq_succeeded_5 : ~_GEN_33 & ldq_succeeded_5); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_653 = _T_1178 & _GEN_494; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_654 = ~_T_1176 & _GEN_653; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_6 = _GEN_654 | (_GEN_513 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_66 & ldq_succeeded_6 : ~_GEN_34 & ldq_succeeded_6); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_655 = _T_1178 & _GEN_495; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_656 = ~_T_1176 & _GEN_655; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_7 = _GEN_656 | (_GEN_514 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_67 & ldq_succeeded_7 : ~_GEN_35 & ldq_succeeded_7); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_657 = _T_1178 & _GEN_496; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_658 = ~_T_1176 & _GEN_657; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_8 = _GEN_658 | (_GEN_515 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_68 & ldq_succeeded_8 : ~_GEN_36 & ldq_succeeded_8); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_659 = _T_1178 & _GEN_497; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_660 = ~_T_1176 & _GEN_659; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_9 = _GEN_660 | (_GEN_516 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_69 & ldq_succeeded_9 : ~_GEN_37 & ldq_succeeded_9); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_661 = _T_1178 & _GEN_498; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_662 = ~_T_1176 & _GEN_661; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_10 = _GEN_662 | (_GEN_517 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_70 & ldq_succeeded_10 : ~_GEN_38 & ldq_succeeded_10); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_663 = _T_1178 & _GEN_499; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_664 = ~_T_1176 & _GEN_663; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_11 = _GEN_664 | (_GEN_518 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_71 & ldq_succeeded_11 : ~_GEN_39 & ldq_succeeded_11); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_665 = _T_1178 & _GEN_500; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_666 = ~_T_1176 & _GEN_665; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_12 = _GEN_666 | (_GEN_519 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_72 & ldq_succeeded_12 : ~_GEN_40 & ldq_succeeded_12); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_667 = _T_1178 & _GEN_501; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_668 = ~_T_1176 & _GEN_667; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_13 = _GEN_668 | (_GEN_520 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_73 & ldq_succeeded_13 : ~_GEN_41 & ldq_succeeded_13); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_669 = _T_1178 & _GEN_502; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_670 = ~_T_1176 & _GEN_669; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_14 = _GEN_670 | (_GEN_521 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_74 & ldq_succeeded_14 : ~_GEN_42 & ldq_succeeded_14); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_671 = _T_1178 & (&wb_ldst_forward_ldq_idx_0); // @[lsu.scala:1174:41, :1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_672 = ~_T_1176 & _GEN_671; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_15 = _GEN_672 | (_GEN_522 ? _ldq_will_succeed_T : _T_60 ? ~_GEN_75 & ldq_succeeded_15 : ~_GEN_43 & ldq_succeeded_15); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire [31:0] ldq_debug_wb_data_shifted = _ldq_debug_wb_data_shifted_T ? _ldq_debug_wb_data_shifted_T_1 : _ldq_debug_wb_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] ldq_debug_wb_data_zeroed = ldq_debug_wb_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _ldq_debug_wb_data_T_1 = _ldq_debug_wb_data_T; // @[AMOALU.scala:45:{26,34}] wire _ldq_debug_wb_data_T_2 = ldq_debug_wb_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_debug_wb_data_T_3 = wb_ldst_forward_e_0_uop_mem_signed & _ldq_debug_wb_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _ldq_debug_wb_data_T_4 = {32{_ldq_debug_wb_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _ldq_debug_wb_data_T_6 = _ldq_debug_wb_data_T_1 ? _ldq_debug_wb_data_T_4 : _ldq_debug_wb_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_debug_wb_data_T_7 = {_ldq_debug_wb_data_T_6, ldq_debug_wb_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _ldq_debug_wb_data_shifted_T_4 = _ldq_debug_wb_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _ldq_debug_wb_data_shifted_T_5 = _ldq_debug_wb_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] ldq_debug_wb_data_shifted_1 = _ldq_debug_wb_data_shifted_T_3 ? _ldq_debug_wb_data_shifted_T_4 : _ldq_debug_wb_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] ldq_debug_wb_data_zeroed_1 = ldq_debug_wb_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _ldq_debug_wb_data_T_9 = _ldq_debug_wb_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _ldq_debug_wb_data_T_10 = ldq_debug_wb_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_debug_wb_data_T_11 = wb_ldst_forward_e_0_uop_mem_signed & _ldq_debug_wb_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _ldq_debug_wb_data_T_12 = {48{_ldq_debug_wb_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _ldq_debug_wb_data_T_13 = _ldq_debug_wb_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _ldq_debug_wb_data_T_14 = _ldq_debug_wb_data_T_9 ? _ldq_debug_wb_data_T_12 : _ldq_debug_wb_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_debug_wb_data_T_15 = {_ldq_debug_wb_data_T_14, ldq_debug_wb_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _ldq_debug_wb_data_shifted_T_7 = _ldq_debug_wb_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _ldq_debug_wb_data_shifted_T_8 = _ldq_debug_wb_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] ldq_debug_wb_data_shifted_2 = _ldq_debug_wb_data_shifted_T_6 ? _ldq_debug_wb_data_shifted_T_7 : _ldq_debug_wb_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] ldq_debug_wb_data_zeroed_2 = ldq_debug_wb_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _ldq_debug_wb_data_T_17 = _ldq_debug_wb_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _ldq_debug_wb_data_T_18 = ldq_debug_wb_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_debug_wb_data_T_19 = wb_ldst_forward_e_0_uop_mem_signed & _ldq_debug_wb_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _ldq_debug_wb_data_T_20 = {56{_ldq_debug_wb_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _ldq_debug_wb_data_T_21 = _ldq_debug_wb_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _ldq_debug_wb_data_T_22 = _ldq_debug_wb_data_T_17 ? _ldq_debug_wb_data_T_20 : _ldq_debug_wb_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_debug_wb_data_T_23 = {_ldq_debug_wb_data_T_22, ldq_debug_wb_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _slow_wakeups_0_out_valid_T_4; // @[util.scala:116:31] wire [11:0] _slow_wakeups_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] slow_wakeups_0_out_bits_uop_br_mask; // @[util.scala:114:23] wire slow_wakeups_0_out_valid; // @[util.scala:114:23] wire [11:0] _slow_wakeups_0_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _slow_wakeups_0_out_bits_uop_br_mask_T_1 = wb_slow_wakeups_0_bits_uop_br_mask & _slow_wakeups_0_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign slow_wakeups_0_out_bits_uop_br_mask = _slow_wakeups_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [11:0] _slow_wakeups_0_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & wb_slow_wakeups_0_bits_uop_br_mask; // @[util.scala:126:51] wire _slow_wakeups_0_out_valid_T_1 = |_slow_wakeups_0_out_valid_T; // @[util.scala:126:{51,59}] wire _slow_wakeups_0_out_valid_T_2 = _slow_wakeups_0_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _slow_wakeups_0_out_valid_T_3 = ~_slow_wakeups_0_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _slow_wakeups_0_out_valid_T_4 = wb_slow_wakeups_0_valid & _slow_wakeups_0_out_valid_T_3; // @[util.scala:116:{31,34}] assign slow_wakeups_0_out_valid = _slow_wakeups_0_out_valid_T_4; // @[util.scala:114:23, :116:31] reg slow_wakeups_0_REG_valid; // @[lsu.scala:1647:79] assign slow_wakeups_0_valid = slow_wakeups_0_REG_valid; // @[lsu.scala:1495:26, :1647:79] reg [31:0] slow_wakeups_0_REG_bits_uop_inst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_inst = slow_wakeups_0_REG_bits_uop_inst; // @[lsu.scala:1495:26, :1647:79] reg [31:0] slow_wakeups_0_REG_bits_uop_debug_inst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_inst = slow_wakeups_0_REG_bits_uop_debug_inst; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_rvc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_rvc = slow_wakeups_0_REG_bits_uop_is_rvc; // @[lsu.scala:1495:26, :1647:79] reg [39:0] slow_wakeups_0_REG_bits_uop_debug_pc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_pc = slow_wakeups_0_REG_bits_uop_debug_pc; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_0; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_0 = slow_wakeups_0_REG_bits_uop_iq_type_0; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_1 = slow_wakeups_0_REG_bits_uop_iq_type_1; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_2 = slow_wakeups_0_REG_bits_uop_iq_type_2; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_3 = slow_wakeups_0_REG_bits_uop_iq_type_3; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_0; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_0 = slow_wakeups_0_REG_bits_uop_fu_code_0; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_1 = slow_wakeups_0_REG_bits_uop_fu_code_1; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_2 = slow_wakeups_0_REG_bits_uop_fu_code_2; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_3 = slow_wakeups_0_REG_bits_uop_fu_code_3; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_4; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_4 = slow_wakeups_0_REG_bits_uop_fu_code_4; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_5; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_5 = slow_wakeups_0_REG_bits_uop_fu_code_5; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_6; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_6 = slow_wakeups_0_REG_bits_uop_fu_code_6; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_7; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_7 = slow_wakeups_0_REG_bits_uop_fu_code_7; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_8; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_8 = slow_wakeups_0_REG_bits_uop_fu_code_8; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_9; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_9 = slow_wakeups_0_REG_bits_uop_fu_code_9; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_issued; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_issued = slow_wakeups_0_REG_bits_uop_iw_issued; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_issued_partial_agen = slow_wakeups_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_issued_partial_dgen = slow_wakeups_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p1_speculative_child = slow_wakeups_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p2_speculative_child = slow_wakeups_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p1_bypass_hint = slow_wakeups_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p2_bypass_hint = slow_wakeups_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p3_bypass_hint = slow_wakeups_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_dis_col_sel = slow_wakeups_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:1495:26, :1647:79] reg [11:0] slow_wakeups_0_REG_bits_uop_br_mask; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_br_mask = slow_wakeups_0_REG_bits_uop_br_mask; // @[lsu.scala:1495:26, :1647:79] reg [3:0] slow_wakeups_0_REG_bits_uop_br_tag; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_br_tag = slow_wakeups_0_REG_bits_uop_br_tag; // @[lsu.scala:1495:26, :1647:79] reg [3:0] slow_wakeups_0_REG_bits_uop_br_type; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_br_type = slow_wakeups_0_REG_bits_uop_br_type; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_sfb; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_sfb = slow_wakeups_0_REG_bits_uop_is_sfb; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_fence; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_fence = slow_wakeups_0_REG_bits_uop_is_fence; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_fencei; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_fencei = slow_wakeups_0_REG_bits_uop_is_fencei; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_sfence; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_sfence = slow_wakeups_0_REG_bits_uop_is_sfence; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_amo; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_amo = slow_wakeups_0_REG_bits_uop_is_amo; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_eret; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_eret = slow_wakeups_0_REG_bits_uop_is_eret; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_sys_pc2epc = slow_wakeups_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_rocc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_rocc = slow_wakeups_0_REG_bits_uop_is_rocc; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_mov; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_mov = slow_wakeups_0_REG_bits_uop_is_mov; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_ftq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ftq_idx = slow_wakeups_0_REG_bits_uop_ftq_idx; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_edge_inst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_edge_inst = slow_wakeups_0_REG_bits_uop_edge_inst; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_pc_lob; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_pc_lob = slow_wakeups_0_REG_bits_uop_pc_lob; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_taken; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_taken = slow_wakeups_0_REG_bits_uop_taken; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_imm_rename; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_imm_rename = slow_wakeups_0_REG_bits_uop_imm_rename; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_imm_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_imm_sel = slow_wakeups_0_REG_bits_uop_imm_sel; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_pimm; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_pimm = slow_wakeups_0_REG_bits_uop_pimm; // @[lsu.scala:1495:26, :1647:79] reg [19:0] slow_wakeups_0_REG_bits_uop_imm_packed; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_imm_packed = slow_wakeups_0_REG_bits_uop_imm_packed; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_op1_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_op1_sel = slow_wakeups_0_REG_bits_uop_op1_sel; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_op2_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_op2_sel = slow_wakeups_0_REG_bits_uop_op2_sel; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ldst = slow_wakeups_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_wen = slow_wakeups_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ren1 = slow_wakeups_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ren2 = slow_wakeups_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ren3 = slow_wakeups_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_swap12 = slow_wakeups_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_swap23 = slow_wakeups_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn = slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut = slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_fromint = slow_wakeups_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_toint = slow_wakeups_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_fastpipe = slow_wakeups_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_fma = slow_wakeups_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_div = slow_wakeups_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_sqrt = slow_wakeups_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_wflags = slow_wakeups_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_vec = slow_wakeups_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_rob_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_rob_idx = slow_wakeups_0_REG_bits_uop_rob_idx; // @[lsu.scala:1495:26, :1647:79] reg [3:0] slow_wakeups_0_REG_bits_uop_ldq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ldq_idx = slow_wakeups_0_REG_bits_uop_ldq_idx; // @[lsu.scala:1495:26, :1647:79] reg [3:0] slow_wakeups_0_REG_bits_uop_stq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_stq_idx = slow_wakeups_0_REG_bits_uop_stq_idx; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_rxq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_rxq_idx = slow_wakeups_0_REG_bits_uop_rxq_idx; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_pdst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_pdst = slow_wakeups_0_REG_bits_uop_pdst; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_prs1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs1 = slow_wakeups_0_REG_bits_uop_prs1; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_prs2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs2 = slow_wakeups_0_REG_bits_uop_prs2; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_prs3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs3 = slow_wakeups_0_REG_bits_uop_prs3; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_ppred; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ppred = slow_wakeups_0_REG_bits_uop_ppred; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_prs1_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs1_busy = slow_wakeups_0_REG_bits_uop_prs1_busy; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_prs2_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs2_busy = slow_wakeups_0_REG_bits_uop_prs2_busy; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_prs3_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs3_busy = slow_wakeups_0_REG_bits_uop_prs3_busy; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_ppred_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ppred_busy = slow_wakeups_0_REG_bits_uop_ppred_busy; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_stale_pdst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_stale_pdst = slow_wakeups_0_REG_bits_uop_stale_pdst; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_exception; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_exception = slow_wakeups_0_REG_bits_uop_exception; // @[lsu.scala:1495:26, :1647:79] reg [63:0] slow_wakeups_0_REG_bits_uop_exc_cause; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_exc_cause = slow_wakeups_0_REG_bits_uop_exc_cause; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_mem_cmd; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_mem_cmd = slow_wakeups_0_REG_bits_uop_mem_cmd; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_mem_size; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_mem_size = slow_wakeups_0_REG_bits_uop_mem_size; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_mem_signed; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_mem_signed = slow_wakeups_0_REG_bits_uop_mem_signed; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_uses_ldq; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_uses_ldq = slow_wakeups_0_REG_bits_uop_uses_ldq; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_uses_stq; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_uses_stq = slow_wakeups_0_REG_bits_uop_uses_stq; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_unique; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_unique = slow_wakeups_0_REG_bits_uop_is_unique; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_flush_on_commit = slow_wakeups_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_csr_cmd; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_csr_cmd = slow_wakeups_0_REG_bits_uop_csr_cmd; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ldst_is_rs1 = slow_wakeups_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_ldst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ldst = slow_wakeups_0_REG_bits_uop_ldst; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_lrs1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs1 = slow_wakeups_0_REG_bits_uop_lrs1; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_lrs2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs2 = slow_wakeups_0_REG_bits_uop_lrs2; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_lrs3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs3 = slow_wakeups_0_REG_bits_uop_lrs3; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_dst_rtype; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_dst_rtype = slow_wakeups_0_REG_bits_uop_dst_rtype; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs1_rtype = slow_wakeups_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs2_rtype = slow_wakeups_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_frs3_en; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_frs3_en = slow_wakeups_0_REG_bits_uop_frs3_en; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fcn_dw; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fcn_dw = slow_wakeups_0_REG_bits_uop_fcn_dw; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_fcn_op; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fcn_op = slow_wakeups_0_REG_bits_uop_fcn_op; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_val; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_val = slow_wakeups_0_REG_bits_uop_fp_val; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_fp_rm; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_rm = slow_wakeups_0_REG_bits_uop_fp_rm; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_fp_typ; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_typ = slow_wakeups_0_REG_bits_uop_fp_typ; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_xcpt_pf_if = slow_wakeups_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_xcpt_ae_if = slow_wakeups_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_xcpt_ma_if = slow_wakeups_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_bp_debug_if = slow_wakeups_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_bp_xcpt_if = slow_wakeups_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_fsrc = slow_wakeups_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_tsrc = slow_wakeups_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:1495:26, :1647:79] wire [11:0] _stq_uop_0_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_0_br_mask_T_1 = uop_1_br_mask & _stq_uop_0_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_1_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_1_br_mask_T_1 = uop_2_br_mask & _stq_uop_1_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_2_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_2_br_mask_T_1 = uop_3_br_mask & _stq_uop_2_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_3_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_3_br_mask_T_1 = uop_4_br_mask & _stq_uop_3_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_4_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_4_br_mask_T_1 = uop_5_br_mask & _stq_uop_4_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_5_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_5_br_mask_T_1 = uop_6_br_mask & _stq_uop_5_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_6_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_6_br_mask_T_1 = uop_7_br_mask & _stq_uop_6_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_7_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_7_br_mask_T_1 = uop_8_br_mask & _stq_uop_7_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_8_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_8_br_mask_T_1 = uop_9_br_mask & _stq_uop_8_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_9_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_9_br_mask_T_1 = uop_10_br_mask & _stq_uop_9_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_10_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_10_br_mask_T_1 = uop_11_br_mask & _stq_uop_10_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_11_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_11_br_mask_T_1 = uop_12_br_mask & _stq_uop_11_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_12_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_12_br_mask_T_1 = uop_13_br_mask & _stq_uop_12_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_13_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_13_br_mask_T_1 = uop_14_br_mask & _stq_uop_13_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_14_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_14_br_mask_T_1 = uop_15_br_mask & _stq_uop_14_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _stq_uop_15_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _stq_uop_15_br_mask_T_1 = uop_16_br_mask & _stq_uop_15_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_0_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_0_br_mask_T_1 = uop_17_br_mask & _ldq_uop_0_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_1_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_1_br_mask_T_1 = uop_18_br_mask & _ldq_uop_1_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_2_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_2_br_mask_T_1 = uop_19_br_mask & _ldq_uop_2_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_3_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_3_br_mask_T_1 = uop_20_br_mask & _ldq_uop_3_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_4_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_4_br_mask_T_1 = uop_21_br_mask & _ldq_uop_4_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_5_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_5_br_mask_T_1 = uop_22_br_mask & _ldq_uop_5_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_6_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_6_br_mask_T_1 = uop_23_br_mask & _ldq_uop_6_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_7_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_7_br_mask_T_1 = uop_24_br_mask & _ldq_uop_7_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_8_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_8_br_mask_T_1 = uop_25_br_mask & _ldq_uop_8_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_9_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_9_br_mask_T_1 = uop_26_br_mask & _ldq_uop_9_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_10_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_10_br_mask_T_1 = uop_27_br_mask & _ldq_uop_10_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_11_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_11_br_mask_T_1 = uop_28_br_mask & _ldq_uop_11_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_12_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_12_br_mask_T_1 = uop_29_br_mask & _ldq_uop_12_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_13_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_13_br_mask_T_1 = uop_30_br_mask & _ldq_uop_13_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_14_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_14_br_mask_T_1 = uop_31_br_mask & _ldq_uop_14_br_mask_T; // @[util.scala:97:{21,23}] wire [11:0] _ldq_uop_15_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [11:0] _ldq_uop_15_br_mask_T_1 = uop_32_br_mask & _ldq_uop_15_br_mask_T; // @[util.scala:97:{21,23}] wire commit_store = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_stq_0; // @[lsu.scala:211:7, :1724:49] wire commit_load = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_ldq_0; // @[lsu.scala:211:7, :1725:49] wire l_uop_16_iq_type_0; // @[lsu.scala:1728:25] wire l_uop_16_iq_type_1; // @[lsu.scala:1728:25] wire l_uop_16_iq_type_2; // @[lsu.scala:1728:25] wire l_uop_16_iq_type_3; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_0; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_1; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_2; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_3; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_4; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_5; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_6; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_7; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_8; // @[lsu.scala:1728:25] wire l_uop_16_fu_code_9; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_ldst; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_wen; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_ren1; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_ren2; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_ren3; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_swap12; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_swap23; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_fromint; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_toint; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_fma; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_div; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_sqrt; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_wflags; // @[lsu.scala:1728:25] wire l_uop_16_fp_ctrl_vec; // @[lsu.scala:1728:25] wire [31:0] l_uop_16_inst; // @[lsu.scala:1728:25] wire [31:0] l_uop_16_debug_inst; // @[lsu.scala:1728:25] wire l_uop_16_is_rvc; // @[lsu.scala:1728:25] wire [39:0] l_uop_16_debug_pc; // @[lsu.scala:1728:25] wire l_uop_16_iw_issued; // @[lsu.scala:1728:25] wire l_uop_16_iw_issued_partial_agen; // @[lsu.scala:1728:25] wire l_uop_16_iw_issued_partial_dgen; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_iw_p1_speculative_child; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_iw_p2_speculative_child; // @[lsu.scala:1728:25] wire l_uop_16_iw_p1_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_16_iw_p2_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_16_iw_p3_bypass_hint; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_dis_col_sel; // @[lsu.scala:1728:25] wire [11:0] l_uop_16_br_mask; // @[lsu.scala:1728:25] wire [3:0] l_uop_16_br_tag; // @[lsu.scala:1728:25] wire [3:0] l_uop_16_br_type; // @[lsu.scala:1728:25] wire l_uop_16_is_sfb; // @[lsu.scala:1728:25] wire l_uop_16_is_fence; // @[lsu.scala:1728:25] wire l_uop_16_is_fencei; // @[lsu.scala:1728:25] wire l_uop_16_is_sfence; // @[lsu.scala:1728:25] wire l_uop_16_is_amo; // @[lsu.scala:1728:25] wire l_uop_16_is_eret; // @[lsu.scala:1728:25] wire l_uop_16_is_sys_pc2epc; // @[lsu.scala:1728:25] wire l_uop_16_is_rocc; // @[lsu.scala:1728:25] wire l_uop_16_is_mov; // @[lsu.scala:1728:25] wire [4:0] l_uop_16_ftq_idx; // @[lsu.scala:1728:25] wire l_uop_16_edge_inst; // @[lsu.scala:1728:25] wire [5:0] l_uop_16_pc_lob; // @[lsu.scala:1728:25] wire l_uop_16_taken; // @[lsu.scala:1728:25] wire l_uop_16_imm_rename; // @[lsu.scala:1728:25] wire [2:0] l_uop_16_imm_sel; // @[lsu.scala:1728:25] wire [4:0] l_uop_16_pimm; // @[lsu.scala:1728:25] wire [19:0] l_uop_16_imm_packed; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_op1_sel; // @[lsu.scala:1728:25] wire [2:0] l_uop_16_op2_sel; // @[lsu.scala:1728:25] wire [5:0] l_uop_16_rob_idx; // @[lsu.scala:1728:25] wire [3:0] l_uop_16_ldq_idx; // @[lsu.scala:1728:25] wire [3:0] l_uop_16_stq_idx; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_rxq_idx; // @[lsu.scala:1728:25] wire [6:0] l_uop_16_pdst; // @[lsu.scala:1728:25] wire [6:0] l_uop_16_prs1; // @[lsu.scala:1728:25] wire [6:0] l_uop_16_prs2; // @[lsu.scala:1728:25] wire [6:0] l_uop_16_prs3; // @[lsu.scala:1728:25] wire [4:0] l_uop_16_ppred; // @[lsu.scala:1728:25] wire l_uop_16_prs1_busy; // @[lsu.scala:1728:25] wire l_uop_16_prs2_busy; // @[lsu.scala:1728:25] wire l_uop_16_prs3_busy; // @[lsu.scala:1728:25] wire l_uop_16_ppred_busy; // @[lsu.scala:1728:25] wire [6:0] l_uop_16_stale_pdst; // @[lsu.scala:1728:25] wire l_uop_16_exception; // @[lsu.scala:1728:25] wire [63:0] l_uop_16_exc_cause; // @[lsu.scala:1728:25] wire [4:0] l_uop_16_mem_cmd; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_mem_size; // @[lsu.scala:1728:25] wire l_uop_16_mem_signed; // @[lsu.scala:1728:25] wire l_uop_16_uses_ldq; // @[lsu.scala:1728:25] wire l_uop_16_uses_stq; // @[lsu.scala:1728:25] wire l_uop_16_is_unique; // @[lsu.scala:1728:25] wire l_uop_16_flush_on_commit; // @[lsu.scala:1728:25] wire [2:0] l_uop_16_csr_cmd; // @[lsu.scala:1728:25] wire l_uop_16_ldst_is_rs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_16_ldst; // @[lsu.scala:1728:25] wire [5:0] l_uop_16_lrs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_16_lrs2; // @[lsu.scala:1728:25] wire [5:0] l_uop_16_lrs3; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_dst_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_lrs1_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_lrs2_rtype; // @[lsu.scala:1728:25] wire l_uop_16_frs3_en; // @[lsu.scala:1728:25] wire l_uop_16_fcn_dw; // @[lsu.scala:1728:25] wire [4:0] l_uop_16_fcn_op; // @[lsu.scala:1728:25] wire l_uop_16_fp_val; // @[lsu.scala:1728:25] wire [2:0] l_uop_16_fp_rm; // @[lsu.scala:1728:25] wire [1:0] l_uop_16_fp_typ; // @[lsu.scala:1728:25] wire l_uop_16_xcpt_pf_if; // @[lsu.scala:1728:25] wire l_uop_16_xcpt_ae_if; // @[lsu.scala:1728:25] wire l_uop_16_xcpt_ma_if; // @[lsu.scala:1728:25] wire l_uop_16_bp_debug_if; // @[lsu.scala:1728:25] wire l_uop_16_bp_xcpt_if; // @[lsu.scala:1728:25] wire [2:0] l_uop_16_debug_fsrc; // @[lsu.scala:1728:25] wire [2:0] l_uop_16_debug_tsrc; // @[lsu.scala:1728:25] assign l_uop_16_inst = _GEN_76[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_debug_inst = _GEN_77[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_rvc = _GEN_78[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_debug_pc = _GEN_79[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iq_type_0 = _GEN_80[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iq_type_1 = _GEN_81[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iq_type_2 = _GEN_82[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iq_type_3 = _GEN_83[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_0 = _GEN_84[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_1 = _GEN_85[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_2 = _GEN_86[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_3 = _GEN_87[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_4 = _GEN_88[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_5 = _GEN_89[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_6 = _GEN_90[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_7 = _GEN_91[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_8 = _GEN_92[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fu_code_9 = _GEN_93[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_issued = _GEN_94[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_issued_partial_agen = _GEN_95[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_issued_partial_dgen = _GEN_96[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_p1_speculative_child = _GEN_97[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_p2_speculative_child = _GEN_98[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_p1_bypass_hint = _GEN_99[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_p2_bypass_hint = _GEN_100[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_iw_p3_bypass_hint = _GEN_101[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_dis_col_sel = _GEN_102[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_br_mask = _GEN_103[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_br_tag = _GEN_104[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_br_type = _GEN_105[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_sfb = _GEN_106[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_fence = _GEN_107[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_fencei = _GEN_108[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_sfence = _GEN_109[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_amo = _GEN_110[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_eret = _GEN_111[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_sys_pc2epc = _GEN_112[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_rocc = _GEN_113[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_mov = _GEN_114[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_ftq_idx = _GEN_115[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_edge_inst = _GEN_116[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_pc_lob = _GEN_117[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_taken = _GEN_118[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_imm_rename = _GEN_119[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_imm_sel = _GEN_120[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_pimm = _GEN_121[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_imm_packed = _GEN_122[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_op1_sel = _GEN_123[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_op2_sel = _GEN_124[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_ldst = _GEN_125[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_wen = _GEN_126[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_ren1 = _GEN_127[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_ren2 = _GEN_128[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_ren3 = _GEN_129[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_swap12 = _GEN_130[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_swap23 = _GEN_131[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_typeTagIn = _GEN_132[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_typeTagOut = _GEN_133[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_fromint = _GEN_134[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_toint = _GEN_135[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_fastpipe = _GEN_136[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_fma = _GEN_137[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_div = _GEN_138[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_sqrt = _GEN_139[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_wflags = _GEN_140[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_ctrl_vec = _GEN_141[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_rob_idx = _GEN_142[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_ldq_idx = _GEN_143[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_stq_idx = _GEN_144[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_rxq_idx = _GEN_145[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_pdst = _GEN_146[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_prs1 = _GEN_147[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_prs2 = _GEN_148[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_prs3 = _GEN_149[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_ppred = _GEN_150[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_prs1_busy = _GEN_151[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_prs2_busy = _GEN_152[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_prs3_busy = _GEN_153[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_ppred_busy = _GEN_154[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_stale_pdst = _GEN_155[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_exception = _GEN_156[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_exc_cause = _GEN_157[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_mem_cmd = _GEN_158[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_mem_size = _GEN_159[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_mem_signed = _GEN_160[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_uses_ldq = _GEN_161[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_uses_stq = _GEN_162[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_is_unique = _GEN_163[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_flush_on_commit = _GEN_164[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_csr_cmd = _GEN_165[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_ldst_is_rs1 = _GEN_166[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_ldst = _GEN_167[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_lrs1 = _GEN_168[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_lrs2 = _GEN_169[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_lrs3 = _GEN_170[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_dst_rtype = _GEN_171[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_lrs1_rtype = _GEN_172[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_lrs2_rtype = _GEN_173[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_frs3_en = _GEN_174[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fcn_dw = _GEN_175[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fcn_op = _GEN_176[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_val = _GEN_177[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_rm = _GEN_178[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_fp_typ = _GEN_179[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_xcpt_pf_if = _GEN_180[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_xcpt_ae_if = _GEN_181[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_xcpt_ma_if = _GEN_182[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_bp_debug_if = _GEN_183[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_bp_xcpt_if = _GEN_184[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_debug_fsrc = _GEN_185[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_16_debug_tsrc = _GEN_186[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] wire s_uop_18_iq_type_0; // @[lsu.scala:1729:25] wire s_uop_18_iq_type_1; // @[lsu.scala:1729:25] wire s_uop_18_iq_type_2; // @[lsu.scala:1729:25] wire s_uop_18_iq_type_3; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_0; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_1; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_2; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_3; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_4; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_5; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_6; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_7; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_8; // @[lsu.scala:1729:25] wire s_uop_18_fu_code_9; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_ldst; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_wen; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_ren1; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_ren2; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_ren3; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_swap12; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_swap23; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_fromint; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_toint; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_fma; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_div; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_sqrt; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_wflags; // @[lsu.scala:1729:25] wire s_uop_18_fp_ctrl_vec; // @[lsu.scala:1729:25] wire [31:0] s_uop_18_inst; // @[lsu.scala:1729:25] wire [31:0] s_uop_18_debug_inst; // @[lsu.scala:1729:25] wire s_uop_18_is_rvc; // @[lsu.scala:1729:25] wire [39:0] s_uop_18_debug_pc; // @[lsu.scala:1729:25] wire s_uop_18_iw_issued; // @[lsu.scala:1729:25] wire s_uop_18_iw_issued_partial_agen; // @[lsu.scala:1729:25] wire s_uop_18_iw_issued_partial_dgen; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_iw_p1_speculative_child; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_iw_p2_speculative_child; // @[lsu.scala:1729:25] wire s_uop_18_iw_p1_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_18_iw_p2_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_18_iw_p3_bypass_hint; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_dis_col_sel; // @[lsu.scala:1729:25] wire [11:0] s_uop_18_br_mask; // @[lsu.scala:1729:25] wire [3:0] s_uop_18_br_tag; // @[lsu.scala:1729:25] wire [3:0] s_uop_18_br_type; // @[lsu.scala:1729:25] wire s_uop_18_is_sfb; // @[lsu.scala:1729:25] wire s_uop_18_is_fence; // @[lsu.scala:1729:25] wire s_uop_18_is_fencei; // @[lsu.scala:1729:25] wire s_uop_18_is_sfence; // @[lsu.scala:1729:25] wire s_uop_18_is_amo; // @[lsu.scala:1729:25] wire s_uop_18_is_eret; // @[lsu.scala:1729:25] wire s_uop_18_is_sys_pc2epc; // @[lsu.scala:1729:25] wire s_uop_18_is_rocc; // @[lsu.scala:1729:25] wire s_uop_18_is_mov; // @[lsu.scala:1729:25] wire [4:0] s_uop_18_ftq_idx; // @[lsu.scala:1729:25] wire s_uop_18_edge_inst; // @[lsu.scala:1729:25] wire [5:0] s_uop_18_pc_lob; // @[lsu.scala:1729:25] wire s_uop_18_taken; // @[lsu.scala:1729:25] wire s_uop_18_imm_rename; // @[lsu.scala:1729:25] wire [2:0] s_uop_18_imm_sel; // @[lsu.scala:1729:25] wire [4:0] s_uop_18_pimm; // @[lsu.scala:1729:25] wire [19:0] s_uop_18_imm_packed; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_op1_sel; // @[lsu.scala:1729:25] wire [2:0] s_uop_18_op2_sel; // @[lsu.scala:1729:25] wire [5:0] s_uop_18_rob_idx; // @[lsu.scala:1729:25] wire [3:0] s_uop_18_ldq_idx; // @[lsu.scala:1729:25] wire [3:0] s_uop_18_stq_idx; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_rxq_idx; // @[lsu.scala:1729:25] wire [6:0] s_uop_18_pdst; // @[lsu.scala:1729:25] wire [6:0] s_uop_18_prs1; // @[lsu.scala:1729:25] wire [6:0] s_uop_18_prs2; // @[lsu.scala:1729:25] wire [6:0] s_uop_18_prs3; // @[lsu.scala:1729:25] wire [4:0] s_uop_18_ppred; // @[lsu.scala:1729:25] wire s_uop_18_prs1_busy; // @[lsu.scala:1729:25] wire s_uop_18_prs2_busy; // @[lsu.scala:1729:25] wire s_uop_18_prs3_busy; // @[lsu.scala:1729:25] wire s_uop_18_ppred_busy; // @[lsu.scala:1729:25] wire [6:0] s_uop_18_stale_pdst; // @[lsu.scala:1729:25] wire s_uop_18_exception; // @[lsu.scala:1729:25] wire [63:0] s_uop_18_exc_cause; // @[lsu.scala:1729:25] wire [4:0] s_uop_18_mem_cmd; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_mem_size; // @[lsu.scala:1729:25] wire s_uop_18_mem_signed; // @[lsu.scala:1729:25] wire s_uop_18_uses_ldq; // @[lsu.scala:1729:25] wire s_uop_18_uses_stq; // @[lsu.scala:1729:25] wire s_uop_18_is_unique; // @[lsu.scala:1729:25] wire s_uop_18_flush_on_commit; // @[lsu.scala:1729:25] wire [2:0] s_uop_18_csr_cmd; // @[lsu.scala:1729:25] wire s_uop_18_ldst_is_rs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_18_ldst; // @[lsu.scala:1729:25] wire [5:0] s_uop_18_lrs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_18_lrs2; // @[lsu.scala:1729:25] wire [5:0] s_uop_18_lrs3; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_dst_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_lrs1_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_lrs2_rtype; // @[lsu.scala:1729:25] wire s_uop_18_frs3_en; // @[lsu.scala:1729:25] wire s_uop_18_fcn_dw; // @[lsu.scala:1729:25] wire [4:0] s_uop_18_fcn_op; // @[lsu.scala:1729:25] wire s_uop_18_fp_val; // @[lsu.scala:1729:25] wire [2:0] s_uop_18_fp_rm; // @[lsu.scala:1729:25] wire [1:0] s_uop_18_fp_typ; // @[lsu.scala:1729:25] wire s_uop_18_xcpt_pf_if; // @[lsu.scala:1729:25] wire s_uop_18_xcpt_ae_if; // @[lsu.scala:1729:25] wire s_uop_18_xcpt_ma_if; // @[lsu.scala:1729:25] wire s_uop_18_bp_debug_if; // @[lsu.scala:1729:25] wire s_uop_18_bp_xcpt_if; // @[lsu.scala:1729:25] wire [2:0] s_uop_18_debug_fsrc; // @[lsu.scala:1729:25] wire [2:0] s_uop_18_debug_tsrc; // @[lsu.scala:1729:25] assign s_uop_18_inst = _GEN_200[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_debug_inst = _GEN_201[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_rvc = _GEN_202[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_debug_pc = _GEN_203[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iq_type_0 = _GEN_204[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iq_type_1 = _GEN_205[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iq_type_2 = _GEN_206[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iq_type_3 = _GEN_207[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_0 = _GEN_208[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_1 = _GEN_209[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_2 = _GEN_210[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_3 = _GEN_211[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_4 = _GEN_212[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_5 = _GEN_213[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_6 = _GEN_214[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_7 = _GEN_215[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_8 = _GEN_216[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fu_code_9 = _GEN_217[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_issued = _GEN_218[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_issued_partial_agen = _GEN_219[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_issued_partial_dgen = _GEN_220[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_p1_speculative_child = _GEN_221[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_p2_speculative_child = _GEN_222[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_p1_bypass_hint = _GEN_223[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_p2_bypass_hint = _GEN_224[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_iw_p3_bypass_hint = _GEN_225[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_dis_col_sel = _GEN_226[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_br_mask = _GEN_227[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_br_tag = _GEN_228[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_br_type = _GEN_229[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_sfb = _GEN_230[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_fence = _GEN_231[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_fencei = _GEN_232[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_sfence = _GEN_233[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_amo = _GEN_234[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_eret = _GEN_235[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_sys_pc2epc = _GEN_236[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_rocc = _GEN_237[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_mov = _GEN_238[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_ftq_idx = _GEN_239[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_edge_inst = _GEN_240[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_pc_lob = _GEN_241[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_taken = _GEN_242[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_imm_rename = _GEN_243[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_imm_sel = _GEN_244[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_pimm = _GEN_245[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_imm_packed = _GEN_246[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_op1_sel = _GEN_247[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_op2_sel = _GEN_248[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_ldst = _GEN_249[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_wen = _GEN_250[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_ren1 = _GEN_251[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_ren2 = _GEN_252[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_ren3 = _GEN_253[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_swap12 = _GEN_254[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_swap23 = _GEN_255[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_typeTagIn = _GEN_256[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_typeTagOut = _GEN_257[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_fromint = _GEN_258[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_toint = _GEN_259[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_fastpipe = _GEN_260[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_fma = _GEN_261[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_div = _GEN_262[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_sqrt = _GEN_263[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_wflags = _GEN_264[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_ctrl_vec = _GEN_265[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_rob_idx = _GEN_266[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_ldq_idx = _GEN_267[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_stq_idx = _GEN_268[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_rxq_idx = _GEN_269[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_pdst = _GEN_270[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_prs1 = _GEN_271[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_prs2 = _GEN_272[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_prs3 = _GEN_273[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_ppred = _GEN_274[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_prs1_busy = _GEN_275[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_prs2_busy = _GEN_276[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_prs3_busy = _GEN_277[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_ppred_busy = _GEN_278[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_stale_pdst = _GEN_279[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_exception = _GEN_280[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_exc_cause = _GEN_281[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_mem_cmd = _GEN_282[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_mem_size = _GEN_283[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_mem_signed = _GEN_284[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_uses_ldq = _GEN_285[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_uses_stq = _GEN_286[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_is_unique = _GEN_287[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_flush_on_commit = _GEN_288[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_csr_cmd = _GEN_289[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_ldst_is_rs1 = _GEN_290[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_ldst = _GEN_291[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_lrs1 = _GEN_292[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_lrs2 = _GEN_293[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_lrs3 = _GEN_294[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_dst_rtype = _GEN_295[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_lrs1_rtype = _GEN_296[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_lrs2_rtype = _GEN_297[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_frs3_en = _GEN_298[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fcn_dw = _GEN_299[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fcn_op = _GEN_300[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_val = _GEN_301[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_rm = _GEN_302[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_fp_typ = _GEN_303[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_xcpt_pf_if = _GEN_304[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_xcpt_ae_if = _GEN_305[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_xcpt_ma_if = _GEN_306[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_bp_debug_if = _GEN_307[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_bp_xcpt_if = _GEN_308[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_debug_fsrc = _GEN_309[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_18_debug_tsrc = _GEN_310[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] wire _GEN_673 = ~commit_store & commit_load; // @[lsu.scala:1724:49, :1725:49, :1731:5, :1735:31] wire _GEN_674 = _GEN_673 & ~reset; // @[lsu.scala:1735:31, :1736:14] wire _GEN_675 = _GEN_25[ldq_head]; // @[lsu.scala:278:29, :387:15, :1736:14] wire [3:0] _T_1456 = stq_commit_head + 4'h1; // @[util.scala:211:14] wire [3:0] _T_1459 = commit_store ? _T_1456 : stq_commit_head; // @[util.scala:211:14] wire [3:0] _T_1460 = ldq_head + 4'h1; // @[util.scala:211:14] wire [3:0] _T_1463 = commit_load ? _T_1460 : ldq_head; // @[util.scala:211:14] wire commit_store_1 = io_core_commit_valids_1_0 & io_core_commit_uops_1_uses_stq_0; // @[lsu.scala:211:7, :1724:49] wire commit_load_1 = io_core_commit_valids_1_0 & io_core_commit_uops_1_uses_ldq_0; // @[lsu.scala:211:7, :1725:49] wire l_uop_17_iq_type_0; // @[lsu.scala:1728:25] wire l_uop_17_iq_type_1; // @[lsu.scala:1728:25] wire l_uop_17_iq_type_2; // @[lsu.scala:1728:25] wire l_uop_17_iq_type_3; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_0; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_1; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_2; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_3; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_4; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_5; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_6; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_7; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_8; // @[lsu.scala:1728:25] wire l_uop_17_fu_code_9; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_ldst; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_wen; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_ren1; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_ren2; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_ren3; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_swap12; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_swap23; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_fromint; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_toint; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_fma; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_div; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_sqrt; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_wflags; // @[lsu.scala:1728:25] wire l_uop_17_fp_ctrl_vec; // @[lsu.scala:1728:25] wire [31:0] l_uop_17_inst; // @[lsu.scala:1728:25] wire [31:0] l_uop_17_debug_inst; // @[lsu.scala:1728:25] wire l_uop_17_is_rvc; // @[lsu.scala:1728:25] wire [39:0] l_uop_17_debug_pc; // @[lsu.scala:1728:25] wire l_uop_17_iw_issued; // @[lsu.scala:1728:25] wire l_uop_17_iw_issued_partial_agen; // @[lsu.scala:1728:25] wire l_uop_17_iw_issued_partial_dgen; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_iw_p1_speculative_child; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_iw_p2_speculative_child; // @[lsu.scala:1728:25] wire l_uop_17_iw_p1_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_17_iw_p2_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_17_iw_p3_bypass_hint; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_dis_col_sel; // @[lsu.scala:1728:25] wire [11:0] l_uop_17_br_mask; // @[lsu.scala:1728:25] wire [3:0] l_uop_17_br_tag; // @[lsu.scala:1728:25] wire [3:0] l_uop_17_br_type; // @[lsu.scala:1728:25] wire l_uop_17_is_sfb; // @[lsu.scala:1728:25] wire l_uop_17_is_fence; // @[lsu.scala:1728:25] wire l_uop_17_is_fencei; // @[lsu.scala:1728:25] wire l_uop_17_is_sfence; // @[lsu.scala:1728:25] wire l_uop_17_is_amo; // @[lsu.scala:1728:25] wire l_uop_17_is_eret; // @[lsu.scala:1728:25] wire l_uop_17_is_sys_pc2epc; // @[lsu.scala:1728:25] wire l_uop_17_is_rocc; // @[lsu.scala:1728:25] wire l_uop_17_is_mov; // @[lsu.scala:1728:25] wire [4:0] l_uop_17_ftq_idx; // @[lsu.scala:1728:25] wire l_uop_17_edge_inst; // @[lsu.scala:1728:25] wire [5:0] l_uop_17_pc_lob; // @[lsu.scala:1728:25] wire l_uop_17_taken; // @[lsu.scala:1728:25] wire l_uop_17_imm_rename; // @[lsu.scala:1728:25] wire [2:0] l_uop_17_imm_sel; // @[lsu.scala:1728:25] wire [4:0] l_uop_17_pimm; // @[lsu.scala:1728:25] wire [19:0] l_uop_17_imm_packed; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_op1_sel; // @[lsu.scala:1728:25] wire [2:0] l_uop_17_op2_sel; // @[lsu.scala:1728:25] wire [5:0] l_uop_17_rob_idx; // @[lsu.scala:1728:25] wire [3:0] l_uop_17_ldq_idx; // @[lsu.scala:1728:25] wire [3:0] l_uop_17_stq_idx; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_rxq_idx; // @[lsu.scala:1728:25] wire [6:0] l_uop_17_pdst; // @[lsu.scala:1728:25] wire [6:0] l_uop_17_prs1; // @[lsu.scala:1728:25] wire [6:0] l_uop_17_prs2; // @[lsu.scala:1728:25] wire [6:0] l_uop_17_prs3; // @[lsu.scala:1728:25] wire [4:0] l_uop_17_ppred; // @[lsu.scala:1728:25] wire l_uop_17_prs1_busy; // @[lsu.scala:1728:25] wire l_uop_17_prs2_busy; // @[lsu.scala:1728:25] wire l_uop_17_prs3_busy; // @[lsu.scala:1728:25] wire l_uop_17_ppred_busy; // @[lsu.scala:1728:25] wire [6:0] l_uop_17_stale_pdst; // @[lsu.scala:1728:25] wire l_uop_17_exception; // @[lsu.scala:1728:25] wire [63:0] l_uop_17_exc_cause; // @[lsu.scala:1728:25] wire [4:0] l_uop_17_mem_cmd; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_mem_size; // @[lsu.scala:1728:25] wire l_uop_17_mem_signed; // @[lsu.scala:1728:25] wire l_uop_17_uses_ldq; // @[lsu.scala:1728:25] wire l_uop_17_uses_stq; // @[lsu.scala:1728:25] wire l_uop_17_is_unique; // @[lsu.scala:1728:25] wire l_uop_17_flush_on_commit; // @[lsu.scala:1728:25] wire [2:0] l_uop_17_csr_cmd; // @[lsu.scala:1728:25] wire l_uop_17_ldst_is_rs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_17_ldst; // @[lsu.scala:1728:25] wire [5:0] l_uop_17_lrs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_17_lrs2; // @[lsu.scala:1728:25] wire [5:0] l_uop_17_lrs3; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_dst_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_lrs1_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_lrs2_rtype; // @[lsu.scala:1728:25] wire l_uop_17_frs3_en; // @[lsu.scala:1728:25] wire l_uop_17_fcn_dw; // @[lsu.scala:1728:25] wire [4:0] l_uop_17_fcn_op; // @[lsu.scala:1728:25] wire l_uop_17_fp_val; // @[lsu.scala:1728:25] wire [2:0] l_uop_17_fp_rm; // @[lsu.scala:1728:25] wire [1:0] l_uop_17_fp_typ; // @[lsu.scala:1728:25] wire l_uop_17_xcpt_pf_if; // @[lsu.scala:1728:25] wire l_uop_17_xcpt_ae_if; // @[lsu.scala:1728:25] wire l_uop_17_xcpt_ma_if; // @[lsu.scala:1728:25] wire l_uop_17_bp_debug_if; // @[lsu.scala:1728:25] wire l_uop_17_bp_xcpt_if; // @[lsu.scala:1728:25] wire [2:0] l_uop_17_debug_fsrc; // @[lsu.scala:1728:25] wire [2:0] l_uop_17_debug_tsrc; // @[lsu.scala:1728:25] assign l_uop_17_inst = _GEN_76[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_debug_inst = _GEN_77[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_rvc = _GEN_78[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_debug_pc = _GEN_79[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iq_type_0 = _GEN_80[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iq_type_1 = _GEN_81[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iq_type_2 = _GEN_82[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iq_type_3 = _GEN_83[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_0 = _GEN_84[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_1 = _GEN_85[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_2 = _GEN_86[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_3 = _GEN_87[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_4 = _GEN_88[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_5 = _GEN_89[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_6 = _GEN_90[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_7 = _GEN_91[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_8 = _GEN_92[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fu_code_9 = _GEN_93[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_issued = _GEN_94[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_issued_partial_agen = _GEN_95[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_issued_partial_dgen = _GEN_96[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_p1_speculative_child = _GEN_97[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_p2_speculative_child = _GEN_98[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_p1_bypass_hint = _GEN_99[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_p2_bypass_hint = _GEN_100[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_iw_p3_bypass_hint = _GEN_101[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_dis_col_sel = _GEN_102[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_br_mask = _GEN_103[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_br_tag = _GEN_104[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_br_type = _GEN_105[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_sfb = _GEN_106[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_fence = _GEN_107[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_fencei = _GEN_108[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_sfence = _GEN_109[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_amo = _GEN_110[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_eret = _GEN_111[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_sys_pc2epc = _GEN_112[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_rocc = _GEN_113[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_mov = _GEN_114[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_ftq_idx = _GEN_115[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_edge_inst = _GEN_116[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_pc_lob = _GEN_117[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_taken = _GEN_118[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_imm_rename = _GEN_119[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_imm_sel = _GEN_120[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_pimm = _GEN_121[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_imm_packed = _GEN_122[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_op1_sel = _GEN_123[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_op2_sel = _GEN_124[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_ldst = _GEN_125[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_wen = _GEN_126[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_ren1 = _GEN_127[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_ren2 = _GEN_128[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_ren3 = _GEN_129[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_swap12 = _GEN_130[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_swap23 = _GEN_131[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_typeTagIn = _GEN_132[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_typeTagOut = _GEN_133[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_fromint = _GEN_134[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_toint = _GEN_135[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_fastpipe = _GEN_136[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_fma = _GEN_137[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_div = _GEN_138[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_sqrt = _GEN_139[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_wflags = _GEN_140[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_ctrl_vec = _GEN_141[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_rob_idx = _GEN_142[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_ldq_idx = _GEN_143[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_stq_idx = _GEN_144[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_rxq_idx = _GEN_145[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_pdst = _GEN_146[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_prs1 = _GEN_147[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_prs2 = _GEN_148[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_prs3 = _GEN_149[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_ppred = _GEN_150[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_prs1_busy = _GEN_151[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_prs2_busy = _GEN_152[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_prs3_busy = _GEN_153[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_ppred_busy = _GEN_154[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_stale_pdst = _GEN_155[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_exception = _GEN_156[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_exc_cause = _GEN_157[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_mem_cmd = _GEN_158[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_mem_size = _GEN_159[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_mem_signed = _GEN_160[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_uses_ldq = _GEN_161[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_uses_stq = _GEN_162[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_is_unique = _GEN_163[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_flush_on_commit = _GEN_164[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_csr_cmd = _GEN_165[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_ldst_is_rs1 = _GEN_166[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_ldst = _GEN_167[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_lrs1 = _GEN_168[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_lrs2 = _GEN_169[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_lrs3 = _GEN_170[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_dst_rtype = _GEN_171[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_lrs1_rtype = _GEN_172[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_lrs2_rtype = _GEN_173[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_frs3_en = _GEN_174[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fcn_dw = _GEN_175[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fcn_op = _GEN_176[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_val = _GEN_177[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_rm = _GEN_178[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_fp_typ = _GEN_179[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_xcpt_pf_if = _GEN_180[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_xcpt_ae_if = _GEN_181[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_xcpt_ma_if = _GEN_182[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_bp_debug_if = _GEN_183[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_bp_xcpt_if = _GEN_184[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_debug_fsrc = _GEN_185[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_17_debug_tsrc = _GEN_186[_T_1463]; // @[lsu.scala:235:32, :1728:25, :1758:31] wire s_uop_19_iq_type_0; // @[lsu.scala:1729:25] wire s_uop_19_iq_type_1; // @[lsu.scala:1729:25] wire s_uop_19_iq_type_2; // @[lsu.scala:1729:25] wire s_uop_19_iq_type_3; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_0; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_1; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_2; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_3; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_4; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_5; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_6; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_7; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_8; // @[lsu.scala:1729:25] wire s_uop_19_fu_code_9; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_ldst; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_wen; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_ren1; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_ren2; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_ren3; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_swap12; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_swap23; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_fromint; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_toint; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_fma; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_div; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_sqrt; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_wflags; // @[lsu.scala:1729:25] wire s_uop_19_fp_ctrl_vec; // @[lsu.scala:1729:25] wire [31:0] s_uop_19_inst; // @[lsu.scala:1729:25] wire [31:0] s_uop_19_debug_inst; // @[lsu.scala:1729:25] wire s_uop_19_is_rvc; // @[lsu.scala:1729:25] wire [39:0] s_uop_19_debug_pc; // @[lsu.scala:1729:25] wire s_uop_19_iw_issued; // @[lsu.scala:1729:25] wire s_uop_19_iw_issued_partial_agen; // @[lsu.scala:1729:25] wire s_uop_19_iw_issued_partial_dgen; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_iw_p1_speculative_child; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_iw_p2_speculative_child; // @[lsu.scala:1729:25] wire s_uop_19_iw_p1_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_19_iw_p2_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_19_iw_p3_bypass_hint; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_dis_col_sel; // @[lsu.scala:1729:25] wire [11:0] s_uop_19_br_mask; // @[lsu.scala:1729:25] wire [3:0] s_uop_19_br_tag; // @[lsu.scala:1729:25] wire [3:0] s_uop_19_br_type; // @[lsu.scala:1729:25] wire s_uop_19_is_sfb; // @[lsu.scala:1729:25] wire s_uop_19_is_fence; // @[lsu.scala:1729:25] wire s_uop_19_is_fencei; // @[lsu.scala:1729:25] wire s_uop_19_is_sfence; // @[lsu.scala:1729:25] wire s_uop_19_is_amo; // @[lsu.scala:1729:25] wire s_uop_19_is_eret; // @[lsu.scala:1729:25] wire s_uop_19_is_sys_pc2epc; // @[lsu.scala:1729:25] wire s_uop_19_is_rocc; // @[lsu.scala:1729:25] wire s_uop_19_is_mov; // @[lsu.scala:1729:25] wire [4:0] s_uop_19_ftq_idx; // @[lsu.scala:1729:25] wire s_uop_19_edge_inst; // @[lsu.scala:1729:25] wire [5:0] s_uop_19_pc_lob; // @[lsu.scala:1729:25] wire s_uop_19_taken; // @[lsu.scala:1729:25] wire s_uop_19_imm_rename; // @[lsu.scala:1729:25] wire [2:0] s_uop_19_imm_sel; // @[lsu.scala:1729:25] wire [4:0] s_uop_19_pimm; // @[lsu.scala:1729:25] wire [19:0] s_uop_19_imm_packed; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_op1_sel; // @[lsu.scala:1729:25] wire [2:0] s_uop_19_op2_sel; // @[lsu.scala:1729:25] wire [5:0] s_uop_19_rob_idx; // @[lsu.scala:1729:25] wire [3:0] s_uop_19_ldq_idx; // @[lsu.scala:1729:25] wire [3:0] s_uop_19_stq_idx; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_rxq_idx; // @[lsu.scala:1729:25] wire [6:0] s_uop_19_pdst; // @[lsu.scala:1729:25] wire [6:0] s_uop_19_prs1; // @[lsu.scala:1729:25] wire [6:0] s_uop_19_prs2; // @[lsu.scala:1729:25] wire [6:0] s_uop_19_prs3; // @[lsu.scala:1729:25] wire [4:0] s_uop_19_ppred; // @[lsu.scala:1729:25] wire s_uop_19_prs1_busy; // @[lsu.scala:1729:25] wire s_uop_19_prs2_busy; // @[lsu.scala:1729:25] wire s_uop_19_prs3_busy; // @[lsu.scala:1729:25] wire s_uop_19_ppred_busy; // @[lsu.scala:1729:25] wire [6:0] s_uop_19_stale_pdst; // @[lsu.scala:1729:25] wire s_uop_19_exception; // @[lsu.scala:1729:25] wire [63:0] s_uop_19_exc_cause; // @[lsu.scala:1729:25] wire [4:0] s_uop_19_mem_cmd; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_mem_size; // @[lsu.scala:1729:25] wire s_uop_19_mem_signed; // @[lsu.scala:1729:25] wire s_uop_19_uses_ldq; // @[lsu.scala:1729:25] wire s_uop_19_uses_stq; // @[lsu.scala:1729:25] wire s_uop_19_is_unique; // @[lsu.scala:1729:25] wire s_uop_19_flush_on_commit; // @[lsu.scala:1729:25] wire [2:0] s_uop_19_csr_cmd; // @[lsu.scala:1729:25] wire s_uop_19_ldst_is_rs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_19_ldst; // @[lsu.scala:1729:25] wire [5:0] s_uop_19_lrs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_19_lrs2; // @[lsu.scala:1729:25] wire [5:0] s_uop_19_lrs3; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_dst_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_lrs1_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_lrs2_rtype; // @[lsu.scala:1729:25] wire s_uop_19_frs3_en; // @[lsu.scala:1729:25] wire s_uop_19_fcn_dw; // @[lsu.scala:1729:25] wire [4:0] s_uop_19_fcn_op; // @[lsu.scala:1729:25] wire s_uop_19_fp_val; // @[lsu.scala:1729:25] wire [2:0] s_uop_19_fp_rm; // @[lsu.scala:1729:25] wire [1:0] s_uop_19_fp_typ; // @[lsu.scala:1729:25] wire s_uop_19_xcpt_pf_if; // @[lsu.scala:1729:25] wire s_uop_19_xcpt_ae_if; // @[lsu.scala:1729:25] wire s_uop_19_xcpt_ma_if; // @[lsu.scala:1729:25] wire s_uop_19_bp_debug_if; // @[lsu.scala:1729:25] wire s_uop_19_bp_xcpt_if; // @[lsu.scala:1729:25] wire [2:0] s_uop_19_debug_fsrc; // @[lsu.scala:1729:25] wire [2:0] s_uop_19_debug_tsrc; // @[lsu.scala:1729:25] assign s_uop_19_inst = _GEN_200[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_debug_inst = _GEN_201[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_rvc = _GEN_202[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_debug_pc = _GEN_203[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iq_type_0 = _GEN_204[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iq_type_1 = _GEN_205[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iq_type_2 = _GEN_206[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iq_type_3 = _GEN_207[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_0 = _GEN_208[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_1 = _GEN_209[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_2 = _GEN_210[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_3 = _GEN_211[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_4 = _GEN_212[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_5 = _GEN_213[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_6 = _GEN_214[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_7 = _GEN_215[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_8 = _GEN_216[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fu_code_9 = _GEN_217[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_issued = _GEN_218[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_issued_partial_agen = _GEN_219[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_issued_partial_dgen = _GEN_220[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_p1_speculative_child = _GEN_221[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_p2_speculative_child = _GEN_222[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_p1_bypass_hint = _GEN_223[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_p2_bypass_hint = _GEN_224[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_iw_p3_bypass_hint = _GEN_225[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_dis_col_sel = _GEN_226[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_br_mask = _GEN_227[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_br_tag = _GEN_228[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_br_type = _GEN_229[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_sfb = _GEN_230[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_fence = _GEN_231[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_fencei = _GEN_232[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_sfence = _GEN_233[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_amo = _GEN_234[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_eret = _GEN_235[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_sys_pc2epc = _GEN_236[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_rocc = _GEN_237[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_mov = _GEN_238[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_ftq_idx = _GEN_239[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_edge_inst = _GEN_240[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_pc_lob = _GEN_241[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_taken = _GEN_242[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_imm_rename = _GEN_243[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_imm_sel = _GEN_244[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_pimm = _GEN_245[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_imm_packed = _GEN_246[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_op1_sel = _GEN_247[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_op2_sel = _GEN_248[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_ldst = _GEN_249[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_wen = _GEN_250[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_ren1 = _GEN_251[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_ren2 = _GEN_252[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_ren3 = _GEN_253[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_swap12 = _GEN_254[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_swap23 = _GEN_255[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_typeTagIn = _GEN_256[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_typeTagOut = _GEN_257[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_fromint = _GEN_258[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_toint = _GEN_259[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_fastpipe = _GEN_260[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_fma = _GEN_261[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_div = _GEN_262[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_sqrt = _GEN_263[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_wflags = _GEN_264[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_ctrl_vec = _GEN_265[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_rob_idx = _GEN_266[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_ldq_idx = _GEN_267[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_stq_idx = _GEN_268[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_rxq_idx = _GEN_269[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_pdst = _GEN_270[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_prs1 = _GEN_271[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_prs2 = _GEN_272[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_prs3 = _GEN_273[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_ppred = _GEN_274[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_prs1_busy = _GEN_275[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_prs2_busy = _GEN_276[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_prs3_busy = _GEN_277[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_ppred_busy = _GEN_278[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_stale_pdst = _GEN_279[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_exception = _GEN_280[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_exc_cause = _GEN_281[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_mem_cmd = _GEN_282[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_mem_size = _GEN_283[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_mem_signed = _GEN_284[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_uses_ldq = _GEN_285[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_uses_stq = _GEN_286[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_is_unique = _GEN_287[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_flush_on_commit = _GEN_288[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_csr_cmd = _GEN_289[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_ldst_is_rs1 = _GEN_290[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_ldst = _GEN_291[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_lrs1 = _GEN_292[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_lrs2 = _GEN_293[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_lrs3 = _GEN_294[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_dst_rtype = _GEN_295[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_lrs1_rtype = _GEN_296[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_lrs2_rtype = _GEN_297[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_frs3_en = _GEN_298[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fcn_dw = _GEN_299[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fcn_op = _GEN_300[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_val = _GEN_301[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_rm = _GEN_302[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_fp_typ = _GEN_303[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_xcpt_pf_if = _GEN_304[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_xcpt_ae_if = _GEN_305[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_xcpt_ma_if = _GEN_306[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_bp_debug_if = _GEN_307[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_bp_xcpt_if = _GEN_308[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_debug_fsrc = _GEN_309[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_19_debug_tsrc = _GEN_310[_T_1459]; // @[lsu.scala:264:32, :1729:25, :1754:31] wire _GEN_676 = ~commit_store_1 & commit_load_1; // @[lsu.scala:1724:49, :1725:49, :1731:5, :1735:31] wire _GEN_677 = _GEN_676 & ~reset; // @[lsu.scala:1735:31, :1736:14]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_14( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [4:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [4:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_26 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_32 = 1'h1; // @[Parameters.scala:56:32] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_3 = 3'h6; // @[Misc.scala:202:34] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_13 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1_decode = 3'h7; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _legal_source_uncommonBits_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_6 = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = ~_source_ok_T_6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_9 & _source_ok_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_9 = _uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_12 = _uncommonBits_T_12[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_13 = _uncommonBits_T_13[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_14 = _uncommonBits_T_14[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_15 = _uncommonBits_T_15[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_12 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_18 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_13 = _source_ok_T_12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_16 = source_ok_uncommonBits_2 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_17 = _source_ok_T_15 & _source_ok_T_16; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_22 = source_ok_uncommonBits_3 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_1 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :309:31] wire [3:0] uncommonBits_18 = _uncommonBits_T_18[3:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T = io_in_b_bits_source_0[4]; // @[Monitor.scala:36:7] wire _legal_source_T_6 = io_in_b_bits_source_0[4]; // @[Monitor.scala:36:7] wire [3:0] uncommonBits_19 = _uncommonBits_T_19[3:0]; // @[Parameters.scala:52:{29,56}] wire [31:0] _address_ok_T = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire [3:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_1 = _legal_source_T; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_3 = _legal_source_T_1; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_4 = legal_source_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_3 & _legal_source_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire [3:0] legal_source_uncommonBits_1 = _legal_source_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_7 = ~_legal_source_T_6; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_9 = _legal_source_T_7; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_10 = legal_source_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_11 = _legal_source_T_9 & _legal_source_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire _legal_source_WIRE_1 = _legal_source_T_11; // @[Parameters.scala:1138:31] wire [4:0] _legal_source_T_12 = {_legal_source_WIRE_0, 4'h0}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_14 = _legal_source_T_12; // @[Mux.scala:30:73] wire [4:0] _legal_source_WIRE_1_0 = _legal_source_T_14; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_24 = io_in_c_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = io_in_c_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_25 = _source_ok_T_24; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_27 = _source_ok_T_25; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_28 = source_ok_uncommonBits_4 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_29 = _source_ok_T_27 & _source_ok_T_28; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_31 = ~_source_ok_T_30; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_33 = _source_ok_T_31; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = source_ok_uncommonBits_5 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_35 = _source_ok_T_33 & _source_ok_T_34; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_1 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_0 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_0; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [31:0] _address_ok_T_5 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [3:0] uncommonBits_20 = _uncommonBits_T_20[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_21 = _uncommonBits_T_21[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_24 = _uncommonBits_T_24[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_25 = _uncommonBits_T_25[3:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :367:31] wire _T_1322 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1322; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1322; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1396 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1396; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1396; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1396; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_1396; // @[Decoupled.scala:51:35] wire [12:0] _GEN_1 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_1; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_1; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [2:0] b_first_counter; // @[Edges.scala:229:27] wire [3:0] _b_first_counter1_T = {1'h0, b_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] b_first_counter1 = _b_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _b_first_counter_T = b_first ? 3'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [4:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_1393 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_1393; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_1393; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [4:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [24:0] inflight; // @[Monitor.scala:614:27] reg [99:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [99:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [24:0] a_set; // @[Monitor.scala:626:34] wire [24:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [99:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [99:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_2 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_2; // @[Monitor.scala:637:69] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:637:69, :641:65] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_2; // @[Monitor.scala:637:69, :680:101] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:637:69, :681:99] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_2; // @[Monitor.scala:637:69, :749:69] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:637:69, :750:67] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_2; // @[Monitor.scala:637:69, :790:101] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:637:69, :791:99] wire [99:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [99:0] _a_opcode_lookup_T_6 = {96'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [99:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[99:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [99:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [99:0] _a_size_lookup_T_6 = {96'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [99:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[99:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[24:0] : 25'h0; // @[OneHot.scala:58:35] wire _T_1248 = _T_1322 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1248 ? _a_set_T[24:0] : 25'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1248 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1248 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _GEN_4 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_4; // @[Monitor.scala:659:79] wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_4; // @[Monitor.scala:659:79, :660:77] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1248 ? _a_opcodes_set_T_1[99:0] : 100'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1248 ? _a_sizes_set_T_1[99:0] : 100'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [24:0] d_clr; // @[Monitor.scala:664:34] wire [24:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [99:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [99:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1294 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_6; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1294 & ~d_release_ack ? _d_clr_wo_ready_T[24:0] : 25'h0; // @[OneHot.scala:58:35] wire _T_1263 = _T_1396 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1263 ? _d_clr_T[24:0] : 25'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1263 ? _d_opcodes_clr_T_5[99:0] : 100'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1263 ? _d_sizes_clr_T_5[99:0] : 100'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [24:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [24:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [24:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [99:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [99:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [99:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [99:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [99:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [99:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [24:0] inflight_1; // @[Monitor.scala:726:35] reg [99:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [99:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [24:0] c_set; // @[Monitor.scala:738:34] wire [24:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [99:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [99:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [99:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [99:0] _c_opcode_lookup_T_6 = {96'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [99:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[99:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [99:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [99:0] _c_size_lookup_T_6 = {96'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [99:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[99:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [31:0] _GEN_7 = 32'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_7; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[24:0] : 25'h0; // @[OneHot.scala:58:35] wire _T_1335 = _T_1393 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_1335 ? _c_set_T[24:0] : 25'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_1335 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_1335 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [7:0] _GEN_8 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [7:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_8; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_8; // @[Monitor.scala:767:79, :768:77] wire [258:0] _c_opcodes_set_T_1 = {255'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_1335 ? _c_opcodes_set_T_1[99:0] : 100'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [258:0] _c_sizes_set_T_1 = {255'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_1335 ? _c_sizes_set_T_1[99:0] : 100'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [24:0] d_clr_1; // @[Monitor.scala:774:34] wire [24:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [99:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [99:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1366 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1366 & d_release_ack_1 ? _d_clr_wo_ready_T_1[24:0] : 25'h0; // @[OneHot.scala:58:35] wire _T_1348 = _T_1396 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1348 ? _d_clr_T_1[24:0] : 25'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1348 ? _d_opcodes_clr_T_11[99:0] : 100'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1348 ? _d_sizes_clr_T_11[99:0] : 100'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [24:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [24:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [24:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [99:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [99:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [99:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [99:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [99:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [99:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [6:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [6:0] d_set; // @[Monitor.scala:833:25] wire _T_1402 = _T_1396 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_1402 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35] wire [6:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _e_clr_T = 8'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[6:0] : 7'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to the following Chisel files. File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ class IntXbar()(implicit p: Parameters) extends LazyModule { val intnode = new IntNexusNode( sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, sourceFn = { seq => IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten) }) { override def circuitIdentity = outputs == 1 && inputs == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { override def desiredName = s"IntXbar_i${intnode.in.size}_o${intnode.out.size}" val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten intnode.out.foreach { case (o, _) => o := cat } } } class IntSyncXbar()(implicit p: Parameters) extends LazyModule { val intnode = new IntSyncNexusNode( sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, sourceFn = { seq => IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten) }) { override def circuitIdentity = outputs == 1 && inputs == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncXbar_i${intnode.in.size}_o${intnode.out.size}" val cat = intnode.in.map { case (i, e) => i.sync.take(e.source.num) }.flatten intnode.out.foreach { case (o, _) => o.sync := cat } } } object IntXbar { def apply()(implicit p: Parameters): IntNode = { val xbar = LazyModule(new IntXbar) xbar.intnode } } object IntSyncXbar { def apply()(implicit p: Parameters): IntSyncNode = { val xbar = LazyModule(new IntSyncXbar) xbar.intnode } }

module IntXbar_i1_o1_2(); // @[Xbar.scala:22:9] wire auto_anon_in_0 = 1'h0; // @[Xbar.scala:22:9] wire auto_anon_out_0 = 1'h0; // @[Xbar.scala:22:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire anonIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_0 = 1'h0; // @[MixedNode.scala:542:17] endmodule

Generate the Verilog code corresponding to the following Chisel files. File icache.scala: //****************************************************************************** // Copyright (c) 2017 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // ICache //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.ifu import chisel3._ import chisel3.util._ import chisel3.util.random._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property._ import freechips.rocketchip.rocket.{HasL1ICacheParameters, ICacheParams, ICacheErrors, ICacheReq} import boom.v4.common._ import boom.v4.util.{BoomCoreStringPrefix} /** * ICache module * * @param icacheParams parameters for the icache * @param hartId the id of the hardware thread in the cache * @param enableBlackBox use a blackbox icache */ class ICache( val icacheParams: ICacheParams, val tileId: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new ICacheModule(this) val masterNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( sourceId = IdRange(0, 1 + icacheParams.prefetch.toInt), // 0=refill, 1=hint name = s"Core ${tileId} ICache"))))) val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes private val wordBytes = icacheParams.fetchBytes } /** * IO Signals leaving the ICache * * @param outer top level ICache class */ class ICacheResp(val outer: ICache) extends Bundle { val data = UInt((outer.icacheParams.fetchBytes*8).W) val replay = Bool() val ae = Bool() } /** * IO Signals for interacting with the ICache * * @param outer top level ICache class */ class ICacheBundle(val outer: ICache) extends BoomBundle()(outer.p) with HasBoomFrontendParameters { val req = Flipped(Decoupled(new ICacheReq)) val s1_paddr = Input(UInt(paddrBits.W)) // delayed one cycle w.r.t. req val s1_kill = Input(Bool()) // delayed one cycle w.r.t. req val s2_kill = Input(Bool()) // delayed two cycles; prevents I$ miss emission val s2_prefetch = Input(Bool()) // should I$ prefetch next line on a miss? val resp = Valid(new ICacheResp(outer)) val invalidate = Input(Bool()) val perf = Output(new Bundle { val acquire = Bool() }) } /** * Main ICache module * * @param outer top level ICache class */ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) with HasBoomFrontendParameters { override def tlBundleParams = outer.masterNode.out.head._2.bundle val enableICacheDelay = tileParams.core.asInstanceOf[BoomCoreParams].enableICacheDelay val icacheSinglePorted = tileParams.core.asInstanceOf[BoomCoreParams].icacheSinglePorted val io = IO(new ICacheBundle(outer)) val (tl_out, edge_out) = outer.masterNode.out(0) require(isPow2(nSets) && isPow2(nWays)) require(usingVM) require(pgIdxBits >= untagBits) // How many bits do we intend to fetch at most every cycle? val wordBits = outer.icacheParams.fetchBytes*8 // Each of these cases require some special-case handling. require (tl_out.d.bits.data.getWidth == wordBits) val s0_valid = io.req.fire val s0_vaddr = io.req.bits.addr val s1_valid = RegNext(s0_valid, false.B) val s1_tag_hit = Wire(Vec(nWays, Bool())) val s1_hit = s1_tag_hit.reduce(_||_) val s2_valid = RegNext(s1_valid && !io.s1_kill, false.B) val s2_hit = RegNext(s1_hit) val invalidated = Reg(Bool()) val refill_valid = RegInit(false.B) val refill_fire = tl_out.a.fire val s2_miss = s2_valid && !s2_hit && !RegNext(refill_valid) val refill_paddr = RegEnable(io.s1_paddr, s1_valid && !(refill_valid || s2_miss)) val refill_tag = refill_paddr(tagBits+untagBits-1,untagBits) val refill_idx = refill_paddr(untagBits-1,blockOffBits) val refill_one_beat = tl_out.d.fire && edge_out.hasData(tl_out.d.bits) io.req.ready := !refill_one_beat val (_, _, d_done, refill_cnt) = edge_out.count(tl_out.d) val refill_done = refill_one_beat && d_done tl_out.d.ready := true.B require (edge_out.manager.minLatency > 0) val repl_way = if (isDM) 0.U else LFSR(16, refill_fire)(log2Ceil(nWays)-1,0) val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(tagBits.W))) val tag_rdata = if (icacheSinglePorted) { tag_array.read(s0_vaddr(untagBits-1, blockOffBits), !refill_done && s0_valid) } else { tag_array.read(s0_vaddr(untagBits-1, blockOffBits), io.req.valid) } when (refill_done) { tag_array.write(refill_idx, VecInit(Seq.fill(nWays)(refill_tag)), Seq.tabulate(nWays)(repl_way === _.U)) } val vb_array = RegInit(0.U((nSets*nWays).W)) when (refill_one_beat) { vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), refill_done && !invalidated) } when (io.invalidate) { vb_array := 0.U invalidated := true.B } val s2_dout = Wire(Vec(nWays, UInt(wordBits.W))) val s1_bankid = Wire(Bool()) for (i <- 0 until nWays) { val s1_idx = io.s1_paddr(untagBits-1,blockOffBits) val s1_tag = io.s1_paddr(tagBits+untagBits-1,untagBits) val s1_vb = vb_array(Cat(i.U, s1_idx)) val tag = tag_rdata(i) s1_tag_hit(i) := s1_vb && tag === s1_tag } assert(PopCount(s1_tag_hit) <= 1.U || !s1_valid) val ramDepth = nSets * refillCycles val dataArrays = Seq.tabulate(nBanks) { b => DescribedSRAM( name = s"dataArrayB${b}", desc = "ICache Data Array", size = ramDepth, data = Vec(nWays, UInt((wordBits/nBanks).W)) ) } if (nBanks == 1) { // Use unbanked icache for narrow accesses. s1_bankid := 0.U val array = dataArrays(0) def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) val s0_ren = s0_valid val wen = refill_one_beat && !invalidated val mem_idx = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt, row(s0_vaddr)) val wmask = UIntToOH(repl_way)(nWays-1,0).asBools when (wen) { array.write(mem_idx, VecInit(Seq.fill(nWays) { tl_out.d.bits.data }), wmask) } if (enableICacheDelay) { if (icacheSinglePorted) s2_dout := array.read(RegNext(mem_idx), RegNext(!wen && s0_ren)) else s2_dout := array.read(RegNext(mem_idx), RegNext(s0_ren)) } else { if (icacheSinglePorted) s2_dout := RegNext(array.read(mem_idx, !wen && s0_ren)) else s2_dout := RegNext(array.read(mem_idx, io.req.valid)) } } else { // Use two banks, interleaved. val array_0 = dataArrays(0) val array_1 = dataArrays(1) require (nBanks == 2) // Bank0 row's id wraps around if Bank1 is the starting bank. def b0Row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) + bank(addr) // Bank1 row's id stays the same regardless of which Bank has the fetch address. def b1Row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) s1_bankid := RegNext(bank(s0_vaddr)) val s0_ren = s0_valid val wen = (refill_one_beat && !invalidated) val wmask = UIntToOH(repl_way)(nWays-1,0).asBools var mem_idx0: UInt = null var mem_idx1: UInt = null // write a refill beat across both banks. mem_idx0 = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt, b0Row(s0_vaddr)) mem_idx1 = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt, b1Row(s0_vaddr)) when (wen) { val data = tl_out.d.bits.data val wdata_0 = VecInit(Seq.fill(nWays) { data(wordBits/2-1, 0) }) val wdata_1 = VecInit(Seq.fill(nWays) { data(wordBits-1, wordBits/2) }) array_0.write(mem_idx0, wdata_0, wmask) array_1.write(mem_idx1, wdata_1, wmask) } val rdata_0 = Wire(Vec(nWays, UInt((wordBits/nBanks).W))) val rdata_1 = Wire(Vec(nWays, UInt((wordBits/nBanks).W))) if (enableICacheDelay) { if (icacheSinglePorted) { rdata_0 := array_0.read(RegNext(mem_idx0), RegNext(!wen && s0_ren)) rdata_1 := array_1.read(RegNext(mem_idx1), RegNext(!wen && s0_ren)) } else { rdata_0 := array_0.read(RegNext(mem_idx0), RegNext(s0_ren)) rdata_1 := array_1.read(RegNext(mem_idx1), RegNext(s0_ren)) } } else { if (icacheSinglePorted) { rdata_0 := RegNext(array_0.read(mem_idx0, !wen && s0_ren)) rdata_1 := RegNext(array_1.read(mem_idx1, !wen && s0_ren)) } else { rdata_0 := RegNext(array_0.read(mem_idx0, io.req.valid)) rdata_1 := RegNext(array_1.read(mem_idx1, io.req.valid)) } } for (w <- 0 until nWays) { s2_dout(w) := Cat(rdata_1(w), rdata_0(w)) } } val s2_tag_hit = RegNext(s1_tag_hit) val s2_hit_way = OHToUInt(s2_tag_hit) val s2_bankid = RegNext(s1_bankid) val s2_way_mux = Mux1H(s2_tag_hit, s2_dout) val s2_unbanked_data = s2_way_mux val sz = s2_way_mux.getWidth val s2_bank0_data = s2_way_mux(sz/2-1,0) val s2_bank1_data = s2_way_mux(sz-1,sz/2) val s2_data = if (nBanks == 2) { Mux(s2_bankid, Cat(s2_bank0_data, s2_bank1_data), Cat(s2_bank1_data, s2_bank0_data)) } else { s2_unbanked_data } io.resp.bits.data := s2_data io.resp.bits.ae := DontCare io.resp.bits.replay := DontCare io.resp.valid := s2_valid && s2_hit tl_out.a.valid := s2_miss && !refill_valid && !io.s2_kill tl_out.a.bits := edge_out.Get( fromSource = 0.U, toAddress = (refill_paddr >> blockOffBits) << blockOffBits, lgSize = lgCacheBlockBytes.U)._2 tl_out.b.ready := true.B tl_out.c.valid := false.B tl_out.e.valid := false.B io.perf.acquire := tl_out.a.fire when (!refill_valid) { invalidated := false.B } when (refill_fire) { refill_valid := true.B } when (refill_done) { refill_valid := false.B } override def toString: String = BoomCoreStringPrefix( "==L1-ICache==", "Fetch bytes : " + cacheParams.fetchBytes, "Block bytes : " + (1 << blockOffBits), "Word bits : " + wordBits, "Sets : " + nSets, "Ways : " + nWays, "Refill cycles : " + refillCycles, "RAMs : (" + wordBits/nBanks + " x " + nSets*refillCycles + ") using " + nBanks + " banks", "" + (if (nBanks == 2) "Dual-banked" else "Single-banked"), "I-TLB ways : " + cacheParams.nTLBWays + "\n") }

module tag_array_0( // @[icache.scala:141:30] input [5:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [79:0] RW0_wdata, output [79:0] RW0_rdata, input [3:0] RW0_wmask ); tag_array_0_ext tag_array_0_ext ( // @[icache.scala:141:30] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[icache.scala:141:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }

module dataMems_350( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData_90( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File BankBinder.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} case class BankBinderNode(mask: BigInt)(implicit valName: ValName) extends TLCustomNode { private val bit = mask & -mask val maxXfer = TransferSizes(1, if (bit == 0 || bit > 4096) 4096 else bit.toInt) val ids = AddressSet.enumerateMask(mask) def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { val ports = ids.size val oStar = if (oStars == 0) 0 else (ports - oKnown) / oStars val iStar = if (iStars == 0) 0 else (ports - iKnown) / iStars require (ports == iKnown + iStar*iStars, s"${name} must have ${ports} inputs, but has ${iKnown} + ${iStar}*${iStars} (at ${lazyModule.line})") require (ports == oKnown + oStar*oStars, s"${name} must have ${ports} outputs, but has ${oKnown} + ${oStar}*${oStars} (at ${lazyModule.line})") (iStar, oStar) } def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = (p zip ids) map { case (cp, id) => cp.v1copy(clients = cp.clients.map { c => c.v1copy( visibility = c.visibility.flatMap { a => a.intersect(AddressSet(id, ~mask))}, supportsProbe = c.supports.probe intersect maxXfer, supportsArithmetic = c.supports.arithmetic intersect maxXfer, supportsLogical = c.supports.logical intersect maxXfer, supportsGet = c.supports.get intersect maxXfer, supportsPutFull = c.supports.putFull intersect maxXfer, supportsPutPartial = c.supports.putPartial intersect maxXfer, supportsHint = c.supports.hint intersect maxXfer)})} def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = (p zip ids) map { case (mp, id) => mp.v1copy(managers = mp.managers.flatMap { m => val addresses = m.address.flatMap(a => a.intersect(AddressSet(id, ~mask))) if (addresses.nonEmpty) Some(m.v1copy( address = addresses, supportsAcquireT = m.supportsAcquireT intersect maxXfer, supportsAcquireB = m.supportsAcquireB intersect maxXfer, supportsArithmetic = m.supportsArithmetic intersect maxXfer, supportsLogical = m.supportsLogical intersect maxXfer, supportsGet = m.supportsGet intersect maxXfer, supportsPutFull = m.supportsPutFull intersect maxXfer, supportsPutPartial = m.supportsPutPartial intersect maxXfer, supportsHint = m.supportsHint intersect maxXfer)) else None })} } /* A BankBinder is used to divide contiguous memory regions into banks, suitable for a cache */ class BankBinder(mask: BigInt)(implicit p: Parameters) extends LazyModule { val node = BankBinderNode(mask) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out <> in } } } object BankBinder { def apply(mask: BigInt)(implicit p: Parameters): TLNode = { val binder = LazyModule(new BankBinder(mask)) binder.node } def apply(nBanks: Int, granularity: Int)(implicit p: Parameters): TLNode = { if (nBanks > 0) apply(granularity * (nBanks-1)) else TLTempNode() } } File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Filter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes} class TLFilter( mfilter: TLFilter.ManagerFilter = TLFilter.mIdentity, cfilter: TLFilter.ClientFilter = TLFilter.cIdentity )(implicit p: Parameters) extends LazyModule { val node = new TLAdapterNode( clientFn = { cp => cp.v1copy(clients = cp.clients.flatMap { c => val out = cfilter(c) out.map { o => // Confirm the filter only REMOVES capability require (c.sourceId.contains(o.sourceId)) require (c.supports.probe.contains(o.supports.probe)) require (c.supports.arithmetic.contains(o.supports.arithmetic)) require (c.supports.logical.contains(o.supports.logical)) require (c.supports.get.contains(o.supports.get)) require (c.supports.putFull.contains(o.supports.putFull)) require (c.supports.putPartial.contains(o.supports.putPartial)) require (c.supports.hint.contains(o.supports.hint)) require (!c.requestFifo || o.requestFifo) } out })}, managerFn = { mp => val managers = mp.managers.flatMap { m => val out = mfilter(m) out.map { o => // Confirm the filter only REMOVES capability o.address.foreach { a => require (m.address.map(_.contains(a)).reduce(_||_)) } require (o.regionType <= m.regionType) // we allow executable to be changed both ways require (m.supportsAcquireT.contains(o.supportsAcquireT)) require (m.supportsAcquireB.contains(o.supportsAcquireB)) require (m.supportsArithmetic.contains(o.supportsArithmetic)) require (m.supportsLogical.contains(o.supportsLogical)) require (m.supportsGet.contains(o.supportsGet)) require (m.supportsPutFull.contains(o.supportsPutFull)) require (m.supportsPutPartial.contains(o.supportsPutPartial)) require (m.supportsHint.contains(o.supportsHint)) require (!o.fifoId.isDefined || m.fifoId == o.fifoId) } out } mp.v1copy(managers = managers, endSinkId = if (managers.exists(_.supportsAcquireB)) mp.endSinkId else 0) } ) { override def circuitIdentity = true } lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out <> in // In case the inner interface removes Acquire, tie-off the channels if (!edgeIn.manager.anySupportAcquireB) { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFilter { type ManagerFilter = TLSlaveParameters => Option[TLSlaveParameters] type ClientFilter = TLMasterParameters => Option[TLMasterParameters] // preserve manager visibility def mIdentity: ManagerFilter = { m => Some(m) } // preserve client visibility def cIdentity: ClientFilter = { c => Some(c) } // make only the intersected address sets visible def mSelectIntersect(select: AddressSet): ManagerFilter = { m => val filtered = m.address.map(_.intersect(select)).flatten val alignment = select.alignment /* alignment 0 means 'select' selected everything */ transferSizeHelper(m, filtered, alignment) } // make everything except the intersected address sets visible def mSubtract(excepts: Seq[AddressSet]): ManagerFilter = { m => val filtered = excepts.foldLeft(m.address) { (a,e) => a.flatMap(_.subtract(e)) } val alignment: BigInt = if (filtered.isEmpty) 0 else filtered.map(_.alignment).min transferSizeHelper(m, filtered, alignment) } def mSubtract(except: AddressSet): ManagerFilter = { m => mSubtract(Seq(except))(m) } // adjust supported transfer sizes based on filtered intersection private def transferSizeHelper(m: TLSlaveParameters, filtered: Seq[AddressSet], alignment: BigInt): Option[TLSlaveParameters] = { val maxTransfer = 1 << 30 val capTransfer = if (alignment == 0 || alignment > maxTransfer) maxTransfer else alignment.toInt val cap = TransferSizes(1, capTransfer) if (filtered.isEmpty) { None } else { Some(m.v1copy( address = filtered, supportsAcquireT = m.supportsAcquireT .intersect(cap), supportsAcquireB = m.supportsAcquireB .intersect(cap), supportsArithmetic = m.supportsArithmetic.intersect(cap), supportsLogical = m.supportsLogical .intersect(cap), supportsGet = m.supportsGet .intersect(cap), supportsPutFull = m.supportsPutFull .intersect(cap), supportsPutPartial = m.supportsPutPartial.intersect(cap), supportsHint = m.supportsHint .intersect(cap))) } } // hide any fully contained address sets def mHideContained(containedBy: AddressSet): ManagerFilter = { m => val filtered = m.address.filterNot(containedBy.contains(_)) if (filtered.isEmpty) None else Some(m.v1copy(address = filtered)) } // hide all cacheable managers def mHideCacheable: ManagerFilter = { m => if (m.supportsAcquireB) None else Some(m) } // make visible only cacheable managers def mSelectCacheable: ManagerFilter = { m => if (m.supportsAcquireB) Some(m) else None } // cacheable managers cannot be acquired from def mMaskCacheable: ManagerFilter = { m => if (m.supportsAcquireB) { Some(m.v1copy( regionType = RegionType.UNCACHED, supportsAcquireB = TransferSizes.none, supportsAcquireT = TransferSizes.none, alwaysGrantsT = false)) } else { Some(m) } } // only cacheable managers are visible, but cannot be acquired from def mSelectAndMaskCacheable: ManagerFilter = { m => if (m.supportsAcquireB) { Some(m.v1copy( regionType = RegionType.UNCACHED, supportsAcquireB = TransferSizes.none, supportsAcquireT = TransferSizes.none, alwaysGrantsT = false)) } else { None } } // hide all caching clients def cHideCaching: ClientFilter = { c => if (c.supports.probe) None else Some(c) } // onyl caching clients are visible def cSelectCaching: ClientFilter = { c => if (c.supports.probe) Some(c) else None } // removes resources from managers def mResourceRemover: ManagerFilter = { m => Some(m.v2copy(resources=Nil)) } // default application applies neither type of filter unless overridden def apply( mfilter: ManagerFilter = TLFilter.mIdentity, cfilter: ClientFilter = TLFilter.cIdentity )(implicit p: Parameters): TLNode = { val filter = LazyModule(new TLFilter(mfilter, cfilter)) filter.node } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File Jbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet class TLJbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) extends LazyModule { val node: TLJunctionNode = new TLJunctionNode( clientFn = { seq => Seq.fill(node.dRatio)(seq(0).v1copy( minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } )) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() Seq.fill(node.uRatio)(seq(0).v1copy( minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } )) }) { override def circuitIdentity = uRatio == 1 && dRatio == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { node.inoutGrouped.foreach { case (in, out) => TLXbar.circuit(policy, in, out) } } } object TLJbar { def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) = { val jbar = LazyModule(new TLJbar(policy)) jbar.node } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLJbarTestImp(nClients: Int, nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val jbar = LazyModule(new TLJbar) val fuzzers = Seq.fill(nClients) { val fuzzer = LazyModule(new TLFuzzer(txns)) jbar.node :*= TLXbar() := TLDelayer(0.1) := fuzzer.node fuzzer } for (n <- 0 until nManagers) { TLRAM(AddressSet(0x0+0x400*n, 0x3ff)) := TLFragmenter(4, 256) := TLDelayer(0.1) := jbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.map(_.module.io.finished).reduce(_ && _) } } class TLJbarTest(nClients: Int, nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLJbarTestImp(nClients, nManagers, txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in || corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ || !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready || !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel | count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Configs.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tilelink._ import sifive.blocks.inclusivecache._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util._ import sifive.blocks.inclusivecache.InclusiveCacheParameters case class InclusiveCacheParams( ways: Int, sets: Int, writeBytes: Int, // backing store update granularity portFactor: Int, // numSubBanks = (widest TL port * portFactor) / writeBytes memCycles: Int, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) physicalFilter: Option[PhysicalFilterParams] = None, hintsSkipProbe: Boolean = false, // do hints probe the same client bankedControl: Boolean = false, // bank the cache ctrl with the cache banks ctrlAddr: Option[Int] = Some(InclusiveCacheParameters.L2ControlAddress), // Interior/Exterior refer to placement either inside the Scheduler or outside it // Inner/Outer refer to buffers on the front (towards cores) or back (towards DDR) of the L2 bufInnerInterior: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, bufInnerExterior: InclusiveCachePortParameters = InclusiveCachePortParameters.flowAD, bufOuterInterior: InclusiveCachePortParameters = InclusiveCachePortParameters.full, bufOuterExterior: InclusiveCachePortParameters = InclusiveCachePortParameters.none) case object InclusiveCacheKey extends Field[InclusiveCacheParams] class WithInclusiveCache( nWays: Int = 8, capacityKB: Int = 512, outerLatencyCycles: Int = 40, subBankingFactor: Int = 4, hintsSkipProbe: Boolean = false, bankedControl: Boolean = false, ctrlAddr: Option[Int] = Some(InclusiveCacheParameters.L2ControlAddress), writeBytes: Int = 8 ) extends Config((site, here, up) => { case InclusiveCacheKey => InclusiveCacheParams( sets = (capacityKB * 1024)/(site(CacheBlockBytes) * nWays * up(SubsystemBankedCoherenceKey, site).nBanks), ways = nWays, memCycles = outerLatencyCycles, writeBytes = writeBytes, portFactor = subBankingFactor, hintsSkipProbe = hintsSkipProbe, bankedControl = bankedControl, ctrlAddr = ctrlAddr) case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(coherenceManager = { context => implicit val p = context.p val sbus = context.tlBusWrapperLocationMap(SBUS) val cbus = context.tlBusWrapperLocationMap.lift(CBUS).getOrElse(sbus) val InclusiveCacheParams( ways, sets, writeBytes, portFactor, memCycles, physicalFilter, hintsSkipProbe, bankedControl, ctrlAddr, bufInnerInterior, bufInnerExterior, bufOuterInterior, bufOuterExterior) = p(InclusiveCacheKey) val l2Ctrl = ctrlAddr.map { addr => InclusiveCacheControlParameters( address = addr, beatBytes = cbus.beatBytes, bankedControl = bankedControl) } val l2 = LazyModule(new InclusiveCache( CacheParameters( level = 2, ways = ways, sets = sets, blockBytes = sbus.blockBytes, beatBytes = sbus.beatBytes, hintsSkipProbe = hintsSkipProbe), InclusiveCacheMicroParameters( writeBytes = writeBytes, portFactor = portFactor, memCycles = memCycles, innerBuf = bufInnerInterior, outerBuf = bufOuterInterior), l2Ctrl)) def skipMMIO(x: TLClientParameters) = { val dcacheMMIO = x.requestFifo && x.sourceId.start % 2 == 1 && // 1 => dcache issues acquires from another master x.nodePath.last.name == "dcache.node" if (dcacheMMIO) None else Some(x) } val filter = LazyModule(new TLFilter(cfilter = skipMMIO)) val l2_inner_buffer = bufInnerExterior() val l2_outer_buffer = bufOuterExterior() val cork = LazyModule(new TLCacheCork) val lastLevelNode = cork.node l2_inner_buffer.suggestName("InclusiveCache_inner_TLBuffer") l2_outer_buffer.suggestName("InclusiveCache_outer_TLBuffer") l2_inner_buffer.node :*= filter.node l2.node :*= l2_inner_buffer.node l2_outer_buffer.node :*= l2.node /* PhysicalFilters need to be on the TL-C side of a CacheCork to prevent Acquire.NtoB -> Grant.toT */ physicalFilter match { case None => lastLevelNode :*= l2_outer_buffer.node case Some(fp) => { val physicalFilter = LazyModule(new PhysicalFilter(fp.copy(controlBeatBytes = cbus.beatBytes))) lastLevelNode :*= physicalFilter.node :*= l2_outer_buffer.node physicalFilter.controlNode := cbus.coupleTo("physical_filter") { TLBuffer(1) := TLFragmenter(cbus, Some("LLCPhysicalFilter")) := _ } } } l2.ctrls.foreach { _.ctrlnode := cbus.coupleTo("l2_ctrl") { TLBuffer(1) := TLFragmenter(cbus, Some("LLCCtrl")) := _ } } ElaborationArtefacts.add("l2.json", l2.module.json) (filter.node, lastLevelNode, None) }) }) File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }

module CoherenceManagerWrapper( // @[ClockDomain.scala:14:9] input auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coherent_jbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_coherent_jbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coherent_jbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coherent_jbar_anon_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coherent_jbar_anon_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coherent_jbar_anon_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coherent_jbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coherent_jbar_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coherent_jbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coherent_jbar_anon_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_l2_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_l2_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_l2_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_l2_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_l2_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_l2_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_l2_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_l2_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_l2_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_l2_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coh_clock_groups_in_member_coh_0_clock, // @[LazyModuleImp.scala:107:25] input auto_coh_clock_groups_in_member_coh_0_reset // @[LazyModuleImp.scala:107:25] ); wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [4:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [3:0] coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:216:19] wire [3:0] coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [6:0] coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire filter_auto_anon_out_d_valid; // @[Filter.scala:60:9] wire filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9] wire filter_auto_anon_out_c_ready; // @[Filter.scala:60:9] wire filter_auto_anon_out_b_valid; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9] wire filter_auto_anon_out_a_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_e_valid; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_in_d_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_bits_denied; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_in_d_bits_sink; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_in_d_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_d_bits_size; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_in_d_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_d_bits_opcode; // @[Filter.scala:60:9] wire filter_auto_anon_in_c_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_c_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9] wire filter_auto_anon_in_b_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_b_ready; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_in_b_bits_address; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_in_b_bits_param; // @[Filter.scala:60:9] wire filter_auto_anon_in_a_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_a_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9] wire [15:0] filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9] wire fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] wire fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:53:9] wire _binder_auto_in_a_ready; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_valid; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_d_bits_opcode; // @[BankBinder.scala:71:28] wire [1:0] _binder_auto_in_d_bits_param; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_d_bits_size; // @[BankBinder.scala:71:28] wire [4:0] _binder_auto_in_d_bits_source; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_bits_sink; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_bits_denied; // @[BankBinder.scala:71:28] wire [63:0] _binder_auto_in_d_bits_data; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_bits_corrupt; // @[BankBinder.scala:71:28] wire _cork_auto_out_a_valid; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_a_bits_opcode; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_a_bits_param; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_a_bits_size; // @[Configs.scala:120:26] wire [4:0] _cork_auto_out_a_bits_source; // @[Configs.scala:120:26] wire [31:0] _cork_auto_out_a_bits_address; // @[Configs.scala:120:26] wire [7:0] _cork_auto_out_a_bits_mask; // @[Configs.scala:120:26] wire [63:0] _cork_auto_out_a_bits_data; // @[Configs.scala:120:26] wire _cork_auto_out_a_bits_corrupt; // @[Configs.scala:120:26] wire _cork_auto_out_d_ready; // @[Configs.scala:120:26] wire _InclusiveCache_inner_TLBuffer_auto_out_a_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_size; // @[Parameters.scala:56:69] wire [6:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_address; // @[Parameters.scala:56:69] wire [15:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask; // @[Parameters.scala:56:69] wire [127:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_b_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_c_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_size; // @[Parameters.scala:56:69] wire [6:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_address; // @[Parameters.scala:56:69] wire [127:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_d_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_e_valid; // @[Parameters.scala:56:69] wire [3:0] _InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink; // @[Parameters.scala:56:69] wire _l2_auto_in_a_ready; // @[Configs.scala:93:24] wire _l2_auto_in_b_valid; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_b_bits_param; // @[Configs.scala:93:24] wire [31:0] _l2_auto_in_b_bits_address; // @[Configs.scala:93:24] wire _l2_auto_in_c_ready; // @[Configs.scala:93:24] wire _l2_auto_in_d_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_d_bits_opcode; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_d_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_d_bits_size; // @[Configs.scala:93:24] wire [6:0] _l2_auto_in_d_bits_source; // @[Configs.scala:93:24] wire [3:0] _l2_auto_in_d_bits_sink; // @[Configs.scala:93:24] wire _l2_auto_in_d_bits_denied; // @[Configs.scala:93:24] wire [127:0] _l2_auto_in_d_bits_data; // @[Configs.scala:93:24] wire _l2_auto_in_d_bits_corrupt; // @[Configs.scala:93:24] wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_a_valid_0 = auto_coherent_jbar_anon_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_a_bits_opcode_0 = auto_coherent_jbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_a_bits_param_0 = auto_coherent_jbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_a_bits_size_0 = auto_coherent_jbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_coherent_jbar_anon_in_a_bits_source_0 = auto_coherent_jbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coherent_jbar_anon_in_a_bits_address_0 = auto_coherent_jbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] auto_coherent_jbar_anon_in_a_bits_mask_0 = auto_coherent_jbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] auto_coherent_jbar_anon_in_a_bits_data_0 = auto_coherent_jbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_a_bits_corrupt_0 = auto_coherent_jbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_b_ready_0 = auto_coherent_jbar_anon_in_b_ready; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_c_valid_0 = auto_coherent_jbar_anon_in_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_c_bits_opcode_0 = auto_coherent_jbar_anon_in_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_c_bits_param_0 = auto_coherent_jbar_anon_in_c_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_c_bits_size_0 = auto_coherent_jbar_anon_in_c_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_coherent_jbar_anon_in_c_bits_source_0 = auto_coherent_jbar_anon_in_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coherent_jbar_anon_in_c_bits_address_0 = auto_coherent_jbar_anon_in_c_bits_address; // @[ClockDomain.scala:14:9] wire [127:0] auto_coherent_jbar_anon_in_c_bits_data_0 = auto_coherent_jbar_anon_in_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_c_bits_corrupt_0 = auto_coherent_jbar_anon_in_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_ready_0 = auto_coherent_jbar_anon_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_e_valid_0 = auto_coherent_jbar_anon_in_e_valid; // @[ClockDomain.scala:14:9] wire [3:0] auto_coherent_jbar_anon_in_e_bits_sink_0 = auto_coherent_jbar_anon_in_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_a_valid_0 = auto_l2_ctrls_ctrl_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode_0 = auto_l2_ctrls_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_param_0 = auto_l2_ctrls_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [1:0] auto_l2_ctrls_ctrl_in_a_bits_size_0 = auto_l2_ctrls_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [11:0] auto_l2_ctrls_ctrl_in_a_bits_source_0 = auto_l2_ctrls_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [25:0] auto_l2_ctrls_ctrl_in_a_bits_address_0 = auto_l2_ctrls_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask_0 = auto_l2_ctrls_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_l2_ctrls_ctrl_in_a_bits_data_0 = auto_l2_ctrls_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_a_bits_corrupt_0 = auto_l2_ctrls_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_ready_0 = auto_l2_ctrls_ctrl_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_coh_clock_groups_in_member_coh_0_clock_0 = auto_coh_clock_groups_in_member_coh_0_clock; // @[ClockDomain.scala:14:9] wire auto_coh_clock_groups_in_member_coh_0_reset_0 = auto_coh_clock_groups_in_member_coh_0_reset; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] filter_auto_anon_in_b_bits_opcode = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_b_bits_size = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_b_bits_opcode = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_b_bits_size = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] filter_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] filter_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_auto_anon_in_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_b_bits_size = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_out_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_out_b_bits_size = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coherent_jbar_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coherent_jbar_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_in_0_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_b_bits_size = 3'h6; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_out_0_b_bits_opcode = 3'h6; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_out_0_b_bits_size = 3'h6; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_size = 3'h6; // @[Xbar.scala:352:24] wire [6:0] auto_coherent_jbar_anon_in_b_bits_source = 7'h40; // @[ClockDomain.scala:14:9] wire [6:0] filter_auto_anon_in_b_bits_source = 7'h40; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_b_bits_source = 7'h40; // @[Filter.scala:60:9] wire [6:0] filter_anonOut_b_bits_source = 7'h40; // @[MixedNode.scala:542:17] wire [6:0] filter_anonIn_b_bits_source = 7'h40; // @[MixedNode.scala:551:17] wire [6:0] coherent_jbar_auto_anon_in_b_bits_source = 7'h40; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_out_b_bits_source = 7'h40; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_b_bits_source = 7'h40; // @[MixedNode.scala:542:17] wire [6:0] coherent_jbar_anonIn_b_bits_source = 7'h40; // @[MixedNode.scala:551:17] wire [6:0] coherent_jbar_in_0_b_bits_source = 7'h40; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar__anonIn_b_bits_source_T = 7'h40; // @[Xbar.scala:156:69] wire [6:0] coherent_jbar_out_0_b_bits_source = 7'h40; // @[Xbar.scala:216:19] wire [6:0] coherent_jbar__requestBOI_uncommonBits_T = 7'h40; // @[Parameters.scala:52:29] wire [6:0] coherent_jbar_requestBOI_uncommonBits = 7'h40; // @[Parameters.scala:52:56] wire [6:0] coherent_jbar_portsBIO_filtered_0_bits_source = 7'h40; // @[Xbar.scala:352:24] wire [15:0] auto_coherent_jbar_anon_in_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9] wire [15:0] filter_auto_anon_in_b_bits_mask = 16'hFFFF; // @[Filter.scala:60:9] wire [15:0] filter_auto_anon_out_b_bits_mask = 16'hFFFF; // @[Filter.scala:60:9] wire [15:0] filter_anonOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] filter_anonIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coherent_jbar_auto_anon_in_b_bits_mask = 16'hFFFF; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_auto_anon_out_b_bits_mask = 16'hFFFF; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_anonOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] coherent_jbar_anonIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coherent_jbar_in_0_b_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] coherent_jbar_out_0_b_bits_mask = 16'hFFFF; // @[Xbar.scala:216:19] wire [15:0] coherent_jbar_portsBIO_filtered_0_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [127:0] auto_coherent_jbar_anon_in_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9] wire [127:0] filter_auto_anon_in_b_bits_data = 128'h0; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_b_bits_data = 128'h0; // @[Filter.scala:60:9] wire [127:0] filter_anonOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] filter_anonIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coherent_jbar_auto_anon_in_b_bits_data = 128'h0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_out_b_bits_data = 128'h0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coherent_jbar_anonIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coherent_jbar_in_0_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_out_0_b_bits_data = 128'h0; // @[Xbar.scala:216:19] wire [127:0] coherent_jbar_portsBIO_filtered_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire auto_coherent_jbar_anon_in_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire coh_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire coh_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire coh_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixedClockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire fixedClockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire fixedClockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire filter_auto_anon_in_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9] wire filter_auto_anon_out_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9] wire filter_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire filter_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_auto_in_b_valid = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_b_valid = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_b_valid = 1'h0; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeIn_b_valid = 1'h0; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_in_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coherent_jbar_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coherent_jbar_in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire coherent_jbar_out_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire coherent_jbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire coherent_jbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire coherent_jbar__requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire coherent_jbar_beatsBO_opdata = 1'h0; // @[Edges.scala:97:28] wire coherent_jbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire auto_coherent_jbar_anon_in_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire filter_auto_anon_in_e_ready = 1'h1; // @[Filter.scala:60:9] wire filter_auto_anon_out_e_ready = 1'h1; // @[Filter.scala:60:9] wire filter_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire filter_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_auto_in_b_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_e_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_b_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_e_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_b_ready = 1'h1; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeIn_b_ready = 1'h1; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_in_e_ready = 1'h1; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_e_ready = 1'h1; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coherent_jbar_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coherent_jbar_in_0_e_ready = 1'h1; // @[Xbar.scala:159:18] wire coherent_jbar_out_0_e_ready = 1'h1; // @[Xbar.scala:216:19] wire coherent_jbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire coherent_jbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire coherent_jbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire coherent_jbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire coherent_jbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire coherent_jbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire coherent_jbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire coherent_jbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire coherent_jbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire coherent_jbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire coherent_jbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire coherent_jbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire coherent_jbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire coherent_jbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire coherent_jbar__requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire coherent_jbar__requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire coherent_jbar__requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire coherent_jbar__requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire coherent_jbar_requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48] wire coherent_jbar__beatsBO_opdata_T = 1'h1; // @[Edges.scala:97:37] wire coherent_jbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar_portsEOI_filtered_0_ready = 1'h1; // @[Xbar.scala:352:24] wire coherent_jbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] coherent_jbar_beatsBO_0 = 2'h0; // @[Edges.scala:221:14] wire [1:0] coherent_jbar_beatsBO_decode = 2'h3; // @[Edges.scala:220:59] wire [5:0] coherent_jbar__beatsBO_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] coherent_jbar__beatsBO_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] coherent_jbar__beatsBO_decode_T = 13'hFC0; // @[package.scala:243:71] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_size = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_size = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_size = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_size = 3'h0; // @[MixedNode.scala:551:17] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_source = 4'h0; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_source = 4'h0; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_source = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_source = 4'h0; // @[MixedNode.scala:551:17] wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_address = 32'h0; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_address = 32'h0; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_address = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_address = 32'h0; // @[MixedNode.scala:551:17] wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_mask = 8'h0; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_mask = 8'h0; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_mask = 8'h0; // @[MixedNode.scala:542:17] wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_data = 64'h0; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_data = 64'h0; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [32:0] coherent_jbar__requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] coherent_jbar__requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] coherent_jbar__requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] coherent_jbar__requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coherent_jbar_auto_anon_in_a_valid = auto_coherent_jbar_anon_in_a_valid_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_a_bits_opcode = auto_coherent_jbar_anon_in_a_bits_opcode_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_a_bits_param = auto_coherent_jbar_anon_in_a_bits_param_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_a_bits_size = auto_coherent_jbar_anon_in_a_bits_size_0; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_in_a_bits_source = auto_coherent_jbar_anon_in_a_bits_source_0; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_auto_anon_in_a_bits_address = auto_coherent_jbar_anon_in_a_bits_address_0; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_auto_anon_in_a_bits_mask = auto_coherent_jbar_anon_in_a_bits_mask_0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_in_a_bits_data = auto_coherent_jbar_anon_in_a_bits_data_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_a_bits_corrupt = auto_coherent_jbar_anon_in_a_bits_corrupt_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_b_ready = auto_coherent_jbar_anon_in_b_ready_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_c_valid = auto_coherent_jbar_anon_in_c_valid_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_c_bits_opcode = auto_coherent_jbar_anon_in_c_bits_opcode_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_c_bits_param = auto_coherent_jbar_anon_in_c_bits_param_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_c_bits_size = auto_coherent_jbar_anon_in_c_bits_size_0; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_in_c_bits_source = auto_coherent_jbar_anon_in_c_bits_source_0; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_auto_anon_in_c_bits_address = auto_coherent_jbar_anon_in_c_bits_address_0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_in_c_bits_data = auto_coherent_jbar_anon_in_c_bits_data_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_c_bits_corrupt = auto_coherent_jbar_anon_in_c_bits_corrupt_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_ready = auto_coherent_jbar_anon_in_d_ready_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_e_valid = auto_coherent_jbar_anon_in_e_valid_0; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_auto_anon_in_e_bits_sink = auto_coherent_jbar_anon_in_e_bits_sink_0; // @[Jbar.scala:44:9] wire coh_clock_groups_auto_in_member_coh_0_clock = auto_coh_clock_groups_in_member_coh_0_clock_0; // @[ClockGroup.scala:53:9] wire coh_clock_groups_auto_in_member_coh_0_reset = auto_coh_clock_groups_in_member_coh_0_reset_0; // @[ClockGroup.scala:53:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire coh_clock_groups_nodeIn_member_coh_0_clock = coh_clock_groups_auto_in_member_coh_0_clock; // @[ClockGroup.scala:53:9] wire coh_clock_groups_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17] wire coh_clock_groups_nodeIn_member_coh_0_reset = coh_clock_groups_auto_in_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire coh_clock_groups_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_coh_0_clock = coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_coh_0_reset = coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign coh_clock_groups_auto_out_member_coh_0_clock = coh_clock_groups_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9] assign coh_clock_groups_auto_out_member_coh_0_reset = coh_clock_groups_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9] assign coh_clock_groups_nodeOut_member_coh_0_clock = coh_clock_groups_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17] assign coh_clock_groups_nodeOut_member_coh_0_reset = coh_clock_groups_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_coh_0_clock = clockGroup_auto_in_member_coh_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_coh_0_reset = clockGroup_auto_in_member_coh_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire fixedClockNode_auto_anon_in_clock = clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9, :104:9] wire fixedClockNode_auto_anon_in_reset = clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9, :104:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixedClockNode_anonIn_clock = fixedClockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire fixedClockNode_anonOut_clock; // @[MixedNode.scala:542:17] wire fixedClockNode_anonIn_reset = fixedClockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] wire fixedClockNode_anonOut_reset; // @[MixedNode.scala:542:17] assign clockSinkNodeIn_clock = fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] assign clockSinkNodeIn_reset = fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] assign fixedClockNode_auto_anon_out_clock = fixedClockNode_anonOut_clock; // @[ClockGroup.scala:104:9] assign fixedClockNode_auto_anon_out_reset = fixedClockNode_anonOut_reset; // @[ClockGroup.scala:104:9] assign fixedClockNode_anonOut_clock = fixedClockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17] assign fixedClockNode_anonOut_reset = fixedClockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17] wire filter_anonIn_a_ready; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_a_ready = filter_auto_anon_in_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9] wire filter_anonIn_a_valid = filter_auto_anon_in_a_valid; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_a_bits_opcode = filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_a_bits_param = filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_a_bits_size = filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9] wire [6:0] coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9] wire [6:0] filter_anonIn_a_bits_source = filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9] wire [31:0] coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9] wire [31:0] filter_anonIn_a_bits_address = filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9] wire [15:0] coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9] wire [15:0] filter_anonIn_a_bits_mask = filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9] wire [127:0] coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9] wire [127:0] filter_anonIn_a_bits_data = filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9] wire filter_anonIn_a_bits_corrupt = filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9] wire filter_anonIn_b_ready = filter_auto_anon_in_b_ready; // @[Filter.scala:60:9] wire filter_anonIn_b_valid; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_b_valid = filter_auto_anon_in_b_valid; // @[Jbar.scala:44:9] wire [1:0] filter_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coherent_jbar_auto_anon_out_b_bits_param = filter_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] filter_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [31:0] coherent_jbar_auto_anon_out_b_bits_address = filter_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9] wire filter_anonIn_c_ready; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_c_ready = filter_auto_anon_in_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9] wire filter_anonIn_c_valid = filter_auto_anon_in_c_valid; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_c_bits_opcode = filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_c_bits_param = filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_c_bits_size = filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9] wire [6:0] coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9] wire [6:0] filter_anonIn_c_bits_source = filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9] wire [31:0] coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9] wire [31:0] filter_anonIn_c_bits_address = filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9] wire [127:0] coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9] wire [127:0] filter_anonIn_c_bits_data = filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9] wire filter_anonIn_c_bits_corrupt = filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9] wire filter_anonIn_d_ready = filter_auto_anon_in_d_ready; // @[Filter.scala:60:9] wire filter_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] filter_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_d_valid = filter_auto_anon_in_d_valid; // @[Jbar.scala:44:9] wire [1:0] filter_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_auto_anon_out_d_bits_opcode = filter_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coherent_jbar_auto_anon_out_d_bits_param = filter_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9] wire [6:0] filter_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_auto_anon_out_d_bits_size = filter_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9] wire [3:0] filter_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [6:0] coherent_jbar_auto_anon_out_d_bits_source = filter_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9] wire filter_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [3:0] coherent_jbar_auto_anon_out_d_bits_sink = filter_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9] wire [127:0] filter_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_d_bits_denied = filter_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9] wire filter_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [127:0] coherent_jbar_auto_anon_out_d_bits_data = filter_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_d_bits_corrupt = filter_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9] wire filter_anonIn_e_valid = filter_auto_anon_in_e_valid; // @[Filter.scala:60:9] wire [3:0] coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9] wire [3:0] filter_anonIn_e_bits_sink = filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9] wire filter_anonOut_a_ready = filter_auto_anon_out_a_ready; // @[Filter.scala:60:9] wire filter_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] filter_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] filter_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] filter_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] filter_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire filter_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire filter_anonOut_b_ready; // @[MixedNode.scala:542:17] wire filter_anonOut_b_valid = filter_auto_anon_out_b_valid; // @[Filter.scala:60:9] wire [1:0] filter_anonOut_b_bits_param = filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9] wire [31:0] filter_anonOut_b_bits_address = filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9] wire filter_anonOut_c_ready = filter_auto_anon_out_c_ready; // @[Filter.scala:60:9] wire filter_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [6:0] filter_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] filter_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] filter_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire filter_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire filter_anonOut_d_ready; // @[MixedNode.scala:542:17] wire filter_anonOut_d_valid = filter_auto_anon_out_d_valid; // @[Filter.scala:60:9] wire [2:0] filter_anonOut_d_bits_opcode = filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9] wire [1:0] filter_anonOut_d_bits_param = filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_anonOut_d_bits_size = filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9] wire [6:0] filter_anonOut_d_bits_source = filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9] wire [3:0] filter_anonOut_d_bits_sink = filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9] wire filter_anonOut_d_bits_denied = filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9] wire [127:0] filter_anonOut_d_bits_data = filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9] wire filter_anonOut_d_bits_corrupt = filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9] wire filter_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] filter_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] filter_auto_anon_out_a_bits_opcode; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_a_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_a_bits_size; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_a_bits_source; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_out_a_bits_address; // @[Filter.scala:60:9] wire [15:0] filter_auto_anon_out_a_bits_mask; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_a_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_out_a_bits_corrupt; // @[Filter.scala:60:9] wire filter_auto_anon_out_a_valid; // @[Filter.scala:60:9] wire filter_auto_anon_out_b_ready; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_c_bits_opcode; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_c_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_c_bits_size; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_c_bits_source; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_out_c_bits_address; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_c_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_out_c_bits_corrupt; // @[Filter.scala:60:9] wire filter_auto_anon_out_c_valid; // @[Filter.scala:60:9] wire filter_auto_anon_out_d_ready; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_out_e_bits_sink; // @[Filter.scala:60:9] wire filter_auto_anon_out_e_valid; // @[Filter.scala:60:9] assign filter_anonIn_a_ready = filter_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_out_a_valid = filter_anonOut_a_valid; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_opcode = filter_anonOut_a_bits_opcode; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_param = filter_anonOut_a_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_size = filter_anonOut_a_bits_size; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_source = filter_anonOut_a_bits_source; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_address = filter_anonOut_a_bits_address; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_mask = filter_anonOut_a_bits_mask; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_data = filter_anonOut_a_bits_data; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_corrupt = filter_anonOut_a_bits_corrupt; // @[Filter.scala:60:9] assign filter_auto_anon_out_b_ready = filter_anonOut_b_ready; // @[Filter.scala:60:9] assign filter_anonIn_b_valid = filter_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_b_bits_param = filter_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_b_bits_address = filter_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_c_ready = filter_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_out_c_valid = filter_anonOut_c_valid; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_opcode = filter_anonOut_c_bits_opcode; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_param = filter_anonOut_c_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_size = filter_anonOut_c_bits_size; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_source = filter_anonOut_c_bits_source; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_address = filter_anonOut_c_bits_address; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_data = filter_anonOut_c_bits_data; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_corrupt = filter_anonOut_c_bits_corrupt; // @[Filter.scala:60:9] assign filter_auto_anon_out_d_ready = filter_anonOut_d_ready; // @[Filter.scala:60:9] assign filter_anonIn_d_valid = filter_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_opcode = filter_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_param = filter_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_size = filter_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_source = filter_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_sink = filter_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_denied = filter_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_data = filter_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_corrupt = filter_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_out_e_valid = filter_anonOut_e_valid; // @[Filter.scala:60:9] assign filter_auto_anon_out_e_bits_sink = filter_anonOut_e_bits_sink; // @[Filter.scala:60:9] assign filter_auto_anon_in_a_ready = filter_anonIn_a_ready; // @[Filter.scala:60:9] assign filter_anonOut_a_valid = filter_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_opcode = filter_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_param = filter_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_size = filter_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_source = filter_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_address = filter_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_mask = filter_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_data = filter_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_corrupt = filter_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_b_ready = filter_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_in_b_valid = filter_anonIn_b_valid; // @[Filter.scala:60:9] assign filter_auto_anon_in_b_bits_param = filter_anonIn_b_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_in_b_bits_address = filter_anonIn_b_bits_address; // @[Filter.scala:60:9] assign filter_auto_anon_in_c_ready = filter_anonIn_c_ready; // @[Filter.scala:60:9] assign filter_anonOut_c_valid = filter_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_opcode = filter_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_param = filter_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_size = filter_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_source = filter_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_address = filter_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_data = filter_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_corrupt = filter_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_d_ready = filter_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_in_d_valid = filter_anonIn_d_valid; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_opcode = filter_anonIn_d_bits_opcode; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_param = filter_anonIn_d_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_size = filter_anonIn_d_bits_size; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_source = filter_anonIn_d_bits_source; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_sink = filter_anonIn_d_bits_sink; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_denied = filter_anonIn_d_bits_denied; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_data = filter_anonIn_d_bits_data; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_corrupt = filter_anonIn_d_bits_corrupt; // @[Filter.scala:60:9] assign filter_anonOut_e_valid = filter_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_e_bits_sink = filter_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_a_valid = InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param = InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size = InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source = InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address = InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask = InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data = InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_c_valid = InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param = InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size = InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source = InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address = InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data = InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_d_ready = InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_e_valid = InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink = InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_a_ready = InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_c_ready = InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_d_valid = InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode = InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param = InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size = InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source = InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink = InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied = InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data = InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_e_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeIn_a_ready = InclusiveCache_outer_TLBuffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_out_a_valid = InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeIn_c_ready = InclusiveCache_outer_TLBuffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_out_c_valid = InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_d_ready = InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeIn_d_valid = InclusiveCache_outer_TLBuffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_out_e_valid = InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_a_ready = InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeOut_a_valid = InclusiveCache_outer_TLBuffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_in_c_ready = InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeOut_c_valid = InclusiveCache_outer_TLBuffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_d_ready = InclusiveCache_outer_TLBuffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_in_d_valid = InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeOut_e_valid = InclusiveCache_outer_TLBuffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coherent_jbar_anonIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_a_ready_0 = coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_a_valid = coherent_jbar_auto_anon_in_a_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_a_bits_opcode = coherent_jbar_auto_anon_in_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_a_bits_param = coherent_jbar_auto_anon_in_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_a_bits_size = coherent_jbar_auto_anon_in_a_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonIn_a_bits_source = coherent_jbar_auto_anon_in_a_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonIn_a_bits_address = coherent_jbar_auto_anon_in_a_bits_address; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_anonIn_a_bits_mask = coherent_jbar_auto_anon_in_a_bits_mask; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonIn_a_bits_data = coherent_jbar_auto_anon_in_a_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_a_bits_corrupt = coherent_jbar_auto_anon_in_a_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_b_ready = coherent_jbar_auto_anon_in_b_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_b_valid_0 = coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_b_bits_param_0 = coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_b_bits_address_0 = coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_c_ready_0 = coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_c_valid = coherent_jbar_auto_anon_in_c_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_c_bits_opcode = coherent_jbar_auto_anon_in_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_c_bits_param = coherent_jbar_auto_anon_in_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_c_bits_size = coherent_jbar_auto_anon_in_c_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonIn_c_bits_source = coherent_jbar_auto_anon_in_c_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonIn_c_bits_address = coherent_jbar_auto_anon_in_c_bits_address; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonIn_c_bits_data = coherent_jbar_auto_anon_in_c_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_c_bits_corrupt = coherent_jbar_auto_anon_in_c_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_ready = coherent_jbar_auto_anon_in_d_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_valid_0 = coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_opcode_0 = coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_param_0 = coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_size_0 = coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_source_0 = coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_sink_0 = coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_denied_0 = coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_data_0 = coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_corrupt_0 = coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_e_valid = coherent_jbar_auto_anon_in_e_valid; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonIn_e_bits_sink = coherent_jbar_auto_anon_in_e_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_a_ready = coherent_jbar_auto_anon_out_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_a_valid; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_valid = coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_opcode = coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_param = coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_size = coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_source = coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_address = coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_mask = coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_data = coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_corrupt = coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_b_ready; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_b_ready = coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_b_valid = coherent_jbar_auto_anon_out_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonOut_b_bits_param = coherent_jbar_auto_anon_out_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonOut_b_bits_address = coherent_jbar_auto_anon_out_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_c_ready = coherent_jbar_auto_anon_out_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_c_valid; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_valid = coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_opcode = coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_c_bits_param; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_param = coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_c_bits_size; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_size = coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_c_bits_source; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_source = coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonOut_c_bits_address; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_address = coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_c_bits_data; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_data = coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_corrupt = coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_ready; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_d_ready = coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_valid = coherent_jbar_auto_anon_out_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_d_bits_opcode = coherent_jbar_auto_anon_out_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonOut_d_bits_param = coherent_jbar_auto_anon_out_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_d_bits_size = coherent_jbar_auto_anon_out_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_d_bits_source = coherent_jbar_auto_anon_out_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonOut_d_bits_sink = coherent_jbar_auto_anon_out_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_bits_denied = coherent_jbar_auto_anon_out_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_d_bits_data = coherent_jbar_auto_anon_out_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_bits_corrupt = coherent_jbar_auto_anon_out_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_e_valid; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_e_valid = coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_e_bits_sink = coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_a_ready = coherent_jbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_valid = coherent_jbar_anonOut_a_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_opcode = coherent_jbar_anonOut_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_param = coherent_jbar_anonOut_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_size = coherent_jbar_anonOut_a_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_source = coherent_jbar_anonOut_a_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_address = coherent_jbar_anonOut_a_bits_address; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_mask = coherent_jbar_anonOut_a_bits_mask; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_data = coherent_jbar_anonOut_a_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_corrupt = coherent_jbar_anonOut_a_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_b_ready = coherent_jbar_anonOut_b_ready; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_b_valid = coherent_jbar_anonOut_b_valid; // @[Xbar.scala:216:19] wire [1:0] coherent_jbar_out_0_b_bits_param = coherent_jbar_anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [31:0] coherent_jbar_out_0_b_bits_address = coherent_jbar_anonOut_b_bits_address; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_c_ready = coherent_jbar_anonOut_c_ready; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_valid = coherent_jbar_anonOut_c_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_opcode = coherent_jbar_anonOut_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_param = coherent_jbar_anonOut_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_size = coherent_jbar_anonOut_c_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_source = coherent_jbar_anonOut_c_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_address = coherent_jbar_anonOut_c_bits_address; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_data = coherent_jbar_anonOut_c_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_corrupt = coherent_jbar_anonOut_c_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_d_ready = coherent_jbar_anonOut_d_ready; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_d_valid = coherent_jbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_out_0_d_bits_opcode = coherent_jbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] coherent_jbar_out_0_d_bits_param = coherent_jbar_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_out_0_d_bits_size = coherent_jbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [6:0] coherent_jbar_out_0_d_bits_source = coherent_jbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [3:0] coherent_jbar__out_0_d_bits_sink_T = coherent_jbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire coherent_jbar_out_0_d_bits_denied = coherent_jbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [127:0] coherent_jbar_out_0_d_bits_data = coherent_jbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_d_bits_corrupt = coherent_jbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_e_valid = coherent_jbar_anonOut_e_valid; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign coherent_jbar_auto_anon_out_e_bits_sink = coherent_jbar_anonOut_e_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_a_ready = coherent_jbar_anonIn_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_a_valid = coherent_jbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_a_bits_opcode = coherent_jbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_a_bits_param = coherent_jbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_a_bits_size = coherent_jbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar__in_0_a_bits_source_T = coherent_jbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] coherent_jbar_in_0_a_bits_address = coherent_jbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] coherent_jbar_in_0_a_bits_mask = coherent_jbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_in_0_a_bits_data = coherent_jbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_a_bits_corrupt = coherent_jbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_b_ready = coherent_jbar_anonIn_b_ready; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_b_valid = coherent_jbar_anonIn_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_b_bits_param = coherent_jbar_anonIn_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_b_bits_address = coherent_jbar_anonIn_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_c_ready = coherent_jbar_anonIn_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_c_valid = coherent_jbar_anonIn_c_valid; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_c_bits_opcode = coherent_jbar_anonIn_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_c_bits_param = coherent_jbar_anonIn_c_bits_param; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_c_bits_size = coherent_jbar_anonIn_c_bits_size; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar__in_0_c_bits_source_T = coherent_jbar_anonIn_c_bits_source; // @[Xbar.scala:187:55] wire [31:0] coherent_jbar_in_0_c_bits_address = coherent_jbar_anonIn_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_in_0_c_bits_data = coherent_jbar_anonIn_c_bits_data; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_c_bits_corrupt = coherent_jbar_anonIn_c_bits_corrupt; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_d_ready = coherent_jbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_valid = coherent_jbar_anonIn_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_opcode = coherent_jbar_anonIn_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_param = coherent_jbar_anonIn_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_size = coherent_jbar_anonIn_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign coherent_jbar_auto_anon_in_d_bits_source = coherent_jbar_anonIn_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_sink = coherent_jbar_anonIn_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_denied = coherent_jbar_anonIn_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_data = coherent_jbar_anonIn_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_corrupt = coherent_jbar_anonIn_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_e_valid = coherent_jbar_anonIn_e_valid; // @[Xbar.scala:159:18] wire [3:0] coherent_jbar_in_0_e_bits_sink = coherent_jbar_anonIn_e_bits_sink; // @[Xbar.scala:159:18] wire coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_a_ready = coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18] wire coherent_jbar__portsAOI_filtered_0_valid_T_1 = coherent_jbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_opcode = coherent_jbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_param = coherent_jbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_size = coherent_jbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] coherent_jbar_portsAOI_filtered_0_bits_source = coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] coherent_jbar__requestAIO_T = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] coherent_jbar_portsAOI_filtered_0_bits_address = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] coherent_jbar_portsAOI_filtered_0_bits_mask = coherent_jbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] coherent_jbar_portsAOI_filtered_0_bits_data = coherent_jbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsAOI_filtered_0_bits_corrupt = coherent_jbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsBIO_filtered_0_ready = coherent_jbar_in_0_b_ready; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_b_valid = coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18] wire [1:0] coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_b_bits_param = coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18] wire [31:0] coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_b_bits_address = coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18] wire coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_c_ready = coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18] wire coherent_jbar__portsCOI_filtered_0_valid_T_1 = coherent_jbar_in_0_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_opcode = coherent_jbar_in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_param = coherent_jbar_in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_size = coherent_jbar_in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] coherent_jbar_portsCOI_filtered_0_bits_source = coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] coherent_jbar__requestCIO_T = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] coherent_jbar_portsCOI_filtered_0_bits_address = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] coherent_jbar_portsCOI_filtered_0_bits_data = coherent_jbar_in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsCOI_filtered_0_bits_corrupt = coherent_jbar_in_0_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsDIO_filtered_0_ready = coherent_jbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_valid = coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_opcode = coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_param = coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_size = coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign coherent_jbar__anonIn_d_bits_source_T = coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire [3:0] coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_sink = coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] wire coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_denied = coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_data = coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_corrupt = coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire coherent_jbar__portsEOI_filtered_0_valid_T_1 = coherent_jbar_in_0_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] coherent_jbar__requestEIO_uncommonBits_T = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18] wire [3:0] coherent_jbar_portsEOI_filtered_0_bits_sink = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_a_bits_source = coherent_jbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign coherent_jbar_in_0_c_bits_source = coherent_jbar__in_0_c_bits_source_T; // @[Xbar.scala:159:18, :187:55] assign coherent_jbar_anonIn_d_bits_source = coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign coherent_jbar_portsAOI_filtered_0_ready = coherent_jbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonOut_a_valid = coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_opcode = coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_param = coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_size = coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_source = coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_address = coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_mask = coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_data = coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_corrupt = coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_b_ready = coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19] wire coherent_jbar__portsBIO_filtered_0_valid_T_1 = coherent_jbar_out_0_b_valid; // @[Xbar.scala:216:19, :355:40] assign coherent_jbar_portsBIO_filtered_0_bits_param = coherent_jbar_out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsBIO_filtered_0_bits_address = coherent_jbar_out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsCOI_filtered_0_ready = coherent_jbar_out_0_c_ready; // @[Xbar.scala:216:19, :352:24] wire coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonOut_c_valid = coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_opcode = coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_param = coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_size = coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_source = coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_address = coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_data = coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_corrupt = coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_d_ready = coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19] wire coherent_jbar__portsDIO_filtered_0_valid_T_1 = coherent_jbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign coherent_jbar_portsDIO_filtered_0_bits_opcode = coherent_jbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_param = coherent_jbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_size = coherent_jbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] coherent_jbar__requestDOI_uncommonBits_T = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_portsDIO_filtered_0_bits_source = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_sink = coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_denied = coherent_jbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_data = coherent_jbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_corrupt = coherent_jbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonOut_e_valid = coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19] assign coherent_jbar__anonOut_e_bits_sink_T = coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19] assign coherent_jbar_out_0_d_bits_sink = coherent_jbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign coherent_jbar_anonOut_e_bits_sink = coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] coherent_jbar__requestAIO_T_1 = {1'h0, coherent_jbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] coherent_jbar__requestCIO_T_1 = {1'h0, coherent_jbar__requestCIO_T}; // @[Parameters.scala:137:{31,41}] wire [6:0] coherent_jbar_requestDOI_uncommonBits = coherent_jbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] coherent_jbar_requestEIO_uncommonBits = coherent_jbar__requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] coherent_jbar__beatsAI_decode_T = 13'h3F << coherent_jbar_in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] coherent_jbar__beatsAI_decode_T_1 = coherent_jbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] coherent_jbar__beatsAI_decode_T_2 = ~coherent_jbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] coherent_jbar_beatsAI_decode = coherent_jbar__beatsAI_decode_T_2[5:4]; // @[package.scala:243:46] wire coherent_jbar__beatsAI_opdata_T = coherent_jbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire coherent_jbar_beatsAI_opdata = ~coherent_jbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [1:0] coherent_jbar_beatsAI_0 = coherent_jbar_beatsAI_opdata ? coherent_jbar_beatsAI_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] coherent_jbar__beatsCI_decode_T = 13'h3F << coherent_jbar_in_0_c_bits_size; // @[package.scala:243:71] wire [5:0] coherent_jbar__beatsCI_decode_T_1 = coherent_jbar__beatsCI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] coherent_jbar__beatsCI_decode_T_2 = ~coherent_jbar__beatsCI_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] coherent_jbar_beatsCI_decode = coherent_jbar__beatsCI_decode_T_2[5:4]; // @[package.scala:243:46] wire coherent_jbar_beatsCI_opdata = coherent_jbar_in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [1:0] coherent_jbar_beatsCI_0 = coherent_jbar_beatsCI_opdata ? coherent_jbar_beatsCI_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [12:0] coherent_jbar__beatsDO_decode_T = 13'h3F << coherent_jbar_out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] coherent_jbar__beatsDO_decode_T_1 = coherent_jbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] coherent_jbar__beatsDO_decode_T_2 = ~coherent_jbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] coherent_jbar_beatsDO_decode = coherent_jbar__beatsDO_decode_T_2[5:4]; // @[package.scala:243:46] wire coherent_jbar_beatsDO_opdata = coherent_jbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [1:0] coherent_jbar_beatsDO_0 = coherent_jbar_beatsDO_opdata ? coherent_jbar_beatsDO_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign coherent_jbar_in_0_a_ready = coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_out_0_a_valid = coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_opcode = coherent_jbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_param = coherent_jbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_size = coherent_jbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_source = coherent_jbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_address = coherent_jbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_mask = coherent_jbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_data = coherent_jbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_corrupt = coherent_jbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsAOI_filtered_0_valid = coherent_jbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_out_0_b_ready = coherent_jbar_portsBIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_in_0_b_valid = coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_b_bits_param = coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_b_bits_address = coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_portsBIO_filtered_0_valid = coherent_jbar__portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_in_0_c_ready = coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_out_0_c_valid = coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_opcode = coherent_jbar_portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_param = coherent_jbar_portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_size = coherent_jbar_portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_source = coherent_jbar_portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_address = coherent_jbar_portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_data = coherent_jbar_portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_corrupt = coherent_jbar_portsCOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsCOI_filtered_0_valid = coherent_jbar__portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_out_0_d_ready = coherent_jbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_in_0_d_valid = coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_opcode = coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_param = coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_size = coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_source = coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_sink = coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_denied = coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_data = coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_corrupt = coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_portsDIO_filtered_0_valid = coherent_jbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_out_0_e_valid = coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_e_bits_sink = coherent_jbar_portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsEOI_filtered_0_valid = coherent_jbar__portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingOut_a_ready = coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_bus_xingOut_d_valid = coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_param = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_size = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17] wire [4:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_source = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_data = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [4:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [4:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_anonIn_a_ready = coupler_to_bus_named_mbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_anonIn_d_valid = coupler_to_bus_named_mbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_param = coupler_to_bus_named_mbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_size = coupler_to_bus_named_mbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_source = coupler_to_bus_named_mbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_data = coupler_to_bus_named_mbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_anonOut_a_valid = coupler_to_bus_named_mbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_param = coupler_to_bus_named_mbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_size = coupler_to_bus_named_mbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_source = coupler_to_bus_named_mbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_address = coupler_to_bus_named_mbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_data = coupler_to_bus_named_mbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_d_ready = coupler_to_bus_named_mbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_bus_xingIn_a_ready = coupler_to_bus_named_mbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_valid = coupler_to_bus_named_mbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_param = coupler_to_bus_named_mbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_size = coupler_to_bus_named_mbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_source = coupler_to_bus_named_mbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_data = coupler_to_bus_named_mbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_bus_xingOut_a_valid = coupler_to_bus_named_mbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_param = coupler_to_bus_named_mbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_size = coupler_to_bus_named_mbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_source = coupler_to_bus_named_mbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_address = coupler_to_bus_named_mbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_data = coupler_to_bus_named_mbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_d_ready = coupler_to_bus_named_mbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] InclusiveCache l2 ( // @[Configs.scala:93:24] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_ctrls_ctrl_in_a_ready (auto_l2_ctrls_ctrl_in_a_ready_0), .auto_ctrls_ctrl_in_a_valid (auto_l2_ctrls_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_opcode (auto_l2_ctrls_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_param (auto_l2_ctrls_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_size (auto_l2_ctrls_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_source (auto_l2_ctrls_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_address (auto_l2_ctrls_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_mask (auto_l2_ctrls_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_data (auto_l2_ctrls_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_corrupt (auto_l2_ctrls_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_d_ready (auto_l2_ctrls_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_d_valid (auto_l2_ctrls_ctrl_in_d_valid_0), .auto_ctrls_ctrl_in_d_bits_opcode (auto_l2_ctrls_ctrl_in_d_bits_opcode_0), .auto_ctrls_ctrl_in_d_bits_size (auto_l2_ctrls_ctrl_in_d_bits_size_0), .auto_ctrls_ctrl_in_d_bits_source (auto_l2_ctrls_ctrl_in_d_bits_source_0), .auto_ctrls_ctrl_in_d_bits_data (auto_l2_ctrls_ctrl_in_d_bits_data_0), .auto_in_a_ready (_l2_auto_in_a_ready), .auto_in_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid), // @[Parameters.scala:56:69] .auto_in_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode), // @[Parameters.scala:56:69] .auto_in_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param), // @[Parameters.scala:56:69] .auto_in_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size), // @[Parameters.scala:56:69] .auto_in_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source), // @[Parameters.scala:56:69] .auto_in_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address), // @[Parameters.scala:56:69] .auto_in_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask), // @[Parameters.scala:56:69] .auto_in_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data), // @[Parameters.scala:56:69] .auto_in_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready), // @[Parameters.scala:56:69] .auto_in_b_valid (_l2_auto_in_b_valid), .auto_in_b_bits_param (_l2_auto_in_b_bits_param), .auto_in_b_bits_address (_l2_auto_in_b_bits_address), .auto_in_c_ready (_l2_auto_in_c_ready), .auto_in_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid), // @[Parameters.scala:56:69] .auto_in_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode), // @[Parameters.scala:56:69] .auto_in_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param), // @[Parameters.scala:56:69] .auto_in_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size), // @[Parameters.scala:56:69] .auto_in_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source), // @[Parameters.scala:56:69] .auto_in_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address), // @[Parameters.scala:56:69] .auto_in_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data), // @[Parameters.scala:56:69] .auto_in_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready), // @[Parameters.scala:56:69] .auto_in_d_valid (_l2_auto_in_d_valid), .auto_in_d_bits_opcode (_l2_auto_in_d_bits_opcode), .auto_in_d_bits_param (_l2_auto_in_d_bits_param), .auto_in_d_bits_size (_l2_auto_in_d_bits_size), .auto_in_d_bits_source (_l2_auto_in_d_bits_source), .auto_in_d_bits_sink (_l2_auto_in_d_bits_sink), .auto_in_d_bits_denied (_l2_auto_in_d_bits_denied), .auto_in_d_bits_data (_l2_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_l2_auto_in_d_bits_corrupt), .auto_in_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid), // @[Parameters.scala:56:69] .auto_in_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink), // @[Parameters.scala:56:69] .auto_out_a_ready (InclusiveCache_outer_TLBuffer_auto_in_a_ready), // @[Buffer.scala:40:9] .auto_out_a_valid (InclusiveCache_outer_TLBuffer_auto_in_a_valid), .auto_out_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode), .auto_out_a_bits_param (InclusiveCache_outer_TLBuffer_auto_in_a_bits_param), .auto_out_a_bits_size (InclusiveCache_outer_TLBuffer_auto_in_a_bits_size), .auto_out_a_bits_source (InclusiveCache_outer_TLBuffer_auto_in_a_bits_source), .auto_out_a_bits_address (InclusiveCache_outer_TLBuffer_auto_in_a_bits_address), .auto_out_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask), .auto_out_a_bits_data (InclusiveCache_outer_TLBuffer_auto_in_a_bits_data), .auto_out_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt), .auto_out_c_ready (InclusiveCache_outer_TLBuffer_auto_in_c_ready), // @[Buffer.scala:40:9] .auto_out_c_valid (InclusiveCache_outer_TLBuffer_auto_in_c_valid), .auto_out_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode), .auto_out_c_bits_param (InclusiveCache_outer_TLBuffer_auto_in_c_bits_param), .auto_out_c_bits_size (InclusiveCache_outer_TLBuffer_auto_in_c_bits_size), .auto_out_c_bits_source (InclusiveCache_outer_TLBuffer_auto_in_c_bits_source), .auto_out_c_bits_address (InclusiveCache_outer_TLBuffer_auto_in_c_bits_address), .auto_out_c_bits_data (InclusiveCache_outer_TLBuffer_auto_in_c_bits_data), .auto_out_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt), .auto_out_d_ready (InclusiveCache_outer_TLBuffer_auto_in_d_ready), .auto_out_d_valid (InclusiveCache_outer_TLBuffer_auto_in_d_valid), // @[Buffer.scala:40:9] .auto_out_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode), // @[Buffer.scala:40:9] .auto_out_d_bits_param (InclusiveCache_outer_TLBuffer_auto_in_d_bits_param), // @[Buffer.scala:40:9] .auto_out_d_bits_size (InclusiveCache_outer_TLBuffer_auto_in_d_bits_size), // @[Buffer.scala:40:9] .auto_out_d_bits_source (InclusiveCache_outer_TLBuffer_auto_in_d_bits_source), // @[Buffer.scala:40:9] .auto_out_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink), // @[Buffer.scala:40:9] .auto_out_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied), // @[Buffer.scala:40:9] .auto_out_d_bits_data (InclusiveCache_outer_TLBuffer_auto_in_d_bits_data), // @[Buffer.scala:40:9] .auto_out_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt), // @[Buffer.scala:40:9] .auto_out_e_valid (InclusiveCache_outer_TLBuffer_auto_in_e_valid), .auto_out_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink) ); // @[Configs.scala:93:24] TLBuffer_a32d128s7k4z3c InclusiveCache_inner_TLBuffer ( // @[Parameters.scala:56:69] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (filter_auto_anon_out_a_ready), .auto_in_a_valid (filter_auto_anon_out_a_valid), // @[Filter.scala:60:9] .auto_in_a_bits_opcode (filter_auto_anon_out_a_bits_opcode), // @[Filter.scala:60:9] .auto_in_a_bits_param (filter_auto_anon_out_a_bits_param), // @[Filter.scala:60:9] .auto_in_a_bits_size (filter_auto_anon_out_a_bits_size), // @[Filter.scala:60:9] .auto_in_a_bits_source (filter_auto_anon_out_a_bits_source), // @[Filter.scala:60:9] .auto_in_a_bits_address (filter_auto_anon_out_a_bits_address), // @[Filter.scala:60:9] .auto_in_a_bits_mask (filter_auto_anon_out_a_bits_mask), // @[Filter.scala:60:9] .auto_in_a_bits_data (filter_auto_anon_out_a_bits_data), // @[Filter.scala:60:9] .auto_in_a_bits_corrupt (filter_auto_anon_out_a_bits_corrupt), // @[Filter.scala:60:9] .auto_in_b_ready (filter_auto_anon_out_b_ready), // @[Filter.scala:60:9] .auto_in_b_valid (filter_auto_anon_out_b_valid), .auto_in_b_bits_param (filter_auto_anon_out_b_bits_param), .auto_in_b_bits_address (filter_auto_anon_out_b_bits_address), .auto_in_c_ready (filter_auto_anon_out_c_ready), .auto_in_c_valid (filter_auto_anon_out_c_valid), // @[Filter.scala:60:9] .auto_in_c_bits_opcode (filter_auto_anon_out_c_bits_opcode), // @[Filter.scala:60:9] .auto_in_c_bits_param (filter_auto_anon_out_c_bits_param), // @[Filter.scala:60:9] .auto_in_c_bits_size (filter_auto_anon_out_c_bits_size), // @[Filter.scala:60:9] .auto_in_c_bits_source (filter_auto_anon_out_c_bits_source), // @[Filter.scala:60:9] .auto_in_c_bits_address (filter_auto_anon_out_c_bits_address), // @[Filter.scala:60:9] .auto_in_c_bits_data (filter_auto_anon_out_c_bits_data), // @[Filter.scala:60:9] .auto_in_c_bits_corrupt (filter_auto_anon_out_c_bits_corrupt), // @[Filter.scala:60:9] .auto_in_d_ready (filter_auto_anon_out_d_ready), // @[Filter.scala:60:9] .auto_in_d_valid (filter_auto_anon_out_d_valid), .auto_in_d_bits_opcode (filter_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (filter_auto_anon_out_d_bits_param), .auto_in_d_bits_size (filter_auto_anon_out_d_bits_size), .auto_in_d_bits_source (filter_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (filter_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (filter_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (filter_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (filter_auto_anon_out_d_bits_corrupt), .auto_in_e_valid (filter_auto_anon_out_e_valid), // @[Filter.scala:60:9] .auto_in_e_bits_sink (filter_auto_anon_out_e_bits_sink), // @[Filter.scala:60:9] .auto_out_a_ready (_l2_auto_in_a_ready), // @[Configs.scala:93:24] .auto_out_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid), .auto_out_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode), .auto_out_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param), .auto_out_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size), .auto_out_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source), .auto_out_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address), .auto_out_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask), .auto_out_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt), .auto_out_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready), .auto_out_b_valid (_l2_auto_in_b_valid), // @[Configs.scala:93:24] .auto_out_b_bits_param (_l2_auto_in_b_bits_param), // @[Configs.scala:93:24] .auto_out_b_bits_address (_l2_auto_in_b_bits_address), // @[Configs.scala:93:24] .auto_out_c_ready (_l2_auto_in_c_ready), // @[Configs.scala:93:24] .auto_out_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid), .auto_out_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode), .auto_out_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param), .auto_out_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size), .auto_out_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source), .auto_out_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address), .auto_out_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data), .auto_out_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt), .auto_out_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready), .auto_out_d_valid (_l2_auto_in_d_valid), // @[Configs.scala:93:24] .auto_out_d_bits_opcode (_l2_auto_in_d_bits_opcode), // @[Configs.scala:93:24] .auto_out_d_bits_param (_l2_auto_in_d_bits_param), // @[Configs.scala:93:24] .auto_out_d_bits_size (_l2_auto_in_d_bits_size), // @[Configs.scala:93:24] .auto_out_d_bits_source (_l2_auto_in_d_bits_source), // @[Configs.scala:93:24] .auto_out_d_bits_sink (_l2_auto_in_d_bits_sink), // @[Configs.scala:93:24] .auto_out_d_bits_denied (_l2_auto_in_d_bits_denied), // @[Configs.scala:93:24] .auto_out_d_bits_data (_l2_auto_in_d_bits_data), // @[Configs.scala:93:24] .auto_out_d_bits_corrupt (_l2_auto_in_d_bits_corrupt), // @[Configs.scala:93:24] .auto_out_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid), .auto_out_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink) ); // @[Parameters.scala:56:69] TLCacheCork cork ( // @[Configs.scala:120:26] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (InclusiveCache_outer_TLBuffer_auto_out_a_ready), .auto_in_a_valid (InclusiveCache_outer_TLBuffer_auto_out_a_valid), // @[Buffer.scala:40:9] .auto_in_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode), // @[Buffer.scala:40:9] .auto_in_a_bits_param (InclusiveCache_outer_TLBuffer_auto_out_a_bits_param), // @[Buffer.scala:40:9] .auto_in_a_bits_size (InclusiveCache_outer_TLBuffer_auto_out_a_bits_size), // @[Buffer.scala:40:9] .auto_in_a_bits_source (InclusiveCache_outer_TLBuffer_auto_out_a_bits_source), // @[Buffer.scala:40:9] .auto_in_a_bits_address (InclusiveCache_outer_TLBuffer_auto_out_a_bits_address), // @[Buffer.scala:40:9] .auto_in_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask), // @[Buffer.scala:40:9] .auto_in_a_bits_data (InclusiveCache_outer_TLBuffer_auto_out_a_bits_data), // @[Buffer.scala:40:9] .auto_in_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9] .auto_in_c_ready (InclusiveCache_outer_TLBuffer_auto_out_c_ready), .auto_in_c_valid (InclusiveCache_outer_TLBuffer_auto_out_c_valid), // @[Buffer.scala:40:9] .auto_in_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode), // @[Buffer.scala:40:9] .auto_in_c_bits_param (InclusiveCache_outer_TLBuffer_auto_out_c_bits_param), // @[Buffer.scala:40:9] .auto_in_c_bits_size (InclusiveCache_outer_TLBuffer_auto_out_c_bits_size), // @[Buffer.scala:40:9] .auto_in_c_bits_source (InclusiveCache_outer_TLBuffer_auto_out_c_bits_source), // @[Buffer.scala:40:9] .auto_in_c_bits_address (InclusiveCache_outer_TLBuffer_auto_out_c_bits_address), // @[Buffer.scala:40:9] .auto_in_c_bits_data (InclusiveCache_outer_TLBuffer_auto_out_c_bits_data), // @[Buffer.scala:40:9] .auto_in_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt), // @[Buffer.scala:40:9] .auto_in_d_ready (InclusiveCache_outer_TLBuffer_auto_out_d_ready), // @[Buffer.scala:40:9] .auto_in_d_valid (InclusiveCache_outer_TLBuffer_auto_out_d_valid), .auto_in_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode), .auto_in_d_bits_param (InclusiveCache_outer_TLBuffer_auto_out_d_bits_param), .auto_in_d_bits_size (InclusiveCache_outer_TLBuffer_auto_out_d_bits_size), .auto_in_d_bits_source (InclusiveCache_outer_TLBuffer_auto_out_d_bits_source), .auto_in_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink), .auto_in_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied), .auto_in_d_bits_data (InclusiveCache_outer_TLBuffer_auto_out_d_bits_data), .auto_in_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt), .auto_in_e_valid (InclusiveCache_outer_TLBuffer_auto_out_e_valid), // @[Buffer.scala:40:9] .auto_in_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink), // @[Buffer.scala:40:9] .auto_out_a_ready (_binder_auto_in_a_ready), // @[BankBinder.scala:71:28] .auto_out_a_valid (_cork_auto_out_a_valid), .auto_out_a_bits_opcode (_cork_auto_out_a_bits_opcode), .auto_out_a_bits_param (_cork_auto_out_a_bits_param), .auto_out_a_bits_size (_cork_auto_out_a_bits_size), .auto_out_a_bits_source (_cork_auto_out_a_bits_source), .auto_out_a_bits_address (_cork_auto_out_a_bits_address), .auto_out_a_bits_mask (_cork_auto_out_a_bits_mask), .auto_out_a_bits_data (_cork_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_cork_auto_out_a_bits_corrupt), .auto_out_d_ready (_cork_auto_out_d_ready), .auto_out_d_valid (_binder_auto_in_d_valid), // @[BankBinder.scala:71:28] .auto_out_d_bits_opcode (_binder_auto_in_d_bits_opcode), // @[BankBinder.scala:71:28] .auto_out_d_bits_param (_binder_auto_in_d_bits_param), // @[BankBinder.scala:71:28] .auto_out_d_bits_size (_binder_auto_in_d_bits_size), // @[BankBinder.scala:71:28] .auto_out_d_bits_source (_binder_auto_in_d_bits_source), // @[BankBinder.scala:71:28] .auto_out_d_bits_sink (_binder_auto_in_d_bits_sink), // @[BankBinder.scala:71:28] .auto_out_d_bits_denied (_binder_auto_in_d_bits_denied), // @[BankBinder.scala:71:28] .auto_out_d_bits_data (_binder_auto_in_d_bits_data), // @[BankBinder.scala:71:28] .auto_out_d_bits_corrupt (_binder_auto_in_d_bits_corrupt) // @[BankBinder.scala:71:28] ); // @[Configs.scala:120:26] BankBinder binder ( // @[BankBinder.scala:71:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_binder_auto_in_a_ready), .auto_in_a_valid (_cork_auto_out_a_valid), // @[Configs.scala:120:26] .auto_in_a_bits_opcode (_cork_auto_out_a_bits_opcode), // @[Configs.scala:120:26] .auto_in_a_bits_param (_cork_auto_out_a_bits_param), // @[Configs.scala:120:26] .auto_in_a_bits_size (_cork_auto_out_a_bits_size), // @[Configs.scala:120:26] .auto_in_a_bits_source (_cork_auto_out_a_bits_source), // @[Configs.scala:120:26] .auto_in_a_bits_address (_cork_auto_out_a_bits_address), // @[Configs.scala:120:26] .auto_in_a_bits_mask (_cork_auto_out_a_bits_mask), // @[Configs.scala:120:26] .auto_in_a_bits_data (_cork_auto_out_a_bits_data), // @[Configs.scala:120:26] .auto_in_a_bits_corrupt (_cork_auto_out_a_bits_corrupt), // @[Configs.scala:120:26] .auto_in_d_ready (_cork_auto_out_d_ready), // @[Configs.scala:120:26] .auto_in_d_valid (_binder_auto_in_d_valid), .auto_in_d_bits_opcode (_binder_auto_in_d_bits_opcode), .auto_in_d_bits_param (_binder_auto_in_d_bits_param), .auto_in_d_bits_size (_binder_auto_in_d_bits_size), .auto_in_d_bits_source (_binder_auto_in_d_bits_source), .auto_in_d_bits_sink (_binder_auto_in_d_bits_sink), .auto_in_d_bits_denied (_binder_auto_in_d_bits_denied), .auto_in_d_bits_data (_binder_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_binder_auto_in_d_bits_corrupt), .auto_out_a_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7] .auto_out_a_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid), .auto_out_a_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode), .auto_out_a_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param), .auto_out_a_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size), .auto_out_a_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source), .auto_out_a_bits_address (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address), .auto_out_a_bits_mask (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask), .auto_out_a_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data), .auto_out_a_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt), .auto_out_d_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready), .auto_out_d_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_sink (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_denied (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyModuleImp.scala:138:7] ); // @[BankBinder.scala:71:28] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_a_ready = auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_b_valid = auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_b_bits_param = auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_b_bits_address = auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_c_ready = auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_valid = auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_opcode = auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_param = auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_size = auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_source = auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_sink = auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_denied = auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_data = auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_corrupt = auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_a_ready = auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_valid = auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_opcode = auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_size = auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_source = auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_data = auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module MacUnit_120( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_54( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_607; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module TLBuffer_a32d64s1k4z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_72 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s1k4z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s1k4z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] endmodule

Generate the Verilog code corresponding to the following Chisel files. File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined || nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined || nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBits*rowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /** Bundle definitions for HellaCache interfaces */ trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /** Base classes for Diplomatic TL2 HellaCaches */ abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated */ case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /** Mix-ins for constructing tiles that have a HellaCache */ trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /** Metadata array used for all HellaCaches */ class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst || io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst }

module tag_array_0( // @[HellaCache.scala:339:30] input [3:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [47:0] RW0_wdata, output [47:0] RW0_rdata, input [1:0] RW0_wmask ); tag_array_ext tag_array_ext ( // @[HellaCache.scala:339:30] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[HellaCache.scala:339:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_175( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_151( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }

module MSHR_4( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [5:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] wire [5:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [1:0] meta_clients; // @[MSHR.scala:100:17] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [1:0] probes_done; // @[MSHR.scala:150:24] reg [1:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [1:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _req_clientBit_T = request_source[5:2]; // @[Parameters.scala:54:10] wire [3:0] _req_clientBit_T_6 = request_source[5:2]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_5 = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T_7 = _req_clientBit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_9 = _req_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_10 = req_clientBit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_11 = _req_clientBit_T_9 & _req_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit = {_req_clientBit_T_11, _req_clientBit_T_5}; // @[Parameters.scala:56:48] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [1:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [1:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _probe_bit_T = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire [3:0] _probe_bit_T_6 = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_5 = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T_7 = _probe_bit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_9 = _probe_bit_T_7; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_10 = probe_bit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_11 = _probe_bit_T_9 & _probe_bit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit = {_probe_bit_T_11, _probe_bit_T_5}; // @[Parameters.scala:56:48] wire [1:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10] wire [1:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [1:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [1:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [1:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire [5:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [1:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _new_clientBit_T = new_request_source[5:2]; // @[Parameters.scala:54:10] wire [3:0] _new_clientBit_T_6 = new_request_source[5:2]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_5 = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T_7 = _new_clientBit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_9 = _new_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_10 = new_clientBit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_11 = _new_clientBit_T_9 & _new_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit = {_new_clientBit_T_11, _new_clientBit_T_5}; // @[Parameters.scala:56:48] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }

module dataMems_101( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module PE_378( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_122 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module IntSyncSyncCrossingSink_n1x5( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] input auto_in_sync_1, // @[LazyModuleImp.scala:107:25] input auto_in_sync_2, // @[LazyModuleImp.scala:107:25] input auto_in_sync_3, // @[LazyModuleImp.scala:107:25] input auto_in_sync_4, // @[LazyModuleImp.scala:107:25] output auto_out_0, // @[LazyModuleImp.scala:107:25] output auto_out_1, // @[LazyModuleImp.scala:107:25] output auto_out_2, // @[LazyModuleImp.scala:107:25] output auto_out_3, // @[LazyModuleImp.scala:107:25] output auto_out_4 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire auto_in_sync_1_0 = auto_in_sync_1; // @[Crossing.scala:96:9] wire auto_in_sync_2_0 = auto_in_sync_2; // @[Crossing.scala:96:9] wire auto_in_sync_3_0 = auto_in_sync_3; // @[Crossing.scala:96:9] wire auto_in_sync_4_0 = auto_in_sync_4; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeIn_sync_1 = auto_in_sync_1_0; // @[Crossing.scala:96:9] wire nodeIn_sync_2 = auto_in_sync_2_0; // @[Crossing.scala:96:9] wire nodeIn_sync_3 = auto_in_sync_3_0; // @[Crossing.scala:96:9] wire nodeIn_sync_4 = auto_in_sync_4_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire nodeOut_1; // @[MixedNode.scala:542:17] wire nodeOut_2; // @[MixedNode.scala:542:17] wire nodeOut_3; // @[MixedNode.scala:542:17] wire nodeOut_4; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] wire auto_out_1_0; // @[Crossing.scala:96:9] wire auto_out_2_0; // @[Crossing.scala:96:9] wire auto_out_3_0; // @[Crossing.scala:96:9] wire auto_out_4_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_1 = nodeIn_sync_1; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_2 = nodeIn_sync_2; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_3 = nodeIn_sync_3; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_4 = nodeIn_sync_4; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_1_0 = nodeOut_1; // @[Crossing.scala:96:9] assign auto_out_2_0 = nodeOut_2; // @[Crossing.scala:96:9] assign auto_out_3_0 = nodeOut_3; // @[Crossing.scala:96:9] assign auto_out_4_0 = nodeOut_4; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] assign auto_out_1 = auto_out_1_0; // @[Crossing.scala:96:9] assign auto_out_2 = auto_out_2_0; // @[Crossing.scala:96:9] assign auto_out_3 = auto_out_3_0; // @[Crossing.scala:96:9] assign auto_out_4 = auto_out_4_0; // @[Crossing.scala:96:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }

module TLXbar_mbus_i1_o2_a32d64s4k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _portsAOI_in_0_a_ready_T_2 = auto_anon_in_a_bits_address[31] & auto_anon_out_0_a_ready | ~(auto_anon_in_a_bits_address[31]) & auto_anon_out_1_a_ready; // @[Mux.scala:30:73] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire [1:0] readys_valid = {auto_anon_out_1_d_valid, auto_anon_out_0_d_valid}; // @[Arbiter.scala:68:51] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [1:0] readys_readys = ~({readys_mask[1], _readys_filter_T_1[1] | readys_mask[0]} & ({_readys_filter_T_1[0], auto_anon_out_1_d_valid} | _readys_filter_T_1)); // @[package.scala:262:43] wire winner_0 = readys_readys[0] & auto_anon_out_0_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_1 = readys_readys[1] & auto_anon_out_1_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire _in_0_d_valid_T = auto_anon_out_0_d_valid | auto_anon_out_1_d_valid; // @[Arbiter.scala:79:31]

Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }

module RecFNToRecFN_155( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File composer.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} class ComposedBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val (components, resp) = getBPDComponents(io.resp_in(0), p) io.resp := resp var metas = 0.U(1.W) var meta_sz = 0 for (c <- components) { c.io.f0_valid := io.f0_valid c.io.f0_pc := io.f0_pc c.io.f0_mask := io.f0_mask c.io.f1_ghist := io.f1_ghist c.io.f1_lhist := io.f1_lhist c.io.f3_fire := io.f3_fire if (c.metaSz > 0) { metas = (metas << c.metaSz) | c.io.f3_meta(c.metaSz-1,0) } meta_sz = meta_sz + c.metaSz } require(meta_sz < bpdMaxMetaLength) io.f3_meta := metas var update_meta = io.update.bits.meta for (c <- components.reverse) { c.io.update := io.update c.io.update.bits.meta := update_meta update_meta = update_meta >> c.metaSz } val mems = components.map(_.mems).flatten } File predictor.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} // A branch prediction for a single instruction class BranchPrediction(implicit p: Parameters) extends BoomBundle()(p) { // If this is a branch, do we take it? val taken = Bool() // Is this a branch? val is_br = Bool() // Is this a JAL? val is_jal = Bool() // What is the target of his branch/jump? Do we know the target? val predicted_pc = Valid(UInt(vaddrBitsExtended.W)) } // A branch prediction for a entire fetch-width worth of instructions // This is typically merged from individual predictions from the banked // predictor class BranchPredictionBundle(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val pc = UInt(vaddrBitsExtended.W) val preds = Vec(fetchWidth, new BranchPrediction) val meta = Output(Vec(nBanks, UInt(bpdMaxMetaLength.W))) val lhist = Output(Vec(nBanks, UInt(localHistoryLength.W))) } // A branch update for a fetch-width worth of instructions class BranchPredictionUpdate(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { // Indicates that this update is due to a speculated misprediction // Local predictors typically update themselves with speculative info // Global predictors only care about non-speculative updates val is_mispredict_update = Bool() val is_repair_update = Bool() val btb_mispredicts = UInt(fetchWidth.W) def is_btb_mispredict_update = btb_mispredicts =/= 0.U def is_commit_update = !(is_mispredict_update || is_repair_update || is_btb_mispredict_update) val pc = UInt(vaddrBitsExtended.W) // Mask of instructions which are branches. // If these are not cfi_idx, then they were predicted not taken val br_mask = UInt(fetchWidth.W) // Which CFI was taken/mispredicted (if any) val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W)) // Was the cfi taken? val cfi_taken = Bool() // Was the cfi mispredicted from the original prediction? val cfi_mispredicted = Bool() // Was the cfi a br? val cfi_is_br = Bool() // Was the cfi a jal/jalr? val cfi_is_jal = Bool() // Was the cfi a jalr val cfi_is_jalr = Bool() //val cfi_is_ret = Bool() val ghist = new GlobalHistory val lhist = Vec(nBanks, UInt(localHistoryLength.W)) // What did this CFI jump to? val target = UInt(vaddrBitsExtended.W) val meta = Vec(nBanks, UInt(bpdMaxMetaLength.W)) } // A branch update to a single bank class BranchPredictionBankUpdate(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val is_mispredict_update = Bool() val is_repair_update = Bool() val btb_mispredicts = UInt(bankWidth.W) def is_btb_mispredict_update = btb_mispredicts =/= 0.U def is_commit_update = !(is_mispredict_update || is_repair_update || is_btb_mispredict_update) val pc = UInt(vaddrBitsExtended.W) val br_mask = UInt(bankWidth.W) val cfi_idx = Valid(UInt(log2Ceil(bankWidth).W)) val cfi_taken = Bool() val cfi_mispredicted = Bool() val cfi_is_br = Bool() val cfi_is_jal = Bool() val cfi_is_jalr = Bool() val ghist = UInt(globalHistoryLength.W) val lhist = UInt(localHistoryLength.W) val target = UInt(vaddrBitsExtended.W) val meta = UInt(bpdMaxMetaLength.W) } class BranchPredictionRequest(implicit p: Parameters) extends BoomBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val ghist = new GlobalHistory } class BranchPredictionBankResponse(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val f1 = Vec(bankWidth, new BranchPrediction) val f2 = Vec(bankWidth, new BranchPrediction) val f3 = Vec(bankWidth, new BranchPrediction) } abstract class BranchPredictorBank(implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { val metaSz = 0 def nInputs = 1 val mems: Seq[Tuple3[String, Int, Int]] val io = IO(new Bundle { val f0_valid = Input(Bool()) val f0_pc = Input(UInt(vaddrBitsExtended.W)) val f0_mask = Input(UInt(bankWidth.W)) // Local history not available until end of f1 val f1_ghist = Input(UInt(globalHistoryLength.W)) val f1_lhist = Input(UInt(localHistoryLength.W)) val resp_in = Input(Vec(nInputs, new BranchPredictionBankResponse)) val resp = Output(new BranchPredictionBankResponse) // Store the meta as a UInt, use width inference to figure out the shape val f3_meta = Output(UInt(bpdMaxMetaLength.W)) val f3_fire = Input(Bool()) val update = Input(Valid(new BranchPredictionBankUpdate)) }) io.resp := io.resp_in(0) io.f3_meta := 0.U val s0_idx = fetchIdx(io.f0_pc) val s1_idx = RegNext(s0_idx) val s2_idx = RegNext(s1_idx) val s3_idx = RegNext(s2_idx) val s0_valid = io.f0_valid val s1_valid = RegNext(s0_valid) val s2_valid = RegNext(s1_valid) val s3_valid = RegNext(s2_valid) val s0_mask = io.f0_mask val s1_mask = RegNext(s0_mask) val s2_mask = RegNext(s1_mask) val s3_mask = RegNext(s2_mask) val s0_pc = io.f0_pc val s1_pc = RegNext(s0_pc) val s0_update = io.update val s0_update_idx = fetchIdx(io.update.bits.pc) val s0_update_valid = io.update.valid val s1_update = RegNext(s0_update) val s1_update_idx = RegNext(s0_update_idx) val s1_update_valid = RegNext(s0_update_valid) } class BranchPredictor(implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { val io = IO(new Bundle { // Requests and responses val f0_req = Input(Valid(new BranchPredictionRequest)) val resp = Output(new Bundle { val f1 = new BranchPredictionBundle val f2 = new BranchPredictionBundle val f3 = new BranchPredictionBundle }) val f3_fire = Input(Bool()) // Update val update = Input(Valid(new BranchPredictionUpdate)) }) var total_memsize = 0 val bpdStr = new StringBuilder bpdStr.append(BoomCoreStringPrefix("==Branch Predictor Memory Sizes==\n")) val banked_predictors = (0 until nBanks) map ( b => { val m = Module(if (useBPD) new ComposedBranchPredictorBank else new NullBranchPredictorBank) for ((n, d, w) <- m.mems) { bpdStr.append(BoomCoreStringPrefix(f"bank$b $n: $d x $w = ${d * w / 8}")) total_memsize = total_memsize + d * w / 8 } m }) bpdStr.append(BoomCoreStringPrefix(f"Total bpd size: ${total_memsize / 1024} KB\n")) override def toString: String = bpdStr.toString val banked_lhist_providers = Seq.fill(nBanks) { Module(if (localHistoryNSets > 0) new LocalBranchPredictorBank else new NullLocalBranchPredictorBank) } if (nBanks == 1) { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc) banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) } else { require(nBanks == 2) banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) banked_predictors(1).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist banked_predictors(1).io.f1_lhist := banked_lhist_providers(1).io.f1_lhist when (bank(io.f0_req.bits.pc) === 0.U) { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_lhist_providers(1).io.f0_valid := io.f0_req.valid banked_lhist_providers(1).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc) banked_predictors(1).io.f0_valid := io.f0_req.valid banked_predictors(1).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(1).io.f0_mask := ~(0.U(bankWidth.W)) } .otherwise { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc) banked_lhist_providers(0).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_lhist_providers(1).io.f0_valid := io.f0_req.valid banked_lhist_providers(1).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc) banked_predictors(0).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := ~(0.U(bankWidth.W)) banked_predictors(1).io.f0_valid := io.f0_req.valid banked_predictors(1).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(1).io.f0_mask := fetchMask(io.f0_req.bits.pc) } when (RegNext(bank(io.f0_req.bits.pc) === 0.U)) { banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1)) } .otherwise { banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1)) banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) } } for (i <- 0 until nBanks) { banked_lhist_providers(i).io.f3_taken_br := banked_predictors(i).io.resp.f3.map ( p => p.is_br && p.predicted_pc.valid && p.taken ).reduce(_||_) } if (nBanks == 1) { io.resp.f1.preds := banked_predictors(0).io.resp.f1 io.resp.f2.preds := banked_predictors(0).io.resp.f2 io.resp.f3.preds := banked_predictors(0).io.resp.f3 io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist banked_predictors(0).io.f3_fire := io.f3_fire banked_lhist_providers(0).io.f3_fire := io.f3_fire } else { require(nBanks == 2) val b0_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(0).io.f0_valid))) val b1_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(1).io.f0_valid))) banked_predictors(0).io.f3_fire := b0_fire banked_predictors(1).io.f3_fire := b1_fire banked_lhist_providers(0).io.f3_fire := b0_fire banked_lhist_providers(1).io.f3_fire := b1_fire // The branch prediction metadata is stored un-shuffled io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta io.resp.f3.meta(1) := banked_predictors(1).io.f3_meta io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist io.resp.f3.lhist(1) := banked_lhist_providers(1).io.f3_lhist when (bank(io.resp.f1.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f1.preds(i) := banked_predictors(0).io.resp.f1(i) io.resp.f1.preds(i+bankWidth) := banked_predictors(1).io.resp.f1(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f1.preds(i) := banked_predictors(1).io.resp.f1(i) io.resp.f1.preds(i+bankWidth) := banked_predictors(0).io.resp.f1(i) } } when (bank(io.resp.f2.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f2.preds(i) := banked_predictors(0).io.resp.f2(i) io.resp.f2.preds(i+bankWidth) := banked_predictors(1).io.resp.f2(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f2.preds(i) := banked_predictors(1).io.resp.f2(i) io.resp.f2.preds(i+bankWidth) := banked_predictors(0).io.resp.f2(i) } } when (bank(io.resp.f3.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f3.preds(i) := banked_predictors(0).io.resp.f3(i) io.resp.f3.preds(i+bankWidth) := banked_predictors(1).io.resp.f3(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f3.preds(i) := banked_predictors(1).io.resp.f3(i) io.resp.f3.preds(i+bankWidth) := banked_predictors(0).io.resp.f3(i) } } } io.resp.f1.pc := RegNext(io.f0_req.bits.pc) io.resp.f2.pc := RegNext(io.resp.f1.pc) io.resp.f3.pc := RegNext(io.resp.f2.pc) // We don't care about meta from the f1 and f2 resps // Use the meta from the latest resp io.resp.f1.meta := DontCare io.resp.f2.meta := DontCare io.resp.f1.lhist := DontCare io.resp.f2.lhist := DontCare for (i <- 0 until nBanks) { banked_predictors(i).io.update.bits.is_mispredict_update := io.update.bits.is_mispredict_update banked_predictors(i).io.update.bits.is_repair_update := io.update.bits.is_repair_update banked_predictors(i).io.update.bits.meta := io.update.bits.meta(i) banked_predictors(i).io.update.bits.lhist := io.update.bits.lhist(i) banked_predictors(i).io.update.bits.cfi_idx.bits := io.update.bits.cfi_idx.bits banked_predictors(i).io.update.bits.cfi_taken := io.update.bits.cfi_taken banked_predictors(i).io.update.bits.cfi_mispredicted := io.update.bits.cfi_mispredicted banked_predictors(i).io.update.bits.cfi_is_br := io.update.bits.cfi_is_br banked_predictors(i).io.update.bits.cfi_is_jal := io.update.bits.cfi_is_jal banked_predictors(i).io.update.bits.cfi_is_jalr := io.update.bits.cfi_is_jalr banked_predictors(i).io.update.bits.target := io.update.bits.target banked_lhist_providers(i).io.update.mispredict := io.update.bits.is_mispredict_update banked_lhist_providers(i).io.update.repair := io.update.bits.is_repair_update banked_lhist_providers(i).io.update.lhist := io.update.bits.lhist(i) } if (nBanks == 1) { banked_predictors(0).io.update.valid := io.update.valid banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask =/= 0.U banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc) } else { require(nBanks == 2) // Split the single update bundle for the fetchpacket into two updates // 1 for each bank. when (bank(io.update.bits.pc) === 0.U) { val b1_update_valid = io.update.valid && (!io.update.bits.cfi_idx.valid || io.update.bits.cfi_idx.bits >= bankWidth.U) banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U banked_lhist_providers(1).io.update.valid := b1_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc) banked_lhist_providers(1).io.update.pc := nextBank(io.update.bits.pc) banked_predictors(0).io.update.valid := io.update.valid banked_predictors(1).io.update.valid := b1_update_valid banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(1).io.update.bits.pc := nextBank(io.update.bits.pc) banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(1) } .otherwise { val b0_update_valid = io.update.valid && !mayNotBeDualBanked(io.update.bits.pc) && (!io.update.bits.cfi_idx.valid || io.update.bits.cfi_idx.bits >= bankWidth.U) banked_lhist_providers(1).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U banked_lhist_providers(0).io.update.valid := b0_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U banked_lhist_providers(1).io.update.pc := bankAlign(io.update.bits.pc) banked_lhist_providers(0).io.update.pc := nextBank(io.update.bits.pc) banked_predictors(1).io.update.valid := io.update.valid banked_predictors(0).io.update.valid := b0_update_valid banked_predictors(1).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(0).io.update.bits.pc := nextBank(io.update.bits.pc) banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(1) } } when (io.update.valid) { when (io.update.bits.cfi_is_br && io.update.bits.cfi_idx.valid) { assert(io.update.bits.br_mask(io.update.bits.cfi_idx.bits)) } } } class NullBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val mems = Nil } File config-mixins.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ package boom.v3.common import chisel3._ import chisel3.util.{log2Up} import org.chipsalliance.cde.config.{Parameters, Config, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.{BootROMParams} import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing} import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ import boom.v3.ifu._ import boom.v3.exu._ import boom.v3.lsu._ // --------------------- // BOOM Config Fragments // --------------------- class WithBoomCommitLogPrintf extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( enableCommitLogPrintf = true ))) case other => other } }) class WithBoomBranchPrintf extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( enableBranchPrintf = true ))) case other => other } }) class WithNBoomPerfCounters(n: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( nPerfCounters = n ))) case other => other } }) class WithSynchronousBoomTiles extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( crossingType = SynchronousCrossing() )) case other => other } }) class WithAsynchronousBoomTiles extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( crossingType = AsynchronousCrossing() )) case other => other } }) class WithRationalBoomTiles extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( crossingType = RationalCrossing() )) case other => other } }) /** * 1-wide BOOM. */ class WithNSmallBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 4, decodeWidth = 1, numRobEntries = 32, issueParams = Seq( IssueParams(issueWidth=1, numEntries=8, iqType=IQT_MEM.litValue, dispatchWidth=1), IssueParams(issueWidth=1, numEntries=8, iqType=IQT_INT.litValue, dispatchWidth=1), IssueParams(issueWidth=1, numEntries=8, iqType=IQT_FP.litValue , dispatchWidth=1)), numIntPhysRegisters = 52, numFpPhysRegisters = 48, numLdqEntries = 8, numStqEntries = 8, maxBrCount = 8, numFetchBufferEntries = 8, ftq = FtqParameters(nEntries=16), nPerfCounters = 2, fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true)) ), dcache = Some( DCacheParams(rowBits = 64, nSets=64, nWays=4, nMSHRs=2, nTLBWays=8) ), icache = Some( ICacheParams(rowBits = 64, nSets=64, nWays=4, fetchBytes=2*4) ), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) /** * 2-wide BOOM. */ class WithNMediumBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 4, decodeWidth = 2, numRobEntries = 64, issueParams = Seq( IssueParams(issueWidth=1, numEntries=12, iqType=IQT_MEM.litValue, dispatchWidth=2), IssueParams(issueWidth=2, numEntries=20, iqType=IQT_INT.litValue, dispatchWidth=2), IssueParams(issueWidth=1, numEntries=16, iqType=IQT_FP.litValue , dispatchWidth=2)), numIntPhysRegisters = 80, numFpPhysRegisters = 64, numLdqEntries = 16, numStqEntries = 16, maxBrCount = 12, numFetchBufferEntries = 16, ftq = FtqParameters(nEntries=32), nPerfCounters = 6, fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true)) ), dcache = Some( DCacheParams(rowBits = 64, nSets=64, nWays=4, nMSHRs=2, nTLBWays=8) ), icache = Some( ICacheParams(rowBits = 64, nSets=64, nWays=4, fetchBytes=2*4) ), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) // DOC include start: LargeBoomConfig /** * 3-wide BOOM. Try to match the Cortex-A15. */ class WithNLargeBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 8, decodeWidth = 3, numRobEntries = 96, issueParams = Seq( IssueParams(issueWidth=1, numEntries=16, iqType=IQT_MEM.litValue, dispatchWidth=3), IssueParams(issueWidth=3, numEntries=32, iqType=IQT_INT.litValue, dispatchWidth=3), IssueParams(issueWidth=1, numEntries=24, iqType=IQT_FP.litValue , dispatchWidth=3)), numIntPhysRegisters = 100, numFpPhysRegisters = 96, numLdqEntries = 24, numStqEntries = 24, maxBrCount = 16, numFetchBufferEntries = 24, ftq = FtqParameters(nEntries=32), fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true)) ), dcache = Some( DCacheParams(rowBits = 128, nSets=64, nWays=8, nMSHRs=4, nTLBWays=16) ), icache = Some( ICacheParams(rowBits = 128, nSets=64, nWays=8, fetchBytes=4*4) ), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) // DOC include end: LargeBoomConfig /** * 4-wide BOOM. */ class WithNMegaBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 8, decodeWidth = 4, numRobEntries = 128, issueParams = Seq( IssueParams(issueWidth=2, numEntries=24, iqType=IQT_MEM.litValue, dispatchWidth=4), IssueParams(issueWidth=4, numEntries=40, iqType=IQT_INT.litValue, dispatchWidth=4), IssueParams(issueWidth=2, numEntries=32, iqType=IQT_FP.litValue , dispatchWidth=4)), numIntPhysRegisters = 128, numFpPhysRegisters = 128, numLdqEntries = 32, numStqEntries = 32, maxBrCount = 20, numFetchBufferEntries = 32, enablePrefetching = true, ftq = FtqParameters(nEntries=40), fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true)) ), dcache = Some( DCacheParams(rowBits = 128, nSets=64, nWays=8, nMSHRs=8, nTLBWays=32) ), icache = Some( ICacheParams(rowBits = 128, nSets=64, nWays=8, fetchBytes=4*4) ), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) /** * 5-wide BOOM. */ class WithNGigaBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 8, decodeWidth = 5, numRobEntries = 130, issueParams = Seq( IssueParams(issueWidth=2, numEntries=24, iqType=IQT_MEM.litValue, dispatchWidth=5), IssueParams(issueWidth=5, numEntries=40, iqType=IQT_INT.litValue, dispatchWidth=5), IssueParams(issueWidth=2, numEntries=32, iqType=IQT_FP.litValue , dispatchWidth=5)), numIntPhysRegisters = 128, numFpPhysRegisters = 128, numLdqEntries = 32, numStqEntries = 32, maxBrCount = 20, numFetchBufferEntries = 35, enablePrefetching = true, numDCacheBanks = 1, ftq = FtqParameters(nEntries=40), fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true)) ), dcache = Some( DCacheParams(rowBits = 128, nSets=64, nWays=8, nMSHRs=8, nTLBWays=32) ), icache = Some( ICacheParams(rowBits = 128, nSets=64, nWays=8, fetchBytes=4*4) ), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) class WithCloneBoomTiles( n: Int = 1, cloneTileId: Int = 0, location: HierarchicalLocation = InSubsystem, cloneLocation: HierarchicalLocation = InSubsystem ) extends Config((site, here, up) => { case TilesLocated(`location`) => { val prev = up(TilesLocated(location), site) val idOffset = up(NumTiles) val tileAttachParams = up(TilesLocated(cloneLocation)).find(_.tileParams.tileId == cloneTileId) .get.asInstanceOf[BoomTileAttachParams] (0 until n).map { i => CloneTileAttachParams(cloneTileId, tileAttachParams.copy( tileParams = tileAttachParams.tileParams.copy(tileId = i + idOffset) )) } ++ prev } case NumTiles => up(NumTiles) + n }) /** * BOOM Configs for CS152 lab */ class WithNCS152BaselineBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => val coreWidth = 1 // CS152: Change me (1 to 4) val memWidth = 1 // CS152: Change me (1 or 2) BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 4, // CS152: Change me (4 or 8) numRobEntries = 4, // CS152: Change me (2+) numIntPhysRegisters = 33, // CS152: Change me (33+) numLdqEntries = 8, // CS152: Change me (2+) numStqEntries = 8, // CS152: Change me (2+) maxBrCount = 8, // CS152: Change me (2+) enableBranchPrediction = false, // CS152: Change me numRasEntries = 0, // CS152: Change me // DO NOT CHANGE BELOW enableBranchPrintf = true, decodeWidth = coreWidth, numFetchBufferEntries = coreWidth * 8, numDCacheBanks = memWidth, issueParams = Seq( IssueParams(issueWidth=memWidth, numEntries=8, iqType=IQT_MEM.litValue, dispatchWidth=coreWidth), IssueParams(issueWidth=coreWidth, numEntries=32, iqType=IQT_INT.litValue, dispatchWidth=coreWidth), IssueParams(issueWidth=1, numEntries=4, iqType=IQT_FP.litValue , dispatchWidth=coreWidth)) // DO NOT CHANGE ABOVE ), dcache = Some(DCacheParams( rowBits=64, nSets=64, // CS152: Change me (must be pow2, 2-64) nWays=4, // CS152: Change me (1-8) nMSHRs=2 // CS152: Change me (1+) )), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) class WithNCS152DefaultBooms(n: Int = 1) extends Config( new WithTAGELBPD ++ // Default to TAGE-L BPD new Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) (0 until n).map { i => val coreWidth = 3 // CS152: Change me (1 to 4) val memWidth = 1 // CS152: Change me (1 or 2) val nIssueSlots = 32 // CS152: Change me (2+) BoomTileAttachParams( tileParams = BoomTileParams( core = BoomCoreParams( fetchWidth = 4, // CS152: Change me (4 or 8) numRobEntries = 96, // CS152: Change me (2+) numIntPhysRegisters = 96, // CS152: Change me (33+) numLdqEntries = 16, // CS152: Change me (2+) numStqEntries = 16, // CS152: Change me (2+) maxBrCount = 12, // CS152: Change me (2+) enableBranchPrediction = true, // CS152: Change me numRasEntries = 16, // CS152: Change me // DO NOT CHANGE BELOW enableBranchPrintf = true, decodeWidth = coreWidth, numFetchBufferEntries = coreWidth * 8, numDCacheBanks = memWidth, issueParams = Seq( IssueParams(issueWidth=memWidth, numEntries=nIssueSlots, iqType=IQT_MEM.litValue, dispatchWidth=coreWidth), IssueParams(issueWidth=coreWidth, numEntries=nIssueSlots, iqType=IQT_INT.litValue, dispatchWidth=coreWidth), IssueParams(issueWidth=1, numEntries=nIssueSlots, iqType=IQT_FP.litValue , dispatchWidth=coreWidth)) // DO NOT CHANGE ABOVE ), dcache = Some(DCacheParams( rowBits=64, nSets=64, // CS152: Change me (must be pow2, 2-64) nWays=4, // CS152: Change me (1-8) nMSHRs=2 // CS152: Change me (1+) )), tileId = i + idOffset ), crossingParams = RocketCrossingParams() ) } ++ prev } case NumTiles => up(NumTiles) + n }) ) /** * Branch prediction configs below */ class WithTAGELBPD extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( bpdMaxMetaLength = 120, globalHistoryLength = 64, localHistoryLength = 1, localHistoryNSets = 0, branchPredictor = ((resp_in: BranchPredictionBankResponse, p: Parameters) => { val loop = Module(new LoopBranchPredictorBank()(p)) val tage = Module(new TageBranchPredictorBank()(p)) val btb = Module(new BTBBranchPredictorBank()(p)) val bim = Module(new BIMBranchPredictorBank()(p)) val ubtb = Module(new FAMicroBTBBranchPredictorBank()(p)) val preds = Seq(loop, tage, btb, ubtb, bim) preds.map(_.io := DontCare) ubtb.io.resp_in(0) := resp_in bim.io.resp_in(0) := ubtb.io.resp btb.io.resp_in(0) := bim.io.resp tage.io.resp_in(0) := btb.io.resp loop.io.resp_in(0) := tage.io.resp (preds, loop.io.resp) }) ))) case other => other } }) class WithBoom2BPD extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( bpdMaxMetaLength = 45, globalHistoryLength = 16, localHistoryLength = 1, localHistoryNSets = 0, branchPredictor = ((resp_in: BranchPredictionBankResponse, p: Parameters) => { // gshare is just variant of TAGE with 1 table val gshare = Module(new TageBranchPredictorBank( BoomTageParams(tableInfo = Seq((256, 16, 7))) )(p)) val btb = Module(new BTBBranchPredictorBank()(p)) val bim = Module(new BIMBranchPredictorBank()(p)) val preds = Seq(bim, btb, gshare) preds.map(_.io := DontCare) bim.io.resp_in(0) := resp_in btb.io.resp_in(0) := bim.io.resp gshare.io.resp_in(0) := btb.io.resp (preds, gshare.io.resp) }) ))) case other => other } }) class WithAlpha21264BPD extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( bpdMaxMetaLength = 64, globalHistoryLength = 32, localHistoryLength = 32, localHistoryNSets = 128, branchPredictor = ((resp_in: BranchPredictionBankResponse, p: Parameters) => { val btb = Module(new BTBBranchPredictorBank()(p)) val gbim = Module(new HBIMBranchPredictorBank()(p)) val lbim = Module(new HBIMBranchPredictorBank(BoomHBIMParams(useLocal=true))(p)) val tourney = Module(new TourneyBranchPredictorBank()(p)) val preds = Seq(lbim, btb, gbim, tourney) preds.map(_.io := DontCare) gbim.io.resp_in(0) := resp_in lbim.io.resp_in(0) := resp_in tourney.io.resp_in(0) := gbim.io.resp tourney.io.resp_in(1) := lbim.io.resp btb.io.resp_in(0) := tourney.io.resp (preds, btb.io.resp) }) ))) case other => other } }) class WithSWBPD extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy( bpdMaxMetaLength = 1, globalHistoryLength = 32, localHistoryLength = 1, localHistoryNSets = 0, branchPredictor = ((resp_in: BranchPredictionBankResponse, p: Parameters) => { val sw = Module(new SwBranchPredictorBank()(p)) sw.io.resp_in(0) := resp_in (Seq(sw), sw.io.resp) }) ))) case other => other } })

module ComposedBranchPredictorBank_1( // @[composer.scala:14:7] input clock, // @[composer.scala:14:7] input reset, // @[composer.scala:14:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire _ubtb_io_resp_f1_0_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_0_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_0_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:449:26] wire [119:0] _ubtb_io_f3_meta; // @[config-mixins.scala:449:26] wire _bim_io_resp_f1_0_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_0_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_0_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:448:25] wire [119:0] _bim_io_f3_meta; // @[config-mixins.scala:448:25] wire _btb_io_resp_f1_0_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_0_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_0_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:447:25] wire [119:0] _btb_io_f3_meta; // @[config-mixins.scala:447:25] wire _tage_io_resp_f1_0_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_0_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_0_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:446:26] wire [119:0] _tage_io_f3_meta; // @[config-mixins.scala:446:26] wire [119:0] _loop_io_f3_meta; // @[config-mixins.scala:445:26] wire io_f0_valid_0 = io_f0_valid; // @[composer.scala:14:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[composer.scala:14:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[composer.scala:14:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[composer.scala:14:7] wire io_f3_fire_0 = io_f3_fire; // @[composer.scala:14:7] wire io_update_valid_0 = io_update_valid; // @[composer.scala:14:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[composer.scala:14:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[composer.scala:14:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[composer.scala:14:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[composer.scala:14:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[composer.scala:14:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[composer.scala:14:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[composer.scala:14:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[composer.scala:14:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[composer.scala:14:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[composer.scala:14:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[composer.scala:14:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[composer.scala:14:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[composer.scala:14:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[composer.scala:14:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[composer.scala:14:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[composer.scala:14:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire io_f1_lhist = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_0_taken_0; // @[composer.scala:14:7] wire io_resp_f1_0_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_0_is_jal_0; // @[composer.scala:14:7] wire io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_1_taken_0; // @[composer.scala:14:7] wire io_resp_f1_1_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_1_is_jal_0; // @[composer.scala:14:7] wire io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_2_taken_0; // @[composer.scala:14:7] wire io_resp_f1_2_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_2_is_jal_0; // @[composer.scala:14:7] wire io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_3_taken_0; // @[composer.scala:14:7] wire io_resp_f1_3_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_3_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_0_taken_0; // @[composer.scala:14:7] wire io_resp_f2_0_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_0_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_1_taken_0; // @[composer.scala:14:7] wire io_resp_f2_1_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_1_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_2_taken_0; // @[composer.scala:14:7] wire io_resp_f2_2_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_2_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_3_taken_0; // @[composer.scala:14:7] wire io_resp_f2_3_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_3_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_0_taken_0; // @[composer.scala:14:7] wire io_resp_f3_0_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_0_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_1_taken_0; // @[composer.scala:14:7] wire io_resp_f3_1_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_1_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_2_taken_0; // @[composer.scala:14:7] wire io_resp_f3_2_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_2_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_3_taken_0; // @[composer.scala:14:7] wire io_resp_f3_3_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_3_is_jal_0; // @[composer.scala:14:7] wire [119:0] io_f3_meta_0; // @[composer.scala:14:7] wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35] reg [35:0] s1_idx; // @[predictor.scala:163:29] reg [35:0] s2_idx; // @[predictor.scala:164:29] reg [35:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [35:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] assign io_f3_meta_0 = {7'h0, _loop_io_f3_meta[39:0], _tage_io_f3_meta[55:0], _btb_io_f3_meta[0], _ubtb_io_f3_meta[7:0], _bim_io_f3_meta[7:0]}; // @[composer.scala:14:7, :31:49, :36:14] always @(posedge clock) begin // @[composer.scala:14:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30] s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32] always @(posedge) LoopBranchPredictorBank_1 loop ( // @[config-mixins.scala:445:26] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_tage_io_resp_f1_0_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_is_br (_tage_io_resp_f1_0_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_is_jal (_tage_io_resp_f1_0_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_taken (_tage_io_resp_f1_1_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_is_br (_tage_io_resp_f1_1_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_is_jal (_tage_io_resp_f1_1_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_taken (_tage_io_resp_f1_2_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_is_br (_tage_io_resp_f1_2_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_is_jal (_tage_io_resp_f1_2_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_taken (_tage_io_resp_f1_3_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_is_br (_tage_io_resp_f1_3_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_is_jal (_tage_io_resp_f1_3_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_taken (_tage_io_resp_f2_0_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_is_br (_tage_io_resp_f2_0_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_is_jal (_tage_io_resp_f2_0_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_taken (_tage_io_resp_f2_1_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_is_br (_tage_io_resp_f2_1_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_is_jal (_tage_io_resp_f2_1_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_taken (_tage_io_resp_f2_2_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_is_br (_tage_io_resp_f2_2_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_is_jal (_tage_io_resp_f2_2_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_taken (_tage_io_resp_f2_3_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_is_br (_tage_io_resp_f2_3_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_is_jal (_tage_io_resp_f2_3_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_taken (_tage_io_resp_f3_0_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_is_br (_tage_io_resp_f3_0_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_is_jal (_tage_io_resp_f3_0_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_taken (_tage_io_resp_f3_1_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_is_br (_tage_io_resp_f3_1_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_is_jal (_tage_io_resp_f3_1_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_taken (_tage_io_resp_f3_2_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_is_br (_tage_io_resp_f3_2_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_is_jal (_tage_io_resp_f3_2_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_taken (_tage_io_resp_f3_3_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_is_br (_tage_io_resp_f3_3_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_is_jal (_tage_io_resp_f3_3_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_f1_0_taken (io_resp_f1_0_taken_0), .io_resp_f1_0_is_br (io_resp_f1_0_is_br_0), .io_resp_f1_0_is_jal (io_resp_f1_0_is_jal_0), .io_resp_f1_0_predicted_pc_valid (io_resp_f1_0_predicted_pc_valid_0), .io_resp_f1_0_predicted_pc_bits (io_resp_f1_0_predicted_pc_bits_0), .io_resp_f1_1_taken (io_resp_f1_1_taken_0), .io_resp_f1_1_is_br (io_resp_f1_1_is_br_0), .io_resp_f1_1_is_jal (io_resp_f1_1_is_jal_0), .io_resp_f1_1_predicted_pc_valid (io_resp_f1_1_predicted_pc_valid_0), .io_resp_f1_1_predicted_pc_bits (io_resp_f1_1_predicted_pc_bits_0), .io_resp_f1_2_taken (io_resp_f1_2_taken_0), .io_resp_f1_2_is_br (io_resp_f1_2_is_br_0), .io_resp_f1_2_is_jal (io_resp_f1_2_is_jal_0), .io_resp_f1_2_predicted_pc_valid (io_resp_f1_2_predicted_pc_valid_0), .io_resp_f1_2_predicted_pc_bits (io_resp_f1_2_predicted_pc_bits_0), .io_resp_f1_3_taken (io_resp_f1_3_taken_0), .io_resp_f1_3_is_br (io_resp_f1_3_is_br_0), .io_resp_f1_3_is_jal (io_resp_f1_3_is_jal_0), .io_resp_f1_3_predicted_pc_valid (io_resp_f1_3_predicted_pc_valid_0), .io_resp_f1_3_predicted_pc_bits (io_resp_f1_3_predicted_pc_bits_0), .io_resp_f2_0_taken (io_resp_f2_0_taken_0), .io_resp_f2_0_is_br (io_resp_f2_0_is_br_0), .io_resp_f2_0_is_jal (io_resp_f2_0_is_jal_0), .io_resp_f2_0_predicted_pc_valid (io_resp_f2_0_predicted_pc_valid_0), .io_resp_f2_0_predicted_pc_bits (io_resp_f2_0_predicted_pc_bits_0), .io_resp_f2_1_taken (io_resp_f2_1_taken_0), .io_resp_f2_1_is_br (io_resp_f2_1_is_br_0), .io_resp_f2_1_is_jal (io_resp_f2_1_is_jal_0), .io_resp_f2_1_predicted_pc_valid (io_resp_f2_1_predicted_pc_valid_0), .io_resp_f2_1_predicted_pc_bits (io_resp_f2_1_predicted_pc_bits_0), .io_resp_f2_2_taken (io_resp_f2_2_taken_0), .io_resp_f2_2_is_br (io_resp_f2_2_is_br_0), .io_resp_f2_2_is_jal (io_resp_f2_2_is_jal_0), .io_resp_f2_2_predicted_pc_valid (io_resp_f2_2_predicted_pc_valid_0), .io_resp_f2_2_predicted_pc_bits (io_resp_f2_2_predicted_pc_bits_0), .io_resp_f2_3_taken (io_resp_f2_3_taken_0), .io_resp_f2_3_is_br (io_resp_f2_3_is_br_0), .io_resp_f2_3_is_jal (io_resp_f2_3_is_jal_0), .io_resp_f2_3_predicted_pc_valid (io_resp_f2_3_predicted_pc_valid_0), .io_resp_f2_3_predicted_pc_bits (io_resp_f2_3_predicted_pc_bits_0), .io_resp_f3_0_taken (io_resp_f3_0_taken_0), .io_resp_f3_0_is_br (io_resp_f3_0_is_br_0), .io_resp_f3_0_is_jal (io_resp_f3_0_is_jal_0), .io_resp_f3_0_predicted_pc_valid (io_resp_f3_0_predicted_pc_valid_0), .io_resp_f3_0_predicted_pc_bits (io_resp_f3_0_predicted_pc_bits_0), .io_resp_f3_1_taken (io_resp_f3_1_taken_0), .io_resp_f3_1_is_br (io_resp_f3_1_is_br_0), .io_resp_f3_1_is_jal (io_resp_f3_1_is_jal_0), .io_resp_f3_1_predicted_pc_valid (io_resp_f3_1_predicted_pc_valid_0), .io_resp_f3_1_predicted_pc_bits (io_resp_f3_1_predicted_pc_bits_0), .io_resp_f3_2_taken (io_resp_f3_2_taken_0), .io_resp_f3_2_is_br (io_resp_f3_2_is_br_0), .io_resp_f3_2_is_jal (io_resp_f3_2_is_jal_0), .io_resp_f3_2_predicted_pc_valid (io_resp_f3_2_predicted_pc_valid_0), .io_resp_f3_2_predicted_pc_bits (io_resp_f3_2_predicted_pc_bits_0), .io_resp_f3_3_taken (io_resp_f3_3_taken_0), .io_resp_f3_3_is_br (io_resp_f3_3_is_br_0), .io_resp_f3_3_is_jal (io_resp_f3_3_is_jal_0), .io_resp_f3_3_predicted_pc_valid (io_resp_f3_3_predicted_pc_valid_0), .io_resp_f3_3_predicted_pc_bits (io_resp_f3_3_predicted_pc_bits_0), .io_f3_meta (_loop_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({73'h0, io_update_bits_meta_0[119:73]}) // @[composer.scala:14:7, :42:27, :43:31] ); // @[config-mixins.scala:445:26] TageBranchPredictorBank_1 tage ( // @[config-mixins.scala:446:26] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_btb_io_resp_f1_0_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_is_br (_btb_io_resp_f1_0_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_is_jal (_btb_io_resp_f1_0_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_taken (_btb_io_resp_f1_1_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_is_br (_btb_io_resp_f1_1_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_is_jal (_btb_io_resp_f1_1_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_taken (_btb_io_resp_f1_2_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_is_br (_btb_io_resp_f1_2_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_is_jal (_btb_io_resp_f1_2_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_taken (_btb_io_resp_f1_3_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_is_br (_btb_io_resp_f1_3_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_is_jal (_btb_io_resp_f1_3_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_taken (_btb_io_resp_f2_0_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_is_br (_btb_io_resp_f2_0_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_is_jal (_btb_io_resp_f2_0_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_taken (_btb_io_resp_f2_1_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_is_br (_btb_io_resp_f2_1_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_is_jal (_btb_io_resp_f2_1_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_taken (_btb_io_resp_f2_2_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_is_br (_btb_io_resp_f2_2_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_is_jal (_btb_io_resp_f2_2_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_taken (_btb_io_resp_f2_3_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_is_br (_btb_io_resp_f2_3_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_is_jal (_btb_io_resp_f2_3_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_taken (_btb_io_resp_f3_0_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_is_br (_btb_io_resp_f3_0_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_is_jal (_btb_io_resp_f3_0_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_taken (_btb_io_resp_f3_1_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_is_br (_btb_io_resp_f3_1_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_is_jal (_btb_io_resp_f3_1_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_taken (_btb_io_resp_f3_2_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_is_br (_btb_io_resp_f3_2_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_is_jal (_btb_io_resp_f3_2_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_taken (_btb_io_resp_f3_3_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_is_br (_btb_io_resp_f3_3_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_is_jal (_btb_io_resp_f3_3_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_f1_0_taken (_tage_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_tage_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_tage_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_tage_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_tage_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_tage_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_tage_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_tage_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_tage_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_tage_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_tage_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_tage_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_tage_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_tage_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_tage_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_tage_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_tage_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_tage_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_tage_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_tage_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_tage_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_tage_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_tage_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_tage_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_tage_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_tage_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_tage_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_tage_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_tage_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_tage_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_tage_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_tage_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_tage_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_tage_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_tage_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_tage_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_tage_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({17'h0, io_update_bits_meta_0[119:17]}) // @[composer.scala:14:7, :42:27, :43:31] ); // @[config-mixins.scala:446:26] BTBBranchPredictorBank_1 btb ( // @[config-mixins.scala:447:25] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_bim_io_resp_f1_0_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_is_br (_bim_io_resp_f1_0_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_is_jal (_bim_io_resp_f1_0_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_taken (_bim_io_resp_f1_1_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_is_br (_bim_io_resp_f1_1_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_is_jal (_bim_io_resp_f1_1_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_taken (_bim_io_resp_f1_2_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_is_br (_bim_io_resp_f1_2_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_is_jal (_bim_io_resp_f1_2_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_taken (_bim_io_resp_f1_3_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_is_br (_bim_io_resp_f1_3_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_is_jal (_bim_io_resp_f1_3_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_taken (_bim_io_resp_f2_0_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_is_br (_bim_io_resp_f2_0_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_is_jal (_bim_io_resp_f2_0_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_taken (_bim_io_resp_f2_1_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_is_br (_bim_io_resp_f2_1_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_is_jal (_bim_io_resp_f2_1_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_taken (_bim_io_resp_f2_2_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_is_br (_bim_io_resp_f2_2_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_is_jal (_bim_io_resp_f2_2_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_taken (_bim_io_resp_f2_3_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_is_br (_bim_io_resp_f2_3_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_is_jal (_bim_io_resp_f2_3_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_taken (_bim_io_resp_f3_0_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_is_br (_bim_io_resp_f3_0_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_is_jal (_bim_io_resp_f3_0_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_taken (_bim_io_resp_f3_1_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_is_br (_bim_io_resp_f3_1_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_is_jal (_bim_io_resp_f3_1_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_taken (_bim_io_resp_f3_2_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_is_br (_bim_io_resp_f3_2_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_is_jal (_bim_io_resp_f3_2_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_taken (_bim_io_resp_f3_3_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_is_br (_bim_io_resp_f3_3_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_is_jal (_bim_io_resp_f3_3_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_f1_0_taken (_btb_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_btb_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_btb_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_btb_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_btb_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_btb_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_btb_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_btb_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_btb_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_btb_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_btb_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_btb_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_btb_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_btb_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_btb_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_btb_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_btb_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_btb_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_btb_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_btb_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_btb_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_btb_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_btb_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_btb_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_btb_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_btb_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_btb_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_btb_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_btb_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_btb_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_btb_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_btb_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_btb_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_btb_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_btb_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_btb_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_btb_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({16'h0, io_update_bits_meta_0[119:16]}) // @[composer.scala:14:7, :42:27, :43:31] ); // @[config-mixins.scala:447:25] BIMBranchPredictorBank_1 bim ( // @[config-mixins.scala:448:25] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_ubtb_io_resp_f1_0_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_is_br (_ubtb_io_resp_f1_0_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_taken (_ubtb_io_resp_f1_1_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_is_br (_ubtb_io_resp_f1_1_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_taken (_ubtb_io_resp_f1_2_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_is_br (_ubtb_io_resp_f1_2_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_taken (_ubtb_io_resp_f1_3_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_is_br (_ubtb_io_resp_f1_3_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_taken (_ubtb_io_resp_f2_0_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_is_br (_ubtb_io_resp_f2_0_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_taken (_ubtb_io_resp_f2_1_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_is_br (_ubtb_io_resp_f2_1_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_taken (_ubtb_io_resp_f2_2_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_is_br (_ubtb_io_resp_f2_2_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_taken (_ubtb_io_resp_f2_3_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_is_br (_ubtb_io_resp_f2_3_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_taken (_ubtb_io_resp_f3_0_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_is_br (_ubtb_io_resp_f3_0_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_taken (_ubtb_io_resp_f3_1_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_is_br (_ubtb_io_resp_f3_1_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_taken (_ubtb_io_resp_f3_2_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_is_br (_ubtb_io_resp_f3_2_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_taken (_ubtb_io_resp_f3_3_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_is_br (_ubtb_io_resp_f3_3_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_f1_0_taken (_bim_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_bim_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_bim_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_bim_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_bim_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_bim_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_bim_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_bim_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_bim_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_bim_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_bim_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_bim_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_bim_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_bim_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_bim_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_bim_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_bim_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_bim_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_bim_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_bim_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_bim_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_bim_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_bim_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_bim_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_bim_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_bim_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_bim_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_bim_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_bim_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_bim_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_bim_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_bim_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_bim_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_bim_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_bim_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_bim_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_bim_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta (io_update_bits_meta_0) // @[composer.scala:14:7] ); // @[config-mixins.scala:448:25] FAMicroBTBBranchPredictorBank_1 ubtb ( // @[config-mixins.scala:449:26] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_f1_0_taken (_ubtb_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_ubtb_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_ubtb_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_ubtb_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_ubtb_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_ubtb_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_ubtb_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_ubtb_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_ubtb_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_ubtb_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_ubtb_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_ubtb_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_ubtb_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_ubtb_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_ubtb_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_ubtb_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_ubtb_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_ubtb_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_ubtb_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_ubtb_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_ubtb_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_ubtb_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_ubtb_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_ubtb_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_ubtb_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({8'h0, io_update_bits_meta_0[119:8]}) // @[composer.scala:14:7, :31:22, :42:27, :43:31] ); // @[config-mixins.scala:449:26] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[composer.scala:14:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[composer.scala:14:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[composer.scala:14:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[composer.scala:14:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[composer.scala:14:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[composer.scala:14:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[composer.scala:14:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[composer.scala:14:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[composer.scala:14:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[composer.scala:14:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[composer.scala:14:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[composer.scala:14:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_f3_meta = io_f3_meta_0; // @[composer.scala:14:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }

module PriorityQueueStage_122( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_EntryData_28( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn || noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }

module TLNoC_router_1ClockSinkDomain( // @[ClockDomain.scala:14:9] output [3:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_1 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready), .auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload), .auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready), .auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail), .auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload), .auto_ingress_nodes_in_2_flit_ready (auto_routers_ingress_nodes_in_2_flit_ready), .auto_ingress_nodes_in_2_flit_valid (auto_routers_ingress_nodes_in_2_flit_valid), .auto_ingress_nodes_in_2_flit_bits_head (auto_routers_ingress_nodes_in_2_flit_bits_head), .auto_ingress_nodes_in_2_flit_bits_payload (auto_routers_ingress_nodes_in_2_flit_bits_payload), .auto_ingress_nodes_in_2_flit_bits_egress_id (auto_routers_ingress_nodes_in_2_flit_bits_egress_id), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways * (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /** @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File BTB.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.HasCoreParameters import freechips.rocketchip.util._ case class BHTParams( nEntries: Int = 512, counterLength: Int = 1, historyLength: Int = 8, historyBits: Int = 3) case class BTBParams( nEntries: Int = 28, nMatchBits: Int = 14, nPages: Int = 6, nRAS: Int = 6, bhtParams: Option[BHTParams] = Some(BHTParams()), updatesOutOfOrder: Boolean = false) trait HasBtbParameters extends HasCoreParameters { this: InstanceId => val btbParams = tileParams.btb.getOrElse(BTBParams(nEntries = 0)) val matchBits = btbParams.nMatchBits max log2Ceil(p(CacheBlockBytes) * tileParams.icache.get.nSets) val entries = btbParams.nEntries val updatesOutOfOrder = btbParams.updatesOutOfOrder val nPages = (btbParams.nPages + 1) / 2 * 2 // control logic assumes 2 divides pages } abstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters { Annotated.params(this, btbParams) } abstract class BtbBundle(implicit val p: Parameters) extends Bundle with HasBtbParameters class RAS(nras: Int) { def push(addr: UInt): Unit = { when (count < nras.U) { count := count + 1.U } val nextPos = Mux((isPow2(nras)).B || pos < (nras-1).U, pos+1.U, 0.U) stack(nextPos) := addr pos := nextPos } def peek: UInt = stack(pos) def pop(): Unit = when (!isEmpty) { count := count - 1.U pos := Mux((isPow2(nras)).B || pos > 0.U, pos-1.U, (nras-1).U) } def clear(): Unit = count := 0.U def isEmpty: Bool = count === 0.U private val count = RegInit(0.U(log2Up(nras+1).W)) private val pos = RegInit(0.U(log2Up(nras).W)) private val stack = Reg(Vec(nras, UInt())) } class BHTResp(implicit p: Parameters) extends BtbBundle()(p) { val history = UInt(btbParams.bhtParams.map(_.historyLength).getOrElse(1).W) val value = UInt(btbParams.bhtParams.map(_.counterLength).getOrElse(1).W) def taken = value(0) def strongly_taken = value === 1.U } // BHT contains table of 2-bit counters and a global history register. // The BHT only predicts and updates when there is a BTB hit. // The global history: // - updated speculatively in fetch (if there's a BTB hit). // - on a mispredict, the history register is reset (again, only if BTB hit). // The counter table: // - each counter corresponds with the address of the fetch packet ("fetch pc"). // - updated when a branch resolves (and BTB was a hit for that branch). // The updating branch must provide its "fetch pc". class BHT(params: BHTParams)(implicit val p: Parameters) extends HasCoreParameters { def index(addr: UInt, history: UInt) = { def hashHistory(hist: UInt) = if (params.historyLength == params.historyBits) hist else { val k = math.sqrt(3)/2 val i = BigDecimal(k * math.pow(2, params.historyLength)).toBigInt (i.U * hist)(params.historyLength-1, params.historyLength-params.historyBits) } def hashAddr(addr: UInt) = { val hi = addr >> log2Ceil(fetchBytes) hi(log2Ceil(params.nEntries)-1, 0) ^ (hi >> log2Ceil(params.nEntries))(1, 0) } hashAddr(addr) ^ (hashHistory(history) << (log2Up(params.nEntries) - params.historyBits)) } def get(addr: UInt): BHTResp = { val res = Wire(new BHTResp) res.value := Mux(resetting, 0.U, table(index(addr, history))) res.history := history res } def updateTable(addr: UInt, d: BHTResp, taken: Bool): Unit = { wen := true.B when (!resetting) { waddr := index(addr, d.history) wdata := (params.counterLength match { case 1 => taken case 2 => Cat(taken ^ d.value(0), d.value === 1.U || d.value(1) && taken) }) } } def resetHistory(d: BHTResp): Unit = { history := d.history } def updateHistory(addr: UInt, d: BHTResp, taken: Bool): Unit = { history := Cat(taken, d.history >> 1) } def advanceHistory(taken: Bool): Unit = { history := Cat(taken, history >> 1) } private val table = Mem(params.nEntries, UInt(params.counterLength.W)) val history = RegInit(0.U(params.historyLength.W)) private val reset_waddr = RegInit(0.U((params.nEntries.log2+1).W)) private val resetting = !reset_waddr(params.nEntries.log2) private val wen = WireInit(resetting) private val waddr = WireInit(reset_waddr) private val wdata = WireInit(0.U) when (resetting) { reset_waddr := reset_waddr + 1.U } when (wen) { table(waddr) := wdata } } object CFIType { def SZ = 2 def apply() = UInt(SZ.W) def branch = 0.U def jump = 1.U def call = 2.U def ret = 3.U } // BTB update occurs during branch resolution (and only on a mispredict). // - "pc" is what future fetch PCs will tag match against. // - "br_pc" is the PC of the branch instruction. class BTBUpdate(implicit p: Parameters) extends BtbBundle()(p) { val prediction = new BTBResp val pc = UInt(vaddrBits.W) val target = UInt(vaddrBits.W) val taken = Bool() val isValid = Bool() val br_pc = UInt(vaddrBits.W) val cfiType = CFIType() } // BHT update occurs during branch resolution on all conditional branches. // - "pc" is what future fetch PCs will tag match against. class BHTUpdate(implicit p: Parameters) extends BtbBundle()(p) { val prediction = new BHTResp val pc = UInt(vaddrBits.W) val branch = Bool() val taken = Bool() val mispredict = Bool() } class RASUpdate(implicit p: Parameters) extends BtbBundle()(p) { val cfiType = CFIType() val returnAddr = UInt(vaddrBits.W) } // - "bridx" is the low-order PC bits of the predicted branch (after // shifting off the lowest log(inst_bytes) bits off). // - "mask" provides a mask of valid instructions (instructions are // masked off by the predicted taken branch from the BTB). class BTBResp(implicit p: Parameters) extends BtbBundle()(p) { val cfiType = CFIType() val taken = Bool() val mask = Bits(fetchWidth.W) val bridx = Bits(log2Up(fetchWidth).W) val target = UInt(vaddrBits.W) val entry = UInt(log2Up(entries + 1).W) val bht = new BHTResp } class BTBReq(implicit p: Parameters) extends BtbBundle()(p) { val addr = UInt(vaddrBits.W) } // fully-associative branch target buffer // Higher-performance processors may cause BTB updates to occur out-of-order, // which requires an extra CAM port for updates (to ensure no duplicates get // placed in BTB). class BTB(implicit p: Parameters) extends BtbModule { val io = IO(new Bundle { val req = Flipped(Valid(new BTBReq)) val resp = Valid(new BTBResp) val btb_update = Flipped(Valid(new BTBUpdate)) val bht_update = Flipped(Valid(new BHTUpdate)) val bht_advance = Flipped(Valid(new BTBResp)) val ras_update = Flipped(Valid(new RASUpdate)) val ras_head = Valid(UInt(vaddrBits.W)) val flush = Input(Bool()) }) val idxs = Reg(Vec(entries, UInt((matchBits - log2Up(coreInstBytes)).W))) val idxPages = Reg(Vec(entries, UInt(log2Up(nPages).W))) val tgts = Reg(Vec(entries, UInt((matchBits - log2Up(coreInstBytes)).W))) val tgtPages = Reg(Vec(entries, UInt(log2Up(nPages).W))) val pages = Reg(Vec(nPages, UInt((vaddrBits - matchBits).W))) val pageValid = RegInit(0.U(nPages.W)) val pagesMasked = (pageValid.asBools zip pages).map { case (v, p) => Mux(v, p, 0.U) } val isValid = RegInit(0.U(entries.W)) val cfiType = Reg(Vec(entries, CFIType())) val brIdx = Reg(Vec(entries, UInt(log2Up(fetchWidth).W))) private def page(addr: UInt) = addr >> matchBits private def pageMatch(addr: UInt) = { val p = page(addr) pageValid & pages.map(_ === p).asUInt } private def idxMatch(addr: UInt) = { val idx = addr(matchBits-1, log2Up(coreInstBytes)) idxs.map(_ === idx).asUInt & isValid } val r_btb_update = Pipe(io.btb_update) val update_target = io.req.bits.addr val pageHit = pageMatch(io.req.bits.addr) val idxHit = idxMatch(io.req.bits.addr) val updatePageHit = pageMatch(r_btb_update.bits.pc) val (updateHit, updateHitAddr) = if (updatesOutOfOrder) { val updateHits = (pageHit << 1)(Mux1H(idxMatch(r_btb_update.bits.pc), idxPages)) (updateHits.orR, OHToUInt(updateHits)) } else (r_btb_update.bits.prediction.entry < entries.U, r_btb_update.bits.prediction.entry) val useUpdatePageHit = updatePageHit.orR val usePageHit = pageHit.orR val doIdxPageRepl = !useUpdatePageHit val nextPageRepl = RegInit(0.U(log2Ceil(nPages).W)) val idxPageRepl = Cat(pageHit(nPages-2,0), pageHit(nPages-1)) | Mux(usePageHit, 0.U, UIntToOH(nextPageRepl)) val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl) val idxPageUpdate = OHToUInt(idxPageUpdateOH) val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, 0.U) val samePage = page(r_btb_update.bits.pc) === page(update_target) val doTgtPageRepl = !samePage && !usePageHit val tgtPageRepl = Mux(samePage, idxPageUpdateOH, Cat(idxPageUpdateOH(nPages-2,0), idxPageUpdateOH(nPages-1))) val tgtPageUpdate = OHToUInt(pageHit | Mux(usePageHit, 0.U, tgtPageRepl)) val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, 0.U) when (r_btb_update.valid && (doIdxPageRepl || doTgtPageRepl)) { val both = doIdxPageRepl && doTgtPageRepl val next = nextPageRepl + Mux[UInt](both, 2.U, 1.U) nextPageRepl := Mux(next >= nPages.U, next(0), next) } val repl = new PseudoLRU(entries) val waddr = Mux(updateHit, updateHitAddr, repl.way) val r_resp = Pipe(io.resp) when (r_resp.valid && r_resp.bits.taken || r_btb_update.valid) { repl.access(Mux(r_btb_update.valid, waddr, r_resp.bits.entry)) } when (r_btb_update.valid) { val mask = UIntToOH(waddr) idxs(waddr) := r_btb_update.bits.pc(matchBits-1, log2Up(coreInstBytes)) tgts(waddr) := update_target(matchBits-1, log2Up(coreInstBytes)) idxPages(waddr) := idxPageUpdate +& 1.U // the +1 corresponds to the <<1 on io.resp.valid tgtPages(waddr) := tgtPageUpdate cfiType(waddr) := r_btb_update.bits.cfiType isValid := Mux(r_btb_update.bits.isValid, isValid | mask, isValid & ~mask) if (fetchWidth > 1) brIdx(waddr) := r_btb_update.bits.br_pc >> log2Up(coreInstBytes) require(nPages % 2 == 0) val idxWritesEven = !idxPageUpdate(0) def writeBank(i: Int, mod: Int, en: UInt, data: UInt) = for (i <- i until nPages by mod) when (en(i)) { pages(i) := data } writeBank(0, 2, Mux(idxWritesEven, idxPageReplEn, tgtPageReplEn), Mux(idxWritesEven, page(r_btb_update.bits.pc), page(update_target))) writeBank(1, 2, Mux(idxWritesEven, tgtPageReplEn, idxPageReplEn), Mux(idxWritesEven, page(update_target), page(r_btb_update.bits.pc))) pageValid := pageValid | tgtPageReplEn | idxPageReplEn } io.resp.valid := (pageHit << 1)(Mux1H(idxHit, idxPages)) io.resp.bits.taken := true.B io.resp.bits.target := Cat(pagesMasked(Mux1H(idxHit, tgtPages)), Mux1H(idxHit, tgts) << log2Up(coreInstBytes)) io.resp.bits.entry := OHToUInt(idxHit) io.resp.bits.bridx := (if (fetchWidth > 1) Mux1H(idxHit, brIdx) else 0.U) io.resp.bits.mask := Cat((1.U << ~Mux(io.resp.bits.taken, ~io.resp.bits.bridx, 0.U))-1.U, 1.U) io.resp.bits.cfiType := Mux1H(idxHit, cfiType) // if multiple entries for same PC land in BTB, zap them when (PopCountAtLeast(idxHit, 2)) { isValid := isValid & ~idxHit } when (io.flush) { isValid := 0.U } if (btbParams.bhtParams.nonEmpty) { val bht = new BHT(Annotated.params(this, btbParams.bhtParams.get)) val isBranch = (idxHit & cfiType.map(_ === CFIType.branch).asUInt).orR val res = bht.get(io.req.bits.addr) when (io.bht_advance.valid) { bht.advanceHistory(io.bht_advance.bits.bht.taken) } when (io.bht_update.valid) { when (io.bht_update.bits.branch) { bht.updateTable(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken) when (io.bht_update.bits.mispredict) { bht.updateHistory(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken) } }.elsewhen (io.bht_update.bits.mispredict) { bht.resetHistory(io.bht_update.bits.prediction) } } when (!res.taken && isBranch) { io.resp.bits.taken := false.B } io.resp.bits.bht := res } if (btbParams.nRAS > 0) { val ras = new RAS(btbParams.nRAS) val doPeek = (idxHit & cfiType.map(_ === CFIType.ret).asUInt).orR io.ras_head.valid := !ras.isEmpty io.ras_head.bits := ras.peek when (!ras.isEmpty && doPeek) { io.resp.bits.target := ras.peek } when (io.ras_update.valid) { when (io.ras_update.bits.cfiType === CFIType.call) { ras.push(io.ras_update.bits.returnAddr) }.elsewhen (io.ras_update.bits.cfiType === CFIType.ret) { ras.pop() } } } }

module BTB_4( // @[BTB.scala:187:7] input clock, // @[BTB.scala:187:7] input reset, // @[BTB.scala:187:7] input io_req_valid, // @[BTB.scala:188:14] input [38:0] io_req_bits_addr, // @[BTB.scala:188:14] output io_resp_valid, // @[BTB.scala:188:14] output [1:0] io_resp_bits_cfiType, // @[BTB.scala:188:14] output io_resp_bits_taken, // @[BTB.scala:188:14] output [1:0] io_resp_bits_mask, // @[BTB.scala:188:14] output io_resp_bits_bridx, // @[BTB.scala:188:14] output [38:0] io_resp_bits_target, // @[BTB.scala:188:14] output [4:0] io_resp_bits_entry, // @[BTB.scala:188:14] output [7:0] io_resp_bits_bht_history, // @[BTB.scala:188:14] output io_resp_bits_bht_value, // @[BTB.scala:188:14] input io_btb_update_valid, // @[BTB.scala:188:14] input [1:0] io_btb_update_bits_prediction_cfiType, // @[BTB.scala:188:14] input io_btb_update_bits_prediction_taken, // @[BTB.scala:188:14] input [1:0] io_btb_update_bits_prediction_mask, // @[BTB.scala:188:14] input io_btb_update_bits_prediction_bridx, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_prediction_target, // @[BTB.scala:188:14] input [4:0] io_btb_update_bits_prediction_entry, // @[BTB.scala:188:14] input [7:0] io_btb_update_bits_prediction_bht_history, // @[BTB.scala:188:14] input io_btb_update_bits_prediction_bht_value, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_pc, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_target, // @[BTB.scala:188:14] input io_btb_update_bits_isValid, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_br_pc, // @[BTB.scala:188:14] input [1:0] io_btb_update_bits_cfiType, // @[BTB.scala:188:14] input io_bht_update_valid, // @[BTB.scala:188:14] input [7:0] io_bht_update_bits_prediction_history, // @[BTB.scala:188:14] input io_bht_update_bits_prediction_value, // @[BTB.scala:188:14] input [38:0] io_bht_update_bits_pc, // @[BTB.scala:188:14] input io_bht_update_bits_branch, // @[BTB.scala:188:14] input io_bht_update_bits_taken, // @[BTB.scala:188:14] input io_bht_update_bits_mispredict, // @[BTB.scala:188:14] input io_bht_advance_valid, // @[BTB.scala:188:14] input [1:0] io_bht_advance_bits_cfiType, // @[BTB.scala:188:14] input io_bht_advance_bits_taken, // @[BTB.scala:188:14] input [1:0] io_bht_advance_bits_mask, // @[BTB.scala:188:14] input io_bht_advance_bits_bridx, // @[BTB.scala:188:14] input [38:0] io_bht_advance_bits_target, // @[BTB.scala:188:14] input [4:0] io_bht_advance_bits_entry, // @[BTB.scala:188:14] input [7:0] io_bht_advance_bits_bht_history, // @[BTB.scala:188:14] input io_bht_advance_bits_bht_value, // @[BTB.scala:188:14] input io_ras_update_valid, // @[BTB.scala:188:14] input [1:0] io_ras_update_bits_cfiType, // @[BTB.scala:188:14] input [38:0] io_ras_update_bits_returnAddr, // @[BTB.scala:188:14] output io_ras_head_valid, // @[BTB.scala:188:14] output [38:0] io_ras_head_bits, // @[BTB.scala:188:14] input io_flush // @[BTB.scala:188:14] ); wire _table_ext_R0_data; // @[BTB.scala:116:26] wire io_req_valid_0 = io_req_valid; // @[BTB.scala:187:7] wire [38:0] io_req_bits_addr_0 = io_req_bits_addr; // @[BTB.scala:187:7] wire io_btb_update_valid_0 = io_btb_update_valid; // @[BTB.scala:187:7] wire [1:0] io_btb_update_bits_prediction_cfiType_0 = io_btb_update_bits_prediction_cfiType; // @[BTB.scala:187:7] wire io_btb_update_bits_prediction_taken_0 = io_btb_update_bits_prediction_taken; // @[BTB.scala:187:7] wire [1:0] io_btb_update_bits_prediction_mask_0 = io_btb_update_bits_prediction_mask; // @[BTB.scala:187:7] wire io_btb_update_bits_prediction_bridx_0 = io_btb_update_bits_prediction_bridx; // @[BTB.scala:187:7] wire [38:0] io_btb_update_bits_prediction_target_0 = io_btb_update_bits_prediction_target; // @[BTB.scala:187:7] wire [4:0] io_btb_update_bits_prediction_entry_0 = io_btb_update_bits_prediction_entry; // @[BTB.scala:187:7] wire [7:0] io_btb_update_bits_prediction_bht_history_0 = io_btb_update_bits_prediction_bht_history; // @[BTB.scala:187:7] wire io_btb_update_bits_prediction_bht_value_0 = io_btb_update_bits_prediction_bht_value; // @[BTB.scala:187:7] wire [38:0] io_btb_update_bits_pc_0 = io_btb_update_bits_pc; // @[BTB.scala:187:7] wire [38:0] io_btb_update_bits_target_0 = io_btb_update_bits_target; // @[BTB.scala:187:7] wire io_btb_update_bits_isValid_0 = io_btb_update_bits_isValid; // @[BTB.scala:187:7] wire [38:0] io_btb_update_bits_br_pc_0 = io_btb_update_bits_br_pc; // @[BTB.scala:187:7] wire [1:0] io_btb_update_bits_cfiType_0 = io_btb_update_bits_cfiType; // @[BTB.scala:187:7] wire io_bht_update_valid_0 = io_bht_update_valid; // @[BTB.scala:187:7] wire [7:0] io_bht_update_bits_prediction_history_0 = io_bht_update_bits_prediction_history; // @[BTB.scala:187:7] wire io_bht_update_bits_prediction_value_0 = io_bht_update_bits_prediction_value; // @[BTB.scala:187:7] wire [38:0] io_bht_update_bits_pc_0 = io_bht_update_bits_pc; // @[BTB.scala:187:7] wire io_bht_update_bits_branch_0 = io_bht_update_bits_branch; // @[BTB.scala:187:7] wire io_bht_update_bits_taken_0 = io_bht_update_bits_taken; // @[BTB.scala:187:7] wire io_bht_update_bits_mispredict_0 = io_bht_update_bits_mispredict; // @[BTB.scala:187:7] wire io_bht_advance_valid_0 = io_bht_advance_valid; // @[BTB.scala:187:7] wire [1:0] io_bht_advance_bits_cfiType_0 = io_bht_advance_bits_cfiType; // @[BTB.scala:187:7] wire io_bht_advance_bits_taken_0 = io_bht_advance_bits_taken; // @[BTB.scala:187:7] wire [1:0] io_bht_advance_bits_mask_0 = io_bht_advance_bits_mask; // @[BTB.scala:187:7] wire io_bht_advance_bits_bridx_0 = io_bht_advance_bits_bridx; // @[BTB.scala:187:7] wire [38:0] io_bht_advance_bits_target_0 = io_bht_advance_bits_target; // @[BTB.scala:187:7] wire [4:0] io_bht_advance_bits_entry_0 = io_bht_advance_bits_entry; // @[BTB.scala:187:7] wire [7:0] io_bht_advance_bits_bht_history_0 = io_bht_advance_bits_bht_history; // @[BTB.scala:187:7] wire io_bht_advance_bits_bht_value_0 = io_bht_advance_bits_bht_value; // @[BTB.scala:187:7] wire io_ras_update_valid_0 = io_ras_update_valid; // @[BTB.scala:187:7] wire [1:0] io_ras_update_bits_cfiType_0 = io_ras_update_bits_cfiType; // @[BTB.scala:187:7] wire [38:0] io_ras_update_bits_returnAddr_0 = io_ras_update_bits_returnAddr; // @[BTB.scala:187:7] wire io_flush_0 = io_flush; // @[BTB.scala:187:7] wire io_btb_update_bits_taken = 1'h0; // @[BTB.scala:187:7] wire r_btb_update_bits_taken = 1'h0; // @[Valid.scala:135:21] wire _io_resp_valid_T_85; // @[BTB.scala:287:34] wire [1:0] _io_resp_bits_cfiType_WIRE; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_WIRE; // @[Mux.scala:30:73] wire [4:0] _io_resp_bits_entry_T_12; // @[OneHot.scala:32:10] wire [7:0] res_history; // @[BTB.scala:91:19] wire res_value; // @[BTB.scala:91:19] wire _io_ras_head_valid_T_1; // @[BTB.scala:327:26] wire [7:0] io_resp_bits_bht_history_0; // @[BTB.scala:187:7] wire io_resp_bits_bht_value_0; // @[BTB.scala:187:7] wire [1:0] io_resp_bits_cfiType_0; // @[BTB.scala:187:7] wire io_resp_bits_taken_0; // @[BTB.scala:187:7] wire [1:0] io_resp_bits_mask_0; // @[BTB.scala:187:7] wire io_resp_bits_bridx_0; // @[BTB.scala:187:7] wire [38:0] io_resp_bits_target_0; // @[BTB.scala:187:7] wire [4:0] io_resp_bits_entry_0; // @[BTB.scala:187:7] wire io_resp_valid_0; // @[BTB.scala:187:7] wire io_ras_head_valid_0; // @[BTB.scala:187:7] wire [38:0] io_ras_head_bits_0; // @[BTB.scala:187:7] reg [12:0] idxs_0; // @[BTB.scala:199:17] reg [12:0] idxs_1; // @[BTB.scala:199:17] reg [12:0] idxs_2; // @[BTB.scala:199:17] reg [12:0] idxs_3; // @[BTB.scala:199:17] reg [12:0] idxs_4; // @[BTB.scala:199:17] reg [12:0] idxs_5; // @[BTB.scala:199:17] reg [12:0] idxs_6; // @[BTB.scala:199:17] reg [12:0] idxs_7; // @[BTB.scala:199:17] reg [12:0] idxs_8; // @[BTB.scala:199:17] reg [12:0] idxs_9; // @[BTB.scala:199:17] reg [12:0] idxs_10; // @[BTB.scala:199:17] reg [12:0] idxs_11; // @[BTB.scala:199:17] reg [12:0] idxs_12; // @[BTB.scala:199:17] reg [12:0] idxs_13; // @[BTB.scala:199:17] reg [12:0] idxs_14; // @[BTB.scala:199:17] reg [12:0] idxs_15; // @[BTB.scala:199:17] reg [12:0] idxs_16; // @[BTB.scala:199:17] reg [12:0] idxs_17; // @[BTB.scala:199:17] reg [12:0] idxs_18; // @[BTB.scala:199:17] reg [12:0] idxs_19; // @[BTB.scala:199:17] reg [12:0] idxs_20; // @[BTB.scala:199:17] reg [12:0] idxs_21; // @[BTB.scala:199:17] reg [12:0] idxs_22; // @[BTB.scala:199:17] reg [12:0] idxs_23; // @[BTB.scala:199:17] reg [12:0] idxs_24; // @[BTB.scala:199:17] reg [12:0] idxs_25; // @[BTB.scala:199:17] reg [12:0] idxs_26; // @[BTB.scala:199:17] reg [12:0] idxs_27; // @[BTB.scala:199:17] reg [2:0] idxPages_0; // @[BTB.scala:200:21] reg [2:0] idxPages_1; // @[BTB.scala:200:21] reg [2:0] idxPages_2; // @[BTB.scala:200:21] reg [2:0] idxPages_3; // @[BTB.scala:200:21] reg [2:0] idxPages_4; // @[BTB.scala:200:21] reg [2:0] idxPages_5; // @[BTB.scala:200:21] reg [2:0] idxPages_6; // @[BTB.scala:200:21] reg [2:0] idxPages_7; // @[BTB.scala:200:21] reg [2:0] idxPages_8; // @[BTB.scala:200:21] reg [2:0] idxPages_9; // @[BTB.scala:200:21] reg [2:0] idxPages_10; // @[BTB.scala:200:21] reg [2:0] idxPages_11; // @[BTB.scala:200:21] reg [2:0] idxPages_12; // @[BTB.scala:200:21] reg [2:0] idxPages_13; // @[BTB.scala:200:21] reg [2:0] idxPages_14; // @[BTB.scala:200:21] reg [2:0] idxPages_15; // @[BTB.scala:200:21] reg [2:0] idxPages_16; // @[BTB.scala:200:21] reg [2:0] idxPages_17; // @[BTB.scala:200:21] reg [2:0] idxPages_18; // @[BTB.scala:200:21] reg [2:0] idxPages_19; // @[BTB.scala:200:21] reg [2:0] idxPages_20; // @[BTB.scala:200:21] reg [2:0] idxPages_21; // @[BTB.scala:200:21] reg [2:0] idxPages_22; // @[BTB.scala:200:21] reg [2:0] idxPages_23; // @[BTB.scala:200:21] reg [2:0] idxPages_24; // @[BTB.scala:200:21] reg [2:0] idxPages_25; // @[BTB.scala:200:21] reg [2:0] idxPages_26; // @[BTB.scala:200:21] reg [2:0] idxPages_27; // @[BTB.scala:200:21] reg [12:0] tgts_0; // @[BTB.scala:201:17] reg [12:0] tgts_1; // @[BTB.scala:201:17] reg [12:0] tgts_2; // @[BTB.scala:201:17] reg [12:0] tgts_3; // @[BTB.scala:201:17] reg [12:0] tgts_4; // @[BTB.scala:201:17] reg [12:0] tgts_5; // @[BTB.scala:201:17] reg [12:0] tgts_6; // @[BTB.scala:201:17] reg [12:0] tgts_7; // @[BTB.scala:201:17] reg [12:0] tgts_8; // @[BTB.scala:201:17] reg [12:0] tgts_9; // @[BTB.scala:201:17] reg [12:0] tgts_10; // @[BTB.scala:201:17] reg [12:0] tgts_11; // @[BTB.scala:201:17] reg [12:0] tgts_12; // @[BTB.scala:201:17] reg [12:0] tgts_13; // @[BTB.scala:201:17] reg [12:0] tgts_14; // @[BTB.scala:201:17] reg [12:0] tgts_15; // @[BTB.scala:201:17] reg [12:0] tgts_16; // @[BTB.scala:201:17] reg [12:0] tgts_17; // @[BTB.scala:201:17] reg [12:0] tgts_18; // @[BTB.scala:201:17] reg [12:0] tgts_19; // @[BTB.scala:201:17] reg [12:0] tgts_20; // @[BTB.scala:201:17] reg [12:0] tgts_21; // @[BTB.scala:201:17] reg [12:0] tgts_22; // @[BTB.scala:201:17] reg [12:0] tgts_23; // @[BTB.scala:201:17] reg [12:0] tgts_24; // @[BTB.scala:201:17] reg [12:0] tgts_25; // @[BTB.scala:201:17] reg [12:0] tgts_26; // @[BTB.scala:201:17] reg [12:0] tgts_27; // @[BTB.scala:201:17] reg [2:0] tgtPages_0; // @[BTB.scala:202:21] reg [2:0] tgtPages_1; // @[BTB.scala:202:21] reg [2:0] tgtPages_2; // @[BTB.scala:202:21] reg [2:0] tgtPages_3; // @[BTB.scala:202:21] reg [2:0] tgtPages_4; // @[BTB.scala:202:21] reg [2:0] tgtPages_5; // @[BTB.scala:202:21] reg [2:0] tgtPages_6; // @[BTB.scala:202:21] reg [2:0] tgtPages_7; // @[BTB.scala:202:21] reg [2:0] tgtPages_8; // @[BTB.scala:202:21] reg [2:0] tgtPages_9; // @[BTB.scala:202:21] reg [2:0] tgtPages_10; // @[BTB.scala:202:21] reg [2:0] tgtPages_11; // @[BTB.scala:202:21] reg [2:0] tgtPages_12; // @[BTB.scala:202:21] reg [2:0] tgtPages_13; // @[BTB.scala:202:21] reg [2:0] tgtPages_14; // @[BTB.scala:202:21] reg [2:0] tgtPages_15; // @[BTB.scala:202:21] reg [2:0] tgtPages_16; // @[BTB.scala:202:21] reg [2:0] tgtPages_17; // @[BTB.scala:202:21] reg [2:0] tgtPages_18; // @[BTB.scala:202:21] reg [2:0] tgtPages_19; // @[BTB.scala:202:21] reg [2:0] tgtPages_20; // @[BTB.scala:202:21] reg [2:0] tgtPages_21; // @[BTB.scala:202:21] reg [2:0] tgtPages_22; // @[BTB.scala:202:21] reg [2:0] tgtPages_23; // @[BTB.scala:202:21] reg [2:0] tgtPages_24; // @[BTB.scala:202:21] reg [2:0] tgtPages_25; // @[BTB.scala:202:21] reg [2:0] tgtPages_26; // @[BTB.scala:202:21] reg [2:0] tgtPages_27; // @[BTB.scala:202:21] reg [24:0] pages_0; // @[BTB.scala:203:18] reg [24:0] pages_1; // @[BTB.scala:203:18] reg [24:0] pages_2; // @[BTB.scala:203:18] reg [24:0] pages_3; // @[BTB.scala:203:18] reg [24:0] pages_4; // @[BTB.scala:203:18] reg [24:0] pages_5; // @[BTB.scala:203:18] reg [5:0] pageValid; // @[BTB.scala:204:26] wire _pagesMasked_T = pageValid[0]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_1 = pageValid[1]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_2 = pageValid[2]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_3 = pageValid[3]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_4 = pageValid[4]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_5 = pageValid[5]; // @[BTB.scala:204:26, :205:32] wire [24:0] pagesMasked_0 = _pagesMasked_T ? pages_0 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_1 = _pagesMasked_T_1 ? pages_1 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_2 = _pagesMasked_T_2 ? pages_2 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_3 = _pagesMasked_T_3 ? pages_3 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_4 = _pagesMasked_T_4 ? pages_4 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_5 = _pagesMasked_T_5 ? pages_5 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] reg [27:0] isValid; // @[BTB.scala:207:24] reg [1:0] cfiType_0; // @[BTB.scala:208:20] reg [1:0] cfiType_1; // @[BTB.scala:208:20] reg [1:0] cfiType_2; // @[BTB.scala:208:20] reg [1:0] cfiType_3; // @[BTB.scala:208:20] reg [1:0] cfiType_4; // @[BTB.scala:208:20] reg [1:0] cfiType_5; // @[BTB.scala:208:20] reg [1:0] cfiType_6; // @[BTB.scala:208:20] reg [1:0] cfiType_7; // @[BTB.scala:208:20] reg [1:0] cfiType_8; // @[BTB.scala:208:20] reg [1:0] cfiType_9; // @[BTB.scala:208:20] reg [1:0] cfiType_10; // @[BTB.scala:208:20] reg [1:0] cfiType_11; // @[BTB.scala:208:20] reg [1:0] cfiType_12; // @[BTB.scala:208:20] reg [1:0] cfiType_13; // @[BTB.scala:208:20] reg [1:0] cfiType_14; // @[BTB.scala:208:20] reg [1:0] cfiType_15; // @[BTB.scala:208:20] reg [1:0] cfiType_16; // @[BTB.scala:208:20] reg [1:0] cfiType_17; // @[BTB.scala:208:20] reg [1:0] cfiType_18; // @[BTB.scala:208:20] reg [1:0] cfiType_19; // @[BTB.scala:208:20] reg [1:0] cfiType_20; // @[BTB.scala:208:20] reg [1:0] cfiType_21; // @[BTB.scala:208:20] reg [1:0] cfiType_22; // @[BTB.scala:208:20] reg [1:0] cfiType_23; // @[BTB.scala:208:20] reg [1:0] cfiType_24; // @[BTB.scala:208:20] reg [1:0] cfiType_25; // @[BTB.scala:208:20] reg [1:0] cfiType_26; // @[BTB.scala:208:20] reg [1:0] cfiType_27; // @[BTB.scala:208:20] reg brIdx_0; // @[BTB.scala:209:18] reg brIdx_1; // @[BTB.scala:209:18] reg brIdx_2; // @[BTB.scala:209:18] reg brIdx_3; // @[BTB.scala:209:18] reg brIdx_4; // @[BTB.scala:209:18] reg brIdx_5; // @[BTB.scala:209:18] reg brIdx_6; // @[BTB.scala:209:18] reg brIdx_7; // @[BTB.scala:209:18] reg brIdx_8; // @[BTB.scala:209:18] reg brIdx_9; // @[BTB.scala:209:18] reg brIdx_10; // @[BTB.scala:209:18] reg brIdx_11; // @[BTB.scala:209:18] reg brIdx_12; // @[BTB.scala:209:18] reg brIdx_13; // @[BTB.scala:209:18] reg brIdx_14; // @[BTB.scala:209:18] reg brIdx_15; // @[BTB.scala:209:18] reg brIdx_16; // @[BTB.scala:209:18] reg brIdx_17; // @[BTB.scala:209:18] reg brIdx_18; // @[BTB.scala:209:18] reg brIdx_19; // @[BTB.scala:209:18] reg brIdx_20; // @[BTB.scala:209:18] reg brIdx_21; // @[BTB.scala:209:18] reg brIdx_22; // @[BTB.scala:209:18] reg brIdx_23; // @[BTB.scala:209:18] reg brIdx_24; // @[BTB.scala:209:18] reg brIdx_25; // @[BTB.scala:209:18] reg brIdx_26; // @[BTB.scala:209:18] reg brIdx_27; // @[BTB.scala:209:18] reg r_btb_update_pipe_v; // @[Valid.scala:141:24] wire r_btb_update_valid = r_btb_update_pipe_v; // @[Valid.scala:135:21, :141:24] reg [1:0] r_btb_update_pipe_b_prediction_cfiType; // @[Valid.scala:142:26] wire [1:0] r_btb_update_bits_prediction_cfiType = r_btb_update_pipe_b_prediction_cfiType; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_prediction_taken; // @[Valid.scala:142:26] wire r_btb_update_bits_prediction_taken = r_btb_update_pipe_b_prediction_taken; // @[Valid.scala:135:21, :142:26] reg [1:0] r_btb_update_pipe_b_prediction_mask; // @[Valid.scala:142:26] wire [1:0] r_btb_update_bits_prediction_mask = r_btb_update_pipe_b_prediction_mask; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_prediction_bridx; // @[Valid.scala:142:26] wire r_btb_update_bits_prediction_bridx = r_btb_update_pipe_b_prediction_bridx; // @[Valid.scala:135:21, :142:26] reg [38:0] r_btb_update_pipe_b_prediction_target; // @[Valid.scala:142:26] wire [38:0] r_btb_update_bits_prediction_target = r_btb_update_pipe_b_prediction_target; // @[Valid.scala:135:21, :142:26] reg [4:0] r_btb_update_pipe_b_prediction_entry; // @[Valid.scala:142:26] wire [4:0] r_btb_update_bits_prediction_entry = r_btb_update_pipe_b_prediction_entry; // @[Valid.scala:135:21, :142:26] reg [7:0] r_btb_update_pipe_b_prediction_bht_history; // @[Valid.scala:142:26] wire [7:0] r_btb_update_bits_prediction_bht_history = r_btb_update_pipe_b_prediction_bht_history; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_prediction_bht_value; // @[Valid.scala:142:26] wire r_btb_update_bits_prediction_bht_value = r_btb_update_pipe_b_prediction_bht_value; // @[Valid.scala:135:21, :142:26] reg [38:0] r_btb_update_pipe_b_pc; // @[Valid.scala:142:26] wire [38:0] r_btb_update_bits_pc = r_btb_update_pipe_b_pc; // @[Valid.scala:135:21, :142:26] reg [38:0] r_btb_update_pipe_b_target; // @[Valid.scala:142:26] wire [38:0] r_btb_update_bits_target = r_btb_update_pipe_b_target; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_isValid; // @[Valid.scala:142:26] wire r_btb_update_bits_isValid = r_btb_update_pipe_b_isValid; // @[Valid.scala:135:21, :142:26] reg [38:0] r_btb_update_pipe_b_br_pc; // @[Valid.scala:142:26] wire [38:0] r_btb_update_bits_br_pc = r_btb_update_pipe_b_br_pc; // @[Valid.scala:135:21, :142:26] reg [1:0] r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] wire [1:0] r_btb_update_bits_cfiType = r_btb_update_pipe_b_cfiType; // @[Valid.scala:135:21, :142:26] wire [24:0] pageHit_p = io_req_bits_addr_0[38:14]; // @[BTB.scala:187:7, :211:39] wire [24:0] _samePage_T_1 = io_req_bits_addr_0[38:14]; // @[BTB.scala:187:7, :211:39] wire _pageHit_T = pages_0 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_1 = pages_1 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_2 = pages_2 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_3 = pages_3 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_4 = pages_4 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_5 = pages_5 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire [1:0] pageHit_lo_hi = {_pageHit_T_2, _pageHit_T_1}; // @[package.scala:45:27] wire [2:0] pageHit_lo = {pageHit_lo_hi, _pageHit_T}; // @[package.scala:45:27] wire [1:0] pageHit_hi_hi = {_pageHit_T_5, _pageHit_T_4}; // @[package.scala:45:27] wire [2:0] pageHit_hi = {pageHit_hi_hi, _pageHit_T_3}; // @[package.scala:45:27] wire [5:0] _pageHit_T_6 = {pageHit_hi, pageHit_lo}; // @[package.scala:45:27] wire [5:0] pageHit = pageValid & _pageHit_T_6; // @[package.scala:45:27] wire [12:0] idxHit_idx = io_req_bits_addr_0[13:1]; // @[BTB.scala:187:7, :217:19] wire [12:0] _tgts_T = io_req_bits_addr_0[13:1]; // @[BTB.scala:187:7, :217:19, :265:33] wire _idxHit_T = idxs_0 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_1 = idxs_1 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_2 = idxs_2 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_3 = idxs_3 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_4 = idxs_4 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_5 = idxs_5 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_6 = idxs_6 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_7 = idxs_7 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_8 = idxs_8 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_9 = idxs_9 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_10 = idxs_10 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_11 = idxs_11 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_12 = idxs_12 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_13 = idxs_13 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_14 = idxs_14 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_15 = idxs_15 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_16 = idxs_16 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_17 = idxs_17 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_18 = idxs_18 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_19 = idxs_19 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_20 = idxs_20 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_21 = idxs_21 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_22 = idxs_22 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_23 = idxs_23 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_24 = idxs_24 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_25 = idxs_25 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_26 = idxs_26 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_27 = idxs_27 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire [1:0] idxHit_lo_lo_lo_hi = {_idxHit_T_2, _idxHit_T_1}; // @[package.scala:45:27] wire [2:0] idxHit_lo_lo_lo = {idxHit_lo_lo_lo_hi, _idxHit_T}; // @[package.scala:45:27] wire [1:0] idxHit_lo_lo_hi_lo = {_idxHit_T_4, _idxHit_T_3}; // @[package.scala:45:27] wire [1:0] idxHit_lo_lo_hi_hi = {_idxHit_T_6, _idxHit_T_5}; // @[package.scala:45:27] wire [3:0] idxHit_lo_lo_hi = {idxHit_lo_lo_hi_hi, idxHit_lo_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_lo_lo = {idxHit_lo_lo_hi, idxHit_lo_lo_lo}; // @[package.scala:45:27] wire [1:0] idxHit_lo_hi_lo_hi = {_idxHit_T_9, _idxHit_T_8}; // @[package.scala:45:27] wire [2:0] idxHit_lo_hi_lo = {idxHit_lo_hi_lo_hi, _idxHit_T_7}; // @[package.scala:45:27] wire [1:0] idxHit_lo_hi_hi_lo = {_idxHit_T_11, _idxHit_T_10}; // @[package.scala:45:27] wire [1:0] idxHit_lo_hi_hi_hi = {_idxHit_T_13, _idxHit_T_12}; // @[package.scala:45:27] wire [3:0] idxHit_lo_hi_hi = {idxHit_lo_hi_hi_hi, idxHit_lo_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_lo_hi = {idxHit_lo_hi_hi, idxHit_lo_hi_lo}; // @[package.scala:45:27] wire [13:0] idxHit_lo = {idxHit_lo_hi, idxHit_lo_lo}; // @[package.scala:45:27] wire [1:0] idxHit_hi_lo_lo_hi = {_idxHit_T_16, _idxHit_T_15}; // @[package.scala:45:27] wire [2:0] idxHit_hi_lo_lo = {idxHit_hi_lo_lo_hi, _idxHit_T_14}; // @[package.scala:45:27] wire [1:0] idxHit_hi_lo_hi_lo = {_idxHit_T_18, _idxHit_T_17}; // @[package.scala:45:27] wire [1:0] idxHit_hi_lo_hi_hi = {_idxHit_T_20, _idxHit_T_19}; // @[package.scala:45:27] wire [3:0] idxHit_hi_lo_hi = {idxHit_hi_lo_hi_hi, idxHit_hi_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_hi_lo = {idxHit_hi_lo_hi, idxHit_hi_lo_lo}; // @[package.scala:45:27] wire [1:0] idxHit_hi_hi_lo_hi = {_idxHit_T_23, _idxHit_T_22}; // @[package.scala:45:27] wire [2:0] idxHit_hi_hi_lo = {idxHit_hi_hi_lo_hi, _idxHit_T_21}; // @[package.scala:45:27] wire [1:0] idxHit_hi_hi_hi_lo = {_idxHit_T_25, _idxHit_T_24}; // @[package.scala:45:27] wire [1:0] idxHit_hi_hi_hi_hi = {_idxHit_T_27, _idxHit_T_26}; // @[package.scala:45:27] wire [3:0] idxHit_hi_hi_hi = {idxHit_hi_hi_hi_hi, idxHit_hi_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_hi_hi = {idxHit_hi_hi_hi, idxHit_hi_hi_lo}; // @[package.scala:45:27] wire [13:0] idxHit_hi = {idxHit_hi_hi, idxHit_hi_lo}; // @[package.scala:45:27] wire [27:0] _idxHit_T_28 = {idxHit_hi, idxHit_lo}; // @[package.scala:45:27] wire [27:0] idxHit = _idxHit_T_28 & isValid; // @[package.scala:45:27] wire [24:0] updatePageHit_p = r_btb_update_bits_pc[38:14]; // @[Valid.scala:135:21] wire [24:0] _samePage_T = r_btb_update_bits_pc[38:14]; // @[Valid.scala:135:21] wire _updatePageHit_T = pages_0 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_1 = pages_1 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_2 = pages_2 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_3 = pages_3 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_4 = pages_4 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_5 = pages_5 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire [1:0] updatePageHit_lo_hi = {_updatePageHit_T_2, _updatePageHit_T_1}; // @[package.scala:45:27] wire [2:0] updatePageHit_lo = {updatePageHit_lo_hi, _updatePageHit_T}; // @[package.scala:45:27] wire [1:0] updatePageHit_hi_hi = {_updatePageHit_T_5, _updatePageHit_T_4}; // @[package.scala:45:27] wire [2:0] updatePageHit_hi = {updatePageHit_hi_hi, _updatePageHit_T_3}; // @[package.scala:45:27] wire [5:0] _updatePageHit_T_6 = {updatePageHit_hi, updatePageHit_lo}; // @[package.scala:45:27] wire [5:0] updatePageHit = pageValid & _updatePageHit_T_6; // @[package.scala:45:27] wire updateHit = r_btb_update_bits_prediction_entry[4:2] != 3'h7; // @[Valid.scala:135:21] wire useUpdatePageHit = |updatePageHit; // @[BTB.scala:214:15, :234:40] wire usePageHit = |pageHit; // @[BTB.scala:214:15, :235:28] wire doIdxPageRepl = ~useUpdatePageHit; // @[BTB.scala:234:40, :236:23] reg [2:0] nextPageRepl; // @[BTB.scala:237:29] wire [4:0] _idxPageRepl_T = pageHit[4:0]; // @[BTB.scala:214:15, :238:32] wire _idxPageRepl_T_1 = pageHit[5]; // @[BTB.scala:214:15, :238:53] wire [5:0] _idxPageRepl_T_2 = {_idxPageRepl_T, _idxPageRepl_T_1}; // @[BTB.scala:238:{24,32,53}] wire [7:0] _idxPageRepl_T_3 = 8'h1 << nextPageRepl; // @[OneHot.scala:58:35] wire [7:0] _idxPageRepl_T_4 = usePageHit ? 8'h0 : _idxPageRepl_T_3; // @[OneHot.scala:58:35] wire [7:0] idxPageRepl = {2'h0, _idxPageRepl_T_2} | _idxPageRepl_T_4; // @[BTB.scala:238:{24,65,70}] wire [7:0] idxPageUpdateOH = useUpdatePageHit ? {2'h0, updatePageHit} : idxPageRepl; // @[BTB.scala:214:15, :234:40, :238:65, :239:28] wire [3:0] idxPageUpdate_hi = idxPageUpdateOH[7:4]; // @[OneHot.scala:30:18] wire [3:0] idxPageUpdate_lo = idxPageUpdateOH[3:0]; // @[OneHot.scala:31:18] wire _idxPageUpdate_T = |idxPageUpdate_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _idxPageUpdate_T_1 = idxPageUpdate_hi | idxPageUpdate_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] idxPageUpdate_hi_1 = _idxPageUpdate_T_1[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] idxPageUpdate_lo_1 = _idxPageUpdate_T_1[1:0]; // @[OneHot.scala:31:18, :32:28] wire _idxPageUpdate_T_2 = |idxPageUpdate_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _idxPageUpdate_T_3 = idxPageUpdate_hi_1 | idxPageUpdate_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _idxPageUpdate_T_4 = _idxPageUpdate_T_3[1]; // @[OneHot.scala:32:28] wire [1:0] _idxPageUpdate_T_5 = {_idxPageUpdate_T_2, _idxPageUpdate_T_4}; // @[OneHot.scala:32:{10,14}] wire [2:0] idxPageUpdate = {_idxPageUpdate_T, _idxPageUpdate_T_5}; // @[OneHot.scala:32:{10,14}] wire [7:0] idxPageReplEn = doIdxPageRepl ? idxPageRepl : 8'h0; // @[BTB.scala:236:23, :238:65, :241:26] wire samePage = _samePage_T == _samePage_T_1; // @[BTB.scala:211:39, :243:45] wire _doTgtPageRepl_T = ~samePage; // @[BTB.scala:243:45, :244:23] wire _doTgtPageRepl_T_1 = ~usePageHit; // @[BTB.scala:235:28, :244:36] wire doTgtPageRepl = _doTgtPageRepl_T & _doTgtPageRepl_T_1; // @[BTB.scala:244:{23,33,36}] wire [4:0] _tgtPageRepl_T = idxPageUpdateOH[4:0]; // @[BTB.scala:239:28, :245:71] wire _tgtPageRepl_T_1 = idxPageUpdateOH[5]; // @[BTB.scala:239:28, :245:100] wire [5:0] _tgtPageRepl_T_2 = {_tgtPageRepl_T, _tgtPageRepl_T_1}; // @[BTB.scala:245:{55,71,100}] wire [7:0] tgtPageRepl = samePage ? idxPageUpdateOH : {2'h0, _tgtPageRepl_T_2}; // @[BTB.scala:239:28, :243:45, :245:{24,55}] wire [7:0] _tgtPageUpdate_T = usePageHit ? 8'h0 : tgtPageRepl; // @[BTB.scala:235:28, :245:24, :246:45] wire [7:0] _tgtPageUpdate_T_1 = {2'h0, pageHit} | _tgtPageUpdate_T; // @[BTB.scala:214:15, :246:{40,45}] wire [3:0] tgtPageUpdate_hi = _tgtPageUpdate_T_1[7:4]; // @[OneHot.scala:30:18] wire [3:0] tgtPageUpdate_lo = _tgtPageUpdate_T_1[3:0]; // @[OneHot.scala:31:18] wire _tgtPageUpdate_T_2 = |tgtPageUpdate_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _tgtPageUpdate_T_3 = tgtPageUpdate_hi | tgtPageUpdate_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] tgtPageUpdate_hi_1 = _tgtPageUpdate_T_3[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] tgtPageUpdate_lo_1 = _tgtPageUpdate_T_3[1:0]; // @[OneHot.scala:31:18, :32:28] wire _tgtPageUpdate_T_4 = |tgtPageUpdate_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _tgtPageUpdate_T_5 = tgtPageUpdate_hi_1 | tgtPageUpdate_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _tgtPageUpdate_T_6 = _tgtPageUpdate_T_5[1]; // @[OneHot.scala:32:28] wire [1:0] _tgtPageUpdate_T_7 = {_tgtPageUpdate_T_4, _tgtPageUpdate_T_6}; // @[OneHot.scala:32:{10,14}] wire [2:0] tgtPageUpdate = {_tgtPageUpdate_T_2, _tgtPageUpdate_T_7}; // @[OneHot.scala:32:{10,14}] wire [7:0] tgtPageReplEn = doTgtPageRepl ? tgtPageRepl : 8'h0; // @[BTB.scala:244:33, :245:24, :247:26] wire both = doIdxPageRepl & doTgtPageRepl; // @[BTB.scala:236:23, :244:33, :250:30] wire [1:0] _next_T = both ? 2'h2 : 2'h1; // @[BTB.scala:250:30, :251:40, :292:33] wire [3:0] _next_T_1 = {1'h0, nextPageRepl} + {2'h0, _next_T}; // @[BTB.scala:237:29, :251:{29,40}] wire [2:0] next = _next_T_1[2:0]; // @[BTB.scala:251:29] wire _nextPageRepl_T = next > 3'h5; // @[BTB.scala:251:29, :252:30] wire _nextPageRepl_T_1 = next[0]; // @[BTB.scala:251:29, :252:47] wire [2:0] _nextPageRepl_T_2 = _nextPageRepl_T ? {2'h0, _nextPageRepl_T_1} : next; // @[BTB.scala:251:29, :252:{24,30,47}] reg [26:0] state_reg; // @[Replacement.scala:168:70] wire waddr_left_subtree_older = state_reg[26]; // @[Replacement.scala:168:70, :243:38] wire [10:0] waddr_left_subtree_state = state_reg[25:15]; // @[package.scala:163:13] wire [10:0] state_reg_left_subtree_state = state_reg[25:15]; // @[package.scala:163:13] wire [14:0] waddr_right_subtree_state = state_reg[14:0]; // @[Replacement.scala:168:70, :245:38] wire [14:0] state_reg_right_subtree_state = state_reg[14:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire waddr_left_subtree_older_1 = waddr_left_subtree_state[10]; // @[package.scala:163:13] wire [2:0] waddr_left_subtree_state_1 = waddr_left_subtree_state[9:7]; // @[package.scala:163:13] wire [6:0] waddr_right_subtree_state_1 = waddr_left_subtree_state[6:0]; // @[package.scala:163:13] wire waddr_left_subtree_older_2 = waddr_left_subtree_state_1[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_2 = waddr_left_subtree_state_1[1]; // @[package.scala:163:13] wire _waddr_T = waddr_left_subtree_state_2; // @[package.scala:163:13] wire waddr_right_subtree_state_2 = waddr_left_subtree_state_1[0]; // @[package.scala:163:13] wire _waddr_T_1 = waddr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_2 = waddr_left_subtree_older_2 ? _waddr_T : _waddr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_3 = {waddr_left_subtree_older_2, _waddr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_3 = waddr_right_subtree_state_1[6]; // @[Replacement.scala:243:38, :245:38] wire [2:0] waddr_left_subtree_state_3 = waddr_right_subtree_state_1[5:3]; // @[package.scala:163:13] wire [2:0] waddr_right_subtree_state_3 = waddr_right_subtree_state_1[2:0]; // @[Replacement.scala:245:38] wire waddr_left_subtree_older_4 = waddr_left_subtree_state_3[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_4 = waddr_left_subtree_state_3[1]; // @[package.scala:163:13] wire _waddr_T_4 = waddr_left_subtree_state_4; // @[package.scala:163:13] wire waddr_right_subtree_state_4 = waddr_left_subtree_state_3[0]; // @[package.scala:163:13] wire _waddr_T_5 = waddr_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_6 = waddr_left_subtree_older_4 ? _waddr_T_4 : _waddr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_7 = {waddr_left_subtree_older_4, _waddr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_5 = waddr_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38] wire waddr_left_subtree_state_5 = waddr_right_subtree_state_3[1]; // @[package.scala:163:13] wire _waddr_T_8 = waddr_left_subtree_state_5; // @[package.scala:163:13] wire waddr_right_subtree_state_5 = waddr_right_subtree_state_3[0]; // @[Replacement.scala:245:38] wire _waddr_T_9 = waddr_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_10 = waddr_left_subtree_older_5 ? _waddr_T_8 : _waddr_T_9; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_11 = {waddr_left_subtree_older_5, _waddr_T_10}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _waddr_T_12 = waddr_left_subtree_older_3 ? _waddr_T_7 : _waddr_T_11; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_13 = {waddr_left_subtree_older_3, _waddr_T_12}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_14 = waddr_left_subtree_older_1 ? {1'h0, _waddr_T_3} : _waddr_T_13; // @[Replacement.scala:243:38, :249:12, :250:16] wire [3:0] _waddr_T_15 = {waddr_left_subtree_older_1, _waddr_T_14}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_6 = waddr_right_subtree_state[14]; // @[Replacement.scala:243:38, :245:38] wire [6:0] waddr_left_subtree_state_6 = waddr_right_subtree_state[13:7]; // @[package.scala:163:13] wire [6:0] waddr_right_subtree_state_6 = waddr_right_subtree_state[6:0]; // @[Replacement.scala:245:38] wire waddr_left_subtree_older_7 = waddr_left_subtree_state_6[6]; // @[package.scala:163:13] wire [2:0] waddr_left_subtree_state_7 = waddr_left_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] waddr_right_subtree_state_7 = waddr_left_subtree_state_6[2:0]; // @[package.scala:163:13] wire waddr_left_subtree_older_8 = waddr_left_subtree_state_7[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_8 = waddr_left_subtree_state_7[1]; // @[package.scala:163:13] wire _waddr_T_16 = waddr_left_subtree_state_8; // @[package.scala:163:13] wire waddr_right_subtree_state_8 = waddr_left_subtree_state_7[0]; // @[package.scala:163:13] wire _waddr_T_17 = waddr_right_subtree_state_8; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_18 = waddr_left_subtree_older_8 ? _waddr_T_16 : _waddr_T_17; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_19 = {waddr_left_subtree_older_8, _waddr_T_18}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_9 = waddr_right_subtree_state_7[2]; // @[Replacement.scala:243:38, :245:38] wire waddr_left_subtree_state_9 = waddr_right_subtree_state_7[1]; // @[package.scala:163:13] wire _waddr_T_20 = waddr_left_subtree_state_9; // @[package.scala:163:13] wire waddr_right_subtree_state_9 = waddr_right_subtree_state_7[0]; // @[Replacement.scala:245:38] wire _waddr_T_21 = waddr_right_subtree_state_9; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_22 = waddr_left_subtree_older_9 ? _waddr_T_20 : _waddr_T_21; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_23 = {waddr_left_subtree_older_9, _waddr_T_22}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _waddr_T_24 = waddr_left_subtree_older_7 ? _waddr_T_19 : _waddr_T_23; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_25 = {waddr_left_subtree_older_7, _waddr_T_24}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_10 = waddr_right_subtree_state_6[6]; // @[Replacement.scala:243:38, :245:38] wire [2:0] waddr_left_subtree_state_10 = waddr_right_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] waddr_right_subtree_state_10 = waddr_right_subtree_state_6[2:0]; // @[Replacement.scala:245:38] wire waddr_left_subtree_older_11 = waddr_left_subtree_state_10[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_11 = waddr_left_subtree_state_10[1]; // @[package.scala:163:13] wire _waddr_T_26 = waddr_left_subtree_state_11; // @[package.scala:163:13] wire waddr_right_subtree_state_11 = waddr_left_subtree_state_10[0]; // @[package.scala:163:13] wire _waddr_T_27 = waddr_right_subtree_state_11; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_28 = waddr_left_subtree_older_11 ? _waddr_T_26 : _waddr_T_27; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_29 = {waddr_left_subtree_older_11, _waddr_T_28}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_12 = waddr_right_subtree_state_10[2]; // @[Replacement.scala:243:38, :245:38] wire waddr_left_subtree_state_12 = waddr_right_subtree_state_10[1]; // @[package.scala:163:13] wire _waddr_T_30 = waddr_left_subtree_state_12; // @[package.scala:163:13] wire waddr_right_subtree_state_12 = waddr_right_subtree_state_10[0]; // @[Replacement.scala:245:38] wire _waddr_T_31 = waddr_right_subtree_state_12; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_32 = waddr_left_subtree_older_12 ? _waddr_T_30 : _waddr_T_31; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_33 = {waddr_left_subtree_older_12, _waddr_T_32}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _waddr_T_34 = waddr_left_subtree_older_10 ? _waddr_T_29 : _waddr_T_33; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_35 = {waddr_left_subtree_older_10, _waddr_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_36 = waddr_left_subtree_older_6 ? _waddr_T_25 : _waddr_T_35; // @[Replacement.scala:243:38, :249:12, :250:16] wire [3:0] _waddr_T_37 = {waddr_left_subtree_older_6, _waddr_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [3:0] _waddr_T_38 = waddr_left_subtree_older ? _waddr_T_15 : _waddr_T_37; // @[Replacement.scala:243:38, :249:12, :250:16] wire [4:0] _waddr_T_39 = {waddr_left_subtree_older, _waddr_T_38}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [4:0] waddr = updateHit ? r_btb_update_bits_prediction_entry : _waddr_T_39; // @[Valid.scala:135:21] reg r_resp_pipe_v; // @[Valid.scala:141:24] wire r_resp_valid = r_resp_pipe_v; // @[Valid.scala:135:21, :141:24] reg [1:0] r_resp_pipe_b_cfiType; // @[Valid.scala:142:26] wire [1:0] r_resp_bits_cfiType = r_resp_pipe_b_cfiType; // @[Valid.scala:135:21, :142:26] reg r_resp_pipe_b_taken; // @[Valid.scala:142:26] wire r_resp_bits_taken = r_resp_pipe_b_taken; // @[Valid.scala:135:21, :142:26] reg [1:0] r_resp_pipe_b_mask; // @[Valid.scala:142:26] wire [1:0] r_resp_bits_mask = r_resp_pipe_b_mask; // @[Valid.scala:135:21, :142:26] reg r_resp_pipe_b_bridx; // @[Valid.scala:142:26] wire r_resp_bits_bridx = r_resp_pipe_b_bridx; // @[Valid.scala:135:21, :142:26] reg [38:0] r_resp_pipe_b_target; // @[Valid.scala:142:26] wire [38:0] r_resp_bits_target = r_resp_pipe_b_target; // @[Valid.scala:135:21, :142:26] reg [4:0] r_resp_pipe_b_entry; // @[Valid.scala:142:26] wire [4:0] r_resp_bits_entry = r_resp_pipe_b_entry; // @[Valid.scala:135:21, :142:26] reg [7:0] r_resp_pipe_b_bht_history; // @[Valid.scala:142:26] wire [7:0] r_resp_bits_bht_history = r_resp_pipe_b_bht_history; // @[Valid.scala:135:21, :142:26] reg r_resp_pipe_b_bht_value; // @[Valid.scala:142:26] wire r_resp_bits_bht_value = r_resp_pipe_b_bht_value; // @[Valid.scala:135:21, :142:26] wire [4:0] state_reg_touch_way_sized = r_btb_update_valid ? waddr : r_resp_bits_entry; // @[Valid.scala:135:21] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[4]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [3:0] _state_reg_T = state_reg_touch_way_sized[3:0]; // @[package.scala:163:13] wire [3:0] _state_reg_T_39 = state_reg_touch_way_sized[3:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_1 = _state_reg_T[3]; // @[package.scala:163:13] wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_1 = state_reg_left_subtree_state[9:7]; // @[package.scala:163:13] wire [6:0] state_reg_right_subtree_state_1 = state_reg_left_subtree_state[6:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_1 = _state_reg_T[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_2 = _state_reg_T_1[1]; // @[package.scala:163:13] wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_2 = state_reg_left_subtree_state_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_2 = state_reg_left_subtree_state_1[0]; // @[package.scala:163:13] wire _state_reg_T_2 = _state_reg_T_1[0]; // @[package.scala:163:13] wire _state_reg_T_6 = _state_reg_T_1[0]; // @[package.scala:163:13] wire _state_reg_T_3 = _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_4 = ~_state_reg_T_3; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_5 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_4; // @[package.scala:163:13] wire _state_reg_T_7 = _state_reg_T_6; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_8 = ~_state_reg_T_7; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_9 = state_reg_set_left_older_2 ? _state_reg_T_8 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older_2, _state_reg_T_5}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_10 = {state_reg_hi, _state_reg_T_9}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_11 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_10; // @[package.scala:163:13] wire [2:0] _state_reg_T_12 = _state_reg_T[2:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_3 = _state_reg_T_12[2]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_3 = state_reg_right_subtree_state_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state_3 = state_reg_right_subtree_state_1[2:0]; // @[Replacement.scala:198:38] wire [1:0] _state_reg_T_13 = _state_reg_T_12[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_24 = _state_reg_T_12[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_4 = _state_reg_T_13[1]; // @[package.scala:163:13] wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13] wire _state_reg_T_14 = _state_reg_T_13[0]; // @[package.scala:163:13] wire _state_reg_T_18 = _state_reg_T_13[0]; // @[package.scala:163:13] wire _state_reg_T_15 = _state_reg_T_14; // @[package.scala:163:13] wire _state_reg_T_16 = ~_state_reg_T_15; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_17 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_16; // @[package.scala:163:13] wire _state_reg_T_19 = _state_reg_T_18; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_20 = ~_state_reg_T_19; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_21 = state_reg_set_left_older_4 ? _state_reg_T_20 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_4, _state_reg_T_17}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_22 = {state_reg_hi_1, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_23 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_22; // @[package.scala:163:13] wire _state_reg_set_left_older_T_5 = _state_reg_T_24[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38] wire _state_reg_T_25 = _state_reg_T_24[0]; // @[package.scala:163:13] wire _state_reg_T_29 = _state_reg_T_24[0]; // @[package.scala:163:13] wire _state_reg_T_26 = _state_reg_T_25; // @[package.scala:163:13] wire _state_reg_T_27 = ~_state_reg_T_26; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_28 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_27; // @[package.scala:163:13] wire _state_reg_T_30 = _state_reg_T_29; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_31 = ~_state_reg_T_30; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_32 = state_reg_set_left_older_5 ? _state_reg_T_31 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_2 = {state_reg_set_left_older_5, _state_reg_T_28}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_33 = {state_reg_hi_2, _state_reg_T_32}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_34 = state_reg_set_left_older_3 ? _state_reg_T_33 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_3 = {state_reg_set_left_older_3, _state_reg_T_23}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_35 = {state_reg_hi_3, _state_reg_T_34}; // @[Replacement.scala:202:12, :206:16] wire [6:0] _state_reg_T_36 = state_reg_set_left_older_1 ? _state_reg_T_35 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_4 = {state_reg_set_left_older_1, _state_reg_T_11}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [10:0] _state_reg_T_37 = {state_reg_hi_4, _state_reg_T_36}; // @[Replacement.scala:202:12, :206:16] wire [10:0] _state_reg_T_38 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_37; // @[package.scala:163:13] wire _state_reg_set_left_older_T_6 = _state_reg_T_39[3]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}] wire [6:0] state_reg_left_subtree_state_6 = state_reg_right_subtree_state[13:7]; // @[package.scala:163:13] wire [6:0] state_reg_right_subtree_state_6 = state_reg_right_subtree_state[6:0]; // @[Replacement.scala:198:38] wire [2:0] _state_reg_T_40 = _state_reg_T_39[2:0]; // @[package.scala:163:13] wire [2:0] _state_reg_T_65 = _state_reg_T_39[2:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_7 = _state_reg_T_40[2]; // @[package.scala:163:13] wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[2:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_41 = _state_reg_T_40[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_52 = _state_reg_T_40[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_8 = _state_reg_T_41[1]; // @[package.scala:163:13] wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_8 = state_reg_left_subtree_state_7[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_8 = state_reg_left_subtree_state_7[0]; // @[package.scala:163:13] wire _state_reg_T_42 = _state_reg_T_41[0]; // @[package.scala:163:13] wire _state_reg_T_46 = _state_reg_T_41[0]; // @[package.scala:163:13] wire _state_reg_T_43 = _state_reg_T_42; // @[package.scala:163:13] wire _state_reg_T_44 = ~_state_reg_T_43; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_45 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_44; // @[package.scala:163:13] wire _state_reg_T_47 = _state_reg_T_46; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_48 = ~_state_reg_T_47; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_49 = state_reg_set_left_older_8 ? _state_reg_T_48 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_5 = {state_reg_set_left_older_8, _state_reg_T_45}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_50 = {state_reg_hi_5, _state_reg_T_49}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_51 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_50; // @[package.scala:163:13] wire _state_reg_set_left_older_T_9 = _state_reg_T_52[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_9 = ~_state_reg_set_left_older_T_9; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_9 = state_reg_right_subtree_state_7[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_9 = state_reg_right_subtree_state_7[0]; // @[Replacement.scala:198:38] wire _state_reg_T_53 = _state_reg_T_52[0]; // @[package.scala:163:13] wire _state_reg_T_57 = _state_reg_T_52[0]; // @[package.scala:163:13] wire _state_reg_T_54 = _state_reg_T_53; // @[package.scala:163:13] wire _state_reg_T_55 = ~_state_reg_T_54; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_56 = state_reg_set_left_older_9 ? state_reg_left_subtree_state_9 : _state_reg_T_55; // @[package.scala:163:13] wire _state_reg_T_58 = _state_reg_T_57; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_59 = ~_state_reg_T_58; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_60 = state_reg_set_left_older_9 ? _state_reg_T_59 : state_reg_right_subtree_state_9; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_9, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_61 = {state_reg_hi_6, _state_reg_T_60}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_62 = state_reg_set_left_older_7 ? _state_reg_T_61 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_7 = {state_reg_set_left_older_7, _state_reg_T_51}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_63 = {state_reg_hi_7, _state_reg_T_62}; // @[Replacement.scala:202:12, :206:16] wire [6:0] _state_reg_T_64 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_63; // @[package.scala:163:13] wire _state_reg_set_left_older_T_10 = _state_reg_T_65[2]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_10 = ~_state_reg_set_left_older_T_10; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_10 = state_reg_right_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state_10 = state_reg_right_subtree_state_6[2:0]; // @[Replacement.scala:198:38] wire [1:0] _state_reg_T_66 = _state_reg_T_65[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_77 = _state_reg_T_65[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_11 = _state_reg_T_66[1]; // @[package.scala:163:13] wire state_reg_set_left_older_11 = ~_state_reg_set_left_older_T_11; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_11 = state_reg_left_subtree_state_10[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_11 = state_reg_left_subtree_state_10[0]; // @[package.scala:163:13] wire _state_reg_T_67 = _state_reg_T_66[0]; // @[package.scala:163:13] wire _state_reg_T_71 = _state_reg_T_66[0]; // @[package.scala:163:13] wire _state_reg_T_68 = _state_reg_T_67; // @[package.scala:163:13] wire _state_reg_T_69 = ~_state_reg_T_68; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_70 = state_reg_set_left_older_11 ? state_reg_left_subtree_state_11 : _state_reg_T_69; // @[package.scala:163:13] wire _state_reg_T_72 = _state_reg_T_71; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_73 = ~_state_reg_T_72; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_74 = state_reg_set_left_older_11 ? _state_reg_T_73 : state_reg_right_subtree_state_11; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_8 = {state_reg_set_left_older_11, _state_reg_T_70}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_75 = {state_reg_hi_8, _state_reg_T_74}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_76 = state_reg_set_left_older_10 ? state_reg_left_subtree_state_10 : _state_reg_T_75; // @[package.scala:163:13] wire _state_reg_set_left_older_T_12 = _state_reg_T_77[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_12 = ~_state_reg_set_left_older_T_12; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_12 = state_reg_right_subtree_state_10[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_12 = state_reg_right_subtree_state_10[0]; // @[Replacement.scala:198:38] wire _state_reg_T_78 = _state_reg_T_77[0]; // @[package.scala:163:13] wire _state_reg_T_82 = _state_reg_T_77[0]; // @[package.scala:163:13] wire _state_reg_T_79 = _state_reg_T_78; // @[package.scala:163:13] wire _state_reg_T_80 = ~_state_reg_T_79; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_81 = state_reg_set_left_older_12 ? state_reg_left_subtree_state_12 : _state_reg_T_80; // @[package.scala:163:13] wire _state_reg_T_83 = _state_reg_T_82; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_84 = ~_state_reg_T_83; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_85 = state_reg_set_left_older_12 ? _state_reg_T_84 : state_reg_right_subtree_state_12; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_9 = {state_reg_set_left_older_12, _state_reg_T_81}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_86 = {state_reg_hi_9, _state_reg_T_85}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_87 = state_reg_set_left_older_10 ? _state_reg_T_86 : state_reg_right_subtree_state_10; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_10 = {state_reg_set_left_older_10, _state_reg_T_76}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_88 = {state_reg_hi_10, _state_reg_T_87}; // @[Replacement.scala:202:12, :206:16] wire [6:0] _state_reg_T_89 = state_reg_set_left_older_6 ? _state_reg_T_88 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [7:0] state_reg_hi_11 = {state_reg_set_left_older_6, _state_reg_T_64}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [14:0] _state_reg_T_90 = {state_reg_hi_11, _state_reg_T_89}; // @[Replacement.scala:202:12, :206:16] wire [14:0] _state_reg_T_91 = state_reg_set_left_older ? _state_reg_T_90 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [11:0] state_reg_hi_12 = {state_reg_set_left_older, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [26:0] _state_reg_T_92 = {state_reg_hi_12, _state_reg_T_91}; // @[Replacement.scala:202:12, :206:16] wire [31:0] mask = 32'h1 << waddr; // @[OneHot.scala:58:35] wire [12:0] _idxs_T = r_btb_update_bits_pc[13:1]; // @[Valid.scala:135:21] wire [3:0] _idxPages_T = {1'h0, idxPageUpdate} + 4'h1; // @[OneHot.scala:32:10] wire [31:0] _isValid_T = {4'h0, isValid} | mask; // @[OneHot.scala:32:14, :58:35] wire [31:0] _isValid_T_1 = ~mask; // @[OneHot.scala:58:35] wire [31:0] _isValid_T_2 = {4'h0, _isValid_T_1[27:0] & isValid}; // @[OneHot.scala:32:14] wire [31:0] _isValid_T_3 = r_btb_update_bits_isValid ? _isValid_T : _isValid_T_2; // @[Valid.scala:135:21] wire [37:0] _brIdx_T = r_btb_update_bits_br_pc[38:1]; // @[Valid.scala:135:21] wire _idxWritesEven_T = idxPageUpdate[0]; // @[OneHot.scala:32:10] wire idxWritesEven = ~_idxWritesEven_T; // @[BTB.scala:274:{25,39}] wire [7:0] _pageValid_T = {2'h0, pageValid} | tgtPageReplEn; // @[BTB.scala:204:26, :247:26, :284:28] wire [7:0] _pageValid_T_1 = _pageValid_T | idxPageReplEn; // @[BTB.scala:241:26, :284:{28,44}] wire [6:0] _io_resp_valid_T = {pageHit, 1'h0}; // @[BTB.scala:214:15, :287:29] wire _io_resp_valid_T_1 = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_97 = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_valid_T_2 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_1 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_98 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_1 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_1 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_valid_T_3 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_2 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_99 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_2 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_2 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_valid_T_4 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_3 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_100 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_3 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_3 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_valid_T_5 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_4 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_101 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_4 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_4 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_valid_T_6 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_5 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_102 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_5 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_5 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_valid_T_7 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_6 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_103 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_6 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_6 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_valid_T_8 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_7 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_104 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_7 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_7 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_valid_T_9 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_8 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_105 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_8 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_8 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_valid_T_10 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_9 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_106 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_9 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_9 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_valid_T_11 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_10 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_107 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_10 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_10 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_valid_T_12 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_11 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_108 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_11 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_11 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_valid_T_13 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_12 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_109 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_12 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_12 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_valid_T_14 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_13 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_110 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_13 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_13 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_valid_T_15 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_14 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_111 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_14 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_14 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_valid_T_16 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_15 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_112 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_15 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_15 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_valid_T_17 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_16 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_113 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_16 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_16 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_valid_T_18 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_17 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_114 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_17 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_17 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_valid_T_19 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_18 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_115 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_18 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_18 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_valid_T_20 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_19 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_116 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_19 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_19 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_valid_T_21 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_20 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_117 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_20 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_20 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_valid_T_22 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_21 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_118 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_21 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_21 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_valid_T_23 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_22 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_119 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_22 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_22 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_valid_T_24 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_23 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_120 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_23 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_23 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_valid_T_25 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_24 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_121 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_24 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_24 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_valid_T_26 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_25 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_122 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_25 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_25 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_valid_T_27 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_26 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_123 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_26 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_26 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_valid_T_28 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_27 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_124 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_27 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_27 = idxHit[27]; // @[Mux.scala:32:36] wire [2:0] _io_resp_valid_T_29 = _io_resp_valid_T_1 ? idxPages_0 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_30 = _io_resp_valid_T_2 ? idxPages_1 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_31 = _io_resp_valid_T_3 ? idxPages_2 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_32 = _io_resp_valid_T_4 ? idxPages_3 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_33 = _io_resp_valid_T_5 ? idxPages_4 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_34 = _io_resp_valid_T_6 ? idxPages_5 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_35 = _io_resp_valid_T_7 ? idxPages_6 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_36 = _io_resp_valid_T_8 ? idxPages_7 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_37 = _io_resp_valid_T_9 ? idxPages_8 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_38 = _io_resp_valid_T_10 ? idxPages_9 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_39 = _io_resp_valid_T_11 ? idxPages_10 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_40 = _io_resp_valid_T_12 ? idxPages_11 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_41 = _io_resp_valid_T_13 ? idxPages_12 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_42 = _io_resp_valid_T_14 ? idxPages_13 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_43 = _io_resp_valid_T_15 ? idxPages_14 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_44 = _io_resp_valid_T_16 ? idxPages_15 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_45 = _io_resp_valid_T_17 ? idxPages_16 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_46 = _io_resp_valid_T_18 ? idxPages_17 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_47 = _io_resp_valid_T_19 ? idxPages_18 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_48 = _io_resp_valid_T_20 ? idxPages_19 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_49 = _io_resp_valid_T_21 ? idxPages_20 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_50 = _io_resp_valid_T_22 ? idxPages_21 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_51 = _io_resp_valid_T_23 ? idxPages_22 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_52 = _io_resp_valid_T_24 ? idxPages_23 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_53 = _io_resp_valid_T_25 ? idxPages_24 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_54 = _io_resp_valid_T_26 ? idxPages_25 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_55 = _io_resp_valid_T_27 ? idxPages_26 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_56 = _io_resp_valid_T_28 ? idxPages_27 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_57 = _io_resp_valid_T_29 | _io_resp_valid_T_30; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_58 = _io_resp_valid_T_57 | _io_resp_valid_T_31; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_59 = _io_resp_valid_T_58 | _io_resp_valid_T_32; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_60 = _io_resp_valid_T_59 | _io_resp_valid_T_33; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_61 = _io_resp_valid_T_60 | _io_resp_valid_T_34; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_62 = _io_resp_valid_T_61 | _io_resp_valid_T_35; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_63 = _io_resp_valid_T_62 | _io_resp_valid_T_36; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_64 = _io_resp_valid_T_63 | _io_resp_valid_T_37; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_65 = _io_resp_valid_T_64 | _io_resp_valid_T_38; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_66 = _io_resp_valid_T_65 | _io_resp_valid_T_39; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_67 = _io_resp_valid_T_66 | _io_resp_valid_T_40; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_68 = _io_resp_valid_T_67 | _io_resp_valid_T_41; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_69 = _io_resp_valid_T_68 | _io_resp_valid_T_42; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_70 = _io_resp_valid_T_69 | _io_resp_valid_T_43; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_71 = _io_resp_valid_T_70 | _io_resp_valid_T_44; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_72 = _io_resp_valid_T_71 | _io_resp_valid_T_45; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_73 = _io_resp_valid_T_72 | _io_resp_valid_T_46; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_74 = _io_resp_valid_T_73 | _io_resp_valid_T_47; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_75 = _io_resp_valid_T_74 | _io_resp_valid_T_48; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_76 = _io_resp_valid_T_75 | _io_resp_valid_T_49; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_77 = _io_resp_valid_T_76 | _io_resp_valid_T_50; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_78 = _io_resp_valid_T_77 | _io_resp_valid_T_51; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_79 = _io_resp_valid_T_78 | _io_resp_valid_T_52; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_80 = _io_resp_valid_T_79 | _io_resp_valid_T_53; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_81 = _io_resp_valid_T_80 | _io_resp_valid_T_54; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_82 = _io_resp_valid_T_81 | _io_resp_valid_T_55; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_83 = _io_resp_valid_T_82 | _io_resp_valid_T_56; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_WIRE = _io_resp_valid_T_83; // @[Mux.scala:30:73] wire [6:0] _io_resp_valid_T_84 = _io_resp_valid_T >> _io_resp_valid_WIRE; // @[Mux.scala:30:73] assign _io_resp_valid_T_85 = _io_resp_valid_T_84[0]; // @[BTB.scala:287:34] assign io_resp_valid_0 = _io_resp_valid_T_85; // @[BTB.scala:187:7, :287:34] wire [2:0] _io_resp_bits_target_T_28 = _io_resp_bits_target_T ? tgtPages_0 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_29 = _io_resp_bits_target_T_1 ? tgtPages_1 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_30 = _io_resp_bits_target_T_2 ? tgtPages_2 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_31 = _io_resp_bits_target_T_3 ? tgtPages_3 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_32 = _io_resp_bits_target_T_4 ? tgtPages_4 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_33 = _io_resp_bits_target_T_5 ? tgtPages_5 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_34 = _io_resp_bits_target_T_6 ? tgtPages_6 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_35 = _io_resp_bits_target_T_7 ? tgtPages_7 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_36 = _io_resp_bits_target_T_8 ? tgtPages_8 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_37 = _io_resp_bits_target_T_9 ? tgtPages_9 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_38 = _io_resp_bits_target_T_10 ? tgtPages_10 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_39 = _io_resp_bits_target_T_11 ? tgtPages_11 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_40 = _io_resp_bits_target_T_12 ? tgtPages_12 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_41 = _io_resp_bits_target_T_13 ? tgtPages_13 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_42 = _io_resp_bits_target_T_14 ? tgtPages_14 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_43 = _io_resp_bits_target_T_15 ? tgtPages_15 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_44 = _io_resp_bits_target_T_16 ? tgtPages_16 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_45 = _io_resp_bits_target_T_17 ? tgtPages_17 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_46 = _io_resp_bits_target_T_18 ? tgtPages_18 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_47 = _io_resp_bits_target_T_19 ? tgtPages_19 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_48 = _io_resp_bits_target_T_20 ? tgtPages_20 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_49 = _io_resp_bits_target_T_21 ? tgtPages_21 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_50 = _io_resp_bits_target_T_22 ? tgtPages_22 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_51 = _io_resp_bits_target_T_23 ? tgtPages_23 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_52 = _io_resp_bits_target_T_24 ? tgtPages_24 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_53 = _io_resp_bits_target_T_25 ? tgtPages_25 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_54 = _io_resp_bits_target_T_26 ? tgtPages_26 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_55 = _io_resp_bits_target_T_27 ? tgtPages_27 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_56 = _io_resp_bits_target_T_28 | _io_resp_bits_target_T_29; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_57 = _io_resp_bits_target_T_56 | _io_resp_bits_target_T_30; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_58 = _io_resp_bits_target_T_57 | _io_resp_bits_target_T_31; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_59 = _io_resp_bits_target_T_58 | _io_resp_bits_target_T_32; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_60 = _io_resp_bits_target_T_59 | _io_resp_bits_target_T_33; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_61 = _io_resp_bits_target_T_60 | _io_resp_bits_target_T_34; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_62 = _io_resp_bits_target_T_61 | _io_resp_bits_target_T_35; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_63 = _io_resp_bits_target_T_62 | _io_resp_bits_target_T_36; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_64 = _io_resp_bits_target_T_63 | _io_resp_bits_target_T_37; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_65 = _io_resp_bits_target_T_64 | _io_resp_bits_target_T_38; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_66 = _io_resp_bits_target_T_65 | _io_resp_bits_target_T_39; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_67 = _io_resp_bits_target_T_66 | _io_resp_bits_target_T_40; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_68 = _io_resp_bits_target_T_67 | _io_resp_bits_target_T_41; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_69 = _io_resp_bits_target_T_68 | _io_resp_bits_target_T_42; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_70 = _io_resp_bits_target_T_69 | _io_resp_bits_target_T_43; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_71 = _io_resp_bits_target_T_70 | _io_resp_bits_target_T_44; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_72 = _io_resp_bits_target_T_71 | _io_resp_bits_target_T_45; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_73 = _io_resp_bits_target_T_72 | _io_resp_bits_target_T_46; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_74 = _io_resp_bits_target_T_73 | _io_resp_bits_target_T_47; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_75 = _io_resp_bits_target_T_74 | _io_resp_bits_target_T_48; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_76 = _io_resp_bits_target_T_75 | _io_resp_bits_target_T_49; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_77 = _io_resp_bits_target_T_76 | _io_resp_bits_target_T_50; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_78 = _io_resp_bits_target_T_77 | _io_resp_bits_target_T_51; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_79 = _io_resp_bits_target_T_78 | _io_resp_bits_target_T_52; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_80 = _io_resp_bits_target_T_79 | _io_resp_bits_target_T_53; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_81 = _io_resp_bits_target_T_80 | _io_resp_bits_target_T_54; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_82 = _io_resp_bits_target_T_81 | _io_resp_bits_target_T_55; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_WIRE = _io_resp_bits_target_T_82; // @[Mux.scala:30:73] wire _io_resp_bits_target_T_83 = _io_resp_bits_target_WIRE == 3'h1; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_84 = _io_resp_bits_target_T_83 ? pagesMasked_1 : pagesMasked_0; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_85 = _io_resp_bits_target_WIRE == 3'h2; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_86 = _io_resp_bits_target_T_85 ? pagesMasked_2 : _io_resp_bits_target_T_84; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_87 = _io_resp_bits_target_WIRE == 3'h3; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_88 = _io_resp_bits_target_T_87 ? pagesMasked_3 : _io_resp_bits_target_T_86; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_89 = _io_resp_bits_target_WIRE == 3'h4; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_90 = _io_resp_bits_target_T_89 ? pagesMasked_4 : _io_resp_bits_target_T_88; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_91 = _io_resp_bits_target_WIRE == 3'h5; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_92 = _io_resp_bits_target_T_91 ? pagesMasked_5 : _io_resp_bits_target_T_90; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_93 = _io_resp_bits_target_WIRE == 3'h6; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_94 = _io_resp_bits_target_T_93 ? pagesMasked_4 : _io_resp_bits_target_T_92; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_95 = &_io_resp_bits_target_WIRE; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_96 = _io_resp_bits_target_T_95 ? pagesMasked_5 : _io_resp_bits_target_T_94; // @[package.scala:39:{76,86}] wire [12:0] _io_resp_bits_target_T_125 = _io_resp_bits_target_T_97 ? tgts_0 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_126 = _io_resp_bits_target_T_98 ? tgts_1 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_127 = _io_resp_bits_target_T_99 ? tgts_2 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_128 = _io_resp_bits_target_T_100 ? tgts_3 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_129 = _io_resp_bits_target_T_101 ? tgts_4 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_130 = _io_resp_bits_target_T_102 ? tgts_5 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_131 = _io_resp_bits_target_T_103 ? tgts_6 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_132 = _io_resp_bits_target_T_104 ? tgts_7 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_133 = _io_resp_bits_target_T_105 ? tgts_8 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_134 = _io_resp_bits_target_T_106 ? tgts_9 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_135 = _io_resp_bits_target_T_107 ? tgts_10 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_136 = _io_resp_bits_target_T_108 ? tgts_11 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_137 = _io_resp_bits_target_T_109 ? tgts_12 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_138 = _io_resp_bits_target_T_110 ? tgts_13 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_139 = _io_resp_bits_target_T_111 ? tgts_14 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_140 = _io_resp_bits_target_T_112 ? tgts_15 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_141 = _io_resp_bits_target_T_113 ? tgts_16 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_142 = _io_resp_bits_target_T_114 ? tgts_17 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_143 = _io_resp_bits_target_T_115 ? tgts_18 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_144 = _io_resp_bits_target_T_116 ? tgts_19 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_145 = _io_resp_bits_target_T_117 ? tgts_20 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_146 = _io_resp_bits_target_T_118 ? tgts_21 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_147 = _io_resp_bits_target_T_119 ? tgts_22 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_148 = _io_resp_bits_target_T_120 ? tgts_23 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_149 = _io_resp_bits_target_T_121 ? tgts_24 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_150 = _io_resp_bits_target_T_122 ? tgts_25 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_151 = _io_resp_bits_target_T_123 ? tgts_26 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_152 = _io_resp_bits_target_T_124 ? tgts_27 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_153 = _io_resp_bits_target_T_125 | _io_resp_bits_target_T_126; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_154 = _io_resp_bits_target_T_153 | _io_resp_bits_target_T_127; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_155 = _io_resp_bits_target_T_154 | _io_resp_bits_target_T_128; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_156 = _io_resp_bits_target_T_155 | _io_resp_bits_target_T_129; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_157 = _io_resp_bits_target_T_156 | _io_resp_bits_target_T_130; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_158 = _io_resp_bits_target_T_157 | _io_resp_bits_target_T_131; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_159 = _io_resp_bits_target_T_158 | _io_resp_bits_target_T_132; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_160 = _io_resp_bits_target_T_159 | _io_resp_bits_target_T_133; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_161 = _io_resp_bits_target_T_160 | _io_resp_bits_target_T_134; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_162 = _io_resp_bits_target_T_161 | _io_resp_bits_target_T_135; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_163 = _io_resp_bits_target_T_162 | _io_resp_bits_target_T_136; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_164 = _io_resp_bits_target_T_163 | _io_resp_bits_target_T_137; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_165 = _io_resp_bits_target_T_164 | _io_resp_bits_target_T_138; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_166 = _io_resp_bits_target_T_165 | _io_resp_bits_target_T_139; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_167 = _io_resp_bits_target_T_166 | _io_resp_bits_target_T_140; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_168 = _io_resp_bits_target_T_167 | _io_resp_bits_target_T_141; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_169 = _io_resp_bits_target_T_168 | _io_resp_bits_target_T_142; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_170 = _io_resp_bits_target_T_169 | _io_resp_bits_target_T_143; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_171 = _io_resp_bits_target_T_170 | _io_resp_bits_target_T_144; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_172 = _io_resp_bits_target_T_171 | _io_resp_bits_target_T_145; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_173 = _io_resp_bits_target_T_172 | _io_resp_bits_target_T_146; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_174 = _io_resp_bits_target_T_173 | _io_resp_bits_target_T_147; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_175 = _io_resp_bits_target_T_174 | _io_resp_bits_target_T_148; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_176 = _io_resp_bits_target_T_175 | _io_resp_bits_target_T_149; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_177 = _io_resp_bits_target_T_176 | _io_resp_bits_target_T_150; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_178 = _io_resp_bits_target_T_177 | _io_resp_bits_target_T_151; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_179 = _io_resp_bits_target_T_178 | _io_resp_bits_target_T_152; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_WIRE_1 = _io_resp_bits_target_T_179; // @[Mux.scala:30:73] wire [13:0] _io_resp_bits_target_T_180 = {_io_resp_bits_target_WIRE_1, 1'h0}; // @[Mux.scala:30:73] wire [38:0] _io_resp_bits_target_T_181 = {_io_resp_bits_target_T_96, _io_resp_bits_target_T_180}; // @[package.scala:39:76] wire [11:0] io_resp_bits_entry_hi = idxHit[27:16]; // @[OneHot.scala:30:18] wire [15:0] io_resp_bits_entry_lo = idxHit[15:0]; // @[OneHot.scala:31:18] wire _io_resp_bits_entry_T = |io_resp_bits_entry_hi; // @[OneHot.scala:30:18, :32:14] wire [15:0] _io_resp_bits_entry_T_1 = {4'h0, io_resp_bits_entry_hi} | io_resp_bits_entry_lo; // @[OneHot.scala:30:18, :31:18, :32:{14,28}] wire [7:0] io_resp_bits_entry_hi_1 = _io_resp_bits_entry_T_1[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] io_resp_bits_entry_lo_1 = _io_resp_bits_entry_T_1[7:0]; // @[OneHot.scala:31:18, :32:28] wire _io_resp_bits_entry_T_2 = |io_resp_bits_entry_hi_1; // @[OneHot.scala:30:18, :32:14] wire [7:0] _io_resp_bits_entry_T_3 = io_resp_bits_entry_hi_1 | io_resp_bits_entry_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] io_resp_bits_entry_hi_2 = _io_resp_bits_entry_T_3[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] io_resp_bits_entry_lo_2 = _io_resp_bits_entry_T_3[3:0]; // @[OneHot.scala:31:18, :32:28] wire _io_resp_bits_entry_T_4 = |io_resp_bits_entry_hi_2; // @[OneHot.scala:30:18, :32:14] wire [3:0] _io_resp_bits_entry_T_5 = io_resp_bits_entry_hi_2 | io_resp_bits_entry_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] io_resp_bits_entry_hi_3 = _io_resp_bits_entry_T_5[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] io_resp_bits_entry_lo_3 = _io_resp_bits_entry_T_5[1:0]; // @[OneHot.scala:31:18, :32:28] wire _io_resp_bits_entry_T_6 = |io_resp_bits_entry_hi_3; // @[OneHot.scala:30:18, :32:14] wire [1:0] _io_resp_bits_entry_T_7 = io_resp_bits_entry_hi_3 | io_resp_bits_entry_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire _io_resp_bits_entry_T_8 = _io_resp_bits_entry_T_7[1]; // @[OneHot.scala:32:28] wire [1:0] _io_resp_bits_entry_T_9 = {_io_resp_bits_entry_T_6, _io_resp_bits_entry_T_8}; // @[OneHot.scala:32:{10,14}] wire [2:0] _io_resp_bits_entry_T_10 = {_io_resp_bits_entry_T_4, _io_resp_bits_entry_T_9}; // @[OneHot.scala:32:{10,14}] wire [3:0] _io_resp_bits_entry_T_11 = {_io_resp_bits_entry_T_2, _io_resp_bits_entry_T_10}; // @[OneHot.scala:32:{10,14}] assign _io_resp_bits_entry_T_12 = {_io_resp_bits_entry_T, _io_resp_bits_entry_T_11}; // @[OneHot.scala:32:{10,14}] assign io_resp_bits_entry_0 = _io_resp_bits_entry_T_12; // @[OneHot.scala:32:10] wire _io_resp_bits_bridx_T_28 = _io_resp_bits_bridx_T & brIdx_0; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_29 = _io_resp_bits_bridx_T_1 & brIdx_1; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_30 = _io_resp_bits_bridx_T_2 & brIdx_2; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_31 = _io_resp_bits_bridx_T_3 & brIdx_3; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_32 = _io_resp_bits_bridx_T_4 & brIdx_4; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_33 = _io_resp_bits_bridx_T_5 & brIdx_5; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_34 = _io_resp_bits_bridx_T_6 & brIdx_6; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_35 = _io_resp_bits_bridx_T_7 & brIdx_7; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_36 = _io_resp_bits_bridx_T_8 & brIdx_8; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_37 = _io_resp_bits_bridx_T_9 & brIdx_9; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_38 = _io_resp_bits_bridx_T_10 & brIdx_10; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_39 = _io_resp_bits_bridx_T_11 & brIdx_11; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_40 = _io_resp_bits_bridx_T_12 & brIdx_12; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_41 = _io_resp_bits_bridx_T_13 & brIdx_13; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_42 = _io_resp_bits_bridx_T_14 & brIdx_14; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_43 = _io_resp_bits_bridx_T_15 & brIdx_15; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_44 = _io_resp_bits_bridx_T_16 & brIdx_16; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_45 = _io_resp_bits_bridx_T_17 & brIdx_17; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_46 = _io_resp_bits_bridx_T_18 & brIdx_18; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_47 = _io_resp_bits_bridx_T_19 & brIdx_19; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_48 = _io_resp_bits_bridx_T_20 & brIdx_20; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_49 = _io_resp_bits_bridx_T_21 & brIdx_21; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_50 = _io_resp_bits_bridx_T_22 & brIdx_22; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_51 = _io_resp_bits_bridx_T_23 & brIdx_23; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_52 = _io_resp_bits_bridx_T_24 & brIdx_24; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_53 = _io_resp_bits_bridx_T_25 & brIdx_25; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_54 = _io_resp_bits_bridx_T_26 & brIdx_26; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_55 = _io_resp_bits_bridx_T_27 & brIdx_27; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_56 = _io_resp_bits_bridx_T_28 | _io_resp_bits_bridx_T_29; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_57 = _io_resp_bits_bridx_T_56 | _io_resp_bits_bridx_T_30; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_58 = _io_resp_bits_bridx_T_57 | _io_resp_bits_bridx_T_31; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_59 = _io_resp_bits_bridx_T_58 | _io_resp_bits_bridx_T_32; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_60 = _io_resp_bits_bridx_T_59 | _io_resp_bits_bridx_T_33; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_61 = _io_resp_bits_bridx_T_60 | _io_resp_bits_bridx_T_34; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_62 = _io_resp_bits_bridx_T_61 | _io_resp_bits_bridx_T_35; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_63 = _io_resp_bits_bridx_T_62 | _io_resp_bits_bridx_T_36; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_64 = _io_resp_bits_bridx_T_63 | _io_resp_bits_bridx_T_37; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_65 = _io_resp_bits_bridx_T_64 | _io_resp_bits_bridx_T_38; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_66 = _io_resp_bits_bridx_T_65 | _io_resp_bits_bridx_T_39; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_67 = _io_resp_bits_bridx_T_66 | _io_resp_bits_bridx_T_40; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_68 = _io_resp_bits_bridx_T_67 | _io_resp_bits_bridx_T_41; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_69 = _io_resp_bits_bridx_T_68 | _io_resp_bits_bridx_T_42; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_70 = _io_resp_bits_bridx_T_69 | _io_resp_bits_bridx_T_43; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_71 = _io_resp_bits_bridx_T_70 | _io_resp_bits_bridx_T_44; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_72 = _io_resp_bits_bridx_T_71 | _io_resp_bits_bridx_T_45; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_73 = _io_resp_bits_bridx_T_72 | _io_resp_bits_bridx_T_46; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_74 = _io_resp_bits_bridx_T_73 | _io_resp_bits_bridx_T_47; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_75 = _io_resp_bits_bridx_T_74 | _io_resp_bits_bridx_T_48; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_76 = _io_resp_bits_bridx_T_75 | _io_resp_bits_bridx_T_49; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_77 = _io_resp_bits_bridx_T_76 | _io_resp_bits_bridx_T_50; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_78 = _io_resp_bits_bridx_T_77 | _io_resp_bits_bridx_T_51; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_79 = _io_resp_bits_bridx_T_78 | _io_resp_bits_bridx_T_52; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_80 = _io_resp_bits_bridx_T_79 | _io_resp_bits_bridx_T_53; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_81 = _io_resp_bits_bridx_T_80 | _io_resp_bits_bridx_T_54; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_82 = _io_resp_bits_bridx_T_81 | _io_resp_bits_bridx_T_55; // @[Mux.scala:30:73] assign _io_resp_bits_bridx_WIRE = _io_resp_bits_bridx_T_82; // @[Mux.scala:30:73] assign io_resp_bits_bridx_0 = _io_resp_bits_bridx_WIRE; // @[Mux.scala:30:73] wire _io_resp_bits_mask_T = ~io_resp_bits_bridx_0; // @[BTB.scala:187:7, :292:61] wire _io_resp_bits_mask_T_1 = io_resp_bits_taken_0 & _io_resp_bits_mask_T; // @[BTB.scala:187:7, :292:{40,61}] wire _io_resp_bits_mask_T_2 = ~_io_resp_bits_mask_T_1; // @[BTB.scala:292:{36,40}] wire [1:0] _io_resp_bits_mask_T_3 = 2'h1 << _io_resp_bits_mask_T_2; // @[BTB.scala:292:{33,36}] wire [2:0] _io_resp_bits_mask_T_4 = {1'h0, _io_resp_bits_mask_T_3} - 3'h1; // @[BTB.scala:292:{33,87}] wire [1:0] _io_resp_bits_mask_T_5 = _io_resp_bits_mask_T_4[1:0]; // @[BTB.scala:292:87] wire [2:0] _io_resp_bits_mask_T_6 = {_io_resp_bits_mask_T_5, 1'h1}; // @[BTB.scala:187:7, :292:{27,87}] assign io_resp_bits_mask_0 = _io_resp_bits_mask_T_6[1:0]; // @[BTB.scala:187:7, :292:{21,27}] wire [1:0] _io_resp_bits_cfiType_T_28 = _io_resp_bits_cfiType_T ? cfiType_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_29 = _io_resp_bits_cfiType_T_1 ? cfiType_1 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_30 = _io_resp_bits_cfiType_T_2 ? cfiType_2 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_31 = _io_resp_bits_cfiType_T_3 ? cfiType_3 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_32 = _io_resp_bits_cfiType_T_4 ? cfiType_4 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_33 = _io_resp_bits_cfiType_T_5 ? cfiType_5 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_34 = _io_resp_bits_cfiType_T_6 ? cfiType_6 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_35 = _io_resp_bits_cfiType_T_7 ? cfiType_7 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_36 = _io_resp_bits_cfiType_T_8 ? cfiType_8 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_37 = _io_resp_bits_cfiType_T_9 ? cfiType_9 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_38 = _io_resp_bits_cfiType_T_10 ? cfiType_10 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_39 = _io_resp_bits_cfiType_T_11 ? cfiType_11 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_40 = _io_resp_bits_cfiType_T_12 ? cfiType_12 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_41 = _io_resp_bits_cfiType_T_13 ? cfiType_13 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_42 = _io_resp_bits_cfiType_T_14 ? cfiType_14 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_43 = _io_resp_bits_cfiType_T_15 ? cfiType_15 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_44 = _io_resp_bits_cfiType_T_16 ? cfiType_16 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_45 = _io_resp_bits_cfiType_T_17 ? cfiType_17 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_46 = _io_resp_bits_cfiType_T_18 ? cfiType_18 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_47 = _io_resp_bits_cfiType_T_19 ? cfiType_19 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_48 = _io_resp_bits_cfiType_T_20 ? cfiType_20 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_49 = _io_resp_bits_cfiType_T_21 ? cfiType_21 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_50 = _io_resp_bits_cfiType_T_22 ? cfiType_22 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_51 = _io_resp_bits_cfiType_T_23 ? cfiType_23 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_52 = _io_resp_bits_cfiType_T_24 ? cfiType_24 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_53 = _io_resp_bits_cfiType_T_25 ? cfiType_25 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_54 = _io_resp_bits_cfiType_T_26 ? cfiType_26 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_55 = _io_resp_bits_cfiType_T_27 ? cfiType_27 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_56 = _io_resp_bits_cfiType_T_28 | _io_resp_bits_cfiType_T_29; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_57 = _io_resp_bits_cfiType_T_56 | _io_resp_bits_cfiType_T_30; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_58 = _io_resp_bits_cfiType_T_57 | _io_resp_bits_cfiType_T_31; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_59 = _io_resp_bits_cfiType_T_58 | _io_resp_bits_cfiType_T_32; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_60 = _io_resp_bits_cfiType_T_59 | _io_resp_bits_cfiType_T_33; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_61 = _io_resp_bits_cfiType_T_60 | _io_resp_bits_cfiType_T_34; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_62 = _io_resp_bits_cfiType_T_61 | _io_resp_bits_cfiType_T_35; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_63 = _io_resp_bits_cfiType_T_62 | _io_resp_bits_cfiType_T_36; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_64 = _io_resp_bits_cfiType_T_63 | _io_resp_bits_cfiType_T_37; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_65 = _io_resp_bits_cfiType_T_64 | _io_resp_bits_cfiType_T_38; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_66 = _io_resp_bits_cfiType_T_65 | _io_resp_bits_cfiType_T_39; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_67 = _io_resp_bits_cfiType_T_66 | _io_resp_bits_cfiType_T_40; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_68 = _io_resp_bits_cfiType_T_67 | _io_resp_bits_cfiType_T_41; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_69 = _io_resp_bits_cfiType_T_68 | _io_resp_bits_cfiType_T_42; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_70 = _io_resp_bits_cfiType_T_69 | _io_resp_bits_cfiType_T_43; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_71 = _io_resp_bits_cfiType_T_70 | _io_resp_bits_cfiType_T_44; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_72 = _io_resp_bits_cfiType_T_71 | _io_resp_bits_cfiType_T_45; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_73 = _io_resp_bits_cfiType_T_72 | _io_resp_bits_cfiType_T_46; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_74 = _io_resp_bits_cfiType_T_73 | _io_resp_bits_cfiType_T_47; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_75 = _io_resp_bits_cfiType_T_74 | _io_resp_bits_cfiType_T_48; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_76 = _io_resp_bits_cfiType_T_75 | _io_resp_bits_cfiType_T_49; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_77 = _io_resp_bits_cfiType_T_76 | _io_resp_bits_cfiType_T_50; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_78 = _io_resp_bits_cfiType_T_77 | _io_resp_bits_cfiType_T_51; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_79 = _io_resp_bits_cfiType_T_78 | _io_resp_bits_cfiType_T_52; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_80 = _io_resp_bits_cfiType_T_79 | _io_resp_bits_cfiType_T_53; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_81 = _io_resp_bits_cfiType_T_80 | _io_resp_bits_cfiType_T_54; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_82 = _io_resp_bits_cfiType_T_81 | _io_resp_bits_cfiType_T_55; // @[Mux.scala:30:73] assign _io_resp_bits_cfiType_WIRE = _io_resp_bits_cfiType_T_82; // @[Mux.scala:30:73] assign io_resp_bits_cfiType_0 = _io_resp_bits_cfiType_WIRE; // @[Mux.scala:30:73] wire leftOne = idxHit[0]; // @[Misc.scala:178:18, :181:37] wire leftOne_1 = idxHit[1]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne = idxHit[2]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_1 = leftOne_1 | rightOne; // @[Misc.scala:178:18, :183:16] wire rightTwo = leftOne_1 & rightOne; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_2 = leftOne | rightOne_1; // @[Misc.scala:178:18, :183:16] wire leftTwo = rightTwo | leftOne & rightOne_1; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_3 = idxHit[3]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_2 = idxHit[4]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_4 = leftOne_3 | rightOne_2; // @[Misc.scala:178:18, :183:16] wire leftTwo_1 = leftOne_3 & rightOne_2; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_5 = idxHit[5]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_3 = idxHit[6]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_4 = leftOne_5 | rightOne_3; // @[Misc.scala:178:18, :183:16] wire rightTwo_1 = leftOne_5 & rightOne_3; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_5 = leftOne_4 | rightOne_4; // @[Misc.scala:183:16] wire rightTwo_2 = leftTwo_1 | rightTwo_1 | leftOne_4 & rightOne_4; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_6 = leftOne_2 | rightOne_5; // @[Misc.scala:183:16] wire leftTwo_2 = leftTwo | rightTwo_2 | leftOne_2 & rightOne_5; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_7 = idxHit[7]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_8 = idxHit[8]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_6 = idxHit[9]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_7 = leftOne_8 | rightOne_6; // @[Misc.scala:178:18, :183:16] wire rightTwo_3 = leftOne_8 & rightOne_6; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_9 = leftOne_7 | rightOne_7; // @[Misc.scala:178:18, :183:16] wire leftTwo_3 = rightTwo_3 | leftOne_7 & rightOne_7; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_10 = idxHit[10]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_8 = idxHit[11]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_11 = leftOne_10 | rightOne_8; // @[Misc.scala:178:18, :183:16] wire leftTwo_4 = leftOne_10 & rightOne_8; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_12 = idxHit[12]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_9 = idxHit[13]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_10 = leftOne_12 | rightOne_9; // @[Misc.scala:178:18, :183:16] wire rightTwo_4 = leftOne_12 & rightOne_9; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_11 = leftOne_11 | rightOne_10; // @[Misc.scala:183:16] wire rightTwo_5 = leftTwo_4 | rightTwo_4 | leftOne_11 & rightOne_10; // @[Misc.scala:183:{16,37,49,61}] wire rightOne_12 = leftOne_9 | rightOne_11; // @[Misc.scala:183:16] wire rightTwo_6 = leftTwo_3 | rightTwo_5 | leftOne_9 & rightOne_11; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_13 = leftOne_6 | rightOne_12; // @[Misc.scala:183:16] wire leftTwo_5 = leftTwo_2 | rightTwo_6 | leftOne_6 & rightOne_12; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_14 = idxHit[14]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_15 = idxHit[15]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_13 = idxHit[16]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_14 = leftOne_15 | rightOne_13; // @[Misc.scala:178:18, :183:16] wire rightTwo_7 = leftOne_15 & rightOne_13; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_16 = leftOne_14 | rightOne_14; // @[Misc.scala:178:18, :183:16] wire leftTwo_6 = rightTwo_7 | leftOne_14 & rightOne_14; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_17 = idxHit[17]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_15 = idxHit[18]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_18 = leftOne_17 | rightOne_15; // @[Misc.scala:178:18, :183:16] wire leftTwo_7 = leftOne_17 & rightOne_15; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_19 = idxHit[19]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_16 = idxHit[20]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_17 = leftOne_19 | rightOne_16; // @[Misc.scala:178:18, :183:16] wire rightTwo_8 = leftOne_19 & rightOne_16; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_18 = leftOne_18 | rightOne_17; // @[Misc.scala:183:16] wire rightTwo_9 = leftTwo_7 | rightTwo_8 | leftOne_18 & rightOne_17; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_20 = leftOne_16 | rightOne_18; // @[Misc.scala:183:16] wire leftTwo_8 = leftTwo_6 | rightTwo_9 | leftOne_16 & rightOne_18; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_21 = idxHit[21]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_22 = idxHit[22]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_19 = idxHit[23]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_20 = leftOne_22 | rightOne_19; // @[Misc.scala:178:18, :183:16] wire rightTwo_10 = leftOne_22 & rightOne_19; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_23 = leftOne_21 | rightOne_20; // @[Misc.scala:178:18, :183:16] wire leftTwo_9 = rightTwo_10 | leftOne_21 & rightOne_20; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_24 = idxHit[24]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_21 = idxHit[25]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_25 = leftOne_24 | rightOne_21; // @[Misc.scala:178:18, :183:16] wire leftTwo_10 = leftOne_24 & rightOne_21; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_26 = idxHit[26]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_22 = idxHit[27]; // @[Misc.scala:178:18, :182:39] wire rightOne_23 = leftOne_26 | rightOne_22; // @[Misc.scala:178:18, :183:16] wire rightTwo_11 = leftOne_26 & rightOne_22; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_24 = leftOne_25 | rightOne_23; // @[Misc.scala:183:16] wire rightTwo_12 = leftTwo_10 | rightTwo_11 | leftOne_25 & rightOne_23; // @[Misc.scala:183:{16,37,49,61}] wire rightOne_25 = leftOne_23 | rightOne_24; // @[Misc.scala:183:16] wire rightTwo_13 = leftTwo_9 | rightTwo_12 | leftOne_23 & rightOne_24; // @[Misc.scala:183:{16,37,49,61}] wire rightOne_26 = leftOne_20 | rightOne_25; // @[Misc.scala:183:16] wire rightTwo_14 = leftTwo_8 | rightTwo_13 | leftOne_20 & rightOne_25; // @[Misc.scala:183:{16,37,49,61}] wire [27:0] _isValid_T_4 = ~idxHit; // @[BTB.scala:218:32, :297:26] wire [27:0] _isValid_T_5 = isValid & _isValid_T_4; // @[BTB.scala:207:24, :297:{24,26}] reg [7:0] history; // @[BTB.scala:117:24] assign res_history = history; // @[BTB.scala:91:19, :117:24] reg [9:0] reset_waddr; // @[BTB.scala:119:36] wire _resetting_T = reset_waddr[9]; // @[BTB.scala:119:36, :120:39] wire resetting = ~_resetting_T; // @[BTB.scala:120:{27,39}] wire wen; // @[BTB.scala:121:29] wire [9:0] waddr_1; // @[BTB.scala:122:31] wire wdata; // @[BTB.scala:123:31] wire [10:0] _reset_waddr_T = {1'h0, reset_waddr} + 11'h1; // @[BTB.scala:119:36, :124:49] wire [9:0] _reset_waddr_T_1 = _reset_waddr_T[9:0]; // @[BTB.scala:124:49] wire _isBranch_T = cfiType_0 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_1 = cfiType_1 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_2 = cfiType_2 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_3 = cfiType_3 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_4 = cfiType_4 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_5 = cfiType_5 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_6 = cfiType_6 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_7 = cfiType_7 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_8 = cfiType_8 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_9 = cfiType_9 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_10 = cfiType_10 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_11 = cfiType_11 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_12 = cfiType_12 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_13 = cfiType_13 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_14 = cfiType_14 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_15 = cfiType_15 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_16 = cfiType_16 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_17 = cfiType_17 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_18 = cfiType_18 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_19 = cfiType_19 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_20 = cfiType_20 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_21 = cfiType_21 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_22 = cfiType_22 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_23 = cfiType_23 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_24 = cfiType_24 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_25 = cfiType_25 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_26 = cfiType_26 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_27 = cfiType_27 == 2'h0; // @[BTB.scala:208:20, :305:44] wire [1:0] isBranch_lo_lo_lo_hi = {_isBranch_T_2, _isBranch_T_1}; // @[package.scala:45:27] wire [2:0] isBranch_lo_lo_lo = {isBranch_lo_lo_lo_hi, _isBranch_T}; // @[package.scala:45:27] wire [1:0] isBranch_lo_lo_hi_lo = {_isBranch_T_4, _isBranch_T_3}; // @[package.scala:45:27] wire [1:0] isBranch_lo_lo_hi_hi = {_isBranch_T_6, _isBranch_T_5}; // @[package.scala:45:27] wire [3:0] isBranch_lo_lo_hi = {isBranch_lo_lo_hi_hi, isBranch_lo_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_lo_lo = {isBranch_lo_lo_hi, isBranch_lo_lo_lo}; // @[package.scala:45:27] wire [1:0] isBranch_lo_hi_lo_hi = {_isBranch_T_9, _isBranch_T_8}; // @[package.scala:45:27] wire [2:0] isBranch_lo_hi_lo = {isBranch_lo_hi_lo_hi, _isBranch_T_7}; // @[package.scala:45:27] wire [1:0] isBranch_lo_hi_hi_lo = {_isBranch_T_11, _isBranch_T_10}; // @[package.scala:45:27] wire [1:0] isBranch_lo_hi_hi_hi = {_isBranch_T_13, _isBranch_T_12}; // @[package.scala:45:27] wire [3:0] isBranch_lo_hi_hi = {isBranch_lo_hi_hi_hi, isBranch_lo_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_lo_hi = {isBranch_lo_hi_hi, isBranch_lo_hi_lo}; // @[package.scala:45:27] wire [13:0] isBranch_lo = {isBranch_lo_hi, isBranch_lo_lo}; // @[package.scala:45:27] wire [1:0] isBranch_hi_lo_lo_hi = {_isBranch_T_16, _isBranch_T_15}; // @[package.scala:45:27] wire [2:0] isBranch_hi_lo_lo = {isBranch_hi_lo_lo_hi, _isBranch_T_14}; // @[package.scala:45:27] wire [1:0] isBranch_hi_lo_hi_lo = {_isBranch_T_18, _isBranch_T_17}; // @[package.scala:45:27] wire [1:0] isBranch_hi_lo_hi_hi = {_isBranch_T_20, _isBranch_T_19}; // @[package.scala:45:27] wire [3:0] isBranch_hi_lo_hi = {isBranch_hi_lo_hi_hi, isBranch_hi_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_hi_lo = {isBranch_hi_lo_hi, isBranch_hi_lo_lo}; // @[package.scala:45:27] wire [1:0] isBranch_hi_hi_lo_hi = {_isBranch_T_23, _isBranch_T_22}; // @[package.scala:45:27] wire [2:0] isBranch_hi_hi_lo = {isBranch_hi_hi_lo_hi, _isBranch_T_21}; // @[package.scala:45:27] wire [1:0] isBranch_hi_hi_hi_lo = {_isBranch_T_25, _isBranch_T_24}; // @[package.scala:45:27] wire [1:0] isBranch_hi_hi_hi_hi = {_isBranch_T_27, _isBranch_T_26}; // @[package.scala:45:27] wire [3:0] isBranch_hi_hi_hi = {isBranch_hi_hi_hi_hi, isBranch_hi_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_hi_hi = {isBranch_hi_hi_hi, isBranch_hi_hi_lo}; // @[package.scala:45:27] wire [13:0] isBranch_hi = {isBranch_hi_hi, isBranch_hi_lo}; // @[package.scala:45:27] wire [27:0] _isBranch_T_28 = {isBranch_hi, isBranch_lo}; // @[package.scala:45:27] wire [27:0] _isBranch_T_29 = idxHit & _isBranch_T_28; // @[package.scala:45:27] wire isBranch = |_isBranch_T_29; // @[BTB.scala:305:{28,72}] assign io_resp_bits_bht_history_0 = res_history; // @[BTB.scala:91:19, :187:7] wire _res_res_value_T_8; // @[BTB.scala:92:21] assign io_resp_bits_bht_value_0 = res_value; // @[BTB.scala:91:19, :187:7] wire [36:0] res_res_value_hi = io_req_bits_addr_0[38:2]; // @[BTB.scala:85:21, :187:7] wire [8:0] _res_res_value_T = res_res_value_hi[8:0]; // @[BTB.scala:85:21, :86:9] wire [27:0] _res_res_value_T_1 = res_res_value_hi[36:9]; // @[BTB.scala:85:21, :86:48] wire [1:0] _res_res_value_T_2 = _res_res_value_T_1[1:0]; // @[BTB.scala:86:{48,77}] wire [8:0] _res_res_value_T_3 = {_res_res_value_T[8:2], _res_res_value_T[1:0] ^ _res_res_value_T_2}; // @[BTB.scala:86:{9,42,77}] wire [15:0] _res_res_value_T_4 = {8'h0, history} * 16'hDD; // @[BTB.scala:82:12, :117:24] wire [2:0] _res_res_value_T_5 = _res_res_value_T_4[7:5]; // @[BTB.scala:82:{12,19}] wire [8:0] _res_res_value_T_6 = {_res_res_value_T_5, 6'h0}; // @[BTB.scala:82:19, :88:44] wire [8:0] _res_res_value_T_7 = _res_res_value_T_3 ^ _res_res_value_T_6; // @[BTB.scala:86:42, :88:{20,44}] assign _res_res_value_T_8 = ~resetting & _table_ext_R0_data; // @[BTB.scala:92:21, :116:26, :120:27] assign res_value = _res_res_value_T_8; // @[BTB.scala:91:19, :92:21] wire [6:0] _history_T = history[7:1]; // @[BTB.scala:113:35, :117:24] wire [7:0] _history_T_1 = {io_bht_advance_bits_bht_value_0, _history_T}; // @[BTB.scala:113:{19,35}, :187:7] wire _GEN = io_bht_update_valid_0 & io_bht_update_bits_branch_0; // @[BTB.scala:97:9, :121:29, :187:7, :310:32, :311:40] assign wen = _GEN | resetting; // @[BTB.scala:97:9, :120:27, :121:29, :310:32, :311:40] wire [36:0] waddr_hi = io_bht_update_bits_pc_0[38:2]; // @[BTB.scala:85:21, :187:7] wire [8:0] _waddr_T_40 = waddr_hi[8:0]; // @[BTB.scala:85:21, :86:9] wire [27:0] _waddr_T_41 = waddr_hi[36:9]; // @[BTB.scala:85:21, :86:48] wire [1:0] _waddr_T_42 = _waddr_T_41[1:0]; // @[BTB.scala:86:{48,77}] wire [8:0] _waddr_T_43 = {_waddr_T_40[8:2], _waddr_T_40[1:0] ^ _waddr_T_42}; // @[BTB.scala:86:{9,42,77}] wire [15:0] _waddr_T_44 = {8'h0, io_bht_update_bits_prediction_history_0} * 16'hDD; // @[BTB.scala:82:12, :187:7] wire [2:0] _waddr_T_45 = _waddr_T_44[7:5]; // @[BTB.scala:82:{12,19}] wire [8:0] _waddr_T_46 = {_waddr_T_45, 6'h0}; // @[BTB.scala:82:19, :88:44] wire [8:0] _waddr_T_47 = _waddr_T_43 ^ _waddr_T_46; // @[BTB.scala:86:42, :88:{20,44}] assign waddr_1 = io_bht_update_valid_0 & io_bht_update_bits_branch_0 & ~resetting ? {1'h0, _waddr_T_47} : reset_waddr; // @[BTB.scala:88:20, :98:{11,23}, :99:13, :119:36, :120:27, :122:31, :187:7, :310:32, :311:40] assign wdata = _GEN & ~resetting & io_bht_update_bits_taken_0; // @[BTB.scala:97:9, :98:{11,23}, :100:13, :120:27, :121:29, :123:31, :187:7, :310:32, :311:40] wire [6:0] _history_T_2 = io_bht_update_bits_prediction_history_0[7:1]; // @[BTB.scala:110:37, :187:7] wire [7:0] _history_T_3 = {io_bht_update_bits_taken_0, _history_T_2}; // @[BTB.scala:110:{19,37}, :187:7] assign io_resp_bits_taken_0 = ~(~res_value & isBranch); // @[BTB.scala:91:19, :187:7, :288:22, :305:72, :320:{11,22,35,56}] reg [2:0] count; // @[BTB.scala:56:30] reg [2:0] pos; // @[BTB.scala:57:28] reg [38:0] stack_0; // @[BTB.scala:58:26] reg [38:0] stack_1; // @[BTB.scala:58:26] reg [38:0] stack_2; // @[BTB.scala:58:26] reg [38:0] stack_3; // @[BTB.scala:58:26] reg [38:0] stack_4; // @[BTB.scala:58:26] reg [38:0] stack_5; // @[BTB.scala:58:26] wire _doPeek_T = &cfiType_0; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_1 = &cfiType_1; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_2 = &cfiType_2; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_3 = &cfiType_3; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_4 = &cfiType_4; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_5 = &cfiType_5; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_6 = &cfiType_6; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_7 = &cfiType_7; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_8 = &cfiType_8; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_9 = &cfiType_9; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_10 = &cfiType_10; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_11 = &cfiType_11; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_12 = &cfiType_12; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_13 = &cfiType_13; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_14 = &cfiType_14; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_15 = &cfiType_15; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_16 = &cfiType_16; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_17 = &cfiType_17; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_18 = &cfiType_18; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_19 = &cfiType_19; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_20 = &cfiType_20; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_21 = &cfiType_21; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_22 = &cfiType_22; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_23 = &cfiType_23; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_24 = &cfiType_24; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_25 = &cfiType_25; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_26 = &cfiType_26; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_27 = &cfiType_27; // @[BTB.scala:208:20, :326:42] wire [1:0] doPeek_lo_lo_lo_hi = {_doPeek_T_2, _doPeek_T_1}; // @[package.scala:45:27] wire [2:0] doPeek_lo_lo_lo = {doPeek_lo_lo_lo_hi, _doPeek_T}; // @[package.scala:45:27] wire [1:0] doPeek_lo_lo_hi_lo = {_doPeek_T_4, _doPeek_T_3}; // @[package.scala:45:27] wire [1:0] doPeek_lo_lo_hi_hi = {_doPeek_T_6, _doPeek_T_5}; // @[package.scala:45:27] wire [3:0] doPeek_lo_lo_hi = {doPeek_lo_lo_hi_hi, doPeek_lo_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_lo_lo = {doPeek_lo_lo_hi, doPeek_lo_lo_lo}; // @[package.scala:45:27] wire [1:0] doPeek_lo_hi_lo_hi = {_doPeek_T_9, _doPeek_T_8}; // @[package.scala:45:27] wire [2:0] doPeek_lo_hi_lo = {doPeek_lo_hi_lo_hi, _doPeek_T_7}; // @[package.scala:45:27] wire [1:0] doPeek_lo_hi_hi_lo = {_doPeek_T_11, _doPeek_T_10}; // @[package.scala:45:27] wire [1:0] doPeek_lo_hi_hi_hi = {_doPeek_T_13, _doPeek_T_12}; // @[package.scala:45:27] wire [3:0] doPeek_lo_hi_hi = {doPeek_lo_hi_hi_hi, doPeek_lo_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_lo_hi = {doPeek_lo_hi_hi, doPeek_lo_hi_lo}; // @[package.scala:45:27] wire [13:0] doPeek_lo = {doPeek_lo_hi, doPeek_lo_lo}; // @[package.scala:45:27] wire [1:0] doPeek_hi_lo_lo_hi = {_doPeek_T_16, _doPeek_T_15}; // @[package.scala:45:27] wire [2:0] doPeek_hi_lo_lo = {doPeek_hi_lo_lo_hi, _doPeek_T_14}; // @[package.scala:45:27] wire [1:0] doPeek_hi_lo_hi_lo = {_doPeek_T_18, _doPeek_T_17}; // @[package.scala:45:27] wire [1:0] doPeek_hi_lo_hi_hi = {_doPeek_T_20, _doPeek_T_19}; // @[package.scala:45:27] wire [3:0] doPeek_hi_lo_hi = {doPeek_hi_lo_hi_hi, doPeek_hi_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_hi_lo = {doPeek_hi_lo_hi, doPeek_hi_lo_lo}; // @[package.scala:45:27] wire [1:0] doPeek_hi_hi_lo_hi = {_doPeek_T_23, _doPeek_T_22}; // @[package.scala:45:27] wire [2:0] doPeek_hi_hi_lo = {doPeek_hi_hi_lo_hi, _doPeek_T_21}; // @[package.scala:45:27] wire [1:0] doPeek_hi_hi_hi_lo = {_doPeek_T_25, _doPeek_T_24}; // @[package.scala:45:27] wire [1:0] doPeek_hi_hi_hi_hi = {_doPeek_T_27, _doPeek_T_26}; // @[package.scala:45:27] wire [3:0] doPeek_hi_hi_hi = {doPeek_hi_hi_hi_hi, doPeek_hi_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_hi_hi = {doPeek_hi_hi_hi, doPeek_hi_hi_lo}; // @[package.scala:45:27] wire [13:0] doPeek_hi = {doPeek_hi_hi, doPeek_hi_lo}; // @[package.scala:45:27] wire [27:0] _doPeek_T_28 = {doPeek_hi, doPeek_lo}; // @[package.scala:45:27] wire [27:0] _doPeek_T_29 = idxHit & _doPeek_T_28; // @[package.scala:45:27] wire doPeek = |_doPeek_T_29; // @[BTB.scala:326:{26,67}] wire _io_ras_head_valid_T = ~(|count); // @[BTB.scala:54:29, :56:30] assign _io_ras_head_valid_T_1 = ~_io_ras_head_valid_T; // @[BTB.scala:54:29, :327:26] assign io_ras_head_valid_0 = _io_ras_head_valid_T_1; // @[BTB.scala:187:7, :327:26] wire [7:0][38:0] _GEN_0 = {{stack_0}, {stack_0}, {stack_5}, {stack_4}, {stack_3}, {stack_2}, {stack_1}, {stack_0}}; // @[BTB.scala:58:26, :328:22] assign io_ras_head_bits_0 = _GEN_0[pos]; // @[BTB.scala:57:28, :187:7, :328:22] assign io_resp_bits_target_0 = (|count) & doPeek ? io_ras_head_bits_0 : _io_resp_bits_target_T_181; // @[BTB.scala:54:29, :56:30, :187:7, :289:{23,29}, :326:67, :329:{24,35}, :330:27] wire [3:0] _GEN_1 = {1'h0, count}; // @[BTB.scala:43:44, :56:30] wire [3:0] _count_T = _GEN_1 + 4'h1; // @[BTB.scala:43:44] wire [2:0] _count_T_1 = _count_T[2:0]; // @[BTB.scala:43:44] wire _nextPos_T = pos < 3'h5; // @[BTB.scala:44:47, :57:28] wire _nextPos_T_1 = _nextPos_T; // @[BTB.scala:44:{40,47}] wire [3:0] _GEN_2 = {1'h0, pos}; // @[BTB.scala:44:64, :57:28] wire [3:0] _nextPos_T_2 = _GEN_2 + 4'h1; // @[BTB.scala:44:64] wire [2:0] _nextPos_T_3 = _nextPos_T_2[2:0]; // @[BTB.scala:44:64] wire [2:0] nextPos = _nextPos_T_1 ? _nextPos_T_3 : 3'h0; // @[BTB.scala:44:{22,40,64}, :51:40] wire [3:0] _count_T_2 = _GEN_1 - 4'h1; // @[BTB.scala:43:44, :50:20] wire [2:0] _count_T_3 = _count_T_2[2:0]; // @[BTB.scala:50:20] wire _pos_T = |pos; // @[BTB.scala:51:40, :57:28] wire _pos_T_1 = _pos_T; // @[BTB.scala:51:{33,40}] wire [3:0] _pos_T_2 = _GEN_2 - 4'h1; // @[BTB.scala:44:64, :51:50] wire [2:0] _pos_T_3 = _pos_T_2[2:0]; // @[BTB.scala:51:50] wire [2:0] _pos_T_4 = _pos_T_1 ? _pos_T_3 : 3'h5; // @[BTB.scala:51:{15,33,50}] wire [4:0] _T_5 = idxWritesEven ? idxPageReplEn[4:0] : tgtPageReplEn[4:0]; // @[BTB.scala:241:26, :247:26, :274:25, :280:24] wire [24:0] _T_8 = idxWritesEven ? r_btb_update_bits_pc[38:14] : io_req_bits_addr_0[38:14]; // @[Valid.scala:135:21] wire [4:0] _T_12 = idxWritesEven ? tgtPageReplEn[5:1] : idxPageReplEn[5:1]; // @[BTB.scala:241:26, :247:26, :274:25, :282:24] wire [24:0] _T_15 = idxWritesEven ? io_req_bits_addr_0[38:14] : r_btb_update_bits_pc[38:14]; // @[Valid.scala:135:21] wire _T_139 = io_ras_update_bits_cfiType_0 == 2'h2; // @[BTB.scala:187:7, :333:40] always @(posedge clock) begin // @[BTB.scala:187:7] if (r_btb_update_valid & waddr == 5'h0) begin // @[Valid.scala:135:21] idxs_0 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_0 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_0 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_0 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_0 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_0 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h1) begin // @[Valid.scala:135:21] idxs_1 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_1 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_1 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_1 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_1 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_1 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h2) begin // @[Valid.scala:135:21] idxs_2 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_2 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_2 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_2 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_2 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_2 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h3) begin // @[Valid.scala:135:21] idxs_3 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_3 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_3 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_3 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_3 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_3 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h4) begin // @[Valid.scala:135:21] idxs_4 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_4 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_4 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_4 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_4 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_4 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h5) begin // @[Valid.scala:135:21] idxs_5 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_5 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_5 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_5 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_5 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_5 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h6) begin // @[Valid.scala:135:21] idxs_6 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_6 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_6 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_6 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_6 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_6 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h7) begin // @[Valid.scala:135:21] idxs_7 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_7 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_7 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_7 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_7 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_7 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h8) begin // @[Valid.scala:135:21] idxs_8 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_8 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_8 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_8 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_8 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_8 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h9) begin // @[Valid.scala:135:21] idxs_9 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_9 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_9 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_9 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_9 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_9 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hA) begin // @[Valid.scala:135:21] idxs_10 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_10 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_10 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_10 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_10 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_10 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hB) begin // @[Valid.scala:135:21] idxs_11 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_11 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_11 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_11 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_11 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_11 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hC) begin // @[Valid.scala:135:21] idxs_12 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_12 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_12 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_12 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_12 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_12 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hD) begin // @[Valid.scala:135:21] idxs_13 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_13 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_13 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_13 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_13 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_13 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hE) begin // @[Valid.scala:135:21] idxs_14 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_14 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_14 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_14 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_14 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_14 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hF) begin // @[Valid.scala:135:21] idxs_15 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_15 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_15 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_15 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_15 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_15 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h10) begin // @[Valid.scala:135:21] idxs_16 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_16 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_16 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_16 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_16 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_16 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h11) begin // @[Valid.scala:135:21] idxs_17 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_17 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_17 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_17 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_17 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_17 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h12) begin // @[Valid.scala:135:21] idxs_18 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_18 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_18 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_18 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_18 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_18 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h13) begin // @[Valid.scala:135:21] idxs_19 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_19 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_19 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_19 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_19 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_19 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h14) begin // @[Valid.scala:135:21] idxs_20 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_20 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_20 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_20 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_20 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_20 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h15) begin // @[Valid.scala:135:21] idxs_21 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_21 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_21 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_21 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_21 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_21 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h16) begin // @[Valid.scala:135:21] idxs_22 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_22 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_22 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_22 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_22 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_22 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h17) begin // @[Valid.scala:135:21] idxs_23 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_23 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_23 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_23 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_23 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_23 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h18) begin // @[Valid.scala:135:21] idxs_24 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_24 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_24 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_24 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_24 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_24 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h19) begin // @[Valid.scala:135:21] idxs_25 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_25 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_25 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_25 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_25 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_25 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h1A) begin // @[Valid.scala:135:21] idxs_26 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_26 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_26 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_26 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_26 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_26 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h1B) begin // @[Valid.scala:135:21] idxs_27 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_27 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_27 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_27 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_27 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_27 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & _T_5[0]) // @[Valid.scala:135:21] pages_0 <= _T_8; // @[BTB.scala:203:18, :281:10] if (r_btb_update_valid & _T_12[0]) // @[Valid.scala:135:21] pages_1 <= _T_15; // @[BTB.scala:203:18, :283:10] if (r_btb_update_valid & _T_5[2]) // @[Valid.scala:135:21] pages_2 <= _T_8; // @[BTB.scala:203:18, :281:10] if (r_btb_update_valid & _T_12[2]) // @[Valid.scala:135:21] pages_3 <= _T_15; // @[BTB.scala:203:18, :283:10] if (r_btb_update_valid & _T_5[4]) // @[Valid.scala:135:21] pages_4 <= _T_8; // @[BTB.scala:203:18, :281:10] if (r_btb_update_valid & _T_12[4]) // @[Valid.scala:135:21] pages_5 <= _T_15; // @[BTB.scala:203:18, :283:10] if (io_btb_update_valid_0) begin // @[BTB.scala:187:7] r_btb_update_pipe_b_prediction_cfiType <= io_btb_update_bits_prediction_cfiType_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_taken <= io_btb_update_bits_prediction_taken_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_mask <= io_btb_update_bits_prediction_mask_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_bridx <= io_btb_update_bits_prediction_bridx_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_target <= io_btb_update_bits_prediction_target_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_entry <= io_btb_update_bits_prediction_entry_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_bht_history <= io_btb_update_bits_prediction_bht_history_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_bht_value <= io_btb_update_bits_prediction_bht_value_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_pc <= io_btb_update_bits_pc_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_target <= io_btb_update_bits_target_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_isValid <= io_btb_update_bits_isValid_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_br_pc <= io_btb_update_bits_br_pc_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_cfiType <= io_btb_update_bits_cfiType_0; // @[Valid.scala:142:26] end if (io_resp_valid_0) begin // @[BTB.scala:187:7] r_resp_pipe_b_cfiType <= io_resp_bits_cfiType_0; // @[Valid.scala:142:26] r_resp_pipe_b_taken <= io_resp_bits_taken_0; // @[Valid.scala:142:26] r_resp_pipe_b_mask <= io_resp_bits_mask_0; // @[Valid.scala:142:26] r_resp_pipe_b_bridx <= io_resp_bits_bridx_0; // @[Valid.scala:142:26] r_resp_pipe_b_target <= io_resp_bits_target_0; // @[Valid.scala:142:26] r_resp_pipe_b_entry <= io_resp_bits_entry_0; // @[Valid.scala:142:26] r_resp_pipe_b_bht_history <= io_resp_bits_bht_history_0; // @[Valid.scala:142:26] r_resp_pipe_b_bht_value <= io_resp_bits_bht_value_0; // @[Valid.scala:142:26] end if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h0) // @[BTB.scala:44:22, :45:20, :51:40, :58:26, :187:7, :332:32, :333:{40,58}] stack_0 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h1) // @[package.scala:39:86] stack_1 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h2) // @[package.scala:39:86] stack_2 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h3) // @[package.scala:39:86] stack_3 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h4) // @[BTB.scala:44:22, :45:20, :58:26, :187:7, :332:32, :333:{40,58}] stack_4 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h5) // @[BTB.scala:44:22, :45:20, :58:26, :187:7, :332:32, :333:{40,58}] stack_5 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (reset) begin // @[BTB.scala:187:7] pageValid <= 6'h0; // @[BTB.scala:204:26] isValid <= 28'h0; // @[BTB.scala:207:24] r_btb_update_pipe_v <= 1'h0; // @[Valid.scala:141:24] nextPageRepl <= 3'h0; // @[BTB.scala:51:40, :237:29] state_reg <= 27'h0; // @[Replacement.scala:168:70] r_resp_pipe_v <= 1'h0; // @[Valid.scala:141:24] history <= 8'h0; // @[BTB.scala:117:24] reset_waddr <= 10'h0; // @[BTB.scala:119:36] count <= 3'h0; // @[BTB.scala:51:40, :56:30] pos <= 3'h0; // @[BTB.scala:51:40, :57:28] end else begin // @[BTB.scala:187:7] if (r_btb_update_valid) // @[Valid.scala:135:21] pageValid <= _pageValid_T_1[5:0]; // @[BTB.scala:204:26, :284:{15,44}] if (io_flush_0) // @[BTB.scala:187:7] isValid <= 28'h0; // @[BTB.scala:207:24] else if (leftTwo_5 | rightTwo_14 | leftOne_13 & rightOne_26) // @[Misc.scala:183:{16,37,49,61}] isValid <= _isValid_T_5; // @[BTB.scala:207:24, :297:24] else if (r_btb_update_valid) // @[Valid.scala:135:21] isValid <= _isValid_T_3[27:0]; // @[BTB.scala:207:24, :269:{13,19}] r_btb_update_pipe_v <= io_btb_update_valid_0; // @[Valid.scala:141:24] if (r_btb_update_valid & (doIdxPageRepl | doTgtPageRepl)) // @[Valid.scala:135:21] nextPageRepl <= _nextPageRepl_T_2; // @[BTB.scala:237:29, :252:24] if (r_resp_valid & r_resp_bits_taken | r_btb_update_valid) // @[Valid.scala:135:21] state_reg <= _state_reg_T_92; // @[Replacement.scala:168:70, :202:12] r_resp_pipe_v <= io_resp_valid_0; // @[Valid.scala:141:24] if (io_bht_update_valid_0 & io_bht_update_bits_mispredict_0) // @[BTB.scala:187:7, :307:33, :310:32, :311:40] history <= io_bht_update_bits_branch_0 ? _history_T_3 : io_bht_update_bits_prediction_history_0; // @[BTB.scala:107:13, :110:{13,19}, :117:24, :187:7, :307:33, :313:46, :316:50] else if (io_bht_advance_valid_0) // @[BTB.scala:187:7] history <= _history_T_1; // @[BTB.scala:113:19, :117:24] if (resetting) // @[BTB.scala:120:27] reset_waddr <= _reset_waddr_T_1; // @[BTB.scala:119:36, :124:49] if (io_ras_update_valid_0) begin // @[BTB.scala:187:7] if (_T_139) begin // @[BTB.scala:333:40] if (count[2:1] != 2'h3) // @[BTB.scala:43:17, :56:30] count <= _count_T_1; // @[BTB.scala:43:44, :56:30] pos <= nextPos; // @[BTB.scala:44:22, :57:28] end else if ((&io_ras_update_bits_cfiType_0) & (|count)) begin // @[BTB.scala:49:37, :50:11, :54:29, :56:30, :187:7, :335:{46,63}] count <= _count_T_3; // @[BTB.scala:50:20, :56:30] pos <= _pos_T_4; // @[BTB.scala:51:15, :57:28] end end end always @(posedge) table_512x1 table_ext ( // @[BTB.scala:116:26] .R0_addr (_res_res_value_T_7), // @[BTB.scala:88:20] .R0_en (1'h1), // @[BTB.scala:187:7] .R0_clk (clock), .R0_data (_table_ext_R0_data), .W0_addr (waddr_1[8:0]), // @[BTB.scala:122:31, :125:21] .W0_en (wen), // @[BTB.scala:121:29] .W0_clk (clock), .W0_data (wdata) // @[BTB.scala:123:31] ); // @[BTB.scala:116:26] assign io_resp_valid = io_resp_valid_0; // @[BTB.scala:187:7] assign io_resp_bits_cfiType = io_resp_bits_cfiType_0; // @[BTB.scala:187:7] assign io_resp_bits_taken = io_resp_bits_taken_0; // @[BTB.scala:187:7] assign io_resp_bits_mask = io_resp_bits_mask_0; // @[BTB.scala:187:7] assign io_resp_bits_bridx = io_resp_bits_bridx_0; // @[BTB.scala:187:7] assign io_resp_bits_target = io_resp_bits_target_0; // @[BTB.scala:187:7] assign io_resp_bits_entry = io_resp_bits_entry_0; // @[BTB.scala:187:7] assign io_resp_bits_bht_history = io_resp_bits_bht_history_0; // @[BTB.scala:187:7] assign io_resp_bits_bht_value = io_resp_bits_bht_value_0; // @[BTB.scala:187:7] assign io_ras_head_valid = io_ras_head_valid_0; // @[BTB.scala:187:7] assign io_ras_head_bits = io_ras_head_bits_0; // @[BTB.scala:187:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File btb.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} import scala.math.min case class BoomBTBParams( nSets: Int = 128, nWays: Int = 2, offsetSz: Int = 13, extendedNSets: Int = 128 ) class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { override val nSets = params.nSets override val nWays = params.nWays val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1 val offsetSz = params.offsetSz val extendedNSets = params.extendedNSets require(isPow2(nSets)) require(isPow2(extendedNSets) || extendedNSets == 0) require(extendedNSets <= nSets) require(extendedNSets >= 1) class BTBEntry extends Bundle { val offset = SInt(offsetSz.W) val extended = Bool() } val btbEntrySz = offsetSz + 1 class BTBMeta extends Bundle { val is_br = Bool() val tag = UInt(tagSz.W) } val btbMetaSz = tagSz + 1 class BTBPredictMeta extends Bundle { val write_way = UInt(log2Ceil(nWays).W) } val s1_meta = Wire(new BTBPredictMeta) val f3_meta = RegNext(RegNext(s1_meta)) io.f3_meta := f3_meta.asUInt override val metaSz = s1_meta.asUInt.getWidth val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) } val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) } val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W)) val mems = (((0 until nWays) map ({w:Int => Seq( (f"btb_meta_way$w", nSets, bankWidth * btbMetaSz), (f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended))) val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) }) val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) }) val s1_req_rebtb = ebtb.read(s0_idx, s0_valid) val s1_req_tag = s1_idx >> log2Ceil(nSets) val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W)))) val s1_is_br = Wire(Vec(bankWidth, Bool())) val s1_is_jal = Wire(Vec(bankWidth, Bool())) val s1_hit_ohs = VecInit((0 until bankWidth) map { i => VecInit((0 until nWays) map { w => s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0) }) }) val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) } val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) } for (w <- 0 until bankWidth) { val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w) val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w) s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w) s1_resp(w).bits := Mux( entry_btb.extended, s1_req_rebtb, (s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt) s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br io.resp.f2(w) := io.resp_in(0).f2(w) io.resp.f3(w) := io.resp_in(0).f3(w) when (RegNext(s1_hits(w))) { io.resp.f2(w).predicted_pc := RegNext(s1_resp(w)) io.resp.f2(w).is_br := RegNext(s1_is_br(w)) io.resp.f2(w).is_jal := RegNext(s1_is_jal(w)) when (RegNext(s1_is_jal(w))) { io.resp.f2(w).taken := true.B } } when (RegNext(RegNext(s1_hits(w)))) { io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc) io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br) io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal) when (RegNext(RegNext(s1_is_jal(w)))) { io.resp.f3(w).taken := true.B } } } val alloc_way = if (nWays > 1) { val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0)) val l = log2Ceil(nWays) val nChunks = (r_metas.getWidth + l - 1) / l val chunks = (0 until nChunks) map { i => r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l) } chunks.reduce(_^_) } else { 0.U } s1_meta.write_way := Mux(s1_hits.reduce(_||_), PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)), alloc_way) val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta) val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt val new_offset_value = (s1_update.bits.target.asSInt - (s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt) val offset_is_extended = (new_offset_value > max_offset_value || new_offset_value < min_offset_value) val s1_update_wbtb_data = Wire(new BTBEntry) s1_update_wbtb_data.extended := offset_is_extended s1_update_wbtb_data.offset := new_offset_value val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) & Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update)) val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) & (Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) | (Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts) ) ) val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta)) for (w <- 0 until bankWidth) { s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets)) s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w) } for (w <- 0 until nWays) { when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) { btb(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }), VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wbtb_mask).asBools ) meta(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }), VecInit(s1_update_wmeta_data.map(_.asUInt))), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wmeta_mask).asBools ) } } when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) { ebtb.write(s1_update_idx, s1_update.bits.target) } }

module btb_1( // @[btb.scala:66:47] input [6:0] R0_addr, input R0_en, input R0_clk, output [55:0] R0_data, input [6:0] W0_addr, input W0_en, input W0_clk, input [55:0] W0_data, input [3:0] W0_mask ); btb_0_ext btb_0_ext ( // @[btb.scala:66:47] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data), .W0_mask (W0_mask) ); // @[btb.scala:66:47] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }

module NoCMonitor_18( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w1_d3_i0_152( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_272 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w4_d3_i0_34( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_311 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_312 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_313 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_314 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_124( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File INToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val signedIn = Input(Bool()) val in = Input(Bits(intWidth.W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in); val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( intAsRawFloat.expWidth, intWidth, expWidth, sigWidth, flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows )) roundAnyRawFNToRecFN.io.invalidExc := false.B roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := intAsRawFloat roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File rawFloatFromIN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ object rawFloatFromIN { def apply(signedIn: Bool, in: Bits): RawFloat = { val expWidth = log2Up(in.getWidth) + 1 //*** CHANGE THIS; CAN BE VERY LARGE: val extIntWidth = 1<<(expWidth - 1) val sign = signedIn && in(in.getWidth - 1) val absIn = Mux(sign, -in.asUInt, in.asUInt) val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) val adjustedNormDist = countLeadingZeros(extAbsIn) val sig = (extAbsIn<<adjustedNormDist)( extIntWidth - 1, extIntWidth - in.getWidth) val out = Wire(new RawFloat(expWidth, in.getWidth)) out.isNaN := false.B out.isInf := false.B out.isZero := ! sig(in.getWidth - 1) out.sign := sign out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext out.sig := sig out } }

module INToRecFN_i1_e8_s24_4(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_4 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w4_d3_i0_28( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_263 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_264 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_265 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_266 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File TLChannelCompactor.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLBeat(val beatWidth: Int) extends Bundle { val payload = UInt(beatWidth.W) val head = Bool() val tail = Bool() } abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper { override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_") val beatWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val beat = Decoupled(new TLBeat(beatWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) q.io.enq <> io.protocol val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.beat.valid := protocol.valid protocol.ready := io.beat.ready && (is_body || !has_body) io.beat.bits.head := head && !is_body io.beat.bits.tail := tail && (is_body || !has_body) io.beat.bits.payload := Mux(is_body, body, const) when (io.beat.fire && io.beat.bits.head) { is_body := true.B } when (io.beat.fire && io.beat.bits.tail) { is_body := false.B } } abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper { override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_") val beatWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val beat = Flipped(Decoupled(new TLBeat(beatWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) io.protocol <> protocol val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg) io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.beat.bits.payload, body_fields) when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload } when (io.beat.fire && io.beat.bits.tail) { is_const := true.B } } class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) { has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) } class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) { when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) { has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) } class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) { when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) { has_body := edgeIn.hasData(protocol.bits) } class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p) class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) { has_body := edgeOut.hasData(protocol.bits) } class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p) class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) { has_body := edgeIn.hasData(protocol.bits) } class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p) File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLAToBeat_SerialRAM_a64d64s8k8z8c( // @[TLChannelCompactor.scala:108:7] input clock, // @[TLChannelCompactor.scala:108:7] input reset, // @[TLChannelCompactor.scala:108:7] output io_protocol_ready, // @[TLChannelCompactor.scala:40:14] input io_protocol_valid, // @[TLChannelCompactor.scala:40:14] input [2:0] io_protocol_bits_opcode, // @[TLChannelCompactor.scala:40:14] input [2:0] io_protocol_bits_param, // @[TLChannelCompactor.scala:40:14] input [7:0] io_protocol_bits_size, // @[TLChannelCompactor.scala:40:14] input [7:0] io_protocol_bits_source, // @[TLChannelCompactor.scala:40:14] input [63:0] io_protocol_bits_address, // @[TLChannelCompactor.scala:40:14] input [7:0] io_protocol_bits_mask, // @[TLChannelCompactor.scala:40:14] input [63:0] io_protocol_bits_data, // @[TLChannelCompactor.scala:40:14] input io_protocol_bits_corrupt, // @[TLChannelCompactor.scala:40:14] input io_beat_ready, // @[TLChannelCompactor.scala:40:14] output io_beat_valid, // @[TLChannelCompactor.scala:40:14] output [85:0] io_beat_bits_payload, // @[TLChannelCompactor.scala:40:14] output io_beat_bits_head, // @[TLChannelCompactor.scala:40:14] output io_beat_bits_tail // @[TLChannelCompactor.scala:40:14] ); wire [8:0] _GEN; // @[TLChannelCompactor.scala:109:{45,69}] wire _q_io_deq_valid; // @[TLChannelCompactor.scala:47:17] wire [2:0] _q_io_deq_bits_opcode; // @[TLChannelCompactor.scala:47:17] wire [2:0] _q_io_deq_bits_param; // @[TLChannelCompactor.scala:47:17] wire [7:0] _q_io_deq_bits_size; // @[TLChannelCompactor.scala:47:17] wire [7:0] _q_io_deq_bits_source; // @[TLChannelCompactor.scala:47:17] wire [63:0] _q_io_deq_bits_address; // @[TLChannelCompactor.scala:47:17] wire [7:0] _q_io_deq_bits_mask; // @[TLChannelCompactor.scala:47:17] wire [63:0] _q_io_deq_bits_data; // @[TLChannelCompactor.scala:47:17] wire _q_io_deq_bits_corrupt; // @[TLChannelCompactor.scala:47:17] wire [266:0] _tail_beats1_decode_T = 267'hFFF << _q_io_deq_bits_size; // @[TLChannelCompactor.scala:47:17] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3]); // @[TLChannelCompactor.scala:47:17] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TLChannelCompactor.scala:60:24] wire _io_beat_bits_tail_T = _GEN == 9'h0; // @[TLChannelCompactor.scala:109:{45,69}] wire q_io_deq_ready = io_beat_ready & (is_body | _io_beat_bits_tail_T); // @[TLChannelCompactor.scala:60:24, :62:{35,47}, :109:{45,69}] wire io_beat_bits_head_0 = head & ~is_body; // @[TLChannelCompactor.scala:60:24, :64:{35,38}] wire io_beat_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | _io_beat_bits_tail_T); // @[TLChannelCompactor.scala:60:24, :65:{35,47}, :109:{45,69}] assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[TLChannelCompactor.scala:47:17, :109:{45,49,69}] wire _GEN_0 = io_beat_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TLChannelCompactor.scala:108:7] if (reset) begin // @[TLChannelCompactor.scala:108:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TLChannelCompactor.scala:60:24, :108:7] end else begin // @[TLChannelCompactor.scala:108:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3])) : head_counter - 9'h1; // @[TLChannelCompactor.scala:47:17] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN_0 & io_beat_bits_tail_0) & (_GEN_0 & io_beat_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)

Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundRawFNToRecFN_e8_s24_27( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_27 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File IterativeTrapCheck.scala: package saturn.frontend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.diplomacy._ import saturn.common._ class IndexMaskAccess(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val in = Input(Bool()) val inst = Input(new VectorIssueInst) val index_access = Flipped(new VectorIndexAccessIO) val mask_access = Flipped(new VectorMaskAccessIO) val access = new Bundle { val ready = Output(Bool()) val eidx = Input(UInt(log2Ceil(maxVLMax).W)) val index = Output(UInt(64.W)) val mask = Output(Bool()) } val pop = Input(Valid(UInt(log2Ceil(maxVLMax).W))) val flush = Input(Bool()) }) val valid = RegInit(false.B) val eidx = Reg(UInt(log2Ceil(maxVLMax).W)) // This all works only with pow2 buffers and eidx starting at 0 val valids = Reg(Vec(4, Bool())) val indices = Reg(Vec(4, UInt(64.W))) val masks = Reg(Vec(4, Bool())) when (io.in) { assert(!valid) valid := true.B eidx := 0.U valids.foreach(_ := false.B) } val needs_index = io.inst.mop.isOneOf(mopOrdered, mopUnordered) val needs_mask = !io.inst.vm val index_ready = io.index_access.ready || !needs_index val mask_ready = io.mask_access.ready || !needs_mask io.index_access.valid := valid && needs_index && !valids(eidx(1,0)) io.mask_access.valid := valid && needs_mask && !valids(eidx(1,0)) io.index_access.vrs := io.inst.rs2 io.index_access.eidx := eidx io.index_access.eew := io.inst.mem_idx_size io.mask_access.eidx := eidx when (valid && index_ready && mask_ready && !valids(eidx(1,0))) { val next_eidx = eidx +& 1.U eidx := eidx + 1.U when (next_eidx === io.inst.vconfig.vl) { valid := false.B } valids(eidx(1,0)) := true.B indices(eidx(1,0)) := io.index_access.idx masks(eidx(1,0)) := io.mask_access.mask } io.access.ready := valids(io.access.eidx(1,0)) io.access.index := indices(io.access.eidx(1,0)) io.access.mask := masks(io.access.eidx(1,0)) when (io.pop.fire) { valids(io.pop.bits(1,0)) := false.B } when (io.flush) { valid := false.B } } class IterativeTrapCheck(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val status = Input(new MStatus) val in = Input(Valid(new VectorIssueInst)) val busy = Output(Bool()) val s0_tlb_req = Valid(new TLBReq(3)) val s1_tlb_req = Valid(new TLBReq(3)) val tlb_resp = Input(new TLBResp) val retire = Output(Bool()) val pc = Output(UInt(vaddrBitsExtended.W)) val vstart = Valid(UInt(log2Ceil(maxVLMax).W)) val vconfig = Valid(new VConfig) val xcpt = Valid(new Bundle { val cause = UInt(xLen.W) val tval = UInt(coreMaxAddrBits.W) }) val inst = Output(new VectorIssueInst) val issue = Decoupled(new VectorIssueInst) val index_access = Flipped(new VectorIndexAccessIO) val mask_access = Flipped(new VectorMaskAccessIO) }) val replay_kill = WireInit(false.B) def nextPage(addr: UInt) = ((addr + (1 << pgIdxBits).U) >> pgIdxBits) << pgIdxBits val valid = RegInit(false.B) val seg_hi = Reg(Bool()) val inst = Reg(new VectorIssueInst) val eidx = Reg(UInt(log2Ceil(maxVLMax).W)) val addr = Reg(UInt(vaddrBitsExtended.W)) val tlb_backoff = RegInit(0.U(2.W)) when (tlb_backoff =/= 0.U) { tlb_backoff := tlb_backoff - 1.U } val im_access = Module(new IndexMaskAccess) im_access.io.in := io.in.valid im_access.io.inst := inst im_access.io.index_access <> io.index_access im_access.io.mask_access <> io.mask_access when (io.in.valid) { assert(!valid) valid := true.B seg_hi := false.B inst := io.in.bits eidx := 0.U addr := io.in.bits.rs1_data } val stride = MuxLookup(inst.mop, 0.U)(Seq( (mopUnit -> ((inst.seg_nf +& 1.U) << inst.mem_elem_size)), (mopStrided -> inst.rs2_data) )) val indexed = inst.mop.isOneOf(mopOrdered, mopUnordered) val index_ready = !indexed || im_access.io.access.ready val mask_ready = inst.vm || im_access.io.access.ready val index = Mux(indexed, im_access.io.access.index & eewBitMask(inst.mem_idx_size), 0.U) val base = Mux(indexed, inst.rs1_data, addr) val indexaddr = base + index val tlb_addr = Mux(seg_hi, nextPage(indexaddr), indexaddr) val seg_nf_consumed = ((1 << pgIdxBits).U - Mux(seg_hi, indexaddr, tlb_addr)(pgIdxBits-1,0)) >> inst.mem_elem_size val seg_single_page = seg_nf_consumed >= (inst.seg_nf +& 1.U) val masked = !im_access.io.access.mask && !inst.vm val tlb_valid = eidx < inst.vconfig.vl && eidx >= inst.vstart && !masked val ff = inst.umop === lumopFF && inst.mop === mopUnit io.busy := valid io.inst := inst im_access.io.access.eidx := eidx io.s0_tlb_req.valid := tlb_valid && tlb_backoff === 0.U && index_ready && mask_ready io.s0_tlb_req.bits.vaddr := tlb_addr io.s0_tlb_req.bits.passthrough := false.B io.s0_tlb_req.bits.size := inst.mem_elem_size io.s0_tlb_req.bits.cmd := Mux(inst.opcode(5), M_XWR, M_XRD) io.s0_tlb_req.bits.prv := io.status.prv io.s0_tlb_req.bits.v := io.status.v io.s1_tlb_req.valid := RegEnable(io.s0_tlb_req.valid, false.B, valid) io.s1_tlb_req.bits := RegEnable(io.s0_tlb_req.bits, valid) val replay_fire = valid && eidx < inst.vconfig.vl && tlb_backoff === 0.U && index_ready && mask_ready when (replay_fire) { when (seg_hi || seg_single_page || inst.seg_nf === 0.U) { eidx := eidx + 1.U addr := addr + stride seg_hi := false.B } .otherwise { seg_hi := true.B } } val s1_valid = RegNext(replay_fire && !replay_kill, false.B) val s1_eidx = RegEnable(eidx, valid) val s1_masked = RegEnable(masked, valid) val s1_seg_hi = RegEnable(seg_hi, valid) val s1_base = RegEnable(base, valid) val s1_tlb_valid = RegEnable(tlb_valid, valid) val s1_tlb_addr = RegEnable(tlb_addr, valid) val s1_seg_nf_consumed = RegEnable(seg_nf_consumed, valid) val s1_seg_single_page = RegEnable(seg_single_page, valid) when (io.tlb_resp.miss && s1_valid && tlb_backoff === 0.U) { tlb_backoff := 3.U } val tlb_resp = WireInit(io.tlb_resp) when (!s1_tlb_valid) { tlb_resp.miss := false.B } val xcpts = Seq( (tlb_resp.pf.st, Causes.store_page_fault.U), (tlb_resp.pf.ld, Causes.load_page_fault.U), (tlb_resp.gf.st, Causes.store_guest_page_fault.U), (tlb_resp.gf.ld, Causes.load_guest_page_fault.U), (tlb_resp.ae.st, Causes.store_access.U), (tlb_resp.ae.ld, Causes.load_access.U), (tlb_resp.ma.st, Causes.misaligned_store.U), (tlb_resp.ma.ld, Causes.misaligned_load.U) ) val xcpt = xcpts.map(_._1).orR && s1_eidx >= inst.vstart && !s1_masked val cause = PriorityMux(xcpts) io.issue.valid := false.B io.issue.bits := inst io.issue.bits.vstart := s1_eidx io.issue.bits.vconfig.vl := s1_eidx +& 1.U io.issue.bits.segend := inst.seg_nf io.issue.bits.segstart := 0.U io.issue.bits.page := tlb_resp.paddr >> pgIdxBits io.xcpt.valid := false.B io.pc := inst.pc io.xcpt.bits.cause := cause io.xcpt.bits.tval := s1_tlb_addr io.vstart.valid := false.B io.vstart.bits := s1_eidx io.retire := false.B io.vconfig.valid := false.B io.vconfig.bits := inst.vconfig io.vconfig.bits.vl := s1_eidx im_access.io.pop.valid := false.B im_access.io.pop.bits := s1_eidx im_access.io.flush := false.B when (s1_valid) { io.issue.valid := !tlb_resp.miss && !xcpt && s1_eidx >= inst.vstart && !s1_masked when (inst.seg_nf =/= 0.U && !s1_seg_single_page) { when (!s1_seg_hi) { io.issue.bits.segend := s1_seg_nf_consumed - 1.U } .otherwise { io.issue.bits.segstart := s1_seg_nf_consumed } } when (s1_seg_hi || s1_seg_single_page || inst.seg_nf === 0.U) { im_access.io.pop.valid := true.B } when (tlb_resp.miss || !io.issue.ready) { tlb_backoff := 3.U replay_kill := true.B eidx := s1_eidx addr := s1_base seg_hi := s1_seg_hi im_access.io.pop.valid := false.B } .elsewhen (xcpt) { val ff_nofault = ff && s1_eidx =/= 0.U valid := false.B replay_kill := true.B io.retire := ff_nofault io.xcpt.valid := !ff_nofault io.vstart.valid := !ff_nofault io.vconfig.valid := ff_nofault im_access.io.flush := true.B } .elsewhen ((s1_eidx +& 1.U) === inst.vconfig.vl && (s1_seg_hi || s1_seg_single_page || inst.seg_nf === 0.U)) { valid := false.B replay_kill := true.B io.retire := true.B io.vstart.valid := true.B io.vstart.bits := 0.U im_access.io.flush := true.B } } }

module IterativeTrapCheck( // @[IterativeTrapCheck.scala:83:7] input clock, // @[IterativeTrapCheck.scala:83:7] input reset, // @[IterativeTrapCheck.scala:83:7] input [1:0] io_status_prv, // @[IterativeTrapCheck.scala:84:14] input io_in_valid, // @[IterativeTrapCheck.scala:84:14] input [39:0] io_in_bits_pc, // @[IterativeTrapCheck.scala:84:14] input [31:0] io_in_bits_bits, // @[IterativeTrapCheck.scala:84:14] input [7:0] io_in_bits_vconfig_vl, // @[IterativeTrapCheck.scala:84:14] input io_in_bits_vconfig_vtype_vill, // @[IterativeTrapCheck.scala:84:14] input [54:0] io_in_bits_vconfig_vtype_reserved, // @[IterativeTrapCheck.scala:84:14] input io_in_bits_vconfig_vtype_vma, // @[IterativeTrapCheck.scala:84:14] input io_in_bits_vconfig_vtype_vta, // @[IterativeTrapCheck.scala:84:14] input [2:0] io_in_bits_vconfig_vtype_vsew, // @[IterativeTrapCheck.scala:84:14] input io_in_bits_vconfig_vtype_vlmul_sign, // @[IterativeTrapCheck.scala:84:14] input [1:0] io_in_bits_vconfig_vtype_vlmul_mag, // @[IterativeTrapCheck.scala:84:14] input [6:0] io_in_bits_vstart, // @[IterativeTrapCheck.scala:84:14] input [63:0] io_in_bits_rs1_data, // @[IterativeTrapCheck.scala:84:14] input [63:0] io_in_bits_rs2_data, // @[IterativeTrapCheck.scala:84:14] input [2:0] io_in_bits_rm, // @[IterativeTrapCheck.scala:84:14] input [1:0] io_in_bits_emul, // @[IterativeTrapCheck.scala:84:14] input [1:0] io_in_bits_mop, // @[IterativeTrapCheck.scala:84:14] output io_busy, // @[IterativeTrapCheck.scala:84:14] output io_s0_tlb_req_valid, // @[IterativeTrapCheck.scala:84:14] output [39:0] io_s0_tlb_req_bits_vaddr, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_s0_tlb_req_bits_size, // @[IterativeTrapCheck.scala:84:14] output [4:0] io_s0_tlb_req_bits_cmd, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_s0_tlb_req_bits_prv, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_miss, // @[IterativeTrapCheck.scala:84:14] input [31:0] io_tlb_resp_paddr, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_pf_ld, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_pf_st, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_ae_ld, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_ae_st, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_ma_ld, // @[IterativeTrapCheck.scala:84:14] input io_tlb_resp_ma_st, // @[IterativeTrapCheck.scala:84:14] output io_retire, // @[IterativeTrapCheck.scala:84:14] output [39:0] io_pc, // @[IterativeTrapCheck.scala:84:14] output io_vstart_valid, // @[IterativeTrapCheck.scala:84:14] output [6:0] io_vstart_bits, // @[IterativeTrapCheck.scala:84:14] output io_vconfig_valid, // @[IterativeTrapCheck.scala:84:14] output [7:0] io_vconfig_bits_vl, // @[IterativeTrapCheck.scala:84:14] output io_vconfig_bits_vtype_vill, // @[IterativeTrapCheck.scala:84:14] output [54:0] io_vconfig_bits_vtype_reserved, // @[IterativeTrapCheck.scala:84:14] output io_vconfig_bits_vtype_vma, // @[IterativeTrapCheck.scala:84:14] output io_vconfig_bits_vtype_vta, // @[IterativeTrapCheck.scala:84:14] output [2:0] io_vconfig_bits_vtype_vsew, // @[IterativeTrapCheck.scala:84:14] output io_vconfig_bits_vtype_vlmul_sign, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_vconfig_bits_vtype_vlmul_mag, // @[IterativeTrapCheck.scala:84:14] output io_xcpt_valid, // @[IterativeTrapCheck.scala:84:14] output [63:0] io_xcpt_bits_cause, // @[IterativeTrapCheck.scala:84:14] output [39:0] io_xcpt_bits_tval, // @[IterativeTrapCheck.scala:84:14] output [31:0] io_inst_bits, // @[IterativeTrapCheck.scala:84:14] input io_issue_ready, // @[IterativeTrapCheck.scala:84:14] output io_issue_valid, // @[IterativeTrapCheck.scala:84:14] output [31:0] io_issue_bits_bits, // @[IterativeTrapCheck.scala:84:14] output [7:0] io_issue_bits_vconfig_vl, // @[IterativeTrapCheck.scala:84:14] output [2:0] io_issue_bits_vconfig_vtype_vsew, // @[IterativeTrapCheck.scala:84:14] output io_issue_bits_vconfig_vtype_vlmul_sign, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_issue_bits_vconfig_vtype_vlmul_mag, // @[IterativeTrapCheck.scala:84:14] output [6:0] io_issue_bits_vstart, // @[IterativeTrapCheck.scala:84:14] output [2:0] io_issue_bits_segstart, // @[IterativeTrapCheck.scala:84:14] output [2:0] io_issue_bits_segend, // @[IterativeTrapCheck.scala:84:14] output [63:0] io_issue_bits_rs1_data, // @[IterativeTrapCheck.scala:84:14] output [63:0] io_issue_bits_rs2_data, // @[IterativeTrapCheck.scala:84:14] output [19:0] io_issue_bits_page, // @[IterativeTrapCheck.scala:84:14] output [2:0] io_issue_bits_rm, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_issue_bits_emul, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_issue_bits_mop, // @[IterativeTrapCheck.scala:84:14] input io_index_access_ready, // @[IterativeTrapCheck.scala:84:14] output io_index_access_valid, // @[IterativeTrapCheck.scala:84:14] output [4:0] io_index_access_vrs, // @[IterativeTrapCheck.scala:84:14] output [7:0] io_index_access_eidx, // @[IterativeTrapCheck.scala:84:14] output [1:0] io_index_access_eew, // @[IterativeTrapCheck.scala:84:14] input [63:0] io_index_access_idx, // @[IterativeTrapCheck.scala:84:14] input io_mask_access_ready, // @[IterativeTrapCheck.scala:84:14] output io_mask_access_valid, // @[IterativeTrapCheck.scala:84:14] output [7:0] io_mask_access_eidx, // @[IterativeTrapCheck.scala:84:14] input io_mask_access_mask // @[IterativeTrapCheck.scala:84:14] ); wire _im_access_io_access_ready; // @[IterativeTrapCheck.scala:118:25] wire [63:0] _im_access_io_access_index; // @[IterativeTrapCheck.scala:118:25] wire _im_access_io_access_mask; // @[IterativeTrapCheck.scala:118:25] reg valid; // @[IterativeTrapCheck.scala:110:23] reg seg_hi; // @[IterativeTrapCheck.scala:111:19] reg [39:0] inst_pc; // @[IterativeTrapCheck.scala:112:19] reg [31:0] inst_bits; // @[IterativeTrapCheck.scala:112:19] reg [7:0] inst_vconfig_vl; // @[IterativeTrapCheck.scala:112:19] reg inst_vconfig_vtype_vill; // @[IterativeTrapCheck.scala:112:19] reg [54:0] inst_vconfig_vtype_reserved; // @[IterativeTrapCheck.scala:112:19] reg inst_vconfig_vtype_vma; // @[IterativeTrapCheck.scala:112:19] reg inst_vconfig_vtype_vta; // @[IterativeTrapCheck.scala:112:19] reg [2:0] inst_vconfig_vtype_vsew; // @[IterativeTrapCheck.scala:112:19] reg inst_vconfig_vtype_vlmul_sign; // @[IterativeTrapCheck.scala:112:19] reg [1:0] inst_vconfig_vtype_vlmul_mag; // @[IterativeTrapCheck.scala:112:19] reg [6:0] inst_vstart; // @[IterativeTrapCheck.scala:112:19] reg [63:0] inst_rs1_data; // @[IterativeTrapCheck.scala:112:19] reg [63:0] inst_rs2_data; // @[IterativeTrapCheck.scala:112:19] reg [2:0] inst_rm; // @[IterativeTrapCheck.scala:112:19] reg [1:0] inst_emul; // @[IterativeTrapCheck.scala:112:19] reg [1:0] inst_mop; // @[IterativeTrapCheck.scala:112:19] reg [6:0] eidx; // @[IterativeTrapCheck.scala:113:19] reg [39:0] addr; // @[IterativeTrapCheck.scala:114:19] reg [1:0] tlb_backoff; // @[IterativeTrapCheck.scala:115:28]

Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }

module PriorityQueueStage_188( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RecFNToIN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.log2Up import scala.math._ import consts._ class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module { override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}" val io = IO(new Bundle { val in = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val signedOut = Input(Bool()) val out = Output(Bits(intWidth.W)) val intExceptionFlags = Output(Bits(3.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in) val magGeOne = rawIn.sExp(expWidth) val posExp = rawIn.sExp(expWidth - 1, 0) val magJustBelowOne = !magGeOne && posExp.andR //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) /*------------------------------------------------------------------------ | Assuming the input floating-point value is not a NaN, its magnitude is | at least 1, and it is not obviously so large as to lead to overflow, | convert its significand to fixed-point (i.e., with the binary point in a | fixed location). For a non-NaN input with a magnitude less than 1, this | expression contrives to ensure that the integer bits of 'alignedSig' | will all be zeros. *------------------------------------------------------------------------*/ val shiftedSig = (magGeOne ## rawIn.sig(sigWidth - 2, 0))<< Mux(magGeOne, rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0), 0.U ) val alignedSig = (shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR val unroundedInt = 0.U(intWidth.W) | alignedSig>>2 val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero) val roundIncr_near_even = (magGeOne && (alignedSig(2, 1).andR || alignedSig(1, 0).andR)) || (magJustBelowOne && alignedSig(1, 0).orR) val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) || magJustBelowOne val roundIncr = (roundingMode_near_even && roundIncr_near_even ) || (roundingMode_near_maxMag && roundIncr_near_maxMag) || ((roundingMode_min || roundingMode_odd) && (rawIn.sign && common_inexact)) || (roundingMode_max && (!rawIn.sign && common_inexact)) val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt) val roundedInt = Mux(roundIncr ^ rawIn.sign, complUnroundedInt + 1.U, complUnroundedInt ) | (roundingMode_odd && common_inexact) val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U) //*** CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM //*** 'unroundedInt'?: val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr val common_overflow = Mux(magGeOne, (posExp >= intWidth.U) || Mux(io.signedOut, Mux(rawIn.sign, magGeOne_atOverflowEdge && (unroundedInt(intWidth - 2, 0).orR || roundIncr), magGeOne_atOverflowEdge || ((posExp === (intWidth - 2).U) && roundCarryBut2) ), rawIn.sign || (magGeOne_atOverflowEdge && unroundedInt(intWidth - 2) && roundCarryBut2) ), !io.signedOut && rawIn.sign && roundIncr ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val invalidExc = rawIn.isNaN || rawIn.isInf val overflow = !invalidExc && common_overflow val inexact = !invalidExc && !common_overflow && common_inexact val excSign = !rawIn.isNaN && rawIn.sign val excOut = Mux((io.signedOut === excSign), (BigInt(1)<<(intWidth - 1)).U, 0.U ) | Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U) io.out := Mux(invalidExc || common_overflow, excOut, roundedInt) io.intExceptionFlags := invalidExc ## overflow ## inexact }

module RecFNToIN_e11_s53_i32( // @[RecFNToIN.scala:46:7] input [64:0] io_in, // @[RecFNToIN.scala:49:16] input [2:0] io_roundingMode, // @[RecFNToIN.scala:49:16] input io_signedOut, // @[RecFNToIN.scala:49:16] output [31:0] io_out, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire rawIn_isNaN = (&(io_in[63:62])) & io_in[61]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}] wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52])); // @[RecFNToIN.scala:61:30, :62:28, :63:{27,37,47}] wire roundingMode_odd = io_roundingMode == 3'h6; // @[RecFNToIN.scala:72:53] wire [83:0] shiftedSig = {31'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[56:52] : 5'h0); // @[rawFloatFromRecFN.scala:61:49] wire [1:0] _roundIncr_near_even_T_6 = {shiftedSig[51], |(shiftedSig[50:0])}; // @[RecFNToIN.scala:83:49, :89:{51,69}, :92:50] wire common_inexact = io_in[63] ? (|_roundIncr_near_even_T_6) : (|(io_in[63:61])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}] wire roundIncr = io_roundingMode == 3'h0 & (io_in[63] & ((&(shiftedSig[52:51])) | (&_roundIncr_near_even_T_6)) | magJustBelowOne & (|_roundIncr_near_even_T_6)) | io_roundingMode == 3'h4 & (io_in[63] & shiftedSig[51] | magJustBelowOne) | (io_roundingMode == 3'h2 | roundingMode_odd) & io_in[64] & common_inexact | io_roundingMode == 3'h3 & ~(io_in[64]) & common_inexact; // @[rawFloatFromRecFN.scala:52:53, :59:25] wire [31:0] complUnroundedInt = {32{io_in[64]}} ^ shiftedSig[83:52]; // @[rawFloatFromRecFN.scala:59:25] wire [31:0] _roundedInt_T_3 = roundIncr ^ io_in[64] ? complUnroundedInt + 32'h1 : complUnroundedInt; // @[rawFloatFromRecFN.scala:59:25] wire magGeOne_atOverflowEdge = io_in[62:52] == 11'h1F; // @[RecFNToIN.scala:62:28, :110:43] wire roundCarryBut2 = (&(shiftedSig[81:52])) & roundIncr; // @[RecFNToIN.scala:83:49, :90:52, :98:61, :99:61, :101:46, :113:{38,56,61}] wire common_overflow = io_in[63] ? (|(io_in[62:57])) | (io_signedOut ? (io_in[64] ? magGeOne_atOverflowEdge & ((|(shiftedSig[82:52])) | roundIncr) : magGeOne_atOverflowEdge | io_in[62:52] == 11'h1E & roundCarryBut2) : io_in[64] | magGeOne_atOverflowEdge & shiftedSig[82] & roundCarryBut2) : ~io_signedOut & io_in[64] & roundIncr; // @[rawFloatFromRecFN.scala:59:25] wire invalidExc = rawIn_isNaN | (&(io_in[63:62])) & ~(io_in[61]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}, :57:{33,36}] wire excSign = ~rawIn_isNaN & io_in[64]; // @[rawFloatFromRecFN.scala:56:33, :59:25] assign io_out = invalidExc | common_overflow ? {io_signedOut == excSign, {31{~excSign}}} : {_roundedInt_T_3[31:1], _roundedInt_T_3[0] | roundingMode_odd & common_inexact}; // @[RecFNToIN.scala:46:7, :72:53, :92:29, :105:12, :108:{11,31}, :115:12, :133:34, :137:32, :139:27, :142:11, :143:{12,13}, :145:{18,30}] assign io_intExceptionFlags = {invalidExc, ~invalidExc & common_overflow, ~invalidExc & ~common_overflow & common_inexact}; // @[RecFNToIN.scala:46:7, :92:29, :115:12, :133:34, :134:{20,32}, :135:{32,35,52}, :146:52] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_223( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File TraceGen.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. // This file was originally written by Matthew Naylor, University of // Cambridge, based on code already present in the groundtest repo. // // This software was partly developed by the University of Cambridge // Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 // ("CTSRD"), as part of the DARPA CRASH research programme. // // This software was partly developed by the University of Cambridge // Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 // ("MRC2"), as part of the DARPA MRC research programme. // // This software was partly developed by the University of Cambridge // Computer Laboratory as part of the Rigorous Engineering of // Mainstream Systems (REMS) project, funded by EPSRC grant // EP/K008528/1. package freechips.rocketchip.groundtest import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem.{HierarchicalElementCrossingParamsLike, CanAttachTile} import freechips.rocketchip.util._ import freechips.rocketchip.prci.{ClockSinkParameters, ClockCrossingType} // ======= // Outline // ======= // Generate memory traces that result from random sequences of memory // operations. These traces can then be validated by an external // tool. A trace is a simply sequence of memory requests and // responses. // ========================== // Trace-generator parameters // ========================== // Compile-time parameters: // // * The id of the generator (there may be more than one in a // multi-core system). // // * The total number of generators present in the system. // // * The desired number of requests to be sent by each generator. // // * A bag of physical addresses, shared by all cores, from which an // address can be drawn when generating a fresh request. // // * A number of random 'extra addresses', local to each core, from // which an address can be drawn when generating a fresh request. // (This is a way to generate a wider range of addresses without having // to repeatedly recompile with a different address bag.) case class TraceGenParams( wordBits: Int, addrBits: Int, addrBag: List[BigInt], maxRequests: Int, memStart: BigInt, numGens: Int, dcache: Option[DCacheParams] = Some(DCacheParams()), tileId: Int = 0 ) extends InstantiableTileParams[TraceGenTile] with GroundTestTileParams { def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): TraceGenTile = { new TraceGenTile(this, crossing, lookup) } val blockerCtrlAddr = None val baseName = "tracegentile" val uniqueName = s"${baseName}_$tileId" val clockSinkParams = ClockSinkParameters() } trait HasTraceGenParams { implicit val p: Parameters val params: TraceGenParams val pAddrBits = params.addrBits val numGens = params.numGens val numReqsPerGen = params.maxRequests val memStart = params.memStart val memRespTimeout = 8192 val numBitsInWord = params.wordBits val numBytesInWord = numBitsInWord / 8 val numBitsInWordOffset = log2Up(numBytesInWord) val addressBag = params.addrBag val addressBagLen = addressBag.length val logAddressBagLen = log2Up(addressBagLen) val genExtraAddrs = false val logNumExtraAddrs = 1 val numExtraAddrs = 1 << logNumExtraAddrs val maxTags = 8 require(numBytesInWord * 8 == numBitsInWord) require((1 << logAddressBagLen) == addressBagLen) } case class TraceGenTileAttachParams( tileParams: TraceGenParams, crossingParams: HierarchicalElementCrossingParamsLike ) extends CanAttachTile { type TileType = TraceGenTile val lookup: LookupByHartIdImpl = HartsWontDeduplicate(tileParams) } // ============ // Trace format // ============ // Let <id> denote a generator id; // <addr> denote an address (in hex); // <data> denote a value that is stored at an address; // <tag> denote a unique request/response id; // and <time> denote an integer representing a cycle-count. // Each line in the trace takes one of the following formats. // // <id>: load-req <addr> #<tag> @<time> // <id>: load-reserve-req <addr> #<tag> @<time> // <id>: store-req <data> <addr> #<tag> @<time> // <id>: store-cond-req <data> <addr> #<tag> @<time> // <id>: swap-req <data> <addr> #<tag> @<time> // <id>: resp <data> #<tag> @<time> // <id>: fence-req @<time> // <id>: fence-resp @<time> // NOTE: The (address, value) pair of every generated store is unique, // i.e. the same value is never written to the same address twice. // This aids trace validation. // ============ // Random seeds // ============ // The generator employs "unitialised registers" to seed its PRNGs; // these are randomly initialised by the C++ backend. This means that // the "-s" command-line argument to the Rocket emulator can be used // to generate new traces, or to replay specific ones. // =========== // Tag manager // =========== // This is used to obtain unique tags for memory requests: each // request must carry a unique tag since responses can come back // out-of-order. // // The tag manager can be viewed as a set of tags. The user can take // a tag out of the set (if there is one available) and later put it // back. class TagMan(val logNumTags : Int) extends Module { val io = IO(new Bundle { // Is there a tag available? val available = Output(Bool()) // If so, which one? val tagOut = Output(UInt(logNumTags.W)) // User pulses this to take the currently available tag val take = Input(Bool()) // User pulses this to put a tag back val put = Input(Bool()) // And the tag put back is val tagIn = Input(UInt((logNumTags.W))) }) // Total number of tags available val numTags = 1 << logNumTags // For each tag, record whether or not it is in use val inUse = List.fill(numTags)(RegInit(false.B)) // Mapping from each tag to its 'inUse' bit val inUseMap = (0 to numTags-1).map(i => i.U).zip(inUse) // Next tag to offer val nextTag = RegInit(0.U(logNumTags.W)) io.tagOut := nextTag // Is the next tag available? io.available := ~MuxLookup(nextTag, true.B)(inUseMap) // When user takes a tag when (io.take) { for ((i, b) <- inUseMap) { when (i === nextTag) { b := true.B } } nextTag := nextTag + 1.U } // When user puts a tag back when (io.put) { for ((i, b) <- inUseMap) { when (i === io.tagIn) { b := false.B } } } } // =============== // Trace generator // =============== class TraceGenerator(val params: TraceGenParams)(implicit val p: Parameters) extends Module with HasTraceGenParams { val io = IO(new Bundle { val finished = Output(Bool()) val timeout = Output(Bool()) val mem = new HellaCacheIO val hartid = Input(UInt(log2Up(numGens).W)) val fence_rdy = Input(Bool()) }) val totalNumAddrs = addressBag.size + numExtraAddrs val initCount = RegInit(0.U(log2Up(totalNumAddrs).W)) val initDone = RegInit(false.B) val reqTimer = Module(new Timer(8192, maxTags)) reqTimer.io.start.valid := io.mem.req.fire reqTimer.io.start.bits := io.mem.req.bits.tag reqTimer.io.stop.valid := io.mem.resp.valid reqTimer.io.stop.bits := io.mem.resp.bits.tag // Random addresses // ---------------- // Address bag, shared by all cores, taken from module parameters. // In addition, there is a per-core random selection of extra addresses. val bagOfAddrs = addressBag.map(x => (memStart + x).U(pAddrBits.W)) val extraAddrs = Seq.fill(numExtraAddrs) { (memStart + SeededRandom.fromSeed.nextInt(1 << 16) * numBytesInWord).U(pAddrBits.W) } // A random index into the address bag. val randAddrBagIndex = LCG(logAddressBagLen) // A random address from the address bag. val addrBagIndices = (0 to addressBagLen-1). map(i => i.U(logAddressBagLen.W)) val randAddrFromBag = MuxLookup(randAddrBagIndex, 0.U)( addrBagIndices.zip(bagOfAddrs)) // Random address from the address bag or the extra addresses. val extraAddrIndices = (0 to numExtraAddrs-1) .map(i => i.U(logNumExtraAddrs.W)) val randAddr = if (! genExtraAddrs) { randAddrFromBag } else { // A random index into the extra addresses. val randExtraAddrIndex = LCG(logNumExtraAddrs) // A random address from the extra addresses. val randAddrFromExtra = Cat(0.U, MuxLookup(randExtraAddrIndex, 0.U)( extraAddrIndices.zip(extraAddrs)), 0.U(3.W)) Frequency(List( (1, randAddrFromBag), (1, randAddrFromExtra))) } val allAddrs = extraAddrs ++ bagOfAddrs val allAddrIndices = (0 until totalNumAddrs) .map(i => i.U(log2Ceil(totalNumAddrs).W)) val initAddr = MuxLookup(initCount, 0.U)( allAddrIndices.zip(allAddrs)) // Random opcodes // -------------- // Generate random opcodes for memory operations according to the // given frequency distribution. // Opcodes val (opNop :: opLoad :: opStore :: opFence :: opLRSC :: opSwap :: opDelay :: Nil) = Enum(7) // Distribution specified as a list of (frequency,value) pairs. // NOTE: frequencies must sum to a power of two. val randOp = Frequency(List( (10, opLoad), (10, opStore), (4, opFence), (3, opLRSC), (3, opSwap), (2, opDelay))) // Request/response tags // --------------------- // Responses may come back out-of-order. Each request and response // therefore contains a unique 7-bit identifier, referred to as a // "tag", used to match each response with its corresponding request. // Create a tag manager giving out unique 3-bit tags val tagMan = Module(new TagMan(log2Ceil(maxTags))) // Default inputs tagMan.io.take := false.B; tagMan.io.put := false.B; tagMan.io.tagIn := 0.U; // Cycle counter // ------------- // 32-bit cycle count used to record send-times of requests and // receive-times of respones. val cycleCount = RegInit(0.U(32.W)) cycleCount := cycleCount + 1.U; // Delay timer // ----------- // Used to implement the delay operation and to insert random // delays between load-reserve and store-conditional commands. // A 16-bit timer is plenty val delayTimer = Module(new DynamicTimer(16)) // Used to generate a random delay period val randDelayBase = LCG16() // Random delay period: usually small, occasionally big val randDelay = Frequency(List( (14, 0.U(13.W) ## randDelayBase(2, 0)), (2, 0.U(11.W) ## randDelayBase(5, 0)))) // Default inputs delayTimer.io.start := false.B delayTimer.io.period := randDelay delayTimer.io.stop := false.B // Operation dispatch // ------------------ // Hardware thread id val tid = io.hartid // Request & response count val reqCount = RegInit(0.U(32.W)) val respCount = RegInit(0.U(32.W)) // Current operation being executed val currentOp = RegInit(opNop) // If larger than 0, a multi-cycle operation is in progress. // Value indicates stage of progress. val opInProgress = RegInit(0.U(2.W)) // Indicate when a fresh request is to be sent val sendFreshReq = Wire(Bool()) sendFreshReq := false.B // Used to generate unique data values val nextData = RegInit(1.U((numBitsInWord-tid.getWidth).W)) // Registers for all the interesting parts of a request val reqValid = RegInit(false.B) val reqAddr = RegInit(0.U(numBitsInWord.W)) val reqData = RegInit(0.U(numBitsInWord.W)) val reqCmd = RegInit(0.U(5.W)) val reqTag = RegInit(0.U(7.W)) // Condition on being allowed to send a fresh request val canSendFreshReq = (!reqValid || io.mem.req.fire) && tagMan.io.available // Operation dispatch when (reqCount < numReqsPerGen.U) { // No-op when (currentOp === opNop) { // Move on to a new operation currentOp := Mux(initDone, randOp, opStore) } // Fence when (currentOp === opFence) { when (opInProgress === 0.U && !reqValid) { // Emit fence request printf("%d: fence-req @%d\n", tid, cycleCount) // Multi-cycle operation now in progress opInProgress := 1.U } // Wait until all requests have had a response .elsewhen (reqCount === respCount && io.fence_rdy) { // Emit fence response printf("%d: fence-resp @%d\n", tid, cycleCount) // Move on to a new operation currentOp := randOp // Operation finished opInProgress := 0.U } } // Delay when (currentOp === opDelay) { when (opInProgress === 0.U) { // Start timer delayTimer.io.start := true.B // Multi-cycle operation now in progress opInProgress := 1.U } .elsewhen (delayTimer.io.timeout) { // Move on to a new operation currentOp := randOp // Operation finished opInProgress := 0.U } } // Load, store, or atomic swap when (currentOp === opLoad || currentOp === opStore || currentOp === opSwap) { when (canSendFreshReq) { // Set address reqAddr := Mux(initDone, randAddr, initAddr) // Set command when (currentOp === opLoad) { reqCmd := M_XRD } .elsewhen (currentOp === opStore) { reqCmd := M_XWR } .elsewhen (currentOp === opSwap) { reqCmd := M_XA_SWAP } // Send request sendFreshReq := true.B // Move on to a new operation when (!initDone && initCount =/= (totalNumAddrs - 1).U) { initCount := initCount + 1.U currentOp := opStore } .otherwise { currentOp := randOp initDone := true.B } } } // Load-reserve and store-conditional // First issue an LR, then delay, then issue an SC when (currentOp === opLRSC) { // LR request has not yet been sent when (opInProgress === 0.U) { when (canSendFreshReq) { // Set address and command reqAddr := randAddr reqCmd := M_XLR // Send request sendFreshReq := true.B // Multi-cycle operation now in progress opInProgress := 1.U } } // LR request has been sent, start delay timer when (opInProgress === 1.U) { // Start timer delayTimer.io.start := true.B // Indicate that delay has started opInProgress := 2.U } // Delay in progress when (opInProgress === 2.U) { when (delayTimer.io.timeout) { // Delay finished opInProgress := 3.U } } // Delay finished, send SC request when (opInProgress === 3.U) { when (canSendFreshReq) { // Set command, but leave address // i.e. use same address as LR did reqCmd := M_XSC // Send request sendFreshReq := true.B // Multi-cycle operation finished opInProgress := 0.U // Move on to a new operation currentOp := randOp } } } } // Sending of requests // ------------------- when (sendFreshReq) { // Grab a unique tag for the request reqTag := tagMan.io.tagOut tagMan.io.take := true.B // Fill in unique data reqData := Cat(nextData, tid) nextData := nextData + 1.U // Request is good to go! reqValid := true.B // Increment request count reqCount := reqCount + 1.U } .elsewhen (io.mem.req.fire) { // Request has been sent and there is no new request ready reqValid := false.B } // Wire up interface to memory io.mem.req.valid := reqValid io.mem.req.bits.addr := reqAddr io.mem.req.bits.data := reqData io.mem.req.bits.size := log2Ceil(numBytesInWord).U io.mem.req.bits.signed := false.B io.mem.req.bits.cmd := reqCmd io.mem.req.bits.tag := reqTag io.mem.req.bits.no_alloc := false.B io.mem.req.bits.no_xcpt := false.B io.mem.req.bits.no_resp := false.B io.mem.req.bits.mask := ~(0.U((numBitsInWord / 8).W)) io.mem.req.bits.phys := false.B io.mem.req.bits.dprv := PRV.M.U io.mem.req.bits.dv := false.B io.mem.keep_clock_enabled := true.B // The below signals don't matter because this uses the SimpleHellaIF io.mem.s1_data.data := RegNext(io.mem.req.bits.data) io.mem.s1_data.mask := RegNext(io.mem.req.bits.mask) io.mem.s1_kill := false.B io.mem.s2_kill := false.B // On cycle when request is actually sent, print it when (io.mem.req.fire) { // Short-hand for address val addr = io.mem.req.bits.addr // Print thread id printf("%d:", tid) // Print command when (reqCmd === M_XRD) { printf(" load-req 0x%x", addr) } when (reqCmd === M_XLR) { printf(" load-reserve-req 0x%x", addr) } when (reqCmd === M_XWR) { printf(" store-req %d 0x%x", reqData, addr) } when (reqCmd === M_XSC) { printf(" store-cond-req %d 0x%x", reqData, addr) } when (reqCmd === M_XA_SWAP) { printf(" swap-req %d 0x%x", reqData, addr) } // Print tag printf(" #%d", reqTag) // Print time printf(" @%d\n", cycleCount) } // Handling of responses // --------------------- // When a response is received when (io.mem.resp.valid) { // Put tag back in tag set tagMan.io.tagIn := io.mem.resp.bits.tag tagMan.io.put := true.B // Print response printf("%d: resp %d #%d @%d\n", tid, io.mem.resp.bits.data, io.mem.resp.bits.tag, cycleCount) // Increment response count respCount := respCount + 1.U } // Termination condition // --------------------- val done = reqCount === numReqsPerGen.U && respCount === numReqsPerGen.U val donePulse = done && !RegNext(done, false.B) // Emit that this thread has completed when (donePulse) { printf(s"FINISHED ${numGens}\n") } io.finished := done io.timeout := reqTimer.io.timeout.valid } // ======================= // Trace-generator wrapper // ======================= class TraceGenTile private( val params: TraceGenParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, q: Parameters ) extends GroundTestTile(params, crossing, lookup, q) { def this(params: TraceGenParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcacheOpt.map(_.node).getOrElse(TLTempNode()) override lazy val module = new TraceGenTileModuleImp(this) } class TraceGenTileModuleImp(outer: TraceGenTile) extends GroundTestTileModuleImp(outer) { val tracegen = Module(new TraceGenerator(outer.params)) tracegen.io.hartid := outer.hartIdSinkNode.bundle outer.dcacheOpt foreach { dcache => val dcacheIF = Module(new SimpleHellaCacheIF()) dcacheIF.io.requestor <> tracegen.io.mem dcache.module.io.cpu <> dcacheIF.io.cache tracegen.io.fence_rdy := dcache.module.io.cpu.ordered } outer.reportCease(Some(tracegen.io.finished)) outer.reportHalt(Some(tracegen.io.timeout)) outer.reportWFI(None) status.timeout.valid := tracegen.io.timeout status.timeout.bits := 0.U status.error.valid := false.B assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.tileId}: request timed out") } File LCG.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.Cat /** A 16-bit psuedo-random generator based on a linear conguential * generator (LCG). The state is stored in an unitialised register. * When using the C++ backend, it is straigtforward to arrange a * random initial value for each uninitialised register, effectively * seeding each LCG16 instance with a different seed. */ class LCG16 extends Module { val io = IO(new Bundle { val out = Output(UInt(16.W)) val inc = Input(Bool()) }) val state = Reg(UInt(32.W)) when (io.inc) { state := state * 1103515245.U(32.W) + 12345.U(32.W) } io.out := state(30, 15) } /** An n-bit psuedo-random generator made from many instances of a * 16-bit LCG. Parameter 'width' must be larger than 0. */ class LCG(val w: Int) extends Module { val io = IO(new Bundle { val out = Output(UInt(w.W)) val inc = Input(Bool()) }) require(w > 0) val numLCG16s : Int = (w+15)/16 val outs = Seq.fill(numLCG16s) { LCG16(io.inc) } io.out := Cat(outs) } object LCG16 { def apply(inc: Bool = true.B): UInt = { val lcg = Module(new LCG16) lcg.io.inc := inc lcg.io.out } } object LCG { def apply(w: Int, inc: Bool = true.B): UInt = { val lcg = Module(new LCG(w)) lcg.io.inc := inc lcg.io.out } } File Frequency.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ /** Given a list of (frequency, value) pairs, return a random value * according to the frequency distribution. The sum of the * frequencies in the distribution must be a power of two. */ object Frequency { def apply(dist : List[(Int, Bits)]) : Bits = { // Distribution must be non-empty require(dist.length > 0) // Require that the frequencies sum to a power of two val (freqs, vals) = dist.unzip val total = freqs.sum require(isPow2(total)) // First item in the distribution val (firstFreq, firstVal) = dist.head // Result wire val result = Wire(Bits(firstVal.getWidth.W)) result := 0.U // Random value val randVal = LCG(log2Up(total)) // Pick return value var count = firstFreq var select = when (randVal < firstFreq.U) { result := firstVal } for (p <- dist.drop(1)) { count = count + p._1 select = select.elsewhen(randVal < count.U) { result := p._2 } } return result } }

module TraceGenerator_1( // @[TraceGen.scala:212:7] input clock, // @[TraceGen.scala:212:7] input reset, // @[TraceGen.scala:212:7] output io_finished, // @[TraceGen.scala:214:14] output io_timeout, // @[TraceGen.scala:214:14] input io_mem_req_ready, // @[TraceGen.scala:214:14] output io_mem_req_valid, // @[TraceGen.scala:214:14] output [39:0] io_mem_req_bits_addr, // @[TraceGen.scala:214:14] output [6:0] io_mem_req_bits_tag, // @[TraceGen.scala:214:14] output [4:0] io_mem_req_bits_cmd, // @[TraceGen.scala:214:14] output [63:0] io_mem_req_bits_data, // @[TraceGen.scala:214:14] output [63:0] io_mem_s1_data_data, // @[TraceGen.scala:214:14] input io_mem_resp_valid, // @[TraceGen.scala:214:14] input [6:0] io_mem_resp_bits_tag, // @[TraceGen.scala:214:14] input [1:0] io_mem_resp_bits_size, // @[TraceGen.scala:214:14] input [63:0] io_mem_resp_bits_data, // @[TraceGen.scala:214:14] input io_mem_ordered, // @[TraceGen.scala:214:14] input io_hartid, // @[TraceGen.scala:214:14] input io_fence_rdy // @[TraceGen.scala:214:14] ); wire [3:0] _randDelay_randVal_lcg_io_out; // @[LCG.scala:51:21] wire [15:0] _randDelayBase_lcg_io_out; // @[LCG.scala:43:21] wire _delayTimer_io_timeout; // @[TraceGen.scala:339:26] wire _tagMan_io_available; // @[TraceGen.scala:316:22] wire [2:0] _tagMan_io_tagOut; // @[TraceGen.scala:316:22] wire [4:0] _randOp_randVal_lcg_io_out; // @[LCG.scala:51:21] wire [3:0] _randAddrBagIndex_lcg_io_out; // @[LCG.scala:51:21] wire io_mem_req_ready_0 = io_mem_req_ready; // @[TraceGen.scala:212:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[TraceGen.scala:212:7] wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[TraceGen.scala:212:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[TraceGen.scala:212:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[TraceGen.scala:212:7] wire io_mem_ordered_0 = io_mem_ordered; // @[TraceGen.scala:212:7] wire io_hartid_0 = io_hartid; // @[TraceGen.scala:212:7] wire io_fence_rdy_0 = io_fence_rdy; // @[TraceGen.scala:212:7] wire [7:0] io_mem_req_bits_mask = 8'hFF; // @[TraceGen.scala:212:7] wire [7:0] io_mem_s1_data_mask = 8'hFF; // @[TraceGen.scala:212:7] wire [7:0] _io_mem_req_bits_mask_T = 8'hFF; // @[TraceGen.scala:538:27] wire [1:0] io_mem_req_bits_size = 2'h3; // @[TraceGen.scala:212:7] wire [1:0] io_mem_req_bits_dprv = 2'h3; // @[TraceGen.scala:212:7] wire io_mem_req_bits_signed = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_req_bits_dv = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_req_bits_phys = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_req_bits_no_resp = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s1_kill = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_nack = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_nack_cause_raw = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_kill = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_uncached = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_resp_bits_signed = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_resp_bits_dv = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_resp_bits_replay = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_resp_bits_has_data = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_replay_next = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_ma_ld = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_ma_st = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_pf_ld = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_pf_st = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_ae_ld = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_xcpt_ae_st = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_store_pending = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_acquire = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_release = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_grant = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_tlbMiss = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_blocked = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[TraceGen.scala:212:7] wire io_mem_clock_enabled = 1'h0; // @[TraceGen.scala:212:7] wire [31:0] io_mem_s2_paddr = 32'h0; // @[TraceGen.scala:212:7] wire [39:0] io_mem_resp_bits_addr = 40'h0; // @[TraceGen.scala:212:7] wire [39:0] io_mem_s2_gpa = 40'h0; // @[TraceGen.scala:212:7] wire [4:0] io_mem_resp_bits_cmd = 5'h0; // @[TraceGen.scala:212:7] wire [1:0] io_mem_resp_bits_dprv = 2'h0; // @[TraceGen.scala:212:7] wire [7:0] io_mem_resp_bits_mask = 8'h0; // @[TraceGen.scala:212:7] wire [63:0] io_mem_resp_bits_data_word_bypass = 64'h0; // @[TraceGen.scala:212:7] wire [63:0] io_mem_resp_bits_data_raw = 64'h0; // @[TraceGen.scala:212:7] wire [63:0] io_mem_resp_bits_store_data = 64'h0; // @[TraceGen.scala:212:7] wire io_mem_keep_clock_enabled = 1'h1; // @[TraceGen.scala:212:7] wire _randOp_T_5 = 1'h1; // @[Frequency.scala:38:40] wire _randDelay_T_5 = 1'h1; // @[Frequency.scala:38:40] wire done; // @[TraceGen.scala:596:44] wire [39:0] io_mem_req_bits_addr_0; // @[TraceGen.scala:212:7] wire [6:0] io_mem_req_bits_tag_0; // @[TraceGen.scala:212:7] wire [4:0] io_mem_req_bits_cmd_0; // @[TraceGen.scala:212:7] wire [63:0] io_mem_req_bits_data_0; // @[TraceGen.scala:212:7] wire io_mem_req_valid_0; // @[TraceGen.scala:212:7] wire [63:0] io_mem_s1_data_data_0; // @[TraceGen.scala:212:7] wire io_finished_0; // @[TraceGen.scala:212:7] wire io_timeout_0; // @[TraceGen.scala:212:7] reg [4:0] initCount; // @[TraceGen.scala:223:26] reg initDone; // @[TraceGen.scala:224:26] wire _T_31 = io_mem_req_ready_0 & io_mem_req_valid_0; // @[Decoupled.scala:51:35] wire _reqTimer_io_start_valid_T; // @[Decoupled.scala:51:35] assign _reqTimer_io_start_valid_T = _T_31; // @[Decoupled.scala:51:35] wire _canSendFreshReq_T_1; // @[Decoupled.scala:51:35] assign _canSendFreshReq_T_1 = _T_31; // @[Decoupled.scala:51:35] wire _randAddrFromBag_T = _randAddrBagIndex_lcg_io_out == 4'h1; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_1 = {44'h8000000, _randAddrFromBag_T, 3'h0}; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_2 = _randAddrBagIndex_lcg_io_out == 4'h2; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_3 = _randAddrFromBag_T_2 ? 48'h80000010 : _randAddrFromBag_T_1; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_4 = _randAddrBagIndex_lcg_io_out == 4'h3; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_5 = _randAddrFromBag_T_4 ? 48'h80000018 : _randAddrFromBag_T_3; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_6 = _randAddrBagIndex_lcg_io_out == 4'h4; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_7 = _randAddrFromBag_T_6 ? 48'h80000020 : _randAddrFromBag_T_5; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_8 = _randAddrBagIndex_lcg_io_out == 4'h5; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_9 = _randAddrFromBag_T_8 ? 48'h80000028 : _randAddrFromBag_T_7; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_10 = _randAddrBagIndex_lcg_io_out == 4'h6; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_11 = _randAddrFromBag_T_10 ? 48'h80000030 : _randAddrFromBag_T_9; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_12 = _randAddrBagIndex_lcg_io_out == 4'h7; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_13 = _randAddrFromBag_T_12 ? 48'h80000038 : _randAddrFromBag_T_11; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_14 = _randAddrBagIndex_lcg_io_out == 4'h8; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_15 = _randAddrFromBag_T_14 ? 48'h80000400 : _randAddrFromBag_T_13; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_16 = _randAddrBagIndex_lcg_io_out == 4'h9; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_17 = _randAddrFromBag_T_16 ? 48'h80000408 : _randAddrFromBag_T_15; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_18 = _randAddrBagIndex_lcg_io_out == 4'hA; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_19 = _randAddrFromBag_T_18 ? 48'h80000410 : _randAddrFromBag_T_17; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_20 = _randAddrBagIndex_lcg_io_out == 4'hB; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_21 = _randAddrFromBag_T_20 ? 48'h80000418 : _randAddrFromBag_T_19; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_22 = _randAddrBagIndex_lcg_io_out == 4'hC; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_23 = _randAddrFromBag_T_22 ? 48'h80000420 : _randAddrFromBag_T_21; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_24 = _randAddrBagIndex_lcg_io_out == 4'hD; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_25 = _randAddrFromBag_T_24 ? 48'h80000428 : _randAddrFromBag_T_23; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_26 = _randAddrBagIndex_lcg_io_out == 4'hE; // @[LCG.scala:51:21] wire [47:0] _randAddrFromBag_T_27 = _randAddrFromBag_T_26 ? 48'h80000430 : _randAddrFromBag_T_25; // @[TraceGen.scala:253:57] wire _randAddrFromBag_T_28 = &_randAddrBagIndex_lcg_io_out; // @[LCG.scala:51:21] wire [47:0] randAddrFromBag = _randAddrFromBag_T_28 ? 48'h80000438 : _randAddrFromBag_T_27; // @[TraceGen.scala:253:57] wire _initAddr_T = initCount == 5'h0; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_1 = _initAddr_T ? 48'h80057738 : 48'h0; // @[TraceGen.scala:283:43] wire _initAddr_T_2 = initCount == 5'h1; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_3 = _initAddr_T_2 ? 48'h80006228 : _initAddr_T_1; // @[TraceGen.scala:283:43] wire _initAddr_T_4 = initCount == 5'h2; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_5 = _initAddr_T_4 ? 48'h80000000 : _initAddr_T_3; // @[TraceGen.scala:283:43] wire _initAddr_T_6 = initCount == 5'h3; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_7 = _initAddr_T_6 ? 48'h80000008 : _initAddr_T_5; // @[TraceGen.scala:283:43] wire _initAddr_T_8 = initCount == 5'h4; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_9 = _initAddr_T_8 ? 48'h80000010 : _initAddr_T_7; // @[TraceGen.scala:283:43] wire _initAddr_T_10 = initCount == 5'h5; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_11 = _initAddr_T_10 ? 48'h80000018 : _initAddr_T_9; // @[TraceGen.scala:283:43] wire _initAddr_T_12 = initCount == 5'h6; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_13 = _initAddr_T_12 ? 48'h80000020 : _initAddr_T_11; // @[TraceGen.scala:283:43] wire _initAddr_T_14 = initCount == 5'h7; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_15 = _initAddr_T_14 ? 48'h80000028 : _initAddr_T_13; // @[TraceGen.scala:283:43] wire _initAddr_T_16 = initCount == 5'h8; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_17 = _initAddr_T_16 ? 48'h80000030 : _initAddr_T_15; // @[TraceGen.scala:283:43] wire _initAddr_T_18 = initCount == 5'h9; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_19 = _initAddr_T_18 ? 48'h80000038 : _initAddr_T_17; // @[TraceGen.scala:283:43] wire _initAddr_T_20 = initCount == 5'hA; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_21 = _initAddr_T_20 ? 48'h80000400 : _initAddr_T_19; // @[TraceGen.scala:283:43] wire _initAddr_T_22 = initCount == 5'hB; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_23 = _initAddr_T_22 ? 48'h80000408 : _initAddr_T_21; // @[TraceGen.scala:283:43] wire _initAddr_T_24 = initCount == 5'hC; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_25 = _initAddr_T_24 ? 48'h80000410 : _initAddr_T_23; // @[TraceGen.scala:283:43] wire _initAddr_T_26 = initCount == 5'hD; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_27 = _initAddr_T_26 ? 48'h80000418 : _initAddr_T_25; // @[TraceGen.scala:283:43] wire _initAddr_T_28 = initCount == 5'hE; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_29 = _initAddr_T_28 ? 48'h80000420 : _initAddr_T_27; // @[TraceGen.scala:283:43] wire _initAddr_T_30 = initCount == 5'hF; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_31 = _initAddr_T_30 ? 48'h80000428 : _initAddr_T_29; // @[TraceGen.scala:283:43] wire _initAddr_T_32 = initCount == 5'h10; // @[TraceGen.scala:223:26, :283:43] wire [47:0] _initAddr_T_33 = _initAddr_T_32 ? 48'h80000430 : _initAddr_T_31; // @[TraceGen.scala:283:43] wire _initAddr_T_34 = initCount == 5'h11; // @[TraceGen.scala:223:26, :283:43] wire [47:0] initAddr = _initAddr_T_34 ? 48'h80000438 : _initAddr_T_33; // @[TraceGen.scala:283:43] wire [2:0] randOp; // @[Frequency.scala:27:22] wire _randOp_T = _randOp_randVal_lcg_io_out < 5'hA; // @[LCG.scala:51:21] wire _randOp_T_1 = _randOp_randVal_lcg_io_out < 5'h14; // @[LCG.scala:51:21] wire _randOp_T_2 = _randOp_randVal_lcg_io_out[4:3] != 2'h3; // @[LCG.scala:51:21] wire _randOp_T_3 = _randOp_randVal_lcg_io_out < 5'h1B; // @[LCG.scala:51:21] wire _randOp_T_4 = _randOp_randVal_lcg_io_out[4:1] != 4'hF; // @[LCG.scala:51:21] assign randOp = _randOp_T ? 3'h1 : _randOp_T_1 ? 3'h2 : _randOp_T_2 ? 3'h3 : _randOp_T_3 ? 3'h4 : _randOp_T_4 ? 3'h5 : 3'h6; // @[Frequency.scala:27:22, :35:{32,47,56}, :38:{40,51,60}] reg [31:0] cycleCount; // @[TraceGen.scala:329:27] wire [32:0] _cycleCount_T = {1'h0, cycleCount} + 33'h1; // @[TraceGen.scala:329:27, :330:28] wire [31:0] _cycleCount_T_1 = _cycleCount_T[31:0]; // @[TraceGen.scala:330:28] wire [2:0] _randDelay_T = _randDelayBase_lcg_io_out[2:0]; // @[LCG.scala:43:21] wire [15:0] _randDelay_T_1 = {13'h0, _randDelay_T}; // @[TraceGen.scala:346:{20,36}] wire [5:0] _randDelay_T_2 = _randDelayBase_lcg_io_out[5:0]; // @[LCG.scala:43:21] wire [16:0] _randDelay_T_3 = {11'h0, _randDelay_T_2}; // @[TraceGen.scala:347:{20,36}] wire [15:0] randDelay; // @[Frequency.scala:27:22] wire _randDelay_T_4 = _randDelay_randVal_lcg_io_out[3:1] != 3'h7; // @[LCG.scala:51:21] assign randDelay = _randDelay_T_4 ? _randDelay_T_1 : _randDelay_T_3[15:0]; // @[Frequency.scala:27:22, :35:{32,47,56}, :38:{51,60}] reg [31:0] reqCount; // @[TraceGen.scala:361:26] reg [31:0] respCount; // @[TraceGen.scala:362:26] reg [2:0] currentOp; // @[TraceGen.scala:365:26] reg [1:0] opInProgress; // @[TraceGen.scala:369:29] wire sendFreshReq; // @[TraceGen.scala:372:26] reg [62:0] nextData; // @[TraceGen.scala:376:25] reg reqValid; // @[TraceGen.scala:379:25] assign io_mem_req_valid_0 = reqValid; // @[TraceGen.scala:212:7, :379:25] reg [63:0] reqAddr; // @[TraceGen.scala:380:25] reg [63:0] reqData; // @[TraceGen.scala:381:25] assign io_mem_req_bits_data_0 = reqData; // @[TraceGen.scala:212:7, :381:25] reg [4:0] reqCmd; // @[TraceGen.scala:382:25] assign io_mem_req_bits_cmd_0 = reqCmd; // @[TraceGen.scala:212:7, :382:25] reg [6:0] reqTag; // @[TraceGen.scala:383:25] assign io_mem_req_bits_tag_0 = reqTag; // @[TraceGen.scala:212:7, :383:25] wire _canSendFreshReq_T = ~reqValid; // @[TraceGen.scala:379:25, :386:26] wire _canSendFreshReq_T_2 = _canSendFreshReq_T | _canSendFreshReq_T_1; // @[Decoupled.scala:51:35] wire canSendFreshReq = _canSendFreshReq_T_2 & _tagMan_io_available; // @[TraceGen.scala:316:22, :386:{36,56}] wire _T = reqCount < 32'h2000; // @[TraceGen.scala:361:26, :390:18] wire [2:0] _currentOp_T = initDone ? randOp : 3'h2; // @[Frequency.scala:27:22] wire _T_2 = currentOp == 3'h3; // @[TraceGen.scala:365:26, :399:21] wire _T_5 = ~(|opInProgress) & ~reqValid; // @[TraceGen.scala:369:29, :379:25, :386:26, :400:{26,34}] wire _T_9 = reqCount == respCount & io_fence_rdy_0; // @[TraceGen.scala:212:7, :361:26, :362:26, :407:{27,41}] wire _T_12 = currentOp == 3'h6; // @[TraceGen.scala:365:26, :418:21] wire _T_19 = currentOp == 3'h1; // @[TraceGen.scala:365:26, :434:21] wire _T_20 = currentOp == 3'h2; // @[TraceGen.scala:365:26, :435:21] wire _T_21 = currentOp == 3'h5; // @[TraceGen.scala:365:26, :436:21] wire _T_18 = _T_19 | _T_20 | _T_21; // @[TraceGen.scala:434:{21,33}, :435:{21,33}, :436:21] wire [47:0] _reqAddr_T = initDone ? randAddrFromBag : initAddr; // @[TraceGen.scala:224:26, :253:57, :283:43, :439:23] wire _GEN = _T_18 & canSendFreshReq; // @[TraceGen.scala:373:16, :386:56, :434:33, :435:33, :436:33, :437:30] wire [5:0] _initCount_T = {1'h0, initCount} + 6'h1; // @[TraceGen.scala:223:26, :452:34] wire [4:0] _initCount_T_1 = _initCount_T[4:0]; // @[TraceGen.scala:452:34] wire _T_25 = currentOp == 3'h4; // @[TraceGen.scala:365:26, :463:21] wire _GEN_0 = ~(|opInProgress) & canSendFreshReq; // @[TraceGen.scala:369:29, :386:56, :400:26, :436:33, :465:{26,35}, :466:32, :468:19] wire _T_27 = opInProgress == 2'h1; // @[TraceGen.scala:369:29, :477:26] assign sendFreshReq = _T & (_T_25 ? ((&opInProgress) ? canSendFreshReq | _GEN_0 | _GEN : _GEN_0 | _GEN) : _GEN); // @[TraceGen.scala:369:29, :372:26, :373:16, :386:56, :390:{18,37}, :436:33, :437:30, :463:{21,33}, :465:35, :466:32, :468:19, :471:24, :491:{26,35}, :492:32, :497:24] wire [63:0] _reqData_T = {nextData, io_hartid_0}; // @[TraceGen.scala:212:7, :376:25, :515:19] wire [63:0] _nextData_T = {1'h0, nextData} + 64'h1; // @[TraceGen.scala:376:25, :516:26] wire [62:0] _nextData_T_1 = _nextData_T[62:0]; // @[TraceGen.scala:516:26] wire [32:0] _reqCount_T = {1'h0, reqCount} + 33'h1; // @[TraceGen.scala:361:26, :520:26] wire [31:0] _reqCount_T_1 = _reqCount_T[31:0]; // @[TraceGen.scala:520:26] assign io_mem_req_bits_addr_0 = reqAddr[39:0]; // @[TraceGen.scala:212:7, :380:25, :529:24] reg [63:0] io_mem_s1_data_data_REG; // @[TraceGen.scala:545:33] assign io_mem_s1_data_data_0 = io_mem_s1_data_data_REG; // @[TraceGen.scala:212:7, :545:33] wire [32:0] _respCount_T = {1'h0, respCount} + 33'h1; // @[TraceGen.scala:362:26, :590:28] wire [31:0] _respCount_T_1 = _respCount_T[31:0]; // @[TraceGen.scala:590:28] wire _done_T = reqCount == 32'h2000; // @[TraceGen.scala:361:26, :596:24] wire _done_T_1 = respCount == 32'h2000; // @[TraceGen.scala:362:26, :597:24] assign done = _done_T & _done_T_1; // @[TraceGen.scala:596:{24,44}, :597:24] assign io_finished_0 = done; // @[TraceGen.scala:212:7, :596:44] reg donePulse_REG; // @[TraceGen.scala:599:35] wire _donePulse_T = ~donePulse_REG; // @[TraceGen.scala:599:{27,35}] wire donePulse = done & _donePulse_T; // @[TraceGen.scala:596:44, :599:{24,27}]

Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }

module PriorityQueueStage_103( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundRawFNToRecFN_e8_s24_43( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_43 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_43( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [511:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [511:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_16 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_17 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_18 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_19 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_20 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_21 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_22 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_23 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_24 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_25 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_26 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_27 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_28 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_29 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_30 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_31 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [5:0] _mask_sizeOH_T_2 = 6'h0; // @[OneHot.scala:65:27] wire [5:0] a_first_beats1_decode = 6'h0; // @[Edges.scala:220:59] wire [5:0] a_first_beats1 = 6'h0; // @[Edges.scala:221:14] wire [5:0] a_first_count = 6'h0; // @[Edges.scala:234:25] wire [5:0] a_first_beats1_decode_1 = 6'h0; // @[Edges.scala:220:59] wire [5:0] a_first_beats1_1 = 6'h0; // @[Edges.scala:221:14] wire [5:0] a_first_count_1 = 6'h0; // @[Edges.scala:234:25] wire [5:0] c_first_beats1_decode = 6'h0; // @[Edges.scala:220:59] wire [5:0] c_first_beats1 = 6'h0; // @[Edges.scala:221:14] wire [5:0] _c_first_count_T = 6'h0; // @[Edges.scala:234:27] wire [5:0] c_first_count = 6'h0; // @[Edges.scala:234:25] wire [5:0] _c_first_counter_T = 6'h0; // @[Edges.scala:236:21] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_8_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_9_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_10_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_11_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_12_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_13_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_14_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_15_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_8_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_9_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_10_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_11_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_12_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_13_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_14_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_15_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_16_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_17_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_18_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_19_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_20_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_21_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_22_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_23_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_24_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_25_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_26_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_27_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_28_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_29_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_30_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_31_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_32 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_33 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_34 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_35 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_36 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_37 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_38 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_39 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_40 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_41 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_42 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_43 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_44 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_45 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_46 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_47 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_48 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_49 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_50 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_51 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_52 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_53 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_54 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_55 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_56 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_57 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_58 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_59 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_60 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_61 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_62 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_63 = 1'h1; // @[Misc.scala:215:29] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [5:0] c_first_counter1 = 6'h3F; // @[Edges.scala:230:28] wire [6:0] _c_first_counter1_T = 7'h7F; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [63:0] io_in_a_bits_mask = 64'hFFFFFFFFFFFFFFFF; // @[Monitor.scala:36:7] wire [63:0] mask = 64'hFFFFFFFFFFFFFFFF; // @[Misc.scala:222:10] wire [511:0] io_in_a_bits_data = 512'h0; // @[Monitor.scala:36:7] wire [511:0] _c_first_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_first_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_first_WIRE_2_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_first_WIRE_3_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_set_wo_ready_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_set_wo_ready_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_set_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_set_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_opcodes_set_interm_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_opcodes_set_interm_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_sizes_set_interm_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_sizes_set_interm_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_opcodes_set_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_opcodes_set_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_sizes_set_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_sizes_set_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_probe_ack_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_probe_ack_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _c_probe_ack_WIRE_2_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _c_probe_ack_WIRE_3_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _same_cycle_resp_WIRE_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _same_cycle_resp_WIRE_1_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _same_cycle_resp_WIRE_2_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _same_cycle_resp_WIRE_3_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [511:0] _same_cycle_resp_WIRE_4_bits_data = 512'h0; // @[Bundles.scala:265:74] wire [511:0] _same_cycle_resp_WIRE_5_bits_data = 512'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] mask_lo_lo_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi_hi = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [31:0] mask_lo = 32'hFFFFFFFF; // @[Misc.scala:222:10] wire [31:0] mask_hi = 32'hFFFFFFFF; // @[Misc.scala:222:10] wire [15:0] mask_lo_lo = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] mask_lo_hi = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] mask_hi_lo = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] mask_hi_hi = 16'hFFFF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [5:0] mask_sizeOH = 6'h1; // @[Misc.scala:202:81] wire [7:0] _mask_sizeOH_T_1 = 8'h40; // @[OneHot.scala:65:12] wire [2:0] mask_sizeOH_shiftAmount = 3'h6; // @[OneHot.scala:64:49] wire [5:0] _mask_sizeOH_T = 6'h6; // @[Misc.scala:202:34] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_sub_sub_bit = io_in_a_bits_address_0[5]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_4_2 = mask_sub_sub_sub_sub_2_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_5_2 = mask_sub_sub_sub_sub_2_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_6_2 = mask_sub_sub_sub_sub_3_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_7_2 = mask_sub_sub_sub_sub_3_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_8_2 = mask_sub_sub_sub_4_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_9_2 = mask_sub_sub_sub_4_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_10_2 = mask_sub_sub_sub_5_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_11_2 = mask_sub_sub_sub_5_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_12_2 = mask_sub_sub_sub_6_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_13_2 = mask_sub_sub_sub_6_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_14_2 = mask_sub_sub_sub_7_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_15_2 = mask_sub_sub_sub_7_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_16_2 = mask_sub_sub_8_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_17_2 = mask_sub_sub_8_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_18_2 = mask_sub_sub_9_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_19_2 = mask_sub_sub_9_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_20_2 = mask_sub_sub_10_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_21_2 = mask_sub_sub_10_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_22_2 = mask_sub_sub_11_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_23_2 = mask_sub_sub_11_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_24_2 = mask_sub_sub_12_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_25_2 = mask_sub_sub_12_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_26_2 = mask_sub_sub_13_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_27_2 = mask_sub_sub_13_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_28_2 = mask_sub_sub_14_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_29_2 = mask_sub_sub_14_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_30_2 = mask_sub_sub_15_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_31_2 = mask_sub_sub_15_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire mask_eq_32 = mask_sub_16_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_32 = mask_eq_32; // @[Misc.scala:214:27, :215:38] wire mask_eq_33 = mask_sub_16_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_33 = mask_eq_33; // @[Misc.scala:214:27, :215:38] wire mask_eq_34 = mask_sub_17_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_34 = mask_eq_34; // @[Misc.scala:214:27, :215:38] wire mask_eq_35 = mask_sub_17_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_35 = mask_eq_35; // @[Misc.scala:214:27, :215:38] wire mask_eq_36 = mask_sub_18_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_36 = mask_eq_36; // @[Misc.scala:214:27, :215:38] wire mask_eq_37 = mask_sub_18_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_37 = mask_eq_37; // @[Misc.scala:214:27, :215:38] wire mask_eq_38 = mask_sub_19_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_38 = mask_eq_38; // @[Misc.scala:214:27, :215:38] wire mask_eq_39 = mask_sub_19_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_39 = mask_eq_39; // @[Misc.scala:214:27, :215:38] wire mask_eq_40 = mask_sub_20_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_40 = mask_eq_40; // @[Misc.scala:214:27, :215:38] wire mask_eq_41 = mask_sub_20_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_41 = mask_eq_41; // @[Misc.scala:214:27, :215:38] wire mask_eq_42 = mask_sub_21_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_42 = mask_eq_42; // @[Misc.scala:214:27, :215:38] wire mask_eq_43 = mask_sub_21_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_43 = mask_eq_43; // @[Misc.scala:214:27, :215:38] wire mask_eq_44 = mask_sub_22_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_44 = mask_eq_44; // @[Misc.scala:214:27, :215:38] wire mask_eq_45 = mask_sub_22_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_45 = mask_eq_45; // @[Misc.scala:214:27, :215:38] wire mask_eq_46 = mask_sub_23_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_46 = mask_eq_46; // @[Misc.scala:214:27, :215:38] wire mask_eq_47 = mask_sub_23_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_47 = mask_eq_47; // @[Misc.scala:214:27, :215:38] wire mask_eq_48 = mask_sub_24_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_48 = mask_eq_48; // @[Misc.scala:214:27, :215:38] wire mask_eq_49 = mask_sub_24_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_49 = mask_eq_49; // @[Misc.scala:214:27, :215:38] wire mask_eq_50 = mask_sub_25_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_50 = mask_eq_50; // @[Misc.scala:214:27, :215:38] wire mask_eq_51 = mask_sub_25_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_51 = mask_eq_51; // @[Misc.scala:214:27, :215:38] wire mask_eq_52 = mask_sub_26_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_52 = mask_eq_52; // @[Misc.scala:214:27, :215:38] wire mask_eq_53 = mask_sub_26_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_53 = mask_eq_53; // @[Misc.scala:214:27, :215:38] wire mask_eq_54 = mask_sub_27_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_54 = mask_eq_54; // @[Misc.scala:214:27, :215:38] wire mask_eq_55 = mask_sub_27_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_55 = mask_eq_55; // @[Misc.scala:214:27, :215:38] wire mask_eq_56 = mask_sub_28_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_56 = mask_eq_56; // @[Misc.scala:214:27, :215:38] wire mask_eq_57 = mask_sub_28_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_57 = mask_eq_57; // @[Misc.scala:214:27, :215:38] wire mask_eq_58 = mask_sub_29_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_58 = mask_eq_58; // @[Misc.scala:214:27, :215:38] wire mask_eq_59 = mask_sub_29_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_59 = mask_eq_59; // @[Misc.scala:214:27, :215:38] wire mask_eq_60 = mask_sub_30_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_60 = mask_eq_60; // @[Misc.scala:214:27, :215:38] wire mask_eq_61 = mask_sub_30_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_61 = mask_eq_61; // @[Misc.scala:214:27, :215:38] wire mask_eq_62 = mask_sub_31_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_62 = mask_eq_62; // @[Misc.scala:214:27, :215:38] wire mask_eq_63 = mask_sub_31_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_63 = mask_eq_63; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [5:0] a_first_counter; // @[Edges.scala:229:27] wire [6:0] _a_first_counter1_T = {1'h0, a_first_counter} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] a_first_counter1 = _a_first_counter1_T[5:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 6'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 6'h1; // @[Edges.scala:229:27, :232:25] wire [5:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [5:0] _a_first_counter_T = a_first ? 6'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:6]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [5:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T = {1'h0, d_first_counter} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1 = _d_first_counter1_T[5:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [5:0] a_first_counter_1; // @[Edges.scala:229:27] wire [6:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] a_first_counter1_1 = _a_first_counter1_T_1[5:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 6'h1; // @[Edges.scala:229:27, :232:25] wire [5:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [5:0] _a_first_counter_T_1 = a_first_1 ? 6'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:6]; // @[package.scala:243:46] wire [5:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter_1; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1_1 = _d_first_counter1_T_1[5:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_1 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_2 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1138 = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1138 & _a_set_T[0]; // @[OneHot.scala:58:35] assign a_opcodes_set_interm = _T_1138 ? 4'h9 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:28] assign a_sizes_set_interm = _T_1138 ? 5'hD : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:28] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[package.scala:243:71] assign a_opcodes_set = _T_1138 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[package.scala:243:71] assign a_sizes_set = _T_1138 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_5 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_6 = 2'h1 << _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_6; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1184 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1153 = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :673:46, :674:74, :678:{25,70}] assign d_clr = _T_1153 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1153 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1153 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:6]; // @[package.scala:243:46] wire [5:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter_2; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1_2 = _d_first_counter1_T_2[5:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1238 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :783:46, :788:{25,70}] assign d_clr_1 = _T_1238 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1238 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1238 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File mshrs.scala: //****************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v3.common._ import boom.v3.exu.BrUpdateInfo import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc} class BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p) with HasL1HellaCacheParameters { // miss info val tag_match = Bool() val old_meta = new L1Metadata val way_en = UInt(nWays.W) // Used in the MSHRs val sdq_id = UInt(log2Ceil(cfg.nSDQ).W) } class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val id = Input(UInt()) val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) val req_sec_rdy = Output(Bool()) val clear_prefetch = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val req = Input(new BoomDCacheReqInternal) val req_is_probe = Input(Bool()) val idx = Output(Valid(UInt())) val way = Output(Valid(UInt())) val tag = Output(Valid(UInt())) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val wb_req = Decoupled(new WritebackReq(edge.bundle)) // To inform the prefetcher when we are commiting the fetch of this line val commit_val = Output(Bool()) val commit_addr = Output(UInt(coreMaxAddrBits.W)) val commit_coh = Output(new ClientMetadata) // Reading from the line buffer val lb_read = Decoupled(new LineBufferReadReq) val lb_resp = Input(UInt(encRowBits.W)) val lb_write = Decoupled(new LineBufferWriteReq) // Replays go through the cache pipeline again val replay = Decoupled(new BoomDCacheReqInternal) // Resp go straight out to the core val resp = Decoupled(new BoomDCacheResp) // Writeback unit tells us when it is done processing our wb val wb_resp = Input(Bool()) val probe_rdy = Output(Bool()) }) // TODO: Optimize this. We don't want to mess with cache during speculation // s_refill_req : Make a request for a new cache line // s_refill_resp : Store the refill response into our buffer // s_drain_rpq_loads : Drain out loads from the rpq // : If miss was misspeculated, go to s_invalid // s_wb_req : Write back the evicted cache line // s_wb_resp : Finish writing back the evicted cache line // s_meta_write_req : Write the metadata for new cache lne // s_meta_write_resp : val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18) val state = RegInit(s_invalid) val req = Reg(new BoomDCacheReqInternal) val req_idx = req.addr(untagBits-1, blockOffBits) val req_tag = req.addr >> untagBits val req_block_addr = (req.addr >> blockOffBits) << blockOffBits val req_needs_wb = RegInit(false.B) val new_coh = RegInit(ClientMetadata.onReset) val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH) val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2 val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param) // We only accept secondary misses if the original request had sufficient permissions val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) = new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd) val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe && !state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false)) rpq.io.brupdate := io.brupdate rpq.io.flush := io.exception assert(!(state === s_invalid && !rpq.io.empty)) rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) || (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd) rpq.io.enq.bits := io.req rpq.io.deq.ready := false.B val grantack = Reg(Valid(new TLBundleE(edge.bundle))) val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W)) val commit_line = Reg(Bool()) val grant_had_data = Reg(Bool()) val finish_to_prefetch = Reg(Bool()) // Block probes if a tag write we started is still in the pipeline val meta_hazard = RegInit(0.U(2.W)) when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U } when (io.meta_write.fire) { meta_hazard := 1.U } io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) || (state === s_meta_read && grantack.valid))) io.idx.valid := state =/= s_invalid io.tag.valid := state =/= s_invalid io.way.valid := !state.isOneOf(s_invalid, s_prefetch) io.idx.bits := req_idx io.tag.bits := req_tag io.way.bits := req.way_en io.meta_write.valid := false.B io.meta_write.bits := DontCare io.req_pri_rdy := false.B io.req_sec_rdy := sec_rdy && rpq.io.enq.ready io.mem_acquire.valid := false.B io.mem_acquire.bits := DontCare io.refill.valid := false.B io.refill.bits := DontCare io.replay.valid := false.B io.replay.bits := DontCare io.wb_req.valid := false.B io.wb_req.bits := DontCare io.resp.valid := false.B io.resp.bits := DontCare io.commit_val := false.B io.commit_addr := req.addr io.commit_coh := coh_on_grant io.meta_read.valid := false.B io.meta_read.bits := DontCare io.mem_finish.valid := false.B io.mem_finish.bits := DontCare io.lb_write.valid := false.B io.lb_write.bits := DontCare io.lb_read.valid := false.B io.lb_read.bits := DontCare io.mem_grant.ready := false.B when (io.req_sec_val && io.req_sec_rdy) { req.uop.mem_cmd := dirtier_cmd when (is_hit_again) { new_coh := dirtier_coh } } def handle_pri_req(old_state: UInt): UInt = { val new_state = WireInit(old_state) grantack.valid := false.B refill_ctr := 0.U assert(rpq.io.enq.ready) req := io.req val old_coh = io.req.old_meta.coh req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back when (io.req.tag_match) { val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // set dirty bit assert(isWrite(io.req.uop.mem_cmd)) new_coh := coh_on_hit new_state := s_drain_rpq } .otherwise { // upgrade permissions new_coh := old_coh new_state := s_refill_req } } .otherwise { // refill and writeback if necessary new_coh := ClientMetadata.onReset new_state := s_refill_req } new_state } when (state === s_invalid) { io.req_pri_rdy := true.B grant_had_data := false.B when (io.req_pri_val && io.req_pri_rdy) { state := handle_pri_req(state) } } .elsewhen (state === s_refill_req) { io.mem_acquire.valid := true.B // TODO: Use AcquirePerm if just doing permissions acquire io.mem_acquire.bits := edge.AcquireBlock( fromSource = io.id, toAddress = Cat(req_tag, req_idx) << blockOffBits, lgSize = lgCacheBlockBytes.U, growPermissions = grow_param)._2 when (io.mem_acquire.fire) { state := s_refill_resp } } .elsewhen (state === s_refill_resp) { when (edge.hasData(io.mem_grant.bits)) { io.mem_grant.ready := io.lb_write.ready io.lb_write.valid := io.mem_grant.valid io.lb_write.bits.id := io.id io.lb_write.bits.offset := refill_address_inc >> rowOffBits io.lb_write.bits.data := io.mem_grant.bits.data } .otherwise { io.mem_grant.ready := true.B } when (io.mem_grant.fire) { grant_had_data := edge.hasData(io.mem_grant.bits) } when (refill_done) { grantack.valid := edge.isRequest(io.mem_grant.bits) grantack.bits := edge.GrantAck(io.mem_grant.bits) state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq) assert(!(!grant_had_data && req_needs_wb)) commit_line := false.B new_coh := coh_on_grant } } .elsewhen (state === s_drain_rpq_loads) { val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) && !isWrite(rpq.io.deq.bits.uop.mem_cmd) && (rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay // drain all loads for now val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWords*coreDataBytes)-1, log2Up(wordBytes)) val data = io.lb_resp val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W)) val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed, Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)), data_word, false.B, wordBytes) rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load io.lb_read.valid := rpq.io.deq.valid && drain_load io.lb_read.bits.id := io.id io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load io.resp.bits.uop := rpq.io.deq.bits.uop io.resp.bits.data := loadgen.data io.resp.bits.is_hella := rpq.io.deq.bits.is_hella when (rpq.io.deq.fire) { commit_line := true.B } .elsewhen (rpq.io.empty && !commit_line) { when (!rpq.io.enq.fire) { state := s_mem_finish_1 finish_to_prefetch := enablePrefetching.B } } .elsewhen (rpq.io.empty || (rpq.io.deq.valid && !drain_load)) { // io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired // The prefetcher should consider fetching the next line io.commit_val := true.B state := s_meta_read } } .elsewhen (state === s_meta_read) { io.meta_read.valid := !io.prober_state.valid || !grantack.valid || (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx) io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := req.way_en when (io.meta_read.fire) { state := s_meta_resp_1 } } .elsewhen (state === s_meta_resp_1) { state := s_meta_resp_2 } .elsewhen (state === s_meta_resp_2) { val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1 state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read Mux(needs_wb, s_meta_clear, s_commit_line)) } .elsewhen (state === s_meta_clear) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := coh_on_clear io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_wb_req } } .elsewhen (state === s_wb_req) { io.wb_req.valid := true.B io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.param := shrink_param io.wb_req.bits.way_en := req.way_en io.wb_req.bits.source := io.id io.wb_req.bits.voluntary := true.B when (io.wb_req.fire) { state := s_wb_resp } } .elsewhen (state === s_wb_resp) { when (io.wb_resp) { state := s_commit_line } } .elsewhen (state === s_commit_line) { io.lb_read.valid := true.B io.lb_read.bits.id := io.id io.lb_read.bits.offset := refill_ctr io.refill.valid := io.lb_read.fire io.refill.bits.addr := req_block_addr | (refill_ctr << rowOffBits) io.refill.bits.way_en := req.way_en io.refill.bits.wmask := ~(0.U(rowWords.W)) io.refill.bits.data := io.lb_resp when (io.refill.fire) { refill_ctr := refill_ctr + 1.U when (refill_ctr === (cacheDataBeats - 1).U) { state := s_drain_rpq } } } .elsewhen (state === s_drain_rpq) { io.replay <> rpq.io.deq io.replay.bits.way_en := req.way_en io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) { // Set dirty bit val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd) assert(is_hit, "We still don't have permissions for this store") new_coh := coh_on_hit } when (rpq.io.empty && !rpq.io.enq.valid) { state := s_meta_write_req } } .elsewhen (state === s_meta_write_req) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := new_coh io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_mem_finish_1 finish_to_prefetch := false.B } } .elsewhen (state === s_mem_finish_1) { io.mem_finish.valid := grantack.valid io.mem_finish.bits := grantack.bits when (io.mem_finish.fire || !grantack.valid) { grantack.valid := false.B state := s_mem_finish_2 } } .elsewhen (state === s_mem_finish_2) { state := Mux(finish_to_prefetch, s_prefetch, s_invalid) } .elsewhen (state === s_prefetch) { io.req_pri_rdy := true.B when ((io.req_sec_val && !io.req_sec_rdy) || io.clear_prefetch) { state := s_invalid } .elsewhen (io.req_sec_val && io.req_sec_rdy) { val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // Proceed with refill new_coh := coh_on_hit state := s_meta_read } .otherwise { // Reacquire this line new_coh := ClientMetadata.onReset state := s_refill_req } } .elsewhen (io.req_pri_val && io.req_pri_rdy) { grant_had_data := false.B state := handle_pri_req(state) } } } class BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Decoupled(new BoomDCacheReq)) val resp = Decoupled(new BoomDCacheResp) val mem_access = Decoupled(new TLBundleA(edge.bundle)) val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle))) // We don't need brupdate in here because uncacheable operations are guaranteed non-speculative }) def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits) def wordFromBeat(addr: UInt, dat: UInt) = { val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W)) (dat >> shift)(wordBits-1, 0) } val req = Reg(new BoomDCacheReq) val grant_word = Reg(UInt(wordBits.W)) val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.req.ready := state === s_idle val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes) val a_source = id.U val a_address = req.addr val a_size = req.uop.mem_size val a_data = Fill(beatWords, req.data) val get = edge.Get(a_source, a_address, a_size)._2 val put = edge.Put(a_source, a_address, a_size, a_data)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array( M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert(state === s_idle || !isAMO(req.uop.mem_cmd)) (0.U).asTypeOf(new TLBundleA(edge.bundle)) } assert(state === s_idle || req.uop.mem_cmd =/= M_XSC) io.mem_access.valid := state === s_mem_access io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put)) val send_resp = isRead(req.uop.mem_cmd) io.resp.valid := (state === s_resp) && send_resp io.resp.bits.is_hella := req.is_hella io.resp.bits.uop := req.uop io.resp.bits.data := loadgen.data when (io.req.fire) { req := io.req.bits state := s_mem_access } when (io.mem_access.fire) { state := s_mem_ack } when (state === s_mem_ack && io.mem_ack.valid) { state := s_resp when (isRead(req.uop.mem_cmd)) { grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data) } } when (state === s_resp) { when (!send_resp || io.resp.fire) { state := s_idle } } } class LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val id = UInt(log2Ceil(nLBEntries).W) val offset = UInt(log2Ceil(cacheDataBeats).W) def lb_addr = Cat(id, offset) } class LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p) { val data = UInt(encRowBits.W) } class LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p) { val id = UInt(log2Ceil(nLBEntries).W) val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe val req_is_probe = Input(Vec(memWidth, Bool())) val resp = Decoupled(new BoomDCacheResp) val secondary_miss = Output(Vec(memWidth, Bool())) val block_hit = Output(Vec(memWidth, Bool())) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val replay = Decoupled(new BoomDCacheReqInternal) val prefetch = Decoupled(new BoomDCacheReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence val wb_resp = Input(Bool()) val fence_rdy = Output(Bool()) val probe_rdy = Output(Bool()) }) val req_idx = OHToUInt(io.req.map(_.valid)) val req = io.req(req_idx) val req_is_probe = io.req_is_probe(0) for (w <- 0 until memWidth) io.req(w).ready := false.B val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher) else Module(new NullPrefetcher) io.prefetch <> prefetcher.io.prefetch val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U) // -------------------- // The MSHR SDQ val sdq_val = RegInit(0.U(cfg.nSDQ.W)) val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0)) val sdq_rdy = !sdq_val.andR val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd) val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W)) when (sdq_enq) { sdq(sdq_alloc_id) := req.bits.data } // -------------------- // The LineBuffer Data // Holds refilling lines, prefetched lines val lb = Mem(nLBEntries * cacheDataBeats, UInt(encRowBits.W)) val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs)) val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs)) lb_read_arb.io.out.ready := false.B lb_write_arb.io.out.ready := true.B val lb_read_data = WireInit(0.U(encRowBits.W)) when (lb_write_arb.io.out.fire) { lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data) } .otherwise { lb_read_arb.io.out.ready := true.B when (lb_read_arb.io.out.fire) { lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr) } } def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w))) val idx_match = widthMap(w => idx_matches(w).reduce(_||_)) val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w))) val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W))) val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs)) val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs)) val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs)) val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs)) val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs)) val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs)) val commit_vals = Wire(Vec(cfg.nMSHRs, Bool())) val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W))) val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata)) var sec_rdy = false.B io.fence_rdy := true.B io.probe_rdy := true.B io.mem_grant.ready := false.B val mshr_alloc_idx = Wire(UInt()) val pri_rdy = WireInit(false.B) val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx) val mshrs = (0 until cfg.nMSHRs) map { i => val mshr = Module(new BoomMSHR) mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W) for (w <- 0 until memWidth) { idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits) tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en } wb_tag_list(i) := mshr.io.wb_req.bits.tag mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val when (i.U === mshr_alloc_idx) { pri_rdy := mshr.io.req_pri_rdy } mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable mshr.io.req := req.bits mshr.io.req_is_probe := req_is_probe mshr.io.req.sdq_id := sdq_alloc_id // Clear because of a FENCE, a request to the same idx as a prefetched line, // a probe to that prefetched line, all mshrs are in use mshr.io.clear_prefetch := ((io.clear_all && !req.valid)|| (req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) || (req_is_probe && idx_matches(req_idx)(i))) mshr.io.brupdate := io.brupdate mshr.io.exception := io.exception mshr.io.rob_pnr_idx := io.rob_pnr_idx mshr.io.rob_head_idx := io.rob_head_idx mshr.io.prober_state := io.prober_state mshr.io.wb_resp := io.wb_resp meta_write_arb.io.in(i) <> mshr.io.meta_write meta_read_arb.io.in(i) <> mshr.io.meta_read mshr.io.meta_resp := io.meta_resp wb_req_arb.io.in(i) <> mshr.io.wb_req replay_arb.io.in(i) <> mshr.io.replay refill_arb.io.in(i) <> mshr.io.refill lb_read_arb.io.in(i) <> mshr.io.lb_read mshr.io.lb_resp := lb_read_data lb_write_arb.io.in(i) <> mshr.io.lb_write commit_vals(i) := mshr.io.commit_val commit_addrs(i) := mshr.io.commit_addr commit_cohs(i) := mshr.io.commit_coh mshr.io.mem_grant.valid := false.B mshr.io.mem_grant.bits := DontCare when (io.mem_grant.bits.source === i.U) { mshr.io.mem_grant <> io.mem_grant } sec_rdy = sec_rdy || (mshr.io.req_sec_rdy && mshr.io.req_sec_val) resp_arb.io.in(i) <> mshr.io.resp when (!mshr.io.req_pri_rdy) { io.fence_rdy := false.B } for (w <- 0 until memWidth) { when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) { io.probe_rdy := false.B } } mshr } // Try to round-robin the MSHRs val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W)) mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head)) when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) } io.meta_write <> meta_write_arb.io.out io.meta_read <> meta_read_arb.io.out io.wb_req <> wb_req_arb.io.out val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs)) var mmio_rdy = false.B val mmios = (0 until nIOMSHRs) map { i => val id = cfg.nMSHRs + 1 + i // +1 for wb unit val mshr = Module(new BoomIOMSHR(id)) mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready mmio_alloc_arb.io.in(i).bits := DontCare mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready mshr.io.req.bits := req.bits mmio_rdy = mmio_rdy || mshr.io.req.ready mshr.io.mem_ack.bits := io.mem_grant.bits mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U when (io.mem_grant.bits.source === id.U) { io.mem_grant.ready := true.B } resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp when (!mshr.io.req.ready) { io.fence_rdy := false.B } mshr } mmio_alloc_arb.io.out.ready := req.valid && !cacheable TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access)) TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish)) val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false)) respq.io.brupdate := io.brupdate respq.io.flush := io.exception respq.io.enq <> resp_arb.io.out io.resp <> respq.io.deq for (w <- 0 until memWidth) { io.req(w).ready := (w.U === req_idx) && Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy)) io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w) io.block_hit(w) := idx_match(w) && tag_match(w) } io.refill <> refill_arb.io.out val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd) io.replay <> replay_arb.io.out io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id) when (io.replay.valid || sdq_enq) { sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) | PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq) } prefetcher.io.mshr_avail := RegNext(pri_rdy) prefetcher.io.req_val := RegNext(commit_vals.reduce(_||_)) prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs)) prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize*8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) | Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and || logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out | ~wmask & io.lhs io.out_unmasked := out }

module BoomIOMSHR( // @[mshrs.scala:402:7] input clock, // @[mshrs.scala:402:7] input reset, // @[mshrs.scala:402:7] output io_req_ready, // @[mshrs.scala:405:14] input io_req_valid, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_uopc, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_inst, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_debug_inst, // @[mshrs.scala:405:14] input io_req_bits_uop_is_rvc, // @[mshrs.scala:405:14] input [39:0] io_req_bits_uop_debug_pc, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_iq_type, // @[mshrs.scala:405:14] input [9:0] io_req_bits_uop_fu_code, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_iw_state, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_is_br, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jalr, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jal, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sfb, // @[mshrs.scala:405:14] input [15:0] io_req_bits_uop_br_mask, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_br_tag, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ftq_idx, // @[mshrs.scala:405:14] input io_req_bits_uop_edge_inst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_pc_lob, // @[mshrs.scala:405:14] input io_req_bits_uop_taken, // @[mshrs.scala:405:14] input [19:0] io_req_bits_uop_imm_packed, // @[mshrs.scala:405:14] input [11:0] io_req_bits_uop_csr_addr, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_rob_idx, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ldq_idx, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_stq_idx, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_rxq_idx, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_pdst, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs1, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs2, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs3, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ppred, // @[mshrs.scala:405:14] input io_req_bits_uop_prs1_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs2_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs3_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_ppred_busy, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_stale_pdst, // @[mshrs.scala:405:14] input io_req_bits_uop_exception, // @[mshrs.scala:405:14] input [63:0] io_req_bits_uop_exc_cause, // @[mshrs.scala:405:14] input io_req_bits_uop_bypassable, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_mem_cmd, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_mem_size, // @[mshrs.scala:405:14] input io_req_bits_uop_mem_signed, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fence, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fencei, // @[mshrs.scala:405:14] input io_req_bits_uop_is_amo, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_ldq, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_stq, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] input io_req_bits_uop_is_unique, // @[mshrs.scala:405:14] input io_req_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_ldst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs2, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs3, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_val, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_dst_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] input io_req_bits_uop_frs3_en, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_val, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_single, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] input [39:0] io_req_bits_addr, // @[mshrs.scala:405:14] input [63:0] io_req_bits_data, // @[mshrs.scala:405:14] input io_req_bits_is_hella, // @[mshrs.scala:405:14] input io_resp_ready, // @[mshrs.scala:405:14] output io_resp_valid, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:405:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:405:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:405:14] output [15:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:405:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:405:14] output io_resp_bits_uop_taken, // @[mshrs.scala:405:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:405:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:405:14] output io_resp_bits_uop_exception, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:405:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:405:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:405:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:405:14] output io_resp_bits_is_hella, // @[mshrs.scala:405:14] input io_mem_access_ready, // @[mshrs.scala:405:14] output io_mem_access_valid, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_opcode, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_param, // @[mshrs.scala:405:14] output [3:0] io_mem_access_bits_size, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_source, // @[mshrs.scala:405:14] output [31:0] io_mem_access_bits_address, // @[mshrs.scala:405:14] output [15:0] io_mem_access_bits_mask, // @[mshrs.scala:405:14] output [127:0] io_mem_access_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_valid, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_opcode, // @[mshrs.scala:405:14] input [1:0] io_mem_ack_bits_param, // @[mshrs.scala:405:14] input [3:0] io_mem_ack_bits_size, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_source, // @[mshrs.scala:405:14] input [3:0] io_mem_ack_bits_sink, // @[mshrs.scala:405:14] input io_mem_ack_bits_denied, // @[mshrs.scala:405:14] input [127:0] io_mem_ack_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_bits_corrupt // @[mshrs.scala:405:14] ); wire io_req_valid_0 = io_req_valid; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[mshrs.scala:402:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[mshrs.scala:402:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[mshrs.scala:402:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[mshrs.scala:402:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[mshrs.scala:402:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[mshrs.scala:402:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[mshrs.scala:402:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[mshrs.scala:402:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[mshrs.scala:402:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[mshrs.scala:402:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[mshrs.scala:402:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[mshrs.scala:402:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[mshrs.scala:402:7] wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[mshrs.scala:402:7] wire io_req_bits_is_hella_0 = io_req_bits_is_hella; // @[mshrs.scala:402:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:402:7] wire io_mem_access_ready_0 = io_mem_access_ready; // @[mshrs.scala:402:7] wire io_mem_ack_valid_0 = io_mem_ack_valid; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_opcode_0 = io_mem_ack_bits_opcode; // @[mshrs.scala:402:7] wire [1:0] io_mem_ack_bits_param_0 = io_mem_ack_bits_param; // @[mshrs.scala:402:7] wire [3:0] io_mem_ack_bits_size_0 = io_mem_ack_bits_size; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_source_0 = io_mem_ack_bits_source; // @[mshrs.scala:402:7] wire [3:0] io_mem_ack_bits_sink_0 = io_mem_ack_bits_sink; // @[mshrs.scala:402:7] wire io_mem_ack_bits_denied_0 = io_mem_ack_bits_denied; // @[mshrs.scala:402:7] wire [127:0] io_mem_ack_bits_data_0 = io_mem_ack_bits_data; // @[mshrs.scala:402:7] wire io_mem_ack_bits_corrupt_0 = io_mem_ack_bits_corrupt; // @[mshrs.scala:402:7] wire io_mem_access_bits_corrupt = 1'h0; // @[mshrs.scala:402:7] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire get_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_74 = 1'h0; // @[Parameters.scala:684:54] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire put_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_WIRE_corrupt = 1'h0; // @[mshrs.scala:439:46] wire _atomics_legal_T_34 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_40 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_93 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_99 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_152 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_158 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_2 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_211 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_217 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_3 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_270 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_276 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_4 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_329 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_335 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_5 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_388 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_394 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_6 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_447 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_453 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_7 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_506 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_512 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_8 = 1'h0; // @[Misc.scala:206:21] wire _atomics_T_1_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_3_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_5_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_7_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_9_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_11_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_13_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_15_corrupt = 1'h0; // @[mshrs.scala:439:75] wire atomics_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_42_corrupt = 1'h0; // @[mshrs.scala:457:66] wire _io_mem_access_bits_T_43_corrupt = 1'h0; // @[mshrs.scala:457:29] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire [2:0] get_source = 3'h5; // @[Edges.scala:460:17] wire [2:0] put_source = 3'h5; // @[Edges.scala:480:17] wire [2:0] atomics_a_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_source = 3'h5; // @[mshrs.scala:457:66] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[mshrs.scala:439:46] wire [2:0] _atomics_WIRE_param = 3'h0; // @[mshrs.scala:439:46] wire [2:0] _atomics_WIRE_source = 3'h0; // @[mshrs.scala:439:46] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_param = 3'h0; // @[mshrs.scala:457:66] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_41 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_42 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_43 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_44 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_59 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_60 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_61 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_62 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_100 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_101 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_102 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_103 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_118 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_119 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_120 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_121 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_159 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_160 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_161 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_177 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_178 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_179 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_180 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_220 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_221 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_236 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_237 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_238 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_239 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_277 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_278 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_279 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_280 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_295 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_296 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_297 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_298 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_336 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_337 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_338 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_339 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_354 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_355 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_356 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_357 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_395 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_396 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_397 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_398 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_413 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_414 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_415 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_416 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_454 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_455 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_456 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_457 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_472 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_473 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_474 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_475 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_513 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_514 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_515 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_516 = 1'h1; // @[Parameters.scala:684:29] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [127:0] get_data = 128'h0; // @[Edges.scala:460:17] wire [127:0] _atomics_WIRE_data = 128'h0; // @[mshrs.scala:439:46] wire [15:0] _atomics_WIRE_mask = 16'h0; // @[mshrs.scala:439:46] wire [31:0] _atomics_WIRE_address = 32'h0; // @[mshrs.scala:439:46] wire [3:0] _atomics_WIRE_size = 4'h0; // @[mshrs.scala:439:46] wire _io_req_ready_T; // @[mshrs.scala:427:25] wire _io_resp_valid_T_1; // @[mshrs.scala:461:43] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_mem_access_valid_T; // @[mshrs.scala:456:32] wire [2:0] _io_mem_access_bits_T_43_opcode; // @[mshrs.scala:457:29] wire [2:0] _io_mem_access_bits_T_43_param; // @[mshrs.scala:457:29] wire [3:0] _io_mem_access_bits_T_43_size; // @[mshrs.scala:457:29] wire [2:0] _io_mem_access_bits_T_43_source; // @[mshrs.scala:457:29] wire [31:0] _io_mem_access_bits_T_43_address; // @[mshrs.scala:457:29] wire [15:0] _io_mem_access_bits_T_43_mask; // @[mshrs.scala:457:29] wire [127:0] _io_mem_access_bits_T_43_data; // @[mshrs.scala:457:29] wire io_req_ready_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:402:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:402:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:402:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:402:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:402:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:402:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:402:7] wire io_resp_valid_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_opcode_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_param_0; // @[mshrs.scala:402:7] wire [3:0] io_mem_access_bits_size_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_source_0; // @[mshrs.scala:402:7] wire [31:0] io_mem_access_bits_address_0; // @[mshrs.scala:402:7] wire [15:0] io_mem_access_bits_mask_0; // @[mshrs.scala:402:7] wire [127:0] io_mem_access_bits_data_0; // @[mshrs.scala:402:7] wire io_mem_access_valid_0; // @[mshrs.scala:402:7] reg [6:0] req_uop_uopc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uopc_0 = req_uop_uopc; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_inst_0 = req_uop_inst; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_inst_0 = req_uop_debug_inst; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_rvc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_rvc_0 = req_uop_is_rvc; // @[mshrs.scala:402:7, :421:16] reg [39:0] req_uop_debug_pc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_pc_0 = req_uop_debug_pc; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_iq_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iq_type_0 = req_uop_iq_type; // @[mshrs.scala:402:7, :421:16] reg [9:0] req_uop_fu_code; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fu_code_0 = req_uop_fu_code; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_br_type_0 = req_uop_ctrl_br_type; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op1_sel_0 = req_uop_ctrl_op1_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op2_sel_0 = req_uop_ctrl_op2_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_imm_sel_0 = req_uop_ctrl_imm_sel; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op_fcn_0 = req_uop_ctrl_op_fcn; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_fcn_dw_0 = req_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_csr_cmd_0 = req_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_load; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_load_0 = req_uop_ctrl_is_load; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_sta; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_sta_0 = req_uop_ctrl_is_sta; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_std; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_std_0 = req_uop_ctrl_is_std; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_iw_state; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_state_0 = req_uop_iw_state; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p1_poisoned_0 = req_uop_iw_p1_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p2_poisoned_0 = req_uop_iw_p2_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_br; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_br_0 = req_uop_is_br; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jalr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jalr_0 = req_uop_is_jalr; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jal; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jal_0 = req_uop_is_jal; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sfb; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sfb_0 = req_uop_is_sfb; // @[mshrs.scala:402:7, :421:16] reg [15:0] req_uop_br_mask; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_mask_0 = req_uop_br_mask; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_br_tag; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_tag_0 = req_uop_br_tag; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ftq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ftq_idx_0 = req_uop_ftq_idx; // @[mshrs.scala:402:7, :421:16] reg req_uop_edge_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_edge_inst_0 = req_uop_edge_inst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pc_lob_0 = req_uop_pc_lob; // @[mshrs.scala:402:7, :421:16] reg req_uop_taken; // @[mshrs.scala:421:16] assign io_resp_bits_uop_taken_0 = req_uop_taken; // @[mshrs.scala:402:7, :421:16] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_imm_packed_0 = req_uop_imm_packed; // @[mshrs.scala:402:7, :421:16] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_csr_addr_0 = req_uop_csr_addr; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_rob_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rob_idx_0 = req_uop_rob_idx; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ldq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldq_idx_0 = req_uop_ldq_idx; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_stq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stq_idx_0 = req_uop_stq_idx; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rxq_idx_0 = req_uop_rxq_idx; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pdst_0 = req_uop_pdst; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_0 = req_uop_prs1; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_0 = req_uop_prs2; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_0 = req_uop_prs3; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ppred; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_0 = req_uop_ppred; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs1_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_busy_0 = req_uop_prs1_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs2_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_busy_0 = req_uop_prs2_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs3_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_busy_0 = req_uop_prs3_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_ppred_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_busy_0 = req_uop_ppred_busy; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stale_pdst_0 = req_uop_stale_pdst; // @[mshrs.scala:402:7, :421:16] reg req_uop_exception; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exception_0 = req_uop_exception; // @[mshrs.scala:402:7, :421:16] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exc_cause_0 = req_uop_exc_cause; // @[mshrs.scala:402:7, :421:16] reg req_uop_bypassable; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bypassable_0 = req_uop_bypassable; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_cmd_0 = req_uop_mem_cmd; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_mem_size; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_size_0 = req_uop_mem_size; // @[mshrs.scala:402:7, :421:16] wire [1:0] size = req_uop_mem_size; // @[AMOALU.scala:11:18] reg req_uop_mem_signed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_signed_0 = req_uop_mem_signed; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fence; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fence_0 = req_uop_is_fence; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fencei; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fencei_0 = req_uop_is_fencei; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_amo; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_amo_0 = req_uop_is_amo; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_ldq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_ldq_0 = req_uop_uses_ldq; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_stq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_stq_0 = req_uop_uses_stq; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sys_pc2epc_0 = req_uop_is_sys_pc2epc; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_unique; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_unique_0 = req_uop_is_unique; // @[mshrs.scala:402:7, :421:16] reg req_uop_flush_on_commit; // @[mshrs.scala:421:16] assign io_resp_bits_uop_flush_on_commit_0 = req_uop_flush_on_commit; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_is_rs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_is_rs1_0 = req_uop_ldst_is_rs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_ldst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_0 = req_uop_ldst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_0 = req_uop_lrs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_0 = req_uop_lrs2; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs3_0 = req_uop_lrs3; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_val_0 = req_uop_ldst_val; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_dst_rtype_0 = req_uop_dst_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_rtype_0 = req_uop_lrs1_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_rtype_0 = req_uop_lrs2_rtype; // @[mshrs.scala:402:7, :421:16] reg req_uop_frs3_en; // @[mshrs.scala:421:16] assign io_resp_bits_uop_frs3_en_0 = req_uop_frs3_en; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_val_0 = req_uop_fp_val; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_single; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_single_0 = req_uop_fp_single; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_pf_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_pf_if_0 = req_uop_xcpt_pf_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ae_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ae_if_0 = req_uop_xcpt_ae_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ma_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ma_if_0 = req_uop_xcpt_ma_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_debug_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_debug_if_0 = req_uop_bp_debug_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_xcpt_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_xcpt_if_0 = req_uop_bp_xcpt_if; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_fsrc_0 = req_uop_debug_fsrc; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_tsrc_0 = req_uop_debug_tsrc; // @[mshrs.scala:402:7, :421:16] reg [39:0] req_addr; // @[mshrs.scala:421:16] wire [39:0] _get_legal_T_14 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_14 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_4 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_63 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_122 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_181 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_240 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_299 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_358 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_417 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_476 = req_addr; // @[Parameters.scala:137:31] reg [63:0] req_data; // @[mshrs.scala:421:16] reg req_is_hella; // @[mshrs.scala:421:16] assign io_resp_bits_is_hella_0 = req_is_hella; // @[mshrs.scala:402:7, :421:16] reg [63:0] grant_word; // @[mshrs.scala:422:23] reg [1:0] state; // @[mshrs.scala:426:22] assign _io_req_ready_T = state == 2'h0; // @[mshrs.scala:426:22, :427:25] assign io_req_ready_0 = _io_req_ready_T; // @[mshrs.scala:402:7, :427:25] wire [127:0] a_data = {2{req_data}}; // @[mshrs.scala:421:16, :434:23] wire [127:0] put_data = a_data; // @[Edges.scala:480:17] wire [127:0] atomics_a_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_1_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_2_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_3_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_4_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_5_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_6_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_7_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_8_data = a_data; // @[Edges.scala:517:17] wire [39:0] _GEN = {req_addr[39:14], req_addr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_68 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_0 = {req_addr[39:17], req_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_69; // @[Parameters.scala:137:31] assign _put_legal_T_69 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_35; // @[Parameters.scala:137:31] assign _atomics_legal_T_35 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_94; // @[Parameters.scala:137:31] assign _atomics_legal_T_94 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_153; // @[Parameters.scala:137:31] assign _atomics_legal_T_153 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_212; // @[Parameters.scala:137:31] assign _atomics_legal_T_212 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_271; // @[Parameters.scala:137:31] assign _atomics_legal_T_271 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_330; // @[Parameters.scala:137:31] assign _atomics_legal_T_330 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_389; // @[Parameters.scala:137:31] assign _atomics_legal_T_389 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_448; // @[Parameters.scala:137:31] assign _atomics_legal_T_448 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_507; // @[Parameters.scala:137:31] assign _atomics_legal_T_507 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {req_addr[39:26], req_addr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {req_addr[39:28], req_addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31] assign _put_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_45; // @[Parameters.scala:137:31] assign _atomics_legal_T_45 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_104; // @[Parameters.scala:137:31] assign _atomics_legal_T_104 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_163; // @[Parameters.scala:137:31] assign _atomics_legal_T_163 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_222; // @[Parameters.scala:137:31] assign _atomics_legal_T_222 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_281; // @[Parameters.scala:137:31] assign _atomics_legal_T_281 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_340; // @[Parameters.scala:137:31] assign _atomics_legal_T_340 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_399; // @[Parameters.scala:137:31] assign _atomics_legal_T_399 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_458; // @[Parameters.scala:137:31] assign _atomics_legal_T_458 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_517; // @[Parameters.scala:137:31] assign _atomics_legal_T_517 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {req_addr[39:29], req_addr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31] assign _get_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31] assign _put_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31] assign _atomics_legal_T_24 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31] assign _atomics_legal_T_142 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_201; // @[Parameters.scala:137:31] assign _atomics_legal_T_201 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_260; // @[Parameters.scala:137:31] assign _atomics_legal_T_260 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_319; // @[Parameters.scala:137:31] assign _atomics_legal_T_319 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_378; // @[Parameters.scala:137:31] assign _atomics_legal_T_378 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_437; // @[Parameters.scala:137:31] assign _atomics_legal_T_437 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_496; // @[Parameters.scala:137:31] assign _atomics_legal_T_496 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46] wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_4 = {req_addr[39:29], req_addr[28:0] ^ 29'h10012000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31] assign _get_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31] assign _put_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46] wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] get_address = req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] atomics_a_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [39:0] _GEN_5 = {req_addr[39:32], req_addr[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_54; // @[Parameters.scala:137:31] assign _get_legal_T_54 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_54; // @[Parameters.scala:137:31] assign _put_legal_T_54 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_50; // @[Parameters.scala:137:31] assign _atomics_legal_T_50 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_109; // @[Parameters.scala:137:31] assign _atomics_legal_T_109 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_168; // @[Parameters.scala:137:31] assign _atomics_legal_T_168 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_227; // @[Parameters.scala:137:31] assign _atomics_legal_T_227 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_286; // @[Parameters.scala:137:31] assign _atomics_legal_T_286 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_345; // @[Parameters.scala:137:31] assign _atomics_legal_T_345 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_404; // @[Parameters.scala:137:31] assign _atomics_legal_T_404 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_463; // @[Parameters.scala:137:31] assign _atomics_legal_T_463 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_522; // @[Parameters.scala:137:31] assign _atomics_legal_T_522 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_55 = {1'h0, _get_legal_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_56 = _get_legal_T_55 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_57 = _get_legal_T_56; // @[Parameters.scala:137:46] wire _get_legal_T_58 = _get_legal_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_59 = _get_legal_T_18 | _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_60 = _get_legal_T_59 | _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_61 = _get_legal_T_60 | _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_62 = _get_legal_T_61 | _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_63 = _get_legal_T_62 | _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_64 = _get_legal_T_63 | _get_legal_T_48; // @[Parameters.scala:685:42] wire _get_legal_T_65 = _get_legal_T_64 | _get_legal_T_53; // @[Parameters.scala:685:42] wire _get_legal_T_66 = _get_legal_T_65 | _get_legal_T_58; // @[Parameters.scala:685:42] wire _get_legal_T_67 = _get_legal_T_66; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_68 | _get_legal_T_67; // @[Parameters.scala:684:54, :686:26] wire [15:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [15:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_6 = {2'h0, req_uop_mem_size}; // @[Edges.scala:463:15] assign get_size = _GEN_6; // @[Edges.scala:460:17, :463:15] wire [3:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_6; // @[Edges.scala:463:15, :480:17] wire [3:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_6; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_6; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_6; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_6; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_6; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_6; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_6; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_6; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_6; // @[Misc.scala:202:34] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_6; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_6; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_size = get_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_sub_bit = req_addr[3]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_sub_bit = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_1 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_2 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_3 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_4 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_5 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_6 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_7 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_8 = req_addr[3]; // @[Misc.scala:210:26] wire _grant_word_shift_T = req_addr[3]; // @[package.scala:163:13] wire get_a_mask_sub_sub_sub_1_2 = get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_sub_nbit = ~get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_sub_0_2 = get_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_sub_acc_T = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_0_1 = _get_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _get_a_mask_sub_sub_sub_acc_T_1 = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_1_1 = _get_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = req_addr[2]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T = req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_2_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T_2 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_2_1 = get_a_mask_sub_sub_sub_1_1 | _get_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_3_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_3 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_3_1 = get_a_mask_sub_sub_sub_1_1 | _get_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = req_addr[1]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_3 = req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_4_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_4 = get_a_mask_sub_size & get_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_4_1 = get_a_mask_sub_sub_2_1 | _get_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_5_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_5 = get_a_mask_sub_size & get_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_5_1 = get_a_mask_sub_sub_2_1 | _get_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_6_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_6 = get_a_mask_sub_size & get_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_6_1 = get_a_mask_sub_sub_3_1 | _get_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_7_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_7 = get_a_mask_sub_size & get_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_7_1 = get_a_mask_sub_sub_3_1 | _get_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = req_addr[0]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_6 = req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 | _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_8 = get_a_mask_sub_4_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_8 = get_a_mask_size & get_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_8 = get_a_mask_sub_4_1 | _get_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_9 = get_a_mask_sub_4_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_9 = get_a_mask_size & get_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_9 = get_a_mask_sub_4_1 | _get_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_10 = get_a_mask_sub_5_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_10 = get_a_mask_size & get_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_10 = get_a_mask_sub_5_1 | _get_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_11 = get_a_mask_sub_5_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_11 = get_a_mask_size & get_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_11 = get_a_mask_sub_5_1 | _get_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_12 = get_a_mask_sub_6_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_12 = get_a_mask_size & get_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_12 = get_a_mask_sub_6_1 | _get_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_13 = get_a_mask_sub_6_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_13 = get_a_mask_size & get_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_13 = get_a_mask_sub_6_1 | _get_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_14 = get_a_mask_sub_7_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_14 = get_a_mask_size & get_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_14 = get_a_mask_sub_7_1 | _get_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_15 = get_a_mask_sub_7_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_15 = get_a_mask_size & get_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_15 = get_a_mask_sub_7_1 | _get_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_lo = {get_a_mask_lo_lo_hi, get_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_lo_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_hi = {get_a_mask_lo_hi_hi, get_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo_lo = {get_a_mask_acc_9, get_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_lo_hi = {get_a_mask_acc_11, get_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_lo = {get_a_mask_hi_lo_hi, get_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_hi_lo = {get_a_mask_acc_13, get_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi_hi = {get_a_mask_acc_15, get_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_hi = {get_a_mask_hi_hi_hi, get_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_75 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_7 = {req_addr[39:21], req_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31] assign _atomics_legal_T_68 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31] assign _atomics_legal_T_127 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31] assign _atomics_legal_T_186 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31] assign _atomics_legal_T_245 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31] assign _atomics_legal_T_304 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_363; // @[Parameters.scala:137:31] assign _atomics_legal_T_363 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_422; // @[Parameters.scala:137:31] assign _atomics_legal_T_422 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_481; // @[Parameters.scala:137:31] assign _atomics_legal_T_481 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_8 = {req_addr[39:26], req_addr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31] assign _atomics_legal_T_73 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31] assign _atomics_legal_T_132 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31] assign _atomics_legal_T_191 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31] assign _atomics_legal_T_250 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_309; // @[Parameters.scala:137:31] assign _atomics_legal_T_309 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_368; // @[Parameters.scala:137:31] assign _atomics_legal_T_368 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_427; // @[Parameters.scala:137:31] assign _atomics_legal_T_427 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_486; // @[Parameters.scala:137:31] assign _atomics_legal_T_486 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46] wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46] wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46] wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_55 = {1'h0, _put_legal_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_56 = _put_legal_T_55 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_57 = _put_legal_T_56; // @[Parameters.scala:137:46] wire _put_legal_T_58 = _put_legal_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_59 = _put_legal_T_18 | _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_60 = _put_legal_T_59 | _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_61 = _put_legal_T_60 | _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_62 = _put_legal_T_61 | _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_63 = _put_legal_T_62 | _put_legal_T_43; // @[Parameters.scala:685:42] wire _put_legal_T_64 = _put_legal_T_63 | _put_legal_T_48; // @[Parameters.scala:685:42] wire _put_legal_T_65 = _put_legal_T_64 | _put_legal_T_53; // @[Parameters.scala:685:42] wire _put_legal_T_66 = _put_legal_T_65 | _put_legal_T_58; // @[Parameters.scala:685:42] wire _put_legal_T_67 = _put_legal_T_66; // @[Parameters.scala:684:54, :685:42] wire [40:0] _put_legal_T_70 = {1'h0, _put_legal_T_69}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_71 = _put_legal_T_70 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_72 = _put_legal_T_71; // @[Parameters.scala:137:46] wire _put_legal_T_73 = _put_legal_T_72 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_76 = _put_legal_T_75 | _put_legal_T_67; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_76; // @[Parameters.scala:686:26] wire [15:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [15:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_size = put_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_sub_1_2 = put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_sub_nbit = ~put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_sub_0_2 = put_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_sub_acc_T = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_0_1 = _put_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _put_a_mask_sub_sub_sub_acc_T_1 = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_1_1 = _put_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_2_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T_2 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_2_1 = put_a_mask_sub_sub_sub_1_1 | _put_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_3_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_3 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_3_1 = put_a_mask_sub_sub_sub_1_1 | _put_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_4_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_4 = put_a_mask_sub_size & put_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_4_1 = put_a_mask_sub_sub_2_1 | _put_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_5_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_5 = put_a_mask_sub_size & put_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_5_1 = put_a_mask_sub_sub_2_1 | _put_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_6_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_6 = put_a_mask_sub_size & put_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_6_1 = put_a_mask_sub_sub_3_1 | _put_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_7_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_7 = put_a_mask_sub_size & put_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_7_1 = put_a_mask_sub_sub_3_1 | _put_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 | _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 | _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_8 = put_a_mask_sub_4_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_8 = put_a_mask_size & put_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_8 = put_a_mask_sub_4_1 | _put_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_9 = put_a_mask_sub_4_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_9 = put_a_mask_size & put_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_9 = put_a_mask_sub_4_1 | _put_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_10 = put_a_mask_sub_5_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_10 = put_a_mask_size & put_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_10 = put_a_mask_sub_5_1 | _put_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_11 = put_a_mask_sub_5_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_11 = put_a_mask_size & put_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_11 = put_a_mask_sub_5_1 | _put_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_12 = put_a_mask_sub_6_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_12 = put_a_mask_size & put_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_12 = put_a_mask_sub_6_1 | _put_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_13 = put_a_mask_sub_6_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_13 = put_a_mask_size & put_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_13 = put_a_mask_sub_6_1 | _put_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_14 = put_a_mask_sub_7_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_14 = put_a_mask_size & put_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_14 = put_a_mask_sub_7_1 | _put_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_15 = put_a_mask_sub_7_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_15 = put_a_mask_size & put_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_15 = put_a_mask_sub_7_1 | _put_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_lo = {put_a_mask_lo_lo_hi, put_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_lo_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_hi = {put_a_mask_lo_hi_hi, put_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo_lo = {put_a_mask_acc_9, put_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_lo_hi = {put_a_mask_acc_11, put_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_lo = {put_a_mask_hi_lo_hi, put_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_hi_lo = {put_a_mask_acc_13, put_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi_hi = {put_a_mask_acc_15, put_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_hi = {put_a_mask_hi_hi_hi, put_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_9 = {req_addr[39:28], req_addr[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31] assign _atomics_legal_T_19 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31] assign _atomics_legal_T_78 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31] assign _atomics_legal_T_137 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31] assign _atomics_legal_T_196 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_255; // @[Parameters.scala:137:31] assign _atomics_legal_T_255 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_314; // @[Parameters.scala:137:31] assign _atomics_legal_T_314 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_373; // @[Parameters.scala:137:31] assign _atomics_legal_T_373 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_432; // @[Parameters.scala:137:31] assign _atomics_legal_T_432 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_491; // @[Parameters.scala:137:31] assign _atomics_legal_T_491 = _GEN_9; // @[Parameters.scala:137:31] wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46] wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46] wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_29 = _atomics_legal_T_8 | _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_30 = _atomics_legal_T_29 | _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_31 = _atomics_legal_T_30 | _atomics_legal_T_23; // @[Parameters.scala:685:42] wire _atomics_legal_T_32 = _atomics_legal_T_31 | _atomics_legal_T_28; // @[Parameters.scala:685:42] wire _atomics_legal_T_33 = _atomics_legal_T_32; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_57 = _atomics_legal_T_33; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_36 = {1'h0, _atomics_legal_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_38 = _atomics_legal_T_37; // @[Parameters.scala:137:46] wire _atomics_legal_T_39 = _atomics_legal_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_46 = {1'h0, _atomics_legal_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_47 = _atomics_legal_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_48 = _atomics_legal_T_47; // @[Parameters.scala:137:46] wire _atomics_legal_T_49 = _atomics_legal_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_51 = {1'h0, _atomics_legal_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_52 = _atomics_legal_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_53 = _atomics_legal_T_52; // @[Parameters.scala:137:46] wire _atomics_legal_T_54 = _atomics_legal_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_55 = _atomics_legal_T_49 | _atomics_legal_T_54; // @[Parameters.scala:685:42] wire _atomics_legal_T_56 = _atomics_legal_T_55; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_58 = _atomics_legal_T_57; // @[Parameters.scala:686:26] wire atomics_legal = _atomics_legal_T_58 | _atomics_legal_T_56; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [15:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size = atomics_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit = ~atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1 = _atomics_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1 = atomics_a_mask_sub_sub_sub_1_1 | _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1 = atomics_a_mask_sub_sub_sub_1_1 | _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size & atomics_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1 = atomics_a_mask_sub_sub_2_1 | _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size & atomics_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1 = atomics_a_mask_sub_sub_2_1 | _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size & atomics_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1 = atomics_a_mask_sub_sub_3_1 | _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size & atomics_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1 = atomics_a_mask_sub_sub_3_1 | _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_4_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_4_1 | _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_4_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_4_1 | _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_5_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_5_1 | _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_5_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_5_1 | _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_6_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_6_1 | _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_6_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_6_1 | _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_7_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_7_1 | _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_7_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_7_1 | _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo = {atomics_a_mask_lo_lo_hi, atomics_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi = {atomics_a_mask_lo_hi_hi, atomics_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo = {atomics_a_mask_hi_lo_hi, atomics_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi = {atomics_a_mask_hi_hi_hi, atomics_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46] wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46] wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46] wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46] wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_88 = _atomics_legal_T_67 | _atomics_legal_T_72; // @[Parameters.scala:685:42] wire _atomics_legal_T_89 = _atomics_legal_T_88 | _atomics_legal_T_77; // @[Parameters.scala:685:42] wire _atomics_legal_T_90 = _atomics_legal_T_89 | _atomics_legal_T_82; // @[Parameters.scala:685:42] wire _atomics_legal_T_91 = _atomics_legal_T_90 | _atomics_legal_T_87; // @[Parameters.scala:685:42] wire _atomics_legal_T_92 = _atomics_legal_T_91; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_116 = _atomics_legal_T_92; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_95 = {1'h0, _atomics_legal_T_94}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_96 = _atomics_legal_T_95 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_97 = _atomics_legal_T_96; // @[Parameters.scala:137:46] wire _atomics_legal_T_98 = _atomics_legal_T_97 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_105 = {1'h0, _atomics_legal_T_104}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_106 = _atomics_legal_T_105 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_107 = _atomics_legal_T_106; // @[Parameters.scala:137:46] wire _atomics_legal_T_108 = _atomics_legal_T_107 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_110 = {1'h0, _atomics_legal_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_111 = _atomics_legal_T_110 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_112 = _atomics_legal_T_111; // @[Parameters.scala:137:46] wire _atomics_legal_T_113 = _atomics_legal_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_114 = _atomics_legal_T_108 | _atomics_legal_T_113; // @[Parameters.scala:685:42] wire _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_117 = _atomics_legal_T_116; // @[Parameters.scala:686:26] wire atomics_legal_1 = _atomics_legal_T_117 | _atomics_legal_T_115; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [15:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_1 = atomics_a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 | _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 | _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_1 = atomics_a_mask_sub_sub_2_1_1 | _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_1 = atomics_a_mask_sub_sub_2_1_1 | _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_1 = atomics_a_mask_sub_sub_3_1_1 | _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_1 = atomics_a_mask_sub_sub_3_1_1 | _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_1 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_1 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_1 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_1 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_1 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_1 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_1 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_1 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_1 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_4_1_1 | _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_1 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_4_1_1 | _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_1 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_5_1_1 | _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_1 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_5_1_1 | _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_1 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_6_1_1 | _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_1 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_6_1_1 | _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_1 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_7_1_1 | _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_1 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_7_1_1 | _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_1 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_1 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_lo_lo_hi_1, atomics_a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_1 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_1 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_lo_hi_hi_1, atomics_a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_1 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_1 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_hi_lo_hi_1, atomics_a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_1 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_1 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_hi_hi_hi_1, atomics_a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46] wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46] wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46] wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46] wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46] wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_147 = _atomics_legal_T_126 | _atomics_legal_T_131; // @[Parameters.scala:685:42] wire _atomics_legal_T_148 = _atomics_legal_T_147 | _atomics_legal_T_136; // @[Parameters.scala:685:42] wire _atomics_legal_T_149 = _atomics_legal_T_148 | _atomics_legal_T_141; // @[Parameters.scala:685:42] wire _atomics_legal_T_150 = _atomics_legal_T_149 | _atomics_legal_T_146; // @[Parameters.scala:685:42] wire _atomics_legal_T_151 = _atomics_legal_T_150; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_175 = _atomics_legal_T_151; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_154 = {1'h0, _atomics_legal_T_153}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_155 = _atomics_legal_T_154 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_156 = _atomics_legal_T_155; // @[Parameters.scala:137:46] wire _atomics_legal_T_157 = _atomics_legal_T_156 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_164 = {1'h0, _atomics_legal_T_163}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_165 = _atomics_legal_T_164 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_166 = _atomics_legal_T_165; // @[Parameters.scala:137:46] wire _atomics_legal_T_167 = _atomics_legal_T_166 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_169 = {1'h0, _atomics_legal_T_168}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_170 = _atomics_legal_T_169 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_171 = _atomics_legal_T_170; // @[Parameters.scala:137:46] wire _atomics_legal_T_172 = _atomics_legal_T_171 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_173 = _atomics_legal_T_167 | _atomics_legal_T_172; // @[Parameters.scala:685:42] wire _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_176 = _atomics_legal_T_175; // @[Parameters.scala:686:26] wire atomics_legal_2 = _atomics_legal_T_176 | _atomics_legal_T_174; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [15:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_2 = atomics_a_mask_sizeOH_2[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 | _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 | _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_4_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_2 = atomics_a_mask_sub_sub_2_1_2 | _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_5_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_2 = atomics_a_mask_sub_sub_2_1_2 | _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_6_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_2 = atomics_a_mask_sub_sub_3_1_2 | _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_7_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_2 = atomics_a_mask_sub_sub_3_1_2 | _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_2 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_2 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_2 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_2 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_2 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_2 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_2 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_2 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_2 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_4_1_2 | _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_2 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_4_1_2 | _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_2 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_5_1_2 | _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_2 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_5_1_2 | _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_2 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_6_1_2 | _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_2 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_6_1_2 | _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_2 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_7_1_2 | _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_2 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_7_1_2 | _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_2 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_2 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_lo_lo_hi_2, atomics_a_mask_lo_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_2 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_2 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_lo_hi_hi_2, atomics_a_mask_lo_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_2 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_2 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_hi_lo_hi_2, atomics_a_mask_hi_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_2 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_2 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_hi_hi_hi_2, atomics_a_mask_hi_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46] wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46] wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46] wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46] wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_202 = {1'h0, _atomics_legal_T_201}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_203 = _atomics_legal_T_202 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_204 = _atomics_legal_T_203; // @[Parameters.scala:137:46] wire _atomics_legal_T_205 = _atomics_legal_T_204 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_206 = _atomics_legal_T_185 | _atomics_legal_T_190; // @[Parameters.scala:685:42] wire _atomics_legal_T_207 = _atomics_legal_T_206 | _atomics_legal_T_195; // @[Parameters.scala:685:42] wire _atomics_legal_T_208 = _atomics_legal_T_207 | _atomics_legal_T_200; // @[Parameters.scala:685:42] wire _atomics_legal_T_209 = _atomics_legal_T_208 | _atomics_legal_T_205; // @[Parameters.scala:685:42] wire _atomics_legal_T_210 = _atomics_legal_T_209; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_234 = _atomics_legal_T_210; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_213 = {1'h0, _atomics_legal_T_212}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_214 = _atomics_legal_T_213 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_215 = _atomics_legal_T_214; // @[Parameters.scala:137:46] wire _atomics_legal_T_216 = _atomics_legal_T_215 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_223 = {1'h0, _atomics_legal_T_222}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_224 = _atomics_legal_T_223 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_225 = _atomics_legal_T_224; // @[Parameters.scala:137:46] wire _atomics_legal_T_226 = _atomics_legal_T_225 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_228 = {1'h0, _atomics_legal_T_227}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_229 = _atomics_legal_T_228 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_230 = _atomics_legal_T_229; // @[Parameters.scala:137:46] wire _atomics_legal_T_231 = _atomics_legal_T_230 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_232 = _atomics_legal_T_226 | _atomics_legal_T_231; // @[Parameters.scala:685:42] wire _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_235 = _atomics_legal_T_234; // @[Parameters.scala:686:26] wire atomics_legal_3 = _atomics_legal_T_235 | _atomics_legal_T_233; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [15:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_3 = atomics_a_mask_sizeOH_3[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 | _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 | _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_4_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_3 = atomics_a_mask_sub_sub_2_1_3 | _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_5_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_3 = atomics_a_mask_sub_sub_2_1_3 | _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_6_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_3 = atomics_a_mask_sub_sub_3_1_3 | _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_7_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_3 = atomics_a_mask_sub_sub_3_1_3 | _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_3 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_3 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_3 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_3 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_3 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_3 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_3 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_3 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_3 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_4_1_3 | _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_3 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_4_1_3 | _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_3 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_5_1_3 | _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_3 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_5_1_3 | _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_3 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_6_1_3 | _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_3 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_6_1_3 | _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_3 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_7_1_3 | _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_3 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_7_1_3 | _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_3 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_3 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_lo_lo_hi_3, atomics_a_mask_lo_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_3 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_3 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_lo_hi_hi_3, atomics_a_mask_lo_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_3 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_3 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_hi_lo_hi_3, atomics_a_mask_hi_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_3 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_3 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_hi_hi_hi_3, atomics_a_mask_hi_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46] wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46] wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46] wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_256 = {1'h0, _atomics_legal_T_255}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_257 = _atomics_legal_T_256 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_258 = _atomics_legal_T_257; // @[Parameters.scala:137:46] wire _atomics_legal_T_259 = _atomics_legal_T_258 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_261 = {1'h0, _atomics_legal_T_260}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_262 = _atomics_legal_T_261 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_263 = _atomics_legal_T_262; // @[Parameters.scala:137:46] wire _atomics_legal_T_264 = _atomics_legal_T_263 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_265 = _atomics_legal_T_244 | _atomics_legal_T_249; // @[Parameters.scala:685:42] wire _atomics_legal_T_266 = _atomics_legal_T_265 | _atomics_legal_T_254; // @[Parameters.scala:685:42] wire _atomics_legal_T_267 = _atomics_legal_T_266 | _atomics_legal_T_259; // @[Parameters.scala:685:42] wire _atomics_legal_T_268 = _atomics_legal_T_267 | _atomics_legal_T_264; // @[Parameters.scala:685:42] wire _atomics_legal_T_269 = _atomics_legal_T_268; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_293 = _atomics_legal_T_269; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_272 = {1'h0, _atomics_legal_T_271}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_273 = _atomics_legal_T_272 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_274 = _atomics_legal_T_273; // @[Parameters.scala:137:46] wire _atomics_legal_T_275 = _atomics_legal_T_274 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_282 = {1'h0, _atomics_legal_T_281}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_283 = _atomics_legal_T_282 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_284 = _atomics_legal_T_283; // @[Parameters.scala:137:46] wire _atomics_legal_T_285 = _atomics_legal_T_284 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_287 = {1'h0, _atomics_legal_T_286}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_288 = _atomics_legal_T_287 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_289 = _atomics_legal_T_288; // @[Parameters.scala:137:46] wire _atomics_legal_T_290 = _atomics_legal_T_289 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_291 = _atomics_legal_T_285 | _atomics_legal_T_290; // @[Parameters.scala:685:42] wire _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_294 = _atomics_legal_T_293; // @[Parameters.scala:686:26] wire atomics_legal_4 = _atomics_legal_T_294 | _atomics_legal_T_292; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [15:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_4 = atomics_a_mask_sizeOH_4[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_18 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 | _atomics_a_mask_sub_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_19 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 | _atomics_a_mask_sub_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_36 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_4_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_4 = atomics_a_mask_sub_sub_2_1_4 | _atomics_a_mask_sub_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_37 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_5_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_4 = atomics_a_mask_sub_sub_2_1_4 | _atomics_a_mask_sub_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_38 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_6_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_4 = atomics_a_mask_sub_sub_3_1_4 | _atomics_a_mask_sub_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_39 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_7_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_4 = atomics_a_mask_sub_sub_3_1_4 | _atomics_a_mask_sub_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_4 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_4 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_4 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_4 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_4 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_4 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_4 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_4 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_72 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_72 = atomics_a_mask_size_4 & atomics_a_mask_eq_72; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_72 = atomics_a_mask_sub_4_1_4 | _atomics_a_mask_acc_T_72; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_73 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_73 = atomics_a_mask_size_4 & atomics_a_mask_eq_73; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_73 = atomics_a_mask_sub_4_1_4 | _atomics_a_mask_acc_T_73; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_74 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_74 = atomics_a_mask_size_4 & atomics_a_mask_eq_74; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_74 = atomics_a_mask_sub_5_1_4 | _atomics_a_mask_acc_T_74; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_75 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_75 = atomics_a_mask_size_4 & atomics_a_mask_eq_75; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_75 = atomics_a_mask_sub_5_1_4 | _atomics_a_mask_acc_T_75; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_76 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_76 = atomics_a_mask_size_4 & atomics_a_mask_eq_76; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_76 = atomics_a_mask_sub_6_1_4 | _atomics_a_mask_acc_T_76; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_77 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_77 = atomics_a_mask_size_4 & atomics_a_mask_eq_77; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_77 = atomics_a_mask_sub_6_1_4 | _atomics_a_mask_acc_T_77; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_78 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_78 = atomics_a_mask_size_4 & atomics_a_mask_eq_78; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_78 = atomics_a_mask_sub_7_1_4 | _atomics_a_mask_acc_T_78; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_79 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_79 = atomics_a_mask_size_4 & atomics_a_mask_eq_79; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_79 = atomics_a_mask_sub_7_1_4 | _atomics_a_mask_acc_T_79; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_4 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_4 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_lo_lo_hi_4, atomics_a_mask_lo_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_4 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_4 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_lo_hi_hi_4, atomics_a_mask_lo_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_4 = {atomics_a_mask_acc_73, atomics_a_mask_acc_72}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_4 = {atomics_a_mask_acc_75, atomics_a_mask_acc_74}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_hi_lo_hi_4, atomics_a_mask_hi_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_4 = {atomics_a_mask_acc_77, atomics_a_mask_acc_76}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_4 = {atomics_a_mask_acc_79, atomics_a_mask_acc_78}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_hi_hi_hi_4, atomics_a_mask_hi_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46] wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46] wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_310 = {1'h0, _atomics_legal_T_309}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_311 = _atomics_legal_T_310 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_312 = _atomics_legal_T_311; // @[Parameters.scala:137:46] wire _atomics_legal_T_313 = _atomics_legal_T_312 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_315 = {1'h0, _atomics_legal_T_314}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_316 = _atomics_legal_T_315 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_317 = _atomics_legal_T_316; // @[Parameters.scala:137:46] wire _atomics_legal_T_318 = _atomics_legal_T_317 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_320 = {1'h0, _atomics_legal_T_319}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_321 = _atomics_legal_T_320 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_322 = _atomics_legal_T_321; // @[Parameters.scala:137:46] wire _atomics_legal_T_323 = _atomics_legal_T_322 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_324 = _atomics_legal_T_303 | _atomics_legal_T_308; // @[Parameters.scala:685:42] wire _atomics_legal_T_325 = _atomics_legal_T_324 | _atomics_legal_T_313; // @[Parameters.scala:685:42] wire _atomics_legal_T_326 = _atomics_legal_T_325 | _atomics_legal_T_318; // @[Parameters.scala:685:42] wire _atomics_legal_T_327 = _atomics_legal_T_326 | _atomics_legal_T_323; // @[Parameters.scala:685:42] wire _atomics_legal_T_328 = _atomics_legal_T_327; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_352 = _atomics_legal_T_328; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_331 = {1'h0, _atomics_legal_T_330}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_332 = _atomics_legal_T_331 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_333 = _atomics_legal_T_332; // @[Parameters.scala:137:46] wire _atomics_legal_T_334 = _atomics_legal_T_333 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_341 = {1'h0, _atomics_legal_T_340}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_342 = _atomics_legal_T_341 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_343 = _atomics_legal_T_342; // @[Parameters.scala:137:46] wire _atomics_legal_T_344 = _atomics_legal_T_343 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_346 = {1'h0, _atomics_legal_T_345}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_347 = _atomics_legal_T_346 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_348 = _atomics_legal_T_347; // @[Parameters.scala:137:46] wire _atomics_legal_T_349 = _atomics_legal_T_348 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_350 = _atomics_legal_T_344 | _atomics_legal_T_349; // @[Parameters.scala:685:42] wire _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_353 = _atomics_legal_T_352; // @[Parameters.scala:686:26] wire atomics_legal_5 = _atomics_legal_T_353 | _atomics_legal_T_351; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [15:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_5 = atomics_a_mask_sizeOH_5[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_20 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_21 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_22 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 | _atomics_a_mask_sub_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_23 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 | _atomics_a_mask_sub_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_40 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_41 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_42 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_43 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_44 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_4_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_5 = atomics_a_mask_sub_sub_2_1_5 | _atomics_a_mask_sub_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_45 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_5_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_5 = atomics_a_mask_sub_sub_2_1_5 | _atomics_a_mask_sub_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_46 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_6_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_5 = atomics_a_mask_sub_sub_3_1_5 | _atomics_a_mask_sub_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_47 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_7_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_5 = atomics_a_mask_sub_sub_3_1_5 | _atomics_a_mask_sub_acc_T_47; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_80 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_80 = atomics_a_mask_size_5 & atomics_a_mask_eq_80; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_80 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_80; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_81 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_81 = atomics_a_mask_size_5 & atomics_a_mask_eq_81; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_81 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_81; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_82 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_82 = atomics_a_mask_size_5 & atomics_a_mask_eq_82; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_82 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_82; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_83 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_83 = atomics_a_mask_size_5 & atomics_a_mask_eq_83; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_83 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_83; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_84 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_84 = atomics_a_mask_size_5 & atomics_a_mask_eq_84; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_84 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_84; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_85 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_85 = atomics_a_mask_size_5 & atomics_a_mask_eq_85; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_85 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_85; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_86 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_86 = atomics_a_mask_size_5 & atomics_a_mask_eq_86; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_86 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_86; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_87 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_87 = atomics_a_mask_size_5 & atomics_a_mask_eq_87; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_87 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_87; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_88 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_88 = atomics_a_mask_size_5 & atomics_a_mask_eq_88; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_88 = atomics_a_mask_sub_4_1_5 | _atomics_a_mask_acc_T_88; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_89 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_89 = atomics_a_mask_size_5 & atomics_a_mask_eq_89; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_89 = atomics_a_mask_sub_4_1_5 | _atomics_a_mask_acc_T_89; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_90 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_90 = atomics_a_mask_size_5 & atomics_a_mask_eq_90; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_90 = atomics_a_mask_sub_5_1_5 | _atomics_a_mask_acc_T_90; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_91 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_91 = atomics_a_mask_size_5 & atomics_a_mask_eq_91; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_91 = atomics_a_mask_sub_5_1_5 | _atomics_a_mask_acc_T_91; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_92 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_92 = atomics_a_mask_size_5 & atomics_a_mask_eq_92; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_92 = atomics_a_mask_sub_6_1_5 | _atomics_a_mask_acc_T_92; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_93 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_93 = atomics_a_mask_size_5 & atomics_a_mask_eq_93; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_93 = atomics_a_mask_sub_6_1_5 | _atomics_a_mask_acc_T_93; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_94 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_94 = atomics_a_mask_size_5 & atomics_a_mask_eq_94; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_94 = atomics_a_mask_sub_7_1_5 | _atomics_a_mask_acc_T_94; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_95 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_95 = atomics_a_mask_size_5 & atomics_a_mask_eq_95; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_95 = atomics_a_mask_sub_7_1_5 | _atomics_a_mask_acc_T_95; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_5 = {atomics_a_mask_acc_81, atomics_a_mask_acc_80}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_5 = {atomics_a_mask_acc_83, atomics_a_mask_acc_82}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_lo_lo_hi_5, atomics_a_mask_lo_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_5 = {atomics_a_mask_acc_85, atomics_a_mask_acc_84}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_5 = {atomics_a_mask_acc_87, atomics_a_mask_acc_86}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_lo_hi_hi_5, atomics_a_mask_lo_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_5 = {atomics_a_mask_acc_89, atomics_a_mask_acc_88}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_5 = {atomics_a_mask_acc_91, atomics_a_mask_acc_90}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_hi_lo_hi_5, atomics_a_mask_hi_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_5 = {atomics_a_mask_acc_93, atomics_a_mask_acc_92}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_5 = {atomics_a_mask_acc_95, atomics_a_mask_acc_94}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_hi_hi_hi_5, atomics_a_mask_hi_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46] wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_364 = {1'h0, _atomics_legal_T_363}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_365 = _atomics_legal_T_364 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_366 = _atomics_legal_T_365; // @[Parameters.scala:137:46] wire _atomics_legal_T_367 = _atomics_legal_T_366 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_369 = {1'h0, _atomics_legal_T_368}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_370 = _atomics_legal_T_369 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_371 = _atomics_legal_T_370; // @[Parameters.scala:137:46] wire _atomics_legal_T_372 = _atomics_legal_T_371 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_374 = {1'h0, _atomics_legal_T_373}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_375 = _atomics_legal_T_374 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_376 = _atomics_legal_T_375; // @[Parameters.scala:137:46] wire _atomics_legal_T_377 = _atomics_legal_T_376 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_379 = {1'h0, _atomics_legal_T_378}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_380 = _atomics_legal_T_379 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_381 = _atomics_legal_T_380; // @[Parameters.scala:137:46] wire _atomics_legal_T_382 = _atomics_legal_T_381 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_383 = _atomics_legal_T_362 | _atomics_legal_T_367; // @[Parameters.scala:685:42] wire _atomics_legal_T_384 = _atomics_legal_T_383 | _atomics_legal_T_372; // @[Parameters.scala:685:42] wire _atomics_legal_T_385 = _atomics_legal_T_384 | _atomics_legal_T_377; // @[Parameters.scala:685:42] wire _atomics_legal_T_386 = _atomics_legal_T_385 | _atomics_legal_T_382; // @[Parameters.scala:685:42] wire _atomics_legal_T_387 = _atomics_legal_T_386; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_411 = _atomics_legal_T_387; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_390 = {1'h0, _atomics_legal_T_389}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_391 = _atomics_legal_T_390 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_392 = _atomics_legal_T_391; // @[Parameters.scala:137:46] wire _atomics_legal_T_393 = _atomics_legal_T_392 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_400 = {1'h0, _atomics_legal_T_399}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_401 = _atomics_legal_T_400 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_402 = _atomics_legal_T_401; // @[Parameters.scala:137:46] wire _atomics_legal_T_403 = _atomics_legal_T_402 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_405 = {1'h0, _atomics_legal_T_404}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_406 = _atomics_legal_T_405 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_407 = _atomics_legal_T_406; // @[Parameters.scala:137:46] wire _atomics_legal_T_408 = _atomics_legal_T_407 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_409 = _atomics_legal_T_403 | _atomics_legal_T_408; // @[Parameters.scala:685:42] wire _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_412 = _atomics_legal_T_411; // @[Parameters.scala:686:26] wire atomics_legal_6 = _atomics_legal_T_412 | _atomics_legal_T_410; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [15:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_6 = atomics_a_mask_sizeOH_6[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_24 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_25 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_26 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 | _atomics_a_mask_sub_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_27 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 | _atomics_a_mask_sub_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_48 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_49 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_50 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_51 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_52 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_4_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_6 = atomics_a_mask_sub_sub_2_1_6 | _atomics_a_mask_sub_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_53 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_5_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_6 = atomics_a_mask_sub_sub_2_1_6 | _atomics_a_mask_sub_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_54 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_6_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_6 = atomics_a_mask_sub_sub_3_1_6 | _atomics_a_mask_sub_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_55 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_7_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_6 = atomics_a_mask_sub_sub_3_1_6 | _atomics_a_mask_sub_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_96 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_96 = atomics_a_mask_size_6 & atomics_a_mask_eq_96; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_96 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_96; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_97 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_97 = atomics_a_mask_size_6 & atomics_a_mask_eq_97; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_97 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_97; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_98 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_98 = atomics_a_mask_size_6 & atomics_a_mask_eq_98; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_98 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_98; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_99 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_99 = atomics_a_mask_size_6 & atomics_a_mask_eq_99; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_99 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_99; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_100 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_100 = atomics_a_mask_size_6 & atomics_a_mask_eq_100; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_100 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_100; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_101 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_101 = atomics_a_mask_size_6 & atomics_a_mask_eq_101; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_101 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_101; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_102 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_102 = atomics_a_mask_size_6 & atomics_a_mask_eq_102; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_102 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_102; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_103 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_103 = atomics_a_mask_size_6 & atomics_a_mask_eq_103; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_103 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_103; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_104 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_104 = atomics_a_mask_size_6 & atomics_a_mask_eq_104; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_104 = atomics_a_mask_sub_4_1_6 | _atomics_a_mask_acc_T_104; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_105 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_105 = atomics_a_mask_size_6 & atomics_a_mask_eq_105; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_105 = atomics_a_mask_sub_4_1_6 | _atomics_a_mask_acc_T_105; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_106 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_106 = atomics_a_mask_size_6 & atomics_a_mask_eq_106; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_106 = atomics_a_mask_sub_5_1_6 | _atomics_a_mask_acc_T_106; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_107 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_107 = atomics_a_mask_size_6 & atomics_a_mask_eq_107; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_107 = atomics_a_mask_sub_5_1_6 | _atomics_a_mask_acc_T_107; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_108 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_108 = atomics_a_mask_size_6 & atomics_a_mask_eq_108; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_108 = atomics_a_mask_sub_6_1_6 | _atomics_a_mask_acc_T_108; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_109 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_109 = atomics_a_mask_size_6 & atomics_a_mask_eq_109; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_109 = atomics_a_mask_sub_6_1_6 | _atomics_a_mask_acc_T_109; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_110 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_110 = atomics_a_mask_size_6 & atomics_a_mask_eq_110; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_110 = atomics_a_mask_sub_7_1_6 | _atomics_a_mask_acc_T_110; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_111 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_111 = atomics_a_mask_size_6 & atomics_a_mask_eq_111; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_111 = atomics_a_mask_sub_7_1_6 | _atomics_a_mask_acc_T_111; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_6 = {atomics_a_mask_acc_97, atomics_a_mask_acc_96}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_6 = {atomics_a_mask_acc_99, atomics_a_mask_acc_98}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_lo_lo_hi_6, atomics_a_mask_lo_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_6 = {atomics_a_mask_acc_101, atomics_a_mask_acc_100}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_6 = {atomics_a_mask_acc_103, atomics_a_mask_acc_102}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_lo_hi_hi_6, atomics_a_mask_lo_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_6 = {atomics_a_mask_acc_105, atomics_a_mask_acc_104}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_6 = {atomics_a_mask_acc_107, atomics_a_mask_acc_106}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_hi_lo_hi_6, atomics_a_mask_hi_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_6 = {atomics_a_mask_acc_109, atomics_a_mask_acc_108}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_6 = {atomics_a_mask_acc_111, atomics_a_mask_acc_110}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_hi_hi_hi_6, atomics_a_mask_hi_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_418 = {1'h0, _atomics_legal_T_417}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_419 = _atomics_legal_T_418 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_420 = _atomics_legal_T_419; // @[Parameters.scala:137:46] wire _atomics_legal_T_421 = _atomics_legal_T_420 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_423 = {1'h0, _atomics_legal_T_422}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_424 = _atomics_legal_T_423 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_425 = _atomics_legal_T_424; // @[Parameters.scala:137:46] wire _atomics_legal_T_426 = _atomics_legal_T_425 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_428 = {1'h0, _atomics_legal_T_427}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_429 = _atomics_legal_T_428 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_430 = _atomics_legal_T_429; // @[Parameters.scala:137:46] wire _atomics_legal_T_431 = _atomics_legal_T_430 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_433 = {1'h0, _atomics_legal_T_432}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_434 = _atomics_legal_T_433 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_435 = _atomics_legal_T_434; // @[Parameters.scala:137:46] wire _atomics_legal_T_436 = _atomics_legal_T_435 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_438 = {1'h0, _atomics_legal_T_437}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_440 = _atomics_legal_T_439; // @[Parameters.scala:137:46] wire _atomics_legal_T_441 = _atomics_legal_T_440 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_442 = _atomics_legal_T_421 | _atomics_legal_T_426; // @[Parameters.scala:685:42] wire _atomics_legal_T_443 = _atomics_legal_T_442 | _atomics_legal_T_431; // @[Parameters.scala:685:42] wire _atomics_legal_T_444 = _atomics_legal_T_443 | _atomics_legal_T_436; // @[Parameters.scala:685:42] wire _atomics_legal_T_445 = _atomics_legal_T_444 | _atomics_legal_T_441; // @[Parameters.scala:685:42] wire _atomics_legal_T_446 = _atomics_legal_T_445; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_470 = _atomics_legal_T_446; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_449 = {1'h0, _atomics_legal_T_448}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_450 = _atomics_legal_T_449 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_451 = _atomics_legal_T_450; // @[Parameters.scala:137:46] wire _atomics_legal_T_452 = _atomics_legal_T_451 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_459 = {1'h0, _atomics_legal_T_458}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_460 = _atomics_legal_T_459 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_461 = _atomics_legal_T_460; // @[Parameters.scala:137:46] wire _atomics_legal_T_462 = _atomics_legal_T_461 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_464 = {1'h0, _atomics_legal_T_463}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_465 = _atomics_legal_T_464 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_466 = _atomics_legal_T_465; // @[Parameters.scala:137:46] wire _atomics_legal_T_467 = _atomics_legal_T_466 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_468 = _atomics_legal_T_462 | _atomics_legal_T_467; // @[Parameters.scala:685:42] wire _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_471 = _atomics_legal_T_470; // @[Parameters.scala:686:26] wire atomics_legal_7 = _atomics_legal_T_471 | _atomics_legal_T_469; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [15:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_7 = atomics_a_mask_sizeOH_7[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_28 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_29 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_30 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 | _atomics_a_mask_sub_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_31 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 | _atomics_a_mask_sub_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_56 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_57 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_58 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_59 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_60 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_4_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_7 = atomics_a_mask_sub_sub_2_1_7 | _atomics_a_mask_sub_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_61 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_5_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_7 = atomics_a_mask_sub_sub_2_1_7 | _atomics_a_mask_sub_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_62 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_6_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_7 = atomics_a_mask_sub_sub_3_1_7 | _atomics_a_mask_sub_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_63 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_7_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_7 = atomics_a_mask_sub_sub_3_1_7 | _atomics_a_mask_sub_acc_T_63; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_112 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_112 = atomics_a_mask_size_7 & atomics_a_mask_eq_112; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_112 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_112; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_113 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_113 = atomics_a_mask_size_7 & atomics_a_mask_eq_113; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_113 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_113; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_114 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_114 = atomics_a_mask_size_7 & atomics_a_mask_eq_114; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_114 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_114; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_115 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_115 = atomics_a_mask_size_7 & atomics_a_mask_eq_115; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_115 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_115; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_116 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_116 = atomics_a_mask_size_7 & atomics_a_mask_eq_116; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_116 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_116; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_117 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_117 = atomics_a_mask_size_7 & atomics_a_mask_eq_117; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_117 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_117; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_118 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_118 = atomics_a_mask_size_7 & atomics_a_mask_eq_118; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_118 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_118; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_119 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_119 = atomics_a_mask_size_7 & atomics_a_mask_eq_119; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_119 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_119; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_120 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_120 = atomics_a_mask_size_7 & atomics_a_mask_eq_120; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_120 = atomics_a_mask_sub_4_1_7 | _atomics_a_mask_acc_T_120; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_121 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_121 = atomics_a_mask_size_7 & atomics_a_mask_eq_121; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_121 = atomics_a_mask_sub_4_1_7 | _atomics_a_mask_acc_T_121; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_122 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_122 = atomics_a_mask_size_7 & atomics_a_mask_eq_122; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_122 = atomics_a_mask_sub_5_1_7 | _atomics_a_mask_acc_T_122; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_123 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_123 = atomics_a_mask_size_7 & atomics_a_mask_eq_123; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_123 = atomics_a_mask_sub_5_1_7 | _atomics_a_mask_acc_T_123; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_124 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_124 = atomics_a_mask_size_7 & atomics_a_mask_eq_124; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_124 = atomics_a_mask_sub_6_1_7 | _atomics_a_mask_acc_T_124; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_125 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_125 = atomics_a_mask_size_7 & atomics_a_mask_eq_125; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_125 = atomics_a_mask_sub_6_1_7 | _atomics_a_mask_acc_T_125; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_126 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_126 = atomics_a_mask_size_7 & atomics_a_mask_eq_126; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_126 = atomics_a_mask_sub_7_1_7 | _atomics_a_mask_acc_T_126; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_127 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_127 = atomics_a_mask_size_7 & atomics_a_mask_eq_127; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_127 = atomics_a_mask_sub_7_1_7 | _atomics_a_mask_acc_T_127; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_7 = {atomics_a_mask_acc_113, atomics_a_mask_acc_112}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_7 = {atomics_a_mask_acc_115, atomics_a_mask_acc_114}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_lo_lo_hi_7, atomics_a_mask_lo_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_7 = {atomics_a_mask_acc_117, atomics_a_mask_acc_116}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_7 = {atomics_a_mask_acc_119, atomics_a_mask_acc_118}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_lo_hi_hi_7, atomics_a_mask_lo_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_7 = {atomics_a_mask_acc_121, atomics_a_mask_acc_120}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_7 = {atomics_a_mask_acc_123, atomics_a_mask_acc_122}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_hi_lo_hi_7, atomics_a_mask_hi_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_7 = {atomics_a_mask_acc_125, atomics_a_mask_acc_124}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_7 = {atomics_a_mask_acc_127, atomics_a_mask_acc_126}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_hi_hi_hi_7, atomics_a_mask_hi_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_477 = {1'h0, _atomics_legal_T_476}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_478 = _atomics_legal_T_477 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_479 = _atomics_legal_T_478; // @[Parameters.scala:137:46] wire _atomics_legal_T_480 = _atomics_legal_T_479 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_482 = {1'h0, _atomics_legal_T_481}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_483 = _atomics_legal_T_482 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_484 = _atomics_legal_T_483; // @[Parameters.scala:137:46] wire _atomics_legal_T_485 = _atomics_legal_T_484 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_487 = {1'h0, _atomics_legal_T_486}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_488 = _atomics_legal_T_487 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_489 = _atomics_legal_T_488; // @[Parameters.scala:137:46] wire _atomics_legal_T_490 = _atomics_legal_T_489 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_492 = {1'h0, _atomics_legal_T_491}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_493 = _atomics_legal_T_492 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_494 = _atomics_legal_T_493; // @[Parameters.scala:137:46] wire _atomics_legal_T_495 = _atomics_legal_T_494 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_497 = {1'h0, _atomics_legal_T_496}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_498 = _atomics_legal_T_497 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_499 = _atomics_legal_T_498; // @[Parameters.scala:137:46] wire _atomics_legal_T_500 = _atomics_legal_T_499 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_501 = _atomics_legal_T_480 | _atomics_legal_T_485; // @[Parameters.scala:685:42] wire _atomics_legal_T_502 = _atomics_legal_T_501 | _atomics_legal_T_490; // @[Parameters.scala:685:42] wire _atomics_legal_T_503 = _atomics_legal_T_502 | _atomics_legal_T_495; // @[Parameters.scala:685:42] wire _atomics_legal_T_504 = _atomics_legal_T_503 | _atomics_legal_T_500; // @[Parameters.scala:685:42] wire _atomics_legal_T_505 = _atomics_legal_T_504; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_529 = _atomics_legal_T_505; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_508 = {1'h0, _atomics_legal_T_507}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_509 = _atomics_legal_T_508 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_510 = _atomics_legal_T_509; // @[Parameters.scala:137:46] wire _atomics_legal_T_511 = _atomics_legal_T_510 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_518 = {1'h0, _atomics_legal_T_517}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_519 = _atomics_legal_T_518 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_520 = _atomics_legal_T_519; // @[Parameters.scala:137:46] wire _atomics_legal_T_521 = _atomics_legal_T_520 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_523 = {1'h0, _atomics_legal_T_522}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_524 = _atomics_legal_T_523 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_525 = _atomics_legal_T_524; // @[Parameters.scala:137:46] wire _atomics_legal_T_526 = _atomics_legal_T_525 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_527 = _atomics_legal_T_521 | _atomics_legal_T_526; // @[Parameters.scala:685:42] wire _atomics_legal_T_528 = _atomics_legal_T_527; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_530 = _atomics_legal_T_529; // @[Parameters.scala:686:26] wire atomics_legal_8 = _atomics_legal_T_530 | _atomics_legal_T_528; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [15:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_8 = atomics_a_mask_sizeOH_8[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_32 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_33 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_34 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 | _atomics_a_mask_sub_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_35 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 | _atomics_a_mask_sub_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_64 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_65 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_66 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_67 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_68 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_4_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_8 = atomics_a_mask_sub_sub_2_1_8 | _atomics_a_mask_sub_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_69 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_5_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_8 = atomics_a_mask_sub_sub_2_1_8 | _atomics_a_mask_sub_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_70 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_6_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_8 = atomics_a_mask_sub_sub_3_1_8 | _atomics_a_mask_sub_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_71 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_7_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_8 = atomics_a_mask_sub_sub_3_1_8 | _atomics_a_mask_sub_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_128 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_128 = atomics_a_mask_size_8 & atomics_a_mask_eq_128; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_128 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_128; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_129 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_129 = atomics_a_mask_size_8 & atomics_a_mask_eq_129; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_129 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_129; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_130 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_130 = atomics_a_mask_size_8 & atomics_a_mask_eq_130; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_130 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_130; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_131 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_131 = atomics_a_mask_size_8 & atomics_a_mask_eq_131; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_131 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_131; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_132 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_132 = atomics_a_mask_size_8 & atomics_a_mask_eq_132; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_132 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_132; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_133 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_133 = atomics_a_mask_size_8 & atomics_a_mask_eq_133; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_133 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_133; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_134 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_134 = atomics_a_mask_size_8 & atomics_a_mask_eq_134; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_134 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_134; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_135 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_135 = atomics_a_mask_size_8 & atomics_a_mask_eq_135; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_135 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_135; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_136 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_136 = atomics_a_mask_size_8 & atomics_a_mask_eq_136; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_136 = atomics_a_mask_sub_4_1_8 | _atomics_a_mask_acc_T_136; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_137 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_137 = atomics_a_mask_size_8 & atomics_a_mask_eq_137; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_137 = atomics_a_mask_sub_4_1_8 | _atomics_a_mask_acc_T_137; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_138 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_138 = atomics_a_mask_size_8 & atomics_a_mask_eq_138; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_138 = atomics_a_mask_sub_5_1_8 | _atomics_a_mask_acc_T_138; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_139 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_139 = atomics_a_mask_size_8 & atomics_a_mask_eq_139; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_139 = atomics_a_mask_sub_5_1_8 | _atomics_a_mask_acc_T_139; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_140 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_140 = atomics_a_mask_size_8 & atomics_a_mask_eq_140; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_140 = atomics_a_mask_sub_6_1_8 | _atomics_a_mask_acc_T_140; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_141 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_141 = atomics_a_mask_size_8 & atomics_a_mask_eq_141; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_141 = atomics_a_mask_sub_6_1_8 | _atomics_a_mask_acc_T_141; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_142 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_142 = atomics_a_mask_size_8 & atomics_a_mask_eq_142; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_142 = atomics_a_mask_sub_7_1_8 | _atomics_a_mask_acc_T_142; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_143 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_143 = atomics_a_mask_size_8 & atomics_a_mask_eq_143; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_143 = atomics_a_mask_sub_7_1_8 | _atomics_a_mask_acc_T_143; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_8 = {atomics_a_mask_acc_129, atomics_a_mask_acc_128}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_8 = {atomics_a_mask_acc_131, atomics_a_mask_acc_130}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_lo_lo_hi_8, atomics_a_mask_lo_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_8 = {atomics_a_mask_acc_133, atomics_a_mask_acc_132}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_8 = {atomics_a_mask_acc_135, atomics_a_mask_acc_134}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_lo_hi_hi_8, atomics_a_mask_lo_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_8 = {atomics_a_mask_acc_137, atomics_a_mask_acc_136}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_8 = {atomics_a_mask_acc_139, atomics_a_mask_acc_138}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_hi_lo_hi_8, atomics_a_mask_hi_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_8 = {atomics_a_mask_acc_141, atomics_a_mask_acc_140}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_8 = {atomics_a_mask_acc_143, atomics_a_mask_acc_142}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_hi_hi_hi_8, atomics_a_mask_hi_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire _T_17 = req_uop_mem_cmd == 5'h4; // @[mshrs.scala:421:16, :439:75] wire _atomics_T; // @[mshrs.scala:439:75] assign _atomics_T = _T_17; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T; // @[package.scala:16:47] assign _io_mem_access_bits_T = _T_17; // @[package.scala:16:47] wire _io_mem_access_bits_T_24; // @[package.scala:16:47] assign _io_mem_access_bits_T_24 = _T_17; // @[package.scala:16:47] wire _send_resp_T_7; // @[package.scala:16:47] assign _send_resp_T_7 = _T_17; // @[package.scala:16:47] wire [2:0] _GEN_10 = _atomics_T ? 3'h3 : 3'h0; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_opcode; // @[mshrs.scala:439:75] assign _atomics_T_1_opcode = _GEN_10; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_param; // @[mshrs.scala:439:75] assign _atomics_T_1_param = _GEN_10; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire [2:0] _atomics_T_1_source = _atomics_T ? 3'h5 : 3'h0; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [15:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 16'h0; // @[Edges.scala:534:17] wire [127:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 128'h0; // @[Edges.scala:534:17] wire _T_18 = req_uop_mem_cmd == 5'h9; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_2; // @[mshrs.scala:439:75] assign _atomics_T_2 = _T_18; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_1; // @[package.scala:16:47] assign _io_mem_access_bits_T_1 = _T_18; // @[package.scala:16:47] wire _io_mem_access_bits_T_25; // @[package.scala:16:47] assign _io_mem_access_bits_T_25 = _T_18; // @[package.scala:16:47] wire _send_resp_T_8; // @[package.scala:16:47] assign _send_resp_T_8 = _T_18; // @[package.scala:16:47] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire [2:0] _atomics_T_3_source = _atomics_T_2 ? 3'h5 : _atomics_T_1_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire _T_19 = req_uop_mem_cmd == 5'hA; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_4; // @[mshrs.scala:439:75] assign _atomics_T_4 = _T_19; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_2; // @[package.scala:16:47] assign _io_mem_access_bits_T_2 = _T_19; // @[package.scala:16:47] wire _io_mem_access_bits_T_26; // @[package.scala:16:47] assign _io_mem_access_bits_T_26 = _T_19; // @[package.scala:16:47] wire _send_resp_T_9; // @[package.scala:16:47] assign _send_resp_T_9 = _T_19; // @[package.scala:16:47] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire [2:0] _atomics_T_5_source = _atomics_T_4 ? 3'h5 : _atomics_T_3_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire _T_20 = req_uop_mem_cmd == 5'hB; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_6; // @[mshrs.scala:439:75] assign _atomics_T_6 = _T_20; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_3; // @[package.scala:16:47] assign _io_mem_access_bits_T_3 = _T_20; // @[package.scala:16:47] wire _io_mem_access_bits_T_27; // @[package.scala:16:47] assign _io_mem_access_bits_T_27 = _T_20; // @[package.scala:16:47] wire _send_resp_T_10; // @[package.scala:16:47] assign _send_resp_T_10 = _T_20; // @[package.scala:16:47] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire [2:0] _atomics_T_7_source = _atomics_T_6 ? 3'h5 : _atomics_T_5_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire _T_24 = req_uop_mem_cmd == 5'h8; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_8; // @[mshrs.scala:439:75] assign _atomics_T_8 = _T_24; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_7; // @[package.scala:16:47] assign _io_mem_access_bits_T_7 = _T_24; // @[package.scala:16:47] wire _io_mem_access_bits_T_31; // @[package.scala:16:47] assign _io_mem_access_bits_T_31 = _T_24; // @[package.scala:16:47] wire _send_resp_T_14; // @[package.scala:16:47] assign _send_resp_T_14 = _T_24; // @[package.scala:16:47] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_9_source = _atomics_T_8 ? 3'h5 : _atomics_T_7_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire _T_25 = req_uop_mem_cmd == 5'hC; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_10; // @[mshrs.scala:439:75] assign _atomics_T_10 = _T_25; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_8; // @[package.scala:16:47] assign _io_mem_access_bits_T_8 = _T_25; // @[package.scala:16:47] wire _io_mem_access_bits_T_32; // @[package.scala:16:47] assign _io_mem_access_bits_T_32 = _T_25; // @[package.scala:16:47] wire _send_resp_T_15; // @[package.scala:16:47] assign _send_resp_T_15 = _T_25; // @[package.scala:16:47] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_11_source = _atomics_T_10 ? 3'h5 : _atomics_T_9_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire _T_26 = req_uop_mem_cmd == 5'hD; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_12; // @[mshrs.scala:439:75] assign _atomics_T_12 = _T_26; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_9; // @[package.scala:16:47] assign _io_mem_access_bits_T_9 = _T_26; // @[package.scala:16:47] wire _io_mem_access_bits_T_33; // @[package.scala:16:47] assign _io_mem_access_bits_T_33 = _T_26; // @[package.scala:16:47] wire _send_resp_T_16; // @[package.scala:16:47] assign _send_resp_T_16 = _T_26; // @[package.scala:16:47] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_13_source = _atomics_T_12 ? 3'h5 : _atomics_T_11_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire _T_27 = req_uop_mem_cmd == 5'hE; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_14; // @[mshrs.scala:439:75] assign _atomics_T_14 = _T_27; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_10; // @[package.scala:16:47] assign _io_mem_access_bits_T_10 = _T_27; // @[package.scala:16:47] wire _io_mem_access_bits_T_34; // @[package.scala:16:47] assign _io_mem_access_bits_T_34 = _T_27; // @[package.scala:16:47] wire _send_resp_T_17; // @[package.scala:16:47] assign _send_resp_T_17 = _T_27; // @[package.scala:16:47] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_15_source = _atomics_T_14 ? 3'h5 : _atomics_T_13_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire _T_28 = req_uop_mem_cmd == 5'hF; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_16; // @[mshrs.scala:439:75] assign _atomics_T_16 = _T_28; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_11; // @[package.scala:16:47] assign _io_mem_access_bits_T_11 = _T_28; // @[package.scala:16:47] wire _io_mem_access_bits_T_35; // @[package.scala:16:47] assign _io_mem_access_bits_T_35 = _T_28; // @[package.scala:16:47] wire _send_resp_T_18; // @[package.scala:16:47] assign _send_resp_T_18 = _T_28; // @[package.scala:16:47] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[mshrs.scala:439:75] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[mshrs.scala:439:75] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire [2:0] atomics_source = _atomics_T_16 ? 3'h5 : _atomics_T_15_source; // @[mshrs.scala:439:75] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [15:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [127:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17]

Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1)) }) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf || io.b.isInf val notNaN_isZeroOut = io.a.isZero || io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN || io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }

module MulRawFN_30( // @[MulRecFN.scala:75:7] input io_a_isNaN, // @[MulRecFN.scala:77:16] input io_a_isInf, // @[MulRecFN.scala:77:16] input io_a_isZero, // @[MulRecFN.scala:77:16] input io_a_sign, // @[MulRecFN.scala:77:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_a_sig, // @[MulRecFN.scala:77:16] input io_b_isNaN, // @[MulRecFN.scala:77:16] input io_b_isInf, // @[MulRecFN.scala:77:16] input io_b_isZero, // @[MulRecFN.scala:77:16] input io_b_sign, // @[MulRecFN.scala:77:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_b_sig, // @[MulRecFN.scala:77:16] output io_invalidExc, // @[MulRecFN.scala:77:16] output io_rawOut_isNaN, // @[MulRecFN.scala:77:16] output io_rawOut_isInf, // @[MulRecFN.scala:77:16] output io_rawOut_isZero, // @[MulRecFN.scala:77:16] output io_rawOut_sign, // @[MulRecFN.scala:77:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16] output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16] ); wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28] wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7] wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7] wire io_invalidExc_0; // @[MulRecFN.scala:75:7] wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15] wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37] wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}] assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10] MulFullRawFN_30 mulFullRaw ( // @[MulRecFN.scala:84:28] .io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7] .io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7] .io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7] .io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7] .io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7] .io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7] .io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7] .io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7] .io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7] .io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7] .io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7] .io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7] .io_invalidExc (io_invalidExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (_mulFullRaw_io_rawOut_sig) ); // @[MulRecFN.scala:84:28] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_50( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [13:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [13:0] source_1; // @[Monitor.scala:541:22] reg [8207:0] inflight; // @[Monitor.scala:614:27] reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [8207:0] inflight_1; // @[Monitor.scala:726:35] reg [32831:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_194( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundAnyRawFNToRecFN_ie6_is32_oe8_os24( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [7:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [32:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire roundingMode_near_even = io_roundingMode == 3'h0; // @[RoundAnyRawFNToRecFN.scala:90:53] wire [1:0] _GEN = {io_in_sig[7], |(io_in_sig[6:0])}; // @[RoundAnyRawFNToRecFN.scala:116:66, :117:{26,60}, :164:56, :165:62, :166:36] wire [25:0] roundedSig = (roundingMode_near_even | io_roundingMode == 3'h4) & io_in_sig[7] | (io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign) & (|_GEN) ? {1'h0, io_in_sig[32:8]} + 26'h1 & {25'h1FFFFFF, ~(roundingMode_near_even & io_in_sig[7] & ~(|(io_in_sig[6:0])))} : {1'h0, io_in_sig[32:9], io_in_sig[8] | io_roundingMode == 3'h6 & (|_GEN)}; // @[RoundAnyRawFNToRecFN.scala:90:53, :92:53, :93:53, :94:53, :95:53, :98:{27,42,63,66}, :106:31, :116:66, :117:{26,60}, :164:{40,56}, :165:62, :166:36, :169:{38,67}, :170:31, :171:29, :173:16, :174:{49,57}, :175:{21,25,49,64}, :176:30, :180:47, :181:42] assign io_out = {io_in_sign, {io_in_sExp[7], io_in_sExp} + {7'h0, roundedSig[25:24]} + 9'hC0 & ~(io_in_isZero ? 9'h1C0 : 9'h0), io_in_isZero ? 23'h0 : roundedSig[22:0]}; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25, :173:16, :185:{40,54}, :191:27, :252:24, :253:{14,18}, :280:12, :281:16, :286:33] endmodule

Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }

module dataMems_239( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule

Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1)) }) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf || io.b.isInf val notNaN_isZeroOut = io.a.isZero || io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN || io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }

module MulRawFN_8( // @[MulRecFN.scala:75:7] input io_a_isNaN, // @[MulRecFN.scala:77:16] input io_a_isInf, // @[MulRecFN.scala:77:16] input io_a_isZero, // @[MulRecFN.scala:77:16] input io_a_sign, // @[MulRecFN.scala:77:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_a_sig, // @[MulRecFN.scala:77:16] input io_b_isNaN, // @[MulRecFN.scala:77:16] input io_b_isInf, // @[MulRecFN.scala:77:16] input io_b_isZero, // @[MulRecFN.scala:77:16] input io_b_sign, // @[MulRecFN.scala:77:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_b_sig, // @[MulRecFN.scala:77:16] output io_invalidExc, // @[MulRecFN.scala:77:16] output io_rawOut_isNaN, // @[MulRecFN.scala:77:16] output io_rawOut_isInf, // @[MulRecFN.scala:77:16] output io_rawOut_isZero, // @[MulRecFN.scala:77:16] output io_rawOut_sign, // @[MulRecFN.scala:77:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16] output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16] ); wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28] wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7] wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7] wire io_invalidExc_0; // @[MulRecFN.scala:75:7] wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15] wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37] wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}] assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10] MulFullRawFN_8 mulFullRaw ( // @[MulRecFN.scala:84:28] .io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7] .io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7] .io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7] .io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7] .io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7] .io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7] .io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7] .io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7] .io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7] .io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7] .io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7] .io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7] .io_invalidExc (io_invalidExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (_mulFullRaw_io_rawOut_sig) ); // @[MulRecFN.scala:84:28] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File RVC.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class ExpandedInstruction extends Bundle { val bits = UInt(32.W) val rd = UInt(5.W) val rs1 = UInt(5.W) val rs2 = UInt(5.W) val rs3 = UInt(5.W) } class RVCDecoder(x: UInt, xLen: Int, fLen: Int, useAddiForMv: Boolean = false) { def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = { val res = Wire(new ExpandedInstruction) res.bits := bits res.rd := rd res.rs1 := rs1 res.rs2 := rs2 res.rs3 := rs3 res } def rs1p = Cat(1.U(2.W), x(9,7)) def rs2p = Cat(1.U(2.W), x(4,2)) def rs2 = x(6,2) def rd = x(11,7) def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W)) def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W)) def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W)) def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W)) def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W)) def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W)) def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W)) def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W)) def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W)) def addiImm = Cat(Fill(7, x(12)), x(6,2)) def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W)) def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W)) def shamt = Cat(x(12), x(6,2)) def x0 = 0.U(5.W) def ra = 1.U(5.W) def sp = 2.U(5.W) def q0 = { def addi4spn = { val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W)) inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p) } def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) def flw = { if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) else ld } def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p) def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) def fsw = { if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) else sd } Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw) } def q1 = { def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p) def addiw = { val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W)) inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p) } def jal = { if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p) else addiw } def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p) def addi16sp = { val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W)) inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p) } def lui = { val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W)) val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p) Mux(rd === x0 || rd === sp, addi16sp, me) } def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p) def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0) def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0) def arith = { def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)) def srai = srli | (1 << 30).U def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)) def rtype = { val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5))) val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U) val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W)) Cat(rs2p, rs1p, funct, rs1p, opc) | sub } inst(Seq(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p) } Seq(addi, jal, li, lui, arith, j, beqz, bnez) } def q2 = { val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W)) def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2) def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2) def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2) def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2) def flwsp = { if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2) else ldsp } def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2) def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2) def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2) def fswsp = { if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2) else sdsp } def jalr = { val mv = { if (useAddiForMv) inst(Cat(rs2, 0.U(3.W), rd, 0x13.U(7.W)), rd, rs2, x0) else inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2) } val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2) val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W)) val reserved = Cat(jr >> 7, 0x1F.U(7.W)) val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2) val jr_mv = Mux(rs2.orR, mv, jr_reserved) val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W)) val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2) val jalr_add = Mux(rs2.orR, add, jalr_ebreak) Mux(x(12), jalr_add, jr_mv) } Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp) } def q3 = Seq.fill(8)(passthrough) def passthrough = inst(x) def decode = { val s = q0 ++ q1 ++ q2 ++ q3 s(Cat(x(1,0), x(15,13))) } def q0_ill = { def allz = !(x(12, 2).orR) def fld = if (fLen >= 64) false.B else true.B def flw32 = if (xLen == 64 || fLen >= 32) false.B else true.B def fsd = if (fLen >= 64) false.B else true.B def fsw32 = if (xLen == 64 || fLen >= 32) false.B else true.B Seq(allz, fld, false.B, flw32, true.B, fsd, false.B, fsw32) } def q1_ill = { def rd0 = if (xLen == 32) false.B else rd === 0.U def immz = !(x(12) | x(6, 2).orR) def arith_res = x(12, 10).andR && (if (xLen == 32) true.B else x(6) === 1.U) Seq(false.B, rd0, false.B, immz, arith_res, false.B, false.B, false.B) } def q2_ill = { def fldsp = if (fLen >= 64) false.B else true.B def rd0 = rd === 0.U def flwsp = if (xLen == 64) rd0 else if (fLen >= 32) false.B else true.B def jr_res = !(x(12 ,2).orR) def fsdsp = if (fLen >= 64) false.B else true.B def fswsp32 = if (xLen == 64) false.B else if (fLen >= 32) false.B else true.B Seq(false.B, fldsp, rd0, flwsp, jr_res, fsdsp, false.B, fswsp32) } def q3_ill = Seq.fill(8)(false.B) def ill = { val s = q0_ill ++ q1_ill ++ q2_ill ++ q3_ill s(Cat(x(1,0), x(15,13))) } } class RVCExpander(useAddiForMv: Boolean = false)(implicit val p: Parameters) extends Module with HasCoreParameters { val io = IO(new Bundle { val in = Input(UInt(32.W)) val out = Output(new ExpandedInstruction) val rvc = Output(Bool()) val ill = Output(Bool()) }) if (usingCompressed) { io.rvc := io.in(1,0) =/= 3.U val decoder = new RVCDecoder(io.in, xLen, fLen, useAddiForMv) io.out := decoder.decode io.ill := decoder.ill } else { io.rvc := false.B io.out := new RVCDecoder(io.in, xLen, fLen, useAddiForMv).passthrough io.ill := false.B // only used for RVC } }

module RVCExpander_1( // @[RVC.scala:190:7] input clock, // @[RVC.scala:190:7] input reset, // @[RVC.scala:190:7] input [31:0] io_in, // @[RVC.scala:191:14] output [31:0] io_out_bits, // @[RVC.scala:191:14] output io_rvc // @[RVC.scala:191:14] ); wire [31:0] io_in_0 = io_in; // @[RVC.scala:190:7] wire [11:0] io_out_s_jr_lo = 12'h67; // @[RVC.scala:135:19] wire [4:0] io_out_s_10_rs1 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_13_rd = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_14_rs2 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_15_rd = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_15_rs2 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_mv_rs1 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_jr_reserved_rd = 5'h0; // @[RVC.scala:21:19] wire [11:0] io_out_s_jalr_lo = 12'hE7; // @[RVC.scala:139:21] wire [4:0] io_out_s_jalr_ebreak_rd = 5'h1; // @[package.scala:39:86] wire [4:0] io_out_s_0_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_17_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_18_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_19_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_21_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_22_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_23_rs1 = 5'h2; // @[package.scala:39:86] wire [31:0] io_out_s_24_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_25_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_26_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_27_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_28_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_29_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_30_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_31_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] _io_out_T_64_bits; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rd; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs1; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs2; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs3; // @[package.scala:39:76] wire _io_rvc_T_1; // @[RVC.scala:199:26] wire _io_ill_T_64; // @[package.scala:39:76] wire [31:0] io_out_bits_0; // @[RVC.scala:190:7] wire [4:0] io_out_rd; // @[RVC.scala:190:7] wire [4:0] io_out_rs1; // @[RVC.scala:190:7] wire [4:0] io_out_rs2; // @[RVC.scala:190:7] wire [4:0] io_out_rs3; // @[RVC.scala:190:7] wire io_rvc_0; // @[RVC.scala:190:7] wire io_ill; // @[RVC.scala:190:7] wire [1:0] _io_rvc_T = io_in_0[1:0]; // @[RVC.scala:190:7, :199:20] wire [1:0] _io_out_T = io_in_0[1:0]; // @[RVC.scala:154:12, :190:7, :199:20] wire [1:0] _io_ill_T = io_in_0[1:0]; // @[RVC.scala:186:12, :190:7, :199:20] assign _io_rvc_T_1 = _io_rvc_T != 2'h3; // @[RVC.scala:199:{20,26}] assign io_rvc_0 = _io_rvc_T_1; // @[RVC.scala:190:7, :199:26] wire [7:0] _io_out_s_opc_T = io_in_0[12:5]; // @[RVC.scala:53:22, :190:7] wire _io_out_s_opc_T_1 = |_io_out_s_opc_T; // @[RVC.scala:53:{22,29}] wire [6:0] io_out_s_opc = _io_out_s_opc_T_1 ? 7'h13 : 7'h1F; // @[RVC.scala:53:{20,29}] wire [3:0] _io_out_s_T = io_in_0[10:7]; // @[RVC.scala:34:26, :190:7] wire [1:0] _io_out_s_T_1 = io_in_0[12:11]; // @[RVC.scala:34:35, :190:7] wire _io_out_s_T_2 = io_in_0[5]; // @[RVC.scala:34:45, :190:7] wire _io_out_s_T_28 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_59 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_68 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_101 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_110 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_185 = io_in_0[5]; // @[RVC.scala:34:45, :42:50, :190:7] wire _io_out_s_T_3 = io_in_0[6]; // @[RVC.scala:34:51, :190:7] wire _io_out_s_T_30 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_61 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_70 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_103 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_112 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_187 = io_in_0[6]; // @[RVC.scala:34:51, :42:62, :190:7] wire _io_out_s_T_249 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_260 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_271 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_282 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_ill_s_T_9 = io_in_0[6]; // @[RVC.scala:34:51, :169:69, :190:7] wire [2:0] io_out_s_lo = {_io_out_s_T_3, 2'h0}; // @[RVC.scala:34:{24,51}] wire [5:0] io_out_s_hi_hi = {_io_out_s_T, _io_out_s_T_1}; // @[RVC.scala:34:{24,26,35}] wire [6:0] io_out_s_hi = {io_out_s_hi_hi, _io_out_s_T_2}; // @[RVC.scala:34:{24,45}] wire [9:0] _io_out_s_T_4 = {io_out_s_hi, io_out_s_lo}; // @[RVC.scala:34:24] wire [2:0] _io_out_s_T_5 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_8 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_10 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_18 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_21 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_25 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_34 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_37 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_41 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_49 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_52 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_56 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_64 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_74 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_78 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_85 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_94 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_98 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_106 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_116 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_120 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_127 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_136 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_140 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_152 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_164 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_174 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_me_T_9 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_194 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_223 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_242 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_292 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_383 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7] wire [2:0] _io_out_s_T_401 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7] wire [4:0] _io_out_s_T_6 = {2'h1, _io_out_s_T_5}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_1 = {_io_out_s_T_6, io_out_s_opc}; // @[RVC.scala:31:17, :53:20, :54:15] wire [14:0] io_out_s_hi_hi_1 = {_io_out_s_T_4, 5'h2}; // @[package.scala:39:86] wire [17:0] io_out_s_hi_1 = {io_out_s_hi_hi_1, 3'h0}; // @[RVC.scala:54:15] wire [29:0] _io_out_s_T_7 = {io_out_s_hi_1, io_out_s_lo_1}; // @[RVC.scala:54:15] wire [4:0] _io_out_s_T_9 = {2'h1, _io_out_s_T_8}; // @[package.scala:39:86] wire [4:0] io_out_s_0_rd = _io_out_s_T_9; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_11 = {2'h1, _io_out_s_T_10}; // @[package.scala:39:86] wire [4:0] io_out_s_0_rs2 = _io_out_s_T_11; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_12 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_27 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_43 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_58 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_80 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_100 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_122 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_142 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_154 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_166 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_176 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_me_T_11 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_196 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_244 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_294 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_334 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_372 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_382 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_391 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_400 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_409 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_mv_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_add_T_7 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_jr_reserved_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_423 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_436 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_449 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_453 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_457 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_461 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_465 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_469 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_473 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_477 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_481 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] io_out_s_0_rs3 = _io_out_s_T_12; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_0_bits; // @[RVC.scala:21:19] assign io_out_s_0_bits = {2'h0, _io_out_s_T_7}; // @[RVC.scala:21:19, :22:14, :54:15] wire [1:0] _io_out_s_T_13 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_44 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_81 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_89 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_123 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_131 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_funct_T_1 = io_in_0[6:5]; // @[RVC.scala:36:20, :102:77, :190:7] wire [1:0] _io_out_s_sub_T = io_in_0[6:5]; // @[RVC.scala:36:20, :103:24, :190:7] wire [1:0] _io_out_s_T_297 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_305 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_315 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_323 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_337 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_345 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_355 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_363 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_385 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7] wire [1:0] _io_out_s_T_403 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7] wire [2:0] _io_out_s_T_14 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_29 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_45 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_60 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_69 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_82 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_90 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_102 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_111 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_124 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_132 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_412 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_417 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_438 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_443 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_ill_s_T_7 = io_in_0[12:10]; // @[RVC.scala:36:28, :169:22, :190:7] wire [4:0] io_out_s_hi_2 = {_io_out_s_T_13, _io_out_s_T_14}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_15 = {io_out_s_hi_2, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_16 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_23 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_32 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_39 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_47 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_54 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_66 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_76 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_87 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_96 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_108 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_118 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_129 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_138 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_200 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_202 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_208 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_210 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_218 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_220 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_225 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_227 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_238 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_240 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_290 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_311 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_330 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_332 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_351 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_370 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_411 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_416 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_437 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_442 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [4:0] _io_out_s_T_17 = {2'h1, _io_out_s_T_16}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_19 = {2'h1, _io_out_s_T_18}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_2 = {_io_out_s_T_19, 7'h7}; // @[RVC.scala:31:17, :58:23] wire [12:0] io_out_s_hi_hi_2 = {_io_out_s_T_15, _io_out_s_T_17}; // @[RVC.scala:30:17, :36:18, :58:23] wire [15:0] io_out_s_hi_3 = {io_out_s_hi_hi_2, 3'h3}; // @[RVC.scala:58:23] wire [27:0] _io_out_s_T_20 = {io_out_s_hi_3, io_out_s_lo_2}; // @[RVC.scala:58:23] wire [4:0] _io_out_s_T_22 = {2'h1, _io_out_s_T_21}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rd = _io_out_s_T_22; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_24 = {2'h1, _io_out_s_T_23}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rs1 = _io_out_s_T_24; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_26 = {2'h1, _io_out_s_T_25}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rs2 = _io_out_s_T_26; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_1_rs3 = _io_out_s_T_27; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_1_bits; // @[RVC.scala:21:19] assign io_out_s_1_bits = {4'h0, _io_out_s_T_20}; // @[RVC.scala:21:19, :22:14, :58:23] wire [2:0] io_out_s_lo_3 = {_io_out_s_T_30, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_4 = {_io_out_s_T_28, _io_out_s_T_29}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_31 = {io_out_s_hi_4, io_out_s_lo_3}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_33 = {2'h1, _io_out_s_T_32}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_35 = {2'h1, _io_out_s_T_34}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_4 = {_io_out_s_T_35, 7'h3}; // @[RVC.scala:31:17, :57:22] wire [11:0] io_out_s_hi_hi_3 = {_io_out_s_T_31, _io_out_s_T_33}; // @[RVC.scala:30:17, :35:18, :57:22] wire [14:0] io_out_s_hi_5 = {io_out_s_hi_hi_3, 3'h2}; // @[package.scala:39:86] wire [26:0] _io_out_s_T_36 = {io_out_s_hi_5, io_out_s_lo_4}; // @[RVC.scala:57:22] wire [4:0] _io_out_s_T_38 = {2'h1, _io_out_s_T_37}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rd = _io_out_s_T_38; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_40 = {2'h1, _io_out_s_T_39}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rs1 = _io_out_s_T_40; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_42 = {2'h1, _io_out_s_T_41}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rs2 = _io_out_s_T_42; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_2_rs3 = _io_out_s_T_43; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_2_bits; // @[RVC.scala:21:19] assign io_out_s_2_bits = {5'h0, _io_out_s_T_36}; // @[RVC.scala:21:19, :22:14, :57:22] wire [4:0] io_out_s_hi_6 = {_io_out_s_T_44, _io_out_s_T_45}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_46 = {io_out_s_hi_6, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_48 = {2'h1, _io_out_s_T_47}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_50 = {2'h1, _io_out_s_T_49}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_5 = {_io_out_s_T_50, 7'h3}; // @[RVC.scala:31:17, :56:22] wire [12:0] io_out_s_hi_hi_4 = {_io_out_s_T_46, _io_out_s_T_48}; // @[RVC.scala:30:17, :36:18, :56:22] wire [15:0] io_out_s_hi_7 = {io_out_s_hi_hi_4, 3'h3}; // @[RVC.scala:56:22] wire [27:0] _io_out_s_T_51 = {io_out_s_hi_7, io_out_s_lo_5}; // @[RVC.scala:56:22] wire [4:0] _io_out_s_T_53 = {2'h1, _io_out_s_T_52}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rd = _io_out_s_T_53; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_55 = {2'h1, _io_out_s_T_54}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rs1 = _io_out_s_T_55; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_57 = {2'h1, _io_out_s_T_56}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rs2 = _io_out_s_T_57; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_3_rs3 = _io_out_s_T_58; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_3_bits; // @[RVC.scala:21:19] assign io_out_s_3_bits = {4'h0, _io_out_s_T_51}; // @[RVC.scala:21:19, :22:14, :56:22] wire [2:0] io_out_s_lo_6 = {_io_out_s_T_61, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_8 = {_io_out_s_T_59, _io_out_s_T_60}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_62 = {io_out_s_hi_8, io_out_s_lo_6}; // @[RVC.scala:35:18] wire [1:0] _io_out_s_T_63 = _io_out_s_T_62[6:5]; // @[RVC.scala:35:18, :63:32] wire [4:0] _io_out_s_T_65 = {2'h1, _io_out_s_T_64}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_67 = {2'h1, _io_out_s_T_66}; // @[package.scala:39:86] wire [2:0] io_out_s_lo_7 = {_io_out_s_T_70, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_9 = {_io_out_s_T_68, _io_out_s_T_69}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_71 = {io_out_s_hi_9, io_out_s_lo_7}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_72 = _io_out_s_T_71[4:0]; // @[RVC.scala:35:18, :63:65] wire [7:0] io_out_s_lo_hi = {3'h2, _io_out_s_T_72}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_8 = {io_out_s_lo_hi, 7'h3F}; // @[RVC.scala:63:25] wire [6:0] io_out_s_hi_hi_5 = {_io_out_s_T_63, _io_out_s_T_65}; // @[RVC.scala:31:17, :63:{25,32}] wire [11:0] io_out_s_hi_10 = {io_out_s_hi_hi_5, _io_out_s_T_67}; // @[RVC.scala:30:17, :63:25] wire [26:0] _io_out_s_T_73 = {io_out_s_hi_10, io_out_s_lo_8}; // @[RVC.scala:63:25] wire [4:0] _io_out_s_T_75 = {2'h1, _io_out_s_T_74}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rd = _io_out_s_T_75; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_77 = {2'h1, _io_out_s_T_76}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rs1 = _io_out_s_T_77; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_79 = {2'h1, _io_out_s_T_78}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rs2 = _io_out_s_T_79; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_4_rs3 = _io_out_s_T_80; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_4_bits; // @[RVC.scala:21:19] assign io_out_s_4_bits = {5'h0, _io_out_s_T_73}; // @[RVC.scala:21:19, :22:14, :63:25] wire [4:0] io_out_s_hi_11 = {_io_out_s_T_81, _io_out_s_T_82}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_83 = {io_out_s_hi_11, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_84 = _io_out_s_T_83[7:5]; // @[RVC.scala:36:18, :66:30] wire [4:0] _io_out_s_T_86 = {2'h1, _io_out_s_T_85}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_88 = {2'h1, _io_out_s_T_87}; // @[package.scala:39:86] wire [4:0] io_out_s_hi_12 = {_io_out_s_T_89, _io_out_s_T_90}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_91 = {io_out_s_hi_12, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_92 = _io_out_s_T_91[4:0]; // @[RVC.scala:36:18, :66:63] wire [7:0] io_out_s_lo_hi_1 = {3'h3, _io_out_s_T_92}; // @[RVC.scala:66:{23,63}] wire [14:0] io_out_s_lo_9 = {io_out_s_lo_hi_1, 7'h27}; // @[RVC.scala:66:23] wire [7:0] io_out_s_hi_hi_6 = {_io_out_s_T_84, _io_out_s_T_86}; // @[RVC.scala:31:17, :66:{23,30}] wire [12:0] io_out_s_hi_13 = {io_out_s_hi_hi_6, _io_out_s_T_88}; // @[RVC.scala:30:17, :66:23] wire [27:0] _io_out_s_T_93 = {io_out_s_hi_13, io_out_s_lo_9}; // @[RVC.scala:66:23] wire [4:0] _io_out_s_T_95 = {2'h1, _io_out_s_T_94}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rd = _io_out_s_T_95; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_97 = {2'h1, _io_out_s_T_96}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rs1 = _io_out_s_T_97; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_99 = {2'h1, _io_out_s_T_98}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rs2 = _io_out_s_T_99; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_5_rs3 = _io_out_s_T_100; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_5_bits; // @[RVC.scala:21:19] assign io_out_s_5_bits = {4'h0, _io_out_s_T_93}; // @[RVC.scala:21:19, :22:14, :66:23] wire [2:0] io_out_s_lo_10 = {_io_out_s_T_103, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_14 = {_io_out_s_T_101, _io_out_s_T_102}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_104 = {io_out_s_hi_14, io_out_s_lo_10}; // @[RVC.scala:35:18] wire [1:0] _io_out_s_T_105 = _io_out_s_T_104[6:5]; // @[RVC.scala:35:18, :65:29] wire [4:0] _io_out_s_T_107 = {2'h1, _io_out_s_T_106}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_109 = {2'h1, _io_out_s_T_108}; // @[package.scala:39:86] wire [2:0] io_out_s_lo_11 = {_io_out_s_T_112, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_15 = {_io_out_s_T_110, _io_out_s_T_111}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_113 = {io_out_s_hi_15, io_out_s_lo_11}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_114 = _io_out_s_T_113[4:0]; // @[RVC.scala:35:18, :65:62] wire [7:0] io_out_s_lo_hi_2 = {3'h2, _io_out_s_T_114}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_12 = {io_out_s_lo_hi_2, 7'h23}; // @[RVC.scala:65:22] wire [6:0] io_out_s_hi_hi_7 = {_io_out_s_T_105, _io_out_s_T_107}; // @[RVC.scala:31:17, :65:{22,29}] wire [11:0] io_out_s_hi_16 = {io_out_s_hi_hi_7, _io_out_s_T_109}; // @[RVC.scala:30:17, :65:22] wire [26:0] _io_out_s_T_115 = {io_out_s_hi_16, io_out_s_lo_12}; // @[RVC.scala:65:22] wire [4:0] _io_out_s_T_117 = {2'h1, _io_out_s_T_116}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rd = _io_out_s_T_117; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_119 = {2'h1, _io_out_s_T_118}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rs1 = _io_out_s_T_119; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_121 = {2'h1, _io_out_s_T_120}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rs2 = _io_out_s_T_121; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_6_rs3 = _io_out_s_T_122; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_6_bits; // @[RVC.scala:21:19] assign io_out_s_6_bits = {5'h0, _io_out_s_T_115}; // @[RVC.scala:21:19, :22:14, :65:22] wire [4:0] io_out_s_hi_17 = {_io_out_s_T_123, _io_out_s_T_124}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_125 = {io_out_s_hi_17, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_126 = _io_out_s_T_125[7:5]; // @[RVC.scala:36:18, :64:29] wire [4:0] _io_out_s_T_128 = {2'h1, _io_out_s_T_127}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_130 = {2'h1, _io_out_s_T_129}; // @[package.scala:39:86] wire [4:0] io_out_s_hi_18 = {_io_out_s_T_131, _io_out_s_T_132}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_133 = {io_out_s_hi_18, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_134 = _io_out_s_T_133[4:0]; // @[RVC.scala:36:18, :64:62] wire [7:0] io_out_s_lo_hi_3 = {3'h3, _io_out_s_T_134}; // @[RVC.scala:64:{22,62}] wire [14:0] io_out_s_lo_13 = {io_out_s_lo_hi_3, 7'h23}; // @[RVC.scala:64:22] wire [7:0] io_out_s_hi_hi_8 = {_io_out_s_T_126, _io_out_s_T_128}; // @[RVC.scala:31:17, :64:{22,29}] wire [12:0] io_out_s_hi_19 = {io_out_s_hi_hi_8, _io_out_s_T_130}; // @[RVC.scala:30:17, :64:22] wire [27:0] _io_out_s_T_135 = {io_out_s_hi_19, io_out_s_lo_13}; // @[RVC.scala:64:22] wire [4:0] _io_out_s_T_137 = {2'h1, _io_out_s_T_136}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rd = _io_out_s_T_137; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_139 = {2'h1, _io_out_s_T_138}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rs1 = _io_out_s_T_139; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_141 = {2'h1, _io_out_s_T_140}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rs2 = _io_out_s_T_141; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_7_rs3 = _io_out_s_T_142; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_7_bits; // @[RVC.scala:21:19] assign io_out_s_7_bits = {4'h0, _io_out_s_T_135}; // @[RVC.scala:21:19, :22:14, :64:22] wire _io_out_s_T_143 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_155 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_167 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_opc_T_4 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_me_T = io_in_0[12]; // @[RVC.scala:41:30, :43:30, :190:7] wire _io_out_s_opc_T_9 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_182 = io_in_0[12]; // @[RVC.scala:42:34, :43:30, :190:7] wire _io_out_s_T_197 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_205 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_214 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_funct_T = io_in_0[12]; // @[RVC.scala:43:30, :102:70, :190:7] wire _io_out_s_opc_T_14 = io_in_0[12]; // @[RVC.scala:43:30, :104:24, :190:7] wire _io_out_s_T_245 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_256 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_267 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_278 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_295 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_303 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_313 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_321 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_335 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_343 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_353 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_361 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_373 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_384 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7] wire _io_out_s_T_393 = io_in_0[12]; // @[RVC.scala:37:30, :43:30, :190:7] wire _io_out_s_T_402 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7] wire _io_out_s_T_410 = io_in_0[12]; // @[RVC.scala:43:30, :143:12, :190:7] wire _io_ill_s_T_3 = io_in_0[12]; // @[RVC.scala:43:30, :168:19, :190:7] wire [6:0] _io_out_s_T_144 = {7{_io_out_s_T_143}}; // @[RVC.scala:43:{25,30}] wire [4:0] _io_out_s_T_145 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_157 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_169 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_opc_T_6 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_me_T_2 = io_in_0[6:2]; // @[RVC.scala:41:38, :43:38, :190:7] wire [4:0] _io_out_s_opc_T_11 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_198 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_206 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_216 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_374 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_381 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_390 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_399 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_408 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_mv_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_add_T_6 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_reserved_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_415 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_422 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_428 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_435 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_441 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_448 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_ill_s_T_4 = io_in_0[6:2]; // @[RVC.scala:43:38, :168:27, :190:7] wire [11:0] _io_out_s_T_146 = {_io_out_s_T_144, _io_out_s_T_145}; // @[RVC.scala:43:{20,25,38}] wire [4:0] _io_out_s_T_147 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_148 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_150 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_151 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_opc_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_159 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_160 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_162 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_163 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_171 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_173 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_7 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_8 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_177 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_179 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_189 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_190 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_192 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_193 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_load_opc_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_376 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_377 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_379 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_380 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_387 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_389 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_396 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_398 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_405 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_407 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_mv_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_mv_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_4 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_reserved_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_reserved_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_421 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_434 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_447 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_450 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_454 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_458 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_462 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_466 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_470 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_474 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_478 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_ill_s_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_ill_s_T_11 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_ill_s_T_12 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [11:0] io_out_s_lo_14 = {_io_out_s_T_148, 7'h13}; // @[RVC.scala:33:13, :75:24] wire [16:0] io_out_s_hi_hi_9 = {_io_out_s_T_146, _io_out_s_T_147}; // @[RVC.scala:33:13, :43:20, :75:24] wire [19:0] io_out_s_hi_20 = {io_out_s_hi_hi_9, 3'h0}; // @[RVC.scala:75:24] wire [31:0] _io_out_s_T_149 = {io_out_s_hi_20, io_out_s_lo_14}; // @[RVC.scala:75:24] wire [31:0] io_out_s_8_bits = _io_out_s_T_149; // @[RVC.scala:21:19, :75:24] wire [4:0] io_out_s_8_rd = _io_out_s_T_150; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_8_rs1 = _io_out_s_T_151; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_153 = {2'h1, _io_out_s_T_152}; // @[package.scala:39:86] wire [4:0] io_out_s_8_rs2 = _io_out_s_T_153; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_8_rs3 = _io_out_s_T_154; // @[RVC.scala:20:101, :21:19] wire _io_out_s_opc_T_3 = |_io_out_s_opc_T_2; // @[RVC.scala:33:13, :77:24] wire [6:0] io_out_s_opc_1 = {4'h3, ~_io_out_s_opc_T_3, 2'h3}; // @[RVC.scala:77:{20,24}] wire [6:0] _io_out_s_T_156 = {7{_io_out_s_T_155}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_158 = {_io_out_s_T_156, _io_out_s_T_157}; // @[RVC.scala:43:{20,25,38}] wire [11:0] io_out_s_lo_15 = {_io_out_s_T_160, io_out_s_opc_1}; // @[RVC.scala:33:13, :77:20, :78:15] wire [16:0] io_out_s_hi_hi_10 = {_io_out_s_T_158, _io_out_s_T_159}; // @[RVC.scala:33:13, :43:20, :78:15] wire [19:0] io_out_s_hi_21 = {io_out_s_hi_hi_10, 3'h0}; // @[RVC.scala:78:15] wire [31:0] _io_out_s_T_161 = {io_out_s_hi_21, io_out_s_lo_15}; // @[RVC.scala:78:15] wire [31:0] io_out_s_9_bits = _io_out_s_T_161; // @[RVC.scala:21:19, :78:15] wire [4:0] io_out_s_9_rd = _io_out_s_T_162; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_9_rs1 = _io_out_s_T_163; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_165 = {2'h1, _io_out_s_T_164}; // @[package.scala:39:86] wire [4:0] io_out_s_9_rs2 = _io_out_s_T_165; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_9_rs3 = _io_out_s_T_166; // @[RVC.scala:20:101, :21:19] wire [6:0] _io_out_s_T_168 = {7{_io_out_s_T_167}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_170 = {_io_out_s_T_168, _io_out_s_T_169}; // @[RVC.scala:43:{20,25,38}] wire [11:0] io_out_s_lo_16 = {_io_out_s_T_171, 7'h13}; // @[RVC.scala:33:13, :84:22] wire [16:0] io_out_s_hi_hi_11 = {_io_out_s_T_170, 5'h0}; // @[RVC.scala:43:20, :84:22] wire [19:0] io_out_s_hi_22 = {io_out_s_hi_hi_11, 3'h0}; // @[RVC.scala:84:22] wire [31:0] _io_out_s_T_172 = {io_out_s_hi_22, io_out_s_lo_16}; // @[RVC.scala:84:22] wire [31:0] io_out_s_10_bits = _io_out_s_T_172; // @[RVC.scala:21:19, :84:22] wire [4:0] io_out_s_10_rd = _io_out_s_T_173; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_175 = {2'h1, _io_out_s_T_174}; // @[package.scala:39:86] wire [4:0] io_out_s_10_rs2 = _io_out_s_T_175; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_10_rs3 = _io_out_s_T_176; // @[RVC.scala:20:101, :21:19] wire [6:0] _io_out_s_opc_T_5 = {7{_io_out_s_opc_T_4}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_opc_T_7 = {_io_out_s_opc_T_5, _io_out_s_opc_T_6}; // @[RVC.scala:43:{20,25,38}] wire _io_out_s_opc_T_8 = |_io_out_s_opc_T_7; // @[RVC.scala:43:20, :90:29] wire [6:0] io_out_s_opc_2 = {3'h3, ~_io_out_s_opc_T_8, 3'h7}; // @[RVC.scala:90:{20,29}] wire [14:0] _io_out_s_me_T_1 = {15{_io_out_s_me_T}}; // @[RVC.scala:41:{24,30}] wire [19:0] io_out_s_me_hi = {_io_out_s_me_T_1, _io_out_s_me_T_2}; // @[RVC.scala:41:{19,24,38}] wire [31:0] _io_out_s_me_T_3 = {io_out_s_me_hi, 12'h0}; // @[RVC.scala:41:19] wire [19:0] _io_out_s_me_T_4 = _io_out_s_me_T_3[31:12]; // @[RVC.scala:41:19, :91:31] wire [24:0] io_out_s_me_hi_1 = {_io_out_s_me_T_4, _io_out_s_me_T_5}; // @[RVC.scala:33:13, :91:{24,31}] wire [31:0] _io_out_s_me_T_6 = {io_out_s_me_hi_1, io_out_s_opc_2}; // @[RVC.scala:90:20, :91:24] wire [31:0] io_out_s_me_bits = _io_out_s_me_T_6; // @[RVC.scala:21:19, :91:24] wire [4:0] io_out_s_me_rd = _io_out_s_me_T_7; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_me_rs1 = _io_out_s_me_T_8; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_me_T_10 = {2'h1, _io_out_s_me_T_9}; // @[package.scala:39:86] wire [4:0] io_out_s_me_rs2 = _io_out_s_me_T_10; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_me_rs3 = _io_out_s_me_T_11; // @[RVC.scala:20:101, :21:19] wire _io_out_s_T_178 = _io_out_s_T_177 == 5'h0; // @[RVC.scala:33:13, :92:14] wire _io_out_s_T_180 = _io_out_s_T_179 == 5'h2; // @[package.scala:39:86] wire _io_out_s_T_181 = _io_out_s_T_178 | _io_out_s_T_180; // @[RVC.scala:92:{14,21,27}] wire [6:0] _io_out_s_opc_T_10 = {7{_io_out_s_opc_T_9}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_opc_T_12 = {_io_out_s_opc_T_10, _io_out_s_opc_T_11}; // @[RVC.scala:43:{20,25,38}] wire _io_out_s_opc_T_13 = |_io_out_s_opc_T_12; // @[RVC.scala:43:20, :86:29] wire [6:0] io_out_s_opc_3 = _io_out_s_opc_T_13 ? 7'h13 : 7'h1F; // @[RVC.scala:86:{20,29}] wire [2:0] _io_out_s_T_183 = {3{_io_out_s_T_182}}; // @[RVC.scala:42:{29,34}] wire [1:0] _io_out_s_T_184 = io_in_0[4:3]; // @[RVC.scala:42:42, :190:7] wire [1:0] _io_out_s_T_300 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_308 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_318 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_326 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_340 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_348 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_358 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_366 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire _io_out_s_T_186 = io_in_0[2]; // @[RVC.scala:42:56, :190:7] wire _io_out_s_T_251 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_262 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_273 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_284 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_298 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_306 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_316 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_324 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_338 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_346 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_356 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_364 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire [1:0] io_out_s_lo_hi_4 = {_io_out_s_T_186, _io_out_s_T_187}; // @[RVC.scala:42:{24,56,62}] wire [5:0] io_out_s_lo_17 = {io_out_s_lo_hi_4, 4'h0}; // @[RVC.scala:42:24] wire [4:0] io_out_s_hi_hi_12 = {_io_out_s_T_183, _io_out_s_T_184}; // @[RVC.scala:42:{24,29,42}] wire [5:0] io_out_s_hi_23 = {io_out_s_hi_hi_12, _io_out_s_T_185}; // @[RVC.scala:42:{24,50}] wire [11:0] _io_out_s_T_188 = {io_out_s_hi_23, io_out_s_lo_17}; // @[RVC.scala:42:24] wire [11:0] io_out_s_lo_18 = {_io_out_s_T_190, io_out_s_opc_3}; // @[RVC.scala:33:13, :86:20, :87:15] wire [16:0] io_out_s_hi_hi_13 = {_io_out_s_T_188, _io_out_s_T_189}; // @[RVC.scala:33:13, :42:24, :87:15] wire [19:0] io_out_s_hi_24 = {io_out_s_hi_hi_13, 3'h0}; // @[RVC.scala:87:15] wire [31:0] _io_out_s_T_191 = {io_out_s_hi_24, io_out_s_lo_18}; // @[RVC.scala:87:15] wire [31:0] io_out_s_res_bits = _io_out_s_T_191; // @[RVC.scala:21:19, :87:15] wire [4:0] io_out_s_res_rd = _io_out_s_T_192; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_res_rs1 = _io_out_s_T_193; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_195 = {2'h1, _io_out_s_T_194}; // @[package.scala:39:86] wire [4:0] io_out_s_res_rs2 = _io_out_s_T_195; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_res_rs3 = _io_out_s_T_196; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_11_bits = _io_out_s_T_181 ? io_out_s_res_bits : io_out_s_me_bits; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rd = _io_out_s_T_181 ? io_out_s_res_rd : io_out_s_me_rd; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs1 = _io_out_s_T_181 ? io_out_s_res_rs1 : io_out_s_me_rs1; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs2 = _io_out_s_T_181 ? io_out_s_res_rs2 : io_out_s_me_rs2; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs3 = _io_out_s_T_181 ? io_out_s_res_rs3 : io_out_s_me_rs3; // @[RVC.scala:21:19, :92:{10,21}] wire [5:0] _io_out_s_T_199 = {_io_out_s_T_197, _io_out_s_T_198}; // @[RVC.scala:46:{18,20,27}] wire [4:0] _io_out_s_T_201 = {2'h1, _io_out_s_T_200}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_203 = {2'h1, _io_out_s_T_202}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_19 = {_io_out_s_T_203, 7'h13}; // @[RVC.scala:30:17, :98:21] wire [10:0] io_out_s_hi_hi_14 = {_io_out_s_T_199, _io_out_s_T_201}; // @[RVC.scala:30:17, :46:18, :98:21] wire [13:0] io_out_s_hi_25 = {io_out_s_hi_hi_14, 3'h5}; // @[RVC.scala:98:21] wire [25:0] _io_out_s_T_204 = {io_out_s_hi_25, io_out_s_lo_19}; // @[RVC.scala:98:21] wire [5:0] _io_out_s_T_207 = {_io_out_s_T_205, _io_out_s_T_206}; // @[RVC.scala:46:{18,20,27}] wire [4:0] _io_out_s_T_209 = {2'h1, _io_out_s_T_208}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_211 = {2'h1, _io_out_s_T_210}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_20 = {_io_out_s_T_211, 7'h13}; // @[RVC.scala:30:17, :98:21] wire [10:0] io_out_s_hi_hi_15 = {_io_out_s_T_207, _io_out_s_T_209}; // @[RVC.scala:30:17, :46:18, :98:21] wire [13:0] io_out_s_hi_26 = {io_out_s_hi_hi_15, 3'h5}; // @[RVC.scala:98:21] wire [25:0] _io_out_s_T_212 = {io_out_s_hi_26, io_out_s_lo_20}; // @[RVC.scala:98:21] wire [30:0] _io_out_s_T_213 = {5'h10, _io_out_s_T_212}; // @[RVC.scala:98:21, :99:23] wire [6:0] _io_out_s_T_215 = {7{_io_out_s_T_214}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_217 = {_io_out_s_T_215, _io_out_s_T_216}; // @[RVC.scala:43:{20,25,38}] wire [4:0] _io_out_s_T_219 = {2'h1, _io_out_s_T_218}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_221 = {2'h1, _io_out_s_T_220}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_21 = {_io_out_s_T_221, 7'h13}; // @[RVC.scala:30:17, :100:21] wire [16:0] io_out_s_hi_hi_16 = {_io_out_s_T_217, _io_out_s_T_219}; // @[RVC.scala:30:17, :43:20, :100:21] wire [19:0] io_out_s_hi_27 = {io_out_s_hi_hi_16, 3'h7}; // @[RVC.scala:100:21] wire [31:0] _io_out_s_T_222 = {io_out_s_hi_27, io_out_s_lo_21}; // @[RVC.scala:100:21] wire [2:0] _io_out_s_funct_T_2 = {_io_out_s_funct_T, _io_out_s_funct_T_1}; // @[RVC.scala:102:{68,70,77}] wire _io_out_s_funct_T_3 = _io_out_s_funct_T_2 == 3'h1; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_4 = {_io_out_s_funct_T_3, 2'h0}; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_5 = _io_out_s_funct_T_2 == 3'h2; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_6 = _io_out_s_funct_T_5 ? 3'h6 : _io_out_s_funct_T_4; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_7 = _io_out_s_funct_T_2 == 3'h3; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_8 = _io_out_s_funct_T_7 ? 3'h7 : _io_out_s_funct_T_6; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_9 = _io_out_s_funct_T_2 == 3'h4; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_10 = _io_out_s_funct_T_9 ? 3'h0 : _io_out_s_funct_T_8; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_11 = _io_out_s_funct_T_2 == 3'h5; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_12 = _io_out_s_funct_T_11 ? 3'h0 : _io_out_s_funct_T_10; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_13 = _io_out_s_funct_T_2 == 3'h6; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_14 = _io_out_s_funct_T_13 ? 3'h2 : _io_out_s_funct_T_12; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_15 = &_io_out_s_funct_T_2; // @[package.scala:39:86] wire [2:0] io_out_s_funct = _io_out_s_funct_T_15 ? 3'h3 : _io_out_s_funct_T_14; // @[package.scala:39:{76,86}] wire _io_out_s_sub_T_1 = _io_out_s_sub_T == 2'h0; // @[RVC.scala:103:{24,30}] wire [30:0] io_out_s_sub = {_io_out_s_sub_T_1, 30'h0}; // @[RVC.scala:103:{22,30}] wire [6:0] io_out_s_opc_4 = {3'h3, _io_out_s_opc_T_14, 3'h3}; // @[RVC.scala:104:{22,24}] wire [4:0] _io_out_s_T_224 = {2'h1, _io_out_s_T_223}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_226 = {2'h1, _io_out_s_T_225}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_228 = {2'h1, _io_out_s_T_227}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_22 = {_io_out_s_T_228, io_out_s_opc_4}; // @[RVC.scala:30:17, :104:22, :105:12] wire [9:0] io_out_s_hi_hi_17 = {_io_out_s_T_224, _io_out_s_T_226}; // @[RVC.scala:30:17, :31:17, :105:12] wire [12:0] io_out_s_hi_28 = {io_out_s_hi_hi_17, io_out_s_funct}; // @[package.scala:39:76] wire [24:0] _io_out_s_T_229 = {io_out_s_hi_28, io_out_s_lo_22}; // @[RVC.scala:105:12] wire [30:0] _io_out_s_T_230 = {6'h0, _io_out_s_T_229} | io_out_s_sub; // @[RVC.scala:103:22, :105:{12,43}] wire [1:0] _io_out_s_T_231 = io_in_0[11:10]; // @[RVC.scala:107:42, :190:7] wire [1:0] _io_out_s_T_299 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_307 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_317 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_325 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_339 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_347 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_357 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_365 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire _io_out_s_T_232 = _io_out_s_T_231 == 2'h1; // @[package.scala:39:86] wire [30:0] _io_out_s_T_233 = _io_out_s_T_232 ? _io_out_s_T_213 : {5'h0, _io_out_s_T_204}; // @[package.scala:39:{76,86}] wire _io_out_s_T_234 = _io_out_s_T_231 == 2'h2; // @[package.scala:39:86] wire [31:0] _io_out_s_T_235 = _io_out_s_T_234 ? _io_out_s_T_222 : {1'h0, _io_out_s_T_233}; // @[package.scala:39:{76,86}] wire _io_out_s_T_236 = &_io_out_s_T_231; // @[package.scala:39:86] wire [31:0] _io_out_s_T_237 = _io_out_s_T_236 ? {1'h0, _io_out_s_T_230} : _io_out_s_T_235; // @[package.scala:39:{76,86}] wire [31:0] io_out_s_12_bits = _io_out_s_T_237; // @[package.scala:39:76] wire [4:0] _io_out_s_T_239 = {2'h1, _io_out_s_T_238}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rd = _io_out_s_T_239; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_241 = {2'h1, _io_out_s_T_240}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rs1 = _io_out_s_T_241; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_243 = {2'h1, _io_out_s_T_242}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rs2 = _io_out_s_T_243; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_12_rs3 = _io_out_s_T_244; // @[RVC.scala:20:101, :21:19] wire [9:0] _io_out_s_T_246 = {10{_io_out_s_T_245}}; // @[RVC.scala:44:{22,28}] wire _io_out_s_T_247 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_258 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_269 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_280 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire [1:0] _io_out_s_T_248 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_259 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_270 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_281 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire _io_out_s_T_250 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_261 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_272 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_283 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_252 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_263 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_274 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_285 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire [2:0] _io_out_s_T_253 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_264 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_275 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_286 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [3:0] io_out_s_lo_lo = {_io_out_s_T_253, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_5 = {_io_out_s_T_251, _io_out_s_T_252}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_23 = {io_out_s_lo_hi_5, io_out_s_lo_lo}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo = {_io_out_s_T_249, _io_out_s_T_250}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi = {_io_out_s_T_246, _io_out_s_T_247}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_18 = {io_out_s_hi_hi_hi, _io_out_s_T_248}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_29 = {io_out_s_hi_hi_18, io_out_s_hi_lo}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_254 = {io_out_s_hi_29, io_out_s_lo_23}; // @[RVC.scala:44:17] wire _io_out_s_T_255 = _io_out_s_T_254[20]; // @[RVC.scala:44:17, :94:26] wire [9:0] _io_out_s_T_257 = {10{_io_out_s_T_256}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_1 = {_io_out_s_T_264, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_6 = {_io_out_s_T_262, _io_out_s_T_263}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_24 = {io_out_s_lo_hi_6, io_out_s_lo_lo_1}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_1 = {_io_out_s_T_260, _io_out_s_T_261}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_1 = {_io_out_s_T_257, _io_out_s_T_258}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_19 = {io_out_s_hi_hi_hi_1, _io_out_s_T_259}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_30 = {io_out_s_hi_hi_19, io_out_s_hi_lo_1}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_265 = {io_out_s_hi_30, io_out_s_lo_24}; // @[RVC.scala:44:17] wire [9:0] _io_out_s_T_266 = _io_out_s_T_265[10:1]; // @[RVC.scala:44:17, :94:36] wire [9:0] _io_out_s_T_268 = {10{_io_out_s_T_267}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_2 = {_io_out_s_T_275, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_7 = {_io_out_s_T_273, _io_out_s_T_274}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_25 = {io_out_s_lo_hi_7, io_out_s_lo_lo_2}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_2 = {_io_out_s_T_271, _io_out_s_T_272}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_2 = {_io_out_s_T_268, _io_out_s_T_269}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_20 = {io_out_s_hi_hi_hi_2, _io_out_s_T_270}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_31 = {io_out_s_hi_hi_20, io_out_s_hi_lo_2}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_276 = {io_out_s_hi_31, io_out_s_lo_25}; // @[RVC.scala:44:17] wire _io_out_s_T_277 = _io_out_s_T_276[11]; // @[RVC.scala:44:17, :94:48] wire [9:0] _io_out_s_T_279 = {10{_io_out_s_T_278}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_3 = {_io_out_s_T_286, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_8 = {_io_out_s_T_284, _io_out_s_T_285}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_26 = {io_out_s_lo_hi_8, io_out_s_lo_lo_3}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_3 = {_io_out_s_T_282, _io_out_s_T_283}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_3 = {_io_out_s_T_279, _io_out_s_T_280}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_21 = {io_out_s_hi_hi_hi_3, _io_out_s_T_281}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_32 = {io_out_s_hi_hi_21, io_out_s_hi_lo_3}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_287 = {io_out_s_hi_32, io_out_s_lo_26}; // @[RVC.scala:44:17] wire [7:0] _io_out_s_T_288 = _io_out_s_T_287[19:12]; // @[RVC.scala:44:17, :94:58] wire [12:0] io_out_s_lo_hi_9 = {_io_out_s_T_288, 5'h0}; // @[RVC.scala:94:{21,58}] wire [19:0] io_out_s_lo_27 = {io_out_s_lo_hi_9, 7'h6F}; // @[RVC.scala:94:21] wire [10:0] io_out_s_hi_hi_22 = {_io_out_s_T_255, _io_out_s_T_266}; // @[RVC.scala:94:{21,26,36}] wire [11:0] io_out_s_hi_33 = {io_out_s_hi_hi_22, _io_out_s_T_277}; // @[RVC.scala:94:{21,48}] wire [31:0] _io_out_s_T_289 = {io_out_s_hi_33, io_out_s_lo_27}; // @[RVC.scala:94:21] wire [31:0] io_out_s_13_bits = _io_out_s_T_289; // @[RVC.scala:21:19, :94:21] wire [4:0] _io_out_s_T_291 = {2'h1, _io_out_s_T_290}; // @[package.scala:39:86] wire [4:0] io_out_s_13_rs1 = _io_out_s_T_291; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_293 = {2'h1, _io_out_s_T_292}; // @[package.scala:39:86] wire [4:0] io_out_s_13_rs2 = _io_out_s_T_293; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_13_rs3 = _io_out_s_T_294; // @[RVC.scala:20:101, :21:19] wire [4:0] _io_out_s_T_296 = {5{_io_out_s_T_295}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_10 = {_io_out_s_T_299, _io_out_s_T_300}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_28 = {io_out_s_lo_hi_10, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_23 = {_io_out_s_T_296, _io_out_s_T_297}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_34 = {io_out_s_hi_hi_23, _io_out_s_T_298}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_301 = {io_out_s_hi_34, io_out_s_lo_28}; // @[RVC.scala:45:17] wire _io_out_s_T_302 = _io_out_s_T_301[12]; // @[RVC.scala:45:17, :95:29] wire [4:0] _io_out_s_T_304 = {5{_io_out_s_T_303}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_11 = {_io_out_s_T_307, _io_out_s_T_308}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_29 = {io_out_s_lo_hi_11, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_24 = {_io_out_s_T_304, _io_out_s_T_305}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_35 = {io_out_s_hi_hi_24, _io_out_s_T_306}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_309 = {io_out_s_hi_35, io_out_s_lo_29}; // @[RVC.scala:45:17] wire [5:0] _io_out_s_T_310 = _io_out_s_T_309[10:5]; // @[RVC.scala:45:17, :95:39] wire [4:0] _io_out_s_T_312 = {2'h1, _io_out_s_T_311}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_314 = {5{_io_out_s_T_313}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_12 = {_io_out_s_T_317, _io_out_s_T_318}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_30 = {io_out_s_lo_hi_12, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_25 = {_io_out_s_T_314, _io_out_s_T_315}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_36 = {io_out_s_hi_hi_25, _io_out_s_T_316}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_319 = {io_out_s_hi_36, io_out_s_lo_30}; // @[RVC.scala:45:17] wire [3:0] _io_out_s_T_320 = _io_out_s_T_319[4:1]; // @[RVC.scala:45:17, :95:71] wire [4:0] _io_out_s_T_322 = {5{_io_out_s_T_321}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_13 = {_io_out_s_T_325, _io_out_s_T_326}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_31 = {io_out_s_lo_hi_13, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_26 = {_io_out_s_T_322, _io_out_s_T_323}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_37 = {io_out_s_hi_hi_26, _io_out_s_T_324}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_327 = {io_out_s_hi_37, io_out_s_lo_31}; // @[RVC.scala:45:17] wire _io_out_s_T_328 = _io_out_s_T_327[11]; // @[RVC.scala:45:17, :95:82] wire [7:0] io_out_s_lo_lo_4 = {_io_out_s_T_328, 7'h63}; // @[RVC.scala:95:{24,82}] wire [6:0] io_out_s_lo_hi_14 = {3'h0, _io_out_s_T_320}; // @[RVC.scala:95:{24,71}] wire [14:0] io_out_s_lo_32 = {io_out_s_lo_hi_14, io_out_s_lo_lo_4}; // @[RVC.scala:95:24] wire [9:0] io_out_s_hi_lo_4 = {5'h0, _io_out_s_T_312}; // @[RVC.scala:30:17, :95:24] wire [6:0] io_out_s_hi_hi_27 = {_io_out_s_T_302, _io_out_s_T_310}; // @[RVC.scala:95:{24,29,39}] wire [16:0] io_out_s_hi_38 = {io_out_s_hi_hi_27, io_out_s_hi_lo_4}; // @[RVC.scala:95:24] wire [31:0] _io_out_s_T_329 = {io_out_s_hi_38, io_out_s_lo_32}; // @[RVC.scala:95:24] wire [31:0] io_out_s_14_bits = _io_out_s_T_329; // @[RVC.scala:21:19, :95:24] wire [4:0] _io_out_s_T_331 = {2'h1, _io_out_s_T_330}; // @[package.scala:39:86] wire [4:0] io_out_s_14_rd = _io_out_s_T_331; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_333 = {2'h1, _io_out_s_T_332}; // @[package.scala:39:86] wire [4:0] io_out_s_14_rs1 = _io_out_s_T_333; // @[RVC.scala:21:19, :30:17] wire [4:0] io_out_s_14_rs3 = _io_out_s_T_334; // @[RVC.scala:20:101, :21:19] wire [4:0] _io_out_s_T_336 = {5{_io_out_s_T_335}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_15 = {_io_out_s_T_339, _io_out_s_T_340}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_33 = {io_out_s_lo_hi_15, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_28 = {_io_out_s_T_336, _io_out_s_T_337}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_39 = {io_out_s_hi_hi_28, _io_out_s_T_338}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_341 = {io_out_s_hi_39, io_out_s_lo_33}; // @[RVC.scala:45:17] wire _io_out_s_T_342 = _io_out_s_T_341[12]; // @[RVC.scala:45:17, :96:29] wire [4:0] _io_out_s_T_344 = {5{_io_out_s_T_343}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_16 = {_io_out_s_T_347, _io_out_s_T_348}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_34 = {io_out_s_lo_hi_16, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_29 = {_io_out_s_T_344, _io_out_s_T_345}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_40 = {io_out_s_hi_hi_29, _io_out_s_T_346}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_349 = {io_out_s_hi_40, io_out_s_lo_34}; // @[RVC.scala:45:17] wire [5:0] _io_out_s_T_350 = _io_out_s_T_349[10:5]; // @[RVC.scala:45:17, :96:39] wire [4:0] _io_out_s_T_352 = {2'h1, _io_out_s_T_351}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_354 = {5{_io_out_s_T_353}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_17 = {_io_out_s_T_357, _io_out_s_T_358}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_35 = {io_out_s_lo_hi_17, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_30 = {_io_out_s_T_354, _io_out_s_T_355}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_41 = {io_out_s_hi_hi_30, _io_out_s_T_356}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_359 = {io_out_s_hi_41, io_out_s_lo_35}; // @[RVC.scala:45:17] wire [3:0] _io_out_s_T_360 = _io_out_s_T_359[4:1]; // @[RVC.scala:45:17, :96:71] wire [4:0] _io_out_s_T_362 = {5{_io_out_s_T_361}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_18 = {_io_out_s_T_365, _io_out_s_T_366}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_36 = {io_out_s_lo_hi_18, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_31 = {_io_out_s_T_362, _io_out_s_T_363}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_42 = {io_out_s_hi_hi_31, _io_out_s_T_364}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_367 = {io_out_s_hi_42, io_out_s_lo_36}; // @[RVC.scala:45:17] wire _io_out_s_T_368 = _io_out_s_T_367[11]; // @[RVC.scala:45:17, :96:82] wire [7:0] io_out_s_lo_lo_5 = {_io_out_s_T_368, 7'h63}; // @[RVC.scala:96:{24,82}] wire [6:0] io_out_s_lo_hi_19 = {3'h1, _io_out_s_T_360}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_37 = {io_out_s_lo_hi_19, io_out_s_lo_lo_5}; // @[RVC.scala:96:24] wire [9:0] io_out_s_hi_lo_5 = {5'h0, _io_out_s_T_352}; // @[RVC.scala:30:17, :96:24] wire [6:0] io_out_s_hi_hi_32 = {_io_out_s_T_342, _io_out_s_T_350}; // @[RVC.scala:96:{24,29,39}] wire [16:0] io_out_s_hi_43 = {io_out_s_hi_hi_32, io_out_s_hi_lo_5}; // @[RVC.scala:96:24] wire [31:0] _io_out_s_T_369 = {io_out_s_hi_43, io_out_s_lo_37}; // @[RVC.scala:96:24] wire [31:0] io_out_s_15_bits = _io_out_s_T_369; // @[RVC.scala:21:19, :96:24] wire [4:0] _io_out_s_T_371 = {2'h1, _io_out_s_T_370}; // @[package.scala:39:86] wire [4:0] io_out_s_15_rs1 = _io_out_s_T_371; // @[RVC.scala:21:19, :30:17] wire [4:0] io_out_s_15_rs3 = _io_out_s_T_372; // @[RVC.scala:20:101, :21:19] wire _io_out_s_load_opc_T_1 = |_io_out_s_load_opc_T; // @[RVC.scala:33:13, :113:27] wire [6:0] io_out_s_load_opc = _io_out_s_load_opc_T_1 ? 7'h3 : 7'h1F; // @[RVC.scala:113:{23,27}] wire [5:0] _io_out_s_T_375 = {_io_out_s_T_373, _io_out_s_T_374}; // @[RVC.scala:46:{18,20,27}] wire [11:0] io_out_s_lo_38 = {_io_out_s_T_377, 7'h13}; // @[RVC.scala:33:13, :114:24] wire [10:0] io_out_s_hi_hi_33 = {_io_out_s_T_375, _io_out_s_T_376}; // @[RVC.scala:33:13, :46:18, :114:24] wire [13:0] io_out_s_hi_44 = {io_out_s_hi_hi_33, 3'h1}; // @[package.scala:39:86] wire [25:0] _io_out_s_T_378 = {io_out_s_hi_44, io_out_s_lo_38}; // @[RVC.scala:114:24] wire [4:0] io_out_s_16_rd = _io_out_s_T_379; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_16_rs1 = _io_out_s_T_380; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_16_rs2 = _io_out_s_T_381; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_16_rs3 = _io_out_s_T_382; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_16_bits; // @[RVC.scala:21:19] assign io_out_s_16_bits = {6'h0, _io_out_s_T_378}; // @[RVC.scala:21:19, :22:14, :105:43, :114:24] wire [4:0] io_out_s_lo_39 = {_io_out_s_T_385, 3'h0}; // @[RVC.scala:38:{20,37}] wire [3:0] io_out_s_hi_45 = {_io_out_s_T_383, _io_out_s_T_384}; // @[RVC.scala:38:{20,22,30}] wire [8:0] _io_out_s_T_386 = {io_out_s_hi_45, io_out_s_lo_39}; // @[RVC.scala:38:20] wire [11:0] io_out_s_lo_40 = {_io_out_s_T_387, 7'h7}; // @[RVC.scala:33:13, :117:25] wire [13:0] io_out_s_hi_hi_34 = {_io_out_s_T_386, 5'h2}; // @[package.scala:39:86] wire [16:0] io_out_s_hi_46 = {io_out_s_hi_hi_34, 3'h3}; // @[RVC.scala:117:25] wire [28:0] _io_out_s_T_388 = {io_out_s_hi_46, io_out_s_lo_40}; // @[RVC.scala:117:25] wire [4:0] io_out_s_17_rd = _io_out_s_T_389; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_17_rs2 = _io_out_s_T_390; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_17_rs3 = _io_out_s_T_391; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_17_bits; // @[RVC.scala:21:19] assign io_out_s_17_bits = {3'h0, _io_out_s_T_388}; // @[RVC.scala:21:19, :22:14, :117:25] wire [1:0] _io_out_s_T_392 = io_in_0[3:2]; // @[RVC.scala:37:22, :190:7] wire [2:0] _io_out_s_T_394 = io_in_0[6:4]; // @[RVC.scala:37:37, :190:7] wire [4:0] io_out_s_lo_41 = {_io_out_s_T_394, 2'h0}; // @[RVC.scala:37:{20,37}] wire [2:0] io_out_s_hi_47 = {_io_out_s_T_392, _io_out_s_T_393}; // @[RVC.scala:37:{20,22,30}] wire [7:0] _io_out_s_T_395 = {io_out_s_hi_47, io_out_s_lo_41}; // @[RVC.scala:37:20] wire [11:0] io_out_s_lo_42 = {_io_out_s_T_396, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :116:24] wire [12:0] io_out_s_hi_hi_35 = {_io_out_s_T_395, 5'h2}; // @[package.scala:39:86] wire [15:0] io_out_s_hi_48 = {io_out_s_hi_hi_35, 3'h2}; // @[package.scala:39:86] wire [27:0] _io_out_s_T_397 = {io_out_s_hi_48, io_out_s_lo_42}; // @[RVC.scala:116:24] wire [4:0] io_out_s_18_rd = _io_out_s_T_398; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_18_rs2 = _io_out_s_T_399; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_18_rs3 = _io_out_s_T_400; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_18_bits; // @[RVC.scala:21:19] assign io_out_s_18_bits = {4'h0, _io_out_s_T_397}; // @[RVC.scala:21:19, :22:14, :116:24] wire [4:0] io_out_s_lo_43 = {_io_out_s_T_403, 3'h0}; // @[RVC.scala:38:{20,37}] wire [3:0] io_out_s_hi_49 = {_io_out_s_T_401, _io_out_s_T_402}; // @[RVC.scala:38:{20,22,30}] wire [8:0] _io_out_s_T_404 = {io_out_s_hi_49, io_out_s_lo_43}; // @[RVC.scala:38:20] wire [11:0] io_out_s_lo_44 = {_io_out_s_T_405, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :115:24] wire [13:0] io_out_s_hi_hi_36 = {_io_out_s_T_404, 5'h2}; // @[package.scala:39:86] wire [16:0] io_out_s_hi_50 = {io_out_s_hi_hi_36, 3'h3}; // @[RVC.scala:115:24] wire [28:0] _io_out_s_T_406 = {io_out_s_hi_50, io_out_s_lo_44}; // @[RVC.scala:115:24] wire [4:0] io_out_s_19_rd = _io_out_s_T_407; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_19_rs2 = _io_out_s_T_408; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_19_rs3 = _io_out_s_T_409; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_19_bits; // @[RVC.scala:21:19] assign io_out_s_19_bits = {3'h0, _io_out_s_T_406}; // @[RVC.scala:21:19, :22:14, :115:24] wire [11:0] io_out_s_mv_lo = {_io_out_s_mv_T_1, 7'h33}; // @[RVC.scala:33:13, :132:22] wire [9:0] io_out_s_mv_hi_hi = {_io_out_s_mv_T, 5'h0}; // @[RVC.scala:32:14, :132:22] wire [12:0] io_out_s_mv_hi = {io_out_s_mv_hi_hi, 3'h0}; // @[RVC.scala:132:22] wire [24:0] _io_out_s_mv_T_2 = {io_out_s_mv_hi, io_out_s_mv_lo}; // @[RVC.scala:132:22] wire [4:0] io_out_s_mv_rd = _io_out_s_mv_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_mv_rs2 = _io_out_s_mv_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_mv_rs3 = _io_out_s_mv_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_mv_bits; // @[RVC.scala:21:19] assign io_out_s_mv_bits = {7'h0, _io_out_s_mv_T_2}; // @[RVC.scala:21:19, :22:14, :132:22] wire [11:0] io_out_s_add_lo = {_io_out_s_add_T_2, 7'h33}; // @[RVC.scala:33:13, :134:25] wire [9:0] io_out_s_add_hi_hi = {_io_out_s_add_T, _io_out_s_add_T_1}; // @[RVC.scala:32:14, :33:13, :134:25] wire [12:0] io_out_s_add_hi = {io_out_s_add_hi_hi, 3'h0}; // @[RVC.scala:134:25] wire [24:0] _io_out_s_add_T_3 = {io_out_s_add_hi, io_out_s_add_lo}; // @[RVC.scala:134:25] wire [4:0] io_out_s_add_rd = _io_out_s_add_T_4; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_add_rs1 = _io_out_s_add_T_5; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_add_rs2 = _io_out_s_add_T_6; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_add_rs3 = _io_out_s_add_T_7; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_add_bits; // @[RVC.scala:21:19] assign io_out_s_add_bits = {7'h0, _io_out_s_add_T_3}; // @[RVC.scala:21:19, :22:14, :134:25] wire [9:0] io_out_s_jr_hi_hi = {_io_out_s_jr_T, _io_out_s_jr_T_1}; // @[RVC.scala:32:14, :33:13, :135:19] wire [12:0] io_out_s_jr_hi = {io_out_s_jr_hi_hi, 3'h0}; // @[RVC.scala:135:19] wire [24:0] io_out_s_jr = {io_out_s_jr_hi, 12'h67}; // @[RVC.scala:135:19] wire [17:0] _io_out_s_reserved_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29] wire [17:0] _io_out_s_ebreak_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29, :140:27] wire [24:0] io_out_s_reserved = {_io_out_s_reserved_T, 7'h1F}; // @[RVC.scala:136:{25,29}] wire _io_out_s_jr_reserved_T_1 = |_io_out_s_jr_reserved_T; // @[RVC.scala:33:13, :137:37] wire [24:0] _io_out_s_jr_reserved_T_2 = _io_out_s_jr_reserved_T_1 ? io_out_s_jr : io_out_s_reserved; // @[RVC.scala:135:19, :136:25, :137:{33,37}] wire [4:0] io_out_s_jr_reserved_rs1 = _io_out_s_jr_reserved_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_jr_reserved_rs2 = _io_out_s_jr_reserved_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_jr_reserved_rs3 = _io_out_s_jr_reserved_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_jr_reserved_bits; // @[RVC.scala:21:19] assign io_out_s_jr_reserved_bits = {7'h0, _io_out_s_jr_reserved_T_2}; // @[RVC.scala:21:19, :22:14, :137:33] wire _io_out_s_jr_mv_T_1 = |_io_out_s_jr_mv_T; // @[RVC.scala:32:14, :138:27] wire [31:0] io_out_s_jr_mv_bits = _io_out_s_jr_mv_T_1 ? io_out_s_mv_bits : io_out_s_jr_reserved_bits; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rd = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rd : 5'h0; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs1 = _io_out_s_jr_mv_T_1 ? 5'h0 : io_out_s_jr_reserved_rs1; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs2 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs2 : io_out_s_jr_reserved_rs2; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs3 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs3 : io_out_s_jr_reserved_rs3; // @[RVC.scala:21:19, :138:{22,27}] wire [9:0] io_out_s_jalr_hi_hi = {_io_out_s_jalr_T, _io_out_s_jalr_T_1}; // @[RVC.scala:32:14, :33:13, :139:21] wire [12:0] io_out_s_jalr_hi = {io_out_s_jalr_hi_hi, 3'h0}; // @[RVC.scala:139:21] wire [24:0] io_out_s_jalr = {io_out_s_jalr_hi, 12'hE7}; // @[RVC.scala:139:21] wire [24:0] _io_out_s_ebreak_T_1 = {_io_out_s_ebreak_T, 7'h73}; // @[RVC.scala:140:{23,27}] wire [24:0] io_out_s_ebreak = {_io_out_s_ebreak_T_1[24:21], _io_out_s_ebreak_T_1[20:0] | 21'h100000}; // @[RVC.scala:140:{23,46}] wire _io_out_s_jalr_ebreak_T_1 = |_io_out_s_jalr_ebreak_T; // @[RVC.scala:33:13, :141:37] wire [24:0] _io_out_s_jalr_ebreak_T_2 = _io_out_s_jalr_ebreak_T_1 ? io_out_s_jalr : io_out_s_ebreak; // @[RVC.scala:139:21, :140:46, :141:{33,37}] wire [4:0] io_out_s_jalr_ebreak_rs1 = _io_out_s_jalr_ebreak_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_jalr_ebreak_rs2 = _io_out_s_jalr_ebreak_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_jalr_ebreak_rs3 = _io_out_s_jalr_ebreak_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19] assign io_out_s_jalr_ebreak_bits = {7'h0, _io_out_s_jalr_ebreak_T_2}; // @[RVC.scala:21:19, :22:14, :141:33] wire _io_out_s_jalr_add_T_1 = |_io_out_s_jalr_add_T; // @[RVC.scala:32:14, :142:30] wire [31:0] io_out_s_jalr_add_bits = _io_out_s_jalr_add_T_1 ? io_out_s_add_bits : io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rd = _io_out_s_jalr_add_T_1 ? io_out_s_add_rd : 5'h1; // @[package.scala:39:86] wire [4:0] io_out_s_jalr_add_rs1 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs1 : io_out_s_jalr_ebreak_rs1; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rs2 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs2 : io_out_s_jalr_ebreak_rs2; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rs3 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs3 : io_out_s_jalr_ebreak_rs3; // @[RVC.scala:21:19, :142:{25,30}] wire [31:0] io_out_s_20_bits = _io_out_s_T_410 ? io_out_s_jalr_add_bits : io_out_s_jr_mv_bits; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rd = _io_out_s_T_410 ? io_out_s_jalr_add_rd : io_out_s_jr_mv_rd; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs1 = _io_out_s_T_410 ? io_out_s_jalr_add_rs1 : io_out_s_jr_mv_rs1; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs2 = _io_out_s_T_410 ? io_out_s_jalr_add_rs2 : io_out_s_jr_mv_rs2; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs3 = _io_out_s_T_410 ? io_out_s_jalr_add_rs3 : io_out_s_jr_mv_rs3; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [5:0] io_out_s_hi_51 = {_io_out_s_T_411, _io_out_s_T_412}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_413 = {io_out_s_hi_51, 3'h0}; // @[RVC.scala:40:20] wire [3:0] _io_out_s_T_414 = _io_out_s_T_413[8:5]; // @[RVC.scala:40:20, :124:34] wire [5:0] io_out_s_hi_52 = {_io_out_s_T_416, _io_out_s_T_417}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_418 = {io_out_s_hi_52, 3'h0}; // @[RVC.scala:40:20] wire [4:0] _io_out_s_T_419 = _io_out_s_T_418[4:0]; // @[RVC.scala:40:20, :124:66] wire [7:0] io_out_s_lo_hi_20 = {3'h3, _io_out_s_T_419}; // @[RVC.scala:124:{25,66}] wire [14:0] io_out_s_lo_45 = {io_out_s_lo_hi_20, 7'h27}; // @[RVC.scala:124:25] wire [8:0] io_out_s_hi_hi_37 = {_io_out_s_T_414, _io_out_s_T_415}; // @[RVC.scala:32:14, :124:{25,34}] wire [13:0] io_out_s_hi_53 = {io_out_s_hi_hi_37, 5'h2}; // @[package.scala:39:86] wire [28:0] _io_out_s_T_420 = {io_out_s_hi_53, io_out_s_lo_45}; // @[RVC.scala:124:25] wire [4:0] io_out_s_21_rd = _io_out_s_T_421; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_21_rs2 = _io_out_s_T_422; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_21_rs3 = _io_out_s_T_423; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_21_bits; // @[RVC.scala:21:19] assign io_out_s_21_bits = {3'h0, _io_out_s_T_420}; // @[RVC.scala:21:19, :22:14, :124:25] wire [1:0] _io_out_s_T_424 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7] wire [1:0] _io_out_s_T_429 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7] wire [3:0] _io_out_s_T_425 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7] wire [3:0] _io_out_s_T_430 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7] wire [5:0] io_out_s_hi_54 = {_io_out_s_T_424, _io_out_s_T_425}; // @[RVC.scala:39:{20,22,30}] wire [7:0] _io_out_s_T_426 = {io_out_s_hi_54, 2'h0}; // @[RVC.scala:39:20] wire [2:0] _io_out_s_T_427 = _io_out_s_T_426[7:5]; // @[RVC.scala:39:20, :123:33] wire [5:0] io_out_s_hi_55 = {_io_out_s_T_429, _io_out_s_T_430}; // @[RVC.scala:39:{20,22,30}] wire [7:0] _io_out_s_T_431 = {io_out_s_hi_55, 2'h0}; // @[RVC.scala:39:20] wire [4:0] _io_out_s_T_432 = _io_out_s_T_431[4:0]; // @[RVC.scala:39:20, :123:65] wire [7:0] io_out_s_lo_hi_21 = {3'h2, _io_out_s_T_432}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_46 = {io_out_s_lo_hi_21, 7'h23}; // @[RVC.scala:123:24] wire [7:0] io_out_s_hi_hi_38 = {_io_out_s_T_427, _io_out_s_T_428}; // @[RVC.scala:32:14, :123:{24,33}] wire [12:0] io_out_s_hi_56 = {io_out_s_hi_hi_38, 5'h2}; // @[package.scala:39:86] wire [27:0] _io_out_s_T_433 = {io_out_s_hi_56, io_out_s_lo_46}; // @[RVC.scala:123:24] wire [4:0] io_out_s_22_rd = _io_out_s_T_434; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_22_rs2 = _io_out_s_T_435; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_22_rs3 = _io_out_s_T_436; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_22_bits; // @[RVC.scala:21:19] assign io_out_s_22_bits = {4'h0, _io_out_s_T_433}; // @[RVC.scala:21:19, :22:14, :123:24] wire [5:0] io_out_s_hi_57 = {_io_out_s_T_437, _io_out_s_T_438}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_439 = {io_out_s_hi_57, 3'h0}; // @[RVC.scala:40:20] wire [3:0] _io_out_s_T_440 = _io_out_s_T_439[8:5]; // @[RVC.scala:40:20, :122:33] wire [5:0] io_out_s_hi_58 = {_io_out_s_T_442, _io_out_s_T_443}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_444 = {io_out_s_hi_58, 3'h0}; // @[RVC.scala:40:20] wire [4:0] _io_out_s_T_445 = _io_out_s_T_444[4:0]; // @[RVC.scala:40:20, :122:65] wire [7:0] io_out_s_lo_hi_22 = {3'h3, _io_out_s_T_445}; // @[RVC.scala:122:{24,65}] wire [14:0] io_out_s_lo_47 = {io_out_s_lo_hi_22, 7'h23}; // @[RVC.scala:122:24] wire [8:0] io_out_s_hi_hi_39 = {_io_out_s_T_440, _io_out_s_T_441}; // @[RVC.scala:32:14, :122:{24,33}] wire [13:0] io_out_s_hi_59 = {io_out_s_hi_hi_39, 5'h2}; // @[package.scala:39:86] wire [28:0] _io_out_s_T_446 = {io_out_s_hi_59, io_out_s_lo_47}; // @[RVC.scala:122:24] wire [4:0] io_out_s_23_rd = _io_out_s_T_447; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_23_rs2 = _io_out_s_T_448; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_23_rs3 = _io_out_s_T_449; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_23_bits; // @[RVC.scala:21:19] assign io_out_s_23_bits = {3'h0, _io_out_s_T_446}; // @[RVC.scala:21:19, :22:14, :122:24] wire [4:0] io_out_s_24_rd = _io_out_s_T_450; // @[RVC.scala:20:36, :21:19] wire [4:0] _io_out_s_T_451 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_455 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_459 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_463 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_467 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_471 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_475 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_479 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] io_out_s_24_rs1 = _io_out_s_T_451; // @[RVC.scala:20:57, :21:19] wire [4:0] _io_out_s_T_452 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_456 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_460 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_464 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_468 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_472 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_476 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_480 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] io_out_s_24_rs2 = _io_out_s_T_452; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_24_rs3 = _io_out_s_T_453; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_25_rd = _io_out_s_T_454; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_25_rs1 = _io_out_s_T_455; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_25_rs2 = _io_out_s_T_456; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_25_rs3 = _io_out_s_T_457; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_26_rd = _io_out_s_T_458; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_26_rs1 = _io_out_s_T_459; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_26_rs2 = _io_out_s_T_460; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_26_rs3 = _io_out_s_T_461; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_27_rd = _io_out_s_T_462; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_27_rs1 = _io_out_s_T_463; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_27_rs2 = _io_out_s_T_464; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_27_rs3 = _io_out_s_T_465; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_28_rd = _io_out_s_T_466; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_28_rs1 = _io_out_s_T_467; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_28_rs2 = _io_out_s_T_468; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_28_rs3 = _io_out_s_T_469; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_29_rd = _io_out_s_T_470; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_29_rs1 = _io_out_s_T_471; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_29_rs2 = _io_out_s_T_472; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_29_rs3 = _io_out_s_T_473; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_30_rd = _io_out_s_T_474; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_30_rs1 = _io_out_s_T_475; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_30_rs2 = _io_out_s_T_476; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_30_rs3 = _io_out_s_T_477; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_31_rd = _io_out_s_T_478; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_31_rs1 = _io_out_s_T_479; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_31_rs2 = _io_out_s_T_480; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_31_rs3 = _io_out_s_T_481; // @[RVC.scala:20:101, :21:19] wire [2:0] _io_out_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :190:7] wire [2:0] _io_ill_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :186:20, :190:7] wire [4:0] _io_out_T_2 = {_io_out_T, _io_out_T_1}; // @[RVC.scala:154:{10,12,20}] wire _io_out_T_3 = _io_out_T_2 == 5'h1; // @[package.scala:39:86] wire [31:0] _io_out_T_4_bits = _io_out_T_3 ? io_out_s_1_bits : io_out_s_0_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rd = _io_out_T_3 ? io_out_s_1_rd : io_out_s_0_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs1 = _io_out_T_3 ? io_out_s_1_rs1 : 5'h2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs2 = _io_out_T_3 ? io_out_s_1_rs2 : io_out_s_0_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs3 = _io_out_T_3 ? io_out_s_1_rs3 : io_out_s_0_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_5 = _io_out_T_2 == 5'h2; // @[package.scala:39:86] wire [31:0] _io_out_T_6_bits = _io_out_T_5 ? io_out_s_2_bits : _io_out_T_4_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rd = _io_out_T_5 ? io_out_s_2_rd : _io_out_T_4_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs1 = _io_out_T_5 ? io_out_s_2_rs1 : _io_out_T_4_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs2 = _io_out_T_5 ? io_out_s_2_rs2 : _io_out_T_4_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs3 = _io_out_T_5 ? io_out_s_2_rs3 : _io_out_T_4_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_7 = _io_out_T_2 == 5'h3; // @[package.scala:39:86] wire [31:0] _io_out_T_8_bits = _io_out_T_7 ? io_out_s_3_bits : _io_out_T_6_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rd = _io_out_T_7 ? io_out_s_3_rd : _io_out_T_6_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs1 = _io_out_T_7 ? io_out_s_3_rs1 : _io_out_T_6_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs2 = _io_out_T_7 ? io_out_s_3_rs2 : _io_out_T_6_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs3 = _io_out_T_7 ? io_out_s_3_rs3 : _io_out_T_6_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_9 = _io_out_T_2 == 5'h4; // @[package.scala:39:86] wire [31:0] _io_out_T_10_bits = _io_out_T_9 ? io_out_s_4_bits : _io_out_T_8_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rd = _io_out_T_9 ? io_out_s_4_rd : _io_out_T_8_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs1 = _io_out_T_9 ? io_out_s_4_rs1 : _io_out_T_8_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs2 = _io_out_T_9 ? io_out_s_4_rs2 : _io_out_T_8_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs3 = _io_out_T_9 ? io_out_s_4_rs3 : _io_out_T_8_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_11 = _io_out_T_2 == 5'h5; // @[package.scala:39:86] wire [31:0] _io_out_T_12_bits = _io_out_T_11 ? io_out_s_5_bits : _io_out_T_10_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rd = _io_out_T_11 ? io_out_s_5_rd : _io_out_T_10_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs1 = _io_out_T_11 ? io_out_s_5_rs1 : _io_out_T_10_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs2 = _io_out_T_11 ? io_out_s_5_rs2 : _io_out_T_10_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs3 = _io_out_T_11 ? io_out_s_5_rs3 : _io_out_T_10_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_13 = _io_out_T_2 == 5'h6; // @[package.scala:39:86] wire [31:0] _io_out_T_14_bits = _io_out_T_13 ? io_out_s_6_bits : _io_out_T_12_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rd = _io_out_T_13 ? io_out_s_6_rd : _io_out_T_12_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs1 = _io_out_T_13 ? io_out_s_6_rs1 : _io_out_T_12_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs2 = _io_out_T_13 ? io_out_s_6_rs2 : _io_out_T_12_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs3 = _io_out_T_13 ? io_out_s_6_rs3 : _io_out_T_12_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_15 = _io_out_T_2 == 5'h7; // @[package.scala:39:86] wire [31:0] _io_out_T_16_bits = _io_out_T_15 ? io_out_s_7_bits : _io_out_T_14_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rd = _io_out_T_15 ? io_out_s_7_rd : _io_out_T_14_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs1 = _io_out_T_15 ? io_out_s_7_rs1 : _io_out_T_14_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs2 = _io_out_T_15 ? io_out_s_7_rs2 : _io_out_T_14_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs3 = _io_out_T_15 ? io_out_s_7_rs3 : _io_out_T_14_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_17 = _io_out_T_2 == 5'h8; // @[package.scala:39:86] wire [31:0] _io_out_T_18_bits = _io_out_T_17 ? io_out_s_8_bits : _io_out_T_16_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rd = _io_out_T_17 ? io_out_s_8_rd : _io_out_T_16_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs1 = _io_out_T_17 ? io_out_s_8_rs1 : _io_out_T_16_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs2 = _io_out_T_17 ? io_out_s_8_rs2 : _io_out_T_16_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs3 = _io_out_T_17 ? io_out_s_8_rs3 : _io_out_T_16_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_19 = _io_out_T_2 == 5'h9; // @[package.scala:39:86] wire [31:0] _io_out_T_20_bits = _io_out_T_19 ? io_out_s_9_bits : _io_out_T_18_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rd = _io_out_T_19 ? io_out_s_9_rd : _io_out_T_18_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs1 = _io_out_T_19 ? io_out_s_9_rs1 : _io_out_T_18_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs2 = _io_out_T_19 ? io_out_s_9_rs2 : _io_out_T_18_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs3 = _io_out_T_19 ? io_out_s_9_rs3 : _io_out_T_18_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_21 = _io_out_T_2 == 5'hA; // @[package.scala:39:86] wire [31:0] _io_out_T_22_bits = _io_out_T_21 ? io_out_s_10_bits : _io_out_T_20_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rd = _io_out_T_21 ? io_out_s_10_rd : _io_out_T_20_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs1 = _io_out_T_21 ? 5'h0 : _io_out_T_20_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs2 = _io_out_T_21 ? io_out_s_10_rs2 : _io_out_T_20_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs3 = _io_out_T_21 ? io_out_s_10_rs3 : _io_out_T_20_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_23 = _io_out_T_2 == 5'hB; // @[package.scala:39:86] wire [31:0] _io_out_T_24_bits = _io_out_T_23 ? io_out_s_11_bits : _io_out_T_22_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rd = _io_out_T_23 ? io_out_s_11_rd : _io_out_T_22_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs1 = _io_out_T_23 ? io_out_s_11_rs1 : _io_out_T_22_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs2 = _io_out_T_23 ? io_out_s_11_rs2 : _io_out_T_22_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs3 = _io_out_T_23 ? io_out_s_11_rs3 : _io_out_T_22_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_25 = _io_out_T_2 == 5'hC; // @[package.scala:39:86] wire [31:0] _io_out_T_26_bits = _io_out_T_25 ? io_out_s_12_bits : _io_out_T_24_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rd = _io_out_T_25 ? io_out_s_12_rd : _io_out_T_24_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs1 = _io_out_T_25 ? io_out_s_12_rs1 : _io_out_T_24_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs2 = _io_out_T_25 ? io_out_s_12_rs2 : _io_out_T_24_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs3 = _io_out_T_25 ? io_out_s_12_rs3 : _io_out_T_24_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_27 = _io_out_T_2 == 5'hD; // @[package.scala:39:86] wire [31:0] _io_out_T_28_bits = _io_out_T_27 ? io_out_s_13_bits : _io_out_T_26_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rd = _io_out_T_27 ? 5'h0 : _io_out_T_26_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs1 = _io_out_T_27 ? io_out_s_13_rs1 : _io_out_T_26_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs2 = _io_out_T_27 ? io_out_s_13_rs2 : _io_out_T_26_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs3 = _io_out_T_27 ? io_out_s_13_rs3 : _io_out_T_26_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_29 = _io_out_T_2 == 5'hE; // @[package.scala:39:86] wire [31:0] _io_out_T_30_bits = _io_out_T_29 ? io_out_s_14_bits : _io_out_T_28_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rd = _io_out_T_29 ? io_out_s_14_rd : _io_out_T_28_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs1 = _io_out_T_29 ? io_out_s_14_rs1 : _io_out_T_28_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs2 = _io_out_T_29 ? 5'h0 : _io_out_T_28_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs3 = _io_out_T_29 ? io_out_s_14_rs3 : _io_out_T_28_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_31 = _io_out_T_2 == 5'hF; // @[package.scala:39:86] wire [31:0] _io_out_T_32_bits = _io_out_T_31 ? io_out_s_15_bits : _io_out_T_30_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rd = _io_out_T_31 ? 5'h0 : _io_out_T_30_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs1 = _io_out_T_31 ? io_out_s_15_rs1 : _io_out_T_30_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs2 = _io_out_T_31 ? 5'h0 : _io_out_T_30_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs3 = _io_out_T_31 ? io_out_s_15_rs3 : _io_out_T_30_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_33 = _io_out_T_2 == 5'h10; // @[package.scala:39:86] wire [31:0] _io_out_T_34_bits = _io_out_T_33 ? io_out_s_16_bits : _io_out_T_32_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rd = _io_out_T_33 ? io_out_s_16_rd : _io_out_T_32_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs1 = _io_out_T_33 ? io_out_s_16_rs1 : _io_out_T_32_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs2 = _io_out_T_33 ? io_out_s_16_rs2 : _io_out_T_32_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs3 = _io_out_T_33 ? io_out_s_16_rs3 : _io_out_T_32_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_35 = _io_out_T_2 == 5'h11; // @[package.scala:39:86] wire [31:0] _io_out_T_36_bits = _io_out_T_35 ? io_out_s_17_bits : _io_out_T_34_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rd = _io_out_T_35 ? io_out_s_17_rd : _io_out_T_34_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs1 = _io_out_T_35 ? 5'h2 : _io_out_T_34_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs2 = _io_out_T_35 ? io_out_s_17_rs2 : _io_out_T_34_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs3 = _io_out_T_35 ? io_out_s_17_rs3 : _io_out_T_34_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_37 = _io_out_T_2 == 5'h12; // @[package.scala:39:86] wire [31:0] _io_out_T_38_bits = _io_out_T_37 ? io_out_s_18_bits : _io_out_T_36_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rd = _io_out_T_37 ? io_out_s_18_rd : _io_out_T_36_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs1 = _io_out_T_37 ? 5'h2 : _io_out_T_36_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs2 = _io_out_T_37 ? io_out_s_18_rs2 : _io_out_T_36_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs3 = _io_out_T_37 ? io_out_s_18_rs3 : _io_out_T_36_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_39 = _io_out_T_2 == 5'h13; // @[package.scala:39:86] wire [31:0] _io_out_T_40_bits = _io_out_T_39 ? io_out_s_19_bits : _io_out_T_38_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rd = _io_out_T_39 ? io_out_s_19_rd : _io_out_T_38_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs1 = _io_out_T_39 ? 5'h2 : _io_out_T_38_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs2 = _io_out_T_39 ? io_out_s_19_rs2 : _io_out_T_38_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs3 = _io_out_T_39 ? io_out_s_19_rs3 : _io_out_T_38_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_41 = _io_out_T_2 == 5'h14; // @[package.scala:39:86] wire [31:0] _io_out_T_42_bits = _io_out_T_41 ? io_out_s_20_bits : _io_out_T_40_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rd = _io_out_T_41 ? io_out_s_20_rd : _io_out_T_40_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs1 = _io_out_T_41 ? io_out_s_20_rs1 : _io_out_T_40_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs2 = _io_out_T_41 ? io_out_s_20_rs2 : _io_out_T_40_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs3 = _io_out_T_41 ? io_out_s_20_rs3 : _io_out_T_40_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_43 = _io_out_T_2 == 5'h15; // @[package.scala:39:86] wire [31:0] _io_out_T_44_bits = _io_out_T_43 ? io_out_s_21_bits : _io_out_T_42_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rd = _io_out_T_43 ? io_out_s_21_rd : _io_out_T_42_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs1 = _io_out_T_43 ? 5'h2 : _io_out_T_42_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs2 = _io_out_T_43 ? io_out_s_21_rs2 : _io_out_T_42_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs3 = _io_out_T_43 ? io_out_s_21_rs3 : _io_out_T_42_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_45 = _io_out_T_2 == 5'h16; // @[package.scala:39:86] wire [31:0] _io_out_T_46_bits = _io_out_T_45 ? io_out_s_22_bits : _io_out_T_44_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rd = _io_out_T_45 ? io_out_s_22_rd : _io_out_T_44_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs1 = _io_out_T_45 ? 5'h2 : _io_out_T_44_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs2 = _io_out_T_45 ? io_out_s_22_rs2 : _io_out_T_44_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs3 = _io_out_T_45 ? io_out_s_22_rs3 : _io_out_T_44_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_47 = _io_out_T_2 == 5'h17; // @[package.scala:39:86] wire [31:0] _io_out_T_48_bits = _io_out_T_47 ? io_out_s_23_bits : _io_out_T_46_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rd = _io_out_T_47 ? io_out_s_23_rd : _io_out_T_46_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs1 = _io_out_T_47 ? 5'h2 : _io_out_T_46_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs2 = _io_out_T_47 ? io_out_s_23_rs2 : _io_out_T_46_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs3 = _io_out_T_47 ? io_out_s_23_rs3 : _io_out_T_46_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_49 = _io_out_T_2 == 5'h18; // @[package.scala:39:86] wire [31:0] _io_out_T_50_bits = _io_out_T_49 ? io_out_s_24_bits : _io_out_T_48_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rd = _io_out_T_49 ? io_out_s_24_rd : _io_out_T_48_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs1 = _io_out_T_49 ? io_out_s_24_rs1 : _io_out_T_48_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs2 = _io_out_T_49 ? io_out_s_24_rs2 : _io_out_T_48_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs3 = _io_out_T_49 ? io_out_s_24_rs3 : _io_out_T_48_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_51 = _io_out_T_2 == 5'h19; // @[package.scala:39:86] wire [31:0] _io_out_T_52_bits = _io_out_T_51 ? io_out_s_25_bits : _io_out_T_50_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rd = _io_out_T_51 ? io_out_s_25_rd : _io_out_T_50_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs1 = _io_out_T_51 ? io_out_s_25_rs1 : _io_out_T_50_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs2 = _io_out_T_51 ? io_out_s_25_rs2 : _io_out_T_50_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs3 = _io_out_T_51 ? io_out_s_25_rs3 : _io_out_T_50_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_53 = _io_out_T_2 == 5'h1A; // @[package.scala:39:86] wire [31:0] _io_out_T_54_bits = _io_out_T_53 ? io_out_s_26_bits : _io_out_T_52_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rd = _io_out_T_53 ? io_out_s_26_rd : _io_out_T_52_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs1 = _io_out_T_53 ? io_out_s_26_rs1 : _io_out_T_52_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs2 = _io_out_T_53 ? io_out_s_26_rs2 : _io_out_T_52_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs3 = _io_out_T_53 ? io_out_s_26_rs3 : _io_out_T_52_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_55 = _io_out_T_2 == 5'h1B; // @[package.scala:39:86] wire [31:0] _io_out_T_56_bits = _io_out_T_55 ? io_out_s_27_bits : _io_out_T_54_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rd = _io_out_T_55 ? io_out_s_27_rd : _io_out_T_54_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs1 = _io_out_T_55 ? io_out_s_27_rs1 : _io_out_T_54_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs2 = _io_out_T_55 ? io_out_s_27_rs2 : _io_out_T_54_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs3 = _io_out_T_55 ? io_out_s_27_rs3 : _io_out_T_54_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_57 = _io_out_T_2 == 5'h1C; // @[package.scala:39:86] wire [31:0] _io_out_T_58_bits = _io_out_T_57 ? io_out_s_28_bits : _io_out_T_56_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rd = _io_out_T_57 ? io_out_s_28_rd : _io_out_T_56_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs1 = _io_out_T_57 ? io_out_s_28_rs1 : _io_out_T_56_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs2 = _io_out_T_57 ? io_out_s_28_rs2 : _io_out_T_56_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs3 = _io_out_T_57 ? io_out_s_28_rs3 : _io_out_T_56_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_59 = _io_out_T_2 == 5'h1D; // @[package.scala:39:86] wire [31:0] _io_out_T_60_bits = _io_out_T_59 ? io_out_s_29_bits : _io_out_T_58_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rd = _io_out_T_59 ? io_out_s_29_rd : _io_out_T_58_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs1 = _io_out_T_59 ? io_out_s_29_rs1 : _io_out_T_58_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs2 = _io_out_T_59 ? io_out_s_29_rs2 : _io_out_T_58_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs3 = _io_out_T_59 ? io_out_s_29_rs3 : _io_out_T_58_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_61 = _io_out_T_2 == 5'h1E; // @[package.scala:39:86] wire [31:0] _io_out_T_62_bits = _io_out_T_61 ? io_out_s_30_bits : _io_out_T_60_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rd = _io_out_T_61 ? io_out_s_30_rd : _io_out_T_60_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs1 = _io_out_T_61 ? io_out_s_30_rs1 : _io_out_T_60_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs2 = _io_out_T_61 ? io_out_s_30_rs2 : _io_out_T_60_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs3 = _io_out_T_61 ? io_out_s_30_rs3 : _io_out_T_60_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_63 = &_io_out_T_2; // @[package.scala:39:86] assign _io_out_T_64_bits = _io_out_T_63 ? io_out_s_31_bits : _io_out_T_62_bits; // @[package.scala:39:{76,86}] assign _io_out_T_64_rd = _io_out_T_63 ? io_out_s_31_rd : _io_out_T_62_rd; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs1 = _io_out_T_63 ? io_out_s_31_rs1 : _io_out_T_62_rs1; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs2 = _io_out_T_63 ? io_out_s_31_rs2 : _io_out_T_62_rs2; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs3 = _io_out_T_63 ? io_out_s_31_rs3 : _io_out_T_62_rs3; // @[package.scala:39:{76,86}] assign io_out_bits_0 = _io_out_T_64_bits; // @[package.scala:39:76] assign io_out_rd = _io_out_T_64_rd; // @[package.scala:39:76] assign io_out_rs1 = _io_out_T_64_rs1; // @[package.scala:39:76] assign io_out_rs2 = _io_out_T_64_rs2; // @[package.scala:39:76] assign io_out_rs3 = _io_out_T_64_rs3; // @[package.scala:39:76] wire [10:0] _io_ill_s_T = io_in_0[12:2]; // @[RVC.scala:158:19, :190:7] wire [10:0] _io_ill_s_T_13 = io_in_0[12:2]; // @[RVC.scala:158:19, :177:21, :190:7] wire _io_ill_s_T_1 = |_io_ill_s_T; // @[RVC.scala:158:{19,27}] wire io_ill_s_0 = ~_io_ill_s_T_1; // @[RVC.scala:158:{16,27}] wire io_ill_s_9 = _io_ill_s_T_2 == 5'h0; // @[RVC.scala:33:13, :167:47] wire _io_ill_s_T_5 = |_io_ill_s_T_4; // @[RVC.scala:168:{27,34}] wire _io_ill_s_T_6 = _io_ill_s_T_3 | _io_ill_s_T_5; // @[RVC.scala:168:{19,24,34}] wire io_ill_s_11 = ~_io_ill_s_T_6; // @[RVC.scala:168:{16,24}] wire _io_ill_s_T_8 = &_io_ill_s_T_7; // @[RVC.scala:169:{22,31}] wire _io_ill_s_T_10 = _io_ill_s_T_9; // @[RVC.scala:169:{69,73}] wire io_ill_s_12 = _io_ill_s_T_8 & _io_ill_s_T_10; // @[RVC.scala:169:{31,36,73}] wire io_ill_s_18 = _io_ill_s_T_11 == 5'h0; // @[RVC.scala:33:13, :175:18] wire io_ill_s_19 = _io_ill_s_T_12 == 5'h0; // @[RVC.scala:33:13, :175:18] wire _io_ill_s_T_14 = |_io_ill_s_T_13; // @[RVC.scala:177:{21,29}] wire io_ill_s_20 = ~_io_ill_s_T_14; // @[RVC.scala:177:{18,29}] wire [4:0] _io_ill_T_2 = {_io_ill_T, _io_ill_T_1}; // @[RVC.scala:186:{10,12,20}] wire _io_ill_T_3 = _io_ill_T_2 == 5'h1; // @[package.scala:39:86] wire _io_ill_T_4 = ~_io_ill_T_3 & io_ill_s_0; // @[package.scala:39:{76,86}] wire _io_ill_T_5 = _io_ill_T_2 == 5'h2; // @[package.scala:39:86] wire _io_ill_T_6 = ~_io_ill_T_5 & _io_ill_T_4; // @[package.scala:39:{76,86}] wire _io_ill_T_7 = _io_ill_T_2 == 5'h3; // @[package.scala:39:86] wire _io_ill_T_8 = ~_io_ill_T_7 & _io_ill_T_6; // @[package.scala:39:{76,86}] wire _io_ill_T_9 = _io_ill_T_2 == 5'h4; // @[package.scala:39:86] wire _io_ill_T_10 = _io_ill_T_9 | _io_ill_T_8; // @[package.scala:39:{76,86}] wire _io_ill_T_11 = _io_ill_T_2 == 5'h5; // @[package.scala:39:86] wire _io_ill_T_12 = ~_io_ill_T_11 & _io_ill_T_10; // @[package.scala:39:{76,86}] wire _io_ill_T_13 = _io_ill_T_2 == 5'h6; // @[package.scala:39:86] wire _io_ill_T_14 = ~_io_ill_T_13 & _io_ill_T_12; // @[package.scala:39:{76,86}] wire _io_ill_T_15 = _io_ill_T_2 == 5'h7; // @[package.scala:39:86] wire _io_ill_T_16 = ~_io_ill_T_15 & _io_ill_T_14; // @[package.scala:39:{76,86}] wire _io_ill_T_17 = _io_ill_T_2 == 5'h8; // @[package.scala:39:86] wire _io_ill_T_18 = ~_io_ill_T_17 & _io_ill_T_16; // @[package.scala:39:{76,86}] wire _io_ill_T_19 = _io_ill_T_2 == 5'h9; // @[package.scala:39:86] wire _io_ill_T_20 = _io_ill_T_19 ? io_ill_s_9 : _io_ill_T_18; // @[package.scala:39:{76,86}] wire _io_ill_T_21 = _io_ill_T_2 == 5'hA; // @[package.scala:39:86] wire _io_ill_T_22 = ~_io_ill_T_21 & _io_ill_T_20; // @[package.scala:39:{76,86}] wire _io_ill_T_23 = _io_ill_T_2 == 5'hB; // @[package.scala:39:86] wire _io_ill_T_24 = _io_ill_T_23 ? io_ill_s_11 : _io_ill_T_22; // @[package.scala:39:{76,86}] wire _io_ill_T_25 = _io_ill_T_2 == 5'hC; // @[package.scala:39:86] wire _io_ill_T_26 = _io_ill_T_25 ? io_ill_s_12 : _io_ill_T_24; // @[package.scala:39:{76,86}] wire _io_ill_T_27 = _io_ill_T_2 == 5'hD; // @[package.scala:39:86] wire _io_ill_T_28 = ~_io_ill_T_27 & _io_ill_T_26; // @[package.scala:39:{76,86}] wire _io_ill_T_29 = _io_ill_T_2 == 5'hE; // @[package.scala:39:86] wire _io_ill_T_30 = ~_io_ill_T_29 & _io_ill_T_28; // @[package.scala:39:{76,86}] wire _io_ill_T_31 = _io_ill_T_2 == 5'hF; // @[package.scala:39:86] wire _io_ill_T_32 = ~_io_ill_T_31 & _io_ill_T_30; // @[package.scala:39:{76,86}] wire _io_ill_T_33 = _io_ill_T_2 == 5'h10; // @[package.scala:39:86] wire _io_ill_T_34 = ~_io_ill_T_33 & _io_ill_T_32; // @[package.scala:39:{76,86}] wire _io_ill_T_35 = _io_ill_T_2 == 5'h11; // @[package.scala:39:86] wire _io_ill_T_36 = ~_io_ill_T_35 & _io_ill_T_34; // @[package.scala:39:{76,86}] wire _io_ill_T_37 = _io_ill_T_2 == 5'h12; // @[package.scala:39:86] wire _io_ill_T_38 = _io_ill_T_37 ? io_ill_s_18 : _io_ill_T_36; // @[package.scala:39:{76,86}] wire _io_ill_T_39 = _io_ill_T_2 == 5'h13; // @[package.scala:39:86] wire _io_ill_T_40 = _io_ill_T_39 ? io_ill_s_19 : _io_ill_T_38; // @[package.scala:39:{76,86}] wire _io_ill_T_41 = _io_ill_T_2 == 5'h14; // @[package.scala:39:86] wire _io_ill_T_42 = _io_ill_T_41 ? io_ill_s_20 : _io_ill_T_40; // @[package.scala:39:{76,86}] wire _io_ill_T_43 = _io_ill_T_2 == 5'h15; // @[package.scala:39:86] wire _io_ill_T_44 = ~_io_ill_T_43 & _io_ill_T_42; // @[package.scala:39:{76,86}] wire _io_ill_T_45 = _io_ill_T_2 == 5'h16; // @[package.scala:39:86] wire _io_ill_T_46 = ~_io_ill_T_45 & _io_ill_T_44; // @[package.scala:39:{76,86}] wire _io_ill_T_47 = _io_ill_T_2 == 5'h17; // @[package.scala:39:86] wire _io_ill_T_48 = ~_io_ill_T_47 & _io_ill_T_46; // @[package.scala:39:{76,86}] wire _io_ill_T_49 = _io_ill_T_2 == 5'h18; // @[package.scala:39:86] wire _io_ill_T_50 = ~_io_ill_T_49 & _io_ill_T_48; // @[package.scala:39:{76,86}] wire _io_ill_T_51 = _io_ill_T_2 == 5'h19; // @[package.scala:39:86] wire _io_ill_T_52 = ~_io_ill_T_51 & _io_ill_T_50; // @[package.scala:39:{76,86}] wire _io_ill_T_53 = _io_ill_T_2 == 5'h1A; // @[package.scala:39:86] wire _io_ill_T_54 = ~_io_ill_T_53 & _io_ill_T_52; // @[package.scala:39:{76,86}] wire _io_ill_T_55 = _io_ill_T_2 == 5'h1B; // @[package.scala:39:86] wire _io_ill_T_56 = ~_io_ill_T_55 & _io_ill_T_54; // @[package.scala:39:{76,86}] wire _io_ill_T_57 = _io_ill_T_2 == 5'h1C; // @[package.scala:39:86] wire _io_ill_T_58 = ~_io_ill_T_57 & _io_ill_T_56; // @[package.scala:39:{76,86}] wire _io_ill_T_59 = _io_ill_T_2 == 5'h1D; // @[package.scala:39:86] wire _io_ill_T_60 = ~_io_ill_T_59 & _io_ill_T_58; // @[package.scala:39:{76,86}] wire _io_ill_T_61 = _io_ill_T_2 == 5'h1E; // @[package.scala:39:86] wire _io_ill_T_62 = ~_io_ill_T_61 & _io_ill_T_60; // @[package.scala:39:{76,86}] wire _io_ill_T_63 = &_io_ill_T_2; // @[package.scala:39:86] assign _io_ill_T_64 = ~_io_ill_T_63 & _io_ill_T_62; // @[package.scala:39:{76,86}] assign io_ill = _io_ill_T_64; // @[package.scala:39:76] assign io_out_bits = io_out_bits_0; // @[RVC.scala:190:7] assign io_rvc = io_rvc_0; // @[RVC.scala:190:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w4_d3_i0_9( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_109 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_110 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_111 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_112 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w4_d3_i0_26( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_242 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_243 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_244 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_245 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File tage.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f3_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)*l, histLength)-1, i*l) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry))) val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f3_resp(w).valid := RegNext(s2_req_rhits(w)) io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w))) io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr) } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) table.write( Mux(doing_reset, reset_idx , update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))), Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools ) val update_hi_wdata = Wire(Vec(bankWidth, Bool())) hi_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)), Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata), Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val update_lo_wdata = Wire(Vec(bankWidth, Bool())) lo_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)), Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata), Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_||_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag update_hi_wdata(w) := io.update_u(w)(1) update_lo_wdata(w) := io.update_u(w)(0) } when (io.update_mask.reduce(_||_)) { when (wrbypass_hits.reduce(_||_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048 ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(io.f0_pc) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f3_resps = VecInit(tables.map(_.io.f3_resp)) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var altpred = io.resp_in(0).f3(w).taken val final_altpred = WireInit(io.resp_in(0).f3(w).taken) var provided = false.B var provider = 0.U io.resp.f3(w).taken := io.resp_in(0).f3(w).taken for (i <- 0 until tageNTables) { val hit = f3_resps(i)(w).valid val ctr = f3_resps(i)(w).bits.ctr when (hit) { io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2)) final_altpred := altpred } provided = provided || hit provider = Mux(hit, i.U, provider) altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred) } f3_meta.provider(w).valid := provided f3_meta.provider(w).bits := provider f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }

module lo_us_20( // @[tage.scala:90:27] input [7:0] R0_addr, input R0_en, input R0_clk, output [3:0] R0_data, input [7:0] W0_addr, input W0_clk, input [3:0] W0_data, input [3:0] W0_mask ); hi_us_0_ext hi_us_0_ext ( // @[tage.scala:90:27] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (1'h1), // @[tage.scala:90:27] .W0_clk (W0_clk), .W0_data (W0_data), .W0_mask (W0_mask) ); // @[tage.scala:90:27] endmodule

Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }

module InputUnit_84( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output io_debug_va_stall, // @[InputUnit.scala:170:14] output io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [1:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_1_0; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_0_0; // @[MixedVec.scala:116:9] wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]

Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel | (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens | chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) | 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_||_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_||_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }

module SwitchArbiter_90( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_3_ready, // @[SwitchAllocator.scala:18:14] input io_in_3_valid, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [3:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [3:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [3:0] unassigned = {io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [3:0] mask; // @[SwitchAllocator.scala:27:21] wire [3:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [7:0] sel = _sel_T_1[0] ? 8'h1 : _sel_T_1[1] ? 8'h2 : _sel_T_1[2] ? 8'h4 : _sel_T_1[3] ? 8'h8 : unassigned[0] ? 8'h10 : unassigned[1] ? 8'h20 : unassigned[2] ? 8'h40 : {unassigned[3], 7'h0}; // @[OneHot.scala:85:71] wire [3:0] in_valids = {io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [3:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[3:0] | sel[7:4]; // @[Mux.scala:50:70] wire [3:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire [2:0] _GEN = chosen[2:0] | chosen[3:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [1:0] _GEN_0 = _GEN[1:0] | chosen[3:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 4'h0; // @[SwitchAllocator.scala:24:38] mask <= 4'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_3_bits_tail, io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (|_io_out_0_valid_T) ? {chosen[3], _GEN[2], _GEN_0[1], _GEN_0[0] | chosen[3]} : (&mask) ? 4'h0 : {mask[2:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}] end always @(posedge)

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncQueueSource_Phit_19( // @[AsyncQueue.scala:70:7] input clock, // @[AsyncQueue.scala:70:7] input reset, // @[AsyncQueue.scala:70:7] output io_enq_ready, // @[AsyncQueue.scala:73:14] input io_enq_valid, // @[AsyncQueue.scala:73:14] input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:73:14] input [3:0] io_async_ridx, // @[AsyncQueue.scala:73:14] output [3:0] io_async_widx, // @[AsyncQueue.scala:73:14] input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14] input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14] ); wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30] wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32] wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:70:7] wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_ridx_0 = io_async_ridx; // @[AsyncQueue.scala:70:7] wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid; // @[AsyncQueue.scala:70:7] wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n; // @[AsyncQueue.scala:70:7] wire _widx_T = reset; // @[AsyncQueue.scala:83:30] wire _ready_reg_T = reset; // @[AsyncQueue.scala:90:35] wire _widx_reg_T = reset; // @[AsyncQueue.scala:93:34] wire _source_valid_0_reset_T = reset; // @[AsyncQueue.scala:107:36] wire _source_valid_1_reset_T = reset; // @[AsyncQueue.scala:108:36] wire _sink_extend_reset_T = reset; // @[AsyncQueue.scala:109:36] wire _sink_valid_reset_T = reset; // @[AsyncQueue.scala:110:35] wire _io_async_safe_source_reset_n_T = reset; // @[AsyncQueue.scala:123:34] wire _io_enq_ready_T; // @[AsyncQueue.scala:91:29] wire _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:123:27] wire io_enq_ready_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_0_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_1_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_2_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_3_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_4_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_5_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_6_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_7_phit_0; // @[AsyncQueue.scala:70:7] wire io_async_safe_widx_valid_0; // @[AsyncQueue.scala:70:7] wire io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_widx_0; // @[AsyncQueue.scala:70:7] wire sink_ready; // @[AsyncQueue.scala:81:28] reg [31:0] mem_0_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_phit_0 = mem_0_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_1_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_phit_0 = mem_1_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_2_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_phit_0 = mem_2_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_3_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_phit_0 = mem_3_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_4_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_phit_0 = mem_4_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_5_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_phit_0 = mem_5_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_6_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_phit_0 = mem_6_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_7_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_phit_0 = mem_7_phit; // @[AsyncQueue.scala:70:7, :82:16] wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala:81:28, :83:77] wire [3:0] _widx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] widx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] widx_widx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77] assign widx_incremented = _widx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _widx_T_3 = widx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] ridx; // @[ShiftReg.scala:48:24] wire [3:0] _ready_T = ridx ^ 4'hC; // @[ShiftReg.scala:48:24] wire _ready_T_1 = widx != _ready_T; // @[AsyncQueue.scala:54:17, :85:{34,44}] wire ready = sink_ready & _ready_T_1; // @[AsyncQueue.scala:81:28, :85:{26,34}] wire [2:0] _index_T = io_async_widx_0[2:0]; // @[AsyncQueue.scala:70:7, :87:52] wire _index_T_1 = io_async_widx_0[3]; // @[AsyncQueue.scala:70:7, :87:80] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:87:{80,93}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:87:{52,64,93}] reg ready_reg; // @[AsyncQueue.scala:90:56] assign _io_enq_ready_T = ready_reg & sink_ready; // @[AsyncQueue.scala:81:28, :90:56, :91:29] assign io_enq_ready_0 = _io_enq_ready_T; // @[AsyncQueue.scala:70:7, :91:29] reg [3:0] widx_gray; // @[AsyncQueue.scala:93:55] assign io_async_widx_0 = widx_gray; // @[AsyncQueue.scala:70:7, :93:55] wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46] wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T | _source_valid_0_reset_T_1; // @[AsyncQueue.scala:107:{36,43,46}] wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2; // @[AsyncQueue.scala:107:{43,65}] wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :108:46] wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T | _source_valid_1_reset_T_1; // @[AsyncQueue.scala:108:{36,43,46}] wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2; // @[AsyncQueue.scala:108:{43,65}] wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :109:46] wire _sink_extend_reset_T_2 = _sink_extend_reset_T | _sink_extend_reset_T_1; // @[AsyncQueue.scala:109:{36,43,46}] wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2; // @[AsyncQueue.scala:109:{43,65}] assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T; // @[AsyncQueue.scala:123:{27,34}] assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:70:7, :123:27] always @(posedge clock) begin // @[AsyncQueue.scala:70:7] if (_widx_T_1 & index == 3'h0) // @[Decoupled.scala:51:35] mem_0_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h1) // @[Decoupled.scala:51:35] mem_1_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h2) // @[Decoupled.scala:51:35] mem_2_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h3) // @[Decoupled.scala:51:35] mem_3_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h4) // @[Decoupled.scala:51:35] mem_4_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h5) // @[Decoupled.scala:51:35] mem_5_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h6) // @[Decoupled.scala:51:35] mem_6_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & (&index)) // @[Decoupled.scala:51:35] mem_7_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] always @(posedge) always @(posedge clock or posedge _widx_T) begin // @[AsyncQueue.scala:70:7, :83:30] if (_widx_T) // @[AsyncQueue.scala:70:7, :83:30] widx_widx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:70:7] widx_widx_bin <= widx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _ready_reg_T) begin // @[AsyncQueue.scala:70:7, :90:35] if (_ready_reg_T) // @[AsyncQueue.scala:70:7, :90:35] ready_reg <= 1'h0; // @[AsyncQueue.scala:90:56] else // @[AsyncQueue.scala:70:7] ready_reg <= ready; // @[AsyncQueue.scala:85:26, :90:56] always @(posedge, posedge) always @(posedge clock or posedge _widx_reg_T) begin // @[AsyncQueue.scala:70:7, :93:34] if (_widx_reg_T) // @[AsyncQueue.scala:70:7, :93:34] widx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :93:55] else // @[AsyncQueue.scala:70:7] widx_gray <= widx; // @[AsyncQueue.scala:54:17, :93:55] always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_61( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_33 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_37 = source_ok_uncommonBits_5 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_38 = _source_ok_T_36 & _source_ok_T_37; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire _source_ok_T_42 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_51 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_52 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_54 = _source_ok_T_53 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_60 = _source_ok_T_59 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_66 = _source_ok_T_65 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = _source_ok_T_71 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = _source_ok_T_77 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_81 = source_ok_uncommonBits_10 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_82 = _source_ok_T_80 & _source_ok_T_81; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_83; // @[Parameters.scala:1138:31] wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_89 = source_ok_uncommonBits_11 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_90 = _source_ok_T_88 & _source_ok_T_89; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_8 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_103 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _T_1299 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1299; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1299; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1367 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1367; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1367; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1367; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1232 = _T_1299 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1232 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1232 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1232 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1232 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1232 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1278 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1278 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1247 = _T_1367 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1247 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1247 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1247 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1343 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1343 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1325 = _T_1367 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1325 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1325 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1325 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body || !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body || !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLCToNoC_7( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [7:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0; // @[package.scala:243:{46,71,76}] reg [7:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 8'h1 | tail_beats1 == 8'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 8'h0; // @[Edges.scala:229:27] tail_counter <= 8'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0) : head_counter - 8'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 8'h0 ? tail_beats1 : tail_counter - 8'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_257( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData_176( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module ClockCrossingReg_w83( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [82:0] io_d, // @[SynchronizerReg.scala:195:14] output [82:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [82:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [82:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [82:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_90( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_101 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File TSIToTileLink.scala: package testchipip.tsi import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import testchipip.serdes._ object TSI { val WIDTH = 32 // hardcoded in FESVR } class TSIIO extends SerialIO(TSI.WIDTH) object TSIIO { def apply(ser: SerialIO): TSIIO = { require(ser.w == TSI.WIDTH) val wire = Wire(new TSIIO) wire <> ser wire } } class TSIToTileLink(sourceIds: Int = 1)(implicit p: Parameters) extends LazyModule { val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( name = "serial", sourceId = IdRange(0, sourceIds)))))) lazy val module = new TSIToTileLinkModule(this) } class TSIToTileLinkModule(outer: TSIToTileLink) extends LazyModuleImp(outer) { val io = IO(new Bundle { val tsi = new TSIIO val state = Output(UInt()) }) val (mem, edge) = outer.node.out(0) require (edge.manager.minLatency > 0) val pAddrBits = edge.bundle.addressBits val wordLen = 64 val nChunksPerWord = wordLen / TSI.WIDTH val dataBits = mem.params.dataBits val beatBytes = dataBits / 8 val nChunksPerBeat = dataBits / TSI.WIDTH val byteAddrBits = log2Ceil(beatBytes) require(nChunksPerWord > 0, s"Serial interface width must be <= $wordLen") val cmd = Reg(UInt(TSI.WIDTH.W)) val addr = Reg(UInt(wordLen.W)) val len = Reg(UInt(wordLen.W)) val body = Reg(Vec(nChunksPerBeat, UInt(TSI.WIDTH.W))) val bodyValid = Reg(UInt(nChunksPerBeat.W)) val idx = Reg(UInt(log2Up(nChunksPerBeat).W)) val (cmd_read :: cmd_write :: Nil) = Enum(2) val (s_cmd :: s_addr :: s_len :: s_read_req :: s_read_data :: s_read_body :: s_write_body :: s_write_data :: s_write_ack :: Nil) = Enum(9) val state = RegInit(s_cmd) io.state := state io.tsi.in.ready := state.isOneOf(s_cmd, s_addr, s_len, s_write_body) io.tsi.out.valid := state === s_read_body io.tsi.out.bits := body(idx) val beatAddr = addr(pAddrBits - 1, byteAddrBits) val nextAddr = Cat(beatAddr + 1.U, 0.U(byteAddrBits.W)) val wmask = FillInterleaved(TSI.WIDTH/8, bodyValid) val addr_size = nextAddr - addr val len_size = Cat(len + 1.U, 0.U(log2Ceil(TSI.WIDTH/8).W)) val raw_size = Mux(len_size < addr_size, len_size, addr_size) val rsize = MuxLookup(raw_size, byteAddrBits.U)( (0 until log2Ceil(beatBytes)).map(i => ((1 << i).U -> i.U))) val pow2size = PopCount(raw_size) === 1.U val byteAddr = Mux(pow2size, addr(byteAddrBits - 1, 0), 0.U) val put_acquire = edge.Put( 0.U, beatAddr << byteAddrBits.U, log2Ceil(beatBytes).U, body.asUInt, wmask)._2 val get_acquire = edge.Get( 0.U, Cat(beatAddr, byteAddr), rsize)._2 mem.a.valid := state.isOneOf(s_write_data, s_read_req) mem.a.bits := Mux(state === s_write_data, put_acquire, get_acquire) mem.b.ready := false.B mem.c.valid := false.B mem.d.ready := state.isOneOf(s_write_ack, s_read_data) mem.e.valid := false.B def shiftBits(bits: UInt, idx: UInt): UInt = if (nChunksPerWord > 1) bits << Cat(idx(log2Ceil(nChunksPerWord) - 1, 0), 0.U(log2Up(TSI.WIDTH).W)) else bits def addrToIdx(addr: UInt): UInt = if (nChunksPerBeat > 1) addr(byteAddrBits - 1, log2Up(TSI.WIDTH/8)) else 0.U when (state === s_cmd && io.tsi.in.valid) { cmd := io.tsi.in.bits idx := 0.U addr := 0.U len := 0.U state := s_addr } when (state === s_addr && io.tsi.in.valid) { addr := addr | shiftBits(io.tsi.in.bits, idx) idx := idx + 1.U when (idx === (nChunksPerWord - 1).U) { idx := 0.U state := s_len } } when (state === s_len && io.tsi.in.valid) { len := len | shiftBits(io.tsi.in.bits, idx) idx := idx + 1.U when (idx === (nChunksPerWord - 1).U) { idx := addrToIdx(addr) when (cmd === cmd_write) { bodyValid := 0.U state := s_write_body } .elsewhen (cmd === cmd_read) { state := s_read_req } .otherwise { assert(false.B, "Bad TSI command") } } } when (state === s_read_req && mem.a.ready) { state := s_read_data } when (state === s_read_data && mem.d.valid) { body := mem.d.bits.data.asTypeOf(body) idx := addrToIdx(addr) addr := nextAddr state := s_read_body } when (state === s_read_body && io.tsi.out.ready) { idx := idx + 1.U len := len - 1.U when (len === 0.U) { state := s_cmd } .elsewhen (idx === (nChunksPerBeat - 1).U) { state := s_read_req } } when (state === s_write_body && io.tsi.in.valid) { body(idx) := io.tsi.in.bits bodyValid := bodyValid | UIntToOH(idx) when (idx === (nChunksPerBeat - 1).U || len === 0.U) { state := s_write_data } .otherwise { idx := idx + 1.U len := len - 1.U } } when (state === s_write_data && mem.a.ready) { state := s_write_ack } when (state === s_write_ack && mem.d.valid) { when (len === 0.U) { state := s_cmd } .otherwise { addr := nextAddr len := len - 1.U idx := 0.U bodyValid := 0.U state := s_write_body } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TSIToTileLink( // @[TSIToTileLink.scala:36:7] input clock, // @[TSIToTileLink.scala:36:7] input reset, // @[TSIToTileLink.scala:36:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_tsi_in_ready, // @[TSIToTileLink.scala:37:14] input io_tsi_in_valid, // @[TSIToTileLink.scala:37:14] input [31:0] io_tsi_in_bits, // @[TSIToTileLink.scala:37:14] input io_tsi_out_ready, // @[TSIToTileLink.scala:37:14] output io_tsi_out_valid, // @[TSIToTileLink.scala:37:14] output [31:0] io_tsi_out_bits, // @[TSIToTileLink.scala:37:14] output [3:0] io_state // @[TSIToTileLink.scala:37:14] ); wire auto_out_a_ready_0 = auto_out_a_ready; // @[TSIToTileLink.scala:36:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[TSIToTileLink.scala:36:7] wire [4:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_valid_0 = io_tsi_in_valid; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_in_bits_0 = io_tsi_in_bits; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_ready_0 = io_tsi_out_ready; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_a_bits_param = 3'h0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] put_acquire_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] get_acquire_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] _nodeOut_a_bits_T_1_param = 3'h0; // @[TSIToTileLink.scala:95:20] wire auto_out_a_bits_source = 1'h0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_bits_corrupt = 1'h0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _put_acquire_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_acquire_source = 1'h0; // @[Edges.scala:500:17] wire put_acquire_corrupt = 1'h0; // @[Edges.scala:500:17] wire get_acquire_source = 1'h0; // @[Edges.scala:460:17] wire get_acquire_corrupt = 1'h0; // @[Edges.scala:460:17] wire _nodeOut_a_bits_T_1_source = 1'h0; // @[TSIToTileLink.scala:95:20] wire _nodeOut_a_bits_T_1_corrupt = 1'h0; // @[TSIToTileLink.scala:95:20] wire [63:0] get_acquire_data = 64'h0; // @[Edges.scala:460:17] wire [2:0] get_acquire_opcode = 3'h4; // @[Edges.scala:460:17] wire _put_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire [3:0] put_acquire_size = 4'h3; // @[Edges.scala:500:17] wire [2:0] put_acquire_opcode = 3'h1; // @[Edges.scala:500:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[TSIToTileLink.scala:36:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[TSIToTileLink.scala:36:7] wire [4:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[TSIToTileLink.scala:36:7] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[TSIToTileLink.scala:36:7] wire _io_tsi_in_ready_T_6; // @[package.scala:81:59] wire _io_tsi_out_valid_T; // @[TSIToTileLink.scala:71:29] wire [2:0] auto_out_a_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_a_bits_size_0; // @[TSIToTileLink.scala:36:7] wire [31:0] auto_out_a_bits_address_0; // @[TSIToTileLink.scala:36:7] wire [7:0] auto_out_a_bits_mask_0; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_a_bits_data_0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_valid_0; // @[TSIToTileLink.scala:36:7] wire auto_out_d_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_valid_0; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_out_bits_0; // @[TSIToTileLink.scala:36:7] wire [3:0] io_state_0; // @[TSIToTileLink.scala:36:7] wire _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [3:0] _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[TSIToTileLink.scala:36:7] wire [31:0] _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[TSIToTileLink.scala:36:7] wire [7:0] _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[TSIToTileLink.scala:36:7] wire [63:0] _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[TSIToTileLink.scala:36:7] wire _nodeOut_d_ready_T_2; // @[package.scala:81:59] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[TSIToTileLink.scala:36:7] reg [31:0] cmd; // @[TSIToTileLink.scala:56:16] reg [63:0] addr; // @[TSIToTileLink.scala:57:17] reg [63:0] len; // @[TSIToTileLink.scala:58:16] reg [31:0] body_0; // @[TSIToTileLink.scala:59:17] reg [31:0] body_1; // @[TSIToTileLink.scala:59:17] reg [1:0] bodyValid; // @[TSIToTileLink.scala:60:22] reg idx; // @[TSIToTileLink.scala:61:16] wire _addr_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] wire _len_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] reg [3:0] state; // @[TSIToTileLink.scala:67:22] assign io_state_0 = state; // @[TSIToTileLink.scala:36:7, :67:22] wire _io_tsi_in_ready_T = state == 4'h0; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_1 = state == 4'h1; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_2 = state == 4'h2; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_3 = state == 4'h6; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_4 = _io_tsi_in_ready_T | _io_tsi_in_ready_T_1; // @[package.scala:16:47, :81:59] wire _io_tsi_in_ready_T_5 = _io_tsi_in_ready_T_4 | _io_tsi_in_ready_T_2; // @[package.scala:16:47, :81:59] assign _io_tsi_in_ready_T_6 = _io_tsi_in_ready_T_5 | _io_tsi_in_ready_T_3; // @[package.scala:16:47, :81:59] assign io_tsi_in_ready_0 = _io_tsi_in_ready_T_6; // @[TSIToTileLink.scala:36:7] assign _io_tsi_out_valid_T = state == 4'h5; // @[TSIToTileLink.scala:67:22, :71:29] assign io_tsi_out_valid_0 = _io_tsi_out_valid_T; // @[TSIToTileLink.scala:36:7, :71:29] assign io_tsi_out_bits_0 = idx ? body_1 : body_0; // @[TSIToTileLink.scala:36:7, :59:17, :61:16, :72:19] wire [28:0] beatAddr = addr[31:3]; // @[TSIToTileLink.scala:57:17, :74:22] wire [29:0] _nextAddr_T = {1'h0, beatAddr} + 30'h1; // @[TSIToTileLink.scala:74:22, :75:31] wire [28:0] _nextAddr_T_1 = _nextAddr_T[28:0]; // @[TSIToTileLink.scala:75:31] wire [31:0] nextAddr = {_nextAddr_T_1, 3'h0}; // @[TSIToTileLink.scala:75:{21,31}] wire _wmask_T = bodyValid[0]; // @[TSIToTileLink.scala:60:22, :77:30] wire _wmask_T_1 = bodyValid[1]; // @[TSIToTileLink.scala:60:22, :77:30] wire [3:0] _wmask_T_2 = {4{_wmask_T}}; // @[TSIToTileLink.scala:77:30] wire [3:0] _wmask_T_3 = {4{_wmask_T_1}}; // @[TSIToTileLink.scala:77:30] wire [7:0] wmask = {_wmask_T_3, _wmask_T_2}; // @[TSIToTileLink.scala:77:30] wire [7:0] put_acquire_mask = wmask; // @[TSIToTileLink.scala:77:30] wire [64:0] _addr_size_T = {33'h0, nextAddr} - {1'h0, addr}; // @[TSIToTileLink.scala:57:17, :75:21, :78:28] wire [63:0] addr_size = _addr_size_T[63:0]; // @[TSIToTileLink.scala:78:28] wire [64:0] _GEN = {1'h0, len}; // @[TSIToTileLink.scala:58:16, :79:26] wire [64:0] _len_size_T = _GEN + 65'h1; // @[TSIToTileLink.scala:79:26] wire [63:0] _len_size_T_1 = _len_size_T[63:0]; // @[TSIToTileLink.scala:79:26] wire [65:0] len_size = {_len_size_T_1, 2'h0}; // @[TSIToTileLink.scala:79:{21,26}] wire [65:0] _GEN_0 = {2'h0, addr_size}; // @[TSIToTileLink.scala:78:28, :80:31] wire _raw_size_T = len_size < _GEN_0; // @[TSIToTileLink.scala:79:21, :80:31] wire [65:0] raw_size = _raw_size_T ? len_size : _GEN_0; // @[TSIToTileLink.scala:79:21, :80:{21,31}] wire _rsize_T = raw_size == 66'h1; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_1 = _rsize_T ? 2'h0 : 2'h3; // @[TSIToTileLink.scala:81:50] wire _rsize_T_2 = raw_size == 66'h2; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_3 = _rsize_T_2 ? 2'h1 : _rsize_T_1; // @[TSIToTileLink.scala:81:50] wire _rsize_T_4 = raw_size == 66'h4; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] rsize = _rsize_T_4 ? 2'h2 : _rsize_T_3; // @[TSIToTileLink.scala:81:50] wire _pow2size_T = raw_size[0]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_1 = raw_size[1]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_2 = raw_size[2]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_3 = raw_size[3]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_4 = raw_size[4]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_5 = raw_size[5]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_6 = raw_size[6]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_7 = raw_size[7]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_8 = raw_size[8]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_9 = raw_size[9]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_10 = raw_size[10]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_11 = raw_size[11]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_12 = raw_size[12]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_13 = raw_size[13]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_14 = raw_size[14]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_15 = raw_size[15]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_16 = raw_size[16]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_17 = raw_size[17]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_18 = raw_size[18]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_19 = raw_size[19]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_20 = raw_size[20]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_21 = raw_size[21]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_22 = raw_size[22]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_23 = raw_size[23]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_24 = raw_size[24]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_25 = raw_size[25]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_26 = raw_size[26]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_27 = raw_size[27]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_28 = raw_size[28]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_29 = raw_size[29]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_30 = raw_size[30]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_31 = raw_size[31]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_32 = raw_size[32]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_33 = raw_size[33]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_34 = raw_size[34]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_35 = raw_size[35]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_36 = raw_size[36]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_37 = raw_size[37]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_38 = raw_size[38]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_39 = raw_size[39]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_40 = raw_size[40]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_41 = raw_size[41]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_42 = raw_size[42]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_43 = raw_size[43]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_44 = raw_size[44]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_45 = raw_size[45]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_46 = raw_size[46]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_47 = raw_size[47]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_48 = raw_size[48]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_49 = raw_size[49]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_50 = raw_size[50]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_51 = raw_size[51]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_52 = raw_size[52]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_53 = raw_size[53]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_54 = raw_size[54]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_55 = raw_size[55]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_56 = raw_size[56]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_57 = raw_size[57]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_58 = raw_size[58]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_59 = raw_size[59]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_60 = raw_size[60]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_61 = raw_size[61]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_62 = raw_size[62]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_63 = raw_size[63]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_64 = raw_size[64]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_65 = raw_size[65]; // @[TSIToTileLink.scala:80:21, :84:26] wire [1:0] _pow2size_T_66 = {1'h0, _pow2size_T} + {1'h0, _pow2size_T_1}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_67 = _pow2size_T_66; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_68 = {1'h0, _pow2size_T_2} + {1'h0, _pow2size_T_3}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_69 = _pow2size_T_68; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_70 = {1'h0, _pow2size_T_67} + {1'h0, _pow2size_T_69}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_71 = _pow2size_T_70; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_72 = {1'h0, _pow2size_T_4} + {1'h0, _pow2size_T_5}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_73 = _pow2size_T_72; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_74 = {1'h0, _pow2size_T_6} + {1'h0, _pow2size_T_7}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_75 = _pow2size_T_74; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_76 = {1'h0, _pow2size_T_73} + {1'h0, _pow2size_T_75}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_77 = _pow2size_T_76; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_78 = {1'h0, _pow2size_T_71} + {1'h0, _pow2size_T_77}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_79 = _pow2size_T_78; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_80 = {1'h0, _pow2size_T_8} + {1'h0, _pow2size_T_9}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_81 = _pow2size_T_80; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_82 = {1'h0, _pow2size_T_10} + {1'h0, _pow2size_T_11}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_83 = _pow2size_T_82; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_84 = {1'h0, _pow2size_T_81} + {1'h0, _pow2size_T_83}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_85 = _pow2size_T_84; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_86 = {1'h0, _pow2size_T_12} + {1'h0, _pow2size_T_13}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_87 = _pow2size_T_86; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_88 = {1'h0, _pow2size_T_14} + {1'h0, _pow2size_T_15}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_89 = _pow2size_T_88; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_90 = {1'h0, _pow2size_T_87} + {1'h0, _pow2size_T_89}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_91 = _pow2size_T_90; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_92 = {1'h0, _pow2size_T_85} + {1'h0, _pow2size_T_91}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_93 = _pow2size_T_92; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_94 = {1'h0, _pow2size_T_79} + {1'h0, _pow2size_T_93}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_95 = _pow2size_T_94; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_96 = {1'h0, _pow2size_T_16} + {1'h0, _pow2size_T_17}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_97 = _pow2size_T_96; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_98 = {1'h0, _pow2size_T_18} + {1'h0, _pow2size_T_19}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_99 = _pow2size_T_98; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_100 = {1'h0, _pow2size_T_97} + {1'h0, _pow2size_T_99}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_101 = _pow2size_T_100; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_102 = {1'h0, _pow2size_T_20} + {1'h0, _pow2size_T_21}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_103 = _pow2size_T_102; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_104 = {1'h0, _pow2size_T_22} + {1'h0, _pow2size_T_23}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_105 = _pow2size_T_104; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_106 = {1'h0, _pow2size_T_103} + {1'h0, _pow2size_T_105}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_107 = _pow2size_T_106; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_108 = {1'h0, _pow2size_T_101} + {1'h0, _pow2size_T_107}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_109 = _pow2size_T_108; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_110 = {1'h0, _pow2size_T_24} + {1'h0, _pow2size_T_25}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_111 = _pow2size_T_110; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_112 = {1'h0, _pow2size_T_26} + {1'h0, _pow2size_T_27}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_113 = _pow2size_T_112; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_114 = {1'h0, _pow2size_T_111} + {1'h0, _pow2size_T_113}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_115 = _pow2size_T_114; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_116 = {1'h0, _pow2size_T_28} + {1'h0, _pow2size_T_29}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_117 = _pow2size_T_116; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_118 = {1'h0, _pow2size_T_31} + {1'h0, _pow2size_T_32}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_119 = _pow2size_T_118; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_120 = {2'h0, _pow2size_T_30} + {1'h0, _pow2size_T_119}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_121 = _pow2size_T_120[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_122 = {1'h0, _pow2size_T_117} + {1'h0, _pow2size_T_121}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_123 = _pow2size_T_122; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_124 = {1'h0, _pow2size_T_115} + {1'h0, _pow2size_T_123}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_125 = _pow2size_T_124; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_126 = {1'h0, _pow2size_T_109} + {1'h0, _pow2size_T_125}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_127 = _pow2size_T_126; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_128 = {1'h0, _pow2size_T_95} + {1'h0, _pow2size_T_127}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_129 = _pow2size_T_128; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_130 = {1'h0, _pow2size_T_33} + {1'h0, _pow2size_T_34}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_131 = _pow2size_T_130; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_132 = {1'h0, _pow2size_T_35} + {1'h0, _pow2size_T_36}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_133 = _pow2size_T_132; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_134 = {1'h0, _pow2size_T_131} + {1'h0, _pow2size_T_133}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_135 = _pow2size_T_134; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_136 = {1'h0, _pow2size_T_37} + {1'h0, _pow2size_T_38}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_137 = _pow2size_T_136; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_138 = {1'h0, _pow2size_T_39} + {1'h0, _pow2size_T_40}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_139 = _pow2size_T_138; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_140 = {1'h0, _pow2size_T_137} + {1'h0, _pow2size_T_139}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_141 = _pow2size_T_140; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_142 = {1'h0, _pow2size_T_135} + {1'h0, _pow2size_T_141}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_143 = _pow2size_T_142; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_144 = {1'h0, _pow2size_T_41} + {1'h0, _pow2size_T_42}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_145 = _pow2size_T_144; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_146 = {1'h0, _pow2size_T_43} + {1'h0, _pow2size_T_44}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_147 = _pow2size_T_146; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_148 = {1'h0, _pow2size_T_145} + {1'h0, _pow2size_T_147}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_149 = _pow2size_T_148; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_150 = {1'h0, _pow2size_T_45} + {1'h0, _pow2size_T_46}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_151 = _pow2size_T_150; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_152 = {1'h0, _pow2size_T_47} + {1'h0, _pow2size_T_48}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_153 = _pow2size_T_152; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_154 = {1'h0, _pow2size_T_151} + {1'h0, _pow2size_T_153}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_155 = _pow2size_T_154; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_156 = {1'h0, _pow2size_T_149} + {1'h0, _pow2size_T_155}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_157 = _pow2size_T_156; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_158 = {1'h0, _pow2size_T_143} + {1'h0, _pow2size_T_157}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_159 = _pow2size_T_158; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_160 = {1'h0, _pow2size_T_49} + {1'h0, _pow2size_T_50}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_161 = _pow2size_T_160; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_162 = {1'h0, _pow2size_T_51} + {1'h0, _pow2size_T_52}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_163 = _pow2size_T_162; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_164 = {1'h0, _pow2size_T_161} + {1'h0, _pow2size_T_163}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_165 = _pow2size_T_164; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_166 = {1'h0, _pow2size_T_53} + {1'h0, _pow2size_T_54}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_167 = _pow2size_T_166; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_168 = {1'h0, _pow2size_T_55} + {1'h0, _pow2size_T_56}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_169 = _pow2size_T_168; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_170 = {1'h0, _pow2size_T_167} + {1'h0, _pow2size_T_169}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_171 = _pow2size_T_170; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_172 = {1'h0, _pow2size_T_165} + {1'h0, _pow2size_T_171}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_173 = _pow2size_T_172; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_174 = {1'h0, _pow2size_T_57} + {1'h0, _pow2size_T_58}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_175 = _pow2size_T_174; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_176 = {1'h0, _pow2size_T_59} + {1'h0, _pow2size_T_60}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_177 = _pow2size_T_176; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_178 = {1'h0, _pow2size_T_175} + {1'h0, _pow2size_T_177}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_179 = _pow2size_T_178; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_180 = {1'h0, _pow2size_T_61} + {1'h0, _pow2size_T_62}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_181 = _pow2size_T_180; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_182 = {1'h0, _pow2size_T_64} + {1'h0, _pow2size_T_65}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_183 = _pow2size_T_182; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_184 = {2'h0, _pow2size_T_63} + {1'h0, _pow2size_T_183}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_185 = _pow2size_T_184[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_186 = {1'h0, _pow2size_T_181} + {1'h0, _pow2size_T_185}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_187 = _pow2size_T_186; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_188 = {1'h0, _pow2size_T_179} + {1'h0, _pow2size_T_187}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_189 = _pow2size_T_188; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_190 = {1'h0, _pow2size_T_173} + {1'h0, _pow2size_T_189}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_191 = _pow2size_T_190; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_192 = {1'h0, _pow2size_T_159} + {1'h0, _pow2size_T_191}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_193 = _pow2size_T_192; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_194 = {1'h0, _pow2size_T_129} + {1'h0, _pow2size_T_193}; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_195 = _pow2size_T_194; // @[TSIToTileLink.scala:84:26] wire pow2size = _pow2size_T_195 == 7'h1; // @[TSIToTileLink.scala:84:{26,37}] wire [2:0] _byteAddr_T = addr[2:0]; // @[TSIToTileLink.scala:57:17, :85:36] wire [2:0] byteAddr = pow2size ? _byteAddr_T : 3'h0; // @[TSIToTileLink.scala:84:37, :85:{21,36}] wire [31:0] _put_acquire_T = {beatAddr, 3'h0}; // @[TSIToTileLink.scala:74:22, :88:19] wire [31:0] _put_acquire_legal_T_14 = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [31:0] put_acquire_address = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [63:0] _put_acquire_T_1 = {body_1, body_0}; // @[TSIToTileLink.scala:59:17, :89:10] wire [63:0] put_acquire_data = _put_acquire_T_1; // @[TSIToTileLink.scala:89:10] wire [31:0] _put_acquire_legal_T_4 = {_put_acquire_T[31:14], _put_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_5 = {1'h0, _put_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_6 = _put_acquire_legal_T_5 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_7 = _put_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_8 = _put_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_9 = _put_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _put_acquire_legal_T_69 = _put_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _put_acquire_legal_T_15 = {1'h0, _put_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_16 = _put_acquire_legal_T_15 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_17 = _put_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_18 = _put_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_19 = {_put_acquire_T[31:21], _put_acquire_T[20:0] ^ 21'h100000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_20 = {1'h0, _put_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_21 = _put_acquire_legal_T_20 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_22 = _put_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_23 = _put_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_24 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_25 = {1'h0, _put_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_26 = _put_acquire_legal_T_25 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_27 = _put_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_28 = _put_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_29 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2010000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_30 = {1'h0, _put_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_31 = _put_acquire_legal_T_30 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_32 = _put_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_33 = _put_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_1 = {_put_acquire_T[31:28], _put_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:88:19] wire [31:0] _put_acquire_legal_T_34; // @[Parameters.scala:137:31] assign _put_acquire_legal_T_34 = _GEN_1; // @[Parameters.scala:137:31] wire [31:0] _put_acquire_legal_T_39; // @[Parameters.scala:137:31] assign _put_acquire_legal_T_39 = _GEN_1; // @[Parameters.scala:137:31] wire [32:0] _put_acquire_legal_T_35 = {1'h0, _put_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_36 = _put_acquire_legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_37 = _put_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_38 = _put_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _put_acquire_legal_T_40 = {1'h0, _put_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_41 = _put_acquire_legal_T_40 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_42 = _put_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_43 = _put_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_44 = {_put_acquire_T[31:29], _put_acquire_T[28:0] ^ 29'h10000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_45 = {1'h0, _put_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_46 = _put_acquire_legal_T_45 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_47 = _put_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_48 = _put_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_49 = _put_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_50 = {1'h0, _put_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_51 = _put_acquire_legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_52 = _put_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_53 = _put_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_54 = _put_acquire_legal_T_18 | _put_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_55 = _put_acquire_legal_T_54 | _put_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_56 = _put_acquire_legal_T_55 | _put_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_57 = _put_acquire_legal_T_56 | _put_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_58 = _put_acquire_legal_T_57 | _put_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_59 = _put_acquire_legal_T_58 | _put_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_60 = _put_acquire_legal_T_59 | _put_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_61 = _put_acquire_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [31:0] _put_acquire_legal_T_63 = {_put_acquire_T[31:17], _put_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_64 = {1'h0, _put_acquire_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_65 = _put_acquire_legal_T_64 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_66 = _put_acquire_legal_T_65; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_67 = _put_acquire_legal_T_66 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_70 = _put_acquire_legal_T_69 | _put_acquire_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_acquire_legal = _put_acquire_legal_T_70; // @[Parameters.scala:686:26] wire [31:0] _get_acquire_T = {beatAddr, byteAddr}; // @[TSIToTileLink.scala:74:22, :85:21, :92:13] wire [31:0] _get_acquire_legal_T_14 = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] get_acquire_address = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_4 = {_get_acquire_T[31:14], _get_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_5 = {1'h0, _get_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_6 = _get_acquire_legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_7 = _get_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_8 = _get_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_9 = _get_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _get_acquire_legal_T_62 = _get_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _get_acquire_legal_T_15 = {1'h0, _get_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_16 = _get_acquire_legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_17 = _get_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_18 = _get_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_2 = {_get_acquire_T[31:17], _get_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_19; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _get_acquire_legal_T_24; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _get_acquire_legal_T_20 = {1'h0, _get_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_21 = _get_acquire_legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_22 = _get_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_23 = _get_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _get_acquire_legal_T_25 = {1'h0, _get_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_26 = _get_acquire_legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_27 = _get_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_28 = _get_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_29 = {_get_acquire_T[31:26], _get_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_30 = {1'h0, _get_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_31 = _get_acquire_legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_32 = _get_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_33 = _get_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_3 = {_get_acquire_T[31:28], _get_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_34; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_34 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _get_acquire_legal_T_39; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [32:0] _get_acquire_legal_T_35 = {1'h0, _get_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_36 = _get_acquire_legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_37 = _get_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_38 = _get_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _get_acquire_legal_T_40 = {1'h0, _get_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_41 = _get_acquire_legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_42 = _get_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_43 = _get_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_44 = {_get_acquire_T[31:29], _get_acquire_T[28:0] ^ 29'h10000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_45 = {1'h0, _get_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_46 = _get_acquire_legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_47 = _get_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_48 = _get_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_49 = _get_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_50 = {1'h0, _get_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_51 = _get_acquire_legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_52 = _get_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_53 = _get_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_54 = _get_acquire_legal_T_18 | _get_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_55 = _get_acquire_legal_T_54 | _get_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_56 = _get_acquire_legal_T_55 | _get_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_57 = _get_acquire_legal_T_56 | _get_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_58 = _get_acquire_legal_T_57 | _get_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_59 = _get_acquire_legal_T_58 | _get_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_60 = _get_acquire_legal_T_59 | _get_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_61 = _get_acquire_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_acquire_legal = _get_acquire_legal_T_62 | _get_acquire_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_acquire_size; // @[Edges.scala:460:17] wire [7:0] get_acquire_mask; // @[Edges.scala:460:17] assign get_acquire_size = {2'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [2:0] _get_acquire_a_mask_sizeOH_T = {1'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [1:0] get_acquire_a_mask_sizeOH_shiftAmount = _get_acquire_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_acquire_a_mask_sizeOH_T_1 = 4'h1 << get_acquire_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_acquire_a_mask_sizeOH_T_2 = _get_acquire_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_acquire_a_mask_sizeOH = {_get_acquire_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_acquire_a_mask_sub_sub_sub_0_1 = &rsize; // @[TSIToTileLink.scala:81:50] wire get_acquire_a_mask_sub_sub_size = get_acquire_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_sub_bit = _get_acquire_T[2]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_sub_1_2 = get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_acquire_a_mask_sub_sub_nbit = ~get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_sub_0_2 = get_acquire_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_sub_acc_T = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_0_1 = get_acquire_a_mask_sub_sub_sub_0_1 | _get_acquire_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_acquire_a_mask_sub_sub_acc_T_1 = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_1_1 = get_acquire_a_mask_sub_sub_sub_0_1 | _get_acquire_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_acquire_a_mask_sub_size = get_acquire_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_bit = _get_acquire_T[1]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_nbit = ~get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_0_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_0_1 = get_acquire_a_mask_sub_sub_0_1 | _get_acquire_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_1_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_1 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_1_1 = get_acquire_a_mask_sub_sub_0_1 | _get_acquire_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_2_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T_2 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_2_1 = get_acquire_a_mask_sub_sub_1_1 | _get_acquire_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_3_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_3 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_3_1 = get_acquire_a_mask_sub_sub_1_1 | _get_acquire_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_size = get_acquire_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_bit = _get_acquire_T[0]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_nbit = ~get_acquire_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_eq = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T = get_acquire_a_mask_size & get_acquire_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc = get_acquire_a_mask_sub_0_1 | _get_acquire_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_1 = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_1 = get_acquire_a_mask_size & get_acquire_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_1 = get_acquire_a_mask_sub_0_1 | _get_acquire_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_2 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_2 = get_acquire_a_mask_size & get_acquire_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_2 = get_acquire_a_mask_sub_1_1 | _get_acquire_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_3 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_3 = get_acquire_a_mask_size & get_acquire_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_3 = get_acquire_a_mask_sub_1_1 | _get_acquire_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_4 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_4 = get_acquire_a_mask_size & get_acquire_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_4 = get_acquire_a_mask_sub_2_1 | _get_acquire_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_5 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_5 = get_acquire_a_mask_size & get_acquire_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_5 = get_acquire_a_mask_sub_2_1 | _get_acquire_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_6 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_6 = get_acquire_a_mask_size & get_acquire_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_6 = get_acquire_a_mask_sub_3_1 | _get_acquire_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_7 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_7 = get_acquire_a_mask_size & get_acquire_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_7 = get_acquire_a_mask_sub_3_1 | _get_acquire_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_acquire_a_mask_lo_lo = {get_acquire_a_mask_acc_1, get_acquire_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_lo_hi = {get_acquire_a_mask_acc_3, get_acquire_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_lo = {get_acquire_a_mask_lo_hi, get_acquire_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_acquire_a_mask_hi_lo = {get_acquire_a_mask_acc_5, get_acquire_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_hi_hi = {get_acquire_a_mask_acc_7, get_acquire_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_hi = {get_acquire_a_mask_hi_hi, get_acquire_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_acquire_a_mask_T = {get_acquire_a_mask_hi, get_acquire_a_mask_lo}; // @[Misc.scala:222:10] assign get_acquire_mask = _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire _T_28 = state == 4'h7; // @[TSIToTileLink.scala:67:22] wire _nodeOut_a_valid_T; // @[package.scala:16:47] assign _nodeOut_a_valid_T = _T_28; // @[package.scala:16:47] wire _nodeOut_a_bits_T; // @[TSIToTileLink.scala:95:27] assign _nodeOut_a_bits_T = _T_28; // @[TSIToTileLink.scala:95:27] wire _nodeOut_a_valid_T_1 = state == 4'h3; // @[TSIToTileLink.scala:67:22] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T | _nodeOut_a_valid_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign _nodeOut_a_bits_T_1_opcode = _nodeOut_a_bits_T ? 3'h1 : 3'h4; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_size = _nodeOut_a_bits_T ? 4'h3 : get_acquire_size; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_address = _nodeOut_a_bits_T ? put_acquire_address : get_acquire_address; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_mask = _nodeOut_a_bits_T ? put_acquire_mask : get_acquire_mask; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_data = _nodeOut_a_bits_T ? put_acquire_data : 64'h0; // @[TSIToTileLink.scala:95:{20,27}] assign nodeOut_a_bits_opcode = _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_size = _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_address = _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_mask = _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_data = _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] wire _nodeOut_d_ready_T = state == 4'h8; // @[TSIToTileLink.scala:67:22] wire _nodeOut_d_ready_T_1 = state == 4'h4; // @[TSIToTileLink.scala:67:22] assign _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T | _nodeOut_d_ready_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire [5:0] _addr_T_1 = {_addr_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _GEN_4 = {63'h0, io_tsi_in_bits_0}; // @[TSIToTileLink.scala:36:7, :103:12] wire [94:0] _addr_T_2 = _GEN_4 << _addr_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _addr_T_3 = {31'h0, addr} | _addr_T_2; // @[TSIToTileLink.scala:57:17, :103:12, :118:18] wire [1:0] _GEN_5 = {1'h0, idx}; // @[TSIToTileLink.scala:61:16, :119:16] wire [1:0] _GEN_6 = _GEN_5 + 2'h1; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T; // @[TSIToTileLink.scala:119:16] assign _idx_T = _GEN_6; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T_2; // @[TSIToTileLink.scala:128:16] assign _idx_T_2 = _GEN_6; // @[TSIToTileLink.scala:119:16, :128:16] wire [1:0] _idx_T_6; // @[TSIToTileLink.scala:154:16] assign _idx_T_6 = _GEN_6; // @[TSIToTileLink.scala:119:16, :154:16] wire [1:0] _idx_T_8; // @[TSIToTileLink.scala:166:18] assign _idx_T_8 = _GEN_6; // @[TSIToTileLink.scala:119:16, :166:18] wire _idx_T_1 = _idx_T[0]; // @[TSIToTileLink.scala:119:16] wire _T_6 = _io_tsi_in_ready_T_2 & io_tsi_in_valid_0; // @[TSIToTileLink.scala:36:7, :126:25] wire [5:0] _len_T_1 = {_len_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _len_T_2 = _GEN_4 << _len_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _len_T_3 = {31'h0, len} | _len_T_2; // @[TSIToTileLink.scala:58:16, :103:12, :127:16] wire _idx_T_3 = _idx_T_2[0]; // @[TSIToTileLink.scala:128:16] wire _GEN_7 = _T_6 & idx; // @[TSIToTileLink.scala:61:16, :126:25, :129:43] wire _idx_T_4 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33] wire _idx_T_5 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33]

Generate the Verilog code corresponding to the following Chisel files. File Multiplier.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe} import freechips.rocketchip.util._ import ALU._ class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle { val fn = Bits(SZ_ALU_FN.W) val dw = Bits(SZ_DW.W) val in1 = Bits(dataBits.W) val in2 = Bits(dataBits.W) val tag = UInt(tagBits.W) } class MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle { val data = Bits(dataBits.W) val full_data = Bits((2*dataBits).W) val tag = UInt(tagBits.W) } class MultiplierIO(val dataBits: Int, val tagBits: Int) extends Bundle { val req = Flipped(Decoupled(new MultiplierReq(dataBits, tagBits))) val kill = Input(Bool()) val resp = Decoupled(new MultiplierResp(dataBits, tagBits)) } case class MulDivParams( mulUnroll: Int = 1, divUnroll: Int = 1, mulEarlyOut: Boolean = false, divEarlyOut: Boolean = false, divEarlyOutGranularity: Int = 1 ) class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module { private def minDivLatency = (cfg.divUnroll > 0).option(if (cfg.divEarlyOut) 3 else 1 + w/cfg.divUnroll) private def minMulLatency = (cfg.mulUnroll > 0).option(if (cfg.mulEarlyOut) 2 else w/cfg.mulUnroll) def minLatency: Int = (minDivLatency ++ minMulLatency).min val io = IO(new MultiplierIO(width, log2Up(nXpr))) val w = io.req.bits.in1.getWidth val mulw = if (cfg.mulUnroll == 0) w else (w + cfg.mulUnroll - 1) / cfg.mulUnroll * cfg.mulUnroll val fastMulW = if (cfg.mulUnroll == 0) false else w/2 > cfg.mulUnroll && w % (2*cfg.mulUnroll) == 0 val s_ready :: s_neg_inputs :: s_mul :: s_div :: s_dummy :: s_neg_output :: s_done_mul :: s_done_div :: Nil = Enum(8) val state = RegInit(s_ready) val req = Reg(chiselTypeOf(io.req.bits)) val count = Reg(UInt(log2Ceil( ((cfg.divUnroll != 0).option(w/cfg.divUnroll + 1).toSeq ++ (cfg.mulUnroll != 0).option(mulw/cfg.mulUnroll)).reduce(_ max _)).W)) val neg_out = Reg(Bool()) val isHi = Reg(Bool()) val resHi = Reg(Bool()) val divisor = Reg(Bits((w+1).W)) // div only needs w bits val remainder = Reg(Bits((2*mulw+2).W)) // div only needs 2*w+1 bits val mulDecode = List( FN_MUL -> List(Y, N, X, X), FN_MULH -> List(Y, Y, Y, Y), FN_MULHU -> List(Y, Y, N, N), FN_MULHSU -> List(Y, Y, Y, N)) val divDecode = List( FN_DIV -> List(N, N, Y, Y), FN_REM -> List(N, Y, Y, Y), FN_DIVU -> List(N, N, N, N), FN_REMU -> List(N, Y, N, N)) val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil = DecodeLogic(io.req.bits.fn, List(X, X, X, X), (if (cfg.divUnroll != 0) divDecode else Nil) ++ (if (cfg.mulUnroll != 0) mulDecode else Nil)).map(_.asBool) require(w == 32 || w == 64) def halfWidth(req: MultiplierReq) = (w > 32).B && req.dw === DW_32 def sext(x: Bits, halfW: Bool, signed: Bool) = { val sign = signed && Mux(halfW, x(w/2-1), x(w-1)) val hi = Mux(halfW, Fill(w/2, sign), x(w-1,w/2)) (Cat(hi, x(w/2-1,0)), sign) } val (lhs_in, lhs_sign) = sext(io.req.bits.in1, halfWidth(io.req.bits), lhsSigned) val (rhs_in, rhs_sign) = sext(io.req.bits.in2, halfWidth(io.req.bits), rhsSigned) val subtractor = remainder(2*w,w) - divisor val result = Mux(resHi, remainder(2*w, w+1), remainder(w-1, 0)) val negated_remainder = -result if (cfg.divUnroll != 0) when (state === s_neg_inputs) { when (remainder(w-1)) { remainder := negated_remainder } when (divisor(w-1)) { divisor := subtractor } state := s_div } if (cfg.divUnroll != 0) when (state === s_neg_output) { remainder := negated_remainder state := s_done_div resHi := false.B } if (cfg.mulUnroll != 0) when (state === s_mul) { val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0)) val mplierSign = remainder(w) val mplier = mulReg(mulw-1,0) val accum = mulReg(2*mulw,mulw).asSInt val mpcand = divisor.asSInt val prod = Cat(mplierSign, mplier(cfg.mulUnroll-1, 0)).asSInt * mpcand + accum val nextMulReg = Cat(prod, mplier(mulw-1, cfg.mulUnroll)) val nextMplierSign = count === (mulw/cfg.mulUnroll-2).U && neg_out val eOutMask = ((BigInt(-1) << mulw).S >> (count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))(mulw-1,0) val eOut = (cfg.mulEarlyOut).B && count =/= (mulw/cfg.mulUnroll-1).U && count =/= 0.U && !isHi && (mplier & ~eOutMask) === 0.U val eOutRes = (mulReg >> (mulw.U - count * cfg.mulUnroll.U)(log2Up(mulw)-1,0)) val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0)) remainder := Cat(nextMulReg1 >> w, nextMplierSign, nextMulReg1(w-1,0)) count := count + 1.U when (eOut || count === (mulw/cfg.mulUnroll-1).U) { state := s_done_mul resHi := isHi } } if (cfg.divUnroll != 0) when (state === s_div) { val unrolls = ((0 until cfg.divUnroll) scanLeft remainder) { case (rem, i) => // the special case for iteration 0 is to save HW, not for correctness val difference = if (i == 0) subtractor else rem(2*w,w) - divisor(w-1,0) val less = difference(w) Cat(Mux(less, rem(2*w-1,w), difference(w-1,0)), rem(w-1,0), !less) }.tail remainder := unrolls.last when (count === (w/cfg.divUnroll).U) { state := Mux(neg_out, s_neg_output, s_done_div) resHi := isHi if (w % cfg.divUnroll < cfg.divUnroll - 1) remainder := unrolls(w % cfg.divUnroll) } count := count + 1.U val divby0 = count === 0.U && !subtractor(w) if (cfg.divEarlyOut) { val align = 1 << log2Floor(cfg.divUnroll max cfg.divEarlyOutGranularity) val alignMask = ~((align-1).U(log2Ceil(w).W)) val divisorMSB = Log2(divisor(w-1,0), w) & alignMask val dividendMSB = Log2(remainder(w-1,0), w) | ~alignMask val eOutPos = ~(dividendMSB - divisorMSB) val eOut = count === 0.U && !divby0 && eOutPos >= align.U when (eOut) { remainder := remainder(w-1,0) << eOutPos count := eOutPos >> log2Floor(cfg.divUnroll) } } when (divby0 && !isHi) { neg_out := false.B } } when (io.resp.fire || io.kill) { state := s_ready } when (io.req.fire) { state := Mux(cmdMul, s_mul, Mux(lhs_sign || rhs_sign, s_neg_inputs, s_div)) isHi := cmdHi resHi := false.B count := (if (fastMulW) Mux[UInt](cmdMul && halfWidth(io.req.bits), (w/cfg.mulUnroll/2).U, 0.U) else 0.U) neg_out := Mux(cmdHi, lhs_sign, lhs_sign =/= rhs_sign) divisor := Cat(rhs_sign, rhs_in) remainder := lhs_in req := io.req.bits } val outMul = (state & (s_done_mul ^ s_done_div)) === (s_done_mul & ~s_done_div) val loOut = Mux(fastMulW.B && halfWidth(req) && outMul, result(w-1,w/2), result(w/2-1,0)) val hiOut = Mux(halfWidth(req), Fill(w/2, loOut(w/2-1)), result(w-1,w/2)) io.resp.bits.tag := req.tag io.resp.bits.data := Cat(hiOut, loOut) io.resp.bits.full_data := Cat(remainder(2*w, w+1), remainder(w-1, 0)) io.resp.valid := (state === s_done_mul || state === s_done_div) io.req.ready := state === s_ready } class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed { val io = IO(new Bundle { val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr)))) val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr))) }) val in = Pipe(io.req) val decode = List( FN_MUL -> List(N, X, X), FN_MULH -> List(Y, Y, Y), FN_MULHU -> List(Y, N, N), FN_MULHSU -> List(Y, Y, N)) val cmdHi :: lhsSigned :: rhsSigned :: Nil = DecodeLogic(in.bits.fn, List(X, X, X), decode).map(_.asBool) val cmdHalf = (width > 32).B && in.bits.dw === DW_32 val lhs = Cat(lhsSigned && in.bits.in1(width-1), in.bits.in1).asSInt val rhs = Cat(rhsSigned && in.bits.in2(width-1), in.bits.in2).asSInt val prod = lhs * rhs val muxed = Mux(cmdHi, prod(2*width-1, width), Mux(cmdHalf, prod(width/2-1, 0).sextTo(width), prod(width-1, 0))) val resp = Pipe(in, latency-1) io.resp.valid := resp.valid io.resp.bits.tag := resp.bits.tag io.resp.bits.data := Pipe(in.valid, muxed, latency-1).bits io.resp.bits.full_data := Pipe(in.valid, prod, latency-1).bits.asUInt }

module MulDiv_1( // @[Multiplier.scala:40:7] input clock, // @[Multiplier.scala:40:7] input reset, // @[Multiplier.scala:40:7] output io_req_ready, // @[Multiplier.scala:45:14] input io_req_valid, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_fn, // @[Multiplier.scala:45:14] input io_req_bits_dw, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in1, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in2, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_tag, // @[Multiplier.scala:45:14] input io_resp_ready, // @[Multiplier.scala:45:14] output io_resp_valid, // @[Multiplier.scala:45:14] output [63:0] io_resp_bits_data, // @[Multiplier.scala:45:14] output [4:0] io_resp_bits_tag // @[Multiplier.scala:45:14] ); reg [2:0] state; // @[Multiplier.scala:51:22] reg req_dw; // @[Multiplier.scala:53:16] reg [4:0] req_tag; // @[Multiplier.scala:53:16] reg [6:0] count; // @[Multiplier.scala:54:18] reg neg_out; // @[Multiplier.scala:57:20] reg isHi; // @[Multiplier.scala:58:17] reg resHi; // @[Multiplier.scala:59:18] reg [64:0] divisor; // @[Multiplier.scala:60:20] reg [129:0] remainder; // @[Multiplier.scala:61:22] wire [63:0] result = resHi ? remainder[128:65] : remainder[63:0]; // @[Multiplier.scala:59:18, :61:22, :89:{19,36,57}] wire io_resp_valid_0 = state == 3'h6 | (&state); // @[Multiplier.scala:51:22, :182:{27,42,51}] wire io_req_ready_0 = state == 3'h0; // @[Multiplier.scala:51:22, :183:25] wire [5:0] _eOutPos_T = {|(remainder[63:32]), (|(remainder[63:32])) ? {|(remainder[63:48]), (|(remainder[63:48])) ? {|(remainder[63:56]), (|(remainder[63:56])) ? {|(remainder[63:60]), (|(remainder[63:60])) ? (remainder[63] ? 2'h3 : remainder[62] ? 2'h2 : {1'h0, remainder[61]}) : remainder[59] ? 2'h3 : remainder[58] ? 2'h2 : {1'h0, remainder[57]}} : {|(remainder[55:52]), (|(remainder[55:52])) ? (remainder[55] ? 2'h3 : remainder[54] ? 2'h2 : {1'h0, remainder[53]}) : remainder[51] ? 2'h3 : remainder[50] ? 2'h2 : {1'h0, remainder[49]}}} : {|(remainder[47:40]), (|(remainder[47:40])) ? {|(remainder[47:44]), (|(remainder[47:44])) ? (remainder[47] ? 2'h3 : remainder[46] ? 2'h2 : {1'h0, remainder[45]}) : remainder[43] ? 2'h3 : remainder[42] ? 2'h2 : {1'h0, remainder[41]}} : {|(remainder[39:36]), (|(remainder[39:36])) ? (remainder[39] ? 2'h3 : remainder[38] ? 2'h2 : {1'h0, remainder[37]}) : remainder[35] ? 2'h3 : remainder[34] ? 2'h2 : {1'h0, remainder[33]}}}} : {|(remainder[31:16]), (|(remainder[31:16])) ? {|(remainder[31:24]), (|(remainder[31:24])) ? {|(remainder[31:28]), (|(remainder[31:28])) ? (remainder[31] ? 2'h3 : remainder[30] ? 2'h2 : {1'h0, remainder[29]}) : remainder[27] ? 2'h3 : remainder[26] ? 2'h2 : {1'h0, remainder[25]}} : {|(remainder[23:20]), (|(remainder[23:20])) ? (remainder[23] ? 2'h3 : remainder[22] ? 2'h2 : {1'h0, remainder[21]}) : remainder[19] ? 2'h3 : remainder[18] ? 2'h2 : {1'h0, remainder[17]}}} : {|(remainder[15:8]), (|(remainder[15:8])) ? {|(remainder[15:12]), (|(remainder[15:12])) ? (remainder[15] ? 2'h3 : remainder[14] ? 2'h2 : {1'h0, remainder[13]}) : remainder[11] ? 2'h3 : remainder[10] ? 2'h2 : {1'h0, remainder[9]}} : {|(remainder[7:4]), (|(remainder[7:4])) ? (remainder[7] ? 2'h3 : remainder[6] ? 2'h2 : {1'h0, remainder[5]}) : remainder[3] ? 2'h3 : remainder[2] ? 2'h2 : {1'h0, remainder[1]}}}}} - {|(divisor[63:32]), (|(divisor[63:32])) ? {|(divisor[63:48]), (|(divisor[63:48])) ? {|(divisor[63:56]), (|(divisor[63:56])) ? {|(divisor[63:60]), (|(divisor[63:60])) ? (divisor[63] ? 2'h3 : divisor[62] ? 2'h2 : {1'h0, divisor[61]}) : divisor[59] ? 2'h3 : divisor[58] ? 2'h2 : {1'h0, divisor[57]}} : {|(divisor[55:52]), (|(divisor[55:52])) ? (divisor[55] ? 2'h3 : divisor[54] ? 2'h2 : {1'h0, divisor[53]}) : divisor[51] ? 2'h3 : divisor[50] ? 2'h2 : {1'h0, divisor[49]}}} : {|(divisor[47:40]), (|(divisor[47:40])) ? {|(divisor[47:44]), (|(divisor[47:44])) ? (divisor[47] ? 2'h3 : divisor[46] ? 2'h2 : {1'h0, divisor[45]}) : divisor[43] ? 2'h3 : divisor[42] ? 2'h2 : {1'h0, divisor[41]}} : {|(divisor[39:36]), (|(divisor[39:36])) ? (divisor[39] ? 2'h3 : divisor[38] ? 2'h2 : {1'h0, divisor[37]}) : divisor[35] ? 2'h3 : divisor[34] ? 2'h2 : {1'h0, divisor[33]}}}} : {|(divisor[31:16]), (|(divisor[31:16])) ? {|(divisor[31:24]), (|(divisor[31:24])) ? {|(divisor[31:28]), (|(divisor[31:28])) ? (divisor[31] ? 2'h3 : divisor[30] ? 2'h2 : {1'h0, divisor[29]}) : divisor[27] ? 2'h3 : divisor[26] ? 2'h2 : {1'h0, divisor[25]}} : {|(divisor[23:20]), (|(divisor[23:20])) ? (divisor[23] ? 2'h3 : divisor[22] ? 2'h2 : {1'h0, divisor[21]}) : divisor[19] ? 2'h3 : divisor[18] ? 2'h2 : {1'h0, divisor[17]}}} : {|(divisor[15:8]), (|(divisor[15:8])) ? {|(divisor[15:12]), (|(divisor[15:12])) ? (divisor[15] ? 2'h3 : divisor[14] ? 2'h2 : {1'h0, divisor[13]}) : divisor[11] ? 2'h3 : divisor[10] ? 2'h2 : {1'h0, divisor[9]}} : {|(divisor[7:4]), (|(divisor[7:4])) ? (divisor[7] ? 2'h3 : divisor[6] ? 2'h2 : {1'h0, divisor[5]}) : divisor[3] ? 2'h3 : divisor[2] ? 2'h2 : {1'h0, divisor[1]}}}}}; // @[CircuitMath.scala:28:8, :30:{10,12}, :33:17, :34:17, :35:22, :36:{10,21}] wire [1:0] _decoded_andMatrixOutputs_T = {~(io_req_bits_fn[0]), io_req_bits_fn[2]}; // @[pla.scala:78:21, :90:45, :98:53] wire [1:0] _decoded_andMatrixOutputs_T_1 = {io_req_bits_fn[1], io_req_bits_fn[2]}; // @[pla.scala:90:45, :98:53] wire lhs_sign = (&_decoded_andMatrixOutputs_T) & (io_req_bits_dw ? io_req_bits_in1[63] : io_req_bits_in1[31]); // @[pla.scala:98:{53,70}] wire rhs_sign = (&_decoded_andMatrixOutputs_T) & (io_req_bits_dw ? io_req_bits_in2[63] : io_req_bits_in2[31]); // @[pla.scala:98:{53,70}] wire [64:0] _subtractor_T_1 = remainder[128:64] - divisor; // @[Multiplier.scala:60:20, :61:22, :88:{29,37}] wire _GEN = state == 3'h1; // @[Multiplier.scala:51:22, :92:39] wire _GEN_0 = state == 3'h5; // @[Multiplier.scala:51:22, :101:39] wire _GEN_1 = state == 3'h3; // @[Multiplier.scala:51:22, :129:39] wire _GEN_2 = _GEN_1 & count == 7'h40; // @[Multiplier.scala:54:18, :101:57, :129:{39,50}, :138:{17,42}, :139:13] wire _eOut_T = count == 7'h0; // @[Multiplier.scala:54:18, :146:24] wire divby0 = _eOut_T & ~(_subtractor_T_1[64]); // @[Multiplier.scala:88:37, :133:28, :146:{24,32,35}] wire _GEN_3 = io_req_ready_0 & io_req_valid; // @[Decoupled.scala:51:35] wire eOut = _eOut_T & ~divby0 & _eOutPos_T != 6'h3F; // @[Multiplier.scala:146:{24,32}, :152:35, :153:{32,35,43,54}] always @(posedge clock) begin // @[Multiplier.scala:40:7] if (reset) // @[Multiplier.scala:40:7] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_GEN_3) // @[Decoupled.scala:51:35] state <= {1'h0, ~(lhs_sign | rhs_sign), 1'h1}; // @[Multiplier.scala:51:22, :81:23, :165:{36,46}] else if (io_resp_ready & io_resp_valid_0) // @[Decoupled.scala:51:35] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_GEN_2) // @[Multiplier.scala:101:57, :129:50, :138:42, :139:13] state <= {1'h1, ~neg_out, 1'h1}; // @[Multiplier.scala:51:22, :57:20, :139:19] else if (_GEN_0) // @[Multiplier.scala:101:39] state <= 3'h7; // @[Multiplier.scala:51:22] else if (_GEN) // @[Multiplier.scala:92:39] state <= 3'h3; // @[Multiplier.scala:51:22] if (_GEN_3) begin // @[Decoupled.scala:51:35] req_dw <= io_req_bits_dw; // @[Multiplier.scala:53:16] req_tag <= io_req_bits_tag; // @[Multiplier.scala:53:16] count <= 7'h0; // @[Multiplier.scala:54:18] isHi <= &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] divisor <= {rhs_sign, io_req_bits_dw ? io_req_bits_in2[63:32] : {32{rhs_sign}}, io_req_bits_in2[31:0]}; // @[Multiplier.scala:60:20, :81:23, :82:{17,29,43}, :83:15, :170:19] remainder <= {66'h0, io_req_bits_dw ? io_req_bits_in1[63:32] : {32{lhs_sign}}, io_req_bits_in1[31:0]}; // @[Multiplier.scala:61:22, :81:23, :82:{17,29,43}, :83:15, :94:17, :171:15] end else begin // @[Decoupled.scala:51:35] if (_GEN_1) begin // @[Multiplier.scala:129:39] count <= eOut ? {1'h0, ~_eOutPos_T} : count + 7'h1; // @[Multiplier.scala:54:18, :144:{11,20}, :152:{21,35}, :153:{32,43}, :154:19, :156:15] remainder <= eOut ? {3'h0, {63'h0, remainder[63:0]} << ~_eOutPos_T} : {1'h0, _subtractor_T_1[64] ? remainder[127:64] : _subtractor_T_1[63:0], remainder[63:0], ~(_subtractor_T_1[64])}; // @[Multiplier.scala:61:22, :88:37, :89:57, :133:28, :134:{14,24,45,67}, :137:15, :152:{21,35}, :153:{32,43}, :154:19, :155:{19,39}] end else if (_GEN_0 | _GEN & remainder[63]) // @[Multiplier.scala:61:22, :92:{39,57}, :93:{20,27}, :94:17, :101:{39,57}, :102:15] remainder <= {66'h0, 64'h0 - result}; // @[Multiplier.scala:61:22, :89:19, :90:27, :94:17] if (_GEN & divisor[63]) // @[Multiplier.scala:60:20, :92:{39,57}, :96:{18,25}, :97:15] divisor <= _subtractor_T_1; // @[Multiplier.scala:60:20, :88:37] end neg_out <= _GEN_3 ? ((&_decoded_andMatrixOutputs_T_1) ? lhs_sign : lhs_sign != rhs_sign) : ~(_GEN_1 & divby0 & ~isHi) & neg_out; // @[pla.scala:98:{53,70}] resHi <= ~_GEN_3 & (_GEN_2 ? isHi : ~_GEN_0 & resHi); // @[Decoupled.scala:51:35] always @(posedge)

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /** Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. */ class ClientMetadata extends Bundle { /** Actual state information stored in this bundle */ val state = UInt(ClientStates.width.W) /** Metadata equality */ def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /** Is the block's data present in this cache */ def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /** Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) */ private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /** Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). */ private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd || param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /** Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). */ def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /** Does a secondary miss on the block require another Acquire message */ def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /** Metadata change on a returned Grant */ def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /** Determine what state to go to based on Probe param */ private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /** Translate cache control cmds into Probe param */ private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /** Factories for ClientMetadata, including on reset */ object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File MSHR.scala: package shuttle.dmem import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ class ShuttleDCacheMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) val req_sec_rdy = Output(Bool()) val req_bits = Input(new ShuttleMSHRReq()) val probe_addr = Input(UInt(paddrBits.W)) val idx_match = Output(Bool()) val tag = Output(Bits(tagBits.W)) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Valid(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val refill = Output(new L1RefillReq()) // Data is bypassed val meta_write = Decoupled(new L1MetaWriteReq) val replay = Decoupled(new ShuttleMSHRReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val probe_rdy = Output(Bool()) }) val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(9) val state = RegInit(s_invalid) val req = Reg(new ShuttleMSHRReq) val req_idx = req.addr(untagBits-1,blockOffBits) val req_tag = req.addr >> untagBits val req_block_addr = (req.addr >> blockOffBits) << blockOffBits val idx_match = req_idx === io.req_bits.addr(untagBits-1,blockOffBits) val probe_idx_match = req_idx === io.probe_addr(untagBits-1,blockOffBits) val new_coh = RegInit(ClientMetadata.onReset) val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH) val grow_param = new_coh.onAccess(req.cmd)._2 val coh_on_grant = new_coh.onGrant(req.cmd, io.mem_grant.bits.param) // We only accept secondary misses if we haven't yet sent an Acquire to outer memory // or if the Acquire that was sent will obtain a Grant with sufficient permissions // to let us replay this new request. I.e. we don't handle multiple outstanding // Acquires on the same block for now. val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) = new_coh.onSecondaryAccess(req.cmd, io.req_bits.cmd) val states_before_refill = Seq(s_wb_req, s_wb_resp, s_meta_clear) val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) val sec_rdy = idx_match && (state.isOneOf(states_before_refill) || (state.isOneOf(s_refill_req, s_refill_resp) && !cmd_requires_second_acquire && !refill_done)) val rpq = Module(new Queue(new ShuttleMSHRReq, cfg.nRPQ)) rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(io.req_bits.cmd) rpq.io.enq.bits := io.req_bits rpq.io.deq.ready := (io.replay.ready && state === s_drain_rpq) || state === s_invalid val acked = Reg(Bool()) when (io.mem_grant.valid) { acked := true.B } when (state === s_drain_rpq && !rpq.io.deq.valid) { state := s_invalid } when (state === s_meta_write_resp) { // this wait state allows us to catch RAW hazards on the tags via nack_victim state := s_drain_rpq } when (state === s_meta_write_req && io.meta_write.ready) { state := s_meta_write_resp } when (state === s_refill_resp && refill_done) { new_coh := coh_on_grant state := s_meta_write_req } when (io.mem_acquire.fire) { // s_refill_req state := s_refill_resp } when (state === s_meta_clear && io.meta_write.ready) { state := s_refill_req } when (state === s_wb_resp && io.wb_req.ready && acked) { state := s_meta_clear } when (io.wb_req.fire) { // s_wb_req state := s_wb_resp } when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req //If we get a secondary miss that needs more permissions before we've sent // out the primary miss's Acquire, we can upgrade the permissions we're // going to ask for in s_refill_req req.cmd := dirtier_cmd when (is_hit_again) { new_coh := dirtier_coh } } when (io.req_pri_val && io.req_pri_rdy) { req := io.req_bits acked := false.B val old_coh = io.req_bits.old_meta.coh val needs_wb = old_coh.onCacheControl(M_FLUSH)._1 val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req_bits.cmd) when (io.req_bits.tag_match) { when (is_hit) { // set dirty bit new_coh := coh_on_hit state := s_meta_write_req }.otherwise { // upgrade permissions new_coh := old_coh state := s_refill_req } }.otherwise { // writback if necessary and refill new_coh := ClientMetadata.onReset state := Mux(needs_wb, s_wb_req, s_meta_clear) } } val grantackq = Module(new Queue(new TLBundleE(edge.bundle), 1)) val can_finish = state.isOneOf(s_invalid, s_refill_req) grantackq.io.enq.valid := refill_done && edge.isRequest(io.mem_grant.bits) grantackq.io.enq.bits := edge.GrantAck(io.mem_grant.bits) io.mem_finish.valid := grantackq.io.deq.valid && can_finish io.mem_finish.bits := grantackq.io.deq.bits grantackq.io.deq.ready := io.mem_finish.ready && can_finish io.idx_match := (state =/= s_invalid) && idx_match io.refill.way_en := req.way_en io.refill.addr := req_block_addr | refill_address_inc io.tag := req_tag io.req_pri_rdy := state === s_invalid io.req_sec_rdy := sec_rdy && rpq.io.enq.ready val meta_hazard = RegInit(0.U(2.W)) when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U } when (io.meta_write.fire) { meta_hazard := 1.U } io.probe_rdy := !(state =/= s_invalid && probe_idx_match) || (!state.isOneOf(states_before_refill) && meta_hazard === 0.U) io.meta_write.valid := state.isOneOf(s_meta_write_req, s_meta_clear) io.meta_write.bits.idx := req_idx io.meta_write.bits.tag := io.tag io.meta_write.bits.data.coh := Mux(state === s_meta_clear, coh_on_clear, new_coh) io.meta_write.bits.data.tag := io.tag io.meta_write.bits.way_en := req.way_en io.wb_req.valid := state === s_wb_req io.wb_req.bits.source := id.U io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.param := shrink_param io.wb_req.bits.way_en := req.way_en io.wb_req.bits.voluntary := true.B io.mem_acquire.valid := state === s_refill_req && grantackq.io.enq.ready io.mem_acquire.bits := edge.AcquireBlock( fromSource = id.U, toAddress = Cat(io.tag, req_idx) << blockOffBits, lgSize = lgCacheBlockBytes.U, growPermissions = grow_param)._2 io.replay.valid := state === s_drain_rpq && rpq.io.deq.valid io.replay.bits := rpq.io.deq.bits io.replay.bits.addr := Cat(io.tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) io.replay.bits.cmd := rpq.io.deq.bits.cmd when (state === s_drain_rpq && !rpq.io.deq.valid) { state := Mux(RegNext(!rpq.io.deq.valid), s_invalid, state) } rpq.io.deq.ready := io.replay.ready && state === s_drain_rpq } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module ShuttleDCacheMSHR_2( // @[MSHR.scala:12:7] input clock, // @[MSHR.scala:12:7] input reset, // @[MSHR.scala:12:7] input io_req_pri_val, // @[MSHR.scala:13:14] output io_req_pri_rdy, // @[MSHR.scala:13:14] input io_req_sec_val, // @[MSHR.scala:13:14] output io_req_sec_rdy, // @[MSHR.scala:13:14] input [39:0] io_req_bits_addr, // @[MSHR.scala:13:14] input [6:0] io_req_bits_tag, // @[MSHR.scala:13:14] input [4:0] io_req_bits_cmd, // @[MSHR.scala:13:14] input [1:0] io_req_bits_size, // @[MSHR.scala:13:14] input io_req_bits_signed, // @[MSHR.scala:13:14] input [63:0] io_req_bits_data, // @[MSHR.scala:13:14] input [7:0] io_req_bits_mask, // @[MSHR.scala:13:14] input io_req_bits_tag_match, // @[MSHR.scala:13:14] input [1:0] io_req_bits_old_meta_coh_state, // @[MSHR.scala:13:14] input [19:0] io_req_bits_old_meta_tag, // @[MSHR.scala:13:14] input [3:0] io_req_bits_way_en, // @[MSHR.scala:13:14] input [4:0] io_req_bits_sdq_id, // @[MSHR.scala:13:14] input [31:0] io_probe_addr, // @[MSHR.scala:13:14] output io_idx_match, // @[MSHR.scala:13:14] output [19:0] io_tag, // @[MSHR.scala:13:14] input io_mem_acquire_ready, // @[MSHR.scala:13:14] output io_mem_acquire_valid, // @[MSHR.scala:13:14] output [2:0] io_mem_acquire_bits_param, // @[MSHR.scala:13:14] output [31:0] io_mem_acquire_bits_address, // @[MSHR.scala:13:14] input io_mem_grant_valid, // @[MSHR.scala:13:14] input [2:0] io_mem_grant_bits_opcode, // @[MSHR.scala:13:14] input [1:0] io_mem_grant_bits_param, // @[MSHR.scala:13:14] input [3:0] io_mem_grant_bits_size, // @[MSHR.scala:13:14] input [2:0] io_mem_grant_bits_source, // @[MSHR.scala:13:14] input [2:0] io_mem_grant_bits_sink, // @[MSHR.scala:13:14] input io_mem_grant_bits_denied, // @[MSHR.scala:13:14] input [63:0] io_mem_grant_bits_data, // @[MSHR.scala:13:14] input io_mem_grant_bits_corrupt, // @[MSHR.scala:13:14] input io_mem_finish_ready, // @[MSHR.scala:13:14] output io_mem_finish_valid, // @[MSHR.scala:13:14] output [2:0] io_mem_finish_bits_sink, // @[MSHR.scala:13:14] output [3:0] io_refill_way_en, // @[MSHR.scala:13:14] output [11:0] io_refill_addr, // @[MSHR.scala:13:14] input io_meta_write_ready, // @[MSHR.scala:13:14] output io_meta_write_valid, // @[MSHR.scala:13:14] output [5:0] io_meta_write_bits_idx, // @[MSHR.scala:13:14] output [3:0] io_meta_write_bits_way_en, // @[MSHR.scala:13:14] output [19:0] io_meta_write_bits_tag, // @[MSHR.scala:13:14] output [1:0] io_meta_write_bits_data_coh_state, // @[MSHR.scala:13:14] output [19:0] io_meta_write_bits_data_tag, // @[MSHR.scala:13:14] input io_replay_ready, // @[MSHR.scala:13:14] output io_replay_valid, // @[MSHR.scala:13:14] output [39:0] io_replay_bits_addr, // @[MSHR.scala:13:14] output [6:0] io_replay_bits_tag, // @[MSHR.scala:13:14] output [4:0] io_replay_bits_cmd, // @[MSHR.scala:13:14] output [1:0] io_replay_bits_size, // @[MSHR.scala:13:14] output io_replay_bits_signed, // @[MSHR.scala:13:14] output [63:0] io_replay_bits_data, // @[MSHR.scala:13:14] output [7:0] io_replay_bits_mask, // @[MSHR.scala:13:14] output io_replay_bits_tag_match, // @[MSHR.scala:13:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[MSHR.scala:13:14] output [19:0] io_replay_bits_old_meta_tag, // @[MSHR.scala:13:14] output [3:0] io_replay_bits_way_en, // @[MSHR.scala:13:14] output [4:0] io_replay_bits_sdq_id, // @[MSHR.scala:13:14] input io_wb_req_ready, // @[MSHR.scala:13:14] output io_wb_req_valid, // @[MSHR.scala:13:14] output [19:0] io_wb_req_bits_tag, // @[MSHR.scala:13:14] output [5:0] io_wb_req_bits_idx, // @[MSHR.scala:13:14] output [2:0] io_wb_req_bits_param, // @[MSHR.scala:13:14] output [3:0] io_wb_req_bits_way_en, // @[MSHR.scala:13:14] output io_probe_rdy // @[MSHR.scala:13:14] ); wire [19:0] io_tag_0; // @[MSHR.scala:12:7] wire _grantackq_io_enq_ready; // @[MSHR.scala:126:25] wire _grantackq_io_deq_valid; // @[MSHR.scala:126:25] wire _rpq_io_enq_ready; // @[MSHR.scala:63:19] wire _rpq_io_deq_valid; // @[MSHR.scala:63:19] wire [39:0] _rpq_io_deq_bits_addr; // @[MSHR.scala:63:19] wire io_req_pri_val_0 = io_req_pri_val; // @[MSHR.scala:12:7] wire io_req_sec_val_0 = io_req_sec_val; // @[MSHR.scala:12:7] wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[MSHR.scala:12:7] wire [6:0] io_req_bits_tag_0 = io_req_bits_tag; // @[MSHR.scala:12:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[MSHR.scala:12:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[MSHR.scala:12:7] wire io_req_bits_signed_0 = io_req_bits_signed; // @[MSHR.scala:12:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[MSHR.scala:12:7] wire [7:0] io_req_bits_mask_0 = io_req_bits_mask; // @[MSHR.scala:12:7] wire io_req_bits_tag_match_0 = io_req_bits_tag_match; // @[MSHR.scala:12:7] wire [1:0] io_req_bits_old_meta_coh_state_0 = io_req_bits_old_meta_coh_state; // @[MSHR.scala:12:7] wire [19:0] io_req_bits_old_meta_tag_0 = io_req_bits_old_meta_tag; // @[MSHR.scala:12:7] wire [3:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[MSHR.scala:12:7] wire [4:0] io_req_bits_sdq_id_0 = io_req_bits_sdq_id; // @[MSHR.scala:12:7] wire [31:0] io_probe_addr_0 = io_probe_addr; // @[MSHR.scala:12:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[MSHR.scala:12:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[MSHR.scala:12:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[MSHR.scala:12:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[MSHR.scala:12:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[MSHR.scala:12:7] wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[MSHR.scala:12:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[MSHR.scala:12:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[MSHR.scala:12:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[MSHR.scala:12:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[MSHR.scala:12:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[MSHR.scala:12:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[MSHR.scala:12:7] wire io_replay_ready_0 = io_replay_ready; // @[MSHR.scala:12:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[MSHR.scala:12:7] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire io_wb_req_bits_voluntary = 1'h1; // @[MSHR.scala:12:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_corrupt = 1'h0; // @[MSHR.scala:12:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[MSHR.scala:12:7] wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[MSHR.scala:12:7, :13:14] wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[MSHR.scala:12:7, :13:14] wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[MSHR.scala:12:7, :13:14] wire [2:0] io_mem_acquire_bits_source = 3'h2; // @[MSHR.scala:12:7] wire [2:0] io_wb_req_bits_source = 3'h2; // @[MSHR.scala:12:7] wire [2:0] io_mem_acquire_bits_a_source = 3'h2; // @[Edges.scala:346:17] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[MSHR.scala:12:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[MSHR.scala:12:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire _io_req_pri_rdy_T; // @[MSHR.scala:138:27] wire _io_req_sec_rdy_T; // @[MSHR.scala:139:29] wire _io_idx_match_T_1; // @[MSHR.scala:134:41] wire [19:0] io_meta_write_bits_tag_0 = io_tag_0; // @[MSHR.scala:12:7] wire [19:0] io_meta_write_bits_data_tag_0 = io_tag_0; // @[MSHR.scala:12:7] wire _io_mem_acquire_valid_T_1; // @[MSHR.scala:161:50] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [2:0] grantackq_io_enq_bits_e_sink = io_mem_grant_bits_sink_0; // @[MSHR.scala:12:7] wire _io_mem_finish_valid_T; // @[MSHR.scala:130:49] wire _io_meta_write_valid_T_2; // @[package.scala:81:59] wire [5:0] req_idx; // @[MSHR.scala:39:25] wire [1:0] _io_meta_write_bits_data_coh_T_1_state; // @[MSHR.scala:149:37] wire _io_replay_valid_T_1; // @[MSHR.scala:168:44] wire _io_wb_req_valid_T; // @[MSHR.scala:153:28] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire _io_probe_rdy_T_11; // @[MSHR.scala:144:61] wire [2:0] io_mem_acquire_bits_param_0; // @[MSHR.scala:12:7] wire [31:0] io_mem_acquire_bits_address_0; // @[MSHR.scala:12:7] wire io_mem_acquire_valid_0; // @[MSHR.scala:12:7] wire [2:0] io_mem_finish_bits_sink_0; // @[MSHR.scala:12:7] wire io_mem_finish_valid_0; // @[MSHR.scala:12:7] wire [3:0] io_refill_way_en_0; // @[MSHR.scala:12:7] wire [11:0] io_refill_addr_0; // @[MSHR.scala:12:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[MSHR.scala:12:7] wire [5:0] io_meta_write_bits_idx_0; // @[MSHR.scala:12:7] wire [3:0] io_meta_write_bits_way_en_0; // @[MSHR.scala:12:7] wire io_meta_write_valid_0; // @[MSHR.scala:12:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7] wire [19:0] io_replay_bits_old_meta_tag_0; // @[MSHR.scala:12:7] wire [39:0] io_replay_bits_addr_0; // @[MSHR.scala:12:7] wire [6:0] io_replay_bits_tag_0; // @[MSHR.scala:12:7] wire [4:0] io_replay_bits_cmd_0; // @[MSHR.scala:12:7] wire [1:0] io_replay_bits_size_0; // @[MSHR.scala:12:7] wire io_replay_bits_signed_0; // @[MSHR.scala:12:7] wire [63:0] io_replay_bits_data_0; // @[MSHR.scala:12:7] wire [7:0] io_replay_bits_mask_0; // @[MSHR.scala:12:7] wire io_replay_bits_tag_match_0; // @[MSHR.scala:12:7] wire [3:0] io_replay_bits_way_en_0; // @[MSHR.scala:12:7] wire [4:0] io_replay_bits_sdq_id_0; // @[MSHR.scala:12:7] wire io_replay_valid_0; // @[MSHR.scala:12:7] wire [19:0] io_wb_req_bits_tag_0; // @[MSHR.scala:12:7] wire [5:0] io_wb_req_bits_idx_0; // @[MSHR.scala:12:7] wire [2:0] io_wb_req_bits_param_0; // @[MSHR.scala:12:7] wire [3:0] io_wb_req_bits_way_en_0; // @[MSHR.scala:12:7] wire io_wb_req_valid_0; // @[MSHR.scala:12:7] wire io_req_pri_rdy_0; // @[MSHR.scala:12:7] wire io_req_sec_rdy_0; // @[MSHR.scala:12:7] wire io_idx_match_0; // @[MSHR.scala:12:7] wire io_probe_rdy_0; // @[MSHR.scala:12:7] reg [3:0] state; // @[MSHR.scala:36:22] reg [39:0] req_addr; // @[MSHR.scala:38:16] reg [6:0] req_tag; // @[MSHR.scala:38:16] reg [4:0] req_cmd; // @[MSHR.scala:38:16] reg [1:0] req_size; // @[MSHR.scala:38:16] reg req_signed; // @[MSHR.scala:38:16] reg [63:0] req_data; // @[MSHR.scala:38:16] reg [7:0] req_mask; // @[MSHR.scala:38:16] reg req_tag_match; // @[MSHR.scala:38:16] reg [1:0] req_old_meta_coh_state; // @[MSHR.scala:38:16] reg [19:0] req_old_meta_tag; // @[MSHR.scala:38:16] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[MSHR.scala:12:7, :38:16] reg [3:0] req_way_en; // @[MSHR.scala:38:16] assign io_refill_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16] assign io_meta_write_bits_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16] assign io_wb_req_bits_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16] reg [4:0] req_sdq_id; // @[MSHR.scala:38:16] assign req_idx = req_addr[11:6]; // @[MSHR.scala:38:16, :39:25] assign io_meta_write_bits_idx_0 = req_idx; // @[MSHR.scala:12:7, :39:25] assign io_wb_req_bits_idx_0 = req_idx; // @[MSHR.scala:12:7, :39:25] wire [27:0] req_tag_0 = req_addr[39:12]; // @[MSHR.scala:38:16, :40:26] wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[MSHR.scala:38:16, :41:34] wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[MSHR.scala:41:{34,51}] wire [5:0] _idx_match_T = io_req_bits_addr_0[11:6]; // @[MSHR.scala:12:7, :42:47] wire idx_match = req_idx == _idx_match_T; // @[MSHR.scala:39:25, :42:{27,47}] wire [5:0] _probe_idx_match_T = io_probe_addr_0[11:6]; // @[MSHR.scala:12:7, :43:50] wire probe_idx_match = req_idx == _probe_idx_match_T; // @[MSHR.scala:39:25, :43:{33,50}] reg [1:0] new_coh_state; // @[MSHR.scala:45:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[MSHR.scala:38:16] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[MSHR.scala:142:59] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[MSHR.scala:142:59] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[MSHR.scala:12:7] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_cmd == 5'h1; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_cmd == 5'h11; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_cmd == 5'h7; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_cmd == 5'h4; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_cmd == 5'h9; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_cmd == 5'hA; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_cmd == 5'hB; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_cmd == 5'h8; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_cmd == 5'hC; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_cmd == 5'hD; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_cmd == 5'hE; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_cmd == 5'hF; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_cmd == 5'h3; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_cmd == 5'h6; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[MSHR.scala:45:24] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[MSHR.scala:12:7] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] wire [1:0] coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[MSHR.scala:45:24] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_bits_cmd_0 == 5'h1; // @[MSHR.scala:12:7] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_bits_cmd_0 == 5'h11; // @[MSHR.scala:12:7] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_bits_cmd_0 == 5'h7; // @[MSHR.scala:12:7] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_bits_cmd_0 == 5'h4; // @[MSHR.scala:12:7] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_bits_cmd_0 == 5'h9; // @[MSHR.scala:12:7] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_bits_cmd_0 == 5'hA; // @[MSHR.scala:12:7] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_bits_cmd_0 == 5'hB; // @[MSHR.scala:12:7] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_bits_cmd_0 == 5'h8; // @[MSHR.scala:12:7] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_bits_cmd_0 == 5'hC; // @[MSHR.scala:12:7] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_bits_cmd_0 == 5'hD; // @[MSHR.scala:12:7] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_bits_cmd_0 == 5'hE; // @[MSHR.scala:12:7] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_bits_cmd_0 == 5'hF; // @[MSHR.scala:12:7] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_bits_cmd_0 == 5'h3; // @[MSHR.scala:12:7] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _r_c_cat_T_46; // @[Consts.scala:91:54] assign _r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_bits_cmd_0 == 5'h6; // @[MSHR.scala:12:7] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[MSHR.scala:45:24] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_bits_cmd_0 : req_cmd; // @[MSHR.scala:12:7, :38:16] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[MSHR.scala:12:7] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[MSHR.scala:12:7] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & io_mem_grant_valid_0; // @[MSHR.scala:12:7] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire _GEN_27 = state == 4'h1; // @[MSHR.scala:36:22] wire _sec_rdy_T; // @[package.scala:16:47] assign _sec_rdy_T = _GEN_27; // @[package.scala:16:47] wire _io_probe_rdy_T_3; // @[package.scala:16:47] assign _io_probe_rdy_T_3 = _GEN_27; // @[package.scala:16:47] assign _io_wb_req_valid_T = _GEN_27; // @[MSHR.scala:153:28] wire _T_11 = state == 4'h2; // @[MSHR.scala:36:22] wire _sec_rdy_T_1; // @[package.scala:16:47] assign _sec_rdy_T_1 = _T_11; // @[package.scala:16:47] wire _io_probe_rdy_T_4; // @[package.scala:16:47] assign _io_probe_rdy_T_4 = _T_11; // @[package.scala:16:47] wire _T_9 = state == 4'h3; // @[MSHR.scala:36:22] wire _sec_rdy_T_2; // @[package.scala:16:47] assign _sec_rdy_T_2 = _T_9; // @[package.scala:16:47] wire _io_probe_rdy_T_5; // @[package.scala:16:47] assign _io_probe_rdy_T_5 = _T_9; // @[package.scala:16:47] wire _io_meta_write_valid_T_1; // @[package.scala:16:47] assign _io_meta_write_valid_T_1 = _T_9; // @[package.scala:16:47] wire _io_meta_write_bits_data_coh_T; // @[MSHR.scala:149:44] assign _io_meta_write_bits_data_coh_T = _T_9; // @[MSHR.scala:149:44] wire _sec_rdy_T_3 = _sec_rdy_T | _sec_rdy_T_1; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_4 = _sec_rdy_T_3 | _sec_rdy_T_2; // @[package.scala:16:47, :81:59] wire _GEN_28 = state == 4'h4; // @[MSHR.scala:36:22] wire _sec_rdy_T_5; // @[package.scala:16:47] assign _sec_rdy_T_5 = _GEN_28; // @[package.scala:16:47] wire _can_finish_T_1; // @[package.scala:16:47] assign _can_finish_T_1 = _GEN_28; // @[package.scala:16:47] wire _io_mem_acquire_valid_T; // @[MSHR.scala:161:33] assign _io_mem_acquire_valid_T = _GEN_28; // @[MSHR.scala:161:33] wire _sec_rdy_T_6 = state == 4'h5; // @[MSHR.scala:36:22] wire _sec_rdy_T_7 = _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = ~cmd_requires_second_acquire; // @[MSHR.scala:61:23] wire _sec_rdy_T_9 = _sec_rdy_T_7 & _sec_rdy_T_8; // @[MSHR.scala:60:65, :61:23] wire _sec_rdy_T_10 = ~refill_done; // @[MSHR.scala:61:55] wire _sec_rdy_T_11 = _sec_rdy_T_9 & _sec_rdy_T_10; // @[MSHR.scala:60:65, :61:{52,55}] wire _sec_rdy_T_12 = _sec_rdy_T_4 | _sec_rdy_T_11; // @[MSHR.scala:59:56, :61:52] wire sec_rdy = idx_match & _sec_rdy_T_12; // @[MSHR.scala:42:27, :58:27, :59:56] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[MSHR.scala:12:7, :64:39] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & sec_rdy; // @[MSHR.scala:12:7, :58:27, :64:75] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[MSHR.scala:64:{39,57,75}] wire _rpq_io_enq_valid_T_3 = io_req_bits_cmd_0 == 5'h2; // @[MSHR.scala:12:7] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[MSHR.scala:64:90] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[MSHR.scala:64:{57,87,90}] wire _T_19 = state == 4'h8; // @[MSHR.scala:36:22, :66:49] wire _rpq_io_deq_ready_T; // @[MSHR.scala:66:49] assign _rpq_io_deq_ready_T = _T_19; // @[MSHR.scala:66:49] wire _io_replay_valid_T; // @[MSHR.scala:168:28] assign _io_replay_valid_T = _T_19; // @[MSHR.scala:66:49, :168:28] wire _rpq_io_deq_ready_T_4; // @[MSHR.scala:176:48] assign _rpq_io_deq_ready_T_4 = _T_19; // @[MSHR.scala:66:49, :176:48] wire _rpq_io_deq_ready_T_1 = io_replay_ready_0 & _rpq_io_deq_ready_T; // @[MSHR.scala:12:7, :66:{40,49}] wire _rpq_io_deq_ready_T_2 = ~(|state); // @[MSHR.scala:36:22, :66:75] wire _rpq_io_deq_ready_T_3 = _rpq_io_deq_ready_T_1 | _rpq_io_deq_ready_T_2; // @[MSHR.scala:66:{40,66,75}] reg acked; // @[MSHR.scala:68:18] wire _io_meta_write_valid_T = state == 4'h6; // @[MSHR.scala:36:22, :78:15] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_req_bits_old_meta_coh_state_0}; // @[MSHR.scala:12:7] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[MSHR.scala:142:59] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[MSHR.scala:142:59] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, io_req_bits_old_meta_coh_state_0}; // @[MSHR.scala:12:7] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire [3:0] _state_T = {2'h0, ~needs_wb, 1'h1}; // @[MSHR.scala:122:19] wire _can_finish_T = ~(|state); // @[MSHR.scala:36:22, :66:75] wire can_finish = _can_finish_T | _can_finish_T_1; // @[package.scala:16:47, :81:59] wire _grantackq_io_enq_valid_T = io_mem_grant_bits_opcode_0[2]; // @[MSHR.scala:12:7] wire _grantackq_io_enq_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[MSHR.scala:12:7] wire _grantackq_io_enq_valid_T_2 = ~_grantackq_io_enq_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantackq_io_enq_valid_T_3 = _grantackq_io_enq_valid_T & _grantackq_io_enq_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire _grantackq_io_enq_valid_T_4 = refill_done & _grantackq_io_enq_valid_T_3; // @[MSHR.scala:128:41] assign _io_mem_finish_valid_T = _grantackq_io_deq_valid & can_finish; // @[MSHR.scala:126:25, :130:49] assign io_mem_finish_valid_0 = _io_mem_finish_valid_T; // @[MSHR.scala:12:7, :130:49] wire _grantackq_io_deq_ready_T = io_mem_finish_ready_0 & can_finish; // @[MSHR.scala:12:7, :132:49] wire _io_idx_match_T = |state; // @[MSHR.scala:36:22, :66:75, :134:26] assign _io_idx_match_T_1 = _io_idx_match_T & idx_match; // @[MSHR.scala:42:27, :134:{26,41}] assign io_idx_match_0 = _io_idx_match_T_1; // @[MSHR.scala:12:7, :134:41] wire [39:0] _io_refill_addr_T = {req_block_addr[39:12], req_block_addr[11:0] | refill_address_inc}; // @[MSHR.scala:41:51, :136:36] assign io_refill_addr_0 = _io_refill_addr_T[11:0]; // @[MSHR.scala:12:7, :136:{18,36}] assign io_tag_0 = req_tag_0[19:0]; // @[MSHR.scala:12:7, :40:26, :137:10] assign _io_req_pri_rdy_T = ~(|state); // @[MSHR.scala:36:22, :66:75, :138:27] assign io_req_pri_rdy_0 = _io_req_pri_rdy_T; // @[MSHR.scala:12:7, :138:27] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[MSHR.scala:58:27, :63:19, :139:29] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[MSHR.scala:12:7, :139:29] reg [1:0] meta_hazard; // @[MSHR.scala:141:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[MSHR.scala:141:28, :142:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[MSHR.scala:142:59] wire _io_probe_rdy_T = |state; // @[MSHR.scala:36:22, :66:75, :144:27] wire _io_probe_rdy_T_1 = _io_probe_rdy_T & probe_idx_match; // @[MSHR.scala:43:33, :144:{27,41}] wire _io_probe_rdy_T_2 = ~_io_probe_rdy_T_1; // @[MSHR.scala:144:{19,41}] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_3 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_5; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = ~_io_probe_rdy_T_7; // @[MSHR.scala:144:65] wire _io_probe_rdy_T_9 = meta_hazard == 2'h0; // @[MSHR.scala:141:28, :144:117] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_8 & _io_probe_rdy_T_9; // @[MSHR.scala:144:{65,102,117}] assign _io_probe_rdy_T_11 = _io_probe_rdy_T_2 | _io_probe_rdy_T_10; // @[MSHR.scala:144:{19,61,102}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[MSHR.scala:12:7, :144:61] assign _io_meta_write_valid_T_2 = _io_meta_write_valid_T | _io_meta_write_valid_T_1; // @[package.scala:16:47, :81:59] assign io_meta_write_valid_0 = _io_meta_write_valid_T_2; // @[MSHR.scala:12:7] assign _io_meta_write_bits_data_coh_T_1_state = _io_meta_write_bits_data_coh_T ? coh_on_clear_state : new_coh_state; // @[MSHR.scala:45:24, :149:{37,44}] assign io_meta_write_bits_data_coh_state_0 = _io_meta_write_bits_data_coh_T_1_state; // @[MSHR.scala:12:7, :149:37] assign io_wb_req_valid_0 = _io_wb_req_valid_T; // @[MSHR.scala:12:7, :153:28] assign _io_mem_acquire_valid_T_1 = _io_mem_acquire_valid_T & _grantackq_io_enq_ready; // @[MSHR.scala:126:25, :161:{33,50}] assign io_mem_acquire_valid_0 = _io_mem_acquire_valid_T_1; // @[MSHR.scala:12:7, :161:50] wire [25:0] _GEN_29 = {io_tag_0, req_idx}; // @[MSHR.scala:12:7, :39:25, :164:48] wire [25:0] _io_mem_acquire_bits_T; // @[MSHR.scala:164:48] assign _io_mem_acquire_bits_T = _GEN_29; // @[MSHR.scala:164:48] wire [25:0] io_replay_bits_addr_hi; // @[MSHR.scala:170:29] assign io_replay_bits_addr_hi = _GEN_29; // @[MSHR.scala:164:48, :170:29] wire [31:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[MSHR.scala:41:51, :164:{48,66}] wire [31:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[MSHR.scala:164:66] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[31:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 | _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 | _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42] wire [31:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_26 = _io_mem_acquire_bits_T_1 ^ 32'h80000000; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 | _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[MSHR.scala:164:66] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[MSHR.scala:164:66] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[MSHR.scala:164:66] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] assign _io_replay_valid_T_1 = _io_replay_valid_T & _rpq_io_deq_valid; // @[MSHR.scala:63:19, :168:{28,44}] assign io_replay_valid_0 = _io_replay_valid_T_1; // @[MSHR.scala:12:7, :168:44] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[MSHR.scala:63:19, :170:67] wire [31:0] _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[MSHR.scala:170:{29,67}] assign io_replay_bits_addr_0 = {8'h0, _io_replay_bits_addr_T_1}; // @[MSHR.scala:12:7, :170:{23,29}] wire _state_T_1 = ~_rpq_io_deq_valid; // @[MSHR.scala:63:19, :71:34, :174:26] reg state_REG; // @[MSHR.scala:174:25] wire [3:0] _state_T_2 = state_REG ? 4'h0 : state; // @[MSHR.scala:36:22, :174:{17,25}] wire _rpq_io_deq_ready_T_5 = io_replay_ready_0 & _rpq_io_deq_ready_T_4; // @[MSHR.scala:12:7, :176:{39,48}] wire _T_7 = _sec_rdy_T_6 & refill_done; // @[MSHR.scala:81:33] wire _T_15 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[MSHR.scala:12:7, :97:24] always @(posedge clock) begin // @[MSHR.scala:12:7] if (reset) begin // @[MSHR.scala:12:7] state <= 4'h0; // @[MSHR.scala:36:22] new_coh_state <= 2'h0; // @[MSHR.scala:45:24] r_counter <= 9'h0; // @[Edges.scala:229:27] meta_hazard <= 2'h0; // @[MSHR.scala:141:28] end else begin // @[MSHR.scala:12:7] if (_T_19 & ~_rpq_io_deq_valid) // @[MSHR.scala:63:19, :66:49, :71:34, :173:31] state <= _state_T_2; // @[MSHR.scala:36:22, :174:17] else if (_rpq_io_enq_valid_T) // @[MSHR.scala:64:39] state <= io_req_bits_tag_match_0 ? {2'h1, is_hit, 1'h0} : _state_T; // @[MSHR.scala:12:7, :36:22, :112:34, :113:21, :115:15, :118:15, :122:{13,19}] else if (io_wb_req_ready_0 & io_wb_req_valid_0) // @[Decoupled.scala:51:35] state <= 4'h2; // @[MSHR.scala:36:22] else if (_T_11 & io_wb_req_ready_0 & acked) // @[MSHR.scala:12:7, :68:18, :91:{29,48}] state <= 4'h3; // @[MSHR.scala:36:22] else if (_T_9 & io_meta_write_ready_0) // @[MSHR.scala:12:7, :88:32] state <= 4'h4; // @[MSHR.scala:36:22] else if (io_mem_acquire_ready_0 & io_mem_acquire_valid_0) // @[Decoupled.scala:51:35] state <= 4'h5; // @[MSHR.scala:36:22] else if (_T_7) // @[MSHR.scala:81:33] state <= 4'h6; // @[MSHR.scala:36:22] else if (_io_meta_write_valid_T & io_meta_write_ready_0) // @[MSHR.scala:12:7, :78:36] state <= 4'h7; // @[MSHR.scala:36:22] else if (state == 4'h7) // @[MSHR.scala:36:22, :74:15] state <= 4'h8; // @[MSHR.scala:36:22] else if (_T_19 & ~_rpq_io_deq_valid) // @[MSHR.scala:63:19, :66:49, :71:{31,34}] state <= 4'h0; // @[MSHR.scala:36:22] if (_rpq_io_enq_valid_T) // @[MSHR.scala:64:39] new_coh_state <= io_req_bits_tag_match_0 ? (is_hit ? coh_on_hit_state : io_req_bits_old_meta_coh_state_0) : 2'h0; // @[MSHR.scala:12:7, :45:24, :112:34, :113:21, :114:17, :117:17, :121:15] else if (_T_15 & is_hit_again) // @[MSHR.scala:81:49, :97:{24,43}, :102:25, :103:15] new_coh_state <= dirtier_coh_state; // @[MSHR.scala:45:24] else if (_T_7) // @[MSHR.scala:81:33] new_coh_state <= coh_on_grant_state; // @[MSHR.scala:45:24] if (io_mem_grant_valid_0) // @[MSHR.scala:12:7] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (io_meta_write_ready_0 & io_meta_write_valid_0) // @[Decoupled.scala:51:35] meta_hazard <= 2'h1; // @[MSHR.scala:141:28] else if (|meta_hazard) // @[MSHR.scala:141:28, :142:21] meta_hazard <= _meta_hazard_T_1; // @[MSHR.scala:141:28, :142:59] end if (_rpq_io_enq_valid_T) begin // @[MSHR.scala:64:39] req_addr <= io_req_bits_addr_0; // @[MSHR.scala:12:7, :38:16] req_tag <= io_req_bits_tag_0; // @[MSHR.scala:12:7, :38:16] req_cmd <= io_req_bits_cmd_0; // @[MSHR.scala:12:7, :38:16] req_size <= io_req_bits_size_0; // @[MSHR.scala:12:7, :38:16] req_signed <= io_req_bits_signed_0; // @[MSHR.scala:12:7, :38:16] req_data <= io_req_bits_data_0; // @[MSHR.scala:12:7, :38:16] req_mask <= io_req_bits_mask_0; // @[MSHR.scala:12:7, :38:16] req_tag_match <= io_req_bits_tag_match_0; // @[MSHR.scala:12:7, :38:16] req_old_meta_coh_state <= io_req_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7, :38:16] req_old_meta_tag <= io_req_bits_old_meta_tag_0; // @[MSHR.scala:12:7, :38:16] req_way_en <= io_req_bits_way_en_0; // @[MSHR.scala:12:7, :38:16] req_sdq_id <= io_req_bits_sdq_id_0; // @[MSHR.scala:12:7, :38:16] end else if (_T_15) // @[MSHR.scala:97:24] req_cmd <= dirtier_cmd; // @[MSHR.scala:38:16] acked <= ~_rpq_io_enq_valid_T & (io_mem_grant_valid_0 | acked); // @[MSHR.scala:12:7, :64:39, :68:18, :69:{29,37}, :106:43, :108:11] state_REG <= _state_T_1; // @[MSHR.scala:174:{25,26}] always @(posedge) Queue16_ShuttleMSHRReq_2 rpq ( // @[MSHR.scala:63:19] .clock (clock), .reset (reset), .io_enq_ready (_rpq_io_enq_ready), .io_enq_valid (_rpq_io_enq_valid_T_7), // @[MSHR.scala:64:87] .io_enq_bits_addr (io_req_bits_addr_0), // @[MSHR.scala:12:7] .io_enq_bits_tag (io_req_bits_tag_0), // @[MSHR.scala:12:7] .io_enq_bits_cmd (io_req_bits_cmd_0), // @[MSHR.scala:12:7] .io_enq_bits_size (io_req_bits_size_0), // @[MSHR.scala:12:7] .io_enq_bits_signed (io_req_bits_signed_0), // @[MSHR.scala:12:7] .io_enq_bits_data (io_req_bits_data_0), // @[MSHR.scala:12:7] .io_enq_bits_mask (io_req_bits_mask_0), // @[MSHR.scala:12:7] .io_enq_bits_tag_match (io_req_bits_tag_match_0), // @[MSHR.scala:12:7] .io_enq_bits_old_meta_coh_state (io_req_bits_old_meta_coh_state_0), // @[MSHR.scala:12:7] .io_enq_bits_old_meta_tag (io_req_bits_old_meta_tag_0), // @[MSHR.scala:12:7] .io_enq_bits_way_en (io_req_bits_way_en_0), // @[MSHR.scala:12:7] .io_enq_bits_sdq_id (io_req_bits_sdq_id_0), // @[MSHR.scala:12:7] .io_deq_ready (_rpq_io_deq_ready_T_5), // @[MSHR.scala:176:39] .io_deq_valid (_rpq_io_deq_valid), .io_deq_bits_addr (_rpq_io_deq_bits_addr), .io_deq_bits_tag (io_replay_bits_tag_0), .io_deq_bits_cmd (io_replay_bits_cmd_0), .io_deq_bits_size (io_replay_bits_size_0), .io_deq_bits_signed (io_replay_bits_signed_0), .io_deq_bits_data (io_replay_bits_data_0), .io_deq_bits_mask (io_replay_bits_mask_0), .io_deq_bits_tag_match (io_replay_bits_tag_match_0), .io_deq_bits_old_meta_coh_state (io_replay_bits_old_meta_coh_state_0), .io_deq_bits_old_meta_tag (io_replay_bits_old_meta_tag_0), .io_deq_bits_way_en (io_replay_bits_way_en_0), .io_deq_bits_sdq_id (io_replay_bits_sdq_id_0) ); // @[MSHR.scala:63:19] Queue1_TLBundleE_a32d64s3k3z4c_2 grantackq ( // @[MSHR.scala:126:25] .clock (clock), .reset (reset), .io_enq_ready (_grantackq_io_enq_ready), .io_enq_valid (_grantackq_io_enq_valid_T_4), // @[MSHR.scala:128:41] .io_enq_bits_sink (grantackq_io_enq_bits_e_sink), // @[Edges.scala:451:17] .io_deq_ready (_grantackq_io_deq_ready_T), // @[MSHR.scala:132:49] .io_deq_valid (_grantackq_io_deq_valid), .io_deq_bits_sink (io_mem_finish_bits_sink_0) ); // @[MSHR.scala:126:25] assign io_req_pri_rdy = io_req_pri_rdy_0; // @[MSHR.scala:12:7] assign io_req_sec_rdy = io_req_sec_rdy_0; // @[MSHR.scala:12:7] assign io_idx_match = io_idx_match_0; // @[MSHR.scala:12:7] assign io_tag = io_tag_0; // @[MSHR.scala:12:7] assign io_mem_acquire_valid = io_mem_acquire_valid_0; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_param = io_mem_acquire_bits_param_0; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_address = io_mem_acquire_bits_address_0; // @[MSHR.scala:12:7] assign io_mem_finish_valid = io_mem_finish_valid_0; // @[MSHR.scala:12:7] assign io_mem_finish_bits_sink = io_mem_finish_bits_sink_0; // @[MSHR.scala:12:7] assign io_refill_way_en = io_refill_way_en_0; // @[MSHR.scala:12:7] assign io_refill_addr = io_refill_addr_0; // @[MSHR.scala:12:7] assign io_meta_write_valid = io_meta_write_valid_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_idx = io_meta_write_bits_idx_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_way_en = io_meta_write_bits_way_en_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_tag = io_meta_write_bits_tag_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_data_coh_state = io_meta_write_bits_data_coh_state_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_data_tag = io_meta_write_bits_data_tag_0; // @[MSHR.scala:12:7] assign io_replay_valid = io_replay_valid_0; // @[MSHR.scala:12:7] assign io_replay_bits_addr = io_replay_bits_addr_0; // @[MSHR.scala:12:7] assign io_replay_bits_tag = io_replay_bits_tag_0; // @[MSHR.scala:12:7] assign io_replay_bits_cmd = io_replay_bits_cmd_0; // @[MSHR.scala:12:7] assign io_replay_bits_size = io_replay_bits_size_0; // @[MSHR.scala:12:7] assign io_replay_bits_signed = io_replay_bits_signed_0; // @[MSHR.scala:12:7] assign io_replay_bits_data = io_replay_bits_data_0; // @[MSHR.scala:12:7] assign io_replay_bits_mask = io_replay_bits_mask_0; // @[MSHR.scala:12:7] assign io_replay_bits_tag_match = io_replay_bits_tag_match_0; // @[MSHR.scala:12:7] assign io_replay_bits_old_meta_coh_state = io_replay_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7] assign io_replay_bits_old_meta_tag = io_replay_bits_old_meta_tag_0; // @[MSHR.scala:12:7] assign io_replay_bits_way_en = io_replay_bits_way_en_0; // @[MSHR.scala:12:7] assign io_replay_bits_sdq_id = io_replay_bits_sdq_id_0; // @[MSHR.scala:12:7] assign io_wb_req_valid = io_wb_req_valid_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_tag = io_wb_req_bits_tag_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_idx = io_wb_req_bits_idx_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_param = io_wb_req_bits_param_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_way_en = io_wb_req_bits_way_en_0; // @[MSHR.scala:12:7] assign io_probe_rdy = io_probe_rdy_0; // @[MSHR.scala:12:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLBuffer_a32d64s6k3z3c( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_e_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_out_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeIn_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_e_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_in_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [63:0] auto_in_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [63:0] auto_out_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [63:0] nodeIn_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [7:0] auto_in_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [7:0] nodeIn_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [5:0] auto_in_b_bits_source = 6'h10; // @[Nodes.scala:27:25] wire [5:0] auto_out_b_bits_source = 6'h10; // @[Nodes.scala:27:25] wire [5:0] nodeIn_b_bits_source = 6'h10; // @[Nodes.scala:27:25] wire [5:0] nodeOut_b_bits_source = 6'h10; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_out_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeIn_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeOut_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign nodeOut_c_valid = nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_opcode = nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_param = nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_size = nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_source = nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_address = nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_data = nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_corrupt = nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign nodeOut_e_valid = nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_e_bits_sink = nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_param = nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_address = nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_c_ready = nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_41 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a32d64s6k3z3c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a32d64s6k3z3c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Debug.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBFanout, APBToTL} import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule} import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError} import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode} import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.rocket.{CSRs, Instructions} import freechips.rocketchip.tile.MaxHartIdBits import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar} import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle} import freechips.rocketchip.util.SeqBoolBitwiseOps import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.BooleanToAugmentedBoolean object DsbBusConsts { def sbAddrWidth = 12 def sbIdWidth = 10 } object DsbRegAddrs{ // These are used by the ROM. def HALTED = 0x100 def GOING = 0x104 def RESUMING = 0x108 def EXCEPTION = 0x10C def WHERETO = 0x300 // This needs to be aligned for up to lq/sq // This shows up in HartInfo, and needs to be aligned // to enable up to LQ/SQ instructions. def DATA = 0x380 // We want DATA to immediately follow PROGBUF so that we can // use them interchangeably. Leave another slot if there is an // implicit ebreak. def PROGBUF(cfg:DebugModuleParams) = { val tmp = DATA - (cfg.nProgramBufferWords * 4) if (cfg.hasImplicitEbreak) (tmp - 4) else tmp } // This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF. def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 } // We want abstract to be immediately before PROGBUF // because we auto-generate 2 (or 5) instructions. def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4) def FLAGS = 0x400 def ROMBASE = 0x800 } /** Enumerations used both in the hardware * and in the configuration specification. */ object DebugModuleAccessType extends scala.Enumeration { type DebugModuleAccessType = Value val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value } object DebugAbstractCommandError extends scala.Enumeration { type DebugAbstractCommandError = Value val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value } object DebugAbstractCommandType extends scala.Enumeration { type DebugAbstractCommandType = Value val AccessRegister, QuickAccess = Value } /** Parameters exposed to the top-level design, set based on * external requirements, etc. * * This object checks that the parameters conform to the * full specification. The implementation which receives this * object can perform more checks on what that implementation * actually supports. * @param nComponents Number of components to support debugging. * @param baseAddress Base offest for debugEntry and debugException * @param nDMIAddrSize Size of the Debug Bus Address * @param nAbstractDataWords Number of 32-bit words for Abstract Commands * @param nProgamBufferWords Number of 32-bit words for Program Buffer * @param hasBusMaster Whether or not a bus master should be included * @param clockGate Whether or not to use dmactive as the clockgate for debug module * @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic. * @param supportQuickAccess Whether or not to support the quick access command. * @param supportHartArray Whether or not to implement the hart array register (if >1 hart). * @param nHaltGroups Number of halt groups * @param nExtTriggers Number of external triggers * @param hasHartResets Feature to reset all the currently selected harts * @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak * @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset. */ case class DebugModuleParams ( baseAddress : BigInt = BigInt(0), nDMIAddrSize : Int = 7, nProgramBufferWords: Int = 16, nAbstractDataWords : Int = 4, nScratch : Int = 1, hasBusMaster : Boolean = false, clockGate : Boolean = true, maxSupportedSBAccess : Int = 32, supportQuickAccess : Boolean = false, supportHartArray : Boolean = true, nHaltGroups : Int = 1, nExtTriggers : Int = 0, hasHartResets : Boolean = false, hasImplicitEbreak : Boolean = false, hasAuthentication : Boolean = false, crossingHasSafeReset : Boolean = true ) { require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}") require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}") require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}") require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}") require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}") if (supportQuickAccess) { // TODO: Check that quick access requirements are met. } def address = AddressSet(baseAddress, 0xFFF) /** the base address of DM */ def atzero = (baseAddress == 0) /** The number of generated instructions * * When the base address is not zero, we need more instruction also, * more dscratch registers) to load/store memory mapped data register * because they may no longer be directly addressible with x0 + 12-bit imm */ def nAbstractInstructions = if (atzero) 2 else 5 def debugEntry: BigInt = baseAddress + 0x800 def debugException: BigInt = baseAddress + 0x808 def nDscratch: Int = if (atzero) 1 else 2 } object DefaultDebugModuleParams { def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = { new DebugModuleParams().copy( nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4), maxSupportedSBAccess = xlen ) } } case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams())) /** Functional parameters exposed to the design configuration. * * hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping. * hartSelToHartId: Provide inverse mapping of the above */ case class DebugModuleHartSelFuncs ( hartIdToHartSel : (UInt) => UInt = (x:UInt) => x, hartSelToHartId : (UInt) => UInt = (x:UInt) => x ) case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs()) class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle { val req = Output(UInt(nExtTriggers.W)) val ack = Input(UInt(nExtTriggers.W)) } class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle { val req = Input(UInt(nExtTriggers.W)) val ack = Output(UInt(nExtTriggers.W)) } class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers) val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers) } class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val dmactive = Output(Bool()) val dmAuthWrite = Output(Bool()) val dmAuthRead = Output(Bool()) val dmAuthWdata = Output(UInt(32.W)) val dmAuthBusy = Input(Bool()) val dmAuthRdata = Input(UInt(32.W)) val dmAuthenticated = Input(Bool()) } // ***************************************** // Module Interfaces // // ***************************************** /** Control signals for Inner, generated in Outer * {{{ * run control: resumreq, ackhavereset, halt-on-reset mask * hart select: hasel, hartsel and the hart array mask * }}} */ class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /** resume request */ val resumereq = Bool() /** hart select */ val hartsel = UInt(10.W) /** reset acknowledge */ val ackhavereset = Bool() /** hart array enable */ val hasel = Bool() /** hart array mask */ val hamask = Vec(nComponents, Bool()) /** halt-on-reset mask */ val hrmask = Vec(nComponents, Bool()) } /** structure for top-level Debug Module signals which aren't the bus interfaces. */ class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /** debug availability status for all harts */ val debugUnavail = Input(Vec(nComponents, Bool())) /** reset signal * * for every part of the hardware platform, * including every hart, except for the DM and any * logic required to access the DM */ val ndreset = Output(Bool()) /** reset signal for the DM itself */ val dmactive = Output(Bool()) /** dmactive acknowlege */ val dmactiveAck = Input(Bool()) } // ***************************************** // Debug Module // // ***************************************** /** Parameterized version of the Debug Module defined in the * RISC-V Debug Specification * * DebugModule is a slave to two asynchronous masters: * The Debug Bus (DMI) -- This is driven by an external debugger * * The System Bus -- This services requests from the cores. Generally * this interface should only be active at the request * of the debugger, but the Debug Module may also * provide the default MTVEC since it is mapped * to address 0x0. * * DebugModule is responsible for control registers and RAM, and * Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and * the TL clock. Therefore, it is divided into "Outer" portion (running * off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset). * This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive, * and ndreset to be modified even while the Core is in reset or not being clocked. * Not all reads from the Debugger to the Debug Module will actually complete * in these scenarios either, they will just block until tl_clock and tl_reset * allow them to complete. This is not strictly necessary for * proper debugger functionality. */ // Local reg mapper function : Notify when written, but give the value as well. object WNotifyWire { def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = { RegField(n, 0.U, RegWriteFn((valid, data) => { set := valid value := data true.B }), Some(RegFieldDesc(name = name, desc = desc, access = RegFieldAccessType.W))) } } // Local reg mapper function : Notify when accessed either as read or write. object RWNotify { def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = { RegField(n, RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}), RegWriteFn((valid, data) => { wNotify := valid when (valid) {wVal := data} true.B } ), desc) } } // Local reg mapper function : Notify with value when written, take read input as presented. // This allows checking or correcting the write value before storing it in the register field. object WNotifyVal { def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = { RegField(n, rVal, RegWriteFn((valid, data) => { wNotify := valid wVal := data true.B } ), desc) } } class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get val intnode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) val dmiNode = TLRegisterNode ( address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++ AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOW << 2, 4), device = device, beatBytes = 4, executable = false ) lazy val module = new Impl class Impl extends LazyModuleImp(this) { require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts") val nComponents = intnode.out.size def getNComponents = () => nComponents val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart val io = IO(new Bundle { /** structure for top-level Debug Module signals which aren't the bus interfaces. */ val ctrl = (new DebugCtrlBundle(nComponents)) /** control signals for Inner, generated in Outer */ val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents)) /** debug interruption from Inner to Outer * * contains 2 type of debug interruption causes: * - halt group * - halt-on-reset */ val hgDebugInt = Input(Vec(nComponents, Bool())) /** hart reset request to core */ val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** authentication support */ val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool())) }) val omRegMap = withReset(reset.asAsyncReset) { // FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available) val dmAuthenticated = io.dmAuthenticated.map( dma => ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B) //----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it // can be written even if 'Inner' is not being clocked or is in reset. This allows halting // harts while the rest of the system is in reset. It doesn't really allow any other // register accesses, which will keep returning 'busy' to the debugger interface. val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg") val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val dmactiveWrEn = WireInit(false.B) val ndmresetWrEn = WireInit(false.B) val clrresethaltreqWrEn = WireInit(false.B) val setresethaltreqWrEn = WireInit(false.B) val hartselloWrEn = WireInit(false.B) val haselWrEn = WireInit(false.B) val ackhaveresetWrEn = WireInit(false.B) val hartresetWrEn = WireInit(false.B) val resumereqWrEn = WireInit(false.B) val haltreqWrEn = WireInit(false.B) val dmactive = DMCONTROLReg.dmactive DMCONTROLNxt := DMCONTROLReg when (~dmactive) { DMCONTROLNxt := DMCONTROLReset } .otherwise { when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset } when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask} when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel } when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset } when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq } } // Put this last to override its own effects. when (dmactiveWrEn) { DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive } //----HARTINFO // DATA registers are mapped to memory. The dataaddr field of HARTINFO has only // 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0 // (implying nonexistence according to the Debug Spec). val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields())) if (cfg.atzero) when (dmAuthenticated) { HARTINFORdData.dataaccess := true.B HARTINFORdData.datasize := cfg.nAbstractDataWords.U HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U HARTINFORdData.nscratch := cfg.nScratch.U } //-------------------------------------------------------------- // Hart array mask and window // hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello // HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW //-------------------------------------------------------------- val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) def haWindowSize = 32 // The following need to be declared even if supportHartArray is false due to reference // at compile time by dmiNode.regmap val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELWrEn = WireInit(false.B) val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrEn = WireInit(false.B) /** whether the hart is selected */ def hartSelected(hart: Int): Bool = { ((io.innerCtrl.bits.hartsel === hart.U) || (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B)) } val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt)) if (supportHartArray) { val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) HAWINDOWSELNxt := HAWINDOWSELReg when (~dmactive || ~dmAuthenticated) { HAWINDOWSELNxt := HAWINDOWSELReset } .otherwise { when (HAWINDOWSELWrEn) { // Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window if (nComponents > haWindowSize) { HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U } else { HAWINDOWSELNxt.hawindowsel := 0.U } } } val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1 HAWINDOWRdData.maskdata := 0.U // default, overridden below // for each slice,use a hamaskReg to store the selection info for (ii <- 0 until numHAMASKSlices) { val sliceMask = if (nComponents > ((ii*haWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist else (BigInt(1)<<(nComponents - (ii*haWindowSize))) - 1 // Partial last slice val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt)) when (ii.U === HAWINDOWSELReg.hawindowsel) { HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U } HAMASKNxt.maskdata := HAMASKReg.asUInt when (~dmactive || ~dmAuthenticated) { HAMASKNxt := HAMASKRst }.otherwise { when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { HAMASKNxt.maskdata := HAWINDOWWrData.maskdata } } // drive each slice of hamask with stored HAMASKReg or with new value being written for (jj <- 0 until haWindowSize) { if (((ii*haWindowSize) + jj) < nComponents) { val tempWrData = HAWINDOWWrData.maskdata.asBools val tempMaskReg = HAMASKReg.asUInt.asBools when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { hamask(ii*haWindowSize + jj) := tempWrData(jj) }.otherwise { hamask(ii*haWindowSize + jj) := tempMaskReg(jj) } } } } } //-------------------------------------------------------------- // Halt-on-reset // hrmaskReg is current set of harts that should halt-on-reset // Reset state (dmactive=0) is all zeroes // Bits are set by writing 1 to DMCONTROL.setresethaltreq // Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq // Spec says if both are 1, then clrresethaltreq is executed // hrmask is the halt-on-reset mask which will be sent to inner //-------------------------------------------------------------- val hrmask = Wire(Vec(nComponents, Bool())) val hrmaskNxt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg") hrmaskNxt := hrmaskReg for (component <- 0 until nComponents) { when (~dmactive || ~dmAuthenticated) { hrmaskNxt(component) := false.B }.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) { hrmaskNxt(component) := false.B }.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) { hrmaskNxt(component) := true.B } } hrmask := hrmaskNxt val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq( WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn, RegFieldDesc("dmactive", "debug module active", reset=Some(0))), WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn, RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))), WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn, RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn, RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)), RegField(12), if (nComponents > 1) WNotifyVal(p(MaxHartIdBits), DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn, RegFieldDesc("hartsello", "hart select low", reset=Some(0))) else RegField(1), if (nComponents > 1) RegField(10-p(MaxHartIdBits)) else RegField(9), if (supportHartArray) WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn, RegFieldDesc("hasel", "hart array select", reset=Some(0))) else RegField(1), RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn, RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)), if (cfg.hasHartResets) WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn, RegFieldDesc("hartreset", "hart reset request", reset=Some(0))) else RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn, RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior RegFieldDesc("haltreq", "halt request", reset=Some(0))) )) val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq( RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))), RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))), RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))), RegField(3), RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0))) )) //-------------------------------------------------------------- // DMI register decoder for Outer //-------------------------------------------------------------- // regmap addresses are byte offsets from lowest address def DMI_DMCONTROL_OFFSET = 0 def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2) def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2) def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2) val omRegMap = dmiNode.regmap( DMI_DMCONTROL_OFFSET -> dmControlRegFields, DMI_HARTINFO_OFFSET -> hartinfoRegFields, DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq( WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn, RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil), DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq( WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn, RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil) ) //-------------------------------------------------------------- // Interrupt Registers //-------------------------------------------------------------- val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs") debugIntNxt := debugIntRegs val (intnode_out, _) = intnode.out.unzip for (component <- 0 until nComponents) { intnode_out(component)(0) := debugIntRegs(component) | io.hgDebugInt(component) } // sends debug interruption to Core when dmcs.haltreq is set, for (component <- 0 until nComponents) { when (~dmactive || ~dmAuthenticated) { debugIntNxt(component) := false.B }. otherwise { when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U) || (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) { debugIntNxt(component) := DMCONTROLWrData.haltreq } } } // Halt request registers are set & cleared by writes to DMCONTROL.haltreq // resumereq also causes the core to execute a 'dret', // so resumereq is passed through to Inner. // hartsel/hasel/hamask must also be used by the DebugModule state machine, // so it is passed to Inner. // These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together. // If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received. // Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent. // Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received. val innerCtrlValid = Wire(Bool()) val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg") val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg") val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg") innerCtrlValid := hartselloWrEn | resumereqWrEn | ackhaveresetWrEn | setresethaltreqWrEn | clrresethaltreqWrEn | haselWrEn | (HAWINDOWWrEn & supportHartArray.B) innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted io.innerCtrl.valid := innerCtrlValid | innerCtrlValidReg io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello) io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) | innerCtrlResumeReqReg io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) | innerCtrlAckHaveResetReg io.innerCtrl.bits.hrmask := hrmask if (supportHartArray) { io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel) io.innerCtrl.bits.hamask := hamask } else { io.innerCtrl.bits.hasel := DontCare io.innerCtrl.bits.hamask := DontCare } io.ctrl.ndreset := DMCONTROLReg.ndmreset io.ctrl.dmactive := DMCONTROLReg.dmactive // hart reset mechanism implementation if (cfg.hasHartResets) { val hartResetNxt = Wire(Vec(nComponents, Bool())) val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt)) for (component <- 0 until nComponents) { hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component) io.hartResetReq.get(component) := hartResetReg(component) } } omRegMap // FIXME: Remove this when withReset is removed }} } // wrap a Outer with a DMIToTL, derived by dmi clock & reset class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar"))) val dmi2tlOpt = (!p(ExportDebug).apb).option({ val dmi2tl = LazyModule(new DMIToTL()) dmiXbar.node := dmi2tl.node dmi2tl }) val apbNodeOpt = p(ExportDebug).apb.option({ val apb2tl = LazyModule(new APBToTL()) val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe)) val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4) val tlError = LazyModule(new TLError(tlErrorParams, buffer=false)) val apbXbar = LazyModule(new APBFanout()) val apbRegs = LazyModule(new APBDebugRegisters()) apbRegs.node := apbXbar.node apb2tl.node := apbXbar.node apb2tlBuffer.node := apb2tl.node dmiXbar.node := apb2tlBuffer.node tlError.node := dmiXbar.node apbXbar.node }) val dmOuter = LazyModule( new TLDebugModuleOuter(device)) val intnode = IntSyncIdentityNode() intnode :*= IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4)) val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node dmOuter.dmiNode := dmiXbar.node lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.intnode.edges.out.size val io = IO(new Bundle { val dmi_clock = Input(Clock()) val dmi_reset = Input(Reset()) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI */ val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p))) // Optional APB Interface is fully diplomatic so is not listed here. val ctrl = new DebugCtrlBundle(nComponents) /** conrol signals for Inner, generated in Outer */ val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) /** debug interruption generated in Inner */ val hgDebugInt = Input(Vec(nComponents, Bool())) /** hart reset request to core */ val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** Authentication signal from core */ val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool())) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.dmi_clock childReset := io.dmi_reset override def provideImplicitClockToLazyChildren = true withClockAndReset(childClock, childReset) { dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get } val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync")) dmiBypass.module.io.bypass := ~io.ctrl.dmactive | ~dmactiveAck io.ctrl <> dmOuter.module.io.ctrl dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) dmOuter.module.io.hgDebugInt := io.hgDebugInt io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}} } } } class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get def getCfg = () => cfg val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 /** dmiNode address set */ val dmiNode = TLRegisterNode( // Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++ AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++ AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++ AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))), device = device, beatBytes = 4, executable = false ) val tlNode = TLRegisterNode( address=Seq(cfg.address), device=device, beatBytes=beatBytes, executable=true ) val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL())) // If we want to support custom registers read through Abstract Commands, // provide a place to bring them into the debug module. What this connects // to is up to the implementation. val customNode = new DebugCustomSink() lazy val module = new Impl class Impl extends LazyModuleImp(this){ val nComponents = getNComponents() Annotated.params(this, cfg) val supportHartArray = cfg.supportHartArray & (nComponents > 1) val nExtTriggers = cfg.nExtTriggers val nHaltGroups = if ((nComponents > 1) | (nExtTriggers > 0)) cfg.nHaltGroups else 0 // no halt groups possible if single hart with no external triggers val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs( hartIdToHartSel = (x) => 0.U, hartSelToHartId = (x) => x ) val io = IO(new Bundle { /** dm reset signal passed in from Outer */ val dmactive = Input(Bool()) /** conrol signals for Inner * * it's generated by Outer and comes in */ val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents))) /** debug unavail signal passed in from Outer*/ val debugUnavail = Input(Vec(nComponents, Bool())) /** debug interruption from Inner to Outer * * contain 2 type of debug interruption causes: * - halt group * - halt-on-reset */ val hgDebugInt = Output(Vec(nComponents, Bool())) /** interface for trigger */ val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(nComponents, Bool())) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /** Debug Authentication signals from core */ val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO()) }) sb2tlOpt.map { sb => sb.module.clock := io.tl_clock sb.module.reset := io.tl_reset sb.module.rf_reset := io.tl_reset } //-------------------------------------------------------------- // Import constants for shorter variable names //-------------------------------------------------------------- import DMI_RegAddrs._ import DsbRegAddrs._ import DsbBusConsts._ //-------------------------------------------------------------- // Sanity Check Configuration For this implementation. //-------------------------------------------------------------- require (cfg.supportQuickAccess == false, "No Quick Access support yet") require ((nHaltGroups > 0) || (nExtTriggers == 0), "External triggers require at least 1 halt group") //-------------------------------------------------------------- // Register & Wire Declarations (which need to be pre-declared) //-------------------------------------------------------------- // run control regs: tracking all the harts // implements: see implementation-specific bits part /** all harts halted status */ val haltedBitRegs = Reg(UInt(nComponents.W)) /** all harts resume request status */ val resumeReqRegs = Reg(UInt(nComponents.W)) /** all harts have reset status */ val haveResetBitRegs = Reg(UInt(nComponents.W)) // default is 1,after resume, resumeAcks get 0 /** all harts resume ack status */ val resumeAcks = Wire(UInt(nComponents.W)) // --- regmapper outputs // hart state Id and En // in Hart Bus Access ROM val hartHaltedWrEn = Wire(Bool()) val hartHaltedId = Wire(UInt(sbIdWidth.W)) val hartGoingWrEn = Wire(Bool()) val hartGoingId = Wire(UInt(sbIdWidth.W)) val hartResumingWrEn = Wire(Bool()) val hartResumingId = Wire(UInt(sbIdWidth.W)) val hartExceptionWrEn = Wire(Bool()) val hartExceptionId = Wire(UInt(sbIdWidth.W)) // progbuf and abstract data: byte-addressable control logic // AccessLegal is set only when state = waiting // RdEn and WrEnMaybe : contrl signal drived by DMI bus val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiProgramBufferAccessLegal = WireInit(false.B) val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) val dmiAbstractDataAccessLegal = WireInit(false.B) val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) //-------------------------------------------------------------- // Registers coming from 'CONTROL' in Outer //-------------------------------------------------------------- val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B) val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W)) // hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nComponents > 1) { when (~io.dmactive) { selectedHartReg := 0.U }.elsewhen (io.innerCtrl.fire){ selectedHartReg := io.innerCtrl.bits.hartsel } } if (supportHartArray) { val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val hamaskReg = Reg(Vec(nComponents, Bool())) when (~io.dmactive || ~dmAuthenticated) { hamaskReg := hamaskZero }.elsewhen (io.innerCtrl.fire){ hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero) } hamaskFull := hamaskReg } // Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello, // so append it here when (selectedHartReg < nComponents.U) { hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B } io.innerCtrl.ready := true.B // Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write // A hart may be selected by hartsel field or by hart array val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) for (component <- 0 until nComponents ) { hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) || (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B)) } //------------------------------------- // Halt-on-reset logic // hrmask is set in dmOuter and passed in // Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set // Debug interrupt is maintained until the hart enters halted state //------------------------------------- val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } )) val hrDebugInt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegInit(hrReset) val hartIsInResetSync = Wire(Vec(nComponents, Bool())) for (component <- 0 until nComponents) { hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component")) } when (~io.dmactive || ~dmAuthenticated) { hrmaskReg := hrReset }.elsewhen (io.innerCtrl.fire){ hrmaskReg := io.innerCtrl.bits.hrmask } withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } )) when (~io.dmactive || ~dmAuthenticated) { hrDebugIntReg := hrReset }.otherwise { hrDebugIntReg := hrmaskReg & (hartIsInResetSync | // set debugInt during reset (hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts } hrDebugInt := hrDebugIntReg } //-------------------------------------------------------------- // DMI Registers //-------------------------------------------------------------- //----DMSTATUS val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields())) DMSTATUSRdData.authenticated := dmAuthenticated DMSTATUSRdData.version := 2.U // Version 0.13 io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy) val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq when (dmAuthenticated) { DMSTATUSRdData.hasresethaltreq := true.B DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent // all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ | _)) when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ | _) when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set DMSTATUSRdData.allunavail := (io.debugUnavail | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allresumeack := (resumeAcks.asBools | ~hamaskFull).reduce(_ & _) } } //TODO DMSTATUSRdData.confstrptrvalid := false.B DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B } when(~io.dmactive || ~dmAuthenticated) { haveResetBitRegs := 0.U }.otherwise { when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) { haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) | hartIsInResetSync.asUInt }.otherwise { haveResetBitRegs := haveResetBitRegs | hartIsInResetSync.asUInt } } //----DMCS2 (Halt Groups) val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val hgselectWrEn = WireInit(false.B) val hgwriteWrEn = WireInit(false.B) val haltgroupWrEn = WireInit(false.B) val exttriggerWrEn = WireInit(false.B) val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup val hgBits = log2Up(nHaltGroups) // hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned. val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W)))) val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil // assign group index to current seledcted harts for (component <- 0 until nComponents) { when (~io.dmactive || ~dmAuthenticated) { hgParticipateHart(component) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect & hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateHart(component) := DMCS2WrData.haltgroup } } } DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg) if (nExtTriggers > 0) { val hgSelect = Reg(Bool()) when (~io.dmactive || ~dmAuthenticated) { hgSelect := false.B }.otherwise { when (hgselectWrEn) { hgSelect := DMCS2WrData.hgselect } } // assign group index to trigger for (trigger <- 0 until nExtTriggers) { when (~io.dmactive || ~dmAuthenticated) { hgParticipateTrig(trigger) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect & (DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateTrig(trigger) := DMCS2WrData.haltgroup } } } DMCS2RdData.hgselect := hgSelect when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(0) } // If there is only 1 ext trigger, then the exttrigger field is fixed at 0 // Otherwise, instantiate a register with only the number of bits required if (nExtTriggers > 1) { val trigBits = log2Up(nExtTriggers-1) val hgExtTrigger = Reg(UInt(trigBits.W)) when (~io.dmactive || ~dmAuthenticated) { hgExtTrigger := 0.U }.otherwise { when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) { hgExtTrigger := DMCS2WrData.exttrigger } } DMCS2RdData.exttrigger := hgExtTrigger when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger) } } } // Halt group state machine // IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0 // or when any trigin assigned to this hg occurs // FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs // and all trig out in this hg have been acknowledged val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} )) val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked io.extTrigger.foreach {extTrigger => val extTriggerInReq = Wire(Vec(nExtTriggers, Bool())) val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool())) extTriggerInReq := extTrigger.in.req.asBools extTriggerOutAck := extTrigger.out.ack.asBools val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync")) val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync")) for (hg <- 1 to nHaltGroups) { hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ | _) hgTrigsAllAcked(hg) := (trigOutAck | hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _) } extTrigger.in.ack := trigInReq.asUInt } for (hg <- 1 to nHaltGroups) { hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U) hgHartsAllHalted(hg) := (haltedBitRegs.asBools | hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _) when (~io.dmactive || ~dmAuthenticated) { hgFired(hg) := false.B }.elsewhen (~hgFired(hg) & (hgHartFiring(hg) | hgTrigFiring(hg))) { hgFired(hg) := true.B }.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) { hgFired(hg) := false.B } } // For each hg that has fired, assert debug interrupt to each hart in that hg for (component <- 0 until nComponents) { hgDebugInt(component) := hgFired(hgParticipateHart(component)) } // For each hg that has fired, assert trigger out for all external triggers in that hg io.extTrigger.foreach {extTrigger => val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} )) for (trig <- 0 until nExtTriggers) { extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig)) } extTrigger.out.req := extTriggerOutReq.asUInt } } io.hgDebugInt := hgDebugInt | hrDebugInt //----HALTSUM* val numHaltedStatus = ((nComponents - 1) / 32) + 1 val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W))) for (ii <- 0 until numHaltedStatus) { when (dmAuthenticated) { haltedStatus(ii) := haltedBitRegs >> (ii*32) }.otherwise { haltedStatus(ii) := 0.U } } val haltedSummary = Cat(haltedStatus.map(_.orR).reverse) val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields()) val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5)) val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields()) // Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3 //----ABSTRACTCS val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U val ABSTRACTCSReg = Reg(new ABSTRACTCSFields()) val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg) val ABSTRACTCSRdEn = WireInit(false.B) val ABSTRACTCSWrEnMaybe = WireInit(false.B) val ABSTRACTCSWrEnLegal = WireInit(false.B) val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal // multiple error types // find implement in the state machine part val errorBusy = WireInit(false.B) val errorException = WireInit(false.B) val errorUnsupported = WireInit(false.B) val errorHaltResume = WireInit(false.B) when (~io.dmactive || ~dmAuthenticated) { ABSTRACTCSReg := ABSTRACTCSReset }.otherwise { when (errorBusy){ ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U }.elsewhen (errorException) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U }.elsewhen (errorUnsupported) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U }.elsewhen (errorHaltResume) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U }.otherwise { //W1C when (ABSTRACTCSWrEn){ ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr); } } } // For busy, see below state machine. val abstractCommandBusy = WireInit(true.B) ABSTRACTCSRdData.busy := abstractCommandBusy when (~dmAuthenticated) { // read value must be 0 when not authenticated ABSTRACTCSRdData.datacount := 0.U ABSTRACTCSRdData.progbufsize := 0.U } //---- ABSTRACTAUTO // It is a mask indicating whether datai/probufi have the autoexcution permisson // this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec // first two specify which reg supports autoexec // autoexec is a control signal, meaning there is at least one enabled autoexec reg // when autoexec is set, generate instructions using COMMAND register val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields()) val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg) val ABSTRACTAUTORdEn = WireInit(false.B) val autoexecdataWrEnMaybe = WireInit(false.B) val autoexecprogbufWrEnMaybe = WireInit(false.B) val ABSTRACTAUTOWrEnLegal = WireInit(false.B) when (~io.dmactive || ~dmAuthenticated) { ABSTRACTAUTOReg := ABSTRACTAUTOReset }.otherwise { when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U } when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U } } // Abstract Data access vector(byte-addressable) val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r | w} // Program Buffer access vector(byte-addressable) val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r | w} // at least one word access val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ || _ ) val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ || _) // This will take the shorter of the lists, which is what we want. val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} )) val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} )) (autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 } (autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2} val autoexec = autoexecData.reduce(_ || _) || autoexecProg.reduce(_ || _) //---- COMMAND val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields())) val COMMANDReg = Reg(new COMMANDFields()) val COMMANDWrDataVal = WireInit(0.U(32.W)) val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields())) val COMMANDWrEnMaybe = WireInit(false.B) val COMMANDWrEnLegal = WireInit(false.B) val COMMANDRdEn = WireInit(false.B) val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal val COMMANDRdData = COMMANDReg when (~io.dmactive || ~dmAuthenticated) { COMMANDReg := COMMANDReset }.otherwise { when (COMMANDWrEn) { COMMANDReg := COMMANDWrData } } // --- Abstract Data // These are byte addressible, s.t. the Processor can use // byte-addressible instructions to store to them. val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords*4, UInt(8.W))) val abstractDataNxt = WireInit(abstractDataMem) // --- Program Buffer // byte-addressible mem val programBufferMem = Reg(Vec(cfg.nProgramBufferWords*4, UInt(8.W))) val programBufferNxt = WireInit(programBufferMem) //-------------------------------------------------------------- // These bits are implementation-specific bits set // by harts executing code. //-------------------------------------------------------------- // Run control logic when (~io.dmactive || ~dmAuthenticated) { haltedBitRegs := 0.U resumeReqRegs := 0.U }.otherwise { //remove those harts in reset resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt) val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId)) val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId)) val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel) when (hartHaltedWrEn) { // add those harts halting and remove those in reset haltedBitRegs := (haltedBitRegs | hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt) }.elsewhen (hartResumingWrEn) { // remove those harts in reset and those in resume haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) }.otherwise { // remove those harts in reset haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt) } when (hartResumingWrEn) { // remove those harts in resume and those in reset resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) } when (resumereq) { // set all sleceted harts to resumeReq, remove those in reset resumeReqRegs := (resumeReqRegs | hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt) } } when (resumereq) { // next cycle resumeAcls will be the negation of next cycle resumeReqRegs resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt)) }.otherwise { resumeAcks := ~resumeReqRegs } //---- AUTHDATA val authRdEnMaybe = WireInit(false.B) val authWrEnMaybe = WireInit(false.B) io.auth.map { a => a.dmactive := io.dmactive a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy } val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq( RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))), RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))), RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))), RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))), RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))), RegField(2), RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0))) )) val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq( WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn, RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)), WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn, RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)), WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn, RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)), if (nExtTriggers > 1) WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn, RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true)) else RegField(4) )) val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq( RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))), RegField(4), WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe, RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(1), RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))), RegField(11), RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords))) )) val (sbcsFields, sbAddrFields, sbDataFields): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl => SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p) }.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]))) //-------------------------------------------------------------- // Program Buffer Access (DMI ... System Bus can override) //-------------------------------------------------------------- val omRegMap = dmiNode.regmap( (DMI_DMSTATUS << 2) -> dmstatusRegFields, //TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields, (DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil), (DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"), Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))), (DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"), Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))), (DMI_ABSTRACTCS << 2) -> abstractcsRegFields, (DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq( WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe, RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))), RegField(16-cfg.nAbstractDataWords), WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe, RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))), (DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"), Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe, Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))), (DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i), dmiAbstractDataRdEn(i), dmiAbstractDataWrEnMaybe(i), Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false), (DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i), dmiProgramBufferRdEn(i), dmiProgramBufferWrEnMaybe(i), Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false), (DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"), Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe, Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil), (DMI_SBCS << 2) -> sbcsFields, (DMI_SBDATA0 << 2) -> sbDataFields(0), (DMI_SBDATA1 << 2) -> sbDataFields(1), (DMI_SBDATA2 << 2) -> sbDataFields(2), (DMI_SBDATA3 << 2) -> sbDataFields(3), (DMI_SBADDRESS0 << 2) -> sbAddrFields(0), (DMI_SBADDRESS1 << 2) -> sbAddrFields(1), (DMI_SBADDRESS2 << 2) -> sbAddrFields(2), (DMI_SBADDRESS3 << 2) -> sbAddrFields(3) ) // Abstract data mem is written by both the tile link interface and DMI... abstractDataMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) { x := abstractDataNxt(i) } } // ... and also by custom register read (if implemented) val (customs, customParams) = customNode.in.unzip val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0) def getNeedCustom = () => needCustom if (needCustom) { val (custom, customP) = customNode.in.head require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}") val custom_data = custom.data.asBools val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i*8, (i+1)*8).asUInt} when (custom.ready && custom.valid) { (abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) => a := b } } } programBufferMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) { x := programBufferNxt(i) } } //-------------------------------------------------------------- // "Variable" ROM Generation //-------------------------------------------------------------- val goReg = Reg(Bool()) val goAbstract = WireInit(false.B) val goCustom = WireInit(false.B) val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ())) jalAbstract.setImm(ABSTRACT(cfg) - WHERETO) when (~io.dmactive){ goReg := false.B }.otherwise { when (goAbstract) { goReg := true.B }.elsewhen (hartGoingWrEn){ assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U) goReg := false.B } } class flagBundle extends Bundle { val reserved = UInt(6.W) val resume = Bool() val go = Bool() } val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} )) assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U), s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.") flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg for (component <- 0 until nComponents) { val componentSel = WireInit(component.U) flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component) } //---------------------------- // Abstract Command Decoding & Generation //---------------------------- val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields())) /** real COMMAND*/ val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields())) // TODO: Quick Access class GeneratedI extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedS extends Bundle { val immhi = UInt(7.W) val rs2 = UInt(5.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val immlo = UInt(5.W) val opcode = UInt(7.W) } class GeneratedCSR extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedUJ extends Bundle { val imm3 = UInt(1.W) val imm0 = UInt(10.W) val imm1 = UInt(1.W) val imm2 = UInt(8.W) val rd = UInt(5.W) val opcode = UInt(7.W) def setImm(imm: Int) : Unit = { // TODO: Check bounds of imm. require(imm % 2 == 0, "Immediate must be even for UJ encoding.") val immWire = WireInit(imm.S(21.W)) val immBits = WireInit(VecInit(immWire.asBools)) imm0 := immBits.slice(1, 1 + 10).asUInt imm1 := immBits.slice(11, 11 + 11).asUInt imm2 := immBits.slice(12, 12 + 8).asUInt imm3 := immBits.slice(20, 20 + 1).asUInt } } require((cfg.atzero && cfg.nAbstractInstructions == 2) || (!cfg.atzero && cfg.nAbstractInstructions == 5), "Mismatch between DebugModuleParams atzero and nAbstractInstructions") val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W)))) def abstractGeneratedI(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedI()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode inst.rd := (accessRegisterCommandReg.regno & 0x1F.U) inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.imm := offset.U inst.asUInt } def abstractGeneratedS(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedS()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode inst.immlo := (offset & 0x1F).U inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U) inst.immhi := (offset >> 5).U inst.asUInt } def abstractGeneratedCSR: UInt = { val inst = Wire(new GeneratedCSR()) val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR())) inst.imm := CSRs.dscratch1.U inst.rs1 := base inst.rd := base inst.asUInt } val nop = Wire(new GeneratedI()) nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI()) nop.rd := 0.U nop.rs1 := 0.U nop.imm := 0.U val isa = Wire(new GeneratedI()) isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI()) isa.rd := 0.U isa.rs1 := 0.U isa.imm := 0.U when (goAbstract) { if (cfg.nAbstractInstructions == 2) { // ABSTRACT(0): Transfer: LW or SW, else NOP // ABSTRACT(1): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } else { // Entry: All regs in GPRs, dscratch1=offset 0x800 in DM // ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64) // ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP // ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(4): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt) abstractGeneratedMem(1) := abstractGeneratedCSR abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(3) := abstractGeneratedCSR abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } } //-------------------------------------------------------------- // Drive Custom Access //-------------------------------------------------------------- if (needCustom) { val (custom, customP) = customNode.in.head custom.addr := accessRegisterCommandReg.regno custom.valid := goCustom } //-------------------------------------------------------------- // Hart Bus Access //-------------------------------------------------------------- tlNode.regmap( // This memory is writable. HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn, "debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")), GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn, "debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")), RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn, "debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")), EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn, "debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")), DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"), abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}), PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"), programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}), // These sections are read-only. IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U, RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil}, WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))), ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"), abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}), FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"), if (nComponents == 1) { Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) } } else { flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))} }), ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"), (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))}) ) // Override System Bus accesses with dmactive reset. when (~io.dmactive){ abstractDataMem.foreach {x => x := 0.U} programBufferMem.foreach {x => x := 0.U} } //-------------------------------------------------------------- // Abstract Command State Machine //-------------------------------------------------------------- object CtrlState extends scala.Enumeration { type CtrlState = Value val Waiting, CheckGenerate, Exec, Custom = Value def apply( t : Value) : UInt = { t.id.U(log2Up(values.size).W) } } import CtrlState._ // This is not an initialization! val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting))) val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg) val ctrlStateNxt = WireInit(ctrlStateReg) //------------------------ // DMI Register Control and Status abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting)) ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting)) dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting)) errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) || (autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) || (autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) || (COMMANDWrEnMaybe && ~COMMANDWrEnLegal) || (dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) || (dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal) // TODO: Maybe Quick Access val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister val commandRegIsUnsupported = WireInit(true.B) val commandRegBadHaltResume = WireInit(false.B) // We only support abstract commands for GPRs and any custom registers, if specified. val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) || (accessRegisterCommandReg.size === 3.U) val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize val accessRegIsCustom = if (needCustom) { val (custom, customP) = customNode.in.head customP.addrs.foldLeft(false.B){ (result, current) => result || (current.U === accessRegisterCommandReg.regno)} } else false.B when (commandRegIsAccessRegister) { when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) { commandRegIsUnsupported := false.B }.elsewhen (!accessRegisterCommandReg.transfer || accessRegIsGPR) { commandRegIsUnsupported := false.B commandRegBadHaltResume := ~hartHalted } } val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) //------------------------ // Variable ROM STATE MACHINE // ----------------------- when (ctrlStateReg === CtrlState(Waiting)){ when (wrAccessRegisterCommand || regAccessRegisterCommand) { ctrlStateNxt := CtrlState(CheckGenerate) }.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type. errorUnsupported := true.B }.elsewhen (autoexec && commandRegIsUnsupported) { errorUnsupported := true.B } }.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){ // We use this state to ensure that the COMMAND has been // registered by the time that we need to use it, to avoid // generating it directly from the COMMANDWrData. // This 'commandRegIsUnsupported' is really just checking the // AccessRegisterCommand parameters (regno) when (commandRegIsUnsupported) { errorUnsupported := true.B ctrlStateNxt := CtrlState(Waiting) }.elsewhen (commandRegBadHaltResume){ errorHaltResume := true.B ctrlStateNxt := CtrlState(Waiting) }.otherwise { when(accessRegIsCustom) { ctrlStateNxt := CtrlState(Custom) }.otherwise { ctrlStateNxt := CtrlState(Exec) goAbstract := true.B } } }.elsewhen (ctrlStateReg === CtrlState(Exec)) { // We can't just look at 'hartHalted' here, because // hartHaltedWrEn is overloaded to mean 'got an ebreak' // which may have happened when we were already halted. when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){ ctrlStateNxt := CtrlState(Waiting) } when(hartExceptionWrEn) { assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U) ctrlStateNxt := CtrlState(Waiting) errorException := true.B } }.elsewhen (ctrlStateReg === CtrlState(Custom)) { assert(needCustom.B, "Should not be in custom state unless we need it.") goCustom := true.B val (custom, customP) = customNode.in.head when (custom.ready && custom.valid) { ctrlStateNxt := CtrlState(Waiting) } } when (~io.dmactive || ~dmAuthenticated) { ctrlStateReg := CtrlState(Waiting) }.otherwise { ctrlStateReg := ctrlStateNxt } assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)), "Unexpected EXCEPTION write: should only get it in Debug Module EXEC state") } } // Wrapper around TL Debug Module Inner and an Async DMI Sink interface. // Handles the synchronization of dmactive, which is used as a synchronous reset // inside the Inner block. // Also is the Sink side of hartsel & resumereq fields of DMCONTROL. class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{ val cfg = p(DebugModuleKey).get val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes)) val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) val dmiNode = dmiXing.node val tlNode = dmInner.tlNode dmInner.dmiNode := dmiXing.node // Require that there are no registers in TL interface, so that spurious // processor accesses to the DM don't need to enable the clock. We don't // require this property of the SBA, because the debugger is responsible for // raising dmactive (hence enabling the clock) during these transactions. require(dmInner.tlNode.concurrency == 0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { // Clock/reset domains: // debug_clock / debug_reset = Debug inner domain // tl_clock / tl_reset = tilelink domain (External: clock / reset) // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) // These are all asynchronous and come from Outer /** reset signal for DM */ val dmactive = Input(Bool()) /** conrol signals for Inner * * generated in Outer */ val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) // This comes from tlClk domain. /** debug available status */ val debugUnavail = Input(Vec(getNComponents(), Bool())) /** debug interruption*/ val hgDebugInt = Output(Vec(getNComponents(), Bool())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(getNComponents(), Bool())) /** Debug Authentication signals from core */ val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.debug_clock childReset := io.debug_reset override def provideImplicitClockToLazyChildren = true val dmactive_synced = withClockAndReset(childClock, childReset) { val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync")) dmInner.module.clock := io.debug_clock dmInner.module.reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.dmactive := dmactive_synced dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl) dmInner.module.io.debugUnavail := io.debugUnavail io.hgDebugInt := dmInner.module.io.hgDebugInt io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} dmactive_synced } } } /** Create a version of the TLDebugModule which includes a synchronization interface * internally for the DMI. This is no longer optional outside of this module * because the Clock must run when tl_clock isn't running or tl_reset is asserted. */ class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){ override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val attach = Map( "debug-attach" -> ( (if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++ (if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++ (if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++ (if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq()))) Description(name, mapping ++ attach) } } val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p)) val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p)) val node = dmInner.tlNode val intnode = dmOuter.intnode val apbNodeOpt = dmOuter.apbNodeOpt dmInner.dmiNode := dmOuter.dmiInnerNode lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.dmOuter.intnode.edges.out.size // Clock/reset domains: // tl_clock / tl_reset = tilelink domain // debug_clock / debug_reset = Inner debug (synchronous to tl_clock) // apb_clock / apb_reset = Outer debug with APB // dmiClock / dmiReset = Outer debug without APB // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /** Debug control signals generated in Outer */ val ctrl = new DebugCtrlBundle(nComponents) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI */ val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO())) val apb_clock = p(ExportDebug).apb.option(Input(Clock())) val apb_reset = p(ExportDebug).apb.option(Input(Reset())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(nComponents, Bool())) /** hart reset request generated by hartreset-logic in Outer */ val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** Debug Authentication signals from core */ val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) childClock := io.tl_clock childReset := io.tl_reset override def provideImplicitClockToLazyChildren = true dmOuter.module.io.dmi.foreach { dmOuterDMI => dmOuterDMI <> io.dmi.get.dmi dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock dmOuter.module.rf_reset := io.dmi.get.dmiReset } (io.apb_clock zip io.apb_reset) foreach { case (c, r) => dmOuter.module.io.dmi_reset := r dmOuter.module.io.dmi_clock := c dmOuter.module.rf_reset := r } dmInner.module.rf_reset := io.debug_reset dmInner.module.io.debug_clock := io.debug_clock dmInner.module.io.debug_reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive dmInner.module.io.debugUnavail := io.ctrl.debugUnavail dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt io.ctrl <> dmOuter.module.io.ctrl io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated } io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} } } File SBA.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug.systembusaccess import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} import freechips.rocketchip.devices.debug.{DebugModuleKey, RWNotify, SBCSFields, WNotifyVal} import freechips.rocketchip.diplomacy.TransferSizes import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType} import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters} import freechips.rocketchip.util.property object SystemBusAccessState extends scala.Enumeration { type SystemBusAccessState = Value val Idle, SBReadRequest, SBWriteRequest, SBReadResponse, SBWriteResponse = Value } object SBErrorCode extends scala.Enumeration { type SBErrorCode = Value val NoError = Value(0) val Timeout = Value(1) val BadAddr = Value(2) val AlgnError = Value(3) val BadAccess = Value(4) val OtherError = Value(7) } object SystemBusAccessModule { def apply(sb2tl: SBToTL, dmactive: Bool, dmAuthenticated: Bool)(implicit p: Parameters): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = { import SBErrorCode._ val cfg = p(DebugModuleKey).get val anyAddressWrEn = WireInit(false.B).suggestName("anyAddressWrEn") val anyDataRdEn = WireInit(false.B).suggestName("anyDataRdEn") val anyDataWrEn = WireInit(false.B).suggestName("anyDataWrEn") // --- SBCS Status Register --- val SBCSFieldsReg = Reg(new SBCSFields()).suggestName("SBCSFieldsReg") val SBCSFieldsRegReset = WireInit(0.U.asTypeOf(new SBCSFields())) SBCSFieldsRegReset.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018 SBCSFieldsRegReset.sbbusy := (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U) SBCSFieldsRegReset.sbaccess := 2.U SBCSFieldsRegReset.sbasize := sb2tl.module.edge.bundle.addressBits.U SBCSFieldsRegReset.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B SBCSFieldsRegReset.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B SBCSFieldsRegReset.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B SBCSFieldsRegReset.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B SBCSFieldsRegReset.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B val SBCSRdData = WireInit(0.U.asTypeOf(new SBCSFields())).suggestName("SBCSRdData") val SBCSWrDataVal = WireInit(0.U(32.W)) val SBCSWrData = WireInit(SBCSWrDataVal.asTypeOf(new SBCSFields())) val sberrorWrEn = WireInit(false.B) val sbreadondataWrEn = WireInit(false.B) val sbautoincrementWrEn= WireInit(false.B) val sbaccessWrEn = WireInit(false.B) val sbreadonaddrWrEn = WireInit(false.B) val sbbusyerrorWrEn = WireInit(false.B) val sbcsfields = RegFieldGroup("sbcs", Some("system bus access control and status"), Seq( RegField.r(1, SBCSRdData.sbaccess8, RegFieldDesc("sbaccess8", "8-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 8) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess16, RegFieldDesc("sbaccess16", "16-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 16) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess32, RegFieldDesc("sbaccess32", "32-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 32) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess64, RegFieldDesc("sbaccess64", "64-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 64) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess128, RegFieldDesc("sbaccess128", "128-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess == 128) 1 else 0))), RegField.r(7, SBCSRdData.sbasize, RegFieldDesc("sbasize", "bits in address", reset=Some(sb2tl.module.edge.bundle.addressBits))), WNotifyVal(3, SBCSRdData.sberror, SBCSWrData.sberror, sberrorWrEn, RegFieldDesc("sberror", "system bus error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), WNotifyVal(1, SBCSRdData.sbreadondata, SBCSWrData.sbreadondata, sbreadondataWrEn, RegFieldDesc("sbreadondata", "system bus read on data", reset=Some(0))), WNotifyVal(1, SBCSRdData.sbautoincrement, SBCSWrData.sbautoincrement, sbautoincrementWrEn, RegFieldDesc("sbautoincrement", "system bus auto-increment address", reset=Some(0))), WNotifyVal(3, SBCSRdData.sbaccess, SBCSWrData.sbaccess, sbaccessWrEn, RegFieldDesc("sbaccess", "system bus access size", reset=Some(2))), WNotifyVal(1, SBCSRdData.sbreadonaddr, SBCSWrData.sbreadonaddr, sbreadonaddrWrEn, RegFieldDesc("sbreadonaddr", "system bus read on data", reset=Some(0))), RegField.r(1, SBCSRdData.sbbusy, RegFieldDesc("sbbusy", "system bus access is busy", reset=Some(0))), WNotifyVal(1, SBCSRdData.sbbusyerror, SBCSWrData.sbbusyerror, sbbusyerrorWrEn, RegFieldDesc("sbbusyerror", "system bus busy error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(6), RegField.r(3, SBCSRdData.sbversion, RegFieldDesc("sbversion", "system bus access version", reset=Some(1))), )) // --- System Bus Address Registers --- // ADDR0 Register is required // Instantiate ADDR1-3 registers as needed depending on system bus address width val hasSBAddr1 = (sb2tl.module.edge.bundle.addressBits >= 33) val hasSBAddr2 = (sb2tl.module.edge.bundle.addressBits >= 65) val hasSBAddr3 = (sb2tl.module.edge.bundle.addressBits >= 97) val hasAddr = Seq(true, hasSBAddr1, hasSBAddr2, hasSBAddr3) val SBADDRESSFieldsReg = Reg(Vec(4, UInt(32.W))) SBADDRESSFieldsReg.zipWithIndex.foreach { case(a,i) => a.suggestName("SBADDRESS"+i+"FieldsReg")} val SBADDRESSWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) val SBADDRESSRdEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val SBADDRESSWrEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val autoIncrementedAddr = WireInit(0.U(128.W)) autoIncrementedAddr := Cat(SBADDRESSFieldsReg.reverse) + (1.U << SBCSFieldsReg.sbaccess) autoIncrementedAddr.suggestName("autoIncrementedAddr") val sbaddrfields: Seq[Seq[RegField]] = SBADDRESSFieldsReg.zipWithIndex.map { case(a,i) => if(hasAddr(i)) { when (~dmactive || ~dmAuthenticated) { a := 0.U(32.W) }.otherwise { a := Mux(SBADDRESSWrEn(i) && !SBCSRdData.sberror && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror, SBADDRESSWrData(i), Mux((sb2tl.module.io.rdDone || sb2tl.module.io.wrDone) && SBCSFieldsReg.sbautoincrement, autoIncrementedAddr(32*i+31,32*i), a)) } RegFieldGroup("dmi_sbaddr"+i, Some("SBA Address Register"), Seq(RWNotify(32, a, SBADDRESSWrData(i), SBADDRESSRdEn(i), SBADDRESSWrEn(i), Some(RegFieldDesc("dmi_sbaddr"+i, "SBA address register", reset=Some(0), volatile=true))))) } else { a := DontCare Seq.empty[RegField] } } sb2tl.module.io.addrIn := Mux(SBADDRESSWrEn(0), Cat(Cat(SBADDRESSFieldsReg.drop(1).reverse), SBADDRESSWrData(0)), Cat(SBADDRESSFieldsReg.reverse)) anyAddressWrEn := SBADDRESSWrEn.reduce(_ || _) // --- System Bus Data Registers --- // DATA0 Register is required // DATA1-3 Registers may not be needed depending on implementation val hasSBData1 = (cfg.maxSupportedSBAccess > 32) val hasSBData2And3 = (cfg.maxSupportedSBAccess == 128) val hasData = Seq(true, hasSBData1, hasSBData2And3, hasSBData2And3) val SBDATAFieldsReg = Reg(Vec(4, Vec(4, UInt(8.W)))) SBDATAFieldsReg.zipWithIndex.foreach { case(d,i) => d.zipWithIndex.foreach { case(d,j) => d.suggestName("SBDATA"+i+"BYTE"+j) }} val SBDATARdData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) SBDATARdData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATARdData"+i) } val SBDATAWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) SBDATAWrData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrData"+i) } val SBDATARdEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val SBDATAWrEn = WireInit(VecInit(Seq.fill(4) {false.B} )) SBDATAWrEn.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrEn"+i) } val sbdatafields: Seq[Seq[RegField]] = SBDATAFieldsReg.zipWithIndex.map { case(d,i) => if(hasData(i)) { // For data registers, load enable per-byte for (j <- 0 to 3) { when (~dmactive || ~dmAuthenticated) { d(j) := 0.U(8.W) }.otherwise { d(j) := Mux(SBDATAWrEn(i) && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror, SBDATAWrData(i)(8*j+7,8*j), Mux(sb2tl.module.io.rdLoad(4*i+j), sb2tl.module.io.dataOut, d(j))) } } SBDATARdData(i) := Cat(d.reverse) RegFieldGroup("dmi_sbdata"+i, Some("SBA Data Register"), Seq(RWNotify(32, SBDATARdData(i), SBDATAWrData(i), SBDATARdEn(i), SBDATAWrEn(i), Some(RegFieldDesc("dmi_sbdata"+i, "SBA data register", reset=Some(0), volatile=true))))) } else { for (j <- 0 to 3) { d(j) := DontCare } Seq.empty[RegField] } } sb2tl.module.io.dataIn := Mux(sb2tl.module.io.wrEn,Cat(SBDATAWrData.reverse),Cat(SBDATAFieldsReg.flatten.reverse)) anyDataRdEn := SBDATARdEn.reduce(_ || _) anyDataWrEn := SBDATAWrEn.reduce(_ || _) val tryWrEn = SBDATAWrEn(0) val tryRdEn = (SBADDRESSWrEn(0) && SBCSFieldsReg.sbreadonaddr) || (SBDATARdEn(0) && SBCSFieldsReg.sbreadondata) val sbAccessError = (SBCSFieldsReg.sbaccess === 0.U) && (SBCSFieldsReg.sbaccess8 =/= 1.U) || (SBCSFieldsReg.sbaccess === 1.U) && (SBCSFieldsReg.sbaccess16 =/= 1.U) || (SBCSFieldsReg.sbaccess === 2.U) && (SBCSFieldsReg.sbaccess32 =/= 1.U) || (SBCSFieldsReg.sbaccess === 3.U) && (SBCSFieldsReg.sbaccess64 =/= 1.U) || (SBCSFieldsReg.sbaccess === 4.U) && (SBCSFieldsReg.sbaccess128 =/= 1.U) || (SBCSFieldsReg.sbaccess > 4.U) val compareAddr = Wire(UInt(32.W)) // Need use written or latched address to detect error case depending on how transaction is initiated compareAddr := Mux(SBADDRESSWrEn(0),SBADDRESSWrData(0),SBADDRESSFieldsReg(0)) val sbAlignmentError = (SBCSFieldsReg.sbaccess === 1.U) && (compareAddr(0) =/= 0.U) || (SBCSFieldsReg.sbaccess === 2.U) && (compareAddr(1,0) =/= 0.U) || (SBCSFieldsReg.sbaccess === 3.U) && (compareAddr(2,0) =/= 0.U) || (SBCSFieldsReg.sbaccess === 4.U) && (compareAddr(3,0) =/= 0.U) sbAccessError.suggestName("sbAccessError") sbAlignmentError.suggestName("sbAlignmentError") sb2tl.module.io.wrEn := dmAuthenticated && tryWrEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError sb2tl.module.io.rdEn := dmAuthenticated && tryRdEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError sb2tl.module.io.sizeIn := SBCSFieldsReg.sbaccess val sbBusy = (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U) when (~dmactive || ~dmAuthenticated) { SBCSFieldsReg := SBCSFieldsRegReset }.otherwise { SBCSFieldsReg.sbbusyerror := Mux(sbbusyerrorWrEn && SBCSWrData.sbbusyerror, false.B, // W1C Mux(anyAddressWrEn && sbBusy, true.B, // Set if a write to SBADDRESS occurs while busy Mux((anyDataRdEn || anyDataWrEn) && sbBusy, true.B, SBCSFieldsReg.sbbusyerror))) // Set if any access to SBDATA occurs while busy SBCSFieldsReg.sbreadonaddr := Mux(sbreadonaddrWrEn, SBCSWrData.sbreadonaddr , SBCSFieldsReg.sbreadonaddr) SBCSFieldsReg.sbautoincrement := Mux(sbautoincrementWrEn, SBCSWrData.sbautoincrement, SBCSFieldsReg.sbautoincrement) SBCSFieldsReg.sbreadondata := Mux(sbreadondataWrEn, SBCSWrData.sbreadondata , SBCSFieldsReg.sbreadondata) SBCSFieldsReg.sbaccess := Mux(sbaccessWrEn, SBCSWrData.sbaccess, SBCSFieldsReg.sbaccess) SBCSFieldsReg.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018 } // sbErrorReg has a per-bit load enable since each bit can be individually cleared by writing a 1 to it val sbErrorReg = Reg(Vec(4, UInt(1.W))) when(~dmactive || ~dmAuthenticated) { for (i <- 0 until 3) sbErrorReg(i) := 0.U }.otherwise { for (i <- 0 until 3) sbErrorReg(i) := Mux(sberrorWrEn && SBCSWrData.sberror(i) === 1.U, NoError.id.U.extract(i), // W1C Mux((sb2tl.module.io.wrEn && !sb2tl.module.io.wrLegal) || (sb2tl.module.io.rdEn && !sb2tl.module.io.rdLegal), BadAddr.id.U.extract(i), // Bad address accessed Mux((tryWrEn || tryRdEn) && sbAlignmentError, AlgnError.id.U.extract(i), // Address alignment error Mux((tryWrEn || tryRdEn) && sbAccessError, BadAccess.id.U.extract(i), // Access size error Mux((sb2tl.module.io.rdDone || sb2tl.module.io.wrDone) && sb2tl.module.io.respError, OtherError.id.U.extract(i), sbErrorReg(i)))))) // Response error from TL } SBCSRdData := SBCSFieldsReg SBCSRdData.sbasize := sb2tl.module.edge.bundle.addressBits.U SBCSRdData.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B SBCSRdData.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B SBCSRdData.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B SBCSRdData.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B SBCSRdData.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B SBCSRdData.sbbusy := sbBusy SBCSRdData.sberror := sbErrorReg.asUInt when (~dmAuthenticated) { // Read value must be 0 if not authenticated SBCSRdData := 0.U.asTypeOf(new SBCSFields()) } property.cover(SBCSFieldsReg.sbbusyerror, "SBCS Cover", "sberror set") property.cover(SBCSFieldsReg.sbbusy === 3.U, "SBCS Cover", "sbbusyerror alignment error") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 0.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "8-bit access") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 1.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "16-bit access") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 2.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "32-bit access") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 3.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "64-bit access") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 4.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "128-bit access") property.cover(SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access with autoincrement set") property.cover(!SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access without autoincrement set") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess > 4.U, "SBCS Cover", "Invalid sbaccess value") (sbcsfields, sbaddrfields, sbdatafields) } } class SBToTL(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1("debug")), requestFields = Seq(AMBAProtField())))) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val rdEn = Input(Bool()) val wrEn = Input(Bool()) val addrIn = Input(UInt(128.W)) // TODO: Parameterize these widths val dataIn = Input(UInt(128.W)) val sizeIn = Input(UInt(3.W)) val rdLegal = Output(Bool()) val wrLegal = Output(Bool()) val rdDone = Output(Bool()) val wrDone = Output(Bool()) val respError = Output(Bool()) val dataOut = Output(UInt(8.W)) val rdLoad = Output(Vec(cfg.maxSupportedSBAccess/8, Bool())) val sbStateOut = Output(UInt(log2Ceil(SystemBusAccessState.maxId).W)) }) val rf_reset = IO(Input(Reset())) import SystemBusAccessState._ val (tl, edge) = node.out(0) val sbState = RegInit(0.U) // --- Drive payloads on bus to TileLink --- val d = Queue(tl.d, 2) // Add a small buffer since response could arrive on same cycle as request d.ready := (sbState === SBReadResponse.id.U) || (sbState === SBWriteResponse.id.U) val muxedData = WireInit(0.U(8.W)) val requestValid = tl.a.valid val requestReady = tl.a.ready val responseValid = d.valid val responseReady = d.ready val counter = RegInit(0.U((log2Ceil(cfg.maxSupportedSBAccess/8)+1).W)) val vecData = Wire(Vec(cfg.maxSupportedSBAccess/8, UInt(8.W))) vecData.zipWithIndex.map { case (vd, i) => vd := io.dataIn(8*i+7,8*i) } muxedData := vecData(counter(log2Ceil(vecData.size)-1,0)) // Need an additional check to determine if address is safe for Get/Put val rdLegal_addr = edge.manager.supportsGetSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8))) val wrLegal_addr = edge.manager.supportsPutFullSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8))) val (_, gbits) = edge.Get(0.U, io.addrIn, io.sizeIn) val (_, pfbits) = edge.Put(0.U, io.addrIn, io.sizeIn, muxedData) io.rdLegal := rdLegal_addr io.wrLegal := wrLegal_addr io.sbStateOut := sbState when(sbState === SBReadRequest.id.U) { tl.a.bits := gbits } .otherwise { tl.a.bits := pfbits } tl.a.bits.user.lift(AMBAProt).foreach { x => x.bufferable := false.B x.modifiable := false.B x.readalloc := false.B x.writealloc := false.B x.privileged := true.B x.secure := true.B x.fetch := false.B } val respError = d.bits.denied || d.bits.corrupt io.respError := respError val wrTxValid = sbState === SBWriteRequest.id.U && requestValid && requestReady val rdTxValid = sbState === SBReadResponse.id.U && responseValid && responseReady val txLast = counter === ((1.U << io.sizeIn) - 1.U) counter := Mux((wrTxValid || rdTxValid) && txLast, 0.U, Mux((wrTxValid || rdTxValid) , counter+1.U, counter)) for (i <- 0 until (cfg.maxSupportedSBAccess/8)) { io.rdLoad(i) := rdTxValid && (counter === i.U) } // --- State Machine to interface with TileLink --- when (sbState === Idle.id.U){ sbState := Mux(io.rdEn && io.rdLegal, SBReadRequest.id.U, Mux(io.wrEn && io.wrLegal, SBWriteRequest.id.U, sbState)) }.elsewhen (sbState === SBReadRequest.id.U){ sbState := Mux(requestValid && requestReady, SBReadResponse.id.U, sbState) }.elsewhen (sbState === SBWriteRequest.id.U){ sbState := Mux(wrTxValid && txLast, SBWriteResponse.id.U, sbState) }.elsewhen (sbState === SBReadResponse.id.U){ sbState := Mux(rdTxValid && txLast, Idle.id.U, sbState) }.elsewhen (sbState === SBWriteResponse.id.U){ sbState := Mux(responseValid && responseReady, Idle.id.U, sbState) } io.rdDone := rdTxValid && txLast io.wrDone := (sbState === SBWriteResponse.id.U) && responseValid && responseReady io.dataOut := d.bits.data tl.a.valid := (sbState === SBReadRequest.id.U) || (sbState === SBWriteRequest.id.U) // Tie off unused channels tl.b.ready := false.B tl.c.valid := false.B tl.e.valid := false.B assert (sbState === Idle.id.U || sbState === SBReadRequest.id.U || sbState === SBWriteRequest.id.U || sbState === SBReadResponse.id.U || sbState === SBWriteResponse.id.U, "SBA state machine in undefined state") property.cover (sbState === Idle.id.U, "SBA State Cover", "SBA Access Idle") property.cover (sbState === SBReadRequest.id.U, "SBA State Cover", "SBA Access Read Req") property.cover (sbState === SBWriteRequest.id.U, "SBA State Cover", "SBA Access Write Req") property.cover (sbState === SBReadResponse.id.U, "SBA State Cover", "SBA Access Read Resp") property.cover (sbState === SBWriteResponse.id.U, "SBA State Cover", "SBA Access Write Resp") property.cover (io.rdEn && !io.rdLegal, "SB Legality Cover", "SBA Rd Address Illegal") property.cover (io.wrEn && !io.wrLegal, "SB Legality Cover", "SBA Wr Address Illegal") } }

module TLDebugModuleInner( // @[Debug.scala:790:9] input clock, // @[Debug.scala:790:9] input reset, // @[Debug.scala:790:9] input auto_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmi_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmi_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmi_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [8:0] auto_dmi_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmi_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmi_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmi_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmi_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmi_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_dmactive, // @[Debug.scala:803:16] input io_innerCtrl_valid, // @[Debug.scala:803:16] input io_innerCtrl_bits_resumereq, // @[Debug.scala:803:16] input [9:0] io_innerCtrl_bits_hartsel, // @[Debug.scala:803:16] input io_innerCtrl_bits_ackhavereset, // @[Debug.scala:803:16] input io_innerCtrl_bits_hrmask_0, // @[Debug.scala:803:16] output io_hgDebugInt_0, // @[Debug.scala:803:16] input io_hartIsInReset_0, // @[Debug.scala:803:16] input io_tl_clock, // @[Debug.scala:803:16] input io_tl_reset // @[Debug.scala:803:16] ); wire abstractCommandBusy; // @[Debug.scala:1740:42] reg [1:0] ctrlStateReg; // @[Debug.scala:1732:27] wire out_woready_1_353; // @[RegisterRouter.scala:87:24] wire out_woready_1_536; // @[RegisterRouter.scala:87:24] wire out_woready_45; // @[RegisterRouter.scala:87:24] wire out_woready_28; // @[RegisterRouter.scala:87:24] wire out_woready_62; // @[RegisterRouter.scala:87:24] wire out_woready_80; // @[RegisterRouter.scala:87:24] wire out_woready_119; // @[RegisterRouter.scala:87:24] wire out_woready_135; // @[RegisterRouter.scala:87:24] wire out_woready_51; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_139; // @[RegisterRouter.scala:87:24] wire out_woready_127; // @[RegisterRouter.scala:87:24] wire out_woready_72; // @[RegisterRouter.scala:87:24] wire out_woready_58; // @[RegisterRouter.scala:87:24] wire out_woready_144; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_108; // @[RegisterRouter.scala:87:24] wire out_woready_76; // @[RegisterRouter.scala:87:24] wire out_woready_104; // @[RegisterRouter.scala:87:24] wire out_woready_54; // @[RegisterRouter.scala:87:24] wire out_woready_131; // @[RegisterRouter.scala:87:24] wire out_woready_32; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_20; // @[RegisterRouter.scala:87:24] wire out_woready_123; // @[RegisterRouter.scala:87:24] wire out_woready_67; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] wire out_roready_28; // @[RegisterRouter.scala:87:24] wire out_roready_62; // @[RegisterRouter.scala:87:24] wire out_roready_80; // @[RegisterRouter.scala:87:24] wire out_roready_119; // @[RegisterRouter.scala:87:24] wire out_roready_135; // @[RegisterRouter.scala:87:24] wire out_roready_51; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_139; // @[RegisterRouter.scala:87:24] wire out_roready_127; // @[RegisterRouter.scala:87:24] wire out_roready_72; // @[RegisterRouter.scala:87:24] wire out_roready_58; // @[RegisterRouter.scala:87:24] wire out_roready_144; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_108; // @[RegisterRouter.scala:87:24] wire out_roready_76; // @[RegisterRouter.scala:87:24] wire out_roready_104; // @[RegisterRouter.scala:87:24] wire out_roready_131; // @[RegisterRouter.scala:87:24] wire out_roready_32; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_20; // @[RegisterRouter.scala:87:24] wire out_roready_123; // @[RegisterRouter.scala:87:24] wire out_roready_67; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_24; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] wire out_backSel_61; // @[RegisterRouter.scala:87:24] wire out_backSel_60; // @[RegisterRouter.scala:87:24] wire out_backSel_57; // @[RegisterRouter.scala:87:24] wire out_backSel_23; // @[RegisterRouter.scala:87:24] wire out_backSel_22; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_19; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_19; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_18; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_18; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_17; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_17; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_16; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_16; // @[RegisterRouter.scala:87:24] wire [31:0] COMMANDWrDataVal; // @[Debug.scala:297:{24,30}, :1279:39] wire COMMANDWrEnMaybe; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_35; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_35; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_34; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_34; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_33; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_33; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_32; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_32; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_47; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_47; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_46; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_46; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_45; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_45; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_44; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_44; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_31; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_31; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_30; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_30; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_29; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_29; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_28; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_31; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_31; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_30; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_30; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_29; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_29; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_28; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_15; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_15; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_14; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_14; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_13; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_13; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_12; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_12; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_51; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_51; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_50; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_50; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_49; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_49; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_48; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_48; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_11; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_11; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_10; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_10; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_9; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_9; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_8; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_8; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_3; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_3; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_2; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_2; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_1; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_1; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_0; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_0; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_55; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_55; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_54; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_54; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_53; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_53; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_52; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_52; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_7; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_7; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_6; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_6; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_5; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_5; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_4; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_4; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_27; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_27; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_26; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_26; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_25; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_25; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_24; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_24; // @[RegisterRouter.scala:87:24] wire [31:0] SBDATAWrData_0; // @[SBA.scala:147:35] wire SBDATAWrEn_0; // @[RegisterRouter.scala:87:24] wire SBDATARdEn_0; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_11; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_11; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_10; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_10; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_9; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_9; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_8; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_8; // @[RegisterRouter.scala:87:24] wire SBADDRESSWrEn_0; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_59; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_59; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_58; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_58; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_57; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_57; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_56; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_56; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_23; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_23; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_22; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_22; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_21; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_21; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_20; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_20; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_43; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_43; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_42; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_42; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_41; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_41; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_40; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_40; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_27; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_27; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_26; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_26; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_25; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_25; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_24; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_24; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_63; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_63; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_62; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_62; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_61; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_61; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_60; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_60; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_3; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_3; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_2; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_2; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_1; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_1; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_0; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_0; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_19; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_19; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_18; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_18; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_17; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_17; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_16; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_16; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_15; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_15; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_14; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_14; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_13; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_13; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_12; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_12; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_39; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_39; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_38; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_38; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_37; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_37; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_36; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_36; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_23; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_23; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_22; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_22; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_21; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_21; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_20; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_20; // @[RegisterRouter.scala:87:24] wire [31:0] SBDATAWrData_1; // @[SBA.scala:147:35] wire dmiAbstractDataWrEnMaybe_7; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_7; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_6; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_6; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_5; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_5; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_4; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_4; // @[RegisterRouter.scala:87:24] wire [2:0] SBCSRdData_sberror; // @[SBA.scala:240:28] wire sb2tlOpt_io_wrEn; // @[SBA.scala:199:{60,85,115,138,156}] wire _hartIsInResetSync_0_debug_hartReset_0_io_q; // @[ShiftReg.scala:45:23] wire _sb2tlOpt_io_rdLegal; // @[Debug.scala:782:52] wire _sb2tlOpt_io_wrLegal; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdDone; // @[Debug.scala:782:52] wire _sb2tlOpt_io_wrDone; // @[Debug.scala:782:52] wire _sb2tlOpt_io_respError; // @[Debug.scala:782:52] wire [7:0] _sb2tlOpt_io_dataOut; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_0; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_1; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_2; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_3; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_4; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_5; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_6; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_7; // @[Debug.scala:782:52] wire [2:0] _sb2tlOpt_io_sbStateOut; // @[Debug.scala:782:52] reg hartHalted; // @[Debug.scala:861:31] reg resumeReqRegs; // @[Debug.scala:863:31] reg haveResetBitRegs; // @[Debug.scala:865:31] wire hamaskWrSel_0 = io_innerCtrl_bits_hartsel == 10'h0; // @[Debug.scala:935:61] reg hrmaskReg_0; // @[Debug.scala:947:29] reg hrDebugIntReg_0; // @[Debug.scala:961:34] wire resumereq = io_innerCtrl_valid & io_innerCtrl_bits_resumereq; // @[Debug.scala:983:39] reg [2:0] ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34] reg [15:0] ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36] reg [11:0] ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36] wire dmiAbstractDataAccessVec_0 = dmiAbstractDataWrEnMaybe_0 | dmiAbstractDataRdEn_0; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_4 = dmiAbstractDataWrEnMaybe_4 | dmiAbstractDataRdEn_4; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_8 = dmiAbstractDataWrEnMaybe_8 | dmiAbstractDataRdEn_8; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_12 = dmiAbstractDataWrEnMaybe_12 | dmiAbstractDataRdEn_12; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_16 = dmiAbstractDataWrEnMaybe_16 | dmiAbstractDataRdEn_16; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_20 = dmiAbstractDataWrEnMaybe_20 | dmiAbstractDataRdEn_20; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_24 = dmiAbstractDataWrEnMaybe_24 | dmiAbstractDataRdEn_24; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataAccessVec_28 = dmiAbstractDataWrEnMaybe_28 | dmiAbstractDataRdEn_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_0 = dmiProgramBufferWrEnMaybe_0 | dmiProgramBufferRdEn_0; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_4 = dmiProgramBufferWrEnMaybe_4 | dmiProgramBufferRdEn_4; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_8 = dmiProgramBufferWrEnMaybe_8 | dmiProgramBufferRdEn_8; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_12 = dmiProgramBufferWrEnMaybe_12 | dmiProgramBufferRdEn_12; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_16 = dmiProgramBufferWrEnMaybe_16 | dmiProgramBufferRdEn_16; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_20 = dmiProgramBufferWrEnMaybe_20 | dmiProgramBufferRdEn_20; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_24 = dmiProgramBufferWrEnMaybe_24 | dmiProgramBufferRdEn_24; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_28 = dmiProgramBufferWrEnMaybe_28 | dmiProgramBufferRdEn_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_32 = dmiProgramBufferWrEnMaybe_32 | dmiProgramBufferRdEn_32; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_36 = dmiProgramBufferWrEnMaybe_36 | dmiProgramBufferRdEn_36; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_40 = dmiProgramBufferWrEnMaybe_40 | dmiProgramBufferRdEn_40; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_44 = dmiProgramBufferWrEnMaybe_44 | dmiProgramBufferRdEn_44; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_48 = dmiProgramBufferWrEnMaybe_48 | dmiProgramBufferRdEn_48; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_52 = dmiProgramBufferWrEnMaybe_52 | dmiProgramBufferRdEn_52; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_56 = dmiProgramBufferWrEnMaybe_56 | dmiProgramBufferRdEn_56; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferAccessVec_60 = dmiProgramBufferWrEnMaybe_60 | dmiProgramBufferRdEn_60; // @[RegisterRouter.scala:87:24] wire autoexec = dmiAbstractDataAccessVec_0 & ABSTRACTAUTOReg_autoexecdata[0] | dmiAbstractDataAccessVec_4 & ABSTRACTAUTOReg_autoexecdata[1] | dmiAbstractDataAccessVec_8 & ABSTRACTAUTOReg_autoexecdata[2] | dmiAbstractDataAccessVec_12 & ABSTRACTAUTOReg_autoexecdata[3] | dmiAbstractDataAccessVec_16 & ABSTRACTAUTOReg_autoexecdata[4] | dmiAbstractDataAccessVec_20 & ABSTRACTAUTOReg_autoexecdata[5] | dmiAbstractDataAccessVec_24 & ABSTRACTAUTOReg_autoexecdata[6] | dmiAbstractDataAccessVec_28 & ABSTRACTAUTOReg_autoexecdata[7] | dmiProgramBufferAccessVec_0 & ABSTRACTAUTOReg_autoexecprogbuf[0] | dmiProgramBufferAccessVec_4 & ABSTRACTAUTOReg_autoexecprogbuf[1] | dmiProgramBufferAccessVec_8 & ABSTRACTAUTOReg_autoexecprogbuf[2] | dmiProgramBufferAccessVec_12 & ABSTRACTAUTOReg_autoexecprogbuf[3] | dmiProgramBufferAccessVec_16 & ABSTRACTAUTOReg_autoexecprogbuf[4] | dmiProgramBufferAccessVec_20 & ABSTRACTAUTOReg_autoexecprogbuf[5] | dmiProgramBufferAccessVec_24 & ABSTRACTAUTOReg_autoexecprogbuf[6] | dmiProgramBufferAccessVec_28 & ABSTRACTAUTOReg_autoexecprogbuf[7] | dmiProgramBufferAccessVec_32 & ABSTRACTAUTOReg_autoexecprogbuf[8] | dmiProgramBufferAccessVec_36 & ABSTRACTAUTOReg_autoexecprogbuf[9] | dmiProgramBufferAccessVec_40 & ABSTRACTAUTOReg_autoexecprogbuf[10] | dmiProgramBufferAccessVec_44 & ABSTRACTAUTOReg_autoexecprogbuf[11] | dmiProgramBufferAccessVec_48 & ABSTRACTAUTOReg_autoexecprogbuf[12] | dmiProgramBufferAccessVec_52 & ABSTRACTAUTOReg_autoexecprogbuf[13] | dmiProgramBufferAccessVec_56 & ABSTRACTAUTOReg_autoexecprogbuf[14] | dmiProgramBufferAccessVec_60 & ABSTRACTAUTOReg_autoexecprogbuf[15]; // @[Debug.scala:1235:36, :1258:105, :1261:108, :1269:{54,140}, :1270:{57,144}, :1272:{42,48,73}] reg [7:0] COMMANDReg_cmdtype; // @[Debug.scala:1277:25] reg [23:0] COMMANDReg_control; // @[Debug.scala:1277:25] wire COMMANDWrEn = COMMANDWrEnMaybe & ~(|ctrlStateReg); // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_0; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_1; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_2; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_3; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_4; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_5; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_6; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_7; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_8; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_9; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_10; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_11; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_12; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_13; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_14; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_15; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_16; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_17; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_18; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_19; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_20; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_21; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_22; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_23; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_24; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_25; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_26; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_27; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_28; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_29; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_30; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_31; // @[Debug.scala:1300:36] reg [7:0] programBufferMem_0; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_1; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_2; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_3; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_4; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_5; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_6; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_7; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_8; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_9; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_10; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_11; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_12; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_13; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_14; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_15; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_16; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_17; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_18; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_19; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_20; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_21; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_22; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_23; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_24; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_25; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_26; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_27; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_28; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_29; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_30; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_31; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_32; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_33; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_34; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_35; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_36; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_37; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_38; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_39; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_40; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_41; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_42; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_43; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_44; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_45; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_46; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_47; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_48; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_49; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_50; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_51; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_52; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_53; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_54; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_55; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_56; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_57; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_58; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_59; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_60; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_61; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_62; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_63; // @[Debug.scala:1306:34] reg SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28] reg SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28] reg SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28] reg [2:0] SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28] reg SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28] reg SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28] reg [31:0] SBADDRESSFieldsReg_0; // @[SBA.scala:104:33] reg [7:0] SBDATAFieldsReg_0_0; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_1; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_2; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_3; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_0; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_1; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_2; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_3; // @[SBA.scala:143:30] wire tryRdEn = SBADDRESSWrEn_0 & SBCSFieldsReg_sbreadonaddr | SBDATARdEn_0 & SBCSFieldsReg_sbreadondata; // @[RegisterRouter.scala:87:24] wire _sbAlignmentError_T_14 = SBCSFieldsReg_sbaccess == 3'h4; // @[SBA.scala:47:28, :186:49] wire sbAccessError = _sbAlignmentError_T_14 | SBCSFieldsReg_sbaccess > 3'h4; // @[SBA.scala:47:28, :186:{49,97,124}] wire [3:0] compareAddr = SBADDRESSWrEn_0 ? auto_dmi_in_a_bits_data[3:0] : SBADDRESSFieldsReg_0[3:0]; // @[RegisterRouter.scala:87:24] wire sbAlignmentError = SBCSFieldsReg_sbaccess == 3'h1 & compareAddr[0] | SBCSFieldsReg_sbaccess == 3'h2 & (|(compareAddr[1:0])) | SBCSFieldsReg_sbaccess == 3'h3 & (|(compareAddr[2:0])) | _sbAlignmentError_T_14 & (|compareAddr); // @[SBA.scala:47:28, :183:49, :184:49, :185:49, :186:49, :189:23, :191:{61,76,91}, :192:{61,76,82,91}, :193:{61,76,82,91}, :194:{61,82}] assign sb2tlOpt_io_wrEn = SBDATAWrEn_0 & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~(|SBCSRdData_sberror) & ~sbAccessError & ~sbAlignmentError; // @[RegisterRouter.scala:87:24] wire sb2tlOpt_io_rdEn = tryRdEn & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~(|SBCSRdData_sberror) & ~sbAccessError & ~sbAlignmentError; // @[SBA.scala:47:28, :119:40, :180:68, :186:97, :191:91, :192:91, :193:91, :199:{63,88,118,141,159}, :200:{60,85,115,138,156}, :240:28] reg sbErrorReg_0; // @[SBA.scala:219:25] reg sbErrorReg_1; // @[SBA.scala:219:25] reg sbErrorReg_2; // @[SBA.scala:219:25] assign SBCSRdData_sberror = {sbErrorReg_2, sbErrorReg_1, sbErrorReg_0}; // @[SBA.scala:219:25, :240:28] wire in_bits_read = auto_dmi_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire [7:0] _out_backMask_T_6 = {8{auto_dmi_in_a_bits_mask[2]}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_7 = {8{auto_dmi_in_a_bits_mask[3]}}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask = {_out_backMask_T_7, _out_backMask_T_6, {8{auto_dmi_in_a_bits_mask[1]}}, {8{auto_dmi_in_a_bits_mask[0]}}}; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_4 = out_roready_3 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_4 = out_woready_3 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_5 = out_roready_3 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_5 = out_woready_3 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_6 = out_roready_3 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_6 = out_woready_3 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_7 = out_roready_3 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_7 = out_woready_3 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire SBDATAWrEn_1 = _out_wofireMux_T_2 & out_backSel_61 & ~(auto_dmi_in_a_bits_address[8]) & (&out_backMask); // @[RegisterRouter.scala:87:24] assign SBDATAWrData_1 = SBDATAWrEn_1 ? auto_dmi_in_a_bits_data : 32'h0; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_20 = out_roready_8 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_20 = out_woready_8 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_21 = out_roready_8 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_21 = out_woready_8 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_22 = out_roready_8 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_22 = out_woready_8 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_23 = out_roready_8 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_23 = out_woready_8 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_36 = out_roready_9 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_36 = out_woready_9 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_37 = out_roready_9 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_37 = out_woready_9 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_38 = out_roready_9 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_38 = out_woready_9 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_39 = out_roready_9 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_39 = out_woready_9 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_12 = out_roready_16 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_12 = out_woready_16 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_13 = out_roready_16 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_13 = out_woready_16 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_14 = out_roready_16 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_14 = out_woready_16 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_15 = out_roready_16 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_15 = out_woready_16 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_16 = out_roready_20 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_16 = out_woready_20 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_17 = out_roready_20 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_17 = out_woready_20 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_18 = out_roready_20 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_18 = out_woready_20 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_19 = out_roready_20 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_19 = out_woready_20 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_0 = out_roready_24 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_0 = out_woready_24 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_1 = out_roready_24 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_1 = out_woready_24 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_2 = out_roready_24 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_2 = out_woready_24 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_3 = out_roready_24 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_3 = out_woready_24 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_60 = out_roready_28 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_60 = out_woready_28 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_61 = out_roready_28 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_61 = out_woready_28 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_62 = out_roready_28 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_62 = out_woready_28 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_63 = out_roready_28 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_63 = out_woready_28 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_24 = out_roready_32 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_24 = out_woready_32 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_25 = out_roready_32 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_25 = out_woready_32 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_26 = out_roready_32 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_26 = out_woready_32 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_27 = out_roready_32 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_27 = out_woready_32 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire sberrorWrEn = out_woready_45 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_40 = out_roready_51 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_40 = out_woready_51 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_41 = out_roready_51 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_41 = out_woready_51 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_42 = out_roready_51 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_42 = out_woready_51 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_43 = out_roready_51 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_43 = out_woready_51 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire autoexecdataWrEnMaybe = out_woready_54 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire autoexecprogbufWrEnMaybe = out_woready_54 & (&{_out_backMask_T_7, _out_backMask_T_6}); // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_20 = out_roready_58 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_20 = out_woready_58 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_21 = out_roready_58 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_21 = out_woready_58 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_22 = out_roready_58 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_22 = out_woready_58 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_23 = out_roready_58 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_23 = out_woready_58 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_56 = out_roready_62 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_56 = out_woready_62 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_57 = out_roready_62 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_57 = out_woready_62 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_58 = out_roready_62 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_58 = out_woready_62 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_59 = out_roready_62 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_59 = out_woready_62 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign SBADDRESSWrEn_0 = _out_wofireMux_T_2 & out_backSel_57 & ~(auto_dmi_in_a_bits_address[8]) & (&out_backMask); // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_8 = out_roready_67 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_8 = out_woready_67 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_9 = out_roready_67 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_9 = out_woready_67 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_10 = out_roready_67 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_10 = out_woready_67 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_11 = out_roready_67 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_11 = out_woready_67 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign SBDATARdEn_0 = _out_rofireMux_T_1 & out_backSel_60 & ~(auto_dmi_in_a_bits_address[8]) & (|out_backMask); // @[RegisterRouter.scala:87:24] assign SBDATAWrEn_0 = _out_wofireMux_T_2 & out_backSel_60 & ~(auto_dmi_in_a_bits_address[8]) & (&out_backMask); // @[RegisterRouter.scala:87:24] assign SBDATAWrData_0 = SBDATAWrEn_0 ? auto_dmi_in_a_bits_data : 32'h0; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_24 = out_roready_72 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_24 = out_woready_72 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_25 = out_roready_72 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_25 = out_woready_72 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_26 = out_roready_72 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_26 = out_woready_72 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_27 = out_roready_72 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_27 = out_woready_72 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_4 = out_roready_76 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_4 = out_woready_76 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_5 = out_roready_76 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_5 = out_woready_76 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_6 = out_roready_76 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_6 = out_woready_76 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_7 = out_roready_76 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_7 = out_woready_76 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_52 = out_roready_80 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_52 = out_woready_80 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_53 = out_roready_80 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_53 = out_woready_80 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_54 = out_roready_80 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_54 = out_woready_80 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_55 = out_roready_80 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_55 = out_woready_80 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_0 = out_roready_104 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_0 = out_woready_104 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_1 = out_roready_104 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_1 = out_woready_104 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_2 = out_roready_104 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_2 = out_woready_104 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_3 = out_roready_104 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_3 = out_woready_104 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_8 = out_roready_108 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_8 = out_woready_108 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_9 = out_roready_108 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_9 = out_woready_108 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_10 = out_roready_108 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_10 = out_woready_108 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_11 = out_roready_108 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_11 = out_woready_108 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire ABSTRACTCSWrEnMaybe = _out_wofireMux_T_2 & out_backSel_22 & ~(auto_dmi_in_a_bits_address[8]) & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_48 = out_roready_119 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_48 = out_woready_119 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_49 = out_roready_119 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_49 = out_woready_119 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_50 = out_roready_119 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_50 = out_woready_119 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_51 = out_roready_119 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_51 = out_woready_119 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_12 = out_roready_123 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_12 = out_woready_123 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_13 = out_roready_123 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_13 = out_woready_123 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_14 = out_roready_123 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_14 = out_woready_123 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_15 = out_roready_123 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_15 = out_woready_123 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_28 = out_roready_127 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_28 = out_woready_127 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_29 = out_roready_127 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_29 = out_woready_127 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_30 = out_roready_127 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_30 = out_woready_127 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_31 = out_roready_127 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_31 = out_woready_127 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_28 = out_roready_131 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_28 = out_woready_131 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_29 = out_roready_131 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_29 = out_woready_131 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_30 = out_roready_131 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_30 = out_woready_131 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_31 = out_roready_131 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_31 = out_woready_131 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_44 = out_roready_135 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_44 = out_woready_135 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_45 = out_roready_135 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_45 = out_woready_135 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_46 = out_roready_135 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_46 = out_woready_135 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_47 = out_roready_135 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_47 = out_woready_135 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_32 = out_roready_139 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_32 = out_woready_139 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_33 = out_roready_139 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_33 = out_woready_139 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_34 = out_roready_139 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_34 = out_woready_139 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_35 = out_roready_139 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_35 = out_woready_139 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign COMMANDWrEnMaybe = _out_wofireMux_T_2 & out_backSel_23 & ~(auto_dmi_in_a_bits_address[8]) & (&out_backMask); // @[RegisterRouter.scala:87:24] assign COMMANDWrDataVal = COMMANDWrEnMaybe ? auto_dmi_in_a_bits_data : 32'h0; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_16 = out_roready_144 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_16 = out_woready_144 & auto_dmi_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_17 = out_roready_144 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_17 = out_woready_144 & auto_dmi_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_18 = out_roready_144 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_18 = out_woready_144 & auto_dmi_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_19 = out_roready_144 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_19 = out_woready_144 & auto_dmi_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire out_backSel_4 = auto_dmi_in_a_bits_address[7:2] == 6'h4; // @[RegisterRouter.scala:87:24] wire out_backSel_5 = auto_dmi_in_a_bits_address[7:2] == 6'h5; // @[RegisterRouter.scala:87:24] wire out_backSel_6 = auto_dmi_in_a_bits_address[7:2] == 6'h6; // @[RegisterRouter.scala:87:24] wire out_backSel_7 = auto_dmi_in_a_bits_address[7:2] == 6'h7; // @[RegisterRouter.scala:87:24] wire out_backSel_8 = auto_dmi_in_a_bits_address[7:2] == 6'h8; // @[RegisterRouter.scala:87:24] wire out_backSel_9 = auto_dmi_in_a_bits_address[7:2] == 6'h9; // @[RegisterRouter.scala:87:24] wire out_backSel_10 = auto_dmi_in_a_bits_address[7:2] == 6'hA; // @[RegisterRouter.scala:87:24] wire out_backSel_11 = auto_dmi_in_a_bits_address[7:2] == 6'hB; // @[RegisterRouter.scala:87:24] assign out_backSel_22 = auto_dmi_in_a_bits_address[7:2] == 6'h16; // @[RegisterRouter.scala:87:24] assign out_backSel_23 = auto_dmi_in_a_bits_address[7:2] == 6'h17; // @[RegisterRouter.scala:87:24] wire out_backSel_32 = auto_dmi_in_a_bits_address[7:2] == 6'h20; // @[RegisterRouter.scala:87:24] wire out_backSel_33 = auto_dmi_in_a_bits_address[7:2] == 6'h21; // @[RegisterRouter.scala:87:24] wire out_backSel_34 = auto_dmi_in_a_bits_address[7:2] == 6'h22; // @[RegisterRouter.scala:87:24] wire out_backSel_35 = auto_dmi_in_a_bits_address[7:2] == 6'h23; // @[RegisterRouter.scala:87:24] wire out_backSel_36 = auto_dmi_in_a_bits_address[7:2] == 6'h24; // @[RegisterRouter.scala:87:24] wire out_backSel_37 = auto_dmi_in_a_bits_address[7:2] == 6'h25; // @[RegisterRouter.scala:87:24] wire out_backSel_38 = auto_dmi_in_a_bits_address[7:2] == 6'h26; // @[RegisterRouter.scala:87:24] wire out_backSel_39 = auto_dmi_in_a_bits_address[7:2] == 6'h27; // @[RegisterRouter.scala:87:24] wire out_backSel_40 = auto_dmi_in_a_bits_address[7:2] == 6'h28; // @[RegisterRouter.scala:87:24] wire out_backSel_41 = auto_dmi_in_a_bits_address[7:2] == 6'h29; // @[RegisterRouter.scala:87:24] wire out_backSel_42 = auto_dmi_in_a_bits_address[7:2] == 6'h2A; // @[RegisterRouter.scala:87:24] wire out_backSel_43 = auto_dmi_in_a_bits_address[7:2] == 6'h2B; // @[RegisterRouter.scala:87:24] wire out_backSel_44 = auto_dmi_in_a_bits_address[7:2] == 6'h2C; // @[RegisterRouter.scala:87:24] wire out_backSel_45 = auto_dmi_in_a_bits_address[7:2] == 6'h2D; // @[RegisterRouter.scala:87:24] wire out_backSel_46 = auto_dmi_in_a_bits_address[7:2] == 6'h2E; // @[RegisterRouter.scala:87:24] wire out_backSel_47 = auto_dmi_in_a_bits_address[7:2] == 6'h2F; // @[RegisterRouter.scala:87:24] assign out_backSel_57 = auto_dmi_in_a_bits_address[7:2] == 6'h39; // @[RegisterRouter.scala:87:24] assign out_backSel_60 = auto_dmi_in_a_bits_address[7:2] == 6'h3C; // @[RegisterRouter.scala:87:24] assign out_backSel_61 = auto_dmi_in_a_bits_address[7:2] == 6'h3D; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T = auto_dmi_in_a_valid & auto_dmi_in_d_ready; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1 = _out_wofireMux_T & in_bits_read; // @[RegisterRouter.scala:74:36, :87:24] assign out_roready_24 = _out_rofireMux_T_1 & out_backSel_4 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_1 & out_backSel_5 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_67 = _out_rofireMux_T_1 & out_backSel_6 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_123 = _out_rofireMux_T_1 & out_backSel_7 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_20 = _out_rofireMux_T_1 & out_backSel_8 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_1 & out_backSel_9 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_32 = _out_rofireMux_T_1 & out_backSel_10 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_131 = _out_rofireMux_T_1 & out_backSel_11 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_104 = _out_rofireMux_T_1 & out_backSel_32 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_76 = _out_rofireMux_T_1 & out_backSel_33 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_108 = _out_rofireMux_T_1 & out_backSel_34 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_1 & out_backSel_35 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_144 = _out_rofireMux_T_1 & out_backSel_36 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_58 = _out_rofireMux_T_1 & out_backSel_37 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_72 = _out_rofireMux_T_1 & out_backSel_38 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_127 = _out_rofireMux_T_1 & out_backSel_39 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_139 = _out_rofireMux_T_1 & out_backSel_40 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_1 & out_backSel_41 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_51 = _out_rofireMux_T_1 & out_backSel_42 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_135 = _out_rofireMux_T_1 & out_backSel_43 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_119 = _out_rofireMux_T_1 & out_backSel_44 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_80 = _out_rofireMux_T_1 & out_backSel_45 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_62 = _out_rofireMux_T_1 & out_backSel_46 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_roready_28 = _out_rofireMux_T_1 & out_backSel_47 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_2 = _out_wofireMux_T & ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24] assign out_woready_24 = _out_wofireMux_T_2 & out_backSel_4 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_2 & out_backSel_5 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_67 = _out_wofireMux_T_2 & out_backSel_6 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_123 = _out_wofireMux_T_2 & out_backSel_7 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_20 = _out_wofireMux_T_2 & out_backSel_8 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_2 & out_backSel_9 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_32 = _out_wofireMux_T_2 & out_backSel_10 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_131 = _out_wofireMux_T_2 & out_backSel_11 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_54 = _out_wofireMux_T_2 & auto_dmi_in_a_bits_address[7:2] == 6'h18 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_104 = _out_wofireMux_T_2 & out_backSel_32 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_76 = _out_wofireMux_T_2 & out_backSel_33 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_108 = _out_wofireMux_T_2 & out_backSel_34 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_2 & out_backSel_35 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_144 = _out_wofireMux_T_2 & out_backSel_36 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_58 = _out_wofireMux_T_2 & out_backSel_37 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_72 = _out_wofireMux_T_2 & out_backSel_38 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_127 = _out_wofireMux_T_2 & out_backSel_39 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_139 = _out_wofireMux_T_2 & out_backSel_40 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_2 & out_backSel_41 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_51 = _out_wofireMux_T_2 & out_backSel_42 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_135 = _out_wofireMux_T_2 & out_backSel_43 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_119 = _out_wofireMux_T_2 & out_backSel_44 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_80 = _out_wofireMux_T_2 & out_backSel_45 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_62 = _out_wofireMux_T_2 & out_backSel_46 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_28 = _out_wofireMux_T_2 & out_backSel_47 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] assign out_woready_45 = _out_wofireMux_T_2 & auto_dmi_in_a_bits_address[7:2] == 6'h38 & ~(auto_dmi_in_a_bits_address[8]); // @[RegisterRouter.scala:87:24] wire [63:0] _GEN = {{1'h1}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {~(auto_dmi_in_a_bits_address[8])}, {1'h1}, {1'h1}, {1'h1}, {auto_dmi_in_a_bits_address[8]}}; // @[MuxLiteral.scala:49:10] wire [63:0][31:0] _GEN_0 = {{32'h0}, {32'h0}, {{SBDATAFieldsReg_1_3, SBDATAFieldsReg_1_2, SBDATAFieldsReg_1_1, SBDATAFieldsReg_1_0}}, {{SBDATAFieldsReg_0_3, SBDATAFieldsReg_0_2, SBDATAFieldsReg_0_1, SBDATAFieldsReg_0_0}}, {32'h0}, {32'h0}, {SBADDRESSFieldsReg_0}, {{9'h40, SBCSFieldsReg_sbbusyerror, |_sb2tlOpt_io_sbStateOut, SBCSFieldsReg_sbreadonaddr, SBCSFieldsReg_sbaccess, SBCSFieldsReg_sbautoincrement, SBCSFieldsReg_sbreadondata, sbErrorReg_2, sbErrorReg_1, sbErrorReg_0, 12'h40F}}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {{programBufferMem_63, programBufferMem_62, programBufferMem_61, programBufferMem_60}}, {{programBufferMem_59, programBufferMem_58, programBufferMem_57, programBufferMem_56}}, {{programBufferMem_55, programBufferMem_54, programBufferMem_53, programBufferMem_52}}, {{programBufferMem_51, programBufferMem_50, programBufferMem_49, programBufferMem_48}}, {{programBufferMem_47, programBufferMem_46, programBufferMem_45, programBufferMem_44}}, {{programBufferMem_43, programBufferMem_42, programBufferMem_41, programBufferMem_40}}, {{programBufferMem_39, programBufferMem_38, programBufferMem_37, programBufferMem_36}}, {{programBufferMem_35, programBufferMem_34, programBufferMem_33, programBufferMem_32}}, {{programBufferMem_31, programBufferMem_30, programBufferMem_29, programBufferMem_28}}, {{programBufferMem_27, programBufferMem_26, programBufferMem_25, programBufferMem_24}}, {{programBufferMem_23, programBufferMem_22, programBufferMem_21, programBufferMem_20}}, {{programBufferMem_19, programBufferMem_18, programBufferMem_17, programBufferMem_16}}, {{programBufferMem_15, programBufferMem_14, programBufferMem_13, programBufferMem_12}}, {{programBufferMem_11, programBufferMem_10, programBufferMem_9, programBufferMem_8}}, {{programBufferMem_7, programBufferMem_6, programBufferMem_5, programBufferMem_4}}, {{programBufferMem_3, programBufferMem_2, programBufferMem_1, programBufferMem_0}}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {{ABSTRACTAUTOReg_autoexecprogbuf, 8'h0, ABSTRACTAUTOReg_autoexecdata[7:0]}}, {{COMMANDReg_cmdtype, COMMANDReg_control}}, {{19'h8000, abstractCommandBusy, 1'h0, ABSTRACTCSReg_cmderr, 8'h8}}, {32'h0}, {32'h0}, {{31'h0, hartHalted}}, {32'h0}, {{12'h0, {2{haveResetBitRegs}}, {2{resumereq ? ~resumeReqRegs & ~hamaskWrSel_0 : ~resumeReqRegs}}, 4'h0, ~hartHalted, ~hartHalted, {2{hartHalted}}, 8'hA2}}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {{abstractDataMem_31, abstractDataMem_30, abstractDataMem_29, abstractDataMem_28}}, {{abstractDataMem_27, abstractDataMem_26, abstractDataMem_25, abstractDataMem_24}}, {{abstractDataMem_23, abstractDataMem_22, abstractDataMem_21, abstractDataMem_20}}, {{abstractDataMem_19, abstractDataMem_18, abstractDataMem_17, abstractDataMem_16}}, {{abstractDataMem_15, abstractDataMem_14, abstractDataMem_13, abstractDataMem_12}}, {{abstractDataMem_11, abstractDataMem_10, abstractDataMem_9, abstractDataMem_8}}, {{abstractDataMem_7, abstractDataMem_6, abstractDataMem_5, abstractDataMem_4}}, {{abstractDataMem_3, abstractDataMem_2, abstractDataMem_1, abstractDataMem_0}}, {32'h0}, {32'h0}, {32'h0}, {{31'h0, hartHalted}}}; // @[package.scala:79:37] wire [2:0] dmiNodeIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] reg goReg; // @[Debug.scala:1494:27] reg [31:0] abstractGeneratedMem_0; // @[Debug.scala:1586:35] reg [31:0] abstractGeneratedMem_1; // @[Debug.scala:1586:35] wire in_1_bits_read = auto_tl_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire [9:0] _out_womask_T_681 = {{2{auto_tl_in_a_bits_mask[1]}}, {8{auto_tl_in_a_bits_mask[0]}}}; // @[RegisterRouter.scala:87:24] wire hartResumingWrEn = out_woready_1_353 & (&_out_womask_T_681); // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_682 = {{2{auto_tl_in_a_bits_mask[5]}}, {8{auto_tl_in_a_bits_mask[4]}}}; // @[RegisterRouter.scala:87:24] wire hartExceptionWrEn = out_woready_1_353 & (&_out_womask_T_682); // @[RegisterRouter.scala:87:24] wire hartHaltedWrEn = out_woready_1_536 & (&_out_womask_T_681); // @[RegisterRouter.scala:87:24] wire hartGoingWrEn = out_woready_1_536 & (&_out_womask_T_682); // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_262 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read; // @[RegisterRouter.scala:74:36, :87:24] assign out_woready_1_536 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h20 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] assign out_woready_1_353 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h21 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_938 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h68 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_518 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h69 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_199 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h6A & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_1098 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h6B & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_738 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h6C & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_450 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h6D & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_119 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h6E & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_1170 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h6F & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_834 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h70 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_664 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h71 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_986 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h72 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire out_woready_1_39 = _out_wofireMux_T_262 & auto_tl_in_a_bits_address[10:3] == 8'h73 & ~(auto_tl_in_a_bits_address[11]); // @[RegisterRouter.scala:87:24] wire [255:0] _GEN_1 = {{~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {~(auto_tl_in_a_bits_address[11])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {~(auto_tl_in_a_bits_address[11])}, {~(auto_tl_in_a_bits_address[11])}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}, {auto_tl_in_a_bits_address[11]}}; // @[MuxLiteral.scala:49:10] wire [255:0][63:0] _GEN_2 = {{{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, 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resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {{6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg, 6'h0, resumeReqRegs, goReg}}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {{abstractDataMem_31, abstractDataMem_30, abstractDataMem_29, abstractDataMem_28, abstractDataMem_27, abstractDataMem_26, abstractDataMem_25, abstractDataMem_24}}, {{abstractDataMem_23, abstractDataMem_22, abstractDataMem_21, abstractDataMem_20, abstractDataMem_19, abstractDataMem_18, abstractDataMem_17, abstractDataMem_16}}, {{abstractDataMem_15, abstractDataMem_14, abstractDataMem_13, abstractDataMem_12, abstractDataMem_11, abstractDataMem_10, abstractDataMem_9, abstractDataMem_8}}, {{abstractDataMem_7, abstractDataMem_6, abstractDataMem_5, abstractDataMem_4, abstractDataMem_3, abstractDataMem_2, abstractDataMem_1, abstractDataMem_0}}, {{programBufferMem_63, programBufferMem_62, programBufferMem_61, programBufferMem_60, programBufferMem_59, programBufferMem_58, programBufferMem_57, programBufferMem_56}}, {{programBufferMem_55, programBufferMem_54, programBufferMem_53, programBufferMem_52, programBufferMem_51, programBufferMem_50, programBufferMem_49, programBufferMem_48}}, {{programBufferMem_47, programBufferMem_46, programBufferMem_45, programBufferMem_44, programBufferMem_43, programBufferMem_42, programBufferMem_41, programBufferMem_40}}, {{programBufferMem_39, programBufferMem_38, programBufferMem_37, programBufferMem_36, programBufferMem_35, programBufferMem_34, programBufferMem_33, programBufferMem_32}}, {{programBufferMem_31, programBufferMem_30, programBufferMem_29, programBufferMem_28, programBufferMem_27, programBufferMem_26, programBufferMem_25, programBufferMem_24}}, {{programBufferMem_23, programBufferMem_22, programBufferMem_21, programBufferMem_20, programBufferMem_19, programBufferMem_18, programBufferMem_17, programBufferMem_16}}, {{programBufferMem_15, programBufferMem_14, programBufferMem_13, programBufferMem_12, programBufferMem_11, programBufferMem_10, programBufferMem_9, programBufferMem_8}}, {{programBufferMem_7, programBufferMem_6, programBufferMem_5, programBufferMem_4, programBufferMem_3, programBufferMem_2, programBufferMem_1, programBufferMem_0}}, {{abstractGeneratedMem_1, abstractGeneratedMem_0}}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h380006F}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h100073}, {64'h100026237B200073}, {64'h7B20247310802423}, {64'hF140247330000067}, {64'h100022237B202473}, {64'h4086300147413}, {64'hFE0408E300347413}, {64'h4004440310802023}, {64'hF14024737B241073}, {64'hFF0000F0440006F}, {64'h380006F00C0006F}}; // @[MuxLiteral.scala:49:10] wire [2:0] tlNodeIn_d_bits_opcode = {2'h0, in_1_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] assign abstractCommandBusy = |ctrlStateReg; // @[Debug.scala:1732:27, :1740:42] wire commandRegIsAccessRegister = COMMANDReg_cmdtype == 8'h0; // @[Debug.scala:1277:25, :1757:58] wire _GEN_3 = ~(COMMANDReg_control[17]) | (|(COMMANDReg_control[15:12])) & COMMANDReg_control[15:0] < 16'h1020 & (COMMANDReg_control[22:20] == 3'h2 | COMMANDReg_control[22:20] == 3'h3); // @[Debug.scala:1277:25, :1533:71, :1765:{63,72,106}, :1766:{58,70,104,117}, :1776:{19,54}] wire commandRegIsUnsupported = ~commandRegIsAccessRegister | ~_GEN_3; // @[Debug.scala:1757:58, :1761:43, :1773:39, :1774:115, :1775:33, :1776:{54,73}, :1777:33] wire commandRegBadHaltResume = commandRegIsAccessRegister & _GEN_3 & ~hartHalted; // @[Debug.scala:861:31, :1757:58, :1762:43, :1773:39, :1774:115, :1776:{54,73}, :1778:{33,36}] wire _regAccessRegisterCommand_T_1 = ABSTRACTCSReg_cmderr == 3'h0; // @[Debug.scala:1183:34, :1782:103] wire _GEN_4 = COMMANDWrEn & ~(|(COMMANDWrDataVal[31:24])) & _regAccessRegisterCommand_T_1 | autoexec & commandRegIsAccessRegister & _regAccessRegisterCommand_T_1; // @[Debug.scala:297:{24,30}, :1272:{42,48,73}, :1279:39, :1280:65, :1285:40, :1756:60, :1757:58, :1782:{48,78,103}, :1783:{48,78}, :1790:37] wire _GEN_5 = ctrlStateReg == 2'h1; // @[Debug.scala:1732:27, :1797:30] wire _GEN_6 = commandRegIsUnsupported | commandRegBadHaltResume; // @[Debug.scala:1761:43, :1762:43, :1773:39, :1774:115, :1776:73, :1778:33, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33] wire goAbstract = (|ctrlStateReg) & _GEN_5 & ~_GEN_6; // @[Debug.scala:1495:32, :1732:27, :1742:44, :1789:47, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33] wire _GEN_7 = ctrlStateReg == 2'h2; // @[Debug.scala:1732:27, :1818:30]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w1_d3_i0_32( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_68 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_20( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty || floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) || helper(unswizzled, prevT) val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL*/fmv.*.x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) | x, maxType) } // implement NaN unboxing and un-recoding for FS*/fmv.x.* def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out | (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma || cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg || io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid || io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm || io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx || mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 | memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) || divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) | Mux(divSqrt_wen, divSqrt_flags, 0.U) | Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight) io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B || io.keep_clock_enabled || // chicken bit io.valid || // ID stage req_valid || // EX stage mem_reg_valid || mem_cp_valid || // MEM stage wb_reg_valid || wb_cp_valid || // WB stage wen.orR || divSqrt_inFlight || // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }

module FPUFMAPipe_l3_f16_2( // @[FPU.scala:697:7] input clock, // @[FPU.scala:697:7] input reset, // @[FPU.scala:697:7] input io_in_valid, // @[FPU.scala:702:14] input io_in_bits_ldst, // @[FPU.scala:702:14] input io_in_bits_wen, // @[FPU.scala:702:14] input io_in_bits_ren1, // @[FPU.scala:702:14] input io_in_bits_ren2, // @[FPU.scala:702:14] input io_in_bits_ren3, // @[FPU.scala:702:14] input io_in_bits_swap12, // @[FPU.scala:702:14] input io_in_bits_swap23, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14] input io_in_bits_fromint, // @[FPU.scala:702:14] input io_in_bits_toint, // @[FPU.scala:702:14] input io_in_bits_fastpipe, // @[FPU.scala:702:14] input io_in_bits_fma, // @[FPU.scala:702:14] input io_in_bits_div, // @[FPU.scala:702:14] input io_in_bits_sqrt, // @[FPU.scala:702:14] input io_in_bits_wflags, // @[FPU.scala:702:14] input io_in_bits_vec, // @[FPU.scala:702:14] input [2:0] io_in_bits_rm, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14] input [1:0] io_in_bits_typ, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14] input [64:0] io_in_bits_in1, // @[FPU.scala:702:14] input [64:0] io_in_bits_in2, // @[FPU.scala:702:14] input [64:0] io_in_bits_in3, // @[FPU.scala:702:14] output [64:0] io_out_bits_data, // @[FPU.scala:702:14] output [4:0] io_out_bits_exc // @[FPU.scala:702:14] ); wire [64:0] res_data; // @[FPU.scala:728:17] wire [16:0] _fma_io_out; // @[FPU.scala:719:19] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:697:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7] wire [15:0] one = 16'h8000; // @[FPU.scala:710:19] wire [16:0] _zero_T_1 = 17'h10000; // @[FPU.scala:711:57] wire io_out_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7] wire io_out_valid; // @[FPU.scala:697:7] reg valid; // @[FPU.scala:707:22] reg in_ldst; // @[FPU.scala:708:15] reg in_wen; // @[FPU.scala:708:15] reg in_ren1; // @[FPU.scala:708:15] reg in_ren2; // @[FPU.scala:708:15] reg in_ren3; // @[FPU.scala:708:15] reg in_swap12; // @[FPU.scala:708:15] reg in_swap23; // @[FPU.scala:708:15] reg [1:0] in_typeTagIn; // @[FPU.scala:708:15] reg [1:0] in_typeTagOut; // @[FPU.scala:708:15] reg in_fromint; // @[FPU.scala:708:15] reg in_toint; // @[FPU.scala:708:15] reg in_fastpipe; // @[FPU.scala:708:15] reg in_fma; // @[FPU.scala:708:15] reg in_div; // @[FPU.scala:708:15] reg in_sqrt; // @[FPU.scala:708:15] reg in_wflags; // @[FPU.scala:708:15] reg in_vec; // @[FPU.scala:708:15] reg [2:0] in_rm; // @[FPU.scala:708:15] reg [1:0] in_fmaCmd; // @[FPU.scala:708:15] reg [1:0] in_typ; // @[FPU.scala:708:15] reg [1:0] in_fmt; // @[FPU.scala:708:15] reg [64:0] in_in1; // @[FPU.scala:708:15] reg [64:0] in_in2; // @[FPU.scala:708:15] reg [64:0] in_in3; // @[FPU.scala:708:15] wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32] wire [64:0] zero = {48'h0, _zero_T[16], 16'h0}; // @[FPU.scala:711:{32,50}] assign io_out_out_bits_data = res_data; // @[Valid.scala:135:21] wire [4:0] res_exc; // @[FPU.scala:728:17] assign io_out_out_bits_exc = res_exc; // @[Valid.scala:135:21] assign res_data = {48'h0, _fma_io_out}; // @[FPU.scala:711:50, :719:19, :728:17, :729:12] assign io_out_valid = io_out_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:697:7] valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22] if (io_in_valid_0) begin // @[FPU.scala:697:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15] in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15] in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15] in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15] in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15] in_vec <= io_in_bits_vec_0; // @[FPU.scala:697:7, :708:15] in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15] in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15] in_in2 <= io_in_bits_swap23_0 ? 65'h8000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}] in_in3 <= io_in_bits_ren3_0 | io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}] end always @(posedge) MulAddRecFNPipe_l2_e5_s11_2 fma ( // @[FPU.scala:719:19] .clock (clock), .reset (reset), .io_validin (valid), // @[FPU.scala:707:22] .io_op (in_fmaCmd), // @[FPU.scala:708:15] .io_a (in_in1[16:0]), // @[FPU.scala:708:15, :724:12] .io_b (in_in2[16:0]), // @[FPU.scala:708:15, :725:12] .io_c (in_in3[16:0]), // @[FPU.scala:708:15, :726:12] .io_roundingMode (in_rm), // @[FPU.scala:708:15] .io_out (_fma_io_out), .io_exceptionFlags (res_exc), .io_validout (io_out_out_valid) ); // @[FPU.scala:719:19] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_70( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [13:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [13:0] source_1; // @[Monitor.scala:541:22] reg [8207:0] inflight; // @[Monitor.scala:614:27] reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [8207:0] inflight_1; // @[Monitor.scala:726:35] reg [32831:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File FIFOFixer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.util.property class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule { private def fifoMap(seq: Seq[TLSlaveParameters]) = { val (flatManagers, keepManagers) = seq.partition(policy) // We need to be careful if one flatManager and one keepManager share an existing domain // Erring on the side of caution, we will also flatten the keepManager in this case val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0 val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted // Calculate what the FIFO domains look like after the fixer is applied val flatMap = flatDomains.map { x => (x, 0) }.toMap val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap val map = flatMap ++ keepMap val fixMap = seq.map { m => m.fifoId match { case None => if (policy(m)) Some(0) else None case Some(id) => Some(map(id)) // also flattens some who did not ask } } // Compress the FIFO domain space of those we are combining val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap val splatMap = seq.map { m => m.fifoId match { case None => None case Some(id) => reMap.lift(id) } } (fixMap, splatMap) } val node = new AdapterNode(TLImp)( { cp => cp }, { mp => val (fixMap, _) = fifoMap(mp.managers) mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) }) }) with TLFormatNode { override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers) // Do we need to serialize the request to this manager? val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B) // Compact the IDs of the cases we serialize val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap { case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None } val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0 val a_id = if (compacted.isEmpty) 0.U else edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address) val a_noDomain = a_id === 0.U if (false) { println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}") println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}") println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}") println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}") println("") } // Count beats val a_first = edgeIn.first(in.a) val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck // Keep one bit for each source recording if there is an outstanding request that must be made FIFO // Sources unused in the stall signal calculation should be pruned by DCE val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B })) when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO } when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B } val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c => val a_sel = c.sourceId.contains(in.a.bits.source) val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO) val track = flight.slice(c.sourceId.start, c.sourceId.end) a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id) } val stall = stalls.foldLeft(false.B)(_||_) out.a <> in.a in.d <> out.d out.a.valid := in.a.valid && (a_notFIFO || !stall) in.a.ready := out.a.ready && (a_notFIFO || !stall) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> out.b out.c <> in .c out.e <> in .e } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } //Functional cover properties property.cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction") val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W)) val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W)) val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W)) when (a_first && in.a.fire && !a_notFIFO) { SourceIdSet := UIntToOH(in.a.bits.source) } when (d_first && in.d.fire) { SourceIdClear := UIntToOH(in.d.bits.source) } SourceIdFIFOed := SourceIdFIFOed | SourceIdSet val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U) property.cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs") //property.cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs") property.cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty") property.cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed") property.cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped") } } } object TLFIFOFixer { // Which slaves should have their FIFOness combined? // NOTE: this transformation is still only applied for masters with requestFifo type Policy = TLSlaveParameters => Boolean import RegionType._ val all: Policy = m => true val allFIFO: Policy = m => m.fifoId.isDefined val allVolatile: Policy = m => m.regionType <= VOLATILE def apply(policy: Policy = all)(implicit p: Parameters): TLNode = { val fixer = LazyModule(new TLFIFOFixer(policy)) fixer.node } } File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File MemoryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInDevices, HasBuiltInDeviceParams, BuiltInErrorDeviceParams, BuiltInZeroDeviceParams} import freechips.rocketchip.tilelink.{ ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, RegionReplicator, TLXbar, TLInwardNode, TLOutwardNode, ProbePicker, TLEdge, TLFIFOFixer } import freechips.rocketchip.util.Location /** Parameterization of the memory-side bus created for each memory channel */ case class MemoryBusParams( beatBytes: Int, blockBytes: Int, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): MemoryBus = { val mbus = LazyModule(new MemoryBus(this, loc.name)) mbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> mbus) mbus } } /** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */ class MemoryBus(params: MemoryBusParams, name: String = "memory_bus")(implicit p: Parameters) extends TLBusWrapper(params, name)(p) { private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val xbar = LazyModule(new TLXbar(nameSuffix = Some(name))).suggestName(busName + "_xbar") val inwardNode: TLInwardNode = replicator.map(xbar.node :*=* TLFIFOFixer(TLFIFOFixer.all) :*=* _.node) .getOrElse(xbar.node :*=* TLFIFOFixer(TLFIFOFixer.all)) val outwardNode: TLOutwardNode = ProbePicker() :*= xbar.node def busView: TLEdge = xbar.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File ProbePicker.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, IdRange} /* A ProbePicker is used to unify multiple cache banks into one logical cache */ class ProbePicker(implicit p: Parameters) extends LazyModule { val node = TLAdapterNode( clientFn = { p => // The ProbePicker assembles multiple clients based on the assumption they are contiguous in the clients list // This should be true for custers of xbar :=* BankBinder connections def combine(next: TLMasterParameters, pair: (TLMasterParameters, Seq[TLMasterParameters])) = { val (head, output) = pair if (head.visibility.exists(x => next.visibility.exists(_.overlaps(x)))) { (next, head +: output) // pair is not banked, push head without merging } else { def redact(x: TLMasterParameters) = x.v1copy(sourceId = IdRange(0,1), nodePath = Nil, visibility = Seq(AddressSet(0, ~0))) require (redact(next) == redact(head), s"${redact(next)} != ${redact(head)}") val merge = head.v1copy( sourceId = IdRange( head.sourceId.start min next.sourceId.start, head.sourceId.end max next.sourceId.end), visibility = AddressSet.unify(head.visibility ++ next.visibility)) (merge, output) } } val myNil: Seq[TLMasterParameters] = Nil val (head, output) = p.clients.init.foldRight((p.clients.last, myNil))(combine) p.v1copy(clients = head +: output) }, managerFn = { p => p }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out <> in // Based on address, adjust source to route to the correct bank if (edgeIn.client.clients.size != edgeOut.client.clients.size) { in.b.bits.source := Mux1H( edgeOut.client.clients.map(_.sourceId contains out.b.bits.source), edgeOut.client.clients.map { c => val banks = edgeIn.client.clients.filter(c.sourceId contains _.sourceId) if (banks.size == 1) { out.b.bits.source // allow sharing the value between single-bank cases } else { Mux1H( banks.map(_.visibility.map(_ contains out.b.bits.address).reduce(_ || _)), banks.map(_.sourceId.start.U)) } } ) } } } } object ProbePicker { def apply()(implicit p: Parameters): TLNode = { val picker = LazyModule(new ProbePicker) picker.node } } File LazyScope.scala: package org.chipsalliance.diplomacy.lazymodule import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.ValName /** Allows dynamic creation of [[Module]] hierarchy and "shoving" logic into a [[LazyModule]]. */ trait LazyScope { this: LazyModule => override def toString: String = s"LazyScope named $name" /** Evaluate `body` in the current [[LazyModule.scope]] */ def apply[T](body: => T): T = { // Preserve the previous value of the [[LazyModule.scope]], because when calling [[apply]] function, // [[LazyModule.scope]] will be altered. val saved = LazyModule.scope // [[LazyModule.scope]] stack push. LazyModule.scope = Some(this) // Evaluate [[body]] in the current `scope`, saving the result to [[out]]. val out = body // Check that the `scope` after evaluating `body` is the same as when we started. require(LazyModule.scope.isDefined, s"LazyScope $name tried to exit, but scope was empty!") require( LazyModule.scope.get eq this, s"LazyScope $name exited before LazyModule ${LazyModule.scope.get.name} was closed" ) // [[LazyModule.scope]] stack pop. LazyModule.scope = saved out } } /** Used to automatically create a level of module hierarchy (a [[SimpleLazyModule]]) within which [[LazyModule]]s can * be instantiated and connected. * * It will instantiate a [[SimpleLazyModule]] to manage evaluation of `body` and evaluate `body` code snippets in this * scope. */ object LazyScope { /** Create a [[LazyScope]] with an implicit instance name. * * @param body * code executed within the generated [[SimpleLazyModule]]. * @param valName * instance name of generated [[SimpleLazyModule]]. * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. */ def apply[T]( body: => T )( implicit valName: ValName, p: Parameters ): T = { apply(valName.value, "SimpleLazyModule", None)(body)(p) } /** Create a [[LazyScope]] with an explicitly defined instance name. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. */ def apply[T]( name: String )(body: => T )( implicit p: Parameters ): T = { apply(name, "SimpleLazyModule", None)(body)(p) } /** Create a [[LazyScope]] with an explicit instance and class name, and control inlining. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param desiredModuleName * class name of generated [[SimpleLazyModule]]. * @param overrideInlining * tell FIRRTL that this [[SimpleLazyModule]]'s module should be inlined. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. */ def apply[T]( name: String, desiredModuleName: String, overrideInlining: Option[Boolean] = None )(body: => T )( implicit p: Parameters ): T = { val scope = LazyModule(new SimpleLazyModule with LazyScope { override lazy val desiredName = desiredModuleName override def shouldBeInlined = overrideInlining.getOrElse(super.shouldBeInlined) }).suggestName(name) scope { body } } /** Create a [[LazyScope]] to temporarily group children for some reason, but tell Firrtl to inline it. * * For example, we might want to control a set of children's clocks but then not keep the parent wrapper. * * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. */ def inline[T]( body: => T )( implicit p: Parameters ): T = { apply("noname", "ShouldBeInlined", Some(false))(body)(p) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }

module MemoryBus( // @[ClockDomain.scala:14:9] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_mbus_clock_groups_in_member_mbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_mbus_clock_groups_in_member_mbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire coupler_to_mbusscratchpad00_auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_mbusscratchpad00_auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_mbusscratchpad00_auto_tl_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_mbusscratchpad00_auto_tl_out_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [27:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [3:0] xbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire [3:0] xbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire [7:0] xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire mbus_clock_groups_auto_out_member_mbus_0_reset; // @[ClockGroup.scala:53:9] wire mbus_clock_groups_auto_out_member_mbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [3:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _picker_auto_in_1_a_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_1_d_bits_opcode; // @[ProbePicker.scala:69:28] wire [1:0] _picker_auto_in_1_d_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_1_d_bits_size; // @[ProbePicker.scala:69:28] wire [3:0] _picker_auto_in_1_d_bits_source; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_sink; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_denied; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_in_1_d_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_a_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_0_d_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_0_d_bits_size; // @[ProbePicker.scala:69:28] wire [3:0] _picker_auto_in_0_d_bits_source; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_bits_denied; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_in_0_d_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_a_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_size; // @[ProbePicker.scala:69:28] wire [3:0] _picker_auto_out_0_a_bits_source; // @[ProbePicker.scala:69:28] wire [31:0] _picker_auto_out_0_a_bits_address; // @[ProbePicker.scala:69:28] wire [7:0] _picker_auto_out_0_a_bits_mask; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_out_0_a_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_a_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_d_ready; // @[ProbePicker.scala:69:28] wire _mbus_xbar_auto_anon_out_1_a_valid; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_opcode; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_param; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_size; // @[MemoryBus.scala:47:32] wire [3:0] _mbus_xbar_auto_anon_out_1_a_bits_source; // @[MemoryBus.scala:47:32] wire [27:0] _mbus_xbar_auto_anon_out_1_a_bits_address; // @[MemoryBus.scala:47:32] wire [7:0] _mbus_xbar_auto_anon_out_1_a_bits_mask; // @[MemoryBus.scala:47:32] wire [63:0] _mbus_xbar_auto_anon_out_1_a_bits_data; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_1_a_bits_corrupt; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_1_d_ready; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_0_a_valid; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_opcode; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_param; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_size; // @[MemoryBus.scala:47:32] wire [3:0] _mbus_xbar_auto_anon_out_0_a_bits_source; // @[MemoryBus.scala:47:32] wire [31:0] _mbus_xbar_auto_anon_out_0_a_bits_address; // @[MemoryBus.scala:47:32] wire [7:0] _mbus_xbar_auto_anon_out_0_a_bits_mask; // @[MemoryBus.scala:47:32] wire [63:0] _mbus_xbar_auto_anon_out_0_a_bits_data; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_0_a_bits_corrupt; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_0_d_ready; // @[MemoryBus.scala:47:32] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last_0 = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last; // @[ClockDomain.scala:14:9] wire auto_mbus_clock_groups_in_member_mbus_0_clock_0 = auto_mbus_clock_groups_in_member_mbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_mbus_clock_groups_in_member_mbus_0_reset_0 = auto_mbus_clock_groups_in_member_mbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire mbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire mbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire mbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire xbar_auto_anon_in_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire xbar_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire xbar_anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire xbar_in_0_d_bits_sink = 1'h0; // @[Xbar.scala:159:18] wire xbar_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire xbar__out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire xbar_portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire [1:0] xbar_auto_anon_in_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] xbar_auto_anon_out_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] xbar_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] xbar_anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] xbar_in_0_d_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] xbar_out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] xbar_portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire [63:0] xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [31:0] xbar__addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] xbar__addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] xbar__requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] xbar__requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] xbar__requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] xbar__beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] xbar__beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] xbar__beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] xbar__beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] xbar__portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] xbar__portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] xbar_portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] xbar__portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] xbar__portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] xbar_portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [3:0] xbar__addressC_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] xbar__addressC_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] xbar__requestBOI_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74] wire [3:0] xbar__requestBOI_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:264:61] wire [3:0] xbar__requestBOI_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29] wire [3:0] xbar_requestBOI_uncommonBits = 4'h0; // @[Parameters.scala:52:56] wire [3:0] xbar__beatsBO_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74] wire [3:0] xbar__beatsBO_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:264:61] wire [3:0] xbar__beatsCI_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] xbar__beatsCI_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] xbar__portsBIO_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74] wire [3:0] xbar__portsBIO_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:264:61] wire [3:0] xbar_portsBIO_filtered_0_bits_source = 4'h0; // @[Xbar.scala:352:24] wire [3:0] xbar__portsCOI_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] xbar__portsCOI_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] xbar_portsCOI_filtered_0_bits_source = 4'h0; // @[Xbar.scala:352:24] wire [2:0] xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [7:0] xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [9:0] fixer__allIDs_FIFOed_T = 10'h3FF; // @[FIFOFixer.scala:127:48] wire [32:0] fixer__a_notFIFO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_notFIFO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] xbar__requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire mbus_clock_groups_auto_in_member_mbus_0_clock = auto_mbus_clock_groups_in_member_mbus_0_clock_0; // @[ClockGroup.scala:53:9] wire mbus_clock_groups_auto_in_member_mbus_0_reset = auto_mbus_clock_groups_in_member_mbus_0_reset_0; // @[ClockGroup.scala:53:9] wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [27:0] auto_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire mbus_clock_groups_nodeIn_member_mbus_0_clock = mbus_clock_groups_auto_in_member_mbus_0_clock; // @[ClockGroup.scala:53:9] wire mbus_clock_groups_nodeOut_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire mbus_clock_groups_nodeIn_member_mbus_0_reset = mbus_clock_groups_auto_in_member_mbus_0_reset; // @[ClockGroup.scala:53:9] wire mbus_clock_groups_nodeOut_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_mbus_0_clock = mbus_clock_groups_auto_out_member_mbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_mbus_0_reset = mbus_clock_groups_auto_out_member_mbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign mbus_clock_groups_auto_out_member_mbus_0_clock = mbus_clock_groups_nodeOut_member_mbus_0_clock; // @[ClockGroup.scala:53:9] assign mbus_clock_groups_auto_out_member_mbus_0_reset = mbus_clock_groups_nodeOut_member_mbus_0_reset; // @[ClockGroup.scala:53:9] assign mbus_clock_groups_nodeOut_member_mbus_0_clock = mbus_clock_groups_nodeIn_member_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign mbus_clock_groups_nodeOut_member_mbus_0_reset = mbus_clock_groups_nodeIn_member_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_mbus_0_clock = clockGroup_auto_in_member_mbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_mbus_0_reset = clockGroup_auto_in_member_mbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire buffer_auto_out_a_ready = fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [31:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire buffer_auto_out_d_valid = fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] buffer_auto_out_d_bits_opcode = fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] buffer_auto_out_d_bits_param = fixer_auto_anon_in_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] buffer_auto_out_d_bits_size = fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [3:0] buffer_auto_out_d_bits_source = fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire buffer_auto_out_d_bits_sink = fixer_auto_anon_in_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire buffer_auto_out_d_bits_denied = fixer_auto_anon_in_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] buffer_auto_out_d_bits_data = fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire buffer_auto_out_d_bits_corrupt = fixer_auto_anon_in_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_sink = fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [32:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46] wire fixer__a_id_T_4 = fixer__a_id_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_id_T_5 = fixer_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46] wire fixer__a_id_T_9 = fixer__a_id_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_11 = fixer__a_id_T_9; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_10 = {fixer__a_id_T_4, 1'h0}; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_12 = {fixer__a_id_T_10[1], fixer__a_id_T_10[0] | fixer__a_id_T_11}; // @[Mux.scala:30:73] wire [1:0] fixer_a_id = fixer__a_id_T_12; // @[Mux.scala:30:73] wire fixer_a_noDomain = fixer_a_id == 2'h0; // @[Mux.scala:30:73] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__a_first_beats1_decode_T = 13'h3F << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [5:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__d_first_beats1_decode_T = 13'h3F << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [5:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [9:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [9:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [9:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [15:0] fixer__SourceIdSet_T = 16'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [15:0] fixer__SourceIdClear_T = 16'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [9:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire bus_xingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] bus_xingOut_d_bits_param = buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] bus_xingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [3:0] bus_xingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] bus_xingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_valid = buffer_auto_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_param = buffer_auto_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_size = buffer_auto_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [3:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_source = buffer_auto_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_address = buffer_auto_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_data = buffer_auto_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_d_ready = buffer_auto_out_d_ready; // @[FIFOFixer.scala:50:9] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_sink = buffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_denied = buffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] wire xbar_anonIn_a_ready; // @[MixedNode.scala:551:17] wire xbar_anonIn_a_valid = xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_anonIn_a_bits_opcode = xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_anonIn_a_bits_param = xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_anonIn_a_bits_size = xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [3:0] xbar_anonIn_a_bits_source = xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_anonIn_a_bits_address = xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_anonIn_a_bits_mask = xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_anonIn_a_bits_data = xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire xbar_anonIn_a_bits_corrupt = xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_anonIn_d_ready = xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire xbar_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire xbar_anonOut_a_ready = xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire xbar_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire xbar_anonOut_d_ready; // @[MixedNode.scala:542:17] wire xbar_anonOut_d_valid = xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_anonOut_d_bits_opcode = xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_anonOut_d_bits_size = xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] xbar_anonOut_d_bits_source = xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire xbar_anonOut_d_bits_denied = xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] xbar_anonOut_d_bits_data = xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire xbar_anonOut_d_bits_corrupt = xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9] wire xbar_out_0_a_ready = xbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_valid = xbar_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_opcode = xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_param = xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_size = xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [3:0] xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_source = xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_address = xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_mask = xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_data = xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_corrupt = xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_out_0_d_ready; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_d_ready = xbar_anonOut_d_ready; // @[Xbar.scala:74:9] wire xbar_out_0_d_valid = xbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] xbar_out_0_d_bits_opcode = xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] xbar_out_0_d_bits_size = xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [3:0] xbar_out_0_d_bits_source = xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire xbar_out_0_d_bits_denied = xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] xbar_out_0_d_bits_data = xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire xbar_out_0_d_bits_corrupt = xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire xbar_in_0_a_ready; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_a_ready = xbar_anonIn_a_ready; // @[Xbar.scala:74:9] wire xbar_in_0_a_valid = xbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_a_bits_opcode = xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_a_bits_param = xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_a_bits_size = xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [3:0] xbar__in_0_a_bits_source_T = xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] xbar_in_0_a_bits_address = xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] xbar_in_0_a_bits_mask = xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] xbar_in_0_a_bits_data = xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire xbar_in_0_a_bits_corrupt = xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire xbar_in_0_d_ready = xbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire xbar_in_0_d_valid; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_valid = xbar_anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_opcode = xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_size = xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign xbar_auto_anon_in_d_bits_source = xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9] wire xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_denied = xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_data = xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9] wire xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_corrupt = xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign xbar_anonIn_a_ready = xbar_in_0_a_ready; // @[Xbar.scala:159:18] wire xbar__portsAOI_filtered_0_valid_T_1 = xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] xbar_portsAOI_filtered_0_bits_opcode = xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] xbar_portsAOI_filtered_0_bits_param = xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] xbar_portsAOI_filtered_0_bits_size = xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] xbar_portsAOI_filtered_0_bits_source = xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] xbar__requestAIO_T = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] xbar_portsAOI_filtered_0_bits_address = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] xbar_portsAOI_filtered_0_bits_mask = xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] xbar_portsAOI_filtered_0_bits_data = xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire xbar_portsAOI_filtered_0_bits_corrupt = xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire xbar_portsDIO_filtered_0_ready = xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonIn_d_valid = xbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_opcode = xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_size = xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire [3:0] xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign xbar__anonIn_d_bits_source_T = xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_denied = xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_data = xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_corrupt = xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign xbar_in_0_a_bits_source = xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign xbar_anonIn_d_bits_source = xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign xbar_portsAOI_filtered_0_ready = xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonOut_a_valid = xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_opcode = xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_param = xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_size = xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_source = xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_address = xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_mask = xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_data = xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_corrupt = xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign xbar_anonOut_d_ready = xbar_out_0_d_ready; // @[Xbar.scala:216:19] wire xbar__portsDIO_filtered_0_valid_T_1 = xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign xbar_portsDIO_filtered_0_bits_opcode = xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_size = xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] xbar__requestDOI_uncommonBits_T = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign xbar_portsDIO_filtered_0_bits_source = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_denied = xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_data = xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_corrupt = xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire [32:0] xbar__requestAIO_T_1 = {1'h0, xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [3:0] xbar_requestDOI_uncommonBits = xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] xbar__beatsAI_decode_T = 13'h3F << xbar_in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] xbar__beatsAI_decode_T_1 = xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] xbar__beatsAI_decode_T_2 = ~xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] xbar_beatsAI_decode = xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire xbar__beatsAI_opdata_T = xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire xbar_beatsAI_opdata = ~xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] xbar_beatsAI_0 = xbar_beatsAI_opdata ? xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] xbar__beatsDO_decode_T = 13'h3F << xbar_out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] xbar__beatsDO_decode_T_1 = xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] xbar__beatsDO_decode_T_2 = ~xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] xbar_beatsDO_decode = xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire xbar_beatsDO_opdata = xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] xbar_beatsDO_0 = xbar_beatsDO_opdata ? xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign xbar_in_0_a_ready = xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign xbar_out_0_a_valid = xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_opcode = xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_param = xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_size = xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_source = xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_address = xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_mask = xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_data = xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_corrupt = xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign xbar_portsAOI_filtered_0_valid = xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign xbar_out_0_d_ready = xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign xbar_in_0_d_valid = xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_opcode = xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_size = xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_source = xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_denied = xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_data = xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_corrupt = xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign xbar_portsDIO_filtered_0_valid = xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire coupler_to_mbusscratchpad00_tlIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_a_valid = coupler_to_mbusscratchpad00_auto_tl_in_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_mbusscratchpad00_tlIn_a_bits_opcode = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_mbusscratchpad00_tlIn_a_bits_param = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_mbusscratchpad00_tlIn_a_bits_size = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_size; // @[MixedNode.scala:551:17] wire [3:0] coupler_to_mbusscratchpad00_tlIn_a_bits_source = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_source; // @[MixedNode.scala:551:17] wire [27:0] coupler_to_mbusscratchpad00_tlIn_a_bits_address = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] coupler_to_mbusscratchpad00_tlIn_a_bits_mask = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_mbusscratchpad00_tlIn_a_bits_data = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_a_bits_corrupt = coupler_to_mbusscratchpad00_auto_tl_in_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_d_ready = coupler_to_mbusscratchpad00_auto_tl_in_d_ready; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_mbusscratchpad00_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] coupler_to_mbusscratchpad00_tlIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_mbusscratchpad00_tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] coupler_to_mbusscratchpad00_tlIn_d_bits_source; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_mbusscratchpad00_tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_mbusscratchpad00_tlOut_a_ready = coupler_to_mbusscratchpad00_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_mbusscratchpad00_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_mbusscratchpad00_tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_mbusscratchpad00_tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] coupler_to_mbusscratchpad00_tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] coupler_to_mbusscratchpad00_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_to_mbusscratchpad00_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_mbusscratchpad00_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_d_valid = coupler_to_mbusscratchpad00_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_mbusscratchpad00_tlOut_d_bits_opcode = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_to_mbusscratchpad00_tlOut_d_bits_param = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_mbusscratchpad00_tlOut_d_bits_size = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire [3:0] coupler_to_mbusscratchpad00_tlOut_d_bits_source = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_d_bits_sink = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_d_bits_denied = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_mbusscratchpad00_tlOut_d_bits_data = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_tlOut_d_bits_corrupt = coupler_to_mbusscratchpad00_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_to_mbusscratchpad00_auto_tl_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_mbusscratchpad00_auto_tl_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_mbusscratchpad00_auto_tl_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_mbusscratchpad00_auto_tl_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_in_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [27:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_mbusscratchpad00_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_mbusscratchpad00_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7] assign coupler_to_mbusscratchpad00_tlIn_a_ready = coupler_to_mbusscratchpad00_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_valid = coupler_to_mbusscratchpad00_tlOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_opcode = coupler_to_mbusscratchpad00_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_param = coupler_to_mbusscratchpad00_tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_size = coupler_to_mbusscratchpad00_tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_source = coupler_to_mbusscratchpad00_tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_address = coupler_to_mbusscratchpad00_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_mask = coupler_to_mbusscratchpad00_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_data = coupler_to_mbusscratchpad00_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_a_bits_corrupt = coupler_to_mbusscratchpad00_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_auto_tl_out_d_ready = coupler_to_mbusscratchpad00_tlOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_mbusscratchpad00_tlIn_d_valid = coupler_to_mbusscratchpad00_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_opcode = coupler_to_mbusscratchpad00_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_param = coupler_to_mbusscratchpad00_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_size = coupler_to_mbusscratchpad00_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_source = coupler_to_mbusscratchpad00_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_sink = coupler_to_mbusscratchpad00_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_denied = coupler_to_mbusscratchpad00_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_data = coupler_to_mbusscratchpad00_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlIn_d_bits_corrupt = coupler_to_mbusscratchpad00_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_a_ready = coupler_to_mbusscratchpad00_tlIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_tlOut_a_valid = coupler_to_mbusscratchpad00_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_opcode = coupler_to_mbusscratchpad00_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_param = coupler_to_mbusscratchpad00_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_size = coupler_to_mbusscratchpad00_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_source = coupler_to_mbusscratchpad00_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_address = coupler_to_mbusscratchpad00_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_mask = coupler_to_mbusscratchpad00_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_data = coupler_to_mbusscratchpad00_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_a_bits_corrupt = coupler_to_mbusscratchpad00_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_tlOut_d_ready = coupler_to_mbusscratchpad00_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_valid = coupler_to_mbusscratchpad00_tlIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_opcode = coupler_to_mbusscratchpad00_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_param = coupler_to_mbusscratchpad00_tlIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_size = coupler_to_mbusscratchpad00_tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_source = coupler_to_mbusscratchpad00_tlIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_sink = coupler_to_mbusscratchpad00_tlIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_denied = coupler_to_mbusscratchpad00_tlIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_data = coupler_to_mbusscratchpad00_tlIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_mbusscratchpad00_auto_tl_in_d_bits_corrupt = coupler_to_mbusscratchpad00_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_valid = bus_xingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_opcode = bus_xingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_param = bus_xingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_size = bus_xingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_source = bus_xingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_address = bus_xingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_mask = bus_xingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_data = bus_xingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_corrupt = bus_xingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_d_ready = bus_xingOut_d_ready; // @[Buffer.scala:40:9] assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 10'h0; // @[FIFOFixer.scala:115:35] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h0 | fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h1 | fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h2 | fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h3 | fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h4 | fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h5 | fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h6 | fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h7 | fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h8 | fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 4'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 4'h9 | fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] end always @(posedge) FixedClockBroadcast_3_1 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0), .auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_mbus_i1_o2_a32d64s4k1z3u mbus_xbar ( // @[MemoryBus.scala:47:32] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (fixer_auto_anon_out_a_ready), .auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_valid (fixer_auto_anon_out_d_valid), .auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode), .auto_anon_in_d_bits_param (fixer_auto_anon_out_d_bits_param), .auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size), .auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source), .auto_anon_in_d_bits_sink (fixer_auto_anon_out_d_bits_sink), .auto_anon_in_d_bits_denied (fixer_auto_anon_out_d_bits_denied), .auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data), .auto_anon_in_d_bits_corrupt (fixer_auto_anon_out_d_bits_corrupt), .auto_anon_out_1_a_ready (_picker_auto_in_1_a_ready), // @[ProbePicker.scala:69:28] .auto_anon_out_1_a_valid (_mbus_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_mbus_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_mbus_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_mbus_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_mbus_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_mbus_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_mbus_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_mbus_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_mbus_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_mbus_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_picker_auto_in_1_d_valid), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_opcode (_picker_auto_in_1_d_bits_opcode), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_param (_picker_auto_in_1_d_bits_param), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_size (_picker_auto_in_1_d_bits_size), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_source (_picker_auto_in_1_d_bits_source), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_sink (_picker_auto_in_1_d_bits_sink), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_denied (_picker_auto_in_1_d_bits_denied), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_data (_picker_auto_in_1_d_bits_data), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_corrupt (_picker_auto_in_1_d_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_anon_out_0_a_ready (_picker_auto_in_0_a_ready), // @[ProbePicker.scala:69:28] .auto_anon_out_0_a_valid (_mbus_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_mbus_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_mbus_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_mbus_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_mbus_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_mbus_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_mbus_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_mbus_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_mbus_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_mbus_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_picker_auto_in_0_d_valid), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_opcode (_picker_auto_in_0_d_bits_opcode), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_size (_picker_auto_in_0_d_bits_size), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_source (_picker_auto_in_0_d_bits_source), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_denied (_picker_auto_in_0_d_bits_denied), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_data (_picker_auto_in_0_d_bits_data), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_corrupt (_picker_auto_in_0_d_bits_corrupt) // @[ProbePicker.scala:69:28] ); // @[MemoryBus.scala:47:32] ProbePicker picker ( // @[ProbePicker.scala:69:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_1_a_ready (_picker_auto_in_1_a_ready), .auto_in_1_a_valid (_mbus_xbar_auto_anon_out_1_a_valid), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_opcode (_mbus_xbar_auto_anon_out_1_a_bits_opcode), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_param (_mbus_xbar_auto_anon_out_1_a_bits_param), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_size (_mbus_xbar_auto_anon_out_1_a_bits_size), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_source (_mbus_xbar_auto_anon_out_1_a_bits_source), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_address (_mbus_xbar_auto_anon_out_1_a_bits_address), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_mask (_mbus_xbar_auto_anon_out_1_a_bits_mask), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_data (_mbus_xbar_auto_anon_out_1_a_bits_data), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_corrupt (_mbus_xbar_auto_anon_out_1_a_bits_corrupt), // @[MemoryBus.scala:47:32] .auto_in_1_d_ready (_mbus_xbar_auto_anon_out_1_d_ready), // @[MemoryBus.scala:47:32] .auto_in_1_d_valid (_picker_auto_in_1_d_valid), .auto_in_1_d_bits_opcode (_picker_auto_in_1_d_bits_opcode), .auto_in_1_d_bits_param (_picker_auto_in_1_d_bits_param), .auto_in_1_d_bits_size (_picker_auto_in_1_d_bits_size), .auto_in_1_d_bits_source (_picker_auto_in_1_d_bits_source), .auto_in_1_d_bits_sink (_picker_auto_in_1_d_bits_sink), .auto_in_1_d_bits_denied (_picker_auto_in_1_d_bits_denied), .auto_in_1_d_bits_data (_picker_auto_in_1_d_bits_data), .auto_in_1_d_bits_corrupt (_picker_auto_in_1_d_bits_corrupt), .auto_in_0_a_ready (_picker_auto_in_0_a_ready), .auto_in_0_a_valid (_mbus_xbar_auto_anon_out_0_a_valid), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_opcode (_mbus_xbar_auto_anon_out_0_a_bits_opcode), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_param (_mbus_xbar_auto_anon_out_0_a_bits_param), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_size (_mbus_xbar_auto_anon_out_0_a_bits_size), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_source (_mbus_xbar_auto_anon_out_0_a_bits_source), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_address (_mbus_xbar_auto_anon_out_0_a_bits_address), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_mask (_mbus_xbar_auto_anon_out_0_a_bits_mask), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_data (_mbus_xbar_auto_anon_out_0_a_bits_data), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_corrupt (_mbus_xbar_auto_anon_out_0_a_bits_corrupt), // @[MemoryBus.scala:47:32] .auto_in_0_d_ready (_mbus_xbar_auto_anon_out_0_d_ready), // @[MemoryBus.scala:47:32] .auto_in_0_d_valid (_picker_auto_in_0_d_valid), .auto_in_0_d_bits_opcode (_picker_auto_in_0_d_bits_opcode), .auto_in_0_d_bits_size (_picker_auto_in_0_d_bits_size), .auto_in_0_d_bits_source (_picker_auto_in_0_d_bits_source), .auto_in_0_d_bits_denied (_picker_auto_in_0_d_bits_denied), .auto_in_0_d_bits_data (_picker_auto_in_0_d_bits_data), .auto_in_0_d_bits_corrupt (_picker_auto_in_0_d_bits_corrupt), .auto_out_1_a_ready (coupler_to_mbusscratchpad00_auto_tl_in_a_ready), // @[LazyModuleImp.scala:138:7] .auto_out_1_a_valid (coupler_to_mbusscratchpad00_auto_tl_in_a_valid), .auto_out_1_a_bits_opcode (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_opcode), .auto_out_1_a_bits_param (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_param), .auto_out_1_a_bits_size (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_size), .auto_out_1_a_bits_source (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_source), .auto_out_1_a_bits_address (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_address), .auto_out_1_a_bits_mask (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_mask), .auto_out_1_a_bits_data (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_data), .auto_out_1_a_bits_corrupt (coupler_to_mbusscratchpad00_auto_tl_in_a_bits_corrupt), .auto_out_1_d_ready (coupler_to_mbusscratchpad00_auto_tl_in_d_ready), .auto_out_1_d_valid (coupler_to_mbusscratchpad00_auto_tl_in_d_valid), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_opcode (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_param (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_size (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_source (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_sink (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_denied (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_data (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_out_1_d_bits_corrupt (coupler_to_mbusscratchpad00_auto_tl_in_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_out_0_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_out_0_a_valid (_picker_auto_out_0_a_valid), .auto_out_0_a_bits_opcode (_picker_auto_out_0_a_bits_opcode), .auto_out_0_a_bits_param (_picker_auto_out_0_a_bits_param), .auto_out_0_a_bits_size (_picker_auto_out_0_a_bits_size), .auto_out_0_a_bits_source (_picker_auto_out_0_a_bits_source), .auto_out_0_a_bits_address (_picker_auto_out_0_a_bits_address), .auto_out_0_a_bits_mask (_picker_auto_out_0_a_bits_mask), .auto_out_0_a_bits_data (_picker_auto_out_0_a_bits_data), .auto_out_0_a_bits_corrupt (_picker_auto_out_0_a_bits_corrupt), .auto_out_0_d_ready (_picker_auto_out_0_d_ready), .auto_out_0_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[ProbePicker.scala:69:28] TLInterconnectCoupler_mbus_to_memory_controller_port_named_tl_mem coupler_to_memory_controller_port_named_tl_mem ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 coupler_to_memory_controller_port_named_axi4 ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_widget_anon_in_a_ready (xbar_auto_anon_out_a_ready), .auto_widget_anon_in_a_valid (xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_opcode (xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_param (xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_size (xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_source (xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_address (xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_mask (xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_data (xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9] .auto_widget_anon_in_a_bits_corrupt (xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9] .auto_widget_anon_in_d_ready (xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9] .auto_widget_anon_in_d_valid (xbar_auto_anon_out_d_valid), .auto_widget_anon_in_d_bits_opcode (xbar_auto_anon_out_d_bits_opcode), .auto_widget_anon_in_d_bits_size (xbar_auto_anon_out_d_bits_size), .auto_widget_anon_in_d_bits_source (xbar_auto_anon_out_d_bits_source), .auto_widget_anon_in_d_bits_denied (xbar_auto_anon_out_d_bits_denied), .auto_widget_anon_in_d_bits_data (xbar_auto_anon_out_d_bits_data), .auto_widget_anon_in_d_bits_corrupt (xbar_auto_anon_out_d_bits_corrupt), .auto_axi4yank_out_aw_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_aw_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid_0), .auto_axi4yank_out_aw_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id_0), .auto_axi4yank_out_aw_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr_0), .auto_axi4yank_out_aw_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len_0), .auto_axi4yank_out_aw_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size_0), .auto_axi4yank_out_aw_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst_0), .auto_axi4yank_out_aw_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock_0), .auto_axi4yank_out_aw_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache_0), .auto_axi4yank_out_aw_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot_0), .auto_axi4yank_out_aw_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos_0), .auto_axi4yank_out_w_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_w_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid_0), .auto_axi4yank_out_w_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data_0), .auto_axi4yank_out_w_bits_strb (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb_0), .auto_axi4yank_out_w_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last_0), .auto_axi4yank_out_b_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready_0), .auto_axi4yank_out_b_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_b_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_b_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_ar_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_ar_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid_0), .auto_axi4yank_out_ar_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id_0), .auto_axi4yank_out_ar_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr_0), .auto_axi4yank_out_ar_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len_0), .auto_axi4yank_out_ar_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size_0), .auto_axi4yank_out_ar_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst_0), .auto_axi4yank_out_ar_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock_0), .auto_axi4yank_out_ar_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache_0), .auto_axi4yank_out_ar_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot_0), .auto_axi4yank_out_ar_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos_0), .auto_axi4yank_out_r_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready_0), .auto_axi4yank_out_r_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_r_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_r_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_r_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp_0), // @[ClockDomain.scala:14:9] .auto_axi4yank_out_r_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready), .auto_tl_in_a_valid (_picker_auto_out_0_a_valid), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_opcode (_picker_auto_out_0_a_bits_opcode), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_param (_picker_auto_out_0_a_bits_param), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_size (_picker_auto_out_0_a_bits_size), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_source (_picker_auto_out_0_a_bits_source), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_address (_picker_auto_out_0_a_bits_address), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_mask (_picker_auto_out_0_a_bits_mask), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_data (_picker_auto_out_0_a_bits_data), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_corrupt (_picker_auto_out_0_a_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_tl_in_d_ready (_picker_auto_out_0_d_ready), // @[ProbePicker.scala:69:28] .auto_tl_in_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt), .auto_tl_out_a_ready (xbar_auto_anon_in_a_ready), // @[Xbar.scala:74:9] .auto_tl_out_a_valid (xbar_auto_anon_in_a_valid), .auto_tl_out_a_bits_opcode (xbar_auto_anon_in_a_bits_opcode), .auto_tl_out_a_bits_param (xbar_auto_anon_in_a_bits_param), .auto_tl_out_a_bits_size (xbar_auto_anon_in_a_bits_size), .auto_tl_out_a_bits_source (xbar_auto_anon_in_a_bits_source), .auto_tl_out_a_bits_address (xbar_auto_anon_in_a_bits_address), .auto_tl_out_a_bits_mask (xbar_auto_anon_in_a_bits_mask), .auto_tl_out_a_bits_data (xbar_auto_anon_in_a_bits_data), .auto_tl_out_a_bits_corrupt (xbar_auto_anon_in_a_bits_corrupt), .auto_tl_out_d_ready (xbar_auto_anon_in_d_ready), .auto_tl_out_d_valid (xbar_auto_anon_in_d_valid), // @[Xbar.scala:74:9] .auto_tl_out_d_bits_opcode (xbar_auto_anon_in_d_bits_opcode), // @[Xbar.scala:74:9] .auto_tl_out_d_bits_size (xbar_auto_anon_in_d_bits_size), // @[Xbar.scala:74:9] .auto_tl_out_d_bits_source (xbar_auto_anon_in_d_bits_source), // @[Xbar.scala:74:9] .auto_tl_out_d_bits_denied (xbar_auto_anon_in_d_bits_denied), // @[Xbar.scala:74:9] .auto_tl_out_d_bits_data (xbar_auto_anon_in_d_bits_data), // @[Xbar.scala:74:9] .auto_tl_out_d_bits_corrupt (xbar_auto_anon_in_d_bits_corrupt) // @[Xbar.scala:74:9] ); // @[LazyScope.scala:98:27] TLBuffer_a28d64s4k1z3u buffer_1 ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (coupler_to_mbusscratchpad00_auto_tl_out_a_ready), .auto_in_a_valid (coupler_to_mbusscratchpad00_auto_tl_out_a_valid), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_opcode (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_param (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_param), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_size (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_size), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_source (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_source), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_address (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_address), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_mask (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_mask), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_data (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_data), // @[LazyModuleImp.scala:138:7] .auto_in_a_bits_corrupt (coupler_to_mbusscratchpad00_auto_tl_out_a_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_in_d_ready (coupler_to_mbusscratchpad00_auto_tl_out_d_ready), // @[LazyModuleImp.scala:138:7] .auto_in_d_valid (coupler_to_mbusscratchpad00_auto_tl_out_d_valid), .auto_in_d_bits_opcode (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_opcode), .auto_in_d_bits_param (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_param), .auto_in_d_bits_size (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_size), .auto_in_d_bits_source (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_source), .auto_in_d_bits_sink (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_sink), .auto_in_d_bits_denied (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_denied), .auto_in_d_bits_data (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_data), .auto_in_d_bits_corrupt (coupler_to_mbusscratchpad00_auto_tl_out_d_bits_corrupt), .auto_out_a_ready (auto_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_out_a_valid (auto_buffer_out_a_valid_0), .auto_out_a_bits_opcode (auto_buffer_out_a_bits_opcode_0), .auto_out_a_bits_param (auto_buffer_out_a_bits_param_0), .auto_out_a_bits_size (auto_buffer_out_a_bits_size_0), .auto_out_a_bits_source (auto_buffer_out_a_bits_source_0), .auto_out_a_bits_address (auto_buffer_out_a_bits_address_0), .auto_out_a_bits_mask (auto_buffer_out_a_bits_mask_0), .auto_out_a_bits_data (auto_buffer_out_a_bits_data_0), .auto_out_a_bits_corrupt (auto_buffer_out_a_bits_corrupt_0), .auto_out_d_ready (auto_buffer_out_d_ready_0), .auto_out_d_valid (auto_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_opcode (auto_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_param (auto_buffer_out_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_size (auto_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_source (auto_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_sink (auto_buffer_out_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_denied (auto_buffer_out_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_data (auto_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_out_d_bits_corrupt (auto_buffer_out_d_bits_corrupt_0) // @[ClockDomain.scala:14:9] ); // @[Buffer.scala:75:28] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_a_bits_corrupt = auto_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready = auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] endmodule